Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Jerome Glisse. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Jerome Glisse <glisse@freedesktop.org> | |
26 | */ | |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/radeon_drm.h> | |
771fe6b9 JG |
29 | #include "radeon_reg.h" |
30 | #include "radeon.h" | |
31 | ||
1109ca09 | 32 | static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) |
771fe6b9 JG |
33 | { |
34 | struct drm_device *ddev = p->rdev->ddev; | |
35 | struct radeon_cs_chunk *chunk; | |
36 | unsigned i, j; | |
37 | bool duplicate; | |
38 | ||
39 | if (p->chunk_relocs_idx == -1) { | |
40 | return 0; | |
41 | } | |
42 | chunk = &p->chunks[p->chunk_relocs_idx]; | |
cf4ccd01 | 43 | p->dma_reloc_idx = 0; |
771fe6b9 JG |
44 | /* FIXME: we assume that each relocs use 4 dwords */ |
45 | p->nrelocs = chunk->length_dw / 4; | |
46 | p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL); | |
47 | if (p->relocs_ptr == NULL) { | |
48 | return -ENOMEM; | |
49 | } | |
50 | p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL); | |
51 | if (p->relocs == NULL) { | |
52 | return -ENOMEM; | |
53 | } | |
54 | for (i = 0; i < p->nrelocs; i++) { | |
55 | struct drm_radeon_cs_reloc *r; | |
56 | ||
57 | duplicate = false; | |
58 | r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; | |
16557f1e | 59 | for (j = 0; j < i; j++) { |
771fe6b9 JG |
60 | if (r->handle == p->relocs[j].handle) { |
61 | p->relocs_ptr[i] = &p->relocs[j]; | |
62 | duplicate = true; | |
63 | break; | |
64 | } | |
65 | } | |
66 | if (!duplicate) { | |
67 | p->relocs[i].gobj = drm_gem_object_lookup(ddev, | |
68 | p->filp, | |
69 | r->handle); | |
70 | if (p->relocs[i].gobj == NULL) { | |
71 | DRM_ERROR("gem object lookup failed 0x%x\n", | |
72 | r->handle); | |
bf79cb91 | 73 | return -ENOENT; |
771fe6b9 JG |
74 | } |
75 | p->relocs_ptr[i] = &p->relocs[i]; | |
7e4d15d9 | 76 | p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj); |
4c788679 | 77 | p->relocs[i].lobj.bo = p->relocs[i].robj; |
771fe6b9 | 78 | p->relocs[i].lobj.wdomain = r->write_domain; |
147666fb TH |
79 | p->relocs[i].lobj.rdomain = r->read_domains; |
80 | p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo; | |
771fe6b9 JG |
81 | p->relocs[i].handle = r->handle; |
82 | p->relocs[i].flags = r->flags; | |
4c788679 | 83 | radeon_bo_list_add_object(&p->relocs[i].lobj, |
147666fb | 84 | &p->validated); |
93504fce | 85 | |
16557f1e CK |
86 | } else |
87 | p->relocs[i].handle = 0; | |
771fe6b9 | 88 | } |
94429bb6 | 89 | return radeon_bo_list_validate(&p->validated); |
771fe6b9 JG |
90 | } |
91 | ||
721604a1 JG |
92 | static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority) |
93 | { | |
94 | p->priority = priority; | |
95 | ||
96 | switch (ring) { | |
97 | default: | |
98 | DRM_ERROR("unknown ring id: %d\n", ring); | |
99 | return -EINVAL; | |
100 | case RADEON_CS_RING_GFX: | |
101 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
102 | break; | |
103 | case RADEON_CS_RING_COMPUTE: | |
8d5ef7b1 AD |
104 | if (p->rdev->family >= CHIP_TAHITI) { |
105 | if (p->priority > 0) | |
106 | p->ring = CAYMAN_RING_TYPE_CP1_INDEX; | |
107 | else | |
108 | p->ring = CAYMAN_RING_TYPE_CP2_INDEX; | |
109 | } else | |
110 | p->ring = RADEON_RING_TYPE_GFX_INDEX; | |
721604a1 | 111 | break; |
278a334c AD |
112 | case RADEON_CS_RING_DMA: |
113 | if (p->rdev->family >= CHIP_CAYMAN) { | |
114 | if (p->priority > 0) | |
115 | p->ring = R600_RING_TYPE_DMA_INDEX; | |
116 | else | |
117 | p->ring = CAYMAN_RING_TYPE_DMA1_INDEX; | |
118 | } else if (p->rdev->family >= CHIP_R600) { | |
119 | p->ring = R600_RING_TYPE_DMA_INDEX; | |
120 | } else { | |
121 | return -EINVAL; | |
122 | } | |
123 | break; | |
721604a1 JG |
124 | } |
125 | return 0; | |
126 | } | |
127 | ||
f82cbddd CK |
128 | static void radeon_cs_sync_to(struct radeon_cs_parser *p, |
129 | struct radeon_fence *fence) | |
130 | { | |
131 | struct radeon_fence *other; | |
132 | ||
133 | if (!fence) | |
134 | return; | |
135 | ||
136 | other = p->ib.sync_to[fence->ring]; | |
137 | p->ib.sync_to[fence->ring] = radeon_fence_later(fence, other); | |
138 | } | |
139 | ||
220907d9 | 140 | static void radeon_cs_sync_rings(struct radeon_cs_parser *p) |
93504fce | 141 | { |
220907d9 | 142 | int i; |
93504fce | 143 | |
cdac5504 | 144 | for (i = 0; i < p->nrelocs; i++) { |
f82cbddd | 145 | if (!p->relocs[i].robj) |
cdac5504 CK |
146 | continue; |
147 | ||
f82cbddd | 148 | radeon_cs_sync_to(p, p->relocs[i].robj->tbo.sync_obj); |
8f676c4c | 149 | } |
93504fce CK |
150 | } |
151 | ||
9b00147d | 152 | /* XXX: note that this is called from the legacy UMS CS ioctl as well */ |
771fe6b9 JG |
153 | int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) |
154 | { | |
155 | struct drm_radeon_cs *cs = data; | |
156 | uint64_t *chunk_array_ptr; | |
721604a1 JG |
157 | unsigned size, i; |
158 | u32 ring = RADEON_CS_RING_GFX; | |
159 | s32 priority = 0; | |
771fe6b9 JG |
160 | |
161 | if (!cs->num_chunks) { | |
162 | return 0; | |
163 | } | |
164 | /* get chunks */ | |
165 | INIT_LIST_HEAD(&p->validated); | |
166 | p->idx = 0; | |
f2e39221 JG |
167 | p->ib.sa_bo = NULL; |
168 | p->ib.semaphore = NULL; | |
169 | p->const_ib.sa_bo = NULL; | |
170 | p->const_ib.semaphore = NULL; | |
771fe6b9 JG |
171 | p->chunk_ib_idx = -1; |
172 | p->chunk_relocs_idx = -1; | |
721604a1 | 173 | p->chunk_flags_idx = -1; |
dfcf5f36 | 174 | p->chunk_const_ib_idx = -1; |
771fe6b9 JG |
175 | p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); |
176 | if (p->chunks_array == NULL) { | |
177 | return -ENOMEM; | |
178 | } | |
179 | chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks); | |
180 | if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr, | |
181 | sizeof(uint64_t)*cs->num_chunks)) { | |
182 | return -EFAULT; | |
183 | } | |
721604a1 | 184 | p->cs_flags = 0; |
771fe6b9 JG |
185 | p->nchunks = cs->num_chunks; |
186 | p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); | |
187 | if (p->chunks == NULL) { | |
188 | return -ENOMEM; | |
189 | } | |
190 | for (i = 0; i < p->nchunks; i++) { | |
191 | struct drm_radeon_cs_chunk __user **chunk_ptr = NULL; | |
192 | struct drm_radeon_cs_chunk user_chunk; | |
193 | uint32_t __user *cdata; | |
194 | ||
195 | chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i]; | |
196 | if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr, | |
197 | sizeof(struct drm_radeon_cs_chunk))) { | |
198 | return -EFAULT; | |
199 | } | |
5176fdc4 DA |
200 | p->chunks[i].length_dw = user_chunk.length_dw; |
201 | p->chunks[i].kdata = NULL; | |
771fe6b9 | 202 | p->chunks[i].chunk_id = user_chunk.chunk_id; |
580f8398 | 203 | p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data; |
771fe6b9 JG |
204 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { |
205 | p->chunk_relocs_idx = i; | |
206 | } | |
207 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) { | |
208 | p->chunk_ib_idx = i; | |
5176fdc4 DA |
209 | /* zero length IB isn't useful */ |
210 | if (p->chunks[i].length_dw == 0) | |
211 | return -EINVAL; | |
771fe6b9 | 212 | } |
dfcf5f36 AD |
213 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) { |
214 | p->chunk_const_ib_idx = i; | |
215 | /* zero length CONST IB isn't useful */ | |
216 | if (p->chunks[i].length_dw == 0) | |
217 | return -EINVAL; | |
218 | } | |
721604a1 JG |
219 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { |
220 | p->chunk_flags_idx = i; | |
221 | /* zero length flags aren't useful */ | |
222 | if (p->chunks[i].length_dw == 0) | |
223 | return -EINVAL; | |
e70f224c | 224 | } |
5176fdc4 | 225 | |
513bcb46 | 226 | cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; |
721604a1 JG |
227 | if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) || |
228 | (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) { | |
513bcb46 DA |
229 | size = p->chunks[i].length_dw * sizeof(uint32_t); |
230 | p->chunks[i].kdata = kmalloc(size, GFP_KERNEL); | |
231 | if (p->chunks[i].kdata == NULL) { | |
232 | return -ENOMEM; | |
233 | } | |
234 | if (DRM_COPY_FROM_USER(p->chunks[i].kdata, | |
235 | p->chunks[i].user_ptr, size)) { | |
236 | return -EFAULT; | |
237 | } | |
e70f224c | 238 | if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { |
721604a1 JG |
239 | p->cs_flags = p->chunks[i].kdata[0]; |
240 | if (p->chunks[i].length_dw > 1) | |
241 | ring = p->chunks[i].kdata[1]; | |
242 | if (p->chunks[i].length_dw > 2) | |
243 | priority = (s32)p->chunks[i].kdata[2]; | |
e70f224c | 244 | } |
771fe6b9 JG |
245 | } |
246 | } | |
721604a1 | 247 | |
9b00147d AD |
248 | /* these are KMS only */ |
249 | if (p->rdev) { | |
250 | if ((p->cs_flags & RADEON_CS_USE_VM) && | |
251 | !p->rdev->vm_manager.enabled) { | |
252 | DRM_ERROR("VM not active on asic!\n"); | |
253 | return -EINVAL; | |
254 | } | |
1b5475db | 255 | |
9b00147d AD |
256 | /* we only support VM on SI+ */ |
257 | if ((p->rdev->family >= CHIP_TAHITI) && | |
258 | ((p->cs_flags & RADEON_CS_USE_VM) == 0)) { | |
259 | DRM_ERROR("VM required on SI+!\n"); | |
260 | return -EINVAL; | |
261 | } | |
721604a1 | 262 | |
9b00147d AD |
263 | if (radeon_cs_get_ring(p, ring, priority)) |
264 | return -EINVAL; | |
265 | } | |
721604a1 JG |
266 | |
267 | /* deal with non-vm */ | |
268 | if ((p->chunk_ib_idx != -1) && | |
269 | ((p->cs_flags & RADEON_CS_USE_VM) == 0) && | |
270 | (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) { | |
271 | if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) { | |
272 | DRM_ERROR("cs IB too big: %d\n", | |
273 | p->chunks[p->chunk_ib_idx].length_dw); | |
274 | return -EINVAL; | |
275 | } | |
ff4bd082 | 276 | if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) { |
6a7068b4 DA |
277 | p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL); |
278 | p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL); | |
279 | if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL || | |
280 | p->chunks[p->chunk_ib_idx].kpage[1] == NULL) { | |
25d89997 IH |
281 | kfree(p->chunks[p->chunk_ib_idx].kpage[0]); |
282 | kfree(p->chunks[p->chunk_ib_idx].kpage[1]); | |
1da80cfa IH |
283 | p->chunks[p->chunk_ib_idx].kpage[0] = NULL; |
284 | p->chunks[p->chunk_ib_idx].kpage[1] = NULL; | |
6a7068b4 DA |
285 | return -ENOMEM; |
286 | } | |
287 | } | |
721604a1 JG |
288 | p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1; |
289 | p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1; | |
290 | p->chunks[p->chunk_ib_idx].last_copied_page = -1; | |
291 | p->chunks[p->chunk_ib_idx].last_page_index = | |
292 | ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE; | |
293 | } | |
294 | ||
771fe6b9 JG |
295 | return 0; |
296 | } | |
297 | ||
298 | /** | |
299 | * cs_parser_fini() - clean parser states | |
300 | * @parser: parser structure holding parsing context. | |
301 | * @error: error number | |
302 | * | |
303 | * If error is set than unvalidate buffer, otherwise just free memory | |
304 | * used by parsing context. | |
305 | **/ | |
306 | static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) | |
307 | { | |
308 | unsigned i; | |
309 | ||
e43b5ec0 | 310 | if (!error) { |
147666fb | 311 | ttm_eu_fence_buffer_objects(&parser->validated, |
f2e39221 | 312 | parser->ib.fence); |
e43b5ec0 | 313 | } else { |
147666fb | 314 | ttm_eu_backoff_reservation(&parser->validated); |
e43b5ec0 | 315 | } |
147666fb | 316 | |
fcbc451b PN |
317 | if (parser->relocs != NULL) { |
318 | for (i = 0; i < parser->nrelocs; i++) { | |
319 | if (parser->relocs[i].gobj) | |
320 | drm_gem_object_unreference_unlocked(parser->relocs[i].gobj); | |
321 | } | |
771fe6b9 | 322 | } |
48e113e5 | 323 | kfree(parser->track); |
771fe6b9 JG |
324 | kfree(parser->relocs); |
325 | kfree(parser->relocs_ptr); | |
326 | for (i = 0; i < parser->nchunks; i++) { | |
327 | kfree(parser->chunks[i].kdata); | |
6a7068b4 DA |
328 | if ((parser->rdev->flags & RADEON_IS_AGP)) { |
329 | kfree(parser->chunks[i].kpage[0]); | |
330 | kfree(parser->chunks[i].kpage[1]); | |
331 | } | |
771fe6b9 JG |
332 | } |
333 | kfree(parser->chunks); | |
334 | kfree(parser->chunks_array); | |
335 | radeon_ib_free(parser->rdev, &parser->ib); | |
f2e39221 | 336 | radeon_ib_free(parser->rdev, &parser->const_ib); |
771fe6b9 JG |
337 | } |
338 | ||
721604a1 JG |
339 | static int radeon_cs_ib_chunk(struct radeon_device *rdev, |
340 | struct radeon_cs_parser *parser) | |
341 | { | |
342 | struct radeon_cs_chunk *ib_chunk; | |
343 | int r; | |
344 | ||
345 | if (parser->chunk_ib_idx == -1) | |
346 | return 0; | |
347 | ||
348 | if (parser->cs_flags & RADEON_CS_USE_VM) | |
349 | return 0; | |
350 | ||
351 | ib_chunk = &parser->chunks[parser->chunk_ib_idx]; | |
352 | /* Copy the packet into the IB, the parser will read from the | |
353 | * input memory (cached) and write to the IB (which can be | |
354 | * uncached). | |
355 | */ | |
356 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, | |
4bf3dd92 | 357 | NULL, ib_chunk->length_dw * 4); |
721604a1 JG |
358 | if (r) { |
359 | DRM_ERROR("Failed to get ib !\n"); | |
360 | return r; | |
361 | } | |
f2e39221 | 362 | parser->ib.length_dw = ib_chunk->length_dw; |
eb0c19c5 | 363 | r = radeon_cs_parse(rdev, parser->ring, parser); |
721604a1 JG |
364 | if (r || parser->parser_error) { |
365 | DRM_ERROR("Invalid command stream !\n"); | |
366 | return r; | |
367 | } | |
368 | r = radeon_cs_finish_pages(parser); | |
369 | if (r) { | |
370 | DRM_ERROR("Invalid command stream !\n"); | |
371 | return r; | |
372 | } | |
220907d9 | 373 | radeon_cs_sync_rings(parser); |
4ef72566 | 374 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); |
721604a1 JG |
375 | if (r) { |
376 | DRM_ERROR("Failed to schedule IB !\n"); | |
377 | } | |
93bf888c | 378 | return r; |
721604a1 JG |
379 | } |
380 | ||
381 | static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser, | |
382 | struct radeon_vm *vm) | |
383 | { | |
3e8970f9 | 384 | struct radeon_device *rdev = parser->rdev; |
721604a1 JG |
385 | struct radeon_bo_list *lobj; |
386 | struct radeon_bo *bo; | |
387 | int r; | |
388 | ||
3e8970f9 JG |
389 | r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem); |
390 | if (r) { | |
391 | return r; | |
392 | } | |
721604a1 JG |
393 | list_for_each_entry(lobj, &parser->validated, tv.head) { |
394 | bo = lobj->bo; | |
395 | r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem); | |
396 | if (r) { | |
397 | return r; | |
398 | } | |
399 | } | |
400 | return 0; | |
401 | } | |
402 | ||
403 | static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev, | |
404 | struct radeon_cs_parser *parser) | |
405 | { | |
406 | struct radeon_cs_chunk *ib_chunk; | |
407 | struct radeon_fpriv *fpriv = parser->filp->driver_priv; | |
408 | struct radeon_vm *vm = &fpriv->vm; | |
409 | int r; | |
410 | ||
411 | if (parser->chunk_ib_idx == -1) | |
412 | return 0; | |
721604a1 JG |
413 | if ((parser->cs_flags & RADEON_CS_USE_VM) == 0) |
414 | return 0; | |
415 | ||
dfcf5f36 AD |
416 | if ((rdev->family >= CHIP_TAHITI) && |
417 | (parser->chunk_const_ib_idx != -1)) { | |
418 | ib_chunk = &parser->chunks[parser->chunk_const_ib_idx]; | |
419 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { | |
420 | DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw); | |
421 | return -EINVAL; | |
422 | } | |
423 | r = radeon_ib_get(rdev, parser->ring, &parser->const_ib, | |
4bf3dd92 | 424 | vm, ib_chunk->length_dw * 4); |
dfcf5f36 AD |
425 | if (r) { |
426 | DRM_ERROR("Failed to get const ib !\n"); | |
427 | return r; | |
428 | } | |
f2e39221 JG |
429 | parser->const_ib.is_const_ib = true; |
430 | parser->const_ib.length_dw = ib_chunk->length_dw; | |
dfcf5f36 | 431 | /* Copy the packet into the IB */ |
f2e39221 | 432 | if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr, |
dfcf5f36 AD |
433 | ib_chunk->length_dw * 4)) { |
434 | return -EFAULT; | |
435 | } | |
f2e39221 | 436 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib); |
dfcf5f36 AD |
437 | if (r) { |
438 | return r; | |
439 | } | |
440 | } | |
441 | ||
721604a1 JG |
442 | ib_chunk = &parser->chunks[parser->chunk_ib_idx]; |
443 | if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) { | |
444 | DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw); | |
445 | return -EINVAL; | |
446 | } | |
447 | r = radeon_ib_get(rdev, parser->ring, &parser->ib, | |
4bf3dd92 | 448 | vm, ib_chunk->length_dw * 4); |
721604a1 JG |
449 | if (r) { |
450 | DRM_ERROR("Failed to get ib !\n"); | |
451 | return r; | |
452 | } | |
f2e39221 | 453 | parser->ib.length_dw = ib_chunk->length_dw; |
721604a1 | 454 | /* Copy the packet into the IB */ |
f2e39221 | 455 | if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr, |
721604a1 JG |
456 | ib_chunk->length_dw * 4)) { |
457 | return -EFAULT; | |
458 | } | |
f2e39221 | 459 | r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib); |
721604a1 JG |
460 | if (r) { |
461 | return r; | |
462 | } | |
463 | ||
36ff39c4 | 464 | mutex_lock(&rdev->vm_manager.lock); |
721604a1 | 465 | mutex_lock(&vm->mutex); |
ddf03f5c | 466 | r = radeon_vm_alloc_pt(rdev, vm); |
721604a1 JG |
467 | if (r) { |
468 | goto out; | |
469 | } | |
470 | r = radeon_bo_vm_update_pte(parser, vm); | |
471 | if (r) { | |
472 | goto out; | |
473 | } | |
220907d9 | 474 | radeon_cs_sync_rings(parser); |
1678dbc2 | 475 | radeon_cs_sync_to(parser, vm->fence); |
ee60e29f | 476 | radeon_cs_sync_to(parser, radeon_vm_grab_id(rdev, vm, parser->ring)); |
4ef72566 | 477 | |
dfcf5f36 AD |
478 | if ((rdev->family >= CHIP_TAHITI) && |
479 | (parser->chunk_const_ib_idx != -1)) { | |
4ef72566 CK |
480 | r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib); |
481 | } else { | |
482 | r = radeon_ib_schedule(rdev, &parser->ib, NULL); | |
dfcf5f36 AD |
483 | } |
484 | ||
721604a1 | 485 | if (!r) { |
ee60e29f | 486 | radeon_vm_fence(rdev, vm, parser->ib.fence); |
721604a1 | 487 | } |
ee60e29f CK |
488 | |
489 | out: | |
13e55c38 | 490 | radeon_vm_add_to_lru(rdev, vm); |
36ff39c4 CK |
491 | mutex_unlock(&vm->mutex); |
492 | mutex_unlock(&rdev->vm_manager.lock); | |
721604a1 JG |
493 | return r; |
494 | } | |
495 | ||
6c6f4783 CK |
496 | static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r) |
497 | { | |
498 | if (r == -EDEADLK) { | |
499 | r = radeon_gpu_reset(rdev); | |
500 | if (!r) | |
501 | r = -EAGAIN; | |
502 | } | |
503 | return r; | |
504 | } | |
505 | ||
771fe6b9 JG |
506 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
507 | { | |
508 | struct radeon_device *rdev = dev->dev_private; | |
509 | struct radeon_cs_parser parser; | |
771fe6b9 JG |
510 | int r; |
511 | ||
dee53e7f | 512 | down_read(&rdev->exclusive_lock); |
6b7746e8 | 513 | if (!rdev->accel_working) { |
dee53e7f | 514 | up_read(&rdev->exclusive_lock); |
6b7746e8 JG |
515 | return -EBUSY; |
516 | } | |
771fe6b9 JG |
517 | /* initialize parser */ |
518 | memset(&parser, 0, sizeof(struct radeon_cs_parser)); | |
519 | parser.filp = filp; | |
520 | parser.rdev = rdev; | |
c8c15ff1 | 521 | parser.dev = rdev->dev; |
428c6e36 | 522 | parser.family = rdev->family; |
771fe6b9 JG |
523 | r = radeon_cs_parser_init(&parser, data); |
524 | if (r) { | |
525 | DRM_ERROR("Failed to initialize parser !\n"); | |
526 | radeon_cs_parser_fini(&parser, r); | |
dee53e7f | 527 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 528 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
529 | return r; |
530 | } | |
771fe6b9 JG |
531 | r = radeon_cs_parser_relocs(&parser); |
532 | if (r) { | |
97f23b3d DA |
533 | if (r != -ERESTARTSYS) |
534 | DRM_ERROR("Failed to parse relocation %d!\n", r); | |
771fe6b9 | 535 | radeon_cs_parser_fini(&parser, r); |
dee53e7f | 536 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 537 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
538 | return r; |
539 | } | |
721604a1 | 540 | r = radeon_cs_ib_chunk(rdev, &parser); |
771fe6b9 | 541 | if (r) { |
721604a1 | 542 | goto out; |
771fe6b9 | 543 | } |
721604a1 | 544 | r = radeon_cs_ib_vm_chunk(rdev, &parser); |
771fe6b9 | 545 | if (r) { |
721604a1 | 546 | goto out; |
771fe6b9 | 547 | } |
721604a1 | 548 | out: |
771fe6b9 | 549 | radeon_cs_parser_fini(&parser, r); |
dee53e7f | 550 | up_read(&rdev->exclusive_lock); |
6c6f4783 | 551 | r = radeon_cs_handle_lockup(rdev, r); |
771fe6b9 JG |
552 | return r; |
553 | } | |
513bcb46 DA |
554 | |
555 | int radeon_cs_finish_pages(struct radeon_cs_parser *p) | |
556 | { | |
557 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
558 | int i; | |
559 | int size = PAGE_SIZE; | |
560 | ||
561 | for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) { | |
562 | if (i == ibc->last_page_index) { | |
563 | size = (ibc->length_dw * 4) % PAGE_SIZE; | |
564 | if (size == 0) | |
565 | size = PAGE_SIZE; | |
566 | } | |
567 | ||
f2e39221 | 568 | if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), |
513bcb46 DA |
569 | ibc->user_ptr + (i * PAGE_SIZE), |
570 | size)) | |
571 | return -EFAULT; | |
572 | } | |
573 | return 0; | |
574 | } | |
575 | ||
c4c7f314 | 576 | static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx) |
513bcb46 DA |
577 | { |
578 | int new_page; | |
513bcb46 DA |
579 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
580 | int i; | |
581 | int size = PAGE_SIZE; | |
ff4bd082 IH |
582 | bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ? |
583 | false : true; | |
513bcb46 | 584 | |
c5e617e2 | 585 | for (i = ibc->last_copied_page + 1; i < pg_idx; i++) { |
f2e39221 | 586 | if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)), |
513bcb46 DA |
587 | ibc->user_ptr + (i * PAGE_SIZE), |
588 | PAGE_SIZE)) { | |
589 | p->parser_error = -EFAULT; | |
590 | return 0; | |
591 | } | |
592 | } | |
593 | ||
513bcb46 DA |
594 | if (pg_idx == ibc->last_page_index) { |
595 | size = (ibc->length_dw * 4) % PAGE_SIZE; | |
6a7068b4 DA |
596 | if (size == 0) |
597 | size = PAGE_SIZE; | |
513bcb46 DA |
598 | } |
599 | ||
6a7068b4 DA |
600 | new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1; |
601 | if (copy1) | |
f2e39221 | 602 | ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4)); |
6a7068b4 | 603 | |
513bcb46 DA |
604 | if (DRM_COPY_FROM_USER(ibc->kpage[new_page], |
605 | ibc->user_ptr + (pg_idx * PAGE_SIZE), | |
606 | size)) { | |
607 | p->parser_error = -EFAULT; | |
608 | return 0; | |
609 | } | |
610 | ||
6a7068b4 DA |
611 | /* copy to IB for non single case */ |
612 | if (!copy1) | |
f2e39221 | 613 | memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size); |
513bcb46 DA |
614 | |
615 | ibc->last_copied_page = pg_idx; | |
616 | ibc->kpage_idx[new_page] = pg_idx; | |
617 | ||
618 | return new_page; | |
619 | } | |
c4c7f314 DA |
620 | |
621 | u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | |
622 | { | |
623 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
624 | u32 pg_idx, pg_offset; | |
625 | u32 idx_value = 0; | |
626 | int new_page; | |
627 | ||
628 | pg_idx = (idx * 4) / PAGE_SIZE; | |
629 | pg_offset = (idx * 4) % PAGE_SIZE; | |
630 | ||
631 | if (ibc->kpage_idx[0] == pg_idx) | |
632 | return ibc->kpage[0][pg_offset/4]; | |
633 | if (ibc->kpage_idx[1] == pg_idx) | |
634 | return ibc->kpage[1][pg_offset/4]; | |
635 | ||
636 | new_page = radeon_cs_update_pages(p, pg_idx); | |
637 | if (new_page < 0) { | |
638 | p->parser_error = new_page; | |
639 | return 0; | |
640 | } | |
641 | ||
642 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
643 | return idx_value; | |
644 | } | |
4db01311 IH |
645 | |
646 | /** | |
647 | * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet | |
648 | * @parser: parser structure holding parsing context. | |
649 | * @pkt: where to store packet information | |
650 | * | |
651 | * Assume that chunk_ib_index is properly set. Will return -EINVAL | |
652 | * if packet is bigger than remaining ib size. or if packets is unknown. | |
653 | **/ | |
654 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, | |
655 | struct radeon_cs_packet *pkt, | |
656 | unsigned idx) | |
657 | { | |
658 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; | |
659 | struct radeon_device *rdev = p->rdev; | |
660 | uint32_t header; | |
661 | ||
662 | if (idx >= ib_chunk->length_dw) { | |
663 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", | |
664 | idx, ib_chunk->length_dw); | |
665 | return -EINVAL; | |
666 | } | |
667 | header = radeon_get_ib_value(p, idx); | |
668 | pkt->idx = idx; | |
669 | pkt->type = RADEON_CP_PACKET_GET_TYPE(header); | |
670 | pkt->count = RADEON_CP_PACKET_GET_COUNT(header); | |
671 | pkt->one_reg_wr = 0; | |
672 | switch (pkt->type) { | |
673 | case RADEON_PACKET_TYPE0: | |
674 | if (rdev->family < CHIP_R600) { | |
675 | pkt->reg = R100_CP_PACKET0_GET_REG(header); | |
676 | pkt->one_reg_wr = | |
677 | RADEON_CP_PACKET0_GET_ONE_REG_WR(header); | |
678 | } else | |
679 | pkt->reg = R600_CP_PACKET0_GET_REG(header); | |
680 | break; | |
681 | case RADEON_PACKET_TYPE3: | |
682 | pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header); | |
683 | break; | |
684 | case RADEON_PACKET_TYPE2: | |
685 | pkt->count = -1; | |
686 | break; | |
687 | default: | |
688 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); | |
689 | return -EINVAL; | |
690 | } | |
691 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { | |
692 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", | |
693 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); | |
694 | return -EINVAL; | |
695 | } | |
696 | return 0; | |
697 | } | |
9ffb7a6d IH |
698 | |
699 | /** | |
700 | * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP | |
701 | * @p: structure holding the parser context. | |
702 | * | |
703 | * Check if the next packet is NOP relocation packet3. | |
704 | **/ | |
705 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p) | |
706 | { | |
707 | struct radeon_cs_packet p3reloc; | |
708 | int r; | |
709 | ||
710 | r = radeon_cs_packet_parse(p, &p3reloc, p->idx); | |
711 | if (r) | |
712 | return false; | |
713 | if (p3reloc.type != RADEON_PACKET_TYPE3) | |
714 | return false; | |
715 | if (p3reloc.opcode != RADEON_PACKET3_NOP) | |
716 | return false; | |
717 | return true; | |
718 | } | |
c3ad63af IH |
719 | |
720 | /** | |
721 | * radeon_cs_dump_packet() - dump raw packet context | |
722 | * @p: structure holding the parser context. | |
723 | * @pkt: structure holding the packet. | |
724 | * | |
725 | * Used mostly for debugging and error reporting. | |
726 | **/ | |
727 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, | |
728 | struct radeon_cs_packet *pkt) | |
729 | { | |
730 | volatile uint32_t *ib; | |
731 | unsigned i; | |
732 | unsigned idx; | |
733 | ||
734 | ib = p->ib.ptr; | |
735 | idx = pkt->idx; | |
736 | for (i = 0; i <= (pkt->count + 1); i++, idx++) | |
737 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); | |
738 | } | |
739 |