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Merge tag 'pci-v6.16-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_connectors.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
f9183127 26
da68386d 27#include <drm/display/drm_dp_mst_helper.h>
760285e7
DH		 28#include <drm/drm_edid.h>
29#include <drm/drm_crtc_helper.h>
f7d17cd4 30#include <drm/drm_modeset_helper_vtables.h>
fcd70cd3 31#include <drm/drm_probe_helper.h>
760285e7 32#include <drm/radeon_drm.h>
771fe6b9 33#include "radeon.h"
1a626b68 34#include "radeon_audio.h"
923f6848 35#include "atom.h"
771fe6b9 36
10ebc0bc 37#include <linux/pm_runtime.h>
47eb8f73 38#include <linux/vga_switcheroo.h>
10ebc0bc 39
d4877cf2
AD		 40void radeon_connector_hotplug(struct drm_connector *connector)
41{
42 struct drm_device *dev = connector->dev;
43 struct radeon_device *rdev = dev->dev_private;
44 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
45
cbac9543
AD		 46 /* bail if the connector does not have hpd pin, e.g.,
47 * VGA, TV, etc.
48 */
49 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE)
50 return;
51
1e85e1d0 52 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
d4877cf2 53
73104b5c 54 /* if the connector is already off, don't turn it back on */
6e9f798d 55 /* FIXME: This access isn't protected by any locks. */
73104b5c
AD		 56 if (connector->dpms != DRM_MODE_DPMS_ON)
57 return;
58
d5811e87
AD		 59 /* just deal with DP (not eDP) here. */
60 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
266dcba5
JG		 61 struct radeon_connector_atom_dig *dig_connector =
62 radeon_connector->con_priv;
7c3ed0fd 63
266dcba5
JG		 64 /* if existing sink type was not DP no need to retrain */
65 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
66 return;
67
68 /* first get sink type as it may be reset after (un)plug */
69 dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
70 /* don't do anything if sink is not display port, i.e.,
71 * passive dp->(dvi|hdmi) adaptor
72 */
2681bc79
MD		 73 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
74 radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&
75 radeon_dp_needs_link_train(radeon_connector)) {
76 /* Don't start link training before we have the DPCD */
77 if (!radeon_dp_getdpcd(radeon_connector))
78 return;
924f92bf 79
2681bc79
MD		 80 /* Turn the connector off and back on immediately, which
81 * will trigger link training
82 */
83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
84 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
266dcba5 85 }
d4877cf2 86 }
d4877cf2
AD		 87}
88
445282db
DA		 89static void radeon_property_change_mode(struct drm_encoder *encoder)
90{
91 struct drm_crtc *crtc = encoder->crtc;
92
93 if (crtc && crtc->enabled) {
94 drm_crtc_helper_set_mode(crtc, &crtc->mode,
f4510a27 95 crtc->x, crtc->y, crtc->primary->fb);
445282db
DA		 96 }
97}
eccea792
AD		 98
99int radeon_get_monitor_bpc(struct drm_connector *connector)
100{
101 struct drm_device *dev = connector->dev;
102 struct radeon_device *rdev = dev->dev_private;
103 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
104 struct radeon_connector_atom_dig *dig_connector;
105 int bpc = 8;
ea292861 106 int mode_clock, max_tmds_clock;
eccea792
AD		 107
108 switch (connector->connector_type) {
109 case DRM_MODE_CONNECTOR_DVII:
110 case DRM_MODE_CONNECTOR_HDMIB:
111 if (radeon_connector->use_digital) {
242136ed 112 if (connector->display_info.is_hdmi) {
eccea792
AD		 113 if (connector->display_info.bpc)
114 bpc = connector->display_info.bpc;
115 }
116 }
117 break;
118 case DRM_MODE_CONNECTOR_DVID:
119 case DRM_MODE_CONNECTOR_HDMIA:
242136ed 120 if (connector->display_info.is_hdmi) {
eccea792
AD		 121 if (connector->display_info.bpc)
122 bpc = connector->display_info.bpc;
123 }
124 break;
125 case DRM_MODE_CONNECTOR_DisplayPort:
126 dig_connector = radeon_connector->con_priv;
127 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
128 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
242136ed 129 connector->display_info.is_hdmi) {
eccea792
AD		 130 if (connector->display_info.bpc)
131 bpc = connector->display_info.bpc;
132 }
133 break;
134 case DRM_MODE_CONNECTOR_eDP:
135 case DRM_MODE_CONNECTOR_LVDS:
136 if (connector->display_info.bpc)
137 bpc = connector->display_info.bpc;
138 else if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
319d1e14 139 const struct drm_connector_helper_funcs *connector_funcs =
eccea792
AD		 140 connector->helper_private;
141 struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
142 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
143 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
144
145 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
146 bpc = 6;
147 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
148 bpc = 8;
149 }
150 break;
151 }
89b92339 152
242136ed 153 if (connector->display_info.is_hdmi) {
89b92339
MK		 154 /* hdmi deep color only implemented on DCE4+ */
155 if ((bpc > 8) && !ASIC_IS_DCE4(rdev)) {
156 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 8 bpc.\n",
72082093 157 connector->name, bpc);
89b92339
MK		 158 bpc = 8;
159 }
160
161 /*
162 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
163 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
164 * 12 bpc is always supported on hdmi deep color sinks, as this is
165 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
166 */
167 if (bpc > 12) {
168 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
72082093 169 connector->name, bpc);
89b92339
MK		 170 bpc = 12;
171 }
ea292861
MK		 172
173 /* Any defined maximum tmds clock limit we must not exceed? */
2a272ca9 174 if (connector->display_info.max_tmds_clock > 0) {
ea292861
MK		 175 /* mode_clock is clock in kHz for mode to be modeset on this connector */
176 mode_clock = radeon_connector->pixelclock_for_modeset;
177
178 /* Maximum allowable input clock in kHz */
2a272ca9 179 max_tmds_clock = connector->display_info.max_tmds_clock;
ea292861
MK		 180
181 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
182 connector->name, mode_clock, max_tmds_clock);
183
184 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
185 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
4adc33f3 186 if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) &&
ea292861
MK		 187 (mode_clock * 5/4 <= max_tmds_clock))
188 bpc = 10;
189 else
190 bpc = 8;
191
192 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
193 connector->name, bpc);
194 }
195
196 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
197 bpc = 8;
198 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
199 connector->name, bpc);
200 }
dc200356 201 } else if (bpc > 8) {
9f51e2e0
MK		 202 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
203 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
204 connector->name);
205 bpc = 8;
206 }
89b92339
MK		 207 }
208
9f51e2e0
MK		 209 if ((radeon_deep_color == 0) && (bpc > 8)) {
210 DRM_DEBUG("%s: Deep color disabled. Set radeon module param deep_color=1 to enable.\n",
211 connector->name);
a624f429 212 bpc = 8;
9f51e2e0 213 }
a624f429 214
89b92339 215 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
72082093 216 connector->name, connector->display_info.bpc, bpc);
89b92339 217
eccea792
AD		 218 return bpc;
219}
220
771fe6b9
JG		 221static void
222radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status)
223{
224 struct drm_device *dev = connector->dev;
225 struct radeon_device *rdev = dev->dev_private;
7b71ca24
VS		 226 struct drm_encoder *best_encoder;
227 struct drm_encoder *encoder;
319d1e14 228 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
771fe6b9 229 bool connected;
771fe6b9
JG		 230
231 best_encoder = connector_funcs->best_encoder(connector);
232
62afb4ad 233 drm_connector_for_each_possible_encoder(connector, encoder) {
771fe6b9
JG		 234 if ((encoder == best_encoder) && (status == connector_status_connected))
235 connected = true;
236 else
237 connected = false;
238
239 if (rdev->is_atom_bios)
240 radeon_atombios_connected_scratch_regs(connector, encoder, connected);
241 else
242 radeon_combios_connected_scratch_regs(connector, encoder, connected);
771fe6b9
JG		 243 }
244}
245
1109ca09 246static struct drm_encoder *radeon_find_encoder(struct drm_connector *connector, int encoder_type)
445282db 247{
445282db 248 struct drm_encoder *encoder;
445282db 249
62afb4ad 250 drm_connector_for_each_possible_encoder(connector, encoder) {
445282db
DA		 251 if (encoder->encoder_type == encoder_type)
252 return encoder;
253 }
7b71ca24 254
445282db
DA		 255 return NULL;
256}
257
72a5c970
AD		 258static void radeon_connector_get_edid(struct drm_connector *connector)
259{
260 struct drm_device *dev = connector->dev;
261 struct radeon_device *rdev = dev->dev_private;
262 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
263
264 if (radeon_connector->edid)
265 return;
266
267 /* on hw with routers, select right port */
268 if (radeon_connector->router.ddc_valid)
269 radeon_router_select_ddc_port(radeon_connector);
270
271 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
272 ENCODER_OBJECT_ID_NONE) &&
273 radeon_connector->ddc_bus->has_aux) {
274 radeon_connector->edid = drm_get_edid(connector,
275 &radeon_connector->ddc_bus->aux.ddc);
276 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
277 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
278 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
279
280 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
281 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
282 radeon_connector->ddc_bus->has_aux)
283 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
284 &radeon_connector->ddc_bus->aux.ddc);
285 else if (radeon_connector->ddc_bus)
286 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
287 &radeon_connector->ddc_bus->adapter);
47eb8f73
LW		 288 } else if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC &&
289 connector->connector_type == DRM_MODE_CONNECTOR_LVDS &&
290 radeon_connector->ddc_bus) {
291 radeon_connector->edid = drm_get_edid_switcheroo(&radeon_connector->base,
292 &radeon_connector->ddc_bus->adapter);
72a5c970
AD		 293 } else if (radeon_connector->ddc_bus) {
294 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
295 &radeon_connector->ddc_bus->adapter);
296 }
297
298 if (!radeon_connector->edid) {
13485794
AD		 299 /* don't fetch the edid from the vbios if ddc fails and runpm is
300 * enabled so we report disconnected.
301 */
302 if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
303 return;
304
72a5c970
AD		 305 if (rdev->is_atom_bios) {
306 /* some laptops provide a hardcoded edid in rom for LCDs */
307 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
308 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
309 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
310 } else {
311 /* some servers provide a hardcoded edid in rom for KVMs */
312 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
313 }
314 }
315}
316
317static void radeon_connector_free_edid(struct drm_connector *connector)
318{
319 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
320
efd9d065
SS		 321 kfree(radeon_connector->edid);
322 radeon_connector->edid = NULL;
72a5c970
AD		 323}
324
325static int radeon_ddc_get_modes(struct drm_connector *connector)
326{
327 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
328 int ret;
329
330 if (radeon_connector->edid) {
c555f023 331 drm_connector_update_edid_property(connector, radeon_connector->edid);
72a5c970 332 ret = drm_add_edid_modes(connector, radeon_connector->edid);
72a5c970
AD		 333 return ret;
334 }
c555f023 335 drm_connector_update_edid_property(connector, NULL);
72a5c970
AD		 336 return 0;
337}
338
1109ca09 339static struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector)
771fe6b9 340{
7b71ca24 341 struct drm_encoder *encoder;
7b71ca24
VS		 342
343 /* pick the first one */
62afb4ad 344 drm_connector_for_each_possible_encoder(connector, encoder)
7b71ca24
VS		 345 return encoder;
346
771fe6b9
JG		 347 return NULL;
348}
349
da997620
AD		 350static void radeon_get_native_mode(struct drm_connector *connector)
351{
352 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
353 struct radeon_encoder *radeon_encoder;
354
355 if (encoder == NULL)
356 return;
357
358 radeon_encoder = to_radeon_encoder(encoder);
359
360 if (!list_empty(&connector->probed_modes)) {
361 struct drm_display_mode *preferred_mode =
362 list_first_entry(&connector->probed_modes,
363 struct drm_display_mode, head);
364
365 radeon_encoder->native_mode = *preferred_mode;
366 } else {
367 radeon_encoder->native_mode.clock = 0;
368 }
369}
370
4ce001ab
DA		 371/*
372 * radeon_connector_analog_encoder_conflict_solve
373 * - search for other connectors sharing this encoder
374 * if priority is true, then set them disconnected if this is connected
375 * if priority is false, set us disconnected if they are connected
376 */
377static enum drm_connector_status
378radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
379 struct drm_encoder *encoder,
380 enum drm_connector_status current_status,
381 bool priority)
382{
383 struct drm_device *dev = connector->dev;
384 struct drm_connector *conflict;
08d07511 385 struct radeon_connector *radeon_conflict;
4ce001ab
DA		 386
387 list_for_each_entry(conflict, &dev->mode_config.connector_list, head) {
7b71ca24 388 struct drm_encoder *enc;
7b71ca24 389
4ce001ab
DA		 390 if (conflict == connector)
391 continue;
392
08d07511 393 radeon_conflict = to_radeon_connector(conflict);
4ce001ab 394
62afb4ad 395 drm_connector_for_each_possible_encoder(conflict, enc) {
4ce001ab 396 /* if the IDs match */
7b71ca24 397 if (enc == encoder) {
4ce001ab
DA		 398 if (conflict->status != connector_status_connected)
399 continue;
08d07511
AD		 400
401 if (radeon_conflict->use_digital)
402 continue;
4ce001ab 403
fbd62354 404 if (priority) {
72082093
JN		 405 DRM_DEBUG_KMS("1: conflicting encoders switching off %s\n",
406 conflict->name);
407 DRM_DEBUG_KMS("in favor of %s\n",
408 connector->name);
4ce001ab
DA		 409 conflict->status = connector_status_disconnected;
410 radeon_connector_update_scratch_regs(conflict, connector_status_disconnected);
411 } else {
72082093
JN		 412 DRM_DEBUG_KMS("2: conflicting encoders switching off %s\n",
413 connector->name);
414 DRM_DEBUG_KMS("in favor of %s\n",
415 conflict->name);
4ce001ab
DA		 416 current_status = connector_status_disconnected;
417 }
418 break;
419 }
420 }
421 }
422 return current_status;
423
424}
425
771fe6b9
JG		 426static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder)
427{
428 struct drm_device *dev = encoder->dev;
429 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
430 struct drm_display_mode *mode = NULL;
de2103e4 431 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
771fe6b9 432
de2103e4
AD		 433 if (native_mode->hdisplay != 0 &&
434 native_mode->vdisplay != 0 &&
435 native_mode->clock != 0) {
fb06ca8f 436 mode = drm_mode_duplicate(dev, native_mode);
a2b28708
GY		 437 if (!mode)
438 return NULL;
771fe6b9
JG		 439 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
440 drm_mode_set_name(mode);
441
d9fdaafb 442 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
d2efdf6d
AD		 443 } else if (native_mode->hdisplay != 0 &&
444 native_mode->vdisplay != 0) {
445 /* mac laptops without an edid */
446 /* Note that this is not necessarily the exact panel mode,
447 * but an approximation based on the cvt formula. For these
448 * systems we should ideally read the mode info out of the
449 * registers or add a mode table, but this works and is much
450 * simpler.
451 */
452 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
a2b28708
GY		 453 if (!mode)
454 return NULL;
d2efdf6d 455 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
d9fdaafb 456 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
771fe6b9
JG		 457 }
458 return mode;
459}
460
923f6848
AD		 461static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector)
462{
463 struct drm_device *dev = encoder->dev;
464 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
465 struct drm_display_mode *mode = NULL;
de2103e4 466 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
923f6848
AD		 467 int i;
468 struct mode_size {
469 int w;
470 int h;
471 } common_modes[17] = {
472 { 640, 480},
473 { 720, 480},
474 { 800, 600},
475 { 848, 480},
476 {1024, 768},
477 {1152, 768},
478 {1280, 720},
479 {1280, 800},
480 {1280, 854},
481 {1280, 960},
482 {1280, 1024},
483 {1440, 900},
484 {1400, 1050},
485 {1680, 1050},
486 {1600, 1200},
487 {1920, 1080},
488 {1920, 1200}
489 };
490
491 for (i = 0; i < 17; i++) {
dfdd6467
AD		 492 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
493 if (common_modes[i].w > 1024 ||
494 common_modes[i].h > 768)
495 continue;
496 }
923f6848 497 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
de2103e4
AD		 498 if (common_modes[i].w > native_mode->hdisplay ||
499 common_modes[i].h > native_mode->vdisplay ||
500 (common_modes[i].w == native_mode->hdisplay &&
501 common_modes[i].h == native_mode->vdisplay))
923f6848
AD		 502 continue;
503 }
504 if (common_modes[i].w < 320 || common_modes[i].h < 200)
505 continue;
506
d50ba256 507 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
7a38efee
MK		 508 if (!mode)
509 continue;
510
923f6848
AD		 511 drm_mode_probed_add(connector, mode);
512 }
513}
514
1109ca09 515static int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property,
771fe6b9
JG		 516 uint64_t val)
517{
445282db
DA		 518 struct drm_device *dev = connector->dev;
519 struct radeon_device *rdev = dev->dev_private;
520 struct drm_encoder *encoder;
521 struct radeon_encoder *radeon_encoder;
522
523 if (property == rdev->mode_info.coherent_mode_property) {
524 struct radeon_encoder_atom_dig *dig;
ce227c41 525 bool new_coherent_mode;
445282db
DA		 526
527 /* need to find digital encoder on connector */
528 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
529 if (!encoder)
530 return 0;
531
532 radeon_encoder = to_radeon_encoder(encoder);
533
534 if (!radeon_encoder->enc_priv)
535 return 0;
536
537 dig = radeon_encoder->enc_priv;
ce227c41
DA		 538 new_coherent_mode = val ? true : false;
539 if (dig->coherent_mode != new_coherent_mode) {
540 dig->coherent_mode = new_coherent_mode;
541 radeon_property_change_mode(&radeon_encoder->base);
542 }
445282db
DA		 543 }
544
8666c076
AD		 545 if (property == rdev->mode_info.audio_property) {
546 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
547 /* need to find digital encoder on connector */
548 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
549 if (!encoder)
550 return 0;
551
552 radeon_encoder = to_radeon_encoder(encoder);
553
554 if (radeon_connector->audio != val) {
555 radeon_connector->audio = val;
556 radeon_property_change_mode(&radeon_encoder->base);
557 }
558 }
559
6214bb74
AD		 560 if (property == rdev->mode_info.dither_property) {
561 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
562 /* need to find digital encoder on connector */
563 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
564 if (!encoder)
565 return 0;
566
567 radeon_encoder = to_radeon_encoder(encoder);
568
569 if (radeon_connector->dither != val) {
570 radeon_connector->dither = val;
571 radeon_property_change_mode(&radeon_encoder->base);
572 }
573 }
574
5b1714d3
AD		 575 if (property == rdev->mode_info.underscan_property) {
576 /* need to find digital encoder on connector */
577 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
578 if (!encoder)
579 return 0;
580
581 radeon_encoder = to_radeon_encoder(encoder);
582
583 if (radeon_encoder->underscan_type != val) {
584 radeon_encoder->underscan_type = val;
585 radeon_property_change_mode(&radeon_encoder->base);
586 }
587 }
588
5bccf5e3
MG		 589 if (property == rdev->mode_info.underscan_hborder_property) {
590 /* need to find digital encoder on connector */
591 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
592 if (!encoder)
593 return 0;
594
595 radeon_encoder = to_radeon_encoder(encoder);
596
597 if (radeon_encoder->underscan_hborder != val) {
598 radeon_encoder->underscan_hborder = val;
599 radeon_property_change_mode(&radeon_encoder->base);
600 }
601 }
602
603 if (property == rdev->mode_info.underscan_vborder_property) {
604 /* need to find digital encoder on connector */
605 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
606 if (!encoder)
607 return 0;
608
609 radeon_encoder = to_radeon_encoder(encoder);
610
611 if (radeon_encoder->underscan_vborder != val) {
612 radeon_encoder->underscan_vborder = val;
613 radeon_property_change_mode(&radeon_encoder->base);
614 }
615 }
616
445282db
DA		 617 if (property == rdev->mode_info.tv_std_property) {
618 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC);
619 if (!encoder) {
620 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_DAC);
621 }
622
623 if (!encoder)
624 return 0;
625
626 radeon_encoder = to_radeon_encoder(encoder);
627 if (!radeon_encoder->enc_priv)
628 return 0;
643acacf 629 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) {
445282db
DA		 630 struct radeon_encoder_atom_dac *dac_int;
631 dac_int = radeon_encoder->enc_priv;
632 dac_int->tv_std = val;
633 } else {
634 struct radeon_encoder_tv_dac *dac_int;
635 dac_int = radeon_encoder->enc_priv;
636 dac_int->tv_std = val;
637 }
638 radeon_property_change_mode(&radeon_encoder->base);
639 }
640
641 if (property == rdev->mode_info.load_detect_property) {
642 struct radeon_connector *radeon_connector =
643 to_radeon_connector(connector);
644
645 if (val == 0)
646 radeon_connector->dac_load_detect = false;
647 else
648 radeon_connector->dac_load_detect = true;
649 }
650
651 if (property == rdev->mode_info.tmds_pll_property) {
652 struct radeon_encoder_int_tmds *tmds = NULL;
653 bool ret = false;
654 /* need to find digital encoder on connector */
655 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
656 if (!encoder)
657 return 0;
658
659 radeon_encoder = to_radeon_encoder(encoder);
660
661 tmds = radeon_encoder->enc_priv;
662 if (!tmds)
663 return 0;
664
665 if (val == 0) {
666 if (rdev->is_atom_bios)
667 ret = radeon_atombios_get_tmds_info(radeon_encoder, tmds);
668 else
669 ret = radeon_legacy_get_tmds_info_from_combios(radeon_encoder, tmds);
670 }
3c20d544 671 if (val == 1 || !ret)
445282db 672 radeon_legacy_get_tmds_info_from_table(radeon_encoder, tmds);
3c20d544 673
445282db
DA		 674 radeon_property_change_mode(&radeon_encoder->base);
675 }
676
da997620
AD		 677 if (property == dev->mode_config.scaling_mode_property) {
678 enum radeon_rmx_type rmx_type;
679
680 if (connector->encoder)
681 radeon_encoder = to_radeon_encoder(connector->encoder);
682 else {
319d1e14 683 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
da997620
AD		 684 radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
685 }
686
687 switch (val) {
688 default:
689 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
690 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
691 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
692 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
693 }
694 if (radeon_encoder->rmx_type == rmx_type)
695 return 0;
696
697 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
698 (radeon_encoder->native_mode.clock == 0))
699 return 0;
700
701 radeon_encoder->rmx_type = rmx_type;
702
703 radeon_property_change_mode(&radeon_encoder->base);
704 }
705
643b1f56
AD		 706 if (property == rdev->mode_info.output_csc_property) {
707 if (connector->encoder)
708 radeon_encoder = to_radeon_encoder(connector->encoder);
709 else {
16bb079e 710 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
643b1f56
AD		 711 radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
712 }
713
714 if (radeon_encoder->output_csc == val)
715 return 0;
716
717 radeon_encoder->output_csc = val;
718
f3eb9b8f 719 if (connector->encoder && connector->encoder->crtc) {
643b1f56 720 struct drm_crtc *crtc = connector->encoder->crtc;
643b1f56
AD		 721 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
722
723 radeon_crtc->output_csc = radeon_encoder->output_csc;
724
42585395
PR		 725 /*
726 * Our .gamma_set assumes the .gamma_store has been
727 * prefilled and don't care about its arguments.
728 */
729 crtc->funcs->gamma_set(crtc, NULL, NULL, NULL, 0, NULL);
643b1f56
AD		 730 }
731 }
732
771fe6b9
JG		 733 return 0;
734}
735
8dfaa8a7
MD		 736static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
737 struct drm_connector *connector)
738{
739 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
de2103e4 740 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
13bb9430
MG		 741 struct drm_display_mode *t, *mode;
742
743 /* If the EDID preferred mode doesn't match the native mode, use it */
744 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
745 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
746 if (mode->hdisplay != native_mode->hdisplay ||
747 mode->vdisplay != native_mode->vdisplay)
606d5877 748 drm_mode_copy(native_mode, mode);
13bb9430
MG		 749 }
750 }
8dfaa8a7
MD		 751
752 /* Try to get native mode details from EDID if necessary */
de2103e4 753 if (!native_mode->clock) {
8dfaa8a7 754 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
de2103e4
AD		 755 if (mode->hdisplay == native_mode->hdisplay &&
756 mode->vdisplay == native_mode->vdisplay) {
606d5877 757 drm_mode_copy(native_mode, mode);
de2103e4 758 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
c5d46b4e 759 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
8dfaa8a7
MD		 760 break;
761 }
762 }
763 }
13bb9430 764
de2103e4 765 if (!native_mode->clock) {
c5d46b4e 766 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
8dfaa8a7
MD		 767 radeon_encoder->rmx_type = RMX_OFF;
768 }
769}
771fe6b9
JG		 770
771static int radeon_lvds_get_modes(struct drm_connector *connector)
772{
771fe6b9
JG		 773 struct drm_encoder *encoder;
774 int ret = 0;
775 struct drm_display_mode *mode;
776
72a5c970
AD		 777 radeon_connector_get_edid(connector);
778 ret = radeon_ddc_get_modes(connector);
779 if (ret > 0) {
780 encoder = radeon_best_single_encoder(connector);
781 if (encoder) {
782 radeon_fixup_lvds_native_mode(encoder, connector);
783 /* add scaled modes */
784 radeon_add_common_modes(encoder, connector);
771fe6b9 785 }
72a5c970 786 return ret;
771fe6b9
JG		 787 }
788
789 encoder = radeon_best_single_encoder(connector);
790 if (!encoder)
791 return 0;
792
793 /* we have no EDID modes */
794 mode = radeon_fp_native_mode(encoder);
795 if (mode) {
796 ret = 1;
797 drm_mode_probed_add(connector, mode);
7a868e18
AD		 798 /* add the width/height from vbios tables if available */
799 connector->display_info.width_mm = mode->width_mm;
800 connector->display_info.height_mm = mode->height_mm;
7747b713
AD		 801 /* add scaled modes */
802 radeon_add_common_modes(encoder, connector);
771fe6b9 803 }
923f6848 804
771fe6b9
JG		 805 return ret;
806}
807
7a47f20e 808static enum drm_mode_status radeon_lvds_mode_valid(struct drm_connector *connector,
26d6fd81 809 const struct drm_display_mode *mode)
771fe6b9 810{
a3fa6320
AD		 811 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
812
813 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
814 return MODE_PANEL;
815
816 if (encoder) {
817 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
818 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
819
820 /* AVIVO hardware supports downscaling modes larger than the panel
821 * to the panel size, but I'm not sure this is desirable.
822 */
823 if ((mode->hdisplay > native_mode->hdisplay) ||
824 (mode->vdisplay > native_mode->vdisplay))
825 return MODE_PANEL;
826
827 /* if scaling is disabled, block non-native modes */
828 if (radeon_encoder->rmx_type == RMX_OFF) {
829 if ((mode->hdisplay != native_mode->hdisplay) ||
830 (mode->vdisplay != native_mode->vdisplay))
831 return MODE_PANEL;
832 }
833 }
834
771fe6b9
JG		 835 return MODE_OK;
836}
837
7b334fcb 838static enum drm_connector_status
930a9e28 839radeon_lvds_detect(struct drm_connector *connector, bool force)
771fe6b9 840{
13485794
AD		 841 struct drm_device *dev = connector->dev;
842 struct radeon_device *rdev = dev->dev_private;
0549a061 843 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2ffb8429 844 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
0549a061 845 enum drm_connector_status ret = connector_status_disconnected;
10ebc0bc
DA		 846 int r;
847
15734fef
LW		 848 if (!drm_kms_helper_is_poll_worker()) {
849 r = pm_runtime_get_sync(connector->dev->dev);
6f2e8acd
AP		 850 if (r < 0) {
851 pm_runtime_put_autosuspend(connector->dev->dev);
15734fef 852 return connector_status_disconnected;
6f2e8acd 853 }
15734fef 854 }
2ffb8429
AD		 855
856 if (encoder) {
857 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
de2103e4 858 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
2ffb8429
AD		 859
860 /* check if panel is valid */
de2103e4 861 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
2ffb8429 862 ret = connector_status_connected;
13485794
AD		 863 /* don't fetch the edid from the vbios if ddc fails and runpm is
864 * enabled so we report disconnected.
865 */
866 if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
867 ret = connector_status_disconnected;
2ffb8429 868 }
0549a061
AD		 869
870 /* check for edid as well */
72a5c970 871 radeon_connector_get_edid(connector);
0294cf4f
AD		 872 if (radeon_connector->edid)
873 ret = connector_status_connected;
771fe6b9 874 /* check acpi lid status ??? */
2ffb8429 875
771fe6b9 876 radeon_connector_update_scratch_regs(connector, ret);
15734fef
LW		 877
878 if (!drm_kms_helper_is_poll_worker()) {
879 pm_runtime_mark_last_busy(connector->dev->dev);
880 pm_runtime_put_autosuspend(connector->dev->dev);
881 }
882
771fe6b9
JG		 883 return ret;
884}
885
b0c80bd5
AD		 886static void radeon_connector_unregister(struct drm_connector *connector)
887{
888 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
889
0a6e2105 890 if (radeon_connector->ddc_bus && radeon_connector->ddc_bus->has_aux) {
b0c80bd5
AD		 891 drm_dp_aux_unregister(&radeon_connector->ddc_bus->aux);
892 radeon_connector->ddc_bus->has_aux = false;
893 }
894}
895
771fe6b9
JG		 896static void radeon_connector_destroy(struct drm_connector *connector)
897{
898 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
899
72a5c970 900 radeon_connector_free_edid(connector);
771fe6b9 901 kfree(radeon_connector->con_priv);
34ea3d38 902 drm_connector_unregister(connector);
771fe6b9
JG		 903 drm_connector_cleanup(connector);
904 kfree(connector);
905}
906
445282db
DA		 907static int radeon_lvds_set_property(struct drm_connector *connector,
908 struct drm_property *property,
909 uint64_t value)
910{
911 struct drm_device *dev = connector->dev;
912 struct radeon_encoder *radeon_encoder;
913 enum radeon_rmx_type rmx_type;
914
d9fdaafb 915 DRM_DEBUG_KMS("\n");
445282db
DA		 916 if (property != dev->mode_config.scaling_mode_property)
917 return 0;
918
919 if (connector->encoder)
920 radeon_encoder = to_radeon_encoder(connector->encoder);
921 else {
319d1e14 922 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
445282db
DA		 923 radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
924 }
925
926 switch (value) {
927 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
928 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
929 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
930 default:
931 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
932 }
933 if (radeon_encoder->rmx_type == rmx_type)
934 return 0;
935
936 radeon_encoder->rmx_type = rmx_type;
937
938 radeon_property_change_mode(&radeon_encoder->base);
939 return 0;
940}
941
942
1109ca09 943static const struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = {
771fe6b9
JG		 944 .get_modes = radeon_lvds_get_modes,
945 .mode_valid = radeon_lvds_mode_valid,
946 .best_encoder = radeon_best_single_encoder,
947};
948
1109ca09 949static const struct drm_connector_funcs radeon_lvds_connector_funcs = {
771fe6b9
JG		 950 .dpms = drm_helper_connector_dpms,
951 .detect = radeon_lvds_detect,
952 .fill_modes = drm_helper_probe_single_connector_modes,
b0c80bd5 953 .early_unregister = radeon_connector_unregister,
771fe6b9 954 .destroy = radeon_connector_destroy,
445282db 955 .set_property = radeon_lvds_set_property,
771fe6b9
JG		 956};
957
958static int radeon_vga_get_modes(struct drm_connector *connector)
959{
771fe6b9
JG		 960 int ret;
961
72a5c970
AD		 962 radeon_connector_get_edid(connector);
963 ret = radeon_ddc_get_modes(connector);
771fe6b9 964
da997620
AD		 965 radeon_get_native_mode(connector);
966
771fe6b9
JG		 967 return ret;
968}
969
7a47f20e 970static enum drm_mode_status radeon_vga_mode_valid(struct drm_connector *connector,
26d6fd81 971 const struct drm_display_mode *mode)
771fe6b9 972{
b20f9bef
AD		 973 struct drm_device *dev = connector->dev;
974 struct radeon_device *rdev = dev->dev_private;
975
a3fa6320 976 /* XXX check mode bandwidth */
b20f9bef
AD		 977
978 if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
979 return MODE_CLOCK_HIGH;
980
771fe6b9
JG		 981 return MODE_OK;
982}
983
7b334fcb 984static enum drm_connector_status
930a9e28 985radeon_vga_detect(struct drm_connector *connector, bool force)
771fe6b9 986{
fafcf94e
AD		 987 struct drm_device *dev = connector->dev;
988 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 989 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
990 struct drm_encoder *encoder;
319d1e14 991 const struct drm_encoder_helper_funcs *encoder_funcs;
4b9d2a21 992 bool dret = false;
771fe6b9 993 enum drm_connector_status ret = connector_status_disconnected;
10ebc0bc
DA		 994 int r;
995
15734fef
LW		 996 if (!drm_kms_helper_is_poll_worker()) {
997 r = pm_runtime_get_sync(connector->dev->dev);
6f2e8acd
AP		 998 if (r < 0) {
999 pm_runtime_put_autosuspend(connector->dev->dev);
15734fef 1000 return connector_status_disconnected;
6f2e8acd 1001 }
15734fef 1002 }
771fe6b9 1003
4ce001ab
DA		 1004 encoder = radeon_best_single_encoder(connector);
1005 if (!encoder)
1006 ret = connector_status_disconnected;
1007
eb6b6d7c 1008 if (radeon_connector->ddc_bus)
0a9069d3 1009 dret = radeon_ddc_probe(radeon_connector, false);
0294cf4f 1010 if (dret) {
d0d0a225 1011 radeon_connector->detected_by_load = false;
72a5c970
AD		 1012 radeon_connector_free_edid(connector);
1013 radeon_connector_get_edid(connector);
0294cf4f
AD		 1014
1015 if (!radeon_connector->edid) {
f82f5f3a 1016 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
72082093 1017 connector->name);
f82f5f3a 1018 ret = connector_status_connected;
0294cf4f 1019 } else {
72a5c970
AD		 1020 radeon_connector->use_digital =
1021 !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
0294cf4f
AD		 1022
1023 /* some oems have boards with separate digital and analog connectors
1024 * with a shared ddc line (often vga + hdmi)
1025 */
1026 if (radeon_connector->use_digital && radeon_connector->shared_ddc) {
72a5c970 1027 radeon_connector_free_edid(connector);
0294cf4f 1028 ret = connector_status_disconnected;
72a5c970 1029 } else {
0294cf4f 1030 ret = connector_status_connected;
72a5c970 1031 }
0294cf4f
AD		 1032 }
1033 } else {
c3cceedd
DA		 1034
1035 /* if we aren't forcing don't do destructive polling */
d0d0a225
AD		 1036 if (!force) {
1037 /* only return the previous status if we last
1038 * detected a monitor via load.
1039 */
1040 if (radeon_connector->detected_by_load)
10ebc0bc
DA		 1041 ret = connector->status;
1042 goto out;
d0d0a225 1043 }
c3cceedd 1044
d8a7f792 1045 if (radeon_connector->dac_load_detect && encoder) {
445282db
DA		 1046 encoder_funcs = encoder->helper_private;
1047 ret = encoder_funcs->detect(encoder, connector);
34076446 1048 if (ret != connector_status_disconnected)
d0d0a225 1049 radeon_connector->detected_by_load = true;
445282db 1050 }
771fe6b9
JG		 1051 }
1052
4ce001ab
DA		 1053 if (ret == connector_status_connected)
1054 ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
fafcf94e
AD		 1055
1056 /* RN50 and some RV100 asics in servers often have a hardcoded EDID in the
1057 * vbios to deal with KVMs. If we have one and are not able to detect a monitor
1058 * by other means, assume the CRT is connected and use that EDID.
1059 */
1060 if ((!rdev->is_atom_bios) &&
1061 (ret == connector_status_disconnected) &&
c6bb3acf 1062 rdev->mode_info.bios_hardcoded_edid) {
fafcf94e
AD		 1063 ret = connector_status_connected;
1064 }
1065
771fe6b9 1066 radeon_connector_update_scratch_regs(connector, ret);
10ebc0bc
DA		 1067
1068out:
15734fef
LW		 1069 if (!drm_kms_helper_is_poll_worker()) {
1070 pm_runtime_mark_last_busy(connector->dev->dev);
1071 pm_runtime_put_autosuspend(connector->dev->dev);
1072 }
10ebc0bc 1073
771fe6b9
JG		 1074 return ret;
1075}
1076
1109ca09 1077static const struct drm_connector_helper_funcs radeon_vga_connector_helper_funcs = {
771fe6b9
JG		 1078 .get_modes = radeon_vga_get_modes,
1079 .mode_valid = radeon_vga_mode_valid,
1080 .best_encoder = radeon_best_single_encoder,
1081};
1082
1109ca09 1083static const struct drm_connector_funcs radeon_vga_connector_funcs = {
771fe6b9
JG		 1084 .dpms = drm_helper_connector_dpms,
1085 .detect = radeon_vga_detect,
1086 .fill_modes = drm_helper_probe_single_connector_modes,
b0c80bd5 1087 .early_unregister = radeon_connector_unregister,
771fe6b9
JG		 1088 .destroy = radeon_connector_destroy,
1089 .set_property = radeon_connector_set_property,
1090};
1091
4ce001ab
DA		 1092static int radeon_tv_get_modes(struct drm_connector *connector)
1093{
1094 struct drm_device *dev = connector->dev;
923f6848 1095 struct radeon_device *rdev = dev->dev_private;
4ce001ab 1096 struct drm_display_mode *tv_mode;
923f6848 1097 struct drm_encoder *encoder;
4ce001ab 1098
923f6848
AD		 1099 encoder = radeon_best_single_encoder(connector);
1100 if (!encoder)
1101 return 0;
4ce001ab 1102
923f6848
AD		 1103 /* avivo chips can scale any mode */
1104 if (rdev->family >= CHIP_RS600)
1105 /* add scaled modes */
1106 radeon_add_common_modes(encoder, connector);
1107 else {
1108 /* only 800x600 is supported right now on pre-avivo chips */
d50ba256 1109 tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false, false);
2c1fe3c4
MK		 1110 if (!tv_mode)
1111 return 0;
923f6848
AD		 1112 tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
1113 drm_mode_probed_add(connector, tv_mode);
1114 }
4ce001ab
DA		 1115 return 1;
1116}
1117
7a47f20e 1118static enum drm_mode_status radeon_tv_mode_valid(struct drm_connector *connector,
26d6fd81 1119 const struct drm_display_mode *mode)
4ce001ab 1120{
a3fa6320
AD		 1121 if ((mode->hdisplay > 1024) || (mode->vdisplay > 768))
1122 return MODE_CLOCK_RANGE;
4ce001ab
DA		 1123 return MODE_OK;
1124}
1125
7b334fcb 1126static enum drm_connector_status
930a9e28 1127radeon_tv_detect(struct drm_connector *connector, bool force)
4ce001ab
DA		 1128{
1129 struct drm_encoder *encoder;
319d1e14 1130 const struct drm_encoder_helper_funcs *encoder_funcs;
445282db
DA		 1131 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1132 enum drm_connector_status ret = connector_status_disconnected;
10ebc0bc 1133 int r;
445282db
DA		 1134
1135 if (!radeon_connector->dac_load_detect)
1136 return ret;
4ce001ab 1137
15734fef
LW		 1138 if (!drm_kms_helper_is_poll_worker()) {
1139 r = pm_runtime_get_sync(connector->dev->dev);
6f2e8acd
AP		 1140 if (r < 0) {
1141 pm_runtime_put_autosuspend(connector->dev->dev);
15734fef 1142 return connector_status_disconnected;
6f2e8acd 1143 }
15734fef 1144 }
10ebc0bc 1145
4ce001ab
DA		 1146 encoder = radeon_best_single_encoder(connector);
1147 if (!encoder)
1148 ret = connector_status_disconnected;
1149 else {
1150 encoder_funcs = encoder->helper_private;
1151 ret = encoder_funcs->detect(encoder, connector);
1152 }
1153 if (ret == connector_status_connected)
1154 ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false);
1155 radeon_connector_update_scratch_regs(connector, ret);
15734fef
LW		 1156
1157 if (!drm_kms_helper_is_poll_worker()) {
1158 pm_runtime_mark_last_busy(connector->dev->dev);
1159 pm_runtime_put_autosuspend(connector->dev->dev);
1160 }
1161
4ce001ab
DA		 1162 return ret;
1163}
1164
1109ca09 1165static const struct drm_connector_helper_funcs radeon_tv_connector_helper_funcs = {
4ce001ab
DA		 1166 .get_modes = radeon_tv_get_modes,
1167 .mode_valid = radeon_tv_mode_valid,
1168 .best_encoder = radeon_best_single_encoder,
1169};
1170
1109ca09 1171static const struct drm_connector_funcs radeon_tv_connector_funcs = {
4ce001ab
DA		 1172 .dpms = drm_helper_connector_dpms,
1173 .detect = radeon_tv_detect,
1174 .fill_modes = drm_helper_probe_single_connector_modes,
b0c80bd5 1175 .early_unregister = radeon_connector_unregister,
4ce001ab
DA		 1176 .destroy = radeon_connector_destroy,
1177 .set_property = radeon_connector_set_property,
1178};
1179
11fe1266
TU		 1180static bool radeon_check_hpd_status_unchanged(struct drm_connector *connector)
1181{
1182 struct drm_device *dev = connector->dev;
1183 struct radeon_device *rdev = dev->dev_private;
1184 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1185 enum drm_connector_status status;
1186
1187 /* We only trust HPD on R600 and newer ASICS. */
1188 if (rdev->family >= CHIP_R600
1189 && radeon_connector->hpd.hpd != RADEON_HPD_NONE) {
1190 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1191 status = connector_status_connected;
1192 else
1193 status = connector_status_disconnected;
1194 if (connector->status == status)
1195 return true;
1196 }
1197
1198 return false;
1199}
1200
4ce001ab
DA		 1201/*
1202 * DVI is complicated
1203 * Do a DDC probe, if DDC probe passes, get the full EDID so
1204 * we can do analog/digital monitor detection at this point.
1205 * If the monitor is an analog monitor or we got no DDC,
1206 * we need to find the DAC encoder object for this connector.
1207 * If we got no DDC, we do load detection on the DAC encoder object.
1208 * If we got analog DDC or load detection passes on the DAC encoder
1209 * we have to check if this analog encoder is shared with anyone else (TV)
1210 * if its shared we have to set the other connector to disconnected.
1211 */
7b334fcb 1212static enum drm_connector_status
930a9e28 1213radeon_dvi_detect(struct drm_connector *connector, bool force)
771fe6b9 1214{
fafcf94e
AD		 1215 struct drm_device *dev = connector->dev;
1216 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1217 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
4ce001ab 1218 struct drm_encoder *encoder = NULL;
319d1e14 1219 const struct drm_encoder_helper_funcs *encoder_funcs;
7b71ca24 1220 int r;
771fe6b9 1221 enum drm_connector_status ret = connector_status_disconnected;
fc87f13b 1222 bool dret = false, broken_edid = false;
771fe6b9 1223
15734fef
LW		 1224 if (!drm_kms_helper_is_poll_worker()) {
1225 r = pm_runtime_get_sync(connector->dev->dev);
6f2e8acd
AP		 1226 if (r < 0) {
1227 pm_runtime_put_autosuspend(connector->dev->dev);
15734fef 1228 return connector_status_disconnected;
6f2e8acd 1229 }
15734fef 1230 }
10ebc0bc 1231
cb5d4166
L		 1232 if (radeon_connector->detected_hpd_without_ddc) {
1233 force = true;
1234 radeon_connector->detected_hpd_without_ddc = false;
1235 }
1236
10ebc0bc
DA		 1237 if (!force && radeon_check_hpd_status_unchanged(connector)) {
1238 ret = connector->status;
1239 goto exit;
1240 }
11fe1266 1241
cb5d4166 1242 if (radeon_connector->ddc_bus) {
0a9069d3 1243 dret = radeon_ddc_probe(radeon_connector, false);
cb5d4166
L		 1244
1245 /* Sometimes the pins required for the DDC probe on DVI
1246 * connectors don't make contact at the same time that the ones
1247 * for HPD do. If the DDC probe fails even though we had an HPD
1248 * signal, try again later */
1249 if (!dret && !force &&
1250 connector->status != connector_status_connected) {
1251 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
1252 radeon_connector->detected_hpd_without_ddc = true;
1253 schedule_delayed_work(&rdev->hotplug_work,
1254 msecs_to_jiffies(1000));
1255 goto exit;
1256 }
1257 }
4ce001ab 1258 if (dret) {
d0d0a225 1259 radeon_connector->detected_by_load = false;
72a5c970
AD		 1260 radeon_connector_free_edid(connector);
1261 radeon_connector_get_edid(connector);
4ce001ab
DA		 1262
1263 if (!radeon_connector->edid) {
f82f5f3a 1264 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
72082093 1265 connector->name);
4a9a8b71
DA		 1266 /* rs690 seems to have a problem with connectors not existing and always
1267 * return a block of 0's. If we see this just stop polling on this output */
72a5c970
AD		 1268 if ((rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) &&
1269 radeon_connector->base.null_edid_counter) {
4a9a8b71 1270 ret = connector_status_disconnected;
72082093
JN		 1271 DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n",
1272 connector->name);
4a9a8b71 1273 radeon_connector->ddc_bus = NULL;
fc87f13b
EE		 1274 } else {
1275 ret = connector_status_connected;
1276 broken_edid = true; /* defer use_digital to later */
4a9a8b71 1277 }
4ce001ab 1278 } else {
72a5c970
AD		 1279 radeon_connector->use_digital =
1280 !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
4ce001ab 1281
0294cf4f
AD		 1282 /* some oems have boards with separate digital and analog connectors
1283 * with a shared ddc line (often vga + hdmi)
1284 */
1285 if ((!radeon_connector->use_digital) && radeon_connector->shared_ddc) {
72a5c970 1286 radeon_connector_free_edid(connector);
0294cf4f 1287 ret = connector_status_disconnected;
72a5c970 1288 } else {
0294cf4f 1289 ret = connector_status_connected;
72a5c970 1290 }
42f14c4b
AD		 1291 /* This gets complicated. We have boards with VGA + HDMI with a
1292 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1293 * DDC line. The latter is more complex because with DVI<->HDMI adapters
1294 * you don't really know what's connected to which port as both are digital.
71407c46 1295 */
d3932d6c 1296 if (radeon_connector->shared_ddc && (ret == connector_status_connected)) {
71407c46
AD		 1297 struct drm_connector *list_connector;
1298 struct radeon_connector *list_radeon_connector;
1299 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1300 if (connector == list_connector)
1301 continue;
1302 list_radeon_connector = to_radeon_connector(list_connector);
b2ea4aa6
AD		 1303 if (list_radeon_connector->shared_ddc &&
1304 (list_radeon_connector->ddc_bus->rec.i2c_id ==
1305 radeon_connector->ddc_bus->rec.i2c_id)) {
42f14c4b
AD		 1306 /* cases where both connectors are digital */
1307 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1308 /* hpd is our only option in this case */
1309 if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
72a5c970 1310 radeon_connector_free_edid(connector);
71407c46
AD		 1311 ret = connector_status_disconnected;
1312 }
1313 }
1314 }
1315 }
1316 }
4ce001ab
DA		 1317 }
1318 }
1319
1320 if ((ret == connector_status_connected) && (radeon_connector->use_digital == true))
1321 goto out;
1322
5f0a2612
AD		 1323 /* DVI-D and HDMI-A are digital only */
1324 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1325 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1326 goto out;
1327
d0d0a225 1328 /* if we aren't forcing don't do destructive polling */
c3cceedd 1329 if (!force) {
d0d0a225
AD		 1330 /* only return the previous status if we last
1331 * detected a monitor via load.
1332 */
1333 if (radeon_connector->detected_by_load)
1334 ret = connector->status;
c3cceedd
DA		 1335 goto out;
1336 }
1337
4ce001ab 1338 /* find analog encoder */
445282db 1339 if (radeon_connector->dac_load_detect) {
62afb4ad 1340 drm_connector_for_each_possible_encoder(connector, encoder) {
e3632507 1341 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
e00e8b5e
AD		 1342 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1343 continue;
1344
445282db
DA		 1345 encoder_funcs = encoder->helper_private;
1346 if (encoder_funcs->detect) {
fc87f13b
EE		 1347 if (!broken_edid) {
1348 if (ret != connector_status_connected) {
1349 /* deal with analog monitors without DDC */
1350 ret = encoder_funcs->detect(encoder, connector);
1351 if (ret == connector_status_connected) {
1352 radeon_connector->use_digital = false;
1353 }
1354 if (ret != connector_status_disconnected)
1355 radeon_connector->detected_by_load = true;
445282db 1356 }
fc87f13b
EE		 1357 } else {
1358 enum drm_connector_status lret;
1359 /* assume digital unless load detected otherwise */
1360 radeon_connector->use_digital = true;
1361 lret = encoder_funcs->detect(encoder, connector);
dc200356 1362 DRM_DEBUG_KMS("load_detect %x returned: %x\n", encoder->encoder_type, lret);
fc87f13b
EE		 1363 if (lret == connector_status_connected)
1364 radeon_connector->use_digital = false;
771fe6b9 1365 }
445282db 1366 break;
771fe6b9
JG		 1367 }
1368 }
1369 }
1370
4ce001ab
DA		 1371 if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) &&
1372 encoder) {
1373 ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
1374 }
1375
fafcf94e
AD		 1376 /* RN50 and some RV100 asics in servers often have a hardcoded EDID in the
1377 * vbios to deal with KVMs. If we have one and are not able to detect a monitor
1378 * by other means, assume the DFP is connected and use that EDID. In most
1379 * cases the DVI port is actually a virtual KVM port connected to the service
1380 * processor.
1381 */
a09d431f 1382out:
fafcf94e
AD		 1383 if ((!rdev->is_atom_bios) &&
1384 (ret == connector_status_disconnected) &&
c6bb3acf 1385 rdev->mode_info.bios_hardcoded_edid) {
fafcf94e
AD		 1386 radeon_connector->use_digital = true;
1387 ret = connector_status_connected;
1388 }
1389
771fe6b9
JG		 1390 /* updated in get modes as well since we need to know if it's analog or digital */
1391 radeon_connector_update_scratch_regs(connector, ret);
10ebc0bc 1392
d0ea397e
AD		 1393 if ((radeon_audio != 0) && radeon_connector->use_digital) {
1394 const struct drm_connector_helper_funcs *connector_funcs =
1395 connector->helper_private;
1396
1397 encoder = connector_funcs->best_encoder(connector);
1398 if (encoder && (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)) {
1399 radeon_connector_get_edid(connector);
1400 radeon_audio_detect(connector, encoder, ret);
1401 }
1402 }
1a626b68 1403
10ebc0bc 1404exit:
15734fef
LW		 1405 if (!drm_kms_helper_is_poll_worker()) {
1406 pm_runtime_mark_last_busy(connector->dev->dev);
1407 pm_runtime_put_autosuspend(connector->dev->dev);
1408 }
10ebc0bc 1409
771fe6b9
JG		 1410 return ret;
1411}
1412
1413/* okay need to be smart in here about which encoder to pick */
1109ca09 1414static struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector)
771fe6b9 1415{
771fe6b9 1416 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9 1417 struct drm_encoder *encoder;
771fe6b9 1418
62afb4ad 1419 drm_connector_for_each_possible_encoder(connector, encoder) {
4ce001ab 1420 if (radeon_connector->use_digital == true) {
771fe6b9
JG		 1421 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1422 return encoder;
1423 } else {
1424 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1425 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1426 return encoder;
1427 }
1428 }
1429
1430 /* see if we have a default encoder TODO */
1431
1432 /* then check use digitial */
1433 /* pick the first one */
62afb4ad 1434 drm_connector_for_each_possible_encoder(connector, encoder)
7b71ca24
VS		 1435 return encoder;
1436
771fe6b9
JG		 1437 return NULL;
1438}
1439
d50ba256
DA		 1440static void radeon_dvi_force(struct drm_connector *connector)
1441{
1442 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1443 if (connector->force == DRM_FORCE_ON)
1444 radeon_connector->use_digital = false;
1445 if (connector->force == DRM_FORCE_ON_DIGITAL)
1446 radeon_connector->use_digital = true;
1447}
1448
7a47f20e 1449static enum drm_mode_status radeon_dvi_mode_valid(struct drm_connector *connector,
26d6fd81 1450 const struct drm_display_mode *mode)
a3fa6320 1451{
1b24203e
AD		 1452 struct drm_device *dev = connector->dev;
1453 struct radeon_device *rdev = dev->dev_private;
a3fa6320
AD		 1454 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1455
1456 /* XXX check mode bandwidth */
1457
1b24203e
AD		 1458 /* clocks over 135 MHz have heat issues with DVI on RV100 */
1459 if (radeon_connector->use_digital &&
1460 (rdev->family == CHIP_RV100) &&
1461 (mode->clock > 135000))
1462 return MODE_CLOCK_HIGH;
1463
a3fa6320
AD		 1464 if (radeon_connector->use_digital && (mode->clock > 165000)) {
1465 if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1466 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1467 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
1468 return MODE_OK;
242136ed 1469 else if (ASIC_IS_DCE6(rdev) && connector->display_info.is_hdmi) {
f2263fc7
AD		 1470 /* HDMI 1.3+ supports max clock of 340 Mhz */
1471 if (mode->clock > 340000)
e1e84017 1472 return MODE_CLOCK_HIGH;
f2263fc7
AD		 1473 else
1474 return MODE_OK;
1475 } else {
a3fa6320 1476 return MODE_CLOCK_HIGH;
f2263fc7 1477 }
a3fa6320 1478 }
b20f9bef
AD		 1479
1480 /* check against the max pixel clock */
1481 if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
1482 return MODE_CLOCK_HIGH;
1483
a3fa6320
AD		 1484 return MODE_OK;
1485}
1486
1109ca09 1487static const struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = {
3e22920f 1488 .get_modes = radeon_vga_get_modes,
a3fa6320 1489 .mode_valid = radeon_dvi_mode_valid,
771fe6b9
JG		 1490 .best_encoder = radeon_dvi_encoder,
1491};
1492
1109ca09 1493static const struct drm_connector_funcs radeon_dvi_connector_funcs = {
771fe6b9
JG		 1494 .dpms = drm_helper_connector_dpms,
1495 .detect = radeon_dvi_detect,
1496 .fill_modes = drm_helper_probe_single_connector_modes,
1497 .set_property = radeon_connector_set_property,
b0c80bd5 1498 .early_unregister = radeon_connector_unregister,
771fe6b9 1499 .destroy = radeon_connector_destroy,
d50ba256 1500 .force = radeon_dvi_force,
771fe6b9
JG		 1501};
1502
746c1aa4
DA		 1503static int radeon_dp_get_modes(struct drm_connector *connector)
1504{
1505 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
8b834852 1506 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
591a10e1 1507 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
746c1aa4
DA		 1508 int ret;
1509
f89931f3
AD		 1510 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1511 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
d291767b
AD		 1512 struct drm_display_mode *mode;
1513
2b69ffb9
AD		 1514 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1515 if (!radeon_dig_connector->edp_on)
1516 atombios_set_edp_panel_power(connector,
1517 ATOM_TRANSMITTER_ACTION_POWER_ON);
72a5c970
AD		 1518 radeon_connector_get_edid(connector);
1519 ret = radeon_ddc_get_modes(connector);
2b69ffb9
AD		 1520 if (!radeon_dig_connector->edp_on)
1521 atombios_set_edp_panel_power(connector,
1522 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1523 } else {
1524 /* need to setup ddc on the bridge */
1525 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1526 ENCODER_OBJECT_ID_NONE) {
1527 if (encoder)
1528 radeon_atom_ext_encoder_setup_ddc(encoder);
1529 }
72a5c970
AD		 1530 radeon_connector_get_edid(connector);
1531 ret = radeon_ddc_get_modes(connector);
2b69ffb9 1532 }
d291767b
AD		 1533
1534 if (ret > 0) {
d291767b
AD		 1535 if (encoder) {
1536 radeon_fixup_lvds_native_mode(encoder, connector);
1537 /* add scaled modes */
1538 radeon_add_common_modes(encoder, connector);
1539 }
1540 return ret;
1541 }
1542
d291767b
AD		 1543 if (!encoder)
1544 return 0;
1545
1546 /* we have no EDID modes */
1547 mode = radeon_fp_native_mode(encoder);
1548 if (mode) {
1549 ret = 1;
1550 drm_mode_probed_add(connector, mode);
1551 /* add the width/height from vbios tables if available */
1552 connector->display_info.width_mm = mode->width_mm;
1553 connector->display_info.height_mm = mode->height_mm;
1554 /* add scaled modes */
1555 radeon_add_common_modes(encoder, connector);
1556 }
591a10e1
AD		 1557 } else {
1558 /* need to setup ddc on the bridge */
1d33e1fc
AD		 1559 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1560 ENCODER_OBJECT_ID_NONE) {
591a10e1
AD		 1561 if (encoder)
1562 radeon_atom_ext_encoder_setup_ddc(encoder);
1563 }
72a5c970
AD		 1564 radeon_connector_get_edid(connector);
1565 ret = radeon_ddc_get_modes(connector);
da997620
AD		 1566
1567 radeon_get_native_mode(connector);
591a10e1 1568 }
8b834852 1569
746c1aa4
DA		 1570 return ret;
1571}
1572
1d33e1fc 1573u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
d7fa8bb3 1574{
d7fa8bb3
AD		 1575 struct drm_encoder *encoder;
1576 struct radeon_encoder *radeon_encoder;
d7fa8bb3 1577
62afb4ad 1578 drm_connector_for_each_possible_encoder(connector, encoder) {
d7fa8bb3
AD		 1579 radeon_encoder = to_radeon_encoder(encoder);
1580
1581 switch (radeon_encoder->encoder_id) {
1582 case ENCODER_OBJECT_ID_TRAVIS:
1583 case ENCODER_OBJECT_ID_NUTMEG:
1d33e1fc 1584 return radeon_encoder->encoder_id;
d7fa8bb3
AD		 1585 default:
1586 break;
1587 }
1588 }
1589
1d33e1fc 1590 return ENCODER_OBJECT_ID_NONE;
d7fa8bb3
AD		 1591}
1592
ebdea82d 1593static bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector)
d7fa8bb3 1594{
d7fa8bb3
AD		 1595 struct drm_encoder *encoder;
1596 struct radeon_encoder *radeon_encoder;
d7fa8bb3
AD		 1597 bool found = false;
1598
62afb4ad 1599 drm_connector_for_each_possible_encoder(connector, encoder) {
d7fa8bb3
AD		 1600 radeon_encoder = to_radeon_encoder(encoder);
1601 if (radeon_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1602 found = true;
1603 }
1604
1605 return found;
1606}
1607
1608bool radeon_connector_is_dp12_capable(struct drm_connector *connector)
1609{
1610 struct drm_device *dev = connector->dev;
1611 struct radeon_device *rdev = dev->dev_private;
1612
1613 if (ASIC_IS_DCE5(rdev) &&
af5d3653 1614 (rdev->clock.default_dispclk >= 53900) &&
d7fa8bb3
AD		 1615 radeon_connector_encoder_is_hbr2(connector)) {
1616 return true;
1617 }
1618
1619 return false;
1620}
1621
7b334fcb 1622static enum drm_connector_status
930a9e28 1623radeon_dp_detect(struct drm_connector *connector, bool force)
746c1aa4 1624{
f8d0edde
AD		 1625 struct drm_device *dev = connector->dev;
1626 struct radeon_device *rdev = dev->dev_private;
746c1aa4 1627 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
746c1aa4 1628 enum drm_connector_status ret = connector_status_disconnected;
4143e919 1629 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
591a10e1 1630 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
10ebc0bc 1631 int r;
746c1aa4 1632
15734fef
LW		 1633 if (!drm_kms_helper_is_poll_worker()) {
1634 r = pm_runtime_get_sync(connector->dev->dev);
6f2e8acd
AP		 1635 if (r < 0) {
1636 pm_runtime_put_autosuspend(connector->dev->dev);
15734fef 1637 return connector_status_disconnected;
6f2e8acd 1638 }
15734fef 1639 }
10ebc0bc
DA		 1640
1641 if (!force && radeon_check_hpd_status_unchanged(connector)) {
1642 ret = connector->status;
1643 goto out;
1644 }
11fe1266 1645
72a5c970 1646 radeon_connector_free_edid(connector);
746c1aa4 1647
f89931f3
AD		 1648 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1649 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
d291767b
AD		 1650 if (encoder) {
1651 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1652 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
1653
1654 /* check if panel is valid */
1655 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1656 ret = connector_status_connected;
13485794
AD		 1657 /* don't fetch the edid from the vbios if ddc fails and runpm is
1658 * enabled so we report disconnected.
1659 */
1660 if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
1661 ret = connector_status_disconnected;
d291767b 1662 }
6f50eae7
AD		 1663 /* eDP is always DP */
1664 radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
8b834852
AD		 1665 if (!radeon_dig_connector->edp_on)
1666 atombios_set_edp_panel_power(connector,
1667 ATOM_TRANSMITTER_ACTION_POWER_ON);
6f50eae7 1668 if (radeon_dp_getdpcd(radeon_connector))
9fa05c98 1669 ret = connector_status_connected;
8b834852
AD		 1670 if (!radeon_dig_connector->edp_on)
1671 atombios_set_edp_panel_power(connector,
1672 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1d33e1fc
AD		 1673 } else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1674 ENCODER_OBJECT_ID_NONE) {
b06947b5
AD		 1675 /* DP bridges are always DP */
1676 radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1677 /* get the DPCD from the bridge */
1678 radeon_dp_getdpcd(radeon_connector);
1679
6777a4f6
AD		 1680 if (encoder) {
1681 /* setup ddc on the bridge */
1682 radeon_atom_ext_encoder_setup_ddc(encoder);
0a9069d3
NOS		 1683 /* bridge chips are always aux */
1684 if (radeon_ddc_probe(radeon_connector, true)) /* try DDC */
b06947b5 1685 ret = connector_status_connected;
6777a4f6 1686 else if (radeon_connector->dac_load_detect) { /* try load detection */
319d1e14 1687 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
b06947b5
AD		 1688 ret = encoder_funcs->detect(encoder, connector);
1689 }
591a10e1 1690 }
b06947b5 1691 } else {
6f50eae7 1692 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
f8d0edde
AD		 1693 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
1694 ret = connector_status_connected;
01ad1d9c 1695 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
f8d0edde 1696 radeon_dp_getdpcd(radeon_connector);
6f50eae7 1697 } else {
f8d0edde 1698 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
01ad1d9c
LP		 1699 if (radeon_dp_getdpcd(radeon_connector))
1700 ret = connector_status_connected;
f8d0edde 1701 } else {
d592fca9 1702 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
0a9069d3 1703 if (radeon_ddc_probe(radeon_connector, false))
f8d0edde
AD		 1704 ret = connector_status_connected;
1705 }
4143e919 1706 }
746c1aa4 1707 }
4143e919 1708
30f44372 1709 radeon_connector_update_scratch_regs(connector, ret);
1a626b68 1710
d0ea397e
AD		 1711 if ((radeon_audio != 0) && encoder) {
1712 radeon_connector_get_edid(connector);
1713 radeon_audio_detect(connector, encoder, ret);
1714 }
1a626b68 1715
10ebc0bc 1716out:
15734fef
LW		 1717 if (!drm_kms_helper_is_poll_worker()) {
1718 pm_runtime_mark_last_busy(connector->dev->dev);
1719 pm_runtime_put_autosuspend(connector->dev->dev);
1720 }
10ebc0bc 1721
746c1aa4
DA		 1722 return ret;
1723}
1724
7a47f20e 1725static enum drm_mode_status radeon_dp_mode_valid(struct drm_connector *connector,
26d6fd81 1726 const struct drm_display_mode *mode)
5801ead6 1727{
6536a3a6
AD		 1728 struct drm_device *dev = connector->dev;
1729 struct radeon_device *rdev = dev->dev_private;
5801ead6
AD		 1730 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1731 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1732
1733 /* XXX check mode bandwidth */
1734
f89931f3
AD		 1735 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1736 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
d291767b
AD		 1737 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1738
1739 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1740 return MODE_PANEL;
1741
1742 if (encoder) {
1743 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1744 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
1745
f89931f3 1746 /* AVIVO hardware supports downscaling modes larger than the panel
d291767b
AD		 1747 * to the panel size, but I'm not sure this is desirable.
1748 */
1749 if ((mode->hdisplay > native_mode->hdisplay) ||
1750 (mode->vdisplay > native_mode->vdisplay))
1751 return MODE_PANEL;
1752
1753 /* if scaling is disabled, block non-native modes */
1754 if (radeon_encoder->rmx_type == RMX_OFF) {
1755 if ((mode->hdisplay != native_mode->hdisplay) ||
1756 (mode->vdisplay != native_mode->vdisplay))
1757 return MODE_PANEL;
1758 }
1759 }
d291767b
AD		 1760 } else {
1761 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
6536a3a6 1762 (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
d291767b 1763 return radeon_dp_mode_valid_helper(connector, mode);
6536a3a6 1764 } else {
242136ed 1765 if (ASIC_IS_DCE6(rdev) && connector->display_info.is_hdmi) {
6536a3a6
AD		 1766 /* HDMI 1.3+ supports max clock of 340 Mhz */
1767 if (mode->clock > 340000)
1768 return MODE_CLOCK_HIGH;
1769 } else {
1770 if (mode->clock > 165000)
1771 return MODE_CLOCK_HIGH;
1772 }
1773 }
d291767b 1774 }
6536a3a6
AD		 1775
1776 return MODE_OK;
5801ead6
AD		 1777}
1778
b4c1ad70
WHP		 1779static int
1780radeon_connector_late_register(struct drm_connector *connector)
1781{
1782 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1783 int r = 0;
1784
1785 if (radeon_connector->ddc_bus->has_aux) {
1786 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
1787 r = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
1788 }
1789
1790 return r;
1791}
1792
1109ca09 1793static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = {
746c1aa4 1794 .get_modes = radeon_dp_get_modes,
5801ead6 1795 .mode_valid = radeon_dp_mode_valid,
746c1aa4
DA		 1796 .best_encoder = radeon_dvi_encoder,
1797};
1798
1109ca09 1799static const struct drm_connector_funcs radeon_dp_connector_funcs = {
746c1aa4
DA		 1800 .dpms = drm_helper_connector_dpms,
1801 .detect = radeon_dp_detect,
1802 .fill_modes = drm_helper_probe_single_connector_modes,
1803 .set_property = radeon_connector_set_property,
b0c80bd5 1804 .early_unregister = radeon_connector_unregister,
379dfc25 1805 .destroy = radeon_connector_destroy,
746c1aa4 1806 .force = radeon_dvi_force,
b4c1ad70 1807 .late_register = radeon_connector_late_register,
746c1aa4
DA		 1808};
1809
855f5f1d
AD		 1810static const struct drm_connector_funcs radeon_edp_connector_funcs = {
1811 .dpms = drm_helper_connector_dpms,
1812 .detect = radeon_dp_detect,
1813 .fill_modes = drm_helper_probe_single_connector_modes,
1814 .set_property = radeon_lvds_set_property,
b0c80bd5 1815 .early_unregister = radeon_connector_unregister,
379dfc25 1816 .destroy = radeon_connector_destroy,
855f5f1d 1817 .force = radeon_dvi_force,
b4c1ad70 1818 .late_register = radeon_connector_late_register,
855f5f1d
AD		 1819};
1820
1821static const struct drm_connector_funcs radeon_lvds_bridge_connector_funcs = {
1822 .dpms = drm_helper_connector_dpms,
1823 .detect = radeon_dp_detect,
1824 .fill_modes = drm_helper_probe_single_connector_modes,
1825 .set_property = radeon_lvds_set_property,
b0c80bd5 1826 .early_unregister = radeon_connector_unregister,
379dfc25 1827 .destroy = radeon_connector_destroy,
855f5f1d 1828 .force = radeon_dvi_force,
b4c1ad70 1829 .late_register = radeon_connector_late_register,
855f5f1d
AD		 1830};
1831
771fe6b9
JG		 1832void
1833radeon_add_atom_connector(struct drm_device *dev,
1834 uint32_t connector_id,
1835 uint32_t supported_device,
1836 int connector_type,
1837 struct radeon_i2c_bus_rec *i2c_bus,
b75fad06 1838 uint32_t igp_lane_info,
eed45b30 1839 uint16_t connector_object_id,
26b5bc98
AD		 1840 struct radeon_hpd *hpd,
1841 struct radeon_router *router)
771fe6b9 1842{
445282db 1843 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1844 struct drm_connector *connector;
1845 struct radeon_connector *radeon_connector;
1846 struct radeon_connector_atom_dig *radeon_dig_connector;
eac4dff6
AD		 1847 struct drm_encoder *encoder;
1848 struct radeon_encoder *radeon_encoder;
af0e31ab 1849 struct i2c_adapter *ddc = NULL;
771fe6b9 1850 uint32_t subpixel_order = SubPixelNone;
0294cf4f 1851 bool shared_ddc = false;
eac4dff6 1852 bool is_dp_bridge = false;
496263bf 1853 bool has_aux = false;
771fe6b9 1854
4ce001ab 1855 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
771fe6b9
JG		 1856 return;
1857
cf4c12f9
AD		 1858 /* if the user selected tv=0 don't try and add the connector */
1859 if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
1860 (connector_type == DRM_MODE_CONNECTOR_Composite) ||
1861 (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
1862 (radeon_tv == 0))
1863 return;
1864
771fe6b9
JG		 1865 /* see if we already added it */
1866 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1867 radeon_connector = to_radeon_connector(connector);
1868 if (radeon_connector->connector_id == connector_id) {
1869 radeon_connector->devices |= supported_device;
1870 return;
1871 }
0294cf4f 1872 if (radeon_connector->ddc_bus && i2c_bus->valid) {
d3932d6c 1873 if (radeon_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
0294cf4f
AD		 1874 radeon_connector->shared_ddc = true;
1875 shared_ddc = true;
1876 }
fb939dfc 1877 if (radeon_connector->router_bus && router->ddc_valid &&
26b5bc98
AD		 1878 (radeon_connector->router.router_id == router->router_id)) {
1879 radeon_connector->shared_ddc = false;
1880 shared_ddc = false;
1881 }
0294cf4f 1882 }
771fe6b9
JG		 1883 }
1884
eac4dff6
AD		 1885 /* check if it's a dp bridge */
1886 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1887 radeon_encoder = to_radeon_encoder(encoder);
1888 if (radeon_encoder->devices & supported_device) {
1889 switch (radeon_encoder->encoder_id) {
1890 case ENCODER_OBJECT_ID_TRAVIS:
1891 case ENCODER_OBJECT_ID_NUTMEG:
1892 is_dp_bridge = true;
1893 break;
1894 default:
1895 break;
1896 }
1897 }
1898 }
1899
771fe6b9
JG		 1900 radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
1901 if (!radeon_connector)
1902 return;
1903
1904 connector = &radeon_connector->base;
1905
1906 radeon_connector->connector_id = connector_id;
1907 radeon_connector->devices = supported_device;
0294cf4f 1908 radeon_connector->shared_ddc = shared_ddc;
b75fad06 1909 radeon_connector->connector_object_id = connector_object_id;
eed45b30 1910 radeon_connector->hpd = *hpd;
bc1c4dc3 1911
26b5bc98 1912 radeon_connector->router = *router;
fb939dfc 1913 if (router->ddc_valid || router->cd_valid) {
26b5bc98
AD		 1914 radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info);
1915 if (!radeon_connector->router_bus)
a70882aa 1916 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
26b5bc98 1917 }
eac4dff6
AD		 1918
1919 if (is_dp_bridge) {
771fe6b9
JG		 1920 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1921 if (!radeon_dig_connector)
1922 goto failed;
771fe6b9
JG		 1923 radeon_dig_connector->igp_lane_info = igp_lane_info;
1924 radeon_connector->con_priv = radeon_dig_connector;
771fe6b9 1925 if (i2c_bus->valid) {
379dfc25 1926 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
af0e31ab 1927 if (radeon_connector->ddc_bus) {
496263bf 1928 has_aux = true;
af0e31ab
AP		 1929 ddc = &radeon_connector->ddc_bus->adapter;
1930 } else {
eac4dff6 1931 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab 1932 }
771fe6b9 1933 }
eac4dff6
AD		 1934 switch (connector_type) {
1935 case DRM_MODE_CONNECTOR_VGA:
1936 case DRM_MODE_CONNECTOR_DVIA:
1937 default:
af0e31ab
AP		 1938 drm_connector_init_with_ddc(dev, &radeon_connector->base,
1939 &radeon_dp_connector_funcs,
1940 connector_type,
1941 ddc);
855f5f1d
AD		 1942 drm_connector_helper_add(&radeon_connector->base,
1943 &radeon_dp_connector_helper_funcs);
eac4dff6
AD		 1944 connector->interlace_allowed = true;
1945 connector->doublescan_allowed = true;
d629a3ce 1946 radeon_connector->dac_load_detect = true;
e35755fa 1947 drm_object_attach_property(&radeon_connector->base.base,
d629a3ce
AD		 1948 rdev->mode_info.load_detect_property,
1949 1);
da997620
AD		 1950 drm_object_attach_property(&radeon_connector->base.base,
1951 dev->mode_config.scaling_mode_property,
1952 DRM_MODE_SCALE_NONE);
643b1f56
AD		 1953 if (ASIC_IS_DCE5(rdev))
1954 drm_object_attach_property(&radeon_connector->base.base,
1955 rdev->mode_info.output_csc_property,
1956 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 1957 break;
1958 case DRM_MODE_CONNECTOR_DVII:
1959 case DRM_MODE_CONNECTOR_DVID:
1960 case DRM_MODE_CONNECTOR_HDMIA:
1961 case DRM_MODE_CONNECTOR_HDMIB:
1962 case DRM_MODE_CONNECTOR_DisplayPort:
af0e31ab
AP		 1963 drm_connector_init_with_ddc(dev, &radeon_connector->base,
1964 &radeon_dp_connector_funcs,
1965 connector_type,
1966 ddc);
855f5f1d
AD		 1967 drm_connector_helper_add(&radeon_connector->base,
1968 &radeon_dp_connector_helper_funcs);
e35755fa 1969 drm_object_attach_property(&radeon_connector->base.base,
430f70d5 1970 rdev->mode_info.underscan_property,
56bec7c0 1971 UNDERSCAN_OFF);
e35755fa 1972 drm_object_attach_property(&radeon_connector->base.base,
5bccf5e3
MG		 1973 rdev->mode_info.underscan_hborder_property,
1974 0);
e35755fa 1975 drm_object_attach_property(&radeon_connector->base.base,
5bccf5e3
MG		 1976 rdev->mode_info.underscan_vborder_property,
1977 0);
91915260 1978
da997620
AD		 1979 drm_object_attach_property(&radeon_connector->base.base,
1980 dev->mode_config.scaling_mode_property,
1981 DRM_MODE_SCALE_NONE);
1982
6214bb74
AD		 1983 drm_object_attach_property(&radeon_connector->base.base,
1984 rdev->mode_info.dither_property,
1985 RADEON_FMT_DITHER_DISABLE);
91915260 1986
7403c515 1987 if (radeon_audio != 0) {
108dc8e8
AD		 1988 drm_object_attach_property(&radeon_connector->base.base,
1989 rdev->mode_info.audio_property,
e31fadd3 1990 RADEON_AUDIO_AUTO);
7403c515
AD		 1991 radeon_connector->audio = RADEON_AUDIO_AUTO;
1992 }
643b1f56
AD		 1993 if (ASIC_IS_DCE5(rdev))
1994 drm_object_attach_property(&radeon_connector->base.base,
1995 rdev->mode_info.output_csc_property,
1996 RADEON_OUTPUT_CSC_BYPASS);
91915260 1997
eac4dff6
AD		 1998 subpixel_order = SubPixelHorizontalRGB;
1999 connector->interlace_allowed = true;
2000 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
2001 connector->doublescan_allowed = true;
2002 else
2003 connector->doublescan_allowed = false;
d629a3ce
AD		 2004 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
2005 radeon_connector->dac_load_detect = true;
e35755fa 2006 drm_object_attach_property(&radeon_connector->base.base,
d629a3ce
AD		 2007 rdev->mode_info.load_detect_property,
2008 1);
2009 }
eac4dff6
AD		 2010 break;
2011 case DRM_MODE_CONNECTOR_LVDS:
2012 case DRM_MODE_CONNECTOR_eDP:
af0e31ab
AP		 2013 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2014 &radeon_lvds_bridge_connector_funcs,
2015 connector_type,
2016 ddc);
855f5f1d
AD		 2017 drm_connector_helper_add(&radeon_connector->base,
2018 &radeon_dp_connector_helper_funcs);
e35755fa 2019 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2020 dev->mode_config.scaling_mode_property,
2021 DRM_MODE_SCALE_FULLSCREEN);
2022 subpixel_order = SubPixelHorizontalRGB;
2023 connector->interlace_allowed = false;
2024 connector->doublescan_allowed = false;
2025 break;
5bccf5e3 2026 }
eac4dff6
AD		 2027 } else {
2028 switch (connector_type) {
2029 case DRM_MODE_CONNECTOR_VGA:
eac4dff6
AD		 2030 if (i2c_bus->valid) {
2031 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2032 if (!radeon_connector->ddc_bus)
2033 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab
AP		 2034 else
2035 ddc = &radeon_connector->ddc_bus->adapter;
eac4dff6 2036 }
af0e31ab
AP		 2037 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2038 &radeon_vga_connector_funcs,
2039 connector_type,
2040 ddc);
2041 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
390d0bbe 2042 radeon_connector->dac_load_detect = true;
e35755fa 2043 drm_object_attach_property(&radeon_connector->base.base,
390d0bbe
AD		 2044 rdev->mode_info.load_detect_property,
2045 1);
da997620
AD		 2046 if (ASIC_IS_AVIVO(rdev))
2047 drm_object_attach_property(&radeon_connector->base.base,
2048 dev->mode_config.scaling_mode_property,
2049 DRM_MODE_SCALE_NONE);
643b1f56
AD		 2050 if (ASIC_IS_DCE5(rdev))
2051 drm_object_attach_property(&radeon_connector->base.base,
2052 rdev->mode_info.output_csc_property,
2053 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 2054 /* no HPD on analog connectors */
2055 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
eac4dff6 2056 connector->interlace_allowed = true;
c49948f4 2057 connector->doublescan_allowed = true;
eac4dff6
AD		 2058 break;
2059 case DRM_MODE_CONNECTOR_DVIA:
eac4dff6
AD		 2060 if (i2c_bus->valid) {
2061 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2062 if (!radeon_connector->ddc_bus)
2063 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab
AP		 2064 else
2065 ddc = &radeon_connector->ddc_bus->adapter;
eac4dff6 2066 }
af0e31ab
AP		 2067 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2068 &radeon_vga_connector_funcs,
2069 connector_type,
2070 ddc);
2071 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
eac4dff6 2072 radeon_connector->dac_load_detect = true;
e35755fa 2073 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2074 rdev->mode_info.load_detect_property,
2075 1);
da997620
AD		 2076 if (ASIC_IS_AVIVO(rdev))
2077 drm_object_attach_property(&radeon_connector->base.base,
2078 dev->mode_config.scaling_mode_property,
2079 DRM_MODE_SCALE_NONE);
643b1f56
AD		 2080 if (ASIC_IS_DCE5(rdev))
2081 drm_object_attach_property(&radeon_connector->base.base,
2082 rdev->mode_info.output_csc_property,
2083 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 2084 /* no HPD on analog connectors */
2085 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
2086 connector->interlace_allowed = true;
2087 connector->doublescan_allowed = true;
2088 break;
2089 case DRM_MODE_CONNECTOR_DVII:
2090 case DRM_MODE_CONNECTOR_DVID:
2091 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2092 if (!radeon_dig_connector)
2093 goto failed;
2094 radeon_dig_connector->igp_lane_info = igp_lane_info;
2095 radeon_connector->con_priv = radeon_dig_connector;
eac4dff6
AD		 2096 if (i2c_bus->valid) {
2097 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2098 if (!radeon_connector->ddc_bus)
2099 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab
AP		 2100 else
2101 ddc = &radeon_connector->ddc_bus->adapter;
eac4dff6 2102 }
af0e31ab
AP		 2103 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2104 &radeon_dvi_connector_funcs,
2105 connector_type,
2106 ddc);
2107 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
eac4dff6 2108 subpixel_order = SubPixelHorizontalRGB;
e35755fa 2109 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2110 rdev->mode_info.coherent_mode_property,
2111 1);
2112 if (ASIC_IS_AVIVO(rdev)) {
e35755fa 2113 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2114 rdev->mode_info.underscan_property,
2115 UNDERSCAN_OFF);
e35755fa 2116 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2117 rdev->mode_info.underscan_hborder_property,
2118 0);
e35755fa 2119 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2120 rdev->mode_info.underscan_vborder_property,
2121 0);
da997620
AD		 2122 drm_object_attach_property(&radeon_connector->base.base,
2123 rdev->mode_info.dither_property,
2124 RADEON_FMT_DITHER_DISABLE);
2125 drm_object_attach_property(&radeon_connector->base.base,
2126 dev->mode_config.scaling_mode_property,
2127 DRM_MODE_SCALE_NONE);
eac4dff6 2128 }
108dc8e8 2129 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
8666c076 2130 drm_object_attach_property(&radeon_connector->base.base,
108dc8e8 2131 rdev->mode_info.audio_property,
e31fadd3 2132 RADEON_AUDIO_AUTO);
7403c515 2133 radeon_connector->audio = RADEON_AUDIO_AUTO;
8666c076 2134 }
eac4dff6
AD		 2135 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
2136 radeon_connector->dac_load_detect = true;
e35755fa 2137 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2138 rdev->mode_info.load_detect_property,
2139 1);
2140 }
643b1f56
AD		 2141 if (ASIC_IS_DCE5(rdev))
2142 drm_object_attach_property(&radeon_connector->base.base,
2143 rdev->mode_info.output_csc_property,
2144 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 2145 connector->interlace_allowed = true;
2146 if (connector_type == DRM_MODE_CONNECTOR_DVII)
2147 connector->doublescan_allowed = true;
2148 else
2149 connector->doublescan_allowed = false;
2150 break;
2151 case DRM_MODE_CONNECTOR_HDMIA:
2152 case DRM_MODE_CONNECTOR_HDMIB:
2153 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2154 if (!radeon_dig_connector)
2155 goto failed;
2156 radeon_dig_connector->igp_lane_info = igp_lane_info;
2157 radeon_connector->con_priv = radeon_dig_connector;
eac4dff6
AD		 2158 if (i2c_bus->valid) {
2159 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2160 if (!radeon_connector->ddc_bus)
2161 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab
AP		 2162 else
2163 ddc = &radeon_connector->ddc_bus->adapter;
eac4dff6 2164 }
af0e31ab
AP		 2165 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2166 &radeon_dvi_connector_funcs,
2167 connector_type,
2168 ddc);
2169 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
e35755fa 2170 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2171 rdev->mode_info.coherent_mode_property,
2172 1);
2173 if (ASIC_IS_AVIVO(rdev)) {
e35755fa 2174 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2175 rdev->mode_info.underscan_property,
2176 UNDERSCAN_OFF);
e35755fa 2177 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2178 rdev->mode_info.underscan_hborder_property,
2179 0);
e35755fa 2180 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2181 rdev->mode_info.underscan_vborder_property,
2182 0);
da997620
AD		 2183 drm_object_attach_property(&radeon_connector->base.base,
2184 rdev->mode_info.dither_property,
2185 RADEON_FMT_DITHER_DISABLE);
2186 drm_object_attach_property(&radeon_connector->base.base,
2187 dev->mode_config.scaling_mode_property,
2188 DRM_MODE_SCALE_NONE);
eac4dff6 2189 }
108dc8e8 2190 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
8666c076 2191 drm_object_attach_property(&radeon_connector->base.base,
108dc8e8 2192 rdev->mode_info.audio_property,
e31fadd3 2193 RADEON_AUDIO_AUTO);
7403c515 2194 radeon_connector->audio = RADEON_AUDIO_AUTO;
8666c076 2195 }
643b1f56
AD		 2196 if (ASIC_IS_DCE5(rdev))
2197 drm_object_attach_property(&radeon_connector->base.base,
2198 rdev->mode_info.output_csc_property,
2199 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 2200 subpixel_order = SubPixelHorizontalRGB;
2201 connector->interlace_allowed = true;
2202 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
2203 connector->doublescan_allowed = true;
2204 else
2205 connector->doublescan_allowed = false;
2206 break;
2207 case DRM_MODE_CONNECTOR_DisplayPort:
2208 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2209 if (!radeon_dig_connector)
2210 goto failed;
2211 radeon_dig_connector->igp_lane_info = igp_lane_info;
2212 radeon_connector->con_priv = radeon_dig_connector;
eac4dff6 2213 if (i2c_bus->valid) {
eac4dff6 2214 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
af0e31ab 2215 if (radeon_connector->ddc_bus) {
496263bf 2216 has_aux = true;
af0e31ab
AP		 2217 ddc = &radeon_connector->ddc_bus->adapter;
2218 } else {
eac4dff6 2219 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab 2220 }
eac4dff6 2221 }
af0e31ab
AP		 2222 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2223 &radeon_dp_connector_funcs,
2224 connector_type,
2225 ddc);
2226 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
eac4dff6 2227 subpixel_order = SubPixelHorizontalRGB;
e35755fa 2228 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2229 rdev->mode_info.coherent_mode_property,
2230 1);
2231 if (ASIC_IS_AVIVO(rdev)) {
e35755fa 2232 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2233 rdev->mode_info.underscan_property,
2234 UNDERSCAN_OFF);
e35755fa 2235 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2236 rdev->mode_info.underscan_hborder_property,
2237 0);
e35755fa 2238 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2239 rdev->mode_info.underscan_vborder_property,
2240 0);
da997620
AD		 2241 drm_object_attach_property(&radeon_connector->base.base,
2242 rdev->mode_info.dither_property,
2243 RADEON_FMT_DITHER_DISABLE);
2244 drm_object_attach_property(&radeon_connector->base.base,
2245 dev->mode_config.scaling_mode_property,
2246 DRM_MODE_SCALE_NONE);
eac4dff6 2247 }
108dc8e8 2248 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
8666c076 2249 drm_object_attach_property(&radeon_connector->base.base,
108dc8e8 2250 rdev->mode_info.audio_property,
e31fadd3 2251 RADEON_AUDIO_AUTO);
7403c515 2252 radeon_connector->audio = RADEON_AUDIO_AUTO;
8666c076 2253 }
643b1f56
AD		 2254 if (ASIC_IS_DCE5(rdev))
2255 drm_object_attach_property(&radeon_connector->base.base,
2256 rdev->mode_info.output_csc_property,
2257 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 2258 connector->interlace_allowed = true;
2259 /* in theory with a DP to VGA converter... */
c49948f4 2260 connector->doublescan_allowed = false;
eac4dff6
AD		 2261 break;
2262 case DRM_MODE_CONNECTOR_eDP:
2263 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2264 if (!radeon_dig_connector)
2265 goto failed;
2266 radeon_dig_connector->igp_lane_info = igp_lane_info;
2267 radeon_connector->con_priv = radeon_dig_connector;
eac4dff6 2268 if (i2c_bus->valid) {
379dfc25 2269 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
af0e31ab 2270 if (radeon_connector->ddc_bus) {
496263bf 2271 has_aux = true;
af0e31ab
AP		 2272 ddc = &radeon_connector->ddc_bus->adapter;
2273 } else {
eac4dff6 2274 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab 2275 }
eac4dff6 2276 }
af0e31ab
AP		 2277 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2278 &radeon_edp_connector_funcs,
2279 connector_type,
2280 ddc);
2281 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
e35755fa 2282 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2283 dev->mode_config.scaling_mode_property,
2284 DRM_MODE_SCALE_FULLSCREEN);
2285 subpixel_order = SubPixelHorizontalRGB;
2286 connector->interlace_allowed = false;
2287 connector->doublescan_allowed = false;
2288 break;
2289 case DRM_MODE_CONNECTOR_SVIDEO:
2290 case DRM_MODE_CONNECTOR_Composite:
2291 case DRM_MODE_CONNECTOR_9PinDIN:
af0e31ab
AP		 2292 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2293 &radeon_tv_connector_funcs,
2294 connector_type,
2295 ddc);
eac4dff6
AD		 2296 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
2297 radeon_connector->dac_load_detect = true;
e35755fa 2298 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2299 rdev->mode_info.load_detect_property,
2300 1);
e35755fa 2301 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2302 rdev->mode_info.tv_std_property,
2303 radeon_atombios_get_tv_info(rdev));
2304 /* no HPD on analog connectors */
2305 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
2306 connector->interlace_allowed = false;
2307 connector->doublescan_allowed = false;
2308 break;
2309 case DRM_MODE_CONNECTOR_LVDS:
2310 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2311 if (!radeon_dig_connector)
2312 goto failed;
2313 radeon_dig_connector->igp_lane_info = igp_lane_info;
2314 radeon_connector->con_priv = radeon_dig_connector;
eac4dff6
AD		 2315 if (i2c_bus->valid) {
2316 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2317 if (!radeon_connector->ddc_bus)
2318 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab
AP		 2319 else
2320 ddc = &radeon_connector->ddc_bus->adapter;
eac4dff6 2321 }
af0e31ab
AP		 2322 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2323 &radeon_lvds_connector_funcs,
2324 connector_type,
2325 ddc);
2326 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
e35755fa 2327 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2328 dev->mode_config.scaling_mode_property,
2329 DRM_MODE_SCALE_FULLSCREEN);
2330 subpixel_order = SubPixelHorizontalRGB;
2331 connector->interlace_allowed = false;
2332 connector->doublescan_allowed = false;
2333 break;
771fe6b9 2334 }
771fe6b9
JG		 2335 }
2336
2581afcc 2337 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) {
14ff8d48
L		 2338 if (i2c_bus->valid) {
2339 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2340 DRM_CONNECTOR_POLL_DISCONNECT;
2341 }
eb1f8e4f
DA		 2342 } else
2343 connector->polled = DRM_CONNECTOR_POLL_HPD;
2344
771fe6b9 2345 connector->display_info.subpixel_order = subpixel_order;
34ea3d38 2346 drm_connector_register(connector);
496263bf
AD		 2347
2348 if (has_aux)
2349 radeon_dp_aux_init(radeon_connector);
2350
771fe6b9
JG		 2351 return;
2352
2353failed:
771fe6b9
JG		 2354 drm_connector_cleanup(connector);
2355 kfree(connector);
2356}
2357
2358void
2359radeon_add_legacy_connector(struct drm_device *dev,
2360 uint32_t connector_id,
2361 uint32_t supported_device,
2362 int connector_type,
b75fad06 2363 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 2364 uint16_t connector_object_id,
2365 struct radeon_hpd *hpd)
771fe6b9 2366{
445282db 2367 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 2368 struct drm_connector *connector;
2369 struct radeon_connector *radeon_connector;
af0e31ab 2370 struct i2c_adapter *ddc = NULL;
771fe6b9
JG		 2371 uint32_t subpixel_order = SubPixelNone;
2372
4ce001ab 2373 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
771fe6b9
JG		 2374 return;
2375
cf4c12f9
AD		 2376 /* if the user selected tv=0 don't try and add the connector */
2377 if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
2378 (connector_type == DRM_MODE_CONNECTOR_Composite) ||
2379 (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
2380 (radeon_tv == 0))
2381 return;
2382
771fe6b9
JG		 2383 /* see if we already added it */
2384 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2385 radeon_connector = to_radeon_connector(connector);
2386 if (radeon_connector->connector_id == connector_id) {
2387 radeon_connector->devices |= supported_device;
2388 return;
2389 }
2390 }
2391
2392 radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
2393 if (!radeon_connector)
2394 return;
2395
2396 connector = &radeon_connector->base;
2397
2398 radeon_connector->connector_id = connector_id;
2399 radeon_connector->devices = supported_device;
b75fad06 2400 radeon_connector->connector_object_id = connector_object_id;
eed45b30 2401 radeon_connector->hpd = *hpd;
bc1c4dc3 2402
771fe6b9
JG		 2403 switch (connector_type) {
2404 case DRM_MODE_CONNECTOR_VGA:
771fe6b9 2405 if (i2c_bus->valid) {
f376b94f 2406 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
771fe6b9 2407 if (!radeon_connector->ddc_bus)
a70882aa 2408 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab
AP		 2409 else
2410 ddc = &radeon_connector->ddc_bus->adapter;
771fe6b9 2411 }
af0e31ab
AP		 2412 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2413 &radeon_vga_connector_funcs,
2414 connector_type,
2415 ddc);
2416 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
35e4b7af 2417 radeon_connector->dac_load_detect = true;
e35755fa 2418 drm_object_attach_property(&radeon_connector->base.base,
445282db
DA		 2419 rdev->mode_info.load_detect_property,
2420 1);
2581afcc
AD		 2421 /* no HPD on analog connectors */
2422 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
c49948f4
AD		 2423 connector->interlace_allowed = true;
2424 connector->doublescan_allowed = true;
771fe6b9
JG		 2425 break;
2426 case DRM_MODE_CONNECTOR_DVIA:
771fe6b9 2427 if (i2c_bus->valid) {
f376b94f 2428 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
771fe6b9 2429 if (!radeon_connector->ddc_bus)
a70882aa 2430 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab
AP		 2431 else
2432 ddc = &radeon_connector->ddc_bus->adapter;
771fe6b9 2433 }
af0e31ab
AP		 2434 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2435 &radeon_vga_connector_funcs,
2436 connector_type,
2437 ddc);
2438 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
35e4b7af 2439 radeon_connector->dac_load_detect = true;
e35755fa 2440 drm_object_attach_property(&radeon_connector->base.base,
445282db
DA		 2441 rdev->mode_info.load_detect_property,
2442 1);
2581afcc
AD		 2443 /* no HPD on analog connectors */
2444 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
c49948f4
AD		 2445 connector->interlace_allowed = true;
2446 connector->doublescan_allowed = true;
771fe6b9
JG		 2447 break;
2448 case DRM_MODE_CONNECTOR_DVII:
2449 case DRM_MODE_CONNECTOR_DVID:
771fe6b9 2450 if (i2c_bus->valid) {
f376b94f 2451 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
771fe6b9 2452 if (!radeon_connector->ddc_bus)
a70882aa 2453 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab
AP		 2454 else
2455 ddc = &radeon_connector->ddc_bus->adapter;
68b3adb4 2456 }
af0e31ab
AP		 2457 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2458 &radeon_dvi_connector_funcs,
2459 connector_type,
2460 ddc);
2461 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
68b3adb4 2462 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
35e4b7af 2463 radeon_connector->dac_load_detect = true;
e35755fa 2464 drm_object_attach_property(&radeon_connector->base.base,
445282db
DA		 2465 rdev->mode_info.load_detect_property,
2466 1);
771fe6b9
JG		 2467 }
2468 subpixel_order = SubPixelHorizontalRGB;
c49948f4
AD		 2469 connector->interlace_allowed = true;
2470 if (connector_type == DRM_MODE_CONNECTOR_DVII)
2471 connector->doublescan_allowed = true;
2472 else
2473 connector->doublescan_allowed = false;
771fe6b9
JG		 2474 break;
2475 case DRM_MODE_CONNECTOR_SVIDEO:
2476 case DRM_MODE_CONNECTOR_Composite:
2477 case DRM_MODE_CONNECTOR_9PinDIN:
af0e31ab
AP		 2478 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2479 &radeon_tv_connector_funcs,
2480 connector_type,
2481 ddc);
cf4c12f9
AD		 2482 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
2483 radeon_connector->dac_load_detect = true;
2484 /* RS400,RC410,RS480 chipset seems to report a lot
2485 * of false positive on load detect, we haven't yet
2486 * found a way to make load detect reliable on those
2487 * chipset, thus just disable it for TV.
2488 */
2489 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480)
2490 radeon_connector->dac_load_detect = false;
e35755fa 2491 drm_object_attach_property(&radeon_connector->base.base,
cf4c12f9
AD		 2492 rdev->mode_info.load_detect_property,
2493 radeon_connector->dac_load_detect);
e35755fa 2494 drm_object_attach_property(&radeon_connector->base.base,
cf4c12f9
AD		 2495 rdev->mode_info.tv_std_property,
2496 radeon_combios_get_tv_info(rdev));
2497 /* no HPD on analog connectors */
2498 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
c49948f4
AD		 2499 connector->interlace_allowed = false;
2500 connector->doublescan_allowed = false;
771fe6b9
JG		 2501 break;
2502 case DRM_MODE_CONNECTOR_LVDS:
771fe6b9 2503 if (i2c_bus->valid) {
f376b94f 2504 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
771fe6b9 2505 if (!radeon_connector->ddc_bus)
a70882aa 2506 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
af0e31ab
AP		 2507 else
2508 ddc = &radeon_connector->ddc_bus->adapter;
771fe6b9 2509 }
af0e31ab
AP		 2510 drm_connector_init_with_ddc(dev, &radeon_connector->base,
2511 &radeon_lvds_connector_funcs,
2512 connector_type,
2513 ddc);
2514 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
e35755fa 2515 drm_object_attach_property(&radeon_connector->base.base,
445282db
DA		 2516 dev->mode_config.scaling_mode_property,
2517 DRM_MODE_SCALE_FULLSCREEN);
771fe6b9 2518 subpixel_order = SubPixelHorizontalRGB;
c49948f4
AD		 2519 connector->interlace_allowed = false;
2520 connector->doublescan_allowed = false;
771fe6b9
JG		 2521 break;
2522 }
2523
2581afcc 2524 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) {
14ff8d48
L		 2525 if (i2c_bus->valid) {
2526 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2527 DRM_CONNECTOR_POLL_DISCONNECT;
2528 }
eb1f8e4f
DA		 2529 } else
2530 connector->polled = DRM_CONNECTOR_POLL_HPD;
14ff8d48 2531
771fe6b9 2532 connector->display_info.subpixel_order = subpixel_order;
34ea3d38 2533 drm_connector_register(connector);
771fe6b9 2534}
Linux 6.x block layer and io_uring tree(s)