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drm/connector: Allow max possible encoders to attach to a connector
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_connectors.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
f9183127 26
760285e7
DH		 27#include <drm/drm_edid.h>
28#include <drm/drm_crtc_helper.h>
29#include <drm/drm_fb_helper.h>
9843ead0 30#include <drm/drm_dp_mst_helper.h>
fcd70cd3 31#include <drm/drm_probe_helper.h>
760285e7 32#include <drm/radeon_drm.h>
771fe6b9 33#include "radeon.h"
1a626b68 34#include "radeon_audio.h"
923f6848 35#include "atom.h"
771fe6b9 36
10ebc0bc 37#include <linux/pm_runtime.h>
47eb8f73 38#include <linux/vga_switcheroo.h>
10ebc0bc 39
9843ead0
DA		 40static int radeon_dp_handle_hpd(struct drm_connector *connector)
41{
42 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
43 int ret;
44
45 ret = radeon_dp_mst_check_status(radeon_connector);
46 if (ret == -EINVAL)
47 return 1;
48 return 0;
49}
d4877cf2
AD		 50void radeon_connector_hotplug(struct drm_connector *connector)
51{
52 struct drm_device *dev = connector->dev;
53 struct radeon_device *rdev = dev->dev_private;
54 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
55
9843ead0
DA		 56 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
57 struct radeon_connector_atom_dig *dig_connector =
58 radeon_connector->con_priv;
59
60 if (radeon_connector->is_mst_connector)
61 return;
62 if (dig_connector->is_mst) {
63 radeon_dp_handle_hpd(connector);
64 return;
65 }
66 }
cbac9543
AD		 67 /* bail if the connector does not have hpd pin, e.g.,
68 * VGA, TV, etc.
69 */
70 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE)
71 return;
72
1e85e1d0 73 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
d4877cf2 74
73104b5c 75 /* if the connector is already off, don't turn it back on */
6e9f798d 76 /* FIXME: This access isn't protected by any locks. */
73104b5c
AD		 77 if (connector->dpms != DRM_MODE_DPMS_ON)
78 return;
79
d5811e87
AD		 80 /* just deal with DP (not eDP) here. */
81 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
266dcba5
JG		 82 struct radeon_connector_atom_dig *dig_connector =
83 radeon_connector->con_priv;
7c3ed0fd 84
266dcba5
JG		 85 /* if existing sink type was not DP no need to retrain */
86 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
87 return;
88
89 /* first get sink type as it may be reset after (un)plug */
90 dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
91 /* don't do anything if sink is not display port, i.e.,
92 * passive dp->(dvi|hdmi) adaptor
93 */
2681bc79
MD		 94 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
95 radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&
96 radeon_dp_needs_link_train(radeon_connector)) {
97 /* Don't start link training before we have the DPCD */
98 if (!radeon_dp_getdpcd(radeon_connector))
99 return;
924f92bf 100
2681bc79
MD		 101 /* Turn the connector off and back on immediately, which
102 * will trigger link training
103 */
104 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
105 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
266dcba5 106 }
d4877cf2 107 }
d4877cf2
AD		 108}
109
445282db
DA		 110static void radeon_property_change_mode(struct drm_encoder *encoder)
111{
112 struct drm_crtc *crtc = encoder->crtc;
113
114 if (crtc && crtc->enabled) {
115 drm_crtc_helper_set_mode(crtc, &crtc->mode,
f4510a27 116 crtc->x, crtc->y, crtc->primary->fb);
445282db
DA		 117 }
118}
eccea792
AD		 119
120int radeon_get_monitor_bpc(struct drm_connector *connector)
121{
122 struct drm_device *dev = connector->dev;
123 struct radeon_device *rdev = dev->dev_private;
124 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
125 struct radeon_connector_atom_dig *dig_connector;
126 int bpc = 8;
ea292861 127 int mode_clock, max_tmds_clock;
eccea792
AD		 128
129 switch (connector->connector_type) {
130 case DRM_MODE_CONNECTOR_DVII:
131 case DRM_MODE_CONNECTOR_HDMIB:
132 if (radeon_connector->use_digital) {
377bd8a9 133 if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
eccea792
AD		 134 if (connector->display_info.bpc)
135 bpc = connector->display_info.bpc;
136 }
137 }
138 break;
139 case DRM_MODE_CONNECTOR_DVID:
140 case DRM_MODE_CONNECTOR_HDMIA:
377bd8a9 141 if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
eccea792
AD		 142 if (connector->display_info.bpc)
143 bpc = connector->display_info.bpc;
144 }
145 break;
146 case DRM_MODE_CONNECTOR_DisplayPort:
147 dig_connector = radeon_connector->con_priv;
148 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
149 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
377bd8a9 150 drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
eccea792
AD		 151 if (connector->display_info.bpc)
152 bpc = connector->display_info.bpc;
153 }
154 break;
155 case DRM_MODE_CONNECTOR_eDP:
156 case DRM_MODE_CONNECTOR_LVDS:
157 if (connector->display_info.bpc)
158 bpc = connector->display_info.bpc;
159 else if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
319d1e14 160 const struct drm_connector_helper_funcs *connector_funcs =
eccea792
AD		 161 connector->helper_private;
162 struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
163 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
164 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
165
166 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
167 bpc = 6;
168 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
169 bpc = 8;
170 }
171 break;
172 }
89b92339 173
377bd8a9 174 if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
89b92339
MK		 175 /* hdmi deep color only implemented on DCE4+ */
176 if ((bpc > 8) && !ASIC_IS_DCE4(rdev)) {
177 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 8 bpc.\n",
72082093 178 connector->name, bpc);
89b92339
MK		 179 bpc = 8;
180 }
181
182 /*
183 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
184 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
185 * 12 bpc is always supported on hdmi deep color sinks, as this is
186 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
187 */
188 if (bpc > 12) {
189 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
72082093 190 connector->name, bpc);
89b92339
MK		 191 bpc = 12;
192 }
ea292861
MK		 193
194 /* Any defined maximum tmds clock limit we must not exceed? */
2a272ca9 195 if (connector->display_info.max_tmds_clock > 0) {
ea292861
MK		 196 /* mode_clock is clock in kHz for mode to be modeset on this connector */
197 mode_clock = radeon_connector->pixelclock_for_modeset;
198
199 /* Maximum allowable input clock in kHz */
2a272ca9 200 max_tmds_clock = connector->display_info.max_tmds_clock;
ea292861
MK		 201
202 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
203 connector->name, mode_clock, max_tmds_clock);
204
205 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
206 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
207 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
208 (mode_clock * 5/4 <= max_tmds_clock))
209 bpc = 10;
210 else
211 bpc = 8;
212
213 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
214 connector->name, bpc);
215 }
216
217 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
218 bpc = 8;
219 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
220 connector->name, bpc);
221 }
222 }
9f51e2e0
MK		 223 else if (bpc > 8) {
224 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
225 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
226 connector->name);
227 bpc = 8;
228 }
89b92339
MK		 229 }
230
9f51e2e0
MK		 231 if ((radeon_deep_color == 0) && (bpc > 8)) {
232 DRM_DEBUG("%s: Deep color disabled. Set radeon module param deep_color=1 to enable.\n",
233 connector->name);
a624f429 234 bpc = 8;
9f51e2e0 235 }
a624f429 236
89b92339 237 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
72082093 238 connector->name, connector->display_info.bpc, bpc);
89b92339 239
eccea792
AD		 240 return bpc;
241}
242
771fe6b9
JG		 243static void
244radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status)
245{
246 struct drm_device *dev = connector->dev;
247 struct radeon_device *rdev = dev->dev_private;
7b71ca24
VS		 248 struct drm_encoder *best_encoder;
249 struct drm_encoder *encoder;
319d1e14 250 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
771fe6b9 251 bool connected;
771fe6b9
JG		 252
253 best_encoder = connector_funcs->best_encoder(connector);
254
62afb4ad 255 drm_connector_for_each_possible_encoder(connector, encoder) {
771fe6b9
JG		 256 if ((encoder == best_encoder) && (status == connector_status_connected))
257 connected = true;
258 else
259 connected = false;
260
261 if (rdev->is_atom_bios)
262 radeon_atombios_connected_scratch_regs(connector, encoder, connected);
263 else
264 radeon_combios_connected_scratch_regs(connector, encoder, connected);
771fe6b9
JG		 265 }
266}
267
1109ca09 268static struct drm_encoder *radeon_find_encoder(struct drm_connector *connector, int encoder_type)
445282db 269{
445282db 270 struct drm_encoder *encoder;
445282db 271
62afb4ad 272 drm_connector_for_each_possible_encoder(connector, encoder) {
445282db
DA		 273 if (encoder->encoder_type == encoder_type)
274 return encoder;
275 }
7b71ca24 276
445282db
DA		 277 return NULL;
278}
279
377bd8a9
AD		 280struct edid *radeon_connector_edid(struct drm_connector *connector)
281{
282 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
283 struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
284
285 if (radeon_connector->edid) {
286 return radeon_connector->edid;
287 } else if (edid_blob) {
288 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
289 if (edid)
290 radeon_connector->edid = edid;
291 }
292 return radeon_connector->edid;
293}
294
72a5c970
AD		 295static void radeon_connector_get_edid(struct drm_connector *connector)
296{
297 struct drm_device *dev = connector->dev;
298 struct radeon_device *rdev = dev->dev_private;
299 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
300
301 if (radeon_connector->edid)
302 return;
303
304 /* on hw with routers, select right port */
305 if (radeon_connector->router.ddc_valid)
306 radeon_router_select_ddc_port(radeon_connector);
307
308 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
309 ENCODER_OBJECT_ID_NONE) &&
310 radeon_connector->ddc_bus->has_aux) {
311 radeon_connector->edid = drm_get_edid(connector,
312 &radeon_connector->ddc_bus->aux.ddc);
313 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
314 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
315 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
316
317 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
318 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
319 radeon_connector->ddc_bus->has_aux)
320 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
321 &radeon_connector->ddc_bus->aux.ddc);
322 else if (radeon_connector->ddc_bus)
323 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
324 &radeon_connector->ddc_bus->adapter);
47eb8f73
LW		 325 } else if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC &&
326 connector->connector_type == DRM_MODE_CONNECTOR_LVDS &&
327 radeon_connector->ddc_bus) {
328 radeon_connector->edid = drm_get_edid_switcheroo(&radeon_connector->base,
329 &radeon_connector->ddc_bus->adapter);
72a5c970
AD		 330 } else if (radeon_connector->ddc_bus) {
331 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
332 &radeon_connector->ddc_bus->adapter);
333 }
334
335 if (!radeon_connector->edid) {
13485794
AD		 336 /* don't fetch the edid from the vbios if ddc fails and runpm is
337 * enabled so we report disconnected.
338 */
339 if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
340 return;
341
72a5c970
AD		 342 if (rdev->is_atom_bios) {
343 /* some laptops provide a hardcoded edid in rom for LCDs */
344 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
345 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
346 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
347 } else {
348 /* some servers provide a hardcoded edid in rom for KVMs */
349 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
350 }
351 }
352}
353
354static void radeon_connector_free_edid(struct drm_connector *connector)
355{
356 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
357
358 if (radeon_connector->edid) {
359 kfree(radeon_connector->edid);
360 radeon_connector->edid = NULL;
361 }
362}
363
364static int radeon_ddc_get_modes(struct drm_connector *connector)
365{
366 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
367 int ret;
368
369 if (radeon_connector->edid) {
c555f023 370 drm_connector_update_edid_property(connector, radeon_connector->edid);
72a5c970 371 ret = drm_add_edid_modes(connector, radeon_connector->edid);
72a5c970
AD		 372 return ret;
373 }
c555f023 374 drm_connector_update_edid_property(connector, NULL);
72a5c970
AD		 375 return 0;
376}
377
1109ca09 378static struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector)
771fe6b9 379{
7b71ca24 380 struct drm_encoder *encoder;
7b71ca24
VS		 381
382 /* pick the first one */
62afb4ad 383 drm_connector_for_each_possible_encoder(connector, encoder)
7b71ca24
VS		 384 return encoder;
385
771fe6b9
JG		 386 return NULL;
387}
388
da997620
AD		 389static void radeon_get_native_mode(struct drm_connector *connector)
390{
391 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
392 struct radeon_encoder *radeon_encoder;
393
394 if (encoder == NULL)
395 return;
396
397 radeon_encoder = to_radeon_encoder(encoder);
398
399 if (!list_empty(&connector->probed_modes)) {
400 struct drm_display_mode *preferred_mode =
401 list_first_entry(&connector->probed_modes,
402 struct drm_display_mode, head);
403
404 radeon_encoder->native_mode = *preferred_mode;
405 } else {
406 radeon_encoder->native_mode.clock = 0;
407 }
408}
409
4ce001ab
DA		 410/*
411 * radeon_connector_analog_encoder_conflict_solve
412 * - search for other connectors sharing this encoder
413 * if priority is true, then set them disconnected if this is connected
414 * if priority is false, set us disconnected if they are connected
415 */
416static enum drm_connector_status
417radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
418 struct drm_encoder *encoder,
419 enum drm_connector_status current_status,
420 bool priority)
421{
422 struct drm_device *dev = connector->dev;
423 struct drm_connector *conflict;
08d07511 424 struct radeon_connector *radeon_conflict;
4ce001ab
DA		 425
426 list_for_each_entry(conflict, &dev->mode_config.connector_list, head) {
7b71ca24 427 struct drm_encoder *enc;
7b71ca24 428
4ce001ab
DA		 429 if (conflict == connector)
430 continue;
431
08d07511 432 radeon_conflict = to_radeon_connector(conflict);
4ce001ab 433
62afb4ad 434 drm_connector_for_each_possible_encoder(conflict, enc) {
4ce001ab 435 /* if the IDs match */
7b71ca24 436 if (enc == encoder) {
4ce001ab
DA		 437 if (conflict->status != connector_status_connected)
438 continue;
08d07511
AD		 439
440 if (radeon_conflict->use_digital)
441 continue;
4ce001ab
DA		 442
443 if (priority == true) {
72082093
JN		 444 DRM_DEBUG_KMS("1: conflicting encoders switching off %s\n",
445 conflict->name);
446 DRM_DEBUG_KMS("in favor of %s\n",
447 connector->name);
4ce001ab
DA		 448 conflict->status = connector_status_disconnected;
449 radeon_connector_update_scratch_regs(conflict, connector_status_disconnected);
450 } else {
72082093
JN		 451 DRM_DEBUG_KMS("2: conflicting encoders switching off %s\n",
452 connector->name);
453 DRM_DEBUG_KMS("in favor of %s\n",
454 conflict->name);
4ce001ab
DA		 455 current_status = connector_status_disconnected;
456 }
457 break;
458 }
459 }
460 }
461 return current_status;
462
463}
464
771fe6b9
JG		 465static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder)
466{
467 struct drm_device *dev = encoder->dev;
468 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
469 struct drm_display_mode *mode = NULL;
de2103e4 470 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
771fe6b9 471
de2103e4
AD		 472 if (native_mode->hdisplay != 0 &&
473 native_mode->vdisplay != 0 &&
474 native_mode->clock != 0) {
fb06ca8f 475 mode = drm_mode_duplicate(dev, native_mode);
771fe6b9
JG		 476 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
477 drm_mode_set_name(mode);
478
d9fdaafb 479 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
d2efdf6d
AD		 480 } else if (native_mode->hdisplay != 0 &&
481 native_mode->vdisplay != 0) {
482 /* mac laptops without an edid */
483 /* Note that this is not necessarily the exact panel mode,
484 * but an approximation based on the cvt formula. For these
485 * systems we should ideally read the mode info out of the
486 * registers or add a mode table, but this works and is much
487 * simpler.
488 */
489 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
490 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
d9fdaafb 491 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
771fe6b9
JG		 492 }
493 return mode;
494}
495
923f6848
AD		 496static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector)
497{
498 struct drm_device *dev = encoder->dev;
499 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
500 struct drm_display_mode *mode = NULL;
de2103e4 501 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
923f6848
AD		 502 int i;
503 struct mode_size {
504 int w;
505 int h;
506 } common_modes[17] = {
507 { 640, 480},
508 { 720, 480},
509 { 800, 600},
510 { 848, 480},
511 {1024, 768},
512 {1152, 768},
513 {1280, 720},
514 {1280, 800},
515 {1280, 854},
516 {1280, 960},
517 {1280, 1024},
518 {1440, 900},
519 {1400, 1050},
520 {1680, 1050},
521 {1600, 1200},
522 {1920, 1080},
523 {1920, 1200}
524 };
525
526 for (i = 0; i < 17; i++) {
dfdd6467
AD		 527 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
528 if (common_modes[i].w > 1024 ||
529 common_modes[i].h > 768)
530 continue;
531 }
923f6848 532 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
de2103e4
AD		 533 if (common_modes[i].w > native_mode->hdisplay ||
534 common_modes[i].h > native_mode->vdisplay ||
535 (common_modes[i].w == native_mode->hdisplay &&
536 common_modes[i].h == native_mode->vdisplay))
923f6848
AD		 537 continue;
538 }
539 if (common_modes[i].w < 320 || common_modes[i].h < 200)
540 continue;
541
d50ba256 542 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
923f6848
AD		 543 drm_mode_probed_add(connector, mode);
544 }
545}
546
1109ca09 547static int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property,
771fe6b9
JG		 548 uint64_t val)
549{
445282db
DA		 550 struct drm_device *dev = connector->dev;
551 struct radeon_device *rdev = dev->dev_private;
552 struct drm_encoder *encoder;
553 struct radeon_encoder *radeon_encoder;
554
555 if (property == rdev->mode_info.coherent_mode_property) {
556 struct radeon_encoder_atom_dig *dig;
ce227c41 557 bool new_coherent_mode;
445282db
DA		 558
559 /* need to find digital encoder on connector */
560 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
561 if (!encoder)
562 return 0;
563
564 radeon_encoder = to_radeon_encoder(encoder);
565
566 if (!radeon_encoder->enc_priv)
567 return 0;
568
569 dig = radeon_encoder->enc_priv;
ce227c41
DA		 570 new_coherent_mode = val ? true : false;
571 if (dig->coherent_mode != new_coherent_mode) {
572 dig->coherent_mode = new_coherent_mode;
573 radeon_property_change_mode(&radeon_encoder->base);
574 }
445282db
DA		 575 }
576
8666c076
AD		 577 if (property == rdev->mode_info.audio_property) {
578 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
579 /* need to find digital encoder on connector */
580 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
581 if (!encoder)
582 return 0;
583
584 radeon_encoder = to_radeon_encoder(encoder);
585
586 if (radeon_connector->audio != val) {
587 radeon_connector->audio = val;
588 radeon_property_change_mode(&radeon_encoder->base);
589 }
590 }
591
6214bb74
AD		 592 if (property == rdev->mode_info.dither_property) {
593 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
594 /* need to find digital encoder on connector */
595 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
596 if (!encoder)
597 return 0;
598
599 radeon_encoder = to_radeon_encoder(encoder);
600
601 if (radeon_connector->dither != val) {
602 radeon_connector->dither = val;
603 radeon_property_change_mode(&radeon_encoder->base);
604 }
605 }
606
5b1714d3
AD		 607 if (property == rdev->mode_info.underscan_property) {
608 /* need to find digital encoder on connector */
609 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
610 if (!encoder)
611 return 0;
612
613 radeon_encoder = to_radeon_encoder(encoder);
614
615 if (radeon_encoder->underscan_type != val) {
616 radeon_encoder->underscan_type = val;
617 radeon_property_change_mode(&radeon_encoder->base);
618 }
619 }
620
5bccf5e3
MG		 621 if (property == rdev->mode_info.underscan_hborder_property) {
622 /* need to find digital encoder on connector */
623 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
624 if (!encoder)
625 return 0;
626
627 radeon_encoder = to_radeon_encoder(encoder);
628
629 if (radeon_encoder->underscan_hborder != val) {
630 radeon_encoder->underscan_hborder = val;
631 radeon_property_change_mode(&radeon_encoder->base);
632 }
633 }
634
635 if (property == rdev->mode_info.underscan_vborder_property) {
636 /* need to find digital encoder on connector */
637 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
638 if (!encoder)
639 return 0;
640
641 radeon_encoder = to_radeon_encoder(encoder);
642
643 if (radeon_encoder->underscan_vborder != val) {
644 radeon_encoder->underscan_vborder = val;
645 radeon_property_change_mode(&radeon_encoder->base);
646 }
647 }
648
445282db
DA		 649 if (property == rdev->mode_info.tv_std_property) {
650 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC);
651 if (!encoder) {
652 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_DAC);
653 }
654
655 if (!encoder)
656 return 0;
657
658 radeon_encoder = to_radeon_encoder(encoder);
659 if (!radeon_encoder->enc_priv)
660 return 0;
643acacf 661 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) {
445282db
DA		 662 struct radeon_encoder_atom_dac *dac_int;
663 dac_int = radeon_encoder->enc_priv;
664 dac_int->tv_std = val;
665 } else {
666 struct radeon_encoder_tv_dac *dac_int;
667 dac_int = radeon_encoder->enc_priv;
668 dac_int->tv_std = val;
669 }
670 radeon_property_change_mode(&radeon_encoder->base);
671 }
672
673 if (property == rdev->mode_info.load_detect_property) {
674 struct radeon_connector *radeon_connector =
675 to_radeon_connector(connector);
676
677 if (val == 0)
678 radeon_connector->dac_load_detect = false;
679 else
680 radeon_connector->dac_load_detect = true;
681 }
682
683 if (property == rdev->mode_info.tmds_pll_property) {
684 struct radeon_encoder_int_tmds *tmds = NULL;
685 bool ret = false;
686 /* need to find digital encoder on connector */
687 encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
688 if (!encoder)
689 return 0;
690
691 radeon_encoder = to_radeon_encoder(encoder);
692
693 tmds = radeon_encoder->enc_priv;
694 if (!tmds)
695 return 0;
696
697 if (val == 0) {
698 if (rdev->is_atom_bios)
699 ret = radeon_atombios_get_tmds_info(radeon_encoder, tmds);
700 else
701 ret = radeon_legacy_get_tmds_info_from_combios(radeon_encoder, tmds);
702 }
703 if (val == 1 || ret == false) {
704 radeon_legacy_get_tmds_info_from_table(radeon_encoder, tmds);
705 }
706 radeon_property_change_mode(&radeon_encoder->base);
707 }
708
da997620
AD		 709 if (property == dev->mode_config.scaling_mode_property) {
710 enum radeon_rmx_type rmx_type;
711
712 if (connector->encoder)
713 radeon_encoder = to_radeon_encoder(connector->encoder);
714 else {
319d1e14 715 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
da997620
AD		 716 radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
717 }
718
719 switch (val) {
720 default:
721 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
722 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
723 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
724 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
725 }
726 if (radeon_encoder->rmx_type == rmx_type)
727 return 0;
728
729 if ((rmx_type != DRM_MODE_SCALE_NONE) &&
730 (radeon_encoder->native_mode.clock == 0))
731 return 0;
732
733 radeon_encoder->rmx_type = rmx_type;
734
735 radeon_property_change_mode(&radeon_encoder->base);
736 }
737
643b1f56
AD		 738 if (property == rdev->mode_info.output_csc_property) {
739 if (connector->encoder)
740 radeon_encoder = to_radeon_encoder(connector->encoder);
741 else {
16bb079e 742 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
643b1f56
AD		 743 radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
744 }
745
746 if (radeon_encoder->output_csc == val)
747 return 0;
748
749 radeon_encoder->output_csc = val;
750
751 if (connector->encoder->crtc) {
752 struct drm_crtc *crtc = connector->encoder->crtc;
643b1f56
AD		 753 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
754
755 radeon_crtc->output_csc = radeon_encoder->output_csc;
756
42585395
PR		 757 /*
758 * Our .gamma_set assumes the .gamma_store has been
759 * prefilled and don't care about its arguments.
760 */
761 crtc->funcs->gamma_set(crtc, NULL, NULL, NULL, 0, NULL);
643b1f56
AD		 762 }
763 }
764
771fe6b9
JG		 765 return 0;
766}
767
8dfaa8a7
MD		 768static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
769 struct drm_connector *connector)
770{
771 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
de2103e4 772 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
13bb9430
MG		 773 struct drm_display_mode *t, *mode;
774
775 /* If the EDID preferred mode doesn't match the native mode, use it */
776 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
777 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
778 if (mode->hdisplay != native_mode->hdisplay ||
779 mode->vdisplay != native_mode->vdisplay)
780 memcpy(native_mode, mode, sizeof(*mode));
781 }
782 }
8dfaa8a7
MD		 783
784 /* Try to get native mode details from EDID if necessary */
de2103e4 785 if (!native_mode->clock) {
8dfaa8a7 786 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
de2103e4
AD		 787 if (mode->hdisplay == native_mode->hdisplay &&
788 mode->vdisplay == native_mode->vdisplay) {
789 *native_mode = *mode;
790 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
c5d46b4e 791 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
8dfaa8a7
MD		 792 break;
793 }
794 }
795 }
13bb9430 796
de2103e4 797 if (!native_mode->clock) {
c5d46b4e 798 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
8dfaa8a7
MD		 799 radeon_encoder->rmx_type = RMX_OFF;
800 }
801}
771fe6b9
JG		 802
803static int radeon_lvds_get_modes(struct drm_connector *connector)
804{
771fe6b9
JG		 805 struct drm_encoder *encoder;
806 int ret = 0;
807 struct drm_display_mode *mode;
808
72a5c970
AD		 809 radeon_connector_get_edid(connector);
810 ret = radeon_ddc_get_modes(connector);
811 if (ret > 0) {
812 encoder = radeon_best_single_encoder(connector);
813 if (encoder) {
814 radeon_fixup_lvds_native_mode(encoder, connector);
815 /* add scaled modes */
816 radeon_add_common_modes(encoder, connector);
771fe6b9 817 }
72a5c970 818 return ret;
771fe6b9
JG		 819 }
820
821 encoder = radeon_best_single_encoder(connector);
822 if (!encoder)
823 return 0;
824
825 /* we have no EDID modes */
826 mode = radeon_fp_native_mode(encoder);
827 if (mode) {
828 ret = 1;
829 drm_mode_probed_add(connector, mode);
7a868e18
AD		 830 /* add the width/height from vbios tables if available */
831 connector->display_info.width_mm = mode->width_mm;
832 connector->display_info.height_mm = mode->height_mm;
7747b713
AD		 833 /* add scaled modes */
834 radeon_add_common_modes(encoder, connector);
771fe6b9 835 }
923f6848 836
771fe6b9
JG		 837 return ret;
838}
839
7a47f20e 840static enum drm_mode_status radeon_lvds_mode_valid(struct drm_connector *connector,
771fe6b9
JG		 841 struct drm_display_mode *mode)
842{
a3fa6320
AD		 843 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
844
845 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
846 return MODE_PANEL;
847
848 if (encoder) {
849 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
850 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
851
852 /* AVIVO hardware supports downscaling modes larger than the panel
853 * to the panel size, but I'm not sure this is desirable.
854 */
855 if ((mode->hdisplay > native_mode->hdisplay) ||
856 (mode->vdisplay > native_mode->vdisplay))
857 return MODE_PANEL;
858
859 /* if scaling is disabled, block non-native modes */
860 if (radeon_encoder->rmx_type == RMX_OFF) {
861 if ((mode->hdisplay != native_mode->hdisplay) ||
862 (mode->vdisplay != native_mode->vdisplay))
863 return MODE_PANEL;
864 }
865 }
866
771fe6b9
JG		 867 return MODE_OK;
868}
869
7b334fcb 870static enum drm_connector_status
930a9e28 871radeon_lvds_detect(struct drm_connector *connector, bool force)
771fe6b9 872{
13485794
AD		 873 struct drm_device *dev = connector->dev;
874 struct radeon_device *rdev = dev->dev_private;
0549a061 875 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2ffb8429 876 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
0549a061 877 enum drm_connector_status ret = connector_status_disconnected;
10ebc0bc
DA		 878 int r;
879
15734fef
LW		 880 if (!drm_kms_helper_is_poll_worker()) {
881 r = pm_runtime_get_sync(connector->dev->dev);
882 if (r < 0)
883 return connector_status_disconnected;
884 }
2ffb8429
AD		 885
886 if (encoder) {
887 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
de2103e4 888 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
2ffb8429
AD		 889
890 /* check if panel is valid */
de2103e4 891 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
2ffb8429 892 ret = connector_status_connected;
13485794
AD		 893 /* don't fetch the edid from the vbios if ddc fails and runpm is
894 * enabled so we report disconnected.
895 */
896 if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
897 ret = connector_status_disconnected;
2ffb8429 898 }
0549a061
AD		 899
900 /* check for edid as well */
72a5c970 901 radeon_connector_get_edid(connector);
0294cf4f
AD		 902 if (radeon_connector->edid)
903 ret = connector_status_connected;
771fe6b9 904 /* check acpi lid status ??? */
2ffb8429 905
771fe6b9 906 radeon_connector_update_scratch_regs(connector, ret);
15734fef
LW		 907
908 if (!drm_kms_helper_is_poll_worker()) {
909 pm_runtime_mark_last_busy(connector->dev->dev);
910 pm_runtime_put_autosuspend(connector->dev->dev);
911 }
912
771fe6b9
JG		 913 return ret;
914}
915
b0c80bd5
AD		 916static void radeon_connector_unregister(struct drm_connector *connector)
917{
918 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
919
0a6e2105 920 if (radeon_connector->ddc_bus && radeon_connector->ddc_bus->has_aux) {
b0c80bd5
AD		 921 drm_dp_aux_unregister(&radeon_connector->ddc_bus->aux);
922 radeon_connector->ddc_bus->has_aux = false;
923 }
924}
925
771fe6b9
JG		 926static void radeon_connector_destroy(struct drm_connector *connector)
927{
928 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
929
72a5c970 930 radeon_connector_free_edid(connector);
771fe6b9 931 kfree(radeon_connector->con_priv);
34ea3d38 932 drm_connector_unregister(connector);
771fe6b9
JG		 933 drm_connector_cleanup(connector);
934 kfree(connector);
935}
936
445282db
DA		 937static int radeon_lvds_set_property(struct drm_connector *connector,
938 struct drm_property *property,
939 uint64_t value)
940{
941 struct drm_device *dev = connector->dev;
942 struct radeon_encoder *radeon_encoder;
943 enum radeon_rmx_type rmx_type;
944
d9fdaafb 945 DRM_DEBUG_KMS("\n");
445282db
DA		 946 if (property != dev->mode_config.scaling_mode_property)
947 return 0;
948
949 if (connector->encoder)
950 radeon_encoder = to_radeon_encoder(connector->encoder);
951 else {
319d1e14 952 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
445282db
DA		 953 radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector));
954 }
955
956 switch (value) {
957 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
958 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
959 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
960 default:
961 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
962 }
963 if (radeon_encoder->rmx_type == rmx_type)
964 return 0;
965
966 radeon_encoder->rmx_type = rmx_type;
967
968 radeon_property_change_mode(&radeon_encoder->base);
969 return 0;
970}
971
972
1109ca09 973static const struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = {
771fe6b9
JG		 974 .get_modes = radeon_lvds_get_modes,
975 .mode_valid = radeon_lvds_mode_valid,
976 .best_encoder = radeon_best_single_encoder,
977};
978
1109ca09 979static const struct drm_connector_funcs radeon_lvds_connector_funcs = {
771fe6b9
JG		 980 .dpms = drm_helper_connector_dpms,
981 .detect = radeon_lvds_detect,
982 .fill_modes = drm_helper_probe_single_connector_modes,
b0c80bd5 983 .early_unregister = radeon_connector_unregister,
771fe6b9 984 .destroy = radeon_connector_destroy,
445282db 985 .set_property = radeon_lvds_set_property,
771fe6b9
JG		 986};
987
988static int radeon_vga_get_modes(struct drm_connector *connector)
989{
771fe6b9
JG		 990 int ret;
991
72a5c970
AD		 992 radeon_connector_get_edid(connector);
993 ret = radeon_ddc_get_modes(connector);
771fe6b9 994
da997620
AD		 995 radeon_get_native_mode(connector);
996
771fe6b9
JG		 997 return ret;
998}
999
7a47f20e 1000static enum drm_mode_status radeon_vga_mode_valid(struct drm_connector *connector,
771fe6b9
JG		 1001 struct drm_display_mode *mode)
1002{
b20f9bef
AD		 1003 struct drm_device *dev = connector->dev;
1004 struct radeon_device *rdev = dev->dev_private;
1005
a3fa6320 1006 /* XXX check mode bandwidth */
b20f9bef
AD		 1007
1008 if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
1009 return MODE_CLOCK_HIGH;
1010
771fe6b9
JG		 1011 return MODE_OK;
1012}
1013
7b334fcb 1014static enum drm_connector_status
930a9e28 1015radeon_vga_detect(struct drm_connector *connector, bool force)
771fe6b9 1016{
fafcf94e
AD		 1017 struct drm_device *dev = connector->dev;
1018 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1019 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1020 struct drm_encoder *encoder;
319d1e14 1021 const struct drm_encoder_helper_funcs *encoder_funcs;
4b9d2a21 1022 bool dret = false;
771fe6b9 1023 enum drm_connector_status ret = connector_status_disconnected;
10ebc0bc
DA		 1024 int r;
1025
15734fef
LW		 1026 if (!drm_kms_helper_is_poll_worker()) {
1027 r = pm_runtime_get_sync(connector->dev->dev);
1028 if (r < 0)
1029 return connector_status_disconnected;
1030 }
771fe6b9 1031
4ce001ab
DA		 1032 encoder = radeon_best_single_encoder(connector);
1033 if (!encoder)
1034 ret = connector_status_disconnected;
1035
eb6b6d7c 1036 if (radeon_connector->ddc_bus)
0a9069d3 1037 dret = radeon_ddc_probe(radeon_connector, false);
0294cf4f 1038 if (dret) {
d0d0a225 1039 radeon_connector->detected_by_load = false;
72a5c970
AD		 1040 radeon_connector_free_edid(connector);
1041 radeon_connector_get_edid(connector);
0294cf4f
AD		 1042
1043 if (!radeon_connector->edid) {
f82f5f3a 1044 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
72082093 1045 connector->name);
f82f5f3a 1046 ret = connector_status_connected;
0294cf4f 1047 } else {
72a5c970
AD		 1048 radeon_connector->use_digital =
1049 !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
0294cf4f
AD		 1050
1051 /* some oems have boards with separate digital and analog connectors
1052 * with a shared ddc line (often vga + hdmi)
1053 */
1054 if (radeon_connector->use_digital && radeon_connector->shared_ddc) {
72a5c970 1055 radeon_connector_free_edid(connector);
0294cf4f 1056 ret = connector_status_disconnected;
72a5c970 1057 } else {
0294cf4f 1058 ret = connector_status_connected;
72a5c970 1059 }
0294cf4f
AD		 1060 }
1061 } else {
c3cceedd
DA		 1062
1063 /* if we aren't forcing don't do destructive polling */
d0d0a225
AD		 1064 if (!force) {
1065 /* only return the previous status if we last
1066 * detected a monitor via load.
1067 */
1068 if (radeon_connector->detected_by_load)
10ebc0bc
DA		 1069 ret = connector->status;
1070 goto out;
d0d0a225 1071 }
c3cceedd 1072
d8a7f792 1073 if (radeon_connector->dac_load_detect && encoder) {
445282db
DA		 1074 encoder_funcs = encoder->helper_private;
1075 ret = encoder_funcs->detect(encoder, connector);
34076446 1076 if (ret != connector_status_disconnected)
d0d0a225 1077 radeon_connector->detected_by_load = true;
445282db 1078 }
771fe6b9
JG		 1079 }
1080
4ce001ab
DA		 1081 if (ret == connector_status_connected)
1082 ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
fafcf94e
AD		 1083
1084 /* RN50 and some RV100 asics in servers often have a hardcoded EDID in the
1085 * vbios to deal with KVMs. If we have one and are not able to detect a monitor
1086 * by other means, assume the CRT is connected and use that EDID.
1087 */
1088 if ((!rdev->is_atom_bios) &&
1089 (ret == connector_status_disconnected) &&
1090 rdev->mode_info.bios_hardcoded_edid_size) {
1091 ret = connector_status_connected;
1092 }
1093
771fe6b9 1094 radeon_connector_update_scratch_regs(connector, ret);
10ebc0bc
DA		 1095
1096out:
15734fef
LW		 1097 if (!drm_kms_helper_is_poll_worker()) {
1098 pm_runtime_mark_last_busy(connector->dev->dev);
1099 pm_runtime_put_autosuspend(connector->dev->dev);
1100 }
10ebc0bc 1101
771fe6b9
JG		 1102 return ret;
1103}
1104
1109ca09 1105static const struct drm_connector_helper_funcs radeon_vga_connector_helper_funcs = {
771fe6b9
JG		 1106 .get_modes = radeon_vga_get_modes,
1107 .mode_valid = radeon_vga_mode_valid,
1108 .best_encoder = radeon_best_single_encoder,
1109};
1110
1109ca09 1111static const struct drm_connector_funcs radeon_vga_connector_funcs = {
771fe6b9
JG		 1112 .dpms = drm_helper_connector_dpms,
1113 .detect = radeon_vga_detect,
1114 .fill_modes = drm_helper_probe_single_connector_modes,
b0c80bd5 1115 .early_unregister = radeon_connector_unregister,
771fe6b9
JG		 1116 .destroy = radeon_connector_destroy,
1117 .set_property = radeon_connector_set_property,
1118};
1119
4ce001ab
DA		 1120static int radeon_tv_get_modes(struct drm_connector *connector)
1121{
1122 struct drm_device *dev = connector->dev;
923f6848 1123 struct radeon_device *rdev = dev->dev_private;
4ce001ab 1124 struct drm_display_mode *tv_mode;
923f6848 1125 struct drm_encoder *encoder;
4ce001ab 1126
923f6848
AD		 1127 encoder = radeon_best_single_encoder(connector);
1128 if (!encoder)
1129 return 0;
4ce001ab 1130
923f6848
AD		 1131 /* avivo chips can scale any mode */
1132 if (rdev->family >= CHIP_RS600)
1133 /* add scaled modes */
1134 radeon_add_common_modes(encoder, connector);
1135 else {
1136 /* only 800x600 is supported right now on pre-avivo chips */
d50ba256 1137 tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false, false);
923f6848
AD		 1138 tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
1139 drm_mode_probed_add(connector, tv_mode);
1140 }
4ce001ab
DA		 1141 return 1;
1142}
1143
7a47f20e 1144static enum drm_mode_status radeon_tv_mode_valid(struct drm_connector *connector,
4ce001ab
DA		 1145 struct drm_display_mode *mode)
1146{
a3fa6320
AD		 1147 if ((mode->hdisplay > 1024) || (mode->vdisplay > 768))
1148 return MODE_CLOCK_RANGE;
4ce001ab
DA		 1149 return MODE_OK;
1150}
1151
7b334fcb 1152static enum drm_connector_status
930a9e28 1153radeon_tv_detect(struct drm_connector *connector, bool force)
4ce001ab
DA		 1154{
1155 struct drm_encoder *encoder;
319d1e14 1156 const struct drm_encoder_helper_funcs *encoder_funcs;
445282db
DA		 1157 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1158 enum drm_connector_status ret = connector_status_disconnected;
10ebc0bc 1159 int r;
445282db
DA		 1160
1161 if (!radeon_connector->dac_load_detect)
1162 return ret;
4ce001ab 1163
15734fef
LW		 1164 if (!drm_kms_helper_is_poll_worker()) {
1165 r = pm_runtime_get_sync(connector->dev->dev);
1166 if (r < 0)
1167 return connector_status_disconnected;
1168 }
10ebc0bc 1169
4ce001ab
DA		 1170 encoder = radeon_best_single_encoder(connector);
1171 if (!encoder)
1172 ret = connector_status_disconnected;
1173 else {
1174 encoder_funcs = encoder->helper_private;
1175 ret = encoder_funcs->detect(encoder, connector);
1176 }
1177 if (ret == connector_status_connected)
1178 ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false);
1179 radeon_connector_update_scratch_regs(connector, ret);
15734fef
LW		 1180
1181 if (!drm_kms_helper_is_poll_worker()) {
1182 pm_runtime_mark_last_busy(connector->dev->dev);
1183 pm_runtime_put_autosuspend(connector->dev->dev);
1184 }
1185
4ce001ab
DA		 1186 return ret;
1187}
1188
1109ca09 1189static const struct drm_connector_helper_funcs radeon_tv_connector_helper_funcs = {
4ce001ab
DA		 1190 .get_modes = radeon_tv_get_modes,
1191 .mode_valid = radeon_tv_mode_valid,
1192 .best_encoder = radeon_best_single_encoder,
1193};
1194
1109ca09 1195static const struct drm_connector_funcs radeon_tv_connector_funcs = {
4ce001ab
DA		 1196 .dpms = drm_helper_connector_dpms,
1197 .detect = radeon_tv_detect,
1198 .fill_modes = drm_helper_probe_single_connector_modes,
b0c80bd5 1199 .early_unregister = radeon_connector_unregister,
4ce001ab
DA		 1200 .destroy = radeon_connector_destroy,
1201 .set_property = radeon_connector_set_property,
1202};
1203
11fe1266
TU		 1204static bool radeon_check_hpd_status_unchanged(struct drm_connector *connector)
1205{
1206 struct drm_device *dev = connector->dev;
1207 struct radeon_device *rdev = dev->dev_private;
1208 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1209 enum drm_connector_status status;
1210
1211 /* We only trust HPD on R600 and newer ASICS. */
1212 if (rdev->family >= CHIP_R600
1213 && radeon_connector->hpd.hpd != RADEON_HPD_NONE) {
1214 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1215 status = connector_status_connected;
1216 else
1217 status = connector_status_disconnected;
1218 if (connector->status == status)
1219 return true;
1220 }
1221
1222 return false;
1223}
1224
4ce001ab
DA		 1225/*
1226 * DVI is complicated
1227 * Do a DDC probe, if DDC probe passes, get the full EDID so
1228 * we can do analog/digital monitor detection at this point.
1229 * If the monitor is an analog monitor or we got no DDC,
1230 * we need to find the DAC encoder object for this connector.
1231 * If we got no DDC, we do load detection on the DAC encoder object.
1232 * If we got analog DDC or load detection passes on the DAC encoder
1233 * we have to check if this analog encoder is shared with anyone else (TV)
1234 * if its shared we have to set the other connector to disconnected.
1235 */
7b334fcb 1236static enum drm_connector_status
930a9e28 1237radeon_dvi_detect(struct drm_connector *connector, bool force)
771fe6b9 1238{
fafcf94e
AD		 1239 struct drm_device *dev = connector->dev;
1240 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1241 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
4ce001ab 1242 struct drm_encoder *encoder = NULL;
319d1e14 1243 const struct drm_encoder_helper_funcs *encoder_funcs;
7b71ca24 1244 int r;
771fe6b9 1245 enum drm_connector_status ret = connector_status_disconnected;
fc87f13b 1246 bool dret = false, broken_edid = false;
771fe6b9 1247
15734fef
LW		 1248 if (!drm_kms_helper_is_poll_worker()) {
1249 r = pm_runtime_get_sync(connector->dev->dev);
1250 if (r < 0)
1251 return connector_status_disconnected;
1252 }
10ebc0bc 1253
cb5d4166
L		 1254 if (radeon_connector->detected_hpd_without_ddc) {
1255 force = true;
1256 radeon_connector->detected_hpd_without_ddc = false;
1257 }
1258
10ebc0bc
DA		 1259 if (!force && radeon_check_hpd_status_unchanged(connector)) {
1260 ret = connector->status;
1261 goto exit;
1262 }
11fe1266 1263
cb5d4166 1264 if (radeon_connector->ddc_bus) {
0a9069d3 1265 dret = radeon_ddc_probe(radeon_connector, false);
cb5d4166
L		 1266
1267 /* Sometimes the pins required for the DDC probe on DVI
1268 * connectors don't make contact at the same time that the ones
1269 * for HPD do. If the DDC probe fails even though we had an HPD
1270 * signal, try again later */
1271 if (!dret && !force &&
1272 connector->status != connector_status_connected) {
1273 DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n");
1274 radeon_connector->detected_hpd_without_ddc = true;
1275 schedule_delayed_work(&rdev->hotplug_work,
1276 msecs_to_jiffies(1000));
1277 goto exit;
1278 }
1279 }
4ce001ab 1280 if (dret) {
d0d0a225 1281 radeon_connector->detected_by_load = false;
72a5c970
AD		 1282 radeon_connector_free_edid(connector);
1283 radeon_connector_get_edid(connector);
4ce001ab
DA		 1284
1285 if (!radeon_connector->edid) {
f82f5f3a 1286 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
72082093 1287 connector->name);
4a9a8b71
DA		 1288 /* rs690 seems to have a problem with connectors not existing and always
1289 * return a block of 0's. If we see this just stop polling on this output */
72a5c970
AD		 1290 if ((rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) &&
1291 radeon_connector->base.null_edid_counter) {
4a9a8b71 1292 ret = connector_status_disconnected;
72082093
JN		 1293 DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n",
1294 connector->name);
4a9a8b71 1295 radeon_connector->ddc_bus = NULL;
fc87f13b
EE		 1296 } else {
1297 ret = connector_status_connected;
1298 broken_edid = true; /* defer use_digital to later */
4a9a8b71 1299 }
4ce001ab 1300 } else {
72a5c970
AD		 1301 radeon_connector->use_digital =
1302 !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
4ce001ab 1303
0294cf4f
AD		 1304 /* some oems have boards with separate digital and analog connectors
1305 * with a shared ddc line (often vga + hdmi)
1306 */
1307 if ((!radeon_connector->use_digital) && radeon_connector->shared_ddc) {
72a5c970 1308 radeon_connector_free_edid(connector);
0294cf4f 1309 ret = connector_status_disconnected;
72a5c970 1310 } else {
0294cf4f 1311 ret = connector_status_connected;
72a5c970 1312 }
42f14c4b
AD		 1313 /* This gets complicated. We have boards with VGA + HDMI with a
1314 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1315 * DDC line. The latter is more complex because with DVI<->HDMI adapters
1316 * you don't really know what's connected to which port as both are digital.
71407c46 1317 */
d3932d6c 1318 if (radeon_connector->shared_ddc && (ret == connector_status_connected)) {
71407c46
AD		 1319 struct drm_connector *list_connector;
1320 struct radeon_connector *list_radeon_connector;
1321 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
1322 if (connector == list_connector)
1323 continue;
1324 list_radeon_connector = to_radeon_connector(list_connector);
b2ea4aa6
AD		 1325 if (list_radeon_connector->shared_ddc &&
1326 (list_radeon_connector->ddc_bus->rec.i2c_id ==
1327 radeon_connector->ddc_bus->rec.i2c_id)) {
42f14c4b
AD		 1328 /* cases where both connectors are digital */
1329 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1330 /* hpd is our only option in this case */
1331 if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
72a5c970 1332 radeon_connector_free_edid(connector);
71407c46
AD		 1333 ret = connector_status_disconnected;
1334 }
1335 }
1336 }
1337 }
1338 }
4ce001ab
DA		 1339 }
1340 }
1341
1342 if ((ret == connector_status_connected) && (radeon_connector->use_digital == true))
1343 goto out;
1344
5f0a2612
AD		 1345 /* DVI-D and HDMI-A are digital only */
1346 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1347 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1348 goto out;
1349
d0d0a225 1350 /* if we aren't forcing don't do destructive polling */
c3cceedd 1351 if (!force) {
d0d0a225
AD		 1352 /* only return the previous status if we last
1353 * detected a monitor via load.
1354 */
1355 if (radeon_connector->detected_by_load)
1356 ret = connector->status;
c3cceedd
DA		 1357 goto out;
1358 }
1359
4ce001ab 1360 /* find analog encoder */
445282db 1361 if (radeon_connector->dac_load_detect) {
62afb4ad 1362 drm_connector_for_each_possible_encoder(connector, encoder) {
e3632507 1363 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
e00e8b5e
AD		 1364 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1365 continue;
1366
445282db
DA		 1367 encoder_funcs = encoder->helper_private;
1368 if (encoder_funcs->detect) {
fc87f13b
EE		 1369 if (!broken_edid) {
1370 if (ret != connector_status_connected) {
1371 /* deal with analog monitors without DDC */
1372 ret = encoder_funcs->detect(encoder, connector);
1373 if (ret == connector_status_connected) {
1374 radeon_connector->use_digital = false;
1375 }
1376 if (ret != connector_status_disconnected)
1377 radeon_connector->detected_by_load = true;
445282db 1378 }
fc87f13b
EE		 1379 } else {
1380 enum drm_connector_status lret;
1381 /* assume digital unless load detected otherwise */
1382 radeon_connector->use_digital = true;
1383 lret = encoder_funcs->detect(encoder, connector);
1384 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1385 if (lret == connector_status_connected)
1386 radeon_connector->use_digital = false;
771fe6b9 1387 }
445282db 1388 break;
771fe6b9
JG		 1389 }
1390 }
1391 }
1392
4ce001ab
DA		 1393 if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) &&
1394 encoder) {
1395 ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true);
1396 }
1397
fafcf94e
AD		 1398 /* RN50 and some RV100 asics in servers often have a hardcoded EDID in the
1399 * vbios to deal with KVMs. If we have one and are not able to detect a monitor
1400 * by other means, assume the DFP is connected and use that EDID. In most
1401 * cases the DVI port is actually a virtual KVM port connected to the service
1402 * processor.
1403 */
a09d431f 1404out:
fafcf94e
AD		 1405 if ((!rdev->is_atom_bios) &&
1406 (ret == connector_status_disconnected) &&
1407 rdev->mode_info.bios_hardcoded_edid_size) {
1408 radeon_connector->use_digital = true;
1409 ret = connector_status_connected;
1410 }
1411
771fe6b9
JG		 1412 /* updated in get modes as well since we need to know if it's analog or digital */
1413 radeon_connector_update_scratch_regs(connector, ret);
10ebc0bc 1414
d0ea397e
AD		 1415 if ((radeon_audio != 0) && radeon_connector->use_digital) {
1416 const struct drm_connector_helper_funcs *connector_funcs =
1417 connector->helper_private;
1418
1419 encoder = connector_funcs->best_encoder(connector);
1420 if (encoder && (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)) {
1421 radeon_connector_get_edid(connector);
1422 radeon_audio_detect(connector, encoder, ret);
1423 }
1424 }
1a626b68 1425
10ebc0bc 1426exit:
15734fef
LW		 1427 if (!drm_kms_helper_is_poll_worker()) {
1428 pm_runtime_mark_last_busy(connector->dev->dev);
1429 pm_runtime_put_autosuspend(connector->dev->dev);
1430 }
10ebc0bc 1431
771fe6b9
JG		 1432 return ret;
1433}
1434
1435/* okay need to be smart in here about which encoder to pick */
1109ca09 1436static struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector)
771fe6b9 1437{
771fe6b9 1438 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
771fe6b9 1439 struct drm_encoder *encoder;
771fe6b9 1440
62afb4ad 1441 drm_connector_for_each_possible_encoder(connector, encoder) {
4ce001ab 1442 if (radeon_connector->use_digital == true) {
771fe6b9
JG		 1443 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1444 return encoder;
1445 } else {
1446 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1447 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1448 return encoder;
1449 }
1450 }
1451
1452 /* see if we have a default encoder TODO */
1453
1454 /* then check use digitial */
1455 /* pick the first one */
62afb4ad 1456 drm_connector_for_each_possible_encoder(connector, encoder)
7b71ca24
VS		 1457 return encoder;
1458
771fe6b9
JG		 1459 return NULL;
1460}
1461
d50ba256
DA		 1462static void radeon_dvi_force(struct drm_connector *connector)
1463{
1464 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1465 if (connector->force == DRM_FORCE_ON)
1466 radeon_connector->use_digital = false;
1467 if (connector->force == DRM_FORCE_ON_DIGITAL)
1468 radeon_connector->use_digital = true;
1469}
1470
7a47f20e 1471static enum drm_mode_status radeon_dvi_mode_valid(struct drm_connector *connector,
a3fa6320
AD		 1472 struct drm_display_mode *mode)
1473{
1b24203e
AD		 1474 struct drm_device *dev = connector->dev;
1475 struct radeon_device *rdev = dev->dev_private;
a3fa6320
AD		 1476 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1477
1478 /* XXX check mode bandwidth */
1479
1b24203e
AD		 1480 /* clocks over 135 MHz have heat issues with DVI on RV100 */
1481 if (radeon_connector->use_digital &&
1482 (rdev->family == CHIP_RV100) &&
1483 (mode->clock > 135000))
1484 return MODE_CLOCK_HIGH;
1485
a3fa6320
AD		 1486 if (radeon_connector->use_digital && (mode->clock > 165000)) {
1487 if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1488 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1489 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
1490 return MODE_OK;
377bd8a9 1491 else if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
f2263fc7
AD		 1492 /* HDMI 1.3+ supports max clock of 340 Mhz */
1493 if (mode->clock > 340000)
e1e84017 1494 return MODE_CLOCK_HIGH;
f2263fc7
AD		 1495 else
1496 return MODE_OK;
1497 } else {
a3fa6320 1498 return MODE_CLOCK_HIGH;
f2263fc7 1499 }
a3fa6320 1500 }
b20f9bef
AD		 1501
1502 /* check against the max pixel clock */
1503 if ((mode->clock / 10) > rdev->clock.max_pixel_clock)
1504 return MODE_CLOCK_HIGH;
1505
a3fa6320
AD		 1506 return MODE_OK;
1507}
1508
1109ca09 1509static const struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = {
3e22920f 1510 .get_modes = radeon_vga_get_modes,
a3fa6320 1511 .mode_valid = radeon_dvi_mode_valid,
771fe6b9
JG		 1512 .best_encoder = radeon_dvi_encoder,
1513};
1514
1109ca09 1515static const struct drm_connector_funcs radeon_dvi_connector_funcs = {
771fe6b9
JG		 1516 .dpms = drm_helper_connector_dpms,
1517 .detect = radeon_dvi_detect,
1518 .fill_modes = drm_helper_probe_single_connector_modes,
1519 .set_property = radeon_connector_set_property,
b0c80bd5 1520 .early_unregister = radeon_connector_unregister,
771fe6b9 1521 .destroy = radeon_connector_destroy,
d50ba256 1522 .force = radeon_dvi_force,
771fe6b9
JG		 1523};
1524
746c1aa4
DA		 1525static int radeon_dp_get_modes(struct drm_connector *connector)
1526{
1527 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
8b834852 1528 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
591a10e1 1529 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
746c1aa4
DA		 1530 int ret;
1531
f89931f3
AD		 1532 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1533 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
d291767b
AD		 1534 struct drm_display_mode *mode;
1535
2b69ffb9
AD		 1536 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1537 if (!radeon_dig_connector->edp_on)
1538 atombios_set_edp_panel_power(connector,
1539 ATOM_TRANSMITTER_ACTION_POWER_ON);
72a5c970
AD		 1540 radeon_connector_get_edid(connector);
1541 ret = radeon_ddc_get_modes(connector);
2b69ffb9
AD		 1542 if (!radeon_dig_connector->edp_on)
1543 atombios_set_edp_panel_power(connector,
1544 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1545 } else {
1546 /* need to setup ddc on the bridge */
1547 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1548 ENCODER_OBJECT_ID_NONE) {
1549 if (encoder)
1550 radeon_atom_ext_encoder_setup_ddc(encoder);
1551 }
72a5c970
AD		 1552 radeon_connector_get_edid(connector);
1553 ret = radeon_ddc_get_modes(connector);
2b69ffb9 1554 }
d291767b
AD		 1555
1556 if (ret > 0) {
d291767b
AD		 1557 if (encoder) {
1558 radeon_fixup_lvds_native_mode(encoder, connector);
1559 /* add scaled modes */
1560 radeon_add_common_modes(encoder, connector);
1561 }
1562 return ret;
1563 }
1564
d291767b
AD		 1565 if (!encoder)
1566 return 0;
1567
1568 /* we have no EDID modes */
1569 mode = radeon_fp_native_mode(encoder);
1570 if (mode) {
1571 ret = 1;
1572 drm_mode_probed_add(connector, mode);
1573 /* add the width/height from vbios tables if available */
1574 connector->display_info.width_mm = mode->width_mm;
1575 connector->display_info.height_mm = mode->height_mm;
1576 /* add scaled modes */
1577 radeon_add_common_modes(encoder, connector);
1578 }
591a10e1
AD		 1579 } else {
1580 /* need to setup ddc on the bridge */
1d33e1fc
AD		 1581 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1582 ENCODER_OBJECT_ID_NONE) {
591a10e1
AD		 1583 if (encoder)
1584 radeon_atom_ext_encoder_setup_ddc(encoder);
1585 }
72a5c970
AD		 1586 radeon_connector_get_edid(connector);
1587 ret = radeon_ddc_get_modes(connector);
da997620
AD		 1588
1589 radeon_get_native_mode(connector);
591a10e1 1590 }
8b834852 1591
746c1aa4
DA		 1592 return ret;
1593}
1594
1d33e1fc 1595u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
d7fa8bb3 1596{
d7fa8bb3
AD		 1597 struct drm_encoder *encoder;
1598 struct radeon_encoder *radeon_encoder;
d7fa8bb3 1599
62afb4ad 1600 drm_connector_for_each_possible_encoder(connector, encoder) {
d7fa8bb3
AD		 1601 radeon_encoder = to_radeon_encoder(encoder);
1602
1603 switch (radeon_encoder->encoder_id) {
1604 case ENCODER_OBJECT_ID_TRAVIS:
1605 case ENCODER_OBJECT_ID_NUTMEG:
1d33e1fc 1606 return radeon_encoder->encoder_id;
d7fa8bb3
AD		 1607 default:
1608 break;
1609 }
1610 }
1611
1d33e1fc 1612 return ENCODER_OBJECT_ID_NONE;
d7fa8bb3
AD		 1613}
1614
ebdea82d 1615static bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector)
d7fa8bb3 1616{
d7fa8bb3
AD		 1617 struct drm_encoder *encoder;
1618 struct radeon_encoder *radeon_encoder;
d7fa8bb3
AD		 1619 bool found = false;
1620
62afb4ad 1621 drm_connector_for_each_possible_encoder(connector, encoder) {
d7fa8bb3
AD		 1622 radeon_encoder = to_radeon_encoder(encoder);
1623 if (radeon_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1624 found = true;
1625 }
1626
1627 return found;
1628}
1629
1630bool radeon_connector_is_dp12_capable(struct drm_connector *connector)
1631{
1632 struct drm_device *dev = connector->dev;
1633 struct radeon_device *rdev = dev->dev_private;
1634
1635 if (ASIC_IS_DCE5(rdev) &&
af5d3653 1636 (rdev->clock.default_dispclk >= 53900) &&
d7fa8bb3
AD		 1637 radeon_connector_encoder_is_hbr2(connector)) {
1638 return true;
1639 }
1640
1641 return false;
1642}
1643
7b334fcb 1644static enum drm_connector_status
930a9e28 1645radeon_dp_detect(struct drm_connector *connector, bool force)
746c1aa4 1646{
f8d0edde
AD		 1647 struct drm_device *dev = connector->dev;
1648 struct radeon_device *rdev = dev->dev_private;
746c1aa4 1649 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
746c1aa4 1650 enum drm_connector_status ret = connector_status_disconnected;
4143e919 1651 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
591a10e1 1652 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
10ebc0bc 1653 int r;
746c1aa4 1654
9843ead0
DA		 1655 if (radeon_dig_connector->is_mst)
1656 return connector_status_disconnected;
1657
15734fef
LW		 1658 if (!drm_kms_helper_is_poll_worker()) {
1659 r = pm_runtime_get_sync(connector->dev->dev);
1660 if (r < 0)
1661 return connector_status_disconnected;
1662 }
10ebc0bc
DA		 1663
1664 if (!force && radeon_check_hpd_status_unchanged(connector)) {
1665 ret = connector->status;
1666 goto out;
1667 }
11fe1266 1668
72a5c970 1669 radeon_connector_free_edid(connector);
746c1aa4 1670
f89931f3
AD		 1671 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1672 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
d291767b
AD		 1673 if (encoder) {
1674 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1675 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
1676
1677 /* check if panel is valid */
1678 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1679 ret = connector_status_connected;
13485794
AD		 1680 /* don't fetch the edid from the vbios if ddc fails and runpm is
1681 * enabled so we report disconnected.
1682 */
1683 if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0))
1684 ret = connector_status_disconnected;
d291767b 1685 }
6f50eae7
AD		 1686 /* eDP is always DP */
1687 radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
8b834852
AD		 1688 if (!radeon_dig_connector->edp_on)
1689 atombios_set_edp_panel_power(connector,
1690 ATOM_TRANSMITTER_ACTION_POWER_ON);
6f50eae7 1691 if (radeon_dp_getdpcd(radeon_connector))
9fa05c98 1692 ret = connector_status_connected;
8b834852
AD		 1693 if (!radeon_dig_connector->edp_on)
1694 atombios_set_edp_panel_power(connector,
1695 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1d33e1fc
AD		 1696 } else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1697 ENCODER_OBJECT_ID_NONE) {
b06947b5
AD		 1698 /* DP bridges are always DP */
1699 radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1700 /* get the DPCD from the bridge */
1701 radeon_dp_getdpcd(radeon_connector);
1702
6777a4f6
AD		 1703 if (encoder) {
1704 /* setup ddc on the bridge */
1705 radeon_atom_ext_encoder_setup_ddc(encoder);
0a9069d3
NOS		 1706 /* bridge chips are always aux */
1707 if (radeon_ddc_probe(radeon_connector, true)) /* try DDC */
b06947b5 1708 ret = connector_status_connected;
6777a4f6 1709 else if (radeon_connector->dac_load_detect) { /* try load detection */
319d1e14 1710 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
b06947b5
AD		 1711 ret = encoder_funcs->detect(encoder, connector);
1712 }
591a10e1 1713 }
b06947b5 1714 } else {
6f50eae7 1715 radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
f8d0edde
AD		 1716 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
1717 ret = connector_status_connected;
9843ead0 1718 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
f8d0edde 1719 radeon_dp_getdpcd(radeon_connector);
9843ead0
DA		 1720 r = radeon_dp_mst_probe(radeon_connector);
1721 if (r == 1)
1722 ret = connector_status_disconnected;
1723 }
6f50eae7 1724 } else {
f8d0edde 1725 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
9843ead0
DA		 1726 if (radeon_dp_getdpcd(radeon_connector)) {
1727 r = radeon_dp_mst_probe(radeon_connector);
1728 if (r == 1)
1729 ret = connector_status_disconnected;
1730 else
1731 ret = connector_status_connected;
1732 }
f8d0edde 1733 } else {
d592fca9 1734 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
0a9069d3 1735 if (radeon_ddc_probe(radeon_connector, false))
f8d0edde
AD		 1736 ret = connector_status_connected;
1737 }
4143e919 1738 }
746c1aa4 1739 }
4143e919 1740
30f44372 1741 radeon_connector_update_scratch_regs(connector, ret);
1a626b68 1742
d0ea397e
AD		 1743 if ((radeon_audio != 0) && encoder) {
1744 radeon_connector_get_edid(connector);
1745 radeon_audio_detect(connector, encoder, ret);
1746 }
1a626b68 1747
10ebc0bc 1748out:
15734fef
LW		 1749 if (!drm_kms_helper_is_poll_worker()) {
1750 pm_runtime_mark_last_busy(connector->dev->dev);
1751 pm_runtime_put_autosuspend(connector->dev->dev);
1752 }
10ebc0bc 1753
746c1aa4
DA		 1754 return ret;
1755}
1756
7a47f20e 1757static enum drm_mode_status radeon_dp_mode_valid(struct drm_connector *connector,
5801ead6
AD		 1758 struct drm_display_mode *mode)
1759{
6536a3a6
AD		 1760 struct drm_device *dev = connector->dev;
1761 struct radeon_device *rdev = dev->dev_private;
5801ead6
AD		 1762 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1763 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
1764
1765 /* XXX check mode bandwidth */
1766
f89931f3
AD		 1767 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1768 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
d291767b
AD		 1769 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
1770
1771 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1772 return MODE_PANEL;
1773
1774 if (encoder) {
1775 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1776 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
1777
f89931f3 1778 /* AVIVO hardware supports downscaling modes larger than the panel
d291767b
AD		 1779 * to the panel size, but I'm not sure this is desirable.
1780 */
1781 if ((mode->hdisplay > native_mode->hdisplay) ||
1782 (mode->vdisplay > native_mode->vdisplay))
1783 return MODE_PANEL;
1784
1785 /* if scaling is disabled, block non-native modes */
1786 if (radeon_encoder->rmx_type == RMX_OFF) {
1787 if ((mode->hdisplay != native_mode->hdisplay) ||
1788 (mode->vdisplay != native_mode->vdisplay))
1789 return MODE_PANEL;
1790 }
1791 }
d291767b
AD		 1792 } else {
1793 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
6536a3a6 1794 (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
d291767b 1795 return radeon_dp_mode_valid_helper(connector, mode);
6536a3a6 1796 } else {
377bd8a9 1797 if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) {
6536a3a6
AD		 1798 /* HDMI 1.3+ supports max clock of 340 Mhz */
1799 if (mode->clock > 340000)
1800 return MODE_CLOCK_HIGH;
1801 } else {
1802 if (mode->clock > 165000)
1803 return MODE_CLOCK_HIGH;
1804 }
1805 }
d291767b 1806 }
6536a3a6
AD		 1807
1808 return MODE_OK;
5801ead6
AD		 1809}
1810
1109ca09 1811static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = {
746c1aa4 1812 .get_modes = radeon_dp_get_modes,
5801ead6 1813 .mode_valid = radeon_dp_mode_valid,
746c1aa4
DA		 1814 .best_encoder = radeon_dvi_encoder,
1815};
1816
1109ca09 1817static const struct drm_connector_funcs radeon_dp_connector_funcs = {
746c1aa4
DA		 1818 .dpms = drm_helper_connector_dpms,
1819 .detect = radeon_dp_detect,
1820 .fill_modes = drm_helper_probe_single_connector_modes,
1821 .set_property = radeon_connector_set_property,
b0c80bd5 1822 .early_unregister = radeon_connector_unregister,
379dfc25 1823 .destroy = radeon_connector_destroy,
746c1aa4
DA		 1824 .force = radeon_dvi_force,
1825};
1826
855f5f1d
AD		 1827static const struct drm_connector_funcs radeon_edp_connector_funcs = {
1828 .dpms = drm_helper_connector_dpms,
1829 .detect = radeon_dp_detect,
1830 .fill_modes = drm_helper_probe_single_connector_modes,
1831 .set_property = radeon_lvds_set_property,
b0c80bd5 1832 .early_unregister = radeon_connector_unregister,
379dfc25 1833 .destroy = radeon_connector_destroy,
855f5f1d
AD		 1834 .force = radeon_dvi_force,
1835};
1836
1837static const struct drm_connector_funcs radeon_lvds_bridge_connector_funcs = {
1838 .dpms = drm_helper_connector_dpms,
1839 .detect = radeon_dp_detect,
1840 .fill_modes = drm_helper_probe_single_connector_modes,
1841 .set_property = radeon_lvds_set_property,
b0c80bd5 1842 .early_unregister = radeon_connector_unregister,
379dfc25 1843 .destroy = radeon_connector_destroy,
855f5f1d
AD		 1844 .force = radeon_dvi_force,
1845};
1846
771fe6b9
JG		 1847void
1848radeon_add_atom_connector(struct drm_device *dev,
1849 uint32_t connector_id,
1850 uint32_t supported_device,
1851 int connector_type,
1852 struct radeon_i2c_bus_rec *i2c_bus,
b75fad06 1853 uint32_t igp_lane_info,
eed45b30 1854 uint16_t connector_object_id,
26b5bc98
AD		 1855 struct radeon_hpd *hpd,
1856 struct radeon_router *router)
771fe6b9 1857{
445282db 1858 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1859 struct drm_connector *connector;
1860 struct radeon_connector *radeon_connector;
1861 struct radeon_connector_atom_dig *radeon_dig_connector;
eac4dff6
AD		 1862 struct drm_encoder *encoder;
1863 struct radeon_encoder *radeon_encoder;
771fe6b9 1864 uint32_t subpixel_order = SubPixelNone;
0294cf4f 1865 bool shared_ddc = false;
eac4dff6 1866 bool is_dp_bridge = false;
496263bf 1867 bool has_aux = false;
771fe6b9 1868
4ce001ab 1869 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
771fe6b9
JG		 1870 return;
1871
cf4c12f9
AD		 1872 /* if the user selected tv=0 don't try and add the connector */
1873 if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
1874 (connector_type == DRM_MODE_CONNECTOR_Composite) ||
1875 (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
1876 (radeon_tv == 0))
1877 return;
1878
771fe6b9
JG		 1879 /* see if we already added it */
1880 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1881 radeon_connector = to_radeon_connector(connector);
1882 if (radeon_connector->connector_id == connector_id) {
1883 radeon_connector->devices |= supported_device;
1884 return;
1885 }
0294cf4f 1886 if (radeon_connector->ddc_bus && i2c_bus->valid) {
d3932d6c 1887 if (radeon_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
0294cf4f
AD		 1888 radeon_connector->shared_ddc = true;
1889 shared_ddc = true;
1890 }
fb939dfc 1891 if (radeon_connector->router_bus && router->ddc_valid &&
26b5bc98
AD		 1892 (radeon_connector->router.router_id == router->router_id)) {
1893 radeon_connector->shared_ddc = false;
1894 shared_ddc = false;
1895 }
0294cf4f 1896 }
771fe6b9
JG		 1897 }
1898
eac4dff6
AD		 1899 /* check if it's a dp bridge */
1900 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1901 radeon_encoder = to_radeon_encoder(encoder);
1902 if (radeon_encoder->devices & supported_device) {
1903 switch (radeon_encoder->encoder_id) {
1904 case ENCODER_OBJECT_ID_TRAVIS:
1905 case ENCODER_OBJECT_ID_NUTMEG:
1906 is_dp_bridge = true;
1907 break;
1908 default:
1909 break;
1910 }
1911 }
1912 }
1913
771fe6b9
JG		 1914 radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
1915 if (!radeon_connector)
1916 return;
1917
1918 connector = &radeon_connector->base;
1919
1920 radeon_connector->connector_id = connector_id;
1921 radeon_connector->devices = supported_device;
0294cf4f 1922 radeon_connector->shared_ddc = shared_ddc;
b75fad06 1923 radeon_connector->connector_object_id = connector_object_id;
eed45b30 1924 radeon_connector->hpd = *hpd;
bc1c4dc3 1925
26b5bc98 1926 radeon_connector->router = *router;
fb939dfc 1927 if (router->ddc_valid || router->cd_valid) {
26b5bc98
AD		 1928 radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info);
1929 if (!radeon_connector->router_bus)
a70882aa 1930 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
26b5bc98 1931 }
eac4dff6
AD		 1932
1933 if (is_dp_bridge) {
771fe6b9
JG		 1934 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1935 if (!radeon_dig_connector)
1936 goto failed;
771fe6b9
JG		 1937 radeon_dig_connector->igp_lane_info = igp_lane_info;
1938 radeon_connector->con_priv = radeon_dig_connector;
771fe6b9 1939 if (i2c_bus->valid) {
379dfc25 1940 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
93386368 1941 if (radeon_connector->ddc_bus)
496263bf 1942 has_aux = true;
93386368 1943 else
eac4dff6 1944 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
771fe6b9 1945 }
eac4dff6
AD		 1946 switch (connector_type) {
1947 case DRM_MODE_CONNECTOR_VGA:
1948 case DRM_MODE_CONNECTOR_DVIA:
1949 default:
93386368
NA		 1950 drm_connector_init(dev, &radeon_connector->base,
1951 &radeon_dp_connector_funcs, connector_type);
855f5f1d
AD		 1952 drm_connector_helper_add(&radeon_connector->base,
1953 &radeon_dp_connector_helper_funcs);
eac4dff6
AD		 1954 connector->interlace_allowed = true;
1955 connector->doublescan_allowed = true;
d629a3ce 1956 radeon_connector->dac_load_detect = true;
e35755fa 1957 drm_object_attach_property(&radeon_connector->base.base,
d629a3ce
AD		 1958 rdev->mode_info.load_detect_property,
1959 1);
da997620
AD		 1960 drm_object_attach_property(&radeon_connector->base.base,
1961 dev->mode_config.scaling_mode_property,
1962 DRM_MODE_SCALE_NONE);
643b1f56
AD		 1963 if (ASIC_IS_DCE5(rdev))
1964 drm_object_attach_property(&radeon_connector->base.base,
1965 rdev->mode_info.output_csc_property,
1966 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 1967 break;
1968 case DRM_MODE_CONNECTOR_DVII:
1969 case DRM_MODE_CONNECTOR_DVID:
1970 case DRM_MODE_CONNECTOR_HDMIA:
1971 case DRM_MODE_CONNECTOR_HDMIB:
1972 case DRM_MODE_CONNECTOR_DisplayPort:
93386368
NA		 1973 drm_connector_init(dev, &radeon_connector->base,
1974 &radeon_dp_connector_funcs, connector_type);
855f5f1d
AD		 1975 drm_connector_helper_add(&radeon_connector->base,
1976 &radeon_dp_connector_helper_funcs);
e35755fa 1977 drm_object_attach_property(&radeon_connector->base.base,
430f70d5 1978 rdev->mode_info.underscan_property,
56bec7c0 1979 UNDERSCAN_OFF);
e35755fa 1980 drm_object_attach_property(&radeon_connector->base.base,
5bccf5e3
MG		 1981 rdev->mode_info.underscan_hborder_property,
1982 0);
e35755fa 1983 drm_object_attach_property(&radeon_connector->base.base,
5bccf5e3
MG		 1984 rdev->mode_info.underscan_vborder_property,
1985 0);
91915260 1986
da997620
AD		 1987 drm_object_attach_property(&radeon_connector->base.base,
1988 dev->mode_config.scaling_mode_property,
1989 DRM_MODE_SCALE_NONE);
1990
6214bb74
AD		 1991 drm_object_attach_property(&radeon_connector->base.base,
1992 rdev->mode_info.dither_property,
1993 RADEON_FMT_DITHER_DISABLE);
91915260 1994
7403c515 1995 if (radeon_audio != 0) {
108dc8e8
AD		 1996 drm_object_attach_property(&radeon_connector->base.base,
1997 rdev->mode_info.audio_property,
e31fadd3 1998 RADEON_AUDIO_AUTO);
7403c515
AD		 1999 radeon_connector->audio = RADEON_AUDIO_AUTO;
2000 }
643b1f56
AD		 2001 if (ASIC_IS_DCE5(rdev))
2002 drm_object_attach_property(&radeon_connector->base.base,
2003 rdev->mode_info.output_csc_property,
2004 RADEON_OUTPUT_CSC_BYPASS);
91915260 2005
eac4dff6
AD		 2006 subpixel_order = SubPixelHorizontalRGB;
2007 connector->interlace_allowed = true;
2008 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
2009 connector->doublescan_allowed = true;
2010 else
2011 connector->doublescan_allowed = false;
d629a3ce
AD		 2012 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
2013 radeon_connector->dac_load_detect = true;
e35755fa 2014 drm_object_attach_property(&radeon_connector->base.base,
d629a3ce
AD		 2015 rdev->mode_info.load_detect_property,
2016 1);
2017 }
eac4dff6
AD		 2018 break;
2019 case DRM_MODE_CONNECTOR_LVDS:
2020 case DRM_MODE_CONNECTOR_eDP:
93386368
NA		 2021 drm_connector_init(dev, &radeon_connector->base,
2022 &radeon_lvds_bridge_connector_funcs, connector_type);
855f5f1d
AD		 2023 drm_connector_helper_add(&radeon_connector->base,
2024 &radeon_dp_connector_helper_funcs);
e35755fa 2025 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2026 dev->mode_config.scaling_mode_property,
2027 DRM_MODE_SCALE_FULLSCREEN);
2028 subpixel_order = SubPixelHorizontalRGB;
2029 connector->interlace_allowed = false;
2030 connector->doublescan_allowed = false;
2031 break;
5bccf5e3 2032 }
eac4dff6
AD		 2033 } else {
2034 switch (connector_type) {
2035 case DRM_MODE_CONNECTOR_VGA:
93386368
NA		 2036 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
2037 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
eac4dff6
AD		 2038 if (i2c_bus->valid) {
2039 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2040 if (!radeon_connector->ddc_bus)
2041 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2042 }
390d0bbe 2043 radeon_connector->dac_load_detect = true;
e35755fa 2044 drm_object_attach_property(&radeon_connector->base.base,
390d0bbe
AD		 2045 rdev->mode_info.load_detect_property,
2046 1);
da997620
AD		 2047 if (ASIC_IS_AVIVO(rdev))
2048 drm_object_attach_property(&radeon_connector->base.base,
2049 dev->mode_config.scaling_mode_property,
2050 DRM_MODE_SCALE_NONE);
643b1f56
AD		 2051 if (ASIC_IS_DCE5(rdev))
2052 drm_object_attach_property(&radeon_connector->base.base,
2053 rdev->mode_info.output_csc_property,
2054 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 2055 /* no HPD on analog connectors */
2056 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
eac4dff6 2057 connector->interlace_allowed = true;
c49948f4 2058 connector->doublescan_allowed = true;
eac4dff6
AD		 2059 break;
2060 case DRM_MODE_CONNECTOR_DVIA:
93386368
NA		 2061 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
2062 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
eac4dff6
AD		 2063 if (i2c_bus->valid) {
2064 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2065 if (!radeon_connector->ddc_bus)
2066 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2067 }
2068 radeon_connector->dac_load_detect = true;
e35755fa 2069 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2070 rdev->mode_info.load_detect_property,
2071 1);
da997620
AD		 2072 if (ASIC_IS_AVIVO(rdev))
2073 drm_object_attach_property(&radeon_connector->base.base,
2074 dev->mode_config.scaling_mode_property,
2075 DRM_MODE_SCALE_NONE);
643b1f56
AD		 2076 if (ASIC_IS_DCE5(rdev))
2077 drm_object_attach_property(&radeon_connector->base.base,
2078 rdev->mode_info.output_csc_property,
2079 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 2080 /* no HPD on analog connectors */
2081 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
2082 connector->interlace_allowed = true;
2083 connector->doublescan_allowed = true;
2084 break;
2085 case DRM_MODE_CONNECTOR_DVII:
2086 case DRM_MODE_CONNECTOR_DVID:
2087 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2088 if (!radeon_dig_connector)
2089 goto failed;
2090 radeon_dig_connector->igp_lane_info = igp_lane_info;
2091 radeon_connector->con_priv = radeon_dig_connector;
93386368
NA		 2092 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
2093 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
eac4dff6
AD		 2094 if (i2c_bus->valid) {
2095 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2096 if (!radeon_connector->ddc_bus)
2097 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2098 }
2099 subpixel_order = SubPixelHorizontalRGB;
e35755fa 2100 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2101 rdev->mode_info.coherent_mode_property,
2102 1);
2103 if (ASIC_IS_AVIVO(rdev)) {
e35755fa 2104 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2105 rdev->mode_info.underscan_property,
2106 UNDERSCAN_OFF);
e35755fa 2107 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2108 rdev->mode_info.underscan_hborder_property,
2109 0);
e35755fa 2110 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2111 rdev->mode_info.underscan_vborder_property,
2112 0);
da997620
AD		 2113 drm_object_attach_property(&radeon_connector->base.base,
2114 rdev->mode_info.dither_property,
2115 RADEON_FMT_DITHER_DISABLE);
2116 drm_object_attach_property(&radeon_connector->base.base,
2117 dev->mode_config.scaling_mode_property,
2118 DRM_MODE_SCALE_NONE);
eac4dff6 2119 }
108dc8e8 2120 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
8666c076 2121 drm_object_attach_property(&radeon_connector->base.base,
108dc8e8 2122 rdev->mode_info.audio_property,
e31fadd3 2123 RADEON_AUDIO_AUTO);
7403c515 2124 radeon_connector->audio = RADEON_AUDIO_AUTO;
8666c076 2125 }
eac4dff6
AD		 2126 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
2127 radeon_connector->dac_load_detect = true;
e35755fa 2128 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2129 rdev->mode_info.load_detect_property,
2130 1);
2131 }
643b1f56
AD		 2132 if (ASIC_IS_DCE5(rdev))
2133 drm_object_attach_property(&radeon_connector->base.base,
2134 rdev->mode_info.output_csc_property,
2135 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 2136 connector->interlace_allowed = true;
2137 if (connector_type == DRM_MODE_CONNECTOR_DVII)
2138 connector->doublescan_allowed = true;
2139 else
2140 connector->doublescan_allowed = false;
2141 break;
2142 case DRM_MODE_CONNECTOR_HDMIA:
2143 case DRM_MODE_CONNECTOR_HDMIB:
2144 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2145 if (!radeon_dig_connector)
2146 goto failed;
2147 radeon_dig_connector->igp_lane_info = igp_lane_info;
2148 radeon_connector->con_priv = radeon_dig_connector;
93386368
NA		 2149 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
2150 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
eac4dff6
AD		 2151 if (i2c_bus->valid) {
2152 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2153 if (!radeon_connector->ddc_bus)
2154 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2155 }
e35755fa 2156 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2157 rdev->mode_info.coherent_mode_property,
2158 1);
2159 if (ASIC_IS_AVIVO(rdev)) {
e35755fa 2160 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2161 rdev->mode_info.underscan_property,
2162 UNDERSCAN_OFF);
e35755fa 2163 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2164 rdev->mode_info.underscan_hborder_property,
2165 0);
e35755fa 2166 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2167 rdev->mode_info.underscan_vborder_property,
2168 0);
da997620
AD		 2169 drm_object_attach_property(&radeon_connector->base.base,
2170 rdev->mode_info.dither_property,
2171 RADEON_FMT_DITHER_DISABLE);
2172 drm_object_attach_property(&radeon_connector->base.base,
2173 dev->mode_config.scaling_mode_property,
2174 DRM_MODE_SCALE_NONE);
eac4dff6 2175 }
108dc8e8 2176 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
8666c076 2177 drm_object_attach_property(&radeon_connector->base.base,
108dc8e8 2178 rdev->mode_info.audio_property,
e31fadd3 2179 RADEON_AUDIO_AUTO);
7403c515 2180 radeon_connector->audio = RADEON_AUDIO_AUTO;
8666c076 2181 }
643b1f56
AD		 2182 if (ASIC_IS_DCE5(rdev))
2183 drm_object_attach_property(&radeon_connector->base.base,
2184 rdev->mode_info.output_csc_property,
2185 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 2186 subpixel_order = SubPixelHorizontalRGB;
2187 connector->interlace_allowed = true;
2188 if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
2189 connector->doublescan_allowed = true;
2190 else
2191 connector->doublescan_allowed = false;
2192 break;
2193 case DRM_MODE_CONNECTOR_DisplayPort:
2194 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2195 if (!radeon_dig_connector)
2196 goto failed;
2197 radeon_dig_connector->igp_lane_info = igp_lane_info;
2198 radeon_connector->con_priv = radeon_dig_connector;
93386368
NA		 2199 drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
2200 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
eac4dff6 2201 if (i2c_bus->valid) {
eac4dff6 2202 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
93386368 2203 if (radeon_connector->ddc_bus)
496263bf 2204 has_aux = true;
93386368 2205 else
eac4dff6
AD		 2206 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2207 }
2208 subpixel_order = SubPixelHorizontalRGB;
e35755fa 2209 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2210 rdev->mode_info.coherent_mode_property,
2211 1);
2212 if (ASIC_IS_AVIVO(rdev)) {
e35755fa 2213 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2214 rdev->mode_info.underscan_property,
2215 UNDERSCAN_OFF);
e35755fa 2216 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2217 rdev->mode_info.underscan_hborder_property,
2218 0);
e35755fa 2219 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2220 rdev->mode_info.underscan_vborder_property,
2221 0);
da997620
AD		 2222 drm_object_attach_property(&radeon_connector->base.base,
2223 rdev->mode_info.dither_property,
2224 RADEON_FMT_DITHER_DISABLE);
2225 drm_object_attach_property(&radeon_connector->base.base,
2226 dev->mode_config.scaling_mode_property,
2227 DRM_MODE_SCALE_NONE);
eac4dff6 2228 }
108dc8e8 2229 if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
8666c076 2230 drm_object_attach_property(&radeon_connector->base.base,
108dc8e8 2231 rdev->mode_info.audio_property,
e31fadd3 2232 RADEON_AUDIO_AUTO);
7403c515 2233 radeon_connector->audio = RADEON_AUDIO_AUTO;
8666c076 2234 }
643b1f56
AD		 2235 if (ASIC_IS_DCE5(rdev))
2236 drm_object_attach_property(&radeon_connector->base.base,
2237 rdev->mode_info.output_csc_property,
2238 RADEON_OUTPUT_CSC_BYPASS);
eac4dff6
AD		 2239 connector->interlace_allowed = true;
2240 /* in theory with a DP to VGA converter... */
c49948f4 2241 connector->doublescan_allowed = false;
eac4dff6
AD		 2242 break;
2243 case DRM_MODE_CONNECTOR_eDP:
2244 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2245 if (!radeon_dig_connector)
2246 goto failed;
2247 radeon_dig_connector->igp_lane_info = igp_lane_info;
2248 radeon_connector->con_priv = radeon_dig_connector;
93386368
NA		 2249 drm_connector_init(dev, &radeon_connector->base, &radeon_edp_connector_funcs, connector_type);
2250 drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
eac4dff6 2251 if (i2c_bus->valid) {
379dfc25 2252 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
93386368 2253 if (radeon_connector->ddc_bus)
496263bf 2254 has_aux = true;
93386368 2255 else
eac4dff6
AD		 2256 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2257 }
e35755fa 2258 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2259 dev->mode_config.scaling_mode_property,
2260 DRM_MODE_SCALE_FULLSCREEN);
2261 subpixel_order = SubPixelHorizontalRGB;
2262 connector->interlace_allowed = false;
2263 connector->doublescan_allowed = false;
2264 break;
2265 case DRM_MODE_CONNECTOR_SVIDEO:
2266 case DRM_MODE_CONNECTOR_Composite:
2267 case DRM_MODE_CONNECTOR_9PinDIN:
93386368 2268 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
eac4dff6
AD		 2269 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
2270 radeon_connector->dac_load_detect = true;
e35755fa 2271 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2272 rdev->mode_info.load_detect_property,
2273 1);
e35755fa 2274 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2275 rdev->mode_info.tv_std_property,
2276 radeon_atombios_get_tv_info(rdev));
2277 /* no HPD on analog connectors */
2278 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
2279 connector->interlace_allowed = false;
2280 connector->doublescan_allowed = false;
2281 break;
2282 case DRM_MODE_CONNECTOR_LVDS:
2283 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
2284 if (!radeon_dig_connector)
2285 goto failed;
2286 radeon_dig_connector->igp_lane_info = igp_lane_info;
2287 radeon_connector->con_priv = radeon_dig_connector;
93386368
NA		 2288 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
2289 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
eac4dff6
AD		 2290 if (i2c_bus->valid) {
2291 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
2292 if (!radeon_connector->ddc_bus)
2293 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
2294 }
e35755fa 2295 drm_object_attach_property(&radeon_connector->base.base,
eac4dff6
AD		 2296 dev->mode_config.scaling_mode_property,
2297 DRM_MODE_SCALE_FULLSCREEN);
2298 subpixel_order = SubPixelHorizontalRGB;
2299 connector->interlace_allowed = false;
2300 connector->doublescan_allowed = false;
2301 break;
771fe6b9 2302 }
771fe6b9
JG		 2303 }
2304
2581afcc 2305 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) {
14ff8d48
L		 2306 if (i2c_bus->valid) {
2307 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2308 DRM_CONNECTOR_POLL_DISCONNECT;
2309 }
eb1f8e4f
DA		 2310 } else
2311 connector->polled = DRM_CONNECTOR_POLL_HPD;
2312
771fe6b9 2313 connector->display_info.subpixel_order = subpixel_order;
34ea3d38 2314 drm_connector_register(connector);
496263bf
AD		 2315
2316 if (has_aux)
2317 radeon_dp_aux_init(radeon_connector);
2318
771fe6b9
JG		 2319 return;
2320
2321failed:
771fe6b9
JG		 2322 drm_connector_cleanup(connector);
2323 kfree(connector);
2324}
2325
2326void
2327radeon_add_legacy_connector(struct drm_device *dev,
2328 uint32_t connector_id,
2329 uint32_t supported_device,
2330 int connector_type,
b75fad06 2331 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 2332 uint16_t connector_object_id,
2333 struct radeon_hpd *hpd)
771fe6b9 2334{
445282db 2335 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 2336 struct drm_connector *connector;
2337 struct radeon_connector *radeon_connector;
2338 uint32_t subpixel_order = SubPixelNone;
2339
4ce001ab 2340 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
771fe6b9
JG		 2341 return;
2342
cf4c12f9
AD		 2343 /* if the user selected tv=0 don't try and add the connector */
2344 if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
2345 (connector_type == DRM_MODE_CONNECTOR_Composite) ||
2346 (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
2347 (radeon_tv == 0))
2348 return;
2349
771fe6b9
JG		 2350 /* see if we already added it */
2351 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2352 radeon_connector = to_radeon_connector(connector);
2353 if (radeon_connector->connector_id == connector_id) {
2354 radeon_connector->devices |= supported_device;
2355 return;
2356 }
2357 }
2358
2359 radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
2360 if (!radeon_connector)
2361 return;
2362
2363 connector = &radeon_connector->base;
2364
2365 radeon_connector->connector_id = connector_id;
2366 radeon_connector->devices = supported_device;
b75fad06 2367 radeon_connector->connector_object_id = connector_object_id;
eed45b30 2368 radeon_connector->hpd = *hpd;
bc1c4dc3 2369
771fe6b9
JG		 2370 switch (connector_type) {
2371 case DRM_MODE_CONNECTOR_VGA:
93386368
NA		 2372 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
2373 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
771fe6b9 2374 if (i2c_bus->valid) {
f376b94f 2375 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
771fe6b9 2376 if (!radeon_connector->ddc_bus)
a70882aa 2377 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
771fe6b9 2378 }
35e4b7af 2379 radeon_connector->dac_load_detect = true;
e35755fa 2380 drm_object_attach_property(&radeon_connector->base.base,
445282db
DA		 2381 rdev->mode_info.load_detect_property,
2382 1);
2581afcc
AD		 2383 /* no HPD on analog connectors */
2384 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
c49948f4
AD		 2385 connector->interlace_allowed = true;
2386 connector->doublescan_allowed = true;
771fe6b9
JG		 2387 break;
2388 case DRM_MODE_CONNECTOR_DVIA:
93386368
NA		 2389 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
2390 drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
771fe6b9 2391 if (i2c_bus->valid) {
f376b94f 2392 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
771fe6b9 2393 if (!radeon_connector->ddc_bus)
a70882aa 2394 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
771fe6b9 2395 }
35e4b7af 2396 radeon_connector->dac_load_detect = true;
e35755fa 2397 drm_object_attach_property(&radeon_connector->base.base,
445282db
DA		 2398 rdev->mode_info.load_detect_property,
2399 1);
2581afcc
AD		 2400 /* no HPD on analog connectors */
2401 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
c49948f4
AD		 2402 connector->interlace_allowed = true;
2403 connector->doublescan_allowed = true;
771fe6b9
JG		 2404 break;
2405 case DRM_MODE_CONNECTOR_DVII:
2406 case DRM_MODE_CONNECTOR_DVID:
93386368
NA		 2407 drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
2408 drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
771fe6b9 2409 if (i2c_bus->valid) {
f376b94f 2410 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
771fe6b9 2411 if (!radeon_connector->ddc_bus)
a70882aa 2412 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
68b3adb4
AD		 2413 }
2414 if (connector_type == DRM_MODE_CONNECTOR_DVII) {
35e4b7af 2415 radeon_connector->dac_load_detect = true;
e35755fa 2416 drm_object_attach_property(&radeon_connector->base.base,
445282db
DA		 2417 rdev->mode_info.load_detect_property,
2418 1);
771fe6b9
JG		 2419 }
2420 subpixel_order = SubPixelHorizontalRGB;
c49948f4
AD		 2421 connector->interlace_allowed = true;
2422 if (connector_type == DRM_MODE_CONNECTOR_DVII)
2423 connector->doublescan_allowed = true;
2424 else
2425 connector->doublescan_allowed = false;
771fe6b9
JG		 2426 break;
2427 case DRM_MODE_CONNECTOR_SVIDEO:
2428 case DRM_MODE_CONNECTOR_Composite:
2429 case DRM_MODE_CONNECTOR_9PinDIN:
93386368 2430 drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
cf4c12f9
AD		 2431 drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
2432 radeon_connector->dac_load_detect = true;
2433 /* RS400,RC410,RS480 chipset seems to report a lot
2434 * of false positive on load detect, we haven't yet
2435 * found a way to make load detect reliable on those
2436 * chipset, thus just disable it for TV.
2437 */
2438 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480)
2439 radeon_connector->dac_load_detect = false;
e35755fa 2440 drm_object_attach_property(&radeon_connector->base.base,
cf4c12f9
AD		 2441 rdev->mode_info.load_detect_property,
2442 radeon_connector->dac_load_detect);
e35755fa 2443 drm_object_attach_property(&radeon_connector->base.base,
cf4c12f9
AD		 2444 rdev->mode_info.tv_std_property,
2445 radeon_combios_get_tv_info(rdev));
2446 /* no HPD on analog connectors */
2447 radeon_connector->hpd.hpd = RADEON_HPD_NONE;
c49948f4
AD		 2448 connector->interlace_allowed = false;
2449 connector->doublescan_allowed = false;
771fe6b9
JG		 2450 break;
2451 case DRM_MODE_CONNECTOR_LVDS:
93386368
NA		 2452 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
2453 drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
771fe6b9 2454 if (i2c_bus->valid) {
f376b94f 2455 radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
771fe6b9 2456 if (!radeon_connector->ddc_bus)
a70882aa 2457 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
771fe6b9 2458 }
e35755fa 2459 drm_object_attach_property(&radeon_connector->base.base,
445282db
DA		 2460 dev->mode_config.scaling_mode_property,
2461 DRM_MODE_SCALE_FULLSCREEN);
771fe6b9 2462 subpixel_order = SubPixelHorizontalRGB;
c49948f4
AD		 2463 connector->interlace_allowed = false;
2464 connector->doublescan_allowed = false;
771fe6b9
JG		 2465 break;
2466 }
2467
2581afcc 2468 if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) {
14ff8d48
L		 2469 if (i2c_bus->valid) {
2470 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
2471 DRM_CONNECTOR_POLL_DISCONNECT;
2472 }
eb1f8e4f
DA		 2473 } else
2474 connector->polled = DRM_CONNECTOR_POLL_HPD;
14ff8d48 2475
771fe6b9 2476 connector->display_info.subpixel_order = subpixel_order;
34ea3d38 2477 drm_connector_register(connector);
771fe6b9 2478}
9843ead0
DA		 2479
2480void radeon_setup_mst_connector(struct drm_device *dev)
2481{
2482 struct radeon_device *rdev = dev->dev_private;
2483 struct drm_connector *connector;
2484 struct radeon_connector *radeon_connector;
2485
2486 if (!ASIC_IS_DCE5(rdev))
2487 return;
2488
2489 if (radeon_mst == 0)
2490 return;
2491
2492 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2493 int ret;
2494
2495 radeon_connector = to_radeon_connector(connector);
2496
2497 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
2498 continue;
2499
2500 ret = radeon_dp_mst_init(radeon_connector);
2501 }
2502}
Linux 6.x block layer and io_uring tree(s)