Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
760285e7 DH |
26 | #include <drm/drmP.h> |
27 | #include <drm/drm_edid.h> | |
28 | #include <drm/drm_crtc_helper.h> | |
29 | #include <drm/drm_fb_helper.h> | |
9843ead0 | 30 | #include <drm/drm_dp_mst_helper.h> |
760285e7 | 31 | #include <drm/radeon_drm.h> |
771fe6b9 | 32 | #include "radeon.h" |
1a626b68 | 33 | #include "radeon_audio.h" |
923f6848 | 34 | #include "atom.h" |
771fe6b9 | 35 | |
10ebc0bc | 36 | #include <linux/pm_runtime.h> |
47eb8f73 | 37 | #include <linux/vga_switcheroo.h> |
10ebc0bc | 38 | |
9843ead0 DA |
39 | static int radeon_dp_handle_hpd(struct drm_connector *connector) |
40 | { | |
41 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
42 | int ret; | |
43 | ||
44 | ret = radeon_dp_mst_check_status(radeon_connector); | |
45 | if (ret == -EINVAL) | |
46 | return 1; | |
47 | return 0; | |
48 | } | |
d4877cf2 AD |
49 | void radeon_connector_hotplug(struct drm_connector *connector) |
50 | { | |
51 | struct drm_device *dev = connector->dev; | |
52 | struct radeon_device *rdev = dev->dev_private; | |
53 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
54 | ||
9843ead0 DA |
55 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { |
56 | struct radeon_connector_atom_dig *dig_connector = | |
57 | radeon_connector->con_priv; | |
58 | ||
59 | if (radeon_connector->is_mst_connector) | |
60 | return; | |
61 | if (dig_connector->is_mst) { | |
62 | radeon_dp_handle_hpd(connector); | |
63 | return; | |
64 | } | |
65 | } | |
cbac9543 AD |
66 | /* bail if the connector does not have hpd pin, e.g., |
67 | * VGA, TV, etc. | |
68 | */ | |
69 | if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) | |
70 | return; | |
71 | ||
1e85e1d0 | 72 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
d4877cf2 | 73 | |
73104b5c | 74 | /* if the connector is already off, don't turn it back on */ |
6e9f798d | 75 | /* FIXME: This access isn't protected by any locks. */ |
73104b5c AD |
76 | if (connector->dpms != DRM_MODE_DPMS_ON) |
77 | return; | |
78 | ||
d5811e87 AD |
79 | /* just deal with DP (not eDP) here. */ |
80 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { | |
266dcba5 JG |
81 | struct radeon_connector_atom_dig *dig_connector = |
82 | radeon_connector->con_priv; | |
7c3ed0fd | 83 | |
266dcba5 JG |
84 | /* if existing sink type was not DP no need to retrain */ |
85 | if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) | |
86 | return; | |
87 | ||
88 | /* first get sink type as it may be reset after (un)plug */ | |
89 | dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector); | |
90 | /* don't do anything if sink is not display port, i.e., | |
91 | * passive dp->(dvi|hdmi) adaptor | |
92 | */ | |
93 | if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { | |
94 | int saved_dpms = connector->dpms; | |
95 | /* Only turn off the display if it's physically disconnected */ | |
ca2ccde5 | 96 | if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) { |
266dcba5 | 97 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); |
ca2ccde5 | 98 | } else if (radeon_dp_needs_link_train(radeon_connector)) { |
924f92bf SCP |
99 | /* Don't try to start link training before we |
100 | * have the dpcd */ | |
101 | if (!radeon_dp_getdpcd(radeon_connector)) | |
102 | return; | |
103 | ||
ca2ccde5 JG |
104 | /* set it to OFF so that drm_helper_connector_dpms() |
105 | * won't return immediately since the current state | |
106 | * is ON at this point. | |
107 | */ | |
108 | connector->dpms = DRM_MODE_DPMS_OFF; | |
266dcba5 | 109 | drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); |
ca2ccde5 | 110 | } |
266dcba5 JG |
111 | connector->dpms = saved_dpms; |
112 | } | |
d4877cf2 | 113 | } |
d4877cf2 AD |
114 | } |
115 | ||
445282db DA |
116 | static void radeon_property_change_mode(struct drm_encoder *encoder) |
117 | { | |
118 | struct drm_crtc *crtc = encoder->crtc; | |
119 | ||
120 | if (crtc && crtc->enabled) { | |
121 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
f4510a27 | 122 | crtc->x, crtc->y, crtc->primary->fb); |
445282db DA |
123 | } |
124 | } | |
eccea792 AD |
125 | |
126 | int radeon_get_monitor_bpc(struct drm_connector *connector) | |
127 | { | |
128 | struct drm_device *dev = connector->dev; | |
129 | struct radeon_device *rdev = dev->dev_private; | |
130 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
131 | struct radeon_connector_atom_dig *dig_connector; | |
132 | int bpc = 8; | |
ea292861 | 133 | int mode_clock, max_tmds_clock; |
eccea792 AD |
134 | |
135 | switch (connector->connector_type) { | |
136 | case DRM_MODE_CONNECTOR_DVII: | |
137 | case DRM_MODE_CONNECTOR_HDMIB: | |
138 | if (radeon_connector->use_digital) { | |
377bd8a9 | 139 | if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
eccea792 AD |
140 | if (connector->display_info.bpc) |
141 | bpc = connector->display_info.bpc; | |
142 | } | |
143 | } | |
144 | break; | |
145 | case DRM_MODE_CONNECTOR_DVID: | |
146 | case DRM_MODE_CONNECTOR_HDMIA: | |
377bd8a9 | 147 | if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
eccea792 AD |
148 | if (connector->display_info.bpc) |
149 | bpc = connector->display_info.bpc; | |
150 | } | |
151 | break; | |
152 | case DRM_MODE_CONNECTOR_DisplayPort: | |
153 | dig_connector = radeon_connector->con_priv; | |
154 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | |
155 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || | |
377bd8a9 | 156 | drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
eccea792 AD |
157 | if (connector->display_info.bpc) |
158 | bpc = connector->display_info.bpc; | |
159 | } | |
160 | break; | |
161 | case DRM_MODE_CONNECTOR_eDP: | |
162 | case DRM_MODE_CONNECTOR_LVDS: | |
163 | if (connector->display_info.bpc) | |
164 | bpc = connector->display_info.bpc; | |
165 | else if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { | |
319d1e14 | 166 | const struct drm_connector_helper_funcs *connector_funcs = |
eccea792 AD |
167 | connector->helper_private; |
168 | struct drm_encoder *encoder = connector_funcs->best_encoder(connector); | |
169 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
170 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
171 | ||
172 | if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) | |
173 | bpc = 6; | |
174 | else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) | |
175 | bpc = 8; | |
176 | } | |
177 | break; | |
178 | } | |
89b92339 | 179 | |
377bd8a9 | 180 | if (drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
89b92339 MK |
181 | /* hdmi deep color only implemented on DCE4+ */ |
182 | if ((bpc > 8) && !ASIC_IS_DCE4(rdev)) { | |
183 | DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 8 bpc.\n", | |
72082093 | 184 | connector->name, bpc); |
89b92339 MK |
185 | bpc = 8; |
186 | } | |
187 | ||
188 | /* | |
189 | * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make | |
190 | * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at | |
191 | * 12 bpc is always supported on hdmi deep color sinks, as this is | |
192 | * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. | |
193 | */ | |
194 | if (bpc > 12) { | |
195 | DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", | |
72082093 | 196 | connector->name, bpc); |
89b92339 MK |
197 | bpc = 12; |
198 | } | |
ea292861 MK |
199 | |
200 | /* Any defined maximum tmds clock limit we must not exceed? */ | |
201 | if (connector->max_tmds_clock > 0) { | |
202 | /* mode_clock is clock in kHz for mode to be modeset on this connector */ | |
203 | mode_clock = radeon_connector->pixelclock_for_modeset; | |
204 | ||
205 | /* Maximum allowable input clock in kHz */ | |
206 | max_tmds_clock = connector->max_tmds_clock * 1000; | |
207 | ||
208 | DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", | |
209 | connector->name, mode_clock, max_tmds_clock); | |
210 | ||
211 | /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ | |
212 | if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { | |
213 | if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && | |
214 | (mode_clock * 5/4 <= max_tmds_clock)) | |
215 | bpc = 10; | |
216 | else | |
217 | bpc = 8; | |
218 | ||
219 | DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", | |
220 | connector->name, bpc); | |
221 | } | |
222 | ||
223 | if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { | |
224 | bpc = 8; | |
225 | DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", | |
226 | connector->name, bpc); | |
227 | } | |
228 | } | |
9f51e2e0 MK |
229 | else if (bpc > 8) { |
230 | /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ | |
231 | DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", | |
232 | connector->name); | |
233 | bpc = 8; | |
234 | } | |
89b92339 MK |
235 | } |
236 | ||
9f51e2e0 MK |
237 | if ((radeon_deep_color == 0) && (bpc > 8)) { |
238 | DRM_DEBUG("%s: Deep color disabled. Set radeon module param deep_color=1 to enable.\n", | |
239 | connector->name); | |
a624f429 | 240 | bpc = 8; |
9f51e2e0 | 241 | } |
a624f429 | 242 | |
89b92339 | 243 | DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", |
72082093 | 244 | connector->name, connector->display_info.bpc, bpc); |
89b92339 | 245 | |
eccea792 AD |
246 | return bpc; |
247 | } | |
248 | ||
771fe6b9 JG |
249 | static void |
250 | radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status) | |
251 | { | |
252 | struct drm_device *dev = connector->dev; | |
253 | struct radeon_device *rdev = dev->dev_private; | |
254 | struct drm_encoder *best_encoder = NULL; | |
255 | struct drm_encoder *encoder = NULL; | |
319d1e14 | 256 | const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; |
771fe6b9 JG |
257 | bool connected; |
258 | int i; | |
259 | ||
260 | best_encoder = connector_funcs->best_encoder(connector); | |
261 | ||
262 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
263 | if (connector->encoder_ids[i] == 0) | |
264 | break; | |
265 | ||
b957f457 RC |
266 | encoder = drm_encoder_find(connector->dev, |
267 | connector->encoder_ids[i]); | |
268 | if (!encoder) | |
771fe6b9 JG |
269 | continue; |
270 | ||
771fe6b9 JG |
271 | if ((encoder == best_encoder) && (status == connector_status_connected)) |
272 | connected = true; | |
273 | else | |
274 | connected = false; | |
275 | ||
276 | if (rdev->is_atom_bios) | |
277 | radeon_atombios_connected_scratch_regs(connector, encoder, connected); | |
278 | else | |
279 | radeon_combios_connected_scratch_regs(connector, encoder, connected); | |
280 | ||
281 | } | |
282 | } | |
283 | ||
1109ca09 | 284 | static struct drm_encoder *radeon_find_encoder(struct drm_connector *connector, int encoder_type) |
445282db | 285 | { |
445282db DA |
286 | struct drm_encoder *encoder; |
287 | int i; | |
288 | ||
289 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
290 | if (connector->encoder_ids[i] == 0) | |
291 | break; | |
292 | ||
b957f457 RC |
293 | encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); |
294 | if (!encoder) | |
445282db DA |
295 | continue; |
296 | ||
445282db DA |
297 | if (encoder->encoder_type == encoder_type) |
298 | return encoder; | |
299 | } | |
300 | return NULL; | |
301 | } | |
302 | ||
377bd8a9 AD |
303 | struct edid *radeon_connector_edid(struct drm_connector *connector) |
304 | { | |
305 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
306 | struct drm_property_blob *edid_blob = connector->edid_blob_ptr; | |
307 | ||
308 | if (radeon_connector->edid) { | |
309 | return radeon_connector->edid; | |
310 | } else if (edid_blob) { | |
311 | struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); | |
312 | if (edid) | |
313 | radeon_connector->edid = edid; | |
314 | } | |
315 | return radeon_connector->edid; | |
316 | } | |
317 | ||
72a5c970 AD |
318 | static void radeon_connector_get_edid(struct drm_connector *connector) |
319 | { | |
320 | struct drm_device *dev = connector->dev; | |
321 | struct radeon_device *rdev = dev->dev_private; | |
322 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
323 | ||
324 | if (radeon_connector->edid) | |
325 | return; | |
326 | ||
327 | /* on hw with routers, select right port */ | |
328 | if (radeon_connector->router.ddc_valid) | |
329 | radeon_router_select_ddc_port(radeon_connector); | |
330 | ||
331 | if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) != | |
332 | ENCODER_OBJECT_ID_NONE) && | |
333 | radeon_connector->ddc_bus->has_aux) { | |
334 | radeon_connector->edid = drm_get_edid(connector, | |
335 | &radeon_connector->ddc_bus->aux.ddc); | |
336 | } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || | |
337 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { | |
338 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; | |
339 | ||
340 | if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || | |
341 | dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && | |
342 | radeon_connector->ddc_bus->has_aux) | |
343 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, | |
344 | &radeon_connector->ddc_bus->aux.ddc); | |
345 | else if (radeon_connector->ddc_bus) | |
346 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, | |
347 | &radeon_connector->ddc_bus->adapter); | |
47eb8f73 LW |
348 | } else if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC && |
349 | connector->connector_type == DRM_MODE_CONNECTOR_LVDS && | |
350 | radeon_connector->ddc_bus) { | |
351 | radeon_connector->edid = drm_get_edid_switcheroo(&radeon_connector->base, | |
352 | &radeon_connector->ddc_bus->adapter); | |
72a5c970 AD |
353 | } else if (radeon_connector->ddc_bus) { |
354 | radeon_connector->edid = drm_get_edid(&radeon_connector->base, | |
355 | &radeon_connector->ddc_bus->adapter); | |
356 | } | |
357 | ||
358 | if (!radeon_connector->edid) { | |
13485794 AD |
359 | /* don't fetch the edid from the vbios if ddc fails and runpm is |
360 | * enabled so we report disconnected. | |
361 | */ | |
362 | if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0)) | |
363 | return; | |
364 | ||
72a5c970 AD |
365 | if (rdev->is_atom_bios) { |
366 | /* some laptops provide a hardcoded edid in rom for LCDs */ | |
367 | if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || | |
368 | (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) | |
369 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); | |
370 | } else { | |
371 | /* some servers provide a hardcoded edid in rom for KVMs */ | |
372 | radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev); | |
373 | } | |
374 | } | |
375 | } | |
376 | ||
377 | static void radeon_connector_free_edid(struct drm_connector *connector) | |
378 | { | |
379 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
380 | ||
381 | if (radeon_connector->edid) { | |
382 | kfree(radeon_connector->edid); | |
383 | radeon_connector->edid = NULL; | |
384 | } | |
385 | } | |
386 | ||
387 | static int radeon_ddc_get_modes(struct drm_connector *connector) | |
388 | { | |
389 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
390 | int ret; | |
391 | ||
392 | if (radeon_connector->edid) { | |
393 | drm_mode_connector_update_edid_property(connector, radeon_connector->edid); | |
394 | ret = drm_add_edid_modes(connector, radeon_connector->edid); | |
395 | drm_edid_to_eld(connector, radeon_connector->edid); | |
396 | return ret; | |
397 | } | |
398 | drm_mode_connector_update_edid_property(connector, NULL); | |
399 | return 0; | |
400 | } | |
401 | ||
1109ca09 | 402 | static struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector) |
771fe6b9 JG |
403 | { |
404 | int enc_id = connector->encoder_ids[0]; | |
771fe6b9 | 405 | /* pick the encoder ids */ |
b957f457 RC |
406 | if (enc_id) |
407 | return drm_encoder_find(connector->dev, enc_id); | |
771fe6b9 JG |
408 | return NULL; |
409 | } | |
410 | ||
da997620 AD |
411 | static void radeon_get_native_mode(struct drm_connector *connector) |
412 | { | |
413 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); | |
414 | struct radeon_encoder *radeon_encoder; | |
415 | ||
416 | if (encoder == NULL) | |
417 | return; | |
418 | ||
419 | radeon_encoder = to_radeon_encoder(encoder); | |
420 | ||
421 | if (!list_empty(&connector->probed_modes)) { | |
422 | struct drm_display_mode *preferred_mode = | |
423 | list_first_entry(&connector->probed_modes, | |
424 | struct drm_display_mode, head); | |
425 | ||
426 | radeon_encoder->native_mode = *preferred_mode; | |
427 | } else { | |
428 | radeon_encoder->native_mode.clock = 0; | |
429 | } | |
430 | } | |
431 | ||
4ce001ab DA |
432 | /* |
433 | * radeon_connector_analog_encoder_conflict_solve | |
434 | * - search for other connectors sharing this encoder | |
435 | * if priority is true, then set them disconnected if this is connected | |
436 | * if priority is false, set us disconnected if they are connected | |
437 | */ | |
438 | static enum drm_connector_status | |
439 | radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector, | |
440 | struct drm_encoder *encoder, | |
441 | enum drm_connector_status current_status, | |
442 | bool priority) | |
443 | { | |
444 | struct drm_device *dev = connector->dev; | |
445 | struct drm_connector *conflict; | |
08d07511 | 446 | struct radeon_connector *radeon_conflict; |
4ce001ab DA |
447 | int i; |
448 | ||
449 | list_for_each_entry(conflict, &dev->mode_config.connector_list, head) { | |
450 | if (conflict == connector) | |
451 | continue; | |
452 | ||
08d07511 | 453 | radeon_conflict = to_radeon_connector(conflict); |
4ce001ab DA |
454 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { |
455 | if (conflict->encoder_ids[i] == 0) | |
456 | break; | |
457 | ||
458 | /* if the IDs match */ | |
459 | if (conflict->encoder_ids[i] == encoder->base.id) { | |
460 | if (conflict->status != connector_status_connected) | |
461 | continue; | |
08d07511 AD |
462 | |
463 | if (radeon_conflict->use_digital) | |
464 | continue; | |
4ce001ab DA |
465 | |
466 | if (priority == true) { | |
72082093 JN |
467 | DRM_DEBUG_KMS("1: conflicting encoders switching off %s\n", |
468 | conflict->name); | |
469 | DRM_DEBUG_KMS("in favor of %s\n", | |
470 | connector->name); | |
4ce001ab DA |
471 | conflict->status = connector_status_disconnected; |
472 | radeon_connector_update_scratch_regs(conflict, connector_status_disconnected); | |
473 | } else { | |
72082093 JN |
474 | DRM_DEBUG_KMS("2: conflicting encoders switching off %s\n", |
475 | connector->name); | |
476 | DRM_DEBUG_KMS("in favor of %s\n", | |
477 | conflict->name); | |
4ce001ab DA |
478 | current_status = connector_status_disconnected; |
479 | } | |
480 | break; | |
481 | } | |
482 | } | |
483 | } | |
484 | return current_status; | |
485 | ||
486 | } | |
487 | ||
771fe6b9 JG |
488 | static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder) |
489 | { | |
490 | struct drm_device *dev = encoder->dev; | |
491 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
492 | struct drm_display_mode *mode = NULL; | |
de2103e4 | 493 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
771fe6b9 | 494 | |
de2103e4 AD |
495 | if (native_mode->hdisplay != 0 && |
496 | native_mode->vdisplay != 0 && | |
497 | native_mode->clock != 0) { | |
fb06ca8f | 498 | mode = drm_mode_duplicate(dev, native_mode); |
771fe6b9 JG |
499 | mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; |
500 | drm_mode_set_name(mode); | |
501 | ||
d9fdaafb | 502 | DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); |
d2efdf6d AD |
503 | } else if (native_mode->hdisplay != 0 && |
504 | native_mode->vdisplay != 0) { | |
505 | /* mac laptops without an edid */ | |
506 | /* Note that this is not necessarily the exact panel mode, | |
507 | * but an approximation based on the cvt formula. For these | |
508 | * systems we should ideally read the mode info out of the | |
509 | * registers or add a mode table, but this works and is much | |
510 | * simpler. | |
511 | */ | |
512 | mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); | |
513 | mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; | |
d9fdaafb | 514 | DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); |
771fe6b9 JG |
515 | } |
516 | return mode; | |
517 | } | |
518 | ||
923f6848 AD |
519 | static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_connector *connector) |
520 | { | |
521 | struct drm_device *dev = encoder->dev; | |
522 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
523 | struct drm_display_mode *mode = NULL; | |
de2103e4 | 524 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
923f6848 AD |
525 | int i; |
526 | struct mode_size { | |
527 | int w; | |
528 | int h; | |
529 | } common_modes[17] = { | |
530 | { 640, 480}, | |
531 | { 720, 480}, | |
532 | { 800, 600}, | |
533 | { 848, 480}, | |
534 | {1024, 768}, | |
535 | {1152, 768}, | |
536 | {1280, 720}, | |
537 | {1280, 800}, | |
538 | {1280, 854}, | |
539 | {1280, 960}, | |
540 | {1280, 1024}, | |
541 | {1440, 900}, | |
542 | {1400, 1050}, | |
543 | {1680, 1050}, | |
544 | {1600, 1200}, | |
545 | {1920, 1080}, | |
546 | {1920, 1200} | |
547 | }; | |
548 | ||
549 | for (i = 0; i < 17; i++) { | |
dfdd6467 AD |
550 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { |
551 | if (common_modes[i].w > 1024 || | |
552 | common_modes[i].h > 768) | |
553 | continue; | |
554 | } | |
923f6848 | 555 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
de2103e4 AD |
556 | if (common_modes[i].w > native_mode->hdisplay || |
557 | common_modes[i].h > native_mode->vdisplay || | |
558 | (common_modes[i].w == native_mode->hdisplay && | |
559 | common_modes[i].h == native_mode->vdisplay)) | |
923f6848 AD |
560 | continue; |
561 | } | |
562 | if (common_modes[i].w < 320 || common_modes[i].h < 200) | |
563 | continue; | |
564 | ||
d50ba256 | 565 | mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); |
923f6848 AD |
566 | drm_mode_probed_add(connector, mode); |
567 | } | |
568 | } | |
569 | ||
1109ca09 | 570 | static int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property, |
771fe6b9 JG |
571 | uint64_t val) |
572 | { | |
445282db DA |
573 | struct drm_device *dev = connector->dev; |
574 | struct radeon_device *rdev = dev->dev_private; | |
575 | struct drm_encoder *encoder; | |
576 | struct radeon_encoder *radeon_encoder; | |
577 | ||
578 | if (property == rdev->mode_info.coherent_mode_property) { | |
579 | struct radeon_encoder_atom_dig *dig; | |
ce227c41 | 580 | bool new_coherent_mode; |
445282db DA |
581 | |
582 | /* need to find digital encoder on connector */ | |
583 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
584 | if (!encoder) | |
585 | return 0; | |
586 | ||
587 | radeon_encoder = to_radeon_encoder(encoder); | |
588 | ||
589 | if (!radeon_encoder->enc_priv) | |
590 | return 0; | |
591 | ||
592 | dig = radeon_encoder->enc_priv; | |
ce227c41 DA |
593 | new_coherent_mode = val ? true : false; |
594 | if (dig->coherent_mode != new_coherent_mode) { | |
595 | dig->coherent_mode = new_coherent_mode; | |
596 | radeon_property_change_mode(&radeon_encoder->base); | |
597 | } | |
445282db DA |
598 | } |
599 | ||
8666c076 AD |
600 | if (property == rdev->mode_info.audio_property) { |
601 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
602 | /* need to find digital encoder on connector */ | |
603 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
604 | if (!encoder) | |
605 | return 0; | |
606 | ||
607 | radeon_encoder = to_radeon_encoder(encoder); | |
608 | ||
609 | if (radeon_connector->audio != val) { | |
610 | radeon_connector->audio = val; | |
611 | radeon_property_change_mode(&radeon_encoder->base); | |
612 | } | |
613 | } | |
614 | ||
6214bb74 AD |
615 | if (property == rdev->mode_info.dither_property) { |
616 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
617 | /* need to find digital encoder on connector */ | |
618 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
619 | if (!encoder) | |
620 | return 0; | |
621 | ||
622 | radeon_encoder = to_radeon_encoder(encoder); | |
623 | ||
624 | if (radeon_connector->dither != val) { | |
625 | radeon_connector->dither = val; | |
626 | radeon_property_change_mode(&radeon_encoder->base); | |
627 | } | |
628 | } | |
629 | ||
5b1714d3 AD |
630 | if (property == rdev->mode_info.underscan_property) { |
631 | /* need to find digital encoder on connector */ | |
632 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
633 | if (!encoder) | |
634 | return 0; | |
635 | ||
636 | radeon_encoder = to_radeon_encoder(encoder); | |
637 | ||
638 | if (radeon_encoder->underscan_type != val) { | |
639 | radeon_encoder->underscan_type = val; | |
640 | radeon_property_change_mode(&radeon_encoder->base); | |
641 | } | |
642 | } | |
643 | ||
5bccf5e3 MG |
644 | if (property == rdev->mode_info.underscan_hborder_property) { |
645 | /* need to find digital encoder on connector */ | |
646 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
647 | if (!encoder) | |
648 | return 0; | |
649 | ||
650 | radeon_encoder = to_radeon_encoder(encoder); | |
651 | ||
652 | if (radeon_encoder->underscan_hborder != val) { | |
653 | radeon_encoder->underscan_hborder = val; | |
654 | radeon_property_change_mode(&radeon_encoder->base); | |
655 | } | |
656 | } | |
657 | ||
658 | if (property == rdev->mode_info.underscan_vborder_property) { | |
659 | /* need to find digital encoder on connector */ | |
660 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
661 | if (!encoder) | |
662 | return 0; | |
663 | ||
664 | radeon_encoder = to_radeon_encoder(encoder); | |
665 | ||
666 | if (radeon_encoder->underscan_vborder != val) { | |
667 | radeon_encoder->underscan_vborder = val; | |
668 | radeon_property_change_mode(&radeon_encoder->base); | |
669 | } | |
670 | } | |
671 | ||
445282db DA |
672 | if (property == rdev->mode_info.tv_std_property) { |
673 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TVDAC); | |
674 | if (!encoder) { | |
675 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_DAC); | |
676 | } | |
677 | ||
678 | if (!encoder) | |
679 | return 0; | |
680 | ||
681 | radeon_encoder = to_radeon_encoder(encoder); | |
682 | if (!radeon_encoder->enc_priv) | |
683 | return 0; | |
643acacf | 684 | if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) { |
445282db DA |
685 | struct radeon_encoder_atom_dac *dac_int; |
686 | dac_int = radeon_encoder->enc_priv; | |
687 | dac_int->tv_std = val; | |
688 | } else { | |
689 | struct radeon_encoder_tv_dac *dac_int; | |
690 | dac_int = radeon_encoder->enc_priv; | |
691 | dac_int->tv_std = val; | |
692 | } | |
693 | radeon_property_change_mode(&radeon_encoder->base); | |
694 | } | |
695 | ||
696 | if (property == rdev->mode_info.load_detect_property) { | |
697 | struct radeon_connector *radeon_connector = | |
698 | to_radeon_connector(connector); | |
699 | ||
700 | if (val == 0) | |
701 | radeon_connector->dac_load_detect = false; | |
702 | else | |
703 | radeon_connector->dac_load_detect = true; | |
704 | } | |
705 | ||
706 | if (property == rdev->mode_info.tmds_pll_property) { | |
707 | struct radeon_encoder_int_tmds *tmds = NULL; | |
708 | bool ret = false; | |
709 | /* need to find digital encoder on connector */ | |
710 | encoder = radeon_find_encoder(connector, DRM_MODE_ENCODER_TMDS); | |
711 | if (!encoder) | |
712 | return 0; | |
713 | ||
714 | radeon_encoder = to_radeon_encoder(encoder); | |
715 | ||
716 | tmds = radeon_encoder->enc_priv; | |
717 | if (!tmds) | |
718 | return 0; | |
719 | ||
720 | if (val == 0) { | |
721 | if (rdev->is_atom_bios) | |
722 | ret = radeon_atombios_get_tmds_info(radeon_encoder, tmds); | |
723 | else | |
724 | ret = radeon_legacy_get_tmds_info_from_combios(radeon_encoder, tmds); | |
725 | } | |
726 | if (val == 1 || ret == false) { | |
727 | radeon_legacy_get_tmds_info_from_table(radeon_encoder, tmds); | |
728 | } | |
729 | radeon_property_change_mode(&radeon_encoder->base); | |
730 | } | |
731 | ||
da997620 AD |
732 | if (property == dev->mode_config.scaling_mode_property) { |
733 | enum radeon_rmx_type rmx_type; | |
734 | ||
735 | if (connector->encoder) | |
736 | radeon_encoder = to_radeon_encoder(connector->encoder); | |
737 | else { | |
319d1e14 | 738 | const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; |
da997620 AD |
739 | radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector)); |
740 | } | |
741 | ||
742 | switch (val) { | |
743 | default: | |
744 | case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; | |
745 | case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; | |
746 | case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; | |
747 | case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; | |
748 | } | |
749 | if (radeon_encoder->rmx_type == rmx_type) | |
750 | return 0; | |
751 | ||
752 | if ((rmx_type != DRM_MODE_SCALE_NONE) && | |
753 | (radeon_encoder->native_mode.clock == 0)) | |
754 | return 0; | |
755 | ||
756 | radeon_encoder->rmx_type = rmx_type; | |
757 | ||
758 | radeon_property_change_mode(&radeon_encoder->base); | |
759 | } | |
760 | ||
643b1f56 AD |
761 | if (property == rdev->mode_info.output_csc_property) { |
762 | if (connector->encoder) | |
763 | radeon_encoder = to_radeon_encoder(connector->encoder); | |
764 | else { | |
16bb079e | 765 | const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; |
643b1f56 AD |
766 | radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector)); |
767 | } | |
768 | ||
769 | if (radeon_encoder->output_csc == val) | |
770 | return 0; | |
771 | ||
772 | radeon_encoder->output_csc = val; | |
773 | ||
774 | if (connector->encoder->crtc) { | |
775 | struct drm_crtc *crtc = connector->encoder->crtc; | |
16bb079e | 776 | const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; |
643b1f56 AD |
777 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
778 | ||
779 | radeon_crtc->output_csc = radeon_encoder->output_csc; | |
780 | ||
781 | (*crtc_funcs->load_lut)(crtc); | |
782 | } | |
783 | } | |
784 | ||
771fe6b9 JG |
785 | return 0; |
786 | } | |
787 | ||
8dfaa8a7 MD |
788 | static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder, |
789 | struct drm_connector *connector) | |
790 | { | |
791 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
de2103e4 | 792 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
13bb9430 MG |
793 | struct drm_display_mode *t, *mode; |
794 | ||
795 | /* If the EDID preferred mode doesn't match the native mode, use it */ | |
796 | list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { | |
797 | if (mode->type & DRM_MODE_TYPE_PREFERRED) { | |
798 | if (mode->hdisplay != native_mode->hdisplay || | |
799 | mode->vdisplay != native_mode->vdisplay) | |
800 | memcpy(native_mode, mode, sizeof(*mode)); | |
801 | } | |
802 | } | |
8dfaa8a7 MD |
803 | |
804 | /* Try to get native mode details from EDID if necessary */ | |
de2103e4 | 805 | if (!native_mode->clock) { |
8dfaa8a7 | 806 | list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { |
de2103e4 AD |
807 | if (mode->hdisplay == native_mode->hdisplay && |
808 | mode->vdisplay == native_mode->vdisplay) { | |
809 | *native_mode = *mode; | |
810 | drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); | |
c5d46b4e | 811 | DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); |
8dfaa8a7 MD |
812 | break; |
813 | } | |
814 | } | |
815 | } | |
13bb9430 | 816 | |
de2103e4 | 817 | if (!native_mode->clock) { |
c5d46b4e | 818 | DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); |
8dfaa8a7 MD |
819 | radeon_encoder->rmx_type = RMX_OFF; |
820 | } | |
821 | } | |
771fe6b9 JG |
822 | |
823 | static int radeon_lvds_get_modes(struct drm_connector *connector) | |
824 | { | |
771fe6b9 JG |
825 | struct drm_encoder *encoder; |
826 | int ret = 0; | |
827 | struct drm_display_mode *mode; | |
828 | ||
72a5c970 AD |
829 | radeon_connector_get_edid(connector); |
830 | ret = radeon_ddc_get_modes(connector); | |
831 | if (ret > 0) { | |
832 | encoder = radeon_best_single_encoder(connector); | |
833 | if (encoder) { | |
834 | radeon_fixup_lvds_native_mode(encoder, connector); | |
835 | /* add scaled modes */ | |
836 | radeon_add_common_modes(encoder, connector); | |
771fe6b9 | 837 | } |
72a5c970 | 838 | return ret; |
771fe6b9 JG |
839 | } |
840 | ||
841 | encoder = radeon_best_single_encoder(connector); | |
842 | if (!encoder) | |
843 | return 0; | |
844 | ||
845 | /* we have no EDID modes */ | |
846 | mode = radeon_fp_native_mode(encoder); | |
847 | if (mode) { | |
848 | ret = 1; | |
849 | drm_mode_probed_add(connector, mode); | |
7a868e18 AD |
850 | /* add the width/height from vbios tables if available */ |
851 | connector->display_info.width_mm = mode->width_mm; | |
852 | connector->display_info.height_mm = mode->height_mm; | |
7747b713 AD |
853 | /* add scaled modes */ |
854 | radeon_add_common_modes(encoder, connector); | |
771fe6b9 | 855 | } |
923f6848 | 856 | |
771fe6b9 JG |
857 | return ret; |
858 | } | |
859 | ||
860 | static int radeon_lvds_mode_valid(struct drm_connector *connector, | |
861 | struct drm_display_mode *mode) | |
862 | { | |
a3fa6320 AD |
863 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); |
864 | ||
865 | if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) | |
866 | return MODE_PANEL; | |
867 | ||
868 | if (encoder) { | |
869 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
870 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | |
871 | ||
872 | /* AVIVO hardware supports downscaling modes larger than the panel | |
873 | * to the panel size, but I'm not sure this is desirable. | |
874 | */ | |
875 | if ((mode->hdisplay > native_mode->hdisplay) || | |
876 | (mode->vdisplay > native_mode->vdisplay)) | |
877 | return MODE_PANEL; | |
878 | ||
879 | /* if scaling is disabled, block non-native modes */ | |
880 | if (radeon_encoder->rmx_type == RMX_OFF) { | |
881 | if ((mode->hdisplay != native_mode->hdisplay) || | |
882 | (mode->vdisplay != native_mode->vdisplay)) | |
883 | return MODE_PANEL; | |
884 | } | |
885 | } | |
886 | ||
771fe6b9 JG |
887 | return MODE_OK; |
888 | } | |
889 | ||
7b334fcb | 890 | static enum drm_connector_status |
930a9e28 | 891 | radeon_lvds_detect(struct drm_connector *connector, bool force) |
771fe6b9 | 892 | { |
13485794 AD |
893 | struct drm_device *dev = connector->dev; |
894 | struct radeon_device *rdev = dev->dev_private; | |
0549a061 | 895 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
2ffb8429 | 896 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); |
0549a061 | 897 | enum drm_connector_status ret = connector_status_disconnected; |
10ebc0bc DA |
898 | int r; |
899 | ||
900 | r = pm_runtime_get_sync(connector->dev->dev); | |
901 | if (r < 0) | |
902 | return connector_status_disconnected; | |
2ffb8429 AD |
903 | |
904 | if (encoder) { | |
905 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
de2103e4 | 906 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; |
2ffb8429 AD |
907 | |
908 | /* check if panel is valid */ | |
de2103e4 | 909 | if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) |
2ffb8429 | 910 | ret = connector_status_connected; |
13485794 AD |
911 | /* don't fetch the edid from the vbios if ddc fails and runpm is |
912 | * enabled so we report disconnected. | |
913 | */ | |
914 | if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0)) | |
915 | ret = connector_status_disconnected; | |
2ffb8429 | 916 | } |
0549a061 AD |
917 | |
918 | /* check for edid as well */ | |
72a5c970 | 919 | radeon_connector_get_edid(connector); |
0294cf4f AD |
920 | if (radeon_connector->edid) |
921 | ret = connector_status_connected; | |
771fe6b9 | 922 | /* check acpi lid status ??? */ |
2ffb8429 | 923 | |
771fe6b9 | 924 | radeon_connector_update_scratch_regs(connector, ret); |
10ebc0bc DA |
925 | pm_runtime_mark_last_busy(connector->dev->dev); |
926 | pm_runtime_put_autosuspend(connector->dev->dev); | |
771fe6b9 JG |
927 | return ret; |
928 | } | |
929 | ||
930 | static void radeon_connector_destroy(struct drm_connector *connector) | |
931 | { | |
932 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
933 | ||
72a5c970 | 934 | radeon_connector_free_edid(connector); |
771fe6b9 | 935 | kfree(radeon_connector->con_priv); |
34ea3d38 | 936 | drm_connector_unregister(connector); |
771fe6b9 JG |
937 | drm_connector_cleanup(connector); |
938 | kfree(connector); | |
939 | } | |
940 | ||
445282db DA |
941 | static int radeon_lvds_set_property(struct drm_connector *connector, |
942 | struct drm_property *property, | |
943 | uint64_t value) | |
944 | { | |
945 | struct drm_device *dev = connector->dev; | |
946 | struct radeon_encoder *radeon_encoder; | |
947 | enum radeon_rmx_type rmx_type; | |
948 | ||
d9fdaafb | 949 | DRM_DEBUG_KMS("\n"); |
445282db DA |
950 | if (property != dev->mode_config.scaling_mode_property) |
951 | return 0; | |
952 | ||
953 | if (connector->encoder) | |
954 | radeon_encoder = to_radeon_encoder(connector->encoder); | |
955 | else { | |
319d1e14 | 956 | const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; |
445282db DA |
957 | radeon_encoder = to_radeon_encoder(connector_funcs->best_encoder(connector)); |
958 | } | |
959 | ||
960 | switch (value) { | |
961 | case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; | |
962 | case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; | |
963 | case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; | |
964 | default: | |
965 | case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; | |
966 | } | |
967 | if (radeon_encoder->rmx_type == rmx_type) | |
968 | return 0; | |
969 | ||
970 | radeon_encoder->rmx_type = rmx_type; | |
971 | ||
972 | radeon_property_change_mode(&radeon_encoder->base); | |
973 | return 0; | |
974 | } | |
975 | ||
976 | ||
1109ca09 | 977 | static const struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = { |
771fe6b9 JG |
978 | .get_modes = radeon_lvds_get_modes, |
979 | .mode_valid = radeon_lvds_mode_valid, | |
980 | .best_encoder = radeon_best_single_encoder, | |
981 | }; | |
982 | ||
1109ca09 | 983 | static const struct drm_connector_funcs radeon_lvds_connector_funcs = { |
771fe6b9 JG |
984 | .dpms = drm_helper_connector_dpms, |
985 | .detect = radeon_lvds_detect, | |
986 | .fill_modes = drm_helper_probe_single_connector_modes, | |
987 | .destroy = radeon_connector_destroy, | |
445282db | 988 | .set_property = radeon_lvds_set_property, |
771fe6b9 JG |
989 | }; |
990 | ||
991 | static int radeon_vga_get_modes(struct drm_connector *connector) | |
992 | { | |
771fe6b9 JG |
993 | int ret; |
994 | ||
72a5c970 AD |
995 | radeon_connector_get_edid(connector); |
996 | ret = radeon_ddc_get_modes(connector); | |
771fe6b9 | 997 | |
da997620 AD |
998 | radeon_get_native_mode(connector); |
999 | ||
771fe6b9 JG |
1000 | return ret; |
1001 | } | |
1002 | ||
1003 | static int radeon_vga_mode_valid(struct drm_connector *connector, | |
1004 | struct drm_display_mode *mode) | |
1005 | { | |
b20f9bef AD |
1006 | struct drm_device *dev = connector->dev; |
1007 | struct radeon_device *rdev = dev->dev_private; | |
1008 | ||
a3fa6320 | 1009 | /* XXX check mode bandwidth */ |
b20f9bef AD |
1010 | |
1011 | if ((mode->clock / 10) > rdev->clock.max_pixel_clock) | |
1012 | return MODE_CLOCK_HIGH; | |
1013 | ||
771fe6b9 JG |
1014 | return MODE_OK; |
1015 | } | |
1016 | ||
7b334fcb | 1017 | static enum drm_connector_status |
930a9e28 | 1018 | radeon_vga_detect(struct drm_connector *connector, bool force) |
771fe6b9 | 1019 | { |
fafcf94e AD |
1020 | struct drm_device *dev = connector->dev; |
1021 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 JG |
1022 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1023 | struct drm_encoder *encoder; | |
319d1e14 | 1024 | const struct drm_encoder_helper_funcs *encoder_funcs; |
4b9d2a21 | 1025 | bool dret = false; |
771fe6b9 | 1026 | enum drm_connector_status ret = connector_status_disconnected; |
10ebc0bc DA |
1027 | int r; |
1028 | ||
1029 | r = pm_runtime_get_sync(connector->dev->dev); | |
1030 | if (r < 0) | |
1031 | return connector_status_disconnected; | |
771fe6b9 | 1032 | |
4ce001ab DA |
1033 | encoder = radeon_best_single_encoder(connector); |
1034 | if (!encoder) | |
1035 | ret = connector_status_disconnected; | |
1036 | ||
eb6b6d7c | 1037 | if (radeon_connector->ddc_bus) |
0a9069d3 | 1038 | dret = radeon_ddc_probe(radeon_connector, false); |
0294cf4f | 1039 | if (dret) { |
d0d0a225 | 1040 | radeon_connector->detected_by_load = false; |
72a5c970 AD |
1041 | radeon_connector_free_edid(connector); |
1042 | radeon_connector_get_edid(connector); | |
0294cf4f AD |
1043 | |
1044 | if (!radeon_connector->edid) { | |
f82f5f3a | 1045 | DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", |
72082093 | 1046 | connector->name); |
f82f5f3a | 1047 | ret = connector_status_connected; |
0294cf4f | 1048 | } else { |
72a5c970 AD |
1049 | radeon_connector->use_digital = |
1050 | !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); | |
0294cf4f AD |
1051 | |
1052 | /* some oems have boards with separate digital and analog connectors | |
1053 | * with a shared ddc line (often vga + hdmi) | |
1054 | */ | |
1055 | if (radeon_connector->use_digital && radeon_connector->shared_ddc) { | |
72a5c970 | 1056 | radeon_connector_free_edid(connector); |
0294cf4f | 1057 | ret = connector_status_disconnected; |
72a5c970 | 1058 | } else { |
0294cf4f | 1059 | ret = connector_status_connected; |
72a5c970 | 1060 | } |
0294cf4f AD |
1061 | } |
1062 | } else { | |
c3cceedd DA |
1063 | |
1064 | /* if we aren't forcing don't do destructive polling */ | |
d0d0a225 AD |
1065 | if (!force) { |
1066 | /* only return the previous status if we last | |
1067 | * detected a monitor via load. | |
1068 | */ | |
1069 | if (radeon_connector->detected_by_load) | |
10ebc0bc DA |
1070 | ret = connector->status; |
1071 | goto out; | |
d0d0a225 | 1072 | } |
c3cceedd | 1073 | |
d8a7f792 | 1074 | if (radeon_connector->dac_load_detect && encoder) { |
445282db DA |
1075 | encoder_funcs = encoder->helper_private; |
1076 | ret = encoder_funcs->detect(encoder, connector); | |
34076446 | 1077 | if (ret != connector_status_disconnected) |
d0d0a225 | 1078 | radeon_connector->detected_by_load = true; |
445282db | 1079 | } |
771fe6b9 JG |
1080 | } |
1081 | ||
4ce001ab DA |
1082 | if (ret == connector_status_connected) |
1083 | ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true); | |
fafcf94e AD |
1084 | |
1085 | /* RN50 and some RV100 asics in servers often have a hardcoded EDID in the | |
1086 | * vbios to deal with KVMs. If we have one and are not able to detect a monitor | |
1087 | * by other means, assume the CRT is connected and use that EDID. | |
1088 | */ | |
1089 | if ((!rdev->is_atom_bios) && | |
1090 | (ret == connector_status_disconnected) && | |
1091 | rdev->mode_info.bios_hardcoded_edid_size) { | |
1092 | ret = connector_status_connected; | |
1093 | } | |
1094 | ||
771fe6b9 | 1095 | radeon_connector_update_scratch_regs(connector, ret); |
10ebc0bc DA |
1096 | |
1097 | out: | |
1098 | pm_runtime_mark_last_busy(connector->dev->dev); | |
1099 | pm_runtime_put_autosuspend(connector->dev->dev); | |
1100 | ||
771fe6b9 JG |
1101 | return ret; |
1102 | } | |
1103 | ||
1109ca09 | 1104 | static const struct drm_connector_helper_funcs radeon_vga_connector_helper_funcs = { |
771fe6b9 JG |
1105 | .get_modes = radeon_vga_get_modes, |
1106 | .mode_valid = radeon_vga_mode_valid, | |
1107 | .best_encoder = radeon_best_single_encoder, | |
1108 | }; | |
1109 | ||
1109ca09 | 1110 | static const struct drm_connector_funcs radeon_vga_connector_funcs = { |
771fe6b9 JG |
1111 | .dpms = drm_helper_connector_dpms, |
1112 | .detect = radeon_vga_detect, | |
1113 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1114 | .destroy = radeon_connector_destroy, | |
1115 | .set_property = radeon_connector_set_property, | |
1116 | }; | |
1117 | ||
4ce001ab DA |
1118 | static int radeon_tv_get_modes(struct drm_connector *connector) |
1119 | { | |
1120 | struct drm_device *dev = connector->dev; | |
923f6848 | 1121 | struct radeon_device *rdev = dev->dev_private; |
4ce001ab | 1122 | struct drm_display_mode *tv_mode; |
923f6848 | 1123 | struct drm_encoder *encoder; |
4ce001ab | 1124 | |
923f6848 AD |
1125 | encoder = radeon_best_single_encoder(connector); |
1126 | if (!encoder) | |
1127 | return 0; | |
4ce001ab | 1128 | |
923f6848 AD |
1129 | /* avivo chips can scale any mode */ |
1130 | if (rdev->family >= CHIP_RS600) | |
1131 | /* add scaled modes */ | |
1132 | radeon_add_common_modes(encoder, connector); | |
1133 | else { | |
1134 | /* only 800x600 is supported right now on pre-avivo chips */ | |
d50ba256 | 1135 | tv_mode = drm_cvt_mode(dev, 800, 600, 60, false, false, false); |
923f6848 AD |
1136 | tv_mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; |
1137 | drm_mode_probed_add(connector, tv_mode); | |
1138 | } | |
4ce001ab DA |
1139 | return 1; |
1140 | } | |
1141 | ||
1142 | static int radeon_tv_mode_valid(struct drm_connector *connector, | |
1143 | struct drm_display_mode *mode) | |
1144 | { | |
a3fa6320 AD |
1145 | if ((mode->hdisplay > 1024) || (mode->vdisplay > 768)) |
1146 | return MODE_CLOCK_RANGE; | |
4ce001ab DA |
1147 | return MODE_OK; |
1148 | } | |
1149 | ||
7b334fcb | 1150 | static enum drm_connector_status |
930a9e28 | 1151 | radeon_tv_detect(struct drm_connector *connector, bool force) |
4ce001ab DA |
1152 | { |
1153 | struct drm_encoder *encoder; | |
319d1e14 | 1154 | const struct drm_encoder_helper_funcs *encoder_funcs; |
445282db DA |
1155 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1156 | enum drm_connector_status ret = connector_status_disconnected; | |
10ebc0bc | 1157 | int r; |
445282db DA |
1158 | |
1159 | if (!radeon_connector->dac_load_detect) | |
1160 | return ret; | |
4ce001ab | 1161 | |
10ebc0bc DA |
1162 | r = pm_runtime_get_sync(connector->dev->dev); |
1163 | if (r < 0) | |
1164 | return connector_status_disconnected; | |
1165 | ||
4ce001ab DA |
1166 | encoder = radeon_best_single_encoder(connector); |
1167 | if (!encoder) | |
1168 | ret = connector_status_disconnected; | |
1169 | else { | |
1170 | encoder_funcs = encoder->helper_private; | |
1171 | ret = encoder_funcs->detect(encoder, connector); | |
1172 | } | |
1173 | if (ret == connector_status_connected) | |
1174 | ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, false); | |
1175 | radeon_connector_update_scratch_regs(connector, ret); | |
10ebc0bc DA |
1176 | pm_runtime_mark_last_busy(connector->dev->dev); |
1177 | pm_runtime_put_autosuspend(connector->dev->dev); | |
4ce001ab DA |
1178 | return ret; |
1179 | } | |
1180 | ||
1109ca09 | 1181 | static const struct drm_connector_helper_funcs radeon_tv_connector_helper_funcs = { |
4ce001ab DA |
1182 | .get_modes = radeon_tv_get_modes, |
1183 | .mode_valid = radeon_tv_mode_valid, | |
1184 | .best_encoder = radeon_best_single_encoder, | |
1185 | }; | |
1186 | ||
1109ca09 | 1187 | static const struct drm_connector_funcs radeon_tv_connector_funcs = { |
4ce001ab DA |
1188 | .dpms = drm_helper_connector_dpms, |
1189 | .detect = radeon_tv_detect, | |
1190 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1191 | .destroy = radeon_connector_destroy, | |
1192 | .set_property = radeon_connector_set_property, | |
1193 | }; | |
1194 | ||
11fe1266 TU |
1195 | static bool radeon_check_hpd_status_unchanged(struct drm_connector *connector) |
1196 | { | |
1197 | struct drm_device *dev = connector->dev; | |
1198 | struct radeon_device *rdev = dev->dev_private; | |
1199 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1200 | enum drm_connector_status status; | |
1201 | ||
1202 | /* We only trust HPD on R600 and newer ASICS. */ | |
1203 | if (rdev->family >= CHIP_R600 | |
1204 | && radeon_connector->hpd.hpd != RADEON_HPD_NONE) { | |
1205 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) | |
1206 | status = connector_status_connected; | |
1207 | else | |
1208 | status = connector_status_disconnected; | |
1209 | if (connector->status == status) | |
1210 | return true; | |
1211 | } | |
1212 | ||
1213 | return false; | |
1214 | } | |
1215 | ||
4ce001ab DA |
1216 | /* |
1217 | * DVI is complicated | |
1218 | * Do a DDC probe, if DDC probe passes, get the full EDID so | |
1219 | * we can do analog/digital monitor detection at this point. | |
1220 | * If the monitor is an analog monitor or we got no DDC, | |
1221 | * we need to find the DAC encoder object for this connector. | |
1222 | * If we got no DDC, we do load detection on the DAC encoder object. | |
1223 | * If we got analog DDC or load detection passes on the DAC encoder | |
1224 | * we have to check if this analog encoder is shared with anyone else (TV) | |
1225 | * if its shared we have to set the other connector to disconnected. | |
1226 | */ | |
7b334fcb | 1227 | static enum drm_connector_status |
930a9e28 | 1228 | radeon_dvi_detect(struct drm_connector *connector, bool force) |
771fe6b9 | 1229 | { |
fafcf94e AD |
1230 | struct drm_device *dev = connector->dev; |
1231 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 | 1232 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
4ce001ab | 1233 | struct drm_encoder *encoder = NULL; |
319d1e14 | 1234 | const struct drm_encoder_helper_funcs *encoder_funcs; |
10ebc0bc | 1235 | int i, r; |
771fe6b9 | 1236 | enum drm_connector_status ret = connector_status_disconnected; |
fc87f13b | 1237 | bool dret = false, broken_edid = false; |
771fe6b9 | 1238 | |
10ebc0bc DA |
1239 | r = pm_runtime_get_sync(connector->dev->dev); |
1240 | if (r < 0) | |
1241 | return connector_status_disconnected; | |
1242 | ||
cb5d4166 L |
1243 | if (radeon_connector->detected_hpd_without_ddc) { |
1244 | force = true; | |
1245 | radeon_connector->detected_hpd_without_ddc = false; | |
1246 | } | |
1247 | ||
10ebc0bc DA |
1248 | if (!force && radeon_check_hpd_status_unchanged(connector)) { |
1249 | ret = connector->status; | |
1250 | goto exit; | |
1251 | } | |
11fe1266 | 1252 | |
cb5d4166 | 1253 | if (radeon_connector->ddc_bus) { |
0a9069d3 | 1254 | dret = radeon_ddc_probe(radeon_connector, false); |
cb5d4166 L |
1255 | |
1256 | /* Sometimes the pins required for the DDC probe on DVI | |
1257 | * connectors don't make contact at the same time that the ones | |
1258 | * for HPD do. If the DDC probe fails even though we had an HPD | |
1259 | * signal, try again later */ | |
1260 | if (!dret && !force && | |
1261 | connector->status != connector_status_connected) { | |
1262 | DRM_DEBUG_KMS("hpd detected without ddc, retrying in 1 second\n"); | |
1263 | radeon_connector->detected_hpd_without_ddc = true; | |
1264 | schedule_delayed_work(&rdev->hotplug_work, | |
1265 | msecs_to_jiffies(1000)); | |
1266 | goto exit; | |
1267 | } | |
1268 | } | |
4ce001ab | 1269 | if (dret) { |
d0d0a225 | 1270 | radeon_connector->detected_by_load = false; |
72a5c970 AD |
1271 | radeon_connector_free_edid(connector); |
1272 | radeon_connector_get_edid(connector); | |
4ce001ab DA |
1273 | |
1274 | if (!radeon_connector->edid) { | |
f82f5f3a | 1275 | DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", |
72082093 | 1276 | connector->name); |
4a9a8b71 DA |
1277 | /* rs690 seems to have a problem with connectors not existing and always |
1278 | * return a block of 0's. If we see this just stop polling on this output */ | |
72a5c970 AD |
1279 | if ((rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) && |
1280 | radeon_connector->base.null_edid_counter) { | |
4a9a8b71 | 1281 | ret = connector_status_disconnected; |
72082093 JN |
1282 | DRM_ERROR("%s: detected RS690 floating bus bug, stopping ddc detect\n", |
1283 | connector->name); | |
4a9a8b71 | 1284 | radeon_connector->ddc_bus = NULL; |
fc87f13b EE |
1285 | } else { |
1286 | ret = connector_status_connected; | |
1287 | broken_edid = true; /* defer use_digital to later */ | |
4a9a8b71 | 1288 | } |
4ce001ab | 1289 | } else { |
72a5c970 AD |
1290 | radeon_connector->use_digital = |
1291 | !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); | |
4ce001ab | 1292 | |
0294cf4f AD |
1293 | /* some oems have boards with separate digital and analog connectors |
1294 | * with a shared ddc line (often vga + hdmi) | |
1295 | */ | |
1296 | if ((!radeon_connector->use_digital) && radeon_connector->shared_ddc) { | |
72a5c970 | 1297 | radeon_connector_free_edid(connector); |
0294cf4f | 1298 | ret = connector_status_disconnected; |
72a5c970 | 1299 | } else { |
0294cf4f | 1300 | ret = connector_status_connected; |
72a5c970 | 1301 | } |
42f14c4b AD |
1302 | /* This gets complicated. We have boards with VGA + HDMI with a |
1303 | * shared DDC line and we have boards with DVI-D + HDMI with a shared | |
1304 | * DDC line. The latter is more complex because with DVI<->HDMI adapters | |
1305 | * you don't really know what's connected to which port as both are digital. | |
71407c46 | 1306 | */ |
d3932d6c | 1307 | if (radeon_connector->shared_ddc && (ret == connector_status_connected)) { |
71407c46 AD |
1308 | struct drm_connector *list_connector; |
1309 | struct radeon_connector *list_radeon_connector; | |
1310 | list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { | |
1311 | if (connector == list_connector) | |
1312 | continue; | |
1313 | list_radeon_connector = to_radeon_connector(list_connector); | |
b2ea4aa6 AD |
1314 | if (list_radeon_connector->shared_ddc && |
1315 | (list_radeon_connector->ddc_bus->rec.i2c_id == | |
1316 | radeon_connector->ddc_bus->rec.i2c_id)) { | |
42f14c4b AD |
1317 | /* cases where both connectors are digital */ |
1318 | if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { | |
1319 | /* hpd is our only option in this case */ | |
1320 | if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) { | |
72a5c970 | 1321 | radeon_connector_free_edid(connector); |
71407c46 AD |
1322 | ret = connector_status_disconnected; |
1323 | } | |
1324 | } | |
1325 | } | |
1326 | } | |
1327 | } | |
4ce001ab DA |
1328 | } |
1329 | } | |
1330 | ||
1331 | if ((ret == connector_status_connected) && (radeon_connector->use_digital == true)) | |
1332 | goto out; | |
1333 | ||
5f0a2612 AD |
1334 | /* DVI-D and HDMI-A are digital only */ |
1335 | if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || | |
1336 | (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) | |
1337 | goto out; | |
1338 | ||
d0d0a225 | 1339 | /* if we aren't forcing don't do destructive polling */ |
c3cceedd | 1340 | if (!force) { |
d0d0a225 AD |
1341 | /* only return the previous status if we last |
1342 | * detected a monitor via load. | |
1343 | */ | |
1344 | if (radeon_connector->detected_by_load) | |
1345 | ret = connector->status; | |
c3cceedd DA |
1346 | goto out; |
1347 | } | |
1348 | ||
4ce001ab | 1349 | /* find analog encoder */ |
445282db DA |
1350 | if (radeon_connector->dac_load_detect) { |
1351 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
1352 | if (connector->encoder_ids[i] == 0) | |
1353 | break; | |
771fe6b9 | 1354 | |
b957f457 RC |
1355 | encoder = drm_encoder_find(connector->dev, |
1356 | connector->encoder_ids[i]); | |
1357 | if (!encoder) | |
445282db | 1358 | continue; |
771fe6b9 | 1359 | |
e3632507 | 1360 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && |
e00e8b5e AD |
1361 | encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) |
1362 | continue; | |
1363 | ||
445282db DA |
1364 | encoder_funcs = encoder->helper_private; |
1365 | if (encoder_funcs->detect) { | |
fc87f13b EE |
1366 | if (!broken_edid) { |
1367 | if (ret != connector_status_connected) { | |
1368 | /* deal with analog monitors without DDC */ | |
1369 | ret = encoder_funcs->detect(encoder, connector); | |
1370 | if (ret == connector_status_connected) { | |
1371 | radeon_connector->use_digital = false; | |
1372 | } | |
1373 | if (ret != connector_status_disconnected) | |
1374 | radeon_connector->detected_by_load = true; | |
445282db | 1375 | } |
fc87f13b EE |
1376 | } else { |
1377 | enum drm_connector_status lret; | |
1378 | /* assume digital unless load detected otherwise */ | |
1379 | radeon_connector->use_digital = true; | |
1380 | lret = encoder_funcs->detect(encoder, connector); | |
1381 | DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); | |
1382 | if (lret == connector_status_connected) | |
1383 | radeon_connector->use_digital = false; | |
771fe6b9 | 1384 | } |
445282db | 1385 | break; |
771fe6b9 JG |
1386 | } |
1387 | } | |
1388 | } | |
1389 | ||
4ce001ab DA |
1390 | if ((ret == connector_status_connected) && (radeon_connector->use_digital == false) && |
1391 | encoder) { | |
1392 | ret = radeon_connector_analog_encoder_conflict_solve(connector, encoder, ret, true); | |
1393 | } | |
1394 | ||
fafcf94e AD |
1395 | /* RN50 and some RV100 asics in servers often have a hardcoded EDID in the |
1396 | * vbios to deal with KVMs. If we have one and are not able to detect a monitor | |
1397 | * by other means, assume the DFP is connected and use that EDID. In most | |
1398 | * cases the DVI port is actually a virtual KVM port connected to the service | |
1399 | * processor. | |
1400 | */ | |
a09d431f | 1401 | out: |
fafcf94e AD |
1402 | if ((!rdev->is_atom_bios) && |
1403 | (ret == connector_status_disconnected) && | |
1404 | rdev->mode_info.bios_hardcoded_edid_size) { | |
1405 | radeon_connector->use_digital = true; | |
1406 | ret = connector_status_connected; | |
1407 | } | |
1408 | ||
771fe6b9 JG |
1409 | /* updated in get modes as well since we need to know if it's analog or digital */ |
1410 | radeon_connector_update_scratch_regs(connector, ret); | |
10ebc0bc | 1411 | |
d0ea397e AD |
1412 | if ((radeon_audio != 0) && radeon_connector->use_digital) { |
1413 | const struct drm_connector_helper_funcs *connector_funcs = | |
1414 | connector->helper_private; | |
1415 | ||
1416 | encoder = connector_funcs->best_encoder(connector); | |
1417 | if (encoder && (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)) { | |
1418 | radeon_connector_get_edid(connector); | |
1419 | radeon_audio_detect(connector, encoder, ret); | |
1420 | } | |
1421 | } | |
1a626b68 | 1422 | |
10ebc0bc DA |
1423 | exit: |
1424 | pm_runtime_mark_last_busy(connector->dev->dev); | |
1425 | pm_runtime_put_autosuspend(connector->dev->dev); | |
1426 | ||
771fe6b9 JG |
1427 | return ret; |
1428 | } | |
1429 | ||
1430 | /* okay need to be smart in here about which encoder to pick */ | |
1109ca09 | 1431 | static struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector) |
771fe6b9 JG |
1432 | { |
1433 | int enc_id = connector->encoder_ids[0]; | |
1434 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
771fe6b9 JG |
1435 | struct drm_encoder *encoder; |
1436 | int i; | |
1437 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
1438 | if (connector->encoder_ids[i] == 0) | |
1439 | break; | |
1440 | ||
b957f457 RC |
1441 | encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); |
1442 | if (!encoder) | |
771fe6b9 JG |
1443 | continue; |
1444 | ||
4ce001ab | 1445 | if (radeon_connector->use_digital == true) { |
771fe6b9 JG |
1446 | if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) |
1447 | return encoder; | |
1448 | } else { | |
1449 | if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || | |
1450 | encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) | |
1451 | return encoder; | |
1452 | } | |
1453 | } | |
1454 | ||
1455 | /* see if we have a default encoder TODO */ | |
1456 | ||
1457 | /* then check use digitial */ | |
1458 | /* pick the first one */ | |
b957f457 RC |
1459 | if (enc_id) |
1460 | return drm_encoder_find(connector->dev, enc_id); | |
771fe6b9 JG |
1461 | return NULL; |
1462 | } | |
1463 | ||
d50ba256 DA |
1464 | static void radeon_dvi_force(struct drm_connector *connector) |
1465 | { | |
1466 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1467 | if (connector->force == DRM_FORCE_ON) | |
1468 | radeon_connector->use_digital = false; | |
1469 | if (connector->force == DRM_FORCE_ON_DIGITAL) | |
1470 | radeon_connector->use_digital = true; | |
1471 | } | |
1472 | ||
a3fa6320 AD |
1473 | static int radeon_dvi_mode_valid(struct drm_connector *connector, |
1474 | struct drm_display_mode *mode) | |
1475 | { | |
1b24203e AD |
1476 | struct drm_device *dev = connector->dev; |
1477 | struct radeon_device *rdev = dev->dev_private; | |
a3fa6320 AD |
1478 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1479 | ||
1480 | /* XXX check mode bandwidth */ | |
1481 | ||
1b24203e AD |
1482 | /* clocks over 135 MHz have heat issues with DVI on RV100 */ |
1483 | if (radeon_connector->use_digital && | |
1484 | (rdev->family == CHIP_RV100) && | |
1485 | (mode->clock > 135000)) | |
1486 | return MODE_CLOCK_HIGH; | |
1487 | ||
a3fa6320 AD |
1488 | if (radeon_connector->use_digital && (mode->clock > 165000)) { |
1489 | if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || | |
1490 | (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || | |
1491 | (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) | |
1492 | return MODE_OK; | |
377bd8a9 | 1493 | else if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
f2263fc7 AD |
1494 | /* HDMI 1.3+ supports max clock of 340 Mhz */ |
1495 | if (mode->clock > 340000) | |
e1e84017 | 1496 | return MODE_CLOCK_HIGH; |
f2263fc7 AD |
1497 | else |
1498 | return MODE_OK; | |
1499 | } else { | |
a3fa6320 | 1500 | return MODE_CLOCK_HIGH; |
f2263fc7 | 1501 | } |
a3fa6320 | 1502 | } |
b20f9bef AD |
1503 | |
1504 | /* check against the max pixel clock */ | |
1505 | if ((mode->clock / 10) > rdev->clock.max_pixel_clock) | |
1506 | return MODE_CLOCK_HIGH; | |
1507 | ||
a3fa6320 AD |
1508 | return MODE_OK; |
1509 | } | |
1510 | ||
1109ca09 | 1511 | static const struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = { |
3e22920f | 1512 | .get_modes = radeon_vga_get_modes, |
a3fa6320 | 1513 | .mode_valid = radeon_dvi_mode_valid, |
771fe6b9 JG |
1514 | .best_encoder = radeon_dvi_encoder, |
1515 | }; | |
1516 | ||
1109ca09 | 1517 | static const struct drm_connector_funcs radeon_dvi_connector_funcs = { |
771fe6b9 JG |
1518 | .dpms = drm_helper_connector_dpms, |
1519 | .detect = radeon_dvi_detect, | |
1520 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1521 | .set_property = radeon_connector_set_property, | |
1522 | .destroy = radeon_connector_destroy, | |
d50ba256 | 1523 | .force = radeon_dvi_force, |
771fe6b9 JG |
1524 | }; |
1525 | ||
746c1aa4 DA |
1526 | static int radeon_dp_get_modes(struct drm_connector *connector) |
1527 | { | |
1528 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
8b834852 | 1529 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
591a10e1 | 1530 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); |
746c1aa4 DA |
1531 | int ret; |
1532 | ||
f89931f3 AD |
1533 | if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || |
1534 | (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { | |
d291767b AD |
1535 | struct drm_display_mode *mode; |
1536 | ||
2b69ffb9 AD |
1537 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1538 | if (!radeon_dig_connector->edp_on) | |
1539 | atombios_set_edp_panel_power(connector, | |
1540 | ATOM_TRANSMITTER_ACTION_POWER_ON); | |
72a5c970 AD |
1541 | radeon_connector_get_edid(connector); |
1542 | ret = radeon_ddc_get_modes(connector); | |
2b69ffb9 AD |
1543 | if (!radeon_dig_connector->edp_on) |
1544 | atombios_set_edp_panel_power(connector, | |
1545 | ATOM_TRANSMITTER_ACTION_POWER_OFF); | |
1546 | } else { | |
1547 | /* need to setup ddc on the bridge */ | |
1548 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) != | |
1549 | ENCODER_OBJECT_ID_NONE) { | |
1550 | if (encoder) | |
1551 | radeon_atom_ext_encoder_setup_ddc(encoder); | |
1552 | } | |
72a5c970 AD |
1553 | radeon_connector_get_edid(connector); |
1554 | ret = radeon_ddc_get_modes(connector); | |
2b69ffb9 | 1555 | } |
d291767b AD |
1556 | |
1557 | if (ret > 0) { | |
d291767b AD |
1558 | if (encoder) { |
1559 | radeon_fixup_lvds_native_mode(encoder, connector); | |
1560 | /* add scaled modes */ | |
1561 | radeon_add_common_modes(encoder, connector); | |
1562 | } | |
1563 | return ret; | |
1564 | } | |
1565 | ||
d291767b AD |
1566 | if (!encoder) |
1567 | return 0; | |
1568 | ||
1569 | /* we have no EDID modes */ | |
1570 | mode = radeon_fp_native_mode(encoder); | |
1571 | if (mode) { | |
1572 | ret = 1; | |
1573 | drm_mode_probed_add(connector, mode); | |
1574 | /* add the width/height from vbios tables if available */ | |
1575 | connector->display_info.width_mm = mode->width_mm; | |
1576 | connector->display_info.height_mm = mode->height_mm; | |
1577 | /* add scaled modes */ | |
1578 | radeon_add_common_modes(encoder, connector); | |
1579 | } | |
591a10e1 AD |
1580 | } else { |
1581 | /* need to setup ddc on the bridge */ | |
1d33e1fc AD |
1582 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) != |
1583 | ENCODER_OBJECT_ID_NONE) { | |
591a10e1 AD |
1584 | if (encoder) |
1585 | radeon_atom_ext_encoder_setup_ddc(encoder); | |
1586 | } | |
72a5c970 AD |
1587 | radeon_connector_get_edid(connector); |
1588 | ret = radeon_ddc_get_modes(connector); | |
da997620 AD |
1589 | |
1590 | radeon_get_native_mode(connector); | |
591a10e1 | 1591 | } |
8b834852 | 1592 | |
746c1aa4 DA |
1593 | return ret; |
1594 | } | |
1595 | ||
1d33e1fc | 1596 | u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) |
d7fa8bb3 | 1597 | { |
d7fa8bb3 AD |
1598 | struct drm_encoder *encoder; |
1599 | struct radeon_encoder *radeon_encoder; | |
1600 | int i; | |
d7fa8bb3 AD |
1601 | |
1602 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
1603 | if (connector->encoder_ids[i] == 0) | |
1604 | break; | |
1605 | ||
b957f457 RC |
1606 | encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); |
1607 | if (!encoder) | |
d7fa8bb3 AD |
1608 | continue; |
1609 | ||
d7fa8bb3 AD |
1610 | radeon_encoder = to_radeon_encoder(encoder); |
1611 | ||
1612 | switch (radeon_encoder->encoder_id) { | |
1613 | case ENCODER_OBJECT_ID_TRAVIS: | |
1614 | case ENCODER_OBJECT_ID_NUTMEG: | |
1d33e1fc | 1615 | return radeon_encoder->encoder_id; |
d7fa8bb3 AD |
1616 | default: |
1617 | break; | |
1618 | } | |
1619 | } | |
1620 | ||
1d33e1fc | 1621 | return ENCODER_OBJECT_ID_NONE; |
d7fa8bb3 AD |
1622 | } |
1623 | ||
ebdea82d | 1624 | static bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector) |
d7fa8bb3 | 1625 | { |
d7fa8bb3 AD |
1626 | struct drm_encoder *encoder; |
1627 | struct radeon_encoder *radeon_encoder; | |
1628 | int i; | |
1629 | bool found = false; | |
1630 | ||
1631 | for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { | |
1632 | if (connector->encoder_ids[i] == 0) | |
1633 | break; | |
1634 | ||
b957f457 RC |
1635 | encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]); |
1636 | if (!encoder) | |
d7fa8bb3 AD |
1637 | continue; |
1638 | ||
d7fa8bb3 AD |
1639 | radeon_encoder = to_radeon_encoder(encoder); |
1640 | if (radeon_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) | |
1641 | found = true; | |
1642 | } | |
1643 | ||
1644 | return found; | |
1645 | } | |
1646 | ||
1647 | bool radeon_connector_is_dp12_capable(struct drm_connector *connector) | |
1648 | { | |
1649 | struct drm_device *dev = connector->dev; | |
1650 | struct radeon_device *rdev = dev->dev_private; | |
1651 | ||
1652 | if (ASIC_IS_DCE5(rdev) && | |
af5d3653 | 1653 | (rdev->clock.default_dispclk >= 53900) && |
d7fa8bb3 AD |
1654 | radeon_connector_encoder_is_hbr2(connector)) { |
1655 | return true; | |
1656 | } | |
1657 | ||
1658 | return false; | |
1659 | } | |
1660 | ||
7b334fcb | 1661 | static enum drm_connector_status |
930a9e28 | 1662 | radeon_dp_detect(struct drm_connector *connector, bool force) |
746c1aa4 | 1663 | { |
f8d0edde AD |
1664 | struct drm_device *dev = connector->dev; |
1665 | struct radeon_device *rdev = dev->dev_private; | |
746c1aa4 | 1666 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
746c1aa4 | 1667 | enum drm_connector_status ret = connector_status_disconnected; |
4143e919 | 1668 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
591a10e1 | 1669 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); |
10ebc0bc | 1670 | int r; |
746c1aa4 | 1671 | |
9843ead0 DA |
1672 | if (radeon_dig_connector->is_mst) |
1673 | return connector_status_disconnected; | |
1674 | ||
10ebc0bc DA |
1675 | r = pm_runtime_get_sync(connector->dev->dev); |
1676 | if (r < 0) | |
1677 | return connector_status_disconnected; | |
1678 | ||
1679 | if (!force && radeon_check_hpd_status_unchanged(connector)) { | |
1680 | ret = connector->status; | |
1681 | goto out; | |
1682 | } | |
11fe1266 | 1683 | |
72a5c970 | 1684 | radeon_connector_free_edid(connector); |
746c1aa4 | 1685 | |
f89931f3 AD |
1686 | if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || |
1687 | (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { | |
d291767b AD |
1688 | if (encoder) { |
1689 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1690 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | |
1691 | ||
1692 | /* check if panel is valid */ | |
1693 | if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) | |
1694 | ret = connector_status_connected; | |
13485794 AD |
1695 | /* don't fetch the edid from the vbios if ddc fails and runpm is |
1696 | * enabled so we report disconnected. | |
1697 | */ | |
1698 | if ((rdev->flags & RADEON_IS_PX) && (radeon_runtime_pm != 0)) | |
1699 | ret = connector_status_disconnected; | |
d291767b | 1700 | } |
6f50eae7 AD |
1701 | /* eDP is always DP */ |
1702 | radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; | |
8b834852 AD |
1703 | if (!radeon_dig_connector->edp_on) |
1704 | atombios_set_edp_panel_power(connector, | |
1705 | ATOM_TRANSMITTER_ACTION_POWER_ON); | |
6f50eae7 | 1706 | if (radeon_dp_getdpcd(radeon_connector)) |
9fa05c98 | 1707 | ret = connector_status_connected; |
8b834852 AD |
1708 | if (!radeon_dig_connector->edp_on) |
1709 | atombios_set_edp_panel_power(connector, | |
1710 | ATOM_TRANSMITTER_ACTION_POWER_OFF); | |
1d33e1fc AD |
1711 | } else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) != |
1712 | ENCODER_OBJECT_ID_NONE) { | |
b06947b5 AD |
1713 | /* DP bridges are always DP */ |
1714 | radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; | |
1715 | /* get the DPCD from the bridge */ | |
1716 | radeon_dp_getdpcd(radeon_connector); | |
1717 | ||
6777a4f6 AD |
1718 | if (encoder) { |
1719 | /* setup ddc on the bridge */ | |
1720 | radeon_atom_ext_encoder_setup_ddc(encoder); | |
0a9069d3 NOS |
1721 | /* bridge chips are always aux */ |
1722 | if (radeon_ddc_probe(radeon_connector, true)) /* try DDC */ | |
b06947b5 | 1723 | ret = connector_status_connected; |
6777a4f6 | 1724 | else if (radeon_connector->dac_load_detect) { /* try load detection */ |
319d1e14 | 1725 | const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; |
b06947b5 AD |
1726 | ret = encoder_funcs->detect(encoder, connector); |
1727 | } | |
591a10e1 | 1728 | } |
b06947b5 | 1729 | } else { |
6f50eae7 | 1730 | radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector); |
f8d0edde AD |
1731 | if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) { |
1732 | ret = connector_status_connected; | |
9843ead0 | 1733 | if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { |
f8d0edde | 1734 | radeon_dp_getdpcd(radeon_connector); |
9843ead0 DA |
1735 | r = radeon_dp_mst_probe(radeon_connector); |
1736 | if (r == 1) | |
1737 | ret = connector_status_disconnected; | |
1738 | } | |
6f50eae7 | 1739 | } else { |
f8d0edde | 1740 | if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { |
9843ead0 DA |
1741 | if (radeon_dp_getdpcd(radeon_connector)) { |
1742 | r = radeon_dp_mst_probe(radeon_connector); | |
1743 | if (r == 1) | |
1744 | ret = connector_status_disconnected; | |
1745 | else | |
1746 | ret = connector_status_connected; | |
1747 | } | |
f8d0edde | 1748 | } else { |
d592fca9 | 1749 | /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ |
0a9069d3 | 1750 | if (radeon_ddc_probe(radeon_connector, false)) |
f8d0edde AD |
1751 | ret = connector_status_connected; |
1752 | } | |
4143e919 | 1753 | } |
746c1aa4 | 1754 | } |
4143e919 | 1755 | |
30f44372 | 1756 | radeon_connector_update_scratch_regs(connector, ret); |
1a626b68 | 1757 | |
d0ea397e AD |
1758 | if ((radeon_audio != 0) && encoder) { |
1759 | radeon_connector_get_edid(connector); | |
1760 | radeon_audio_detect(connector, encoder, ret); | |
1761 | } | |
1a626b68 | 1762 | |
10ebc0bc DA |
1763 | out: |
1764 | pm_runtime_mark_last_busy(connector->dev->dev); | |
1765 | pm_runtime_put_autosuspend(connector->dev->dev); | |
1766 | ||
746c1aa4 DA |
1767 | return ret; |
1768 | } | |
1769 | ||
5801ead6 AD |
1770 | static int radeon_dp_mode_valid(struct drm_connector *connector, |
1771 | struct drm_display_mode *mode) | |
1772 | { | |
6536a3a6 AD |
1773 | struct drm_device *dev = connector->dev; |
1774 | struct radeon_device *rdev = dev->dev_private; | |
5801ead6 AD |
1775 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
1776 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; | |
1777 | ||
1778 | /* XXX check mode bandwidth */ | |
1779 | ||
f89931f3 AD |
1780 | if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || |
1781 | (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { | |
d291767b AD |
1782 | struct drm_encoder *encoder = radeon_best_single_encoder(connector); |
1783 | ||
1784 | if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) | |
1785 | return MODE_PANEL; | |
1786 | ||
1787 | if (encoder) { | |
1788 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1789 | struct drm_display_mode *native_mode = &radeon_encoder->native_mode; | |
1790 | ||
f89931f3 | 1791 | /* AVIVO hardware supports downscaling modes larger than the panel |
d291767b AD |
1792 | * to the panel size, but I'm not sure this is desirable. |
1793 | */ | |
1794 | if ((mode->hdisplay > native_mode->hdisplay) || | |
1795 | (mode->vdisplay > native_mode->vdisplay)) | |
1796 | return MODE_PANEL; | |
1797 | ||
1798 | /* if scaling is disabled, block non-native modes */ | |
1799 | if (radeon_encoder->rmx_type == RMX_OFF) { | |
1800 | if ((mode->hdisplay != native_mode->hdisplay) || | |
1801 | (mode->vdisplay != native_mode->vdisplay)) | |
1802 | return MODE_PANEL; | |
1803 | } | |
1804 | } | |
d291767b AD |
1805 | } else { |
1806 | if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || | |
6536a3a6 | 1807 | (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
d291767b | 1808 | return radeon_dp_mode_valid_helper(connector, mode); |
6536a3a6 | 1809 | } else { |
377bd8a9 | 1810 | if (ASIC_IS_DCE6(rdev) && drm_detect_hdmi_monitor(radeon_connector_edid(connector))) { |
6536a3a6 AD |
1811 | /* HDMI 1.3+ supports max clock of 340 Mhz */ |
1812 | if (mode->clock > 340000) | |
1813 | return MODE_CLOCK_HIGH; | |
1814 | } else { | |
1815 | if (mode->clock > 165000) | |
1816 | return MODE_CLOCK_HIGH; | |
1817 | } | |
1818 | } | |
d291767b | 1819 | } |
6536a3a6 AD |
1820 | |
1821 | return MODE_OK; | |
5801ead6 AD |
1822 | } |
1823 | ||
1109ca09 | 1824 | static const struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = { |
746c1aa4 | 1825 | .get_modes = radeon_dp_get_modes, |
5801ead6 | 1826 | .mode_valid = radeon_dp_mode_valid, |
746c1aa4 DA |
1827 | .best_encoder = radeon_dvi_encoder, |
1828 | }; | |
1829 | ||
1109ca09 | 1830 | static const struct drm_connector_funcs radeon_dp_connector_funcs = { |
746c1aa4 DA |
1831 | .dpms = drm_helper_connector_dpms, |
1832 | .detect = radeon_dp_detect, | |
1833 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1834 | .set_property = radeon_connector_set_property, | |
379dfc25 | 1835 | .destroy = radeon_connector_destroy, |
746c1aa4 DA |
1836 | .force = radeon_dvi_force, |
1837 | }; | |
1838 | ||
855f5f1d AD |
1839 | static const struct drm_connector_funcs radeon_edp_connector_funcs = { |
1840 | .dpms = drm_helper_connector_dpms, | |
1841 | .detect = radeon_dp_detect, | |
1842 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1843 | .set_property = radeon_lvds_set_property, | |
379dfc25 | 1844 | .destroy = radeon_connector_destroy, |
855f5f1d AD |
1845 | .force = radeon_dvi_force, |
1846 | }; | |
1847 | ||
1848 | static const struct drm_connector_funcs radeon_lvds_bridge_connector_funcs = { | |
1849 | .dpms = drm_helper_connector_dpms, | |
1850 | .detect = radeon_dp_detect, | |
1851 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1852 | .set_property = radeon_lvds_set_property, | |
379dfc25 | 1853 | .destroy = radeon_connector_destroy, |
855f5f1d AD |
1854 | .force = radeon_dvi_force, |
1855 | }; | |
1856 | ||
771fe6b9 JG |
1857 | void |
1858 | radeon_add_atom_connector(struct drm_device *dev, | |
1859 | uint32_t connector_id, | |
1860 | uint32_t supported_device, | |
1861 | int connector_type, | |
1862 | struct radeon_i2c_bus_rec *i2c_bus, | |
b75fad06 | 1863 | uint32_t igp_lane_info, |
eed45b30 | 1864 | uint16_t connector_object_id, |
26b5bc98 AD |
1865 | struct radeon_hpd *hpd, |
1866 | struct radeon_router *router) | |
771fe6b9 | 1867 | { |
445282db | 1868 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
1869 | struct drm_connector *connector; |
1870 | struct radeon_connector *radeon_connector; | |
1871 | struct radeon_connector_atom_dig *radeon_dig_connector; | |
eac4dff6 AD |
1872 | struct drm_encoder *encoder; |
1873 | struct radeon_encoder *radeon_encoder; | |
771fe6b9 | 1874 | uint32_t subpixel_order = SubPixelNone; |
0294cf4f | 1875 | bool shared_ddc = false; |
eac4dff6 | 1876 | bool is_dp_bridge = false; |
496263bf | 1877 | bool has_aux = false; |
771fe6b9 | 1878 | |
4ce001ab | 1879 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
771fe6b9 JG |
1880 | return; |
1881 | ||
cf4c12f9 AD |
1882 | /* if the user selected tv=0 don't try and add the connector */ |
1883 | if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) || | |
1884 | (connector_type == DRM_MODE_CONNECTOR_Composite) || | |
1885 | (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) && | |
1886 | (radeon_tv == 0)) | |
1887 | return; | |
1888 | ||
771fe6b9 JG |
1889 | /* see if we already added it */ |
1890 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1891 | radeon_connector = to_radeon_connector(connector); | |
1892 | if (radeon_connector->connector_id == connector_id) { | |
1893 | radeon_connector->devices |= supported_device; | |
1894 | return; | |
1895 | } | |
0294cf4f | 1896 | if (radeon_connector->ddc_bus && i2c_bus->valid) { |
d3932d6c | 1897 | if (radeon_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { |
0294cf4f AD |
1898 | radeon_connector->shared_ddc = true; |
1899 | shared_ddc = true; | |
1900 | } | |
fb939dfc | 1901 | if (radeon_connector->router_bus && router->ddc_valid && |
26b5bc98 AD |
1902 | (radeon_connector->router.router_id == router->router_id)) { |
1903 | radeon_connector->shared_ddc = false; | |
1904 | shared_ddc = false; | |
1905 | } | |
0294cf4f | 1906 | } |
771fe6b9 JG |
1907 | } |
1908 | ||
eac4dff6 AD |
1909 | /* check if it's a dp bridge */ |
1910 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1911 | radeon_encoder = to_radeon_encoder(encoder); | |
1912 | if (radeon_encoder->devices & supported_device) { | |
1913 | switch (radeon_encoder->encoder_id) { | |
1914 | case ENCODER_OBJECT_ID_TRAVIS: | |
1915 | case ENCODER_OBJECT_ID_NUTMEG: | |
1916 | is_dp_bridge = true; | |
1917 | break; | |
1918 | default: | |
1919 | break; | |
1920 | } | |
1921 | } | |
1922 | } | |
1923 | ||
771fe6b9 JG |
1924 | radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL); |
1925 | if (!radeon_connector) | |
1926 | return; | |
1927 | ||
1928 | connector = &radeon_connector->base; | |
1929 | ||
1930 | radeon_connector->connector_id = connector_id; | |
1931 | radeon_connector->devices = supported_device; | |
0294cf4f | 1932 | radeon_connector->shared_ddc = shared_ddc; |
b75fad06 | 1933 | radeon_connector->connector_object_id = connector_object_id; |
eed45b30 | 1934 | radeon_connector->hpd = *hpd; |
bc1c4dc3 | 1935 | |
26b5bc98 | 1936 | radeon_connector->router = *router; |
fb939dfc | 1937 | if (router->ddc_valid || router->cd_valid) { |
26b5bc98 AD |
1938 | radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info); |
1939 | if (!radeon_connector->router_bus) | |
a70882aa | 1940 | DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); |
26b5bc98 | 1941 | } |
eac4dff6 AD |
1942 | |
1943 | if (is_dp_bridge) { | |
771fe6b9 JG |
1944 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); |
1945 | if (!radeon_dig_connector) | |
1946 | goto failed; | |
771fe6b9 JG |
1947 | radeon_dig_connector->igp_lane_info = igp_lane_info; |
1948 | radeon_connector->con_priv = radeon_dig_connector; | |
771fe6b9 | 1949 | if (i2c_bus->valid) { |
379dfc25 AD |
1950 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
1951 | if (radeon_connector->ddc_bus) | |
496263bf AD |
1952 | has_aux = true; |
1953 | else | |
eac4dff6 | 1954 | DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
771fe6b9 | 1955 | } |
eac4dff6 AD |
1956 | switch (connector_type) { |
1957 | case DRM_MODE_CONNECTOR_VGA: | |
1958 | case DRM_MODE_CONNECTOR_DVIA: | |
1959 | default: | |
855f5f1d AD |
1960 | drm_connector_init(dev, &radeon_connector->base, |
1961 | &radeon_dp_connector_funcs, connector_type); | |
1962 | drm_connector_helper_add(&radeon_connector->base, | |
1963 | &radeon_dp_connector_helper_funcs); | |
eac4dff6 AD |
1964 | connector->interlace_allowed = true; |
1965 | connector->doublescan_allowed = true; | |
d629a3ce | 1966 | radeon_connector->dac_load_detect = true; |
e35755fa | 1967 | drm_object_attach_property(&radeon_connector->base.base, |
d629a3ce AD |
1968 | rdev->mode_info.load_detect_property, |
1969 | 1); | |
da997620 AD |
1970 | drm_object_attach_property(&radeon_connector->base.base, |
1971 | dev->mode_config.scaling_mode_property, | |
1972 | DRM_MODE_SCALE_NONE); | |
643b1f56 AD |
1973 | if (ASIC_IS_DCE5(rdev)) |
1974 | drm_object_attach_property(&radeon_connector->base.base, | |
1975 | rdev->mode_info.output_csc_property, | |
1976 | RADEON_OUTPUT_CSC_BYPASS); | |
eac4dff6 AD |
1977 | break; |
1978 | case DRM_MODE_CONNECTOR_DVII: | |
1979 | case DRM_MODE_CONNECTOR_DVID: | |
1980 | case DRM_MODE_CONNECTOR_HDMIA: | |
1981 | case DRM_MODE_CONNECTOR_HDMIB: | |
1982 | case DRM_MODE_CONNECTOR_DisplayPort: | |
855f5f1d AD |
1983 | drm_connector_init(dev, &radeon_connector->base, |
1984 | &radeon_dp_connector_funcs, connector_type); | |
1985 | drm_connector_helper_add(&radeon_connector->base, | |
1986 | &radeon_dp_connector_helper_funcs); | |
e35755fa | 1987 | drm_object_attach_property(&radeon_connector->base.base, |
430f70d5 | 1988 | rdev->mode_info.underscan_property, |
56bec7c0 | 1989 | UNDERSCAN_OFF); |
e35755fa | 1990 | drm_object_attach_property(&radeon_connector->base.base, |
5bccf5e3 MG |
1991 | rdev->mode_info.underscan_hborder_property, |
1992 | 0); | |
e35755fa | 1993 | drm_object_attach_property(&radeon_connector->base.base, |
5bccf5e3 MG |
1994 | rdev->mode_info.underscan_vborder_property, |
1995 | 0); | |
91915260 | 1996 | |
da997620 AD |
1997 | drm_object_attach_property(&radeon_connector->base.base, |
1998 | dev->mode_config.scaling_mode_property, | |
1999 | DRM_MODE_SCALE_NONE); | |
2000 | ||
6214bb74 AD |
2001 | drm_object_attach_property(&radeon_connector->base.base, |
2002 | rdev->mode_info.dither_property, | |
2003 | RADEON_FMT_DITHER_DISABLE); | |
91915260 | 2004 | |
7403c515 | 2005 | if (radeon_audio != 0) { |
108dc8e8 AD |
2006 | drm_object_attach_property(&radeon_connector->base.base, |
2007 | rdev->mode_info.audio_property, | |
e31fadd3 | 2008 | RADEON_AUDIO_AUTO); |
7403c515 AD |
2009 | radeon_connector->audio = RADEON_AUDIO_AUTO; |
2010 | } | |
643b1f56 AD |
2011 | if (ASIC_IS_DCE5(rdev)) |
2012 | drm_object_attach_property(&radeon_connector->base.base, | |
2013 | rdev->mode_info.output_csc_property, | |
2014 | RADEON_OUTPUT_CSC_BYPASS); | |
91915260 | 2015 | |
eac4dff6 AD |
2016 | subpixel_order = SubPixelHorizontalRGB; |
2017 | connector->interlace_allowed = true; | |
2018 | if (connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
2019 | connector->doublescan_allowed = true; | |
2020 | else | |
2021 | connector->doublescan_allowed = false; | |
d629a3ce AD |
2022 | if (connector_type == DRM_MODE_CONNECTOR_DVII) { |
2023 | radeon_connector->dac_load_detect = true; | |
e35755fa | 2024 | drm_object_attach_property(&radeon_connector->base.base, |
d629a3ce AD |
2025 | rdev->mode_info.load_detect_property, |
2026 | 1); | |
2027 | } | |
eac4dff6 AD |
2028 | break; |
2029 | case DRM_MODE_CONNECTOR_LVDS: | |
2030 | case DRM_MODE_CONNECTOR_eDP: | |
855f5f1d AD |
2031 | drm_connector_init(dev, &radeon_connector->base, |
2032 | &radeon_lvds_bridge_connector_funcs, connector_type); | |
2033 | drm_connector_helper_add(&radeon_connector->base, | |
2034 | &radeon_dp_connector_helper_funcs); | |
e35755fa | 2035 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2036 | dev->mode_config.scaling_mode_property, |
2037 | DRM_MODE_SCALE_FULLSCREEN); | |
2038 | subpixel_order = SubPixelHorizontalRGB; | |
2039 | connector->interlace_allowed = false; | |
2040 | connector->doublescan_allowed = false; | |
2041 | break; | |
5bccf5e3 | 2042 | } |
eac4dff6 AD |
2043 | } else { |
2044 | switch (connector_type) { | |
2045 | case DRM_MODE_CONNECTOR_VGA: | |
2046 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | |
2047 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); | |
2048 | if (i2c_bus->valid) { | |
2049 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); | |
2050 | if (!radeon_connector->ddc_bus) | |
2051 | DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); | |
2052 | } | |
390d0bbe | 2053 | radeon_connector->dac_load_detect = true; |
e35755fa | 2054 | drm_object_attach_property(&radeon_connector->base.base, |
390d0bbe AD |
2055 | rdev->mode_info.load_detect_property, |
2056 | 1); | |
da997620 AD |
2057 | if (ASIC_IS_AVIVO(rdev)) |
2058 | drm_object_attach_property(&radeon_connector->base.base, | |
2059 | dev->mode_config.scaling_mode_property, | |
2060 | DRM_MODE_SCALE_NONE); | |
643b1f56 AD |
2061 | if (ASIC_IS_DCE5(rdev)) |
2062 | drm_object_attach_property(&radeon_connector->base.base, | |
2063 | rdev->mode_info.output_csc_property, | |
2064 | RADEON_OUTPUT_CSC_BYPASS); | |
eac4dff6 AD |
2065 | /* no HPD on analog connectors */ |
2066 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
eac4dff6 | 2067 | connector->interlace_allowed = true; |
c49948f4 | 2068 | connector->doublescan_allowed = true; |
eac4dff6 AD |
2069 | break; |
2070 | case DRM_MODE_CONNECTOR_DVIA: | |
2071 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | |
2072 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); | |
2073 | if (i2c_bus->valid) { | |
2074 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); | |
2075 | if (!radeon_connector->ddc_bus) | |
2076 | DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); | |
2077 | } | |
2078 | radeon_connector->dac_load_detect = true; | |
e35755fa | 2079 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2080 | rdev->mode_info.load_detect_property, |
2081 | 1); | |
da997620 AD |
2082 | if (ASIC_IS_AVIVO(rdev)) |
2083 | drm_object_attach_property(&radeon_connector->base.base, | |
2084 | dev->mode_config.scaling_mode_property, | |
2085 | DRM_MODE_SCALE_NONE); | |
643b1f56 AD |
2086 | if (ASIC_IS_DCE5(rdev)) |
2087 | drm_object_attach_property(&radeon_connector->base.base, | |
2088 | rdev->mode_info.output_csc_property, | |
2089 | RADEON_OUTPUT_CSC_BYPASS); | |
eac4dff6 AD |
2090 | /* no HPD on analog connectors */ |
2091 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
2092 | connector->interlace_allowed = true; | |
2093 | connector->doublescan_allowed = true; | |
2094 | break; | |
2095 | case DRM_MODE_CONNECTOR_DVII: | |
2096 | case DRM_MODE_CONNECTOR_DVID: | |
2097 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | |
2098 | if (!radeon_dig_connector) | |
2099 | goto failed; | |
2100 | radeon_dig_connector->igp_lane_info = igp_lane_info; | |
2101 | radeon_connector->con_priv = radeon_dig_connector; | |
2102 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); | |
2103 | drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); | |
2104 | if (i2c_bus->valid) { | |
2105 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); | |
2106 | if (!radeon_connector->ddc_bus) | |
2107 | DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); | |
2108 | } | |
2109 | subpixel_order = SubPixelHorizontalRGB; | |
e35755fa | 2110 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2111 | rdev->mode_info.coherent_mode_property, |
2112 | 1); | |
2113 | if (ASIC_IS_AVIVO(rdev)) { | |
e35755fa | 2114 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2115 | rdev->mode_info.underscan_property, |
2116 | UNDERSCAN_OFF); | |
e35755fa | 2117 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2118 | rdev->mode_info.underscan_hborder_property, |
2119 | 0); | |
e35755fa | 2120 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2121 | rdev->mode_info.underscan_vborder_property, |
2122 | 0); | |
da997620 AD |
2123 | drm_object_attach_property(&radeon_connector->base.base, |
2124 | rdev->mode_info.dither_property, | |
2125 | RADEON_FMT_DITHER_DISABLE); | |
2126 | drm_object_attach_property(&radeon_connector->base.base, | |
2127 | dev->mode_config.scaling_mode_property, | |
2128 | DRM_MODE_SCALE_NONE); | |
eac4dff6 | 2129 | } |
108dc8e8 | 2130 | if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { |
8666c076 | 2131 | drm_object_attach_property(&radeon_connector->base.base, |
108dc8e8 | 2132 | rdev->mode_info.audio_property, |
e31fadd3 | 2133 | RADEON_AUDIO_AUTO); |
7403c515 | 2134 | radeon_connector->audio = RADEON_AUDIO_AUTO; |
8666c076 | 2135 | } |
eac4dff6 AD |
2136 | if (connector_type == DRM_MODE_CONNECTOR_DVII) { |
2137 | radeon_connector->dac_load_detect = true; | |
e35755fa | 2138 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2139 | rdev->mode_info.load_detect_property, |
2140 | 1); | |
2141 | } | |
643b1f56 AD |
2142 | if (ASIC_IS_DCE5(rdev)) |
2143 | drm_object_attach_property(&radeon_connector->base.base, | |
2144 | rdev->mode_info.output_csc_property, | |
2145 | RADEON_OUTPUT_CSC_BYPASS); | |
eac4dff6 AD |
2146 | connector->interlace_allowed = true; |
2147 | if (connector_type == DRM_MODE_CONNECTOR_DVII) | |
2148 | connector->doublescan_allowed = true; | |
2149 | else | |
2150 | connector->doublescan_allowed = false; | |
2151 | break; | |
2152 | case DRM_MODE_CONNECTOR_HDMIA: | |
2153 | case DRM_MODE_CONNECTOR_HDMIB: | |
2154 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | |
2155 | if (!radeon_dig_connector) | |
2156 | goto failed; | |
2157 | radeon_dig_connector->igp_lane_info = igp_lane_info; | |
2158 | radeon_connector->con_priv = radeon_dig_connector; | |
2159 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); | |
2160 | drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); | |
2161 | if (i2c_bus->valid) { | |
2162 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); | |
2163 | if (!radeon_connector->ddc_bus) | |
2164 | DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); | |
2165 | } | |
e35755fa | 2166 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2167 | rdev->mode_info.coherent_mode_property, |
2168 | 1); | |
2169 | if (ASIC_IS_AVIVO(rdev)) { | |
e35755fa | 2170 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2171 | rdev->mode_info.underscan_property, |
2172 | UNDERSCAN_OFF); | |
e35755fa | 2173 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2174 | rdev->mode_info.underscan_hborder_property, |
2175 | 0); | |
e35755fa | 2176 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2177 | rdev->mode_info.underscan_vborder_property, |
2178 | 0); | |
da997620 AD |
2179 | drm_object_attach_property(&radeon_connector->base.base, |
2180 | rdev->mode_info.dither_property, | |
2181 | RADEON_FMT_DITHER_DISABLE); | |
2182 | drm_object_attach_property(&radeon_connector->base.base, | |
2183 | dev->mode_config.scaling_mode_property, | |
2184 | DRM_MODE_SCALE_NONE); | |
eac4dff6 | 2185 | } |
108dc8e8 | 2186 | if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { |
8666c076 | 2187 | drm_object_attach_property(&radeon_connector->base.base, |
108dc8e8 | 2188 | rdev->mode_info.audio_property, |
e31fadd3 | 2189 | RADEON_AUDIO_AUTO); |
7403c515 | 2190 | radeon_connector->audio = RADEON_AUDIO_AUTO; |
8666c076 | 2191 | } |
643b1f56 AD |
2192 | if (ASIC_IS_DCE5(rdev)) |
2193 | drm_object_attach_property(&radeon_connector->base.base, | |
2194 | rdev->mode_info.output_csc_property, | |
2195 | RADEON_OUTPUT_CSC_BYPASS); | |
eac4dff6 AD |
2196 | subpixel_order = SubPixelHorizontalRGB; |
2197 | connector->interlace_allowed = true; | |
2198 | if (connector_type == DRM_MODE_CONNECTOR_HDMIB) | |
2199 | connector->doublescan_allowed = true; | |
2200 | else | |
2201 | connector->doublescan_allowed = false; | |
2202 | break; | |
2203 | case DRM_MODE_CONNECTOR_DisplayPort: | |
2204 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | |
2205 | if (!radeon_dig_connector) | |
2206 | goto failed; | |
2207 | radeon_dig_connector->igp_lane_info = igp_lane_info; | |
2208 | radeon_connector->con_priv = radeon_dig_connector; | |
2209 | drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type); | |
2210 | drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs); | |
2211 | if (i2c_bus->valid) { | |
eac4dff6 | 2212 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
496263bf AD |
2213 | if (radeon_connector->ddc_bus) |
2214 | has_aux = true; | |
2215 | else | |
eac4dff6 AD |
2216 | DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
2217 | } | |
2218 | subpixel_order = SubPixelHorizontalRGB; | |
e35755fa | 2219 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2220 | rdev->mode_info.coherent_mode_property, |
2221 | 1); | |
2222 | if (ASIC_IS_AVIVO(rdev)) { | |
e35755fa | 2223 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2224 | rdev->mode_info.underscan_property, |
2225 | UNDERSCAN_OFF); | |
e35755fa | 2226 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2227 | rdev->mode_info.underscan_hborder_property, |
2228 | 0); | |
e35755fa | 2229 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2230 | rdev->mode_info.underscan_vborder_property, |
2231 | 0); | |
da997620 AD |
2232 | drm_object_attach_property(&radeon_connector->base.base, |
2233 | rdev->mode_info.dither_property, | |
2234 | RADEON_FMT_DITHER_DISABLE); | |
2235 | drm_object_attach_property(&radeon_connector->base.base, | |
2236 | dev->mode_config.scaling_mode_property, | |
2237 | DRM_MODE_SCALE_NONE); | |
eac4dff6 | 2238 | } |
108dc8e8 | 2239 | if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) { |
8666c076 | 2240 | drm_object_attach_property(&radeon_connector->base.base, |
108dc8e8 | 2241 | rdev->mode_info.audio_property, |
e31fadd3 | 2242 | RADEON_AUDIO_AUTO); |
7403c515 | 2243 | radeon_connector->audio = RADEON_AUDIO_AUTO; |
8666c076 | 2244 | } |
643b1f56 AD |
2245 | if (ASIC_IS_DCE5(rdev)) |
2246 | drm_object_attach_property(&radeon_connector->base.base, | |
2247 | rdev->mode_info.output_csc_property, | |
2248 | RADEON_OUTPUT_CSC_BYPASS); | |
eac4dff6 AD |
2249 | connector->interlace_allowed = true; |
2250 | /* in theory with a DP to VGA converter... */ | |
c49948f4 | 2251 | connector->doublescan_allowed = false; |
eac4dff6 AD |
2252 | break; |
2253 | case DRM_MODE_CONNECTOR_eDP: | |
2254 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | |
2255 | if (!radeon_dig_connector) | |
2256 | goto failed; | |
2257 | radeon_dig_connector->igp_lane_info = igp_lane_info; | |
2258 | radeon_connector->con_priv = radeon_dig_connector; | |
855f5f1d | 2259 | drm_connector_init(dev, &radeon_connector->base, &radeon_edp_connector_funcs, connector_type); |
eac4dff6 AD |
2260 | drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs); |
2261 | if (i2c_bus->valid) { | |
379dfc25 AD |
2262 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
2263 | if (radeon_connector->ddc_bus) | |
496263bf AD |
2264 | has_aux = true; |
2265 | else | |
eac4dff6 AD |
2266 | DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
2267 | } | |
e35755fa | 2268 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2269 | dev->mode_config.scaling_mode_property, |
2270 | DRM_MODE_SCALE_FULLSCREEN); | |
2271 | subpixel_order = SubPixelHorizontalRGB; | |
2272 | connector->interlace_allowed = false; | |
2273 | connector->doublescan_allowed = false; | |
2274 | break; | |
2275 | case DRM_MODE_CONNECTOR_SVIDEO: | |
2276 | case DRM_MODE_CONNECTOR_Composite: | |
2277 | case DRM_MODE_CONNECTOR_9PinDIN: | |
2278 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); | |
2279 | drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); | |
2280 | radeon_connector->dac_load_detect = true; | |
e35755fa | 2281 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2282 | rdev->mode_info.load_detect_property, |
2283 | 1); | |
e35755fa | 2284 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2285 | rdev->mode_info.tv_std_property, |
2286 | radeon_atombios_get_tv_info(rdev)); | |
2287 | /* no HPD on analog connectors */ | |
2288 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
2289 | connector->interlace_allowed = false; | |
2290 | connector->doublescan_allowed = false; | |
2291 | break; | |
2292 | case DRM_MODE_CONNECTOR_LVDS: | |
2293 | radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); | |
2294 | if (!radeon_dig_connector) | |
2295 | goto failed; | |
2296 | radeon_dig_connector->igp_lane_info = igp_lane_info; | |
2297 | radeon_connector->con_priv = radeon_dig_connector; | |
2298 | drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); | |
2299 | drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); | |
2300 | if (i2c_bus->valid) { | |
2301 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); | |
2302 | if (!radeon_connector->ddc_bus) | |
2303 | DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); | |
2304 | } | |
e35755fa | 2305 | drm_object_attach_property(&radeon_connector->base.base, |
eac4dff6 AD |
2306 | dev->mode_config.scaling_mode_property, |
2307 | DRM_MODE_SCALE_FULLSCREEN); | |
2308 | subpixel_order = SubPixelHorizontalRGB; | |
2309 | connector->interlace_allowed = false; | |
2310 | connector->doublescan_allowed = false; | |
2311 | break; | |
771fe6b9 | 2312 | } |
771fe6b9 JG |
2313 | } |
2314 | ||
2581afcc | 2315 | if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) { |
14ff8d48 L |
2316 | if (i2c_bus->valid) { |
2317 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | | |
2318 | DRM_CONNECTOR_POLL_DISCONNECT; | |
2319 | } | |
eb1f8e4f DA |
2320 | } else |
2321 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
2322 | ||
771fe6b9 | 2323 | connector->display_info.subpixel_order = subpixel_order; |
34ea3d38 | 2324 | drm_connector_register(connector); |
496263bf AD |
2325 | |
2326 | if (has_aux) | |
2327 | radeon_dp_aux_init(radeon_connector); | |
2328 | ||
771fe6b9 JG |
2329 | return; |
2330 | ||
2331 | failed: | |
771fe6b9 JG |
2332 | drm_connector_cleanup(connector); |
2333 | kfree(connector); | |
2334 | } | |
2335 | ||
2336 | void | |
2337 | radeon_add_legacy_connector(struct drm_device *dev, | |
2338 | uint32_t connector_id, | |
2339 | uint32_t supported_device, | |
2340 | int connector_type, | |
b75fad06 | 2341 | struct radeon_i2c_bus_rec *i2c_bus, |
eed45b30 AD |
2342 | uint16_t connector_object_id, |
2343 | struct radeon_hpd *hpd) | |
771fe6b9 | 2344 | { |
445282db | 2345 | struct radeon_device *rdev = dev->dev_private; |
771fe6b9 JG |
2346 | struct drm_connector *connector; |
2347 | struct radeon_connector *radeon_connector; | |
2348 | uint32_t subpixel_order = SubPixelNone; | |
2349 | ||
4ce001ab | 2350 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
771fe6b9 JG |
2351 | return; |
2352 | ||
cf4c12f9 AD |
2353 | /* if the user selected tv=0 don't try and add the connector */ |
2354 | if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) || | |
2355 | (connector_type == DRM_MODE_CONNECTOR_Composite) || | |
2356 | (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) && | |
2357 | (radeon_tv == 0)) | |
2358 | return; | |
2359 | ||
771fe6b9 JG |
2360 | /* see if we already added it */ |
2361 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2362 | radeon_connector = to_radeon_connector(connector); | |
2363 | if (radeon_connector->connector_id == connector_id) { | |
2364 | radeon_connector->devices |= supported_device; | |
2365 | return; | |
2366 | } | |
2367 | } | |
2368 | ||
2369 | radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL); | |
2370 | if (!radeon_connector) | |
2371 | return; | |
2372 | ||
2373 | connector = &radeon_connector->base; | |
2374 | ||
2375 | radeon_connector->connector_id = connector_id; | |
2376 | radeon_connector->devices = supported_device; | |
b75fad06 | 2377 | radeon_connector->connector_object_id = connector_object_id; |
eed45b30 | 2378 | radeon_connector->hpd = *hpd; |
bc1c4dc3 | 2379 | |
771fe6b9 JG |
2380 | switch (connector_type) { |
2381 | case DRM_MODE_CONNECTOR_VGA: | |
2382 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | |
0b4c0f3f | 2383 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
771fe6b9 | 2384 | if (i2c_bus->valid) { |
f376b94f | 2385 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
771fe6b9 | 2386 | if (!radeon_connector->ddc_bus) |
a70882aa | 2387 | DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
771fe6b9 | 2388 | } |
35e4b7af | 2389 | radeon_connector->dac_load_detect = true; |
e35755fa | 2390 | drm_object_attach_property(&radeon_connector->base.base, |
445282db DA |
2391 | rdev->mode_info.load_detect_property, |
2392 | 1); | |
2581afcc AD |
2393 | /* no HPD on analog connectors */ |
2394 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
c49948f4 AD |
2395 | connector->interlace_allowed = true; |
2396 | connector->doublescan_allowed = true; | |
771fe6b9 JG |
2397 | break; |
2398 | case DRM_MODE_CONNECTOR_DVIA: | |
2399 | drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); | |
0b4c0f3f | 2400 | drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs); |
771fe6b9 | 2401 | if (i2c_bus->valid) { |
f376b94f | 2402 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
771fe6b9 | 2403 | if (!radeon_connector->ddc_bus) |
a70882aa | 2404 | DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
771fe6b9 | 2405 | } |
35e4b7af | 2406 | radeon_connector->dac_load_detect = true; |
e35755fa | 2407 | drm_object_attach_property(&radeon_connector->base.base, |
445282db DA |
2408 | rdev->mode_info.load_detect_property, |
2409 | 1); | |
2581afcc AD |
2410 | /* no HPD on analog connectors */ |
2411 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
c49948f4 AD |
2412 | connector->interlace_allowed = true; |
2413 | connector->doublescan_allowed = true; | |
771fe6b9 JG |
2414 | break; |
2415 | case DRM_MODE_CONNECTOR_DVII: | |
2416 | case DRM_MODE_CONNECTOR_DVID: | |
2417 | drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type); | |
0b4c0f3f | 2418 | drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs); |
771fe6b9 | 2419 | if (i2c_bus->valid) { |
f376b94f | 2420 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
771fe6b9 | 2421 | if (!radeon_connector->ddc_bus) |
a70882aa | 2422 | DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
68b3adb4 AD |
2423 | } |
2424 | if (connector_type == DRM_MODE_CONNECTOR_DVII) { | |
35e4b7af | 2425 | radeon_connector->dac_load_detect = true; |
e35755fa | 2426 | drm_object_attach_property(&radeon_connector->base.base, |
445282db DA |
2427 | rdev->mode_info.load_detect_property, |
2428 | 1); | |
771fe6b9 JG |
2429 | } |
2430 | subpixel_order = SubPixelHorizontalRGB; | |
c49948f4 AD |
2431 | connector->interlace_allowed = true; |
2432 | if (connector_type == DRM_MODE_CONNECTOR_DVII) | |
2433 | connector->doublescan_allowed = true; | |
2434 | else | |
2435 | connector->doublescan_allowed = false; | |
771fe6b9 JG |
2436 | break; |
2437 | case DRM_MODE_CONNECTOR_SVIDEO: | |
2438 | case DRM_MODE_CONNECTOR_Composite: | |
2439 | case DRM_MODE_CONNECTOR_9PinDIN: | |
cf4c12f9 AD |
2440 | drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type); |
2441 | drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs); | |
2442 | radeon_connector->dac_load_detect = true; | |
2443 | /* RS400,RC410,RS480 chipset seems to report a lot | |
2444 | * of false positive on load detect, we haven't yet | |
2445 | * found a way to make load detect reliable on those | |
2446 | * chipset, thus just disable it for TV. | |
2447 | */ | |
2448 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) | |
2449 | radeon_connector->dac_load_detect = false; | |
e35755fa | 2450 | drm_object_attach_property(&radeon_connector->base.base, |
cf4c12f9 AD |
2451 | rdev->mode_info.load_detect_property, |
2452 | radeon_connector->dac_load_detect); | |
e35755fa | 2453 | drm_object_attach_property(&radeon_connector->base.base, |
cf4c12f9 AD |
2454 | rdev->mode_info.tv_std_property, |
2455 | radeon_combios_get_tv_info(rdev)); | |
2456 | /* no HPD on analog connectors */ | |
2457 | radeon_connector->hpd.hpd = RADEON_HPD_NONE; | |
c49948f4 AD |
2458 | connector->interlace_allowed = false; |
2459 | connector->doublescan_allowed = false; | |
771fe6b9 JG |
2460 | break; |
2461 | case DRM_MODE_CONNECTOR_LVDS: | |
2462 | drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type); | |
0b4c0f3f | 2463 | drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs); |
771fe6b9 | 2464 | if (i2c_bus->valid) { |
f376b94f | 2465 | radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); |
771fe6b9 | 2466 | if (!radeon_connector->ddc_bus) |
a70882aa | 2467 | DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); |
771fe6b9 | 2468 | } |
e35755fa | 2469 | drm_object_attach_property(&radeon_connector->base.base, |
445282db DA |
2470 | dev->mode_config.scaling_mode_property, |
2471 | DRM_MODE_SCALE_FULLSCREEN); | |
771fe6b9 | 2472 | subpixel_order = SubPixelHorizontalRGB; |
c49948f4 AD |
2473 | connector->interlace_allowed = false; |
2474 | connector->doublescan_allowed = false; | |
771fe6b9 JG |
2475 | break; |
2476 | } | |
2477 | ||
2581afcc | 2478 | if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) { |
14ff8d48 L |
2479 | if (i2c_bus->valid) { |
2480 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | | |
2481 | DRM_CONNECTOR_POLL_DISCONNECT; | |
2482 | } | |
eb1f8e4f DA |
2483 | } else |
2484 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
14ff8d48 | 2485 | |
771fe6b9 | 2486 | connector->display_info.subpixel_order = subpixel_order; |
34ea3d38 | 2487 | drm_connector_register(connector); |
771fe6b9 | 2488 | } |
9843ead0 DA |
2489 | |
2490 | void radeon_setup_mst_connector(struct drm_device *dev) | |
2491 | { | |
2492 | struct radeon_device *rdev = dev->dev_private; | |
2493 | struct drm_connector *connector; | |
2494 | struct radeon_connector *radeon_connector; | |
2495 | ||
2496 | if (!ASIC_IS_DCE5(rdev)) | |
2497 | return; | |
2498 | ||
2499 | if (radeon_mst == 0) | |
2500 | return; | |
2501 | ||
2502 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
2503 | int ret; | |
2504 | ||
2505 | radeon_connector = to_radeon_connector(connector); | |
2506 | ||
2507 | if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) | |
2508 | continue; | |
2509 | ||
2510 | ret = radeon_dp_mst_init(radeon_connector); | |
2511 | } | |
2512 | } |