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Merge tag 'nfsd-6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux
[linux-block.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
f9183127 27
2ef79416
TZ		 28#include <linux/pci.h>
29
f9183127 30#include <drm/drm_device.h>
e747235e 31#include <drm/drm_edid.h>
760285e7 32#include <drm/radeon_drm.h>
f9183127 33
771fe6b9 34#include "radeon.h"
7ddfba01 35#include "radeon_legacy_encoders.h"
771fe6b9
JG		 36#include "atom.h"
37
38#ifdef CONFIG_PPC_PMAC
39/* not sure which of these are needed */
40#include <asm/machdep.h>
41#include <asm/pmac_feature.h>
42#include <asm/prom.h>
771fe6b9
JG		 43#endif /* CONFIG_PPC_PMAC */
44
771fe6b9
JG		 45/* old legacy ATI BIOS routines */
46
47/* COMBIOS table offsets */
48enum radeon_combios_table_offset {
49 /* absolute offset tables */
50 COMBIOS_ASIC_INIT_1_TABLE,
51 COMBIOS_BIOS_SUPPORT_TABLE,
52 COMBIOS_DAC_PROGRAMMING_TABLE,
53 COMBIOS_MAX_COLOR_DEPTH_TABLE,
54 COMBIOS_CRTC_INFO_TABLE,
55 COMBIOS_PLL_INFO_TABLE,
56 COMBIOS_TV_INFO_TABLE,
57 COMBIOS_DFP_INFO_TABLE,
58 COMBIOS_HW_CONFIG_INFO_TABLE,
59 COMBIOS_MULTIMEDIA_INFO_TABLE,
60 COMBIOS_TV_STD_PATCH_TABLE,
61 COMBIOS_LCD_INFO_TABLE,
62 COMBIOS_MOBILE_INFO_TABLE,
63 COMBIOS_PLL_INIT_TABLE,
64 COMBIOS_MEM_CONFIG_TABLE,
65 COMBIOS_SAVE_MASK_TABLE,
66 COMBIOS_HARDCODED_EDID_TABLE,
67 COMBIOS_ASIC_INIT_2_TABLE,
68 COMBIOS_CONNECTOR_INFO_TABLE,
69 COMBIOS_DYN_CLK_1_TABLE,
70 COMBIOS_RESERVED_MEM_TABLE,
71 COMBIOS_EXT_TMDS_INFO_TABLE,
72 COMBIOS_MEM_CLK_INFO_TABLE,
73 COMBIOS_EXT_DAC_INFO_TABLE,
74 COMBIOS_MISC_INFO_TABLE,
75 COMBIOS_CRT_INFO_TABLE,
76 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
77 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
78 COMBIOS_FAN_SPEED_INFO_TABLE,
79 COMBIOS_OVERDRIVE_INFO_TABLE,
80 COMBIOS_OEM_INFO_TABLE,
81 COMBIOS_DYN_CLK_2_TABLE,
82 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
83 COMBIOS_I2C_INFO_TABLE,
84 /* relative offset tables */
85 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
86 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
87 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
88 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
89 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
90 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
91 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
92 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
93 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
94 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
95 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
96};
97
98enum radeon_combios_ddc {
99 DDC_NONE_DETECTED,
100 DDC_MONID,
101 DDC_DVI,
102 DDC_VGA,
103 DDC_CRT2,
104 DDC_LCD,
105 DDC_GPIO,
106};
107
108enum radeon_combios_connector {
109 CONNECTOR_NONE_LEGACY,
110 CONNECTOR_PROPRIETARY_LEGACY,
111 CONNECTOR_CRT_LEGACY,
112 CONNECTOR_DVI_I_LEGACY,
113 CONNECTOR_DVI_D_LEGACY,
114 CONNECTOR_CTV_LEGACY,
115 CONNECTOR_STV_LEGACY,
116 CONNECTOR_UNSUPPORTED_LEGACY
117};
118
080cbcb4 119static const int legacy_connector_convert[] = {
771fe6b9
JG		 120 DRM_MODE_CONNECTOR_Unknown,
121 DRM_MODE_CONNECTOR_DVID,
122 DRM_MODE_CONNECTOR_VGA,
123 DRM_MODE_CONNECTOR_DVII,
124 DRM_MODE_CONNECTOR_DVID,
125 DRM_MODE_CONNECTOR_Composite,
126 DRM_MODE_CONNECTOR_SVIDEO,
127 DRM_MODE_CONNECTOR_Unknown,
128};
129
130static uint16_t combios_get_table_offset(struct drm_device *dev,
131 enum radeon_combios_table_offset table)
132{
133 struct radeon_device *rdev = dev->dev_private;
cef1d00c 134 int rev, size;
771fe6b9
JG		 135 uint16_t offset = 0, check_offset;
136
03047cdf
MD		 137 if (!rdev->bios)
138 return 0;
139
771fe6b9
JG		 140 switch (table) {
141 /* absolute offset tables */
142 case COMBIOS_ASIC_INIT_1_TABLE:
cef1d00c 143 check_offset = 0xc;
771fe6b9
JG		 144 break;
145 case COMBIOS_BIOS_SUPPORT_TABLE:
cef1d00c 146 check_offset = 0x14;
771fe6b9
JG		 147 break;
148 case COMBIOS_DAC_PROGRAMMING_TABLE:
cef1d00c 149 check_offset = 0x2a;
771fe6b9
JG		 150 break;
151 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
cef1d00c 152 check_offset = 0x2c;
771fe6b9
JG		 153 break;
154 case COMBIOS_CRTC_INFO_TABLE:
cef1d00c 155 check_offset = 0x2e;
771fe6b9
JG		 156 break;
157 case COMBIOS_PLL_INFO_TABLE:
cef1d00c 158 check_offset = 0x30;
771fe6b9
JG		 159 break;
160 case COMBIOS_TV_INFO_TABLE:
cef1d00c 161 check_offset = 0x32;
771fe6b9
JG		 162 break;
163 case COMBIOS_DFP_INFO_TABLE:
cef1d00c 164 check_offset = 0x34;
771fe6b9
JG		 165 break;
166 case COMBIOS_HW_CONFIG_INFO_TABLE:
cef1d00c 167 check_offset = 0x36;
771fe6b9
JG		 168 break;
169 case COMBIOS_MULTIMEDIA_INFO_TABLE:
cef1d00c 170 check_offset = 0x38;
771fe6b9
JG		 171 break;
172 case COMBIOS_TV_STD_PATCH_TABLE:
cef1d00c 173 check_offset = 0x3e;
771fe6b9
JG		 174 break;
175 case COMBIOS_LCD_INFO_TABLE:
cef1d00c 176 check_offset = 0x40;
771fe6b9
JG		 177 break;
178 case COMBIOS_MOBILE_INFO_TABLE:
cef1d00c 179 check_offset = 0x42;
771fe6b9
JG		 180 break;
181 case COMBIOS_PLL_INIT_TABLE:
cef1d00c 182 check_offset = 0x46;
771fe6b9
JG		 183 break;
184 case COMBIOS_MEM_CONFIG_TABLE:
cef1d00c 185 check_offset = 0x48;
771fe6b9
JG		 186 break;
187 case COMBIOS_SAVE_MASK_TABLE:
cef1d00c 188 check_offset = 0x4a;
771fe6b9
JG		 189 break;
190 case COMBIOS_HARDCODED_EDID_TABLE:
cef1d00c 191 check_offset = 0x4c;
771fe6b9
JG		 192 break;
193 case COMBIOS_ASIC_INIT_2_TABLE:
cef1d00c 194 check_offset = 0x4e;
771fe6b9
JG		 195 break;
196 case COMBIOS_CONNECTOR_INFO_TABLE:
cef1d00c 197 check_offset = 0x50;
771fe6b9
JG		 198 break;
199 case COMBIOS_DYN_CLK_1_TABLE:
cef1d00c 200 check_offset = 0x52;
771fe6b9
JG		 201 break;
202 case COMBIOS_RESERVED_MEM_TABLE:
cef1d00c 203 check_offset = 0x54;
771fe6b9
JG		 204 break;
205 case COMBIOS_EXT_TMDS_INFO_TABLE:
cef1d00c 206 check_offset = 0x58;
771fe6b9
JG		 207 break;
208 case COMBIOS_MEM_CLK_INFO_TABLE:
cef1d00c 209 check_offset = 0x5a;
771fe6b9
JG		 210 break;
211 case COMBIOS_EXT_DAC_INFO_TABLE:
cef1d00c 212 check_offset = 0x5c;
771fe6b9
JG		 213 break;
214 case COMBIOS_MISC_INFO_TABLE:
cef1d00c 215 check_offset = 0x5e;
771fe6b9
JG		 216 break;
217 case COMBIOS_CRT_INFO_TABLE:
cef1d00c 218 check_offset = 0x60;
771fe6b9
JG		 219 break;
220 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
cef1d00c 221 check_offset = 0x62;
771fe6b9
JG		 222 break;
223 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
cef1d00c 224 check_offset = 0x64;
771fe6b9
JG		 225 break;
226 case COMBIOS_FAN_SPEED_INFO_TABLE:
cef1d00c 227 check_offset = 0x66;
771fe6b9
JG		 228 break;
229 case COMBIOS_OVERDRIVE_INFO_TABLE:
cef1d00c 230 check_offset = 0x68;
771fe6b9
JG		 231 break;
232 case COMBIOS_OEM_INFO_TABLE:
cef1d00c 233 check_offset = 0x6a;
771fe6b9
JG		 234 break;
235 case COMBIOS_DYN_CLK_2_TABLE:
cef1d00c 236 check_offset = 0x6c;
771fe6b9
JG		 237 break;
238 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
cef1d00c 239 check_offset = 0x6e;
771fe6b9
JG		 240 break;
241 case COMBIOS_I2C_INFO_TABLE:
cef1d00c 242 check_offset = 0x70;
771fe6b9
JG		 243 break;
244 /* relative offset tables */
245 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
246 check_offset =
247 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
248 if (check_offset) {
249 rev = RBIOS8(check_offset);
250 if (rev > 0) {
251 check_offset = RBIOS16(check_offset + 0x3);
252 if (check_offset)
253 offset = check_offset;
254 }
255 }
256 break;
257 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
258 check_offset =
259 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
260 if (check_offset) {
261 rev = RBIOS8(check_offset);
262 if (rev > 0) {
263 check_offset = RBIOS16(check_offset + 0x5);
264 if (check_offset)
265 offset = check_offset;
266 }
267 }
268 break;
269 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
270 check_offset =
271 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
272 if (check_offset) {
273 rev = RBIOS8(check_offset);
274 if (rev > 0) {
275 check_offset = RBIOS16(check_offset + 0x7);
276 if (check_offset)
277 offset = check_offset;
278 }
279 }
280 break;
281 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
282 check_offset =
283 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
284 if (check_offset) {
285 rev = RBIOS8(check_offset);
286 if (rev == 2) {
287 check_offset = RBIOS16(check_offset + 0x9);
288 if (check_offset)
289 offset = check_offset;
290 }
291 }
292 break;
293 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
294 check_offset =
295 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
296 if (check_offset) {
297 while (RBIOS8(check_offset++));
298 check_offset += 2;
299 if (check_offset)
300 offset = check_offset;
301 }
302 break;
303 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
304 check_offset =
305 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
306 if (check_offset) {
307 check_offset = RBIOS16(check_offset + 0x11);
308 if (check_offset)
309 offset = check_offset;
310 }
311 break;
312 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
313 check_offset =
314 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
315 if (check_offset) {
316 check_offset = RBIOS16(check_offset + 0x13);
317 if (check_offset)
318 offset = check_offset;
319 }
320 break;
321 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
322 check_offset =
323 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
324 if (check_offset) {
325 check_offset = RBIOS16(check_offset + 0x15);
326 if (check_offset)
327 offset = check_offset;
328 }
329 break;
330 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
331 check_offset =
332 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
333 if (check_offset) {
334 check_offset = RBIOS16(check_offset + 0x17);
335 if (check_offset)
336 offset = check_offset;
337 }
338 break;
339 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
340 check_offset =
341 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
342 if (check_offset) {
343 check_offset = RBIOS16(check_offset + 0x2);
344 if (check_offset)
345 offset = check_offset;
346 }
347 break;
348 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
349 check_offset =
350 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
351 if (check_offset) {
352 check_offset = RBIOS16(check_offset + 0x4);
353 if (check_offset)
354 offset = check_offset;
355 }
356 break;
357 default:
cef1d00c 358 check_offset = 0;
771fe6b9
JG		 359 break;
360 }
361
cef1d00c
MK		 362 size = RBIOS8(rdev->bios_header_start + 0x6);
363 /* check absolute offset tables */
364 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
365 offset = RBIOS16(rdev->bios_header_start + check_offset);
771fe6b9 366
cef1d00c 367 return offset;
771fe6b9
JG		 368}
369
3c537889
AD		 370bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
371{
fafcf94e 372 int edid_info, size;
3c537889 373 struct edid *edid;
7466f4cc 374 unsigned char *raw;
3c537889
AD		 375 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
376 if (!edid_info)
377 return false;
378
7466f4cc 379 raw = rdev->bios + edid_info;
fafcf94e
AD		 380 size = EDID_LENGTH * (raw[0x7e] + 1);
381 edid = kmalloc(size, GFP_KERNEL);
3c537889
AD		 382 if (edid == NULL)
383 return false;
384
fafcf94e 385 memcpy((unsigned char *)edid, raw, size);
3c537889
AD		 386
387 if (!drm_edid_is_valid(edid)) {
388 kfree(edid);
389 return false;
390 }
391
392 rdev->mode_info.bios_hardcoded_edid = edid;
fafcf94e 393 rdev->mode_info.bios_hardcoded_edid_size = size;
3c537889
AD		 394 return true;
395}
396
c324acd5 397/* this is used for atom LCDs as well */
3c537889 398struct edid *
c324acd5 399radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
3c537889 400{
fafcf94e
AD		 401 struct edid *edid;
402
403 if (rdev->mode_info.bios_hardcoded_edid) {
404 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
405 if (edid) {
406 memcpy((unsigned char *)edid,
407 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
408 rdev->mode_info.bios_hardcoded_edid_size);
409 return edid;
410 }
411 }
3c537889
AD		 412 return NULL;
413}
414
6a93cb25 415static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
179e8078
AD		 416 enum radeon_combios_ddc ddc,
417 u32 clk_mask,
418 u32 data_mask)
771fe6b9
JG		 419{
420 struct radeon_i2c_bus_rec i2c;
179e8078
AD		 421 int ddc_line = 0;
422
423 /* ddc id = mask reg
424 * DDC_NONE_DETECTED = none
425 * DDC_DVI = RADEON_GPIO_DVI_DDC
426 * DDC_VGA = RADEON_GPIO_VGA_DDC
427 * DDC_LCD = RADEON_GPIOPAD_MASK
428 * DDC_GPIO = RADEON_MDGPIO_MASK
508c8d60 429 * r1xx
179e8078
AD		 430 * DDC_MONID = RADEON_GPIO_MONID
431 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
508c8d60 432 * r200
179e8078
AD		 433 * DDC_MONID = RADEON_GPIO_MONID
434 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
508c8d60
AD		 435 * r300/r350
436 * DDC_MONID = RADEON_GPIO_DVI_DDC
437 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
438 * rv2xx/rv3xx
439 * DDC_MONID = RADEON_GPIO_MONID
440 * DDC_CRT2 = RADEON_GPIO_MONID
179e8078
AD		 441 * rs3xx/rs4xx
442 * DDC_MONID = RADEON_GPIOPAD_MASK
443 * DDC_CRT2 = RADEON_GPIO_MONID
444 */
445 switch (ddc) {
446 case DDC_NONE_DETECTED:
447 default:
448 ddc_line = 0;
449 break;
450 case DDC_DVI:
451 ddc_line = RADEON_GPIO_DVI_DDC;
452 break;
453 case DDC_VGA:
454 ddc_line = RADEON_GPIO_VGA_DDC;
455 break;
456 case DDC_LCD:
457 ddc_line = RADEON_GPIOPAD_MASK;
458 break;
459 case DDC_GPIO:
460 ddc_line = RADEON_MDGPIO_MASK;
461 break;
462 case DDC_MONID:
463 if (rdev->family == CHIP_RS300 ||
464 rdev->family == CHIP_RS400 ||
465 rdev->family == CHIP_RS480)
466 ddc_line = RADEON_GPIOPAD_MASK;
508c8d60 467 else if (rdev->family == CHIP_R300 ||
776f2b7c 468 rdev->family == CHIP_R350) {
508c8d60 469 ddc_line = RADEON_GPIO_DVI_DDC;
776f2b7c
AD		 470 ddc = DDC_DVI;
471 } else
179e8078
AD		 472 ddc_line = RADEON_GPIO_MONID;
473 break;
474 case DDC_CRT2:
508c8d60
AD		 475 if (rdev->family == CHIP_R200 ||
476 rdev->family == CHIP_R300 ||
776f2b7c 477 rdev->family == CHIP_R350) {
179e8078 478 ddc_line = RADEON_GPIO_DVI_DDC;
776f2b7c
AD		 479 ddc = DDC_DVI;
480 } else if (rdev->family == CHIP_RS300 ||
481 rdev->family == CHIP_RS400 ||
482 rdev->family == CHIP_RS480)
508c8d60 483 ddc_line = RADEON_GPIO_MONID;
776f2b7c
AD		 484 else if (rdev->family >= CHIP_RV350) {
485 ddc_line = RADEON_GPIO_MONID;
486 ddc = DDC_MONID;
487 } else
179e8078
AD		 488 ddc_line = RADEON_GPIO_CRT2_DDC;
489 break;
490 }
771fe6b9 491
6a93cb25
AD		 492 if (ddc_line == RADEON_GPIOPAD_MASK) {
493 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
494 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
495 i2c.a_clk_reg = RADEON_GPIOPAD_A;
496 i2c.a_data_reg = RADEON_GPIOPAD_A;
497 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
498 i2c.en_data_reg = RADEON_GPIOPAD_EN;
499 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
500 i2c.y_data_reg = RADEON_GPIOPAD_Y;
501 } else if (ddc_line == RADEON_MDGPIO_MASK) {
502 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
503 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
504 i2c.a_clk_reg = RADEON_MDGPIO_A;
505 i2c.a_data_reg = RADEON_MDGPIO_A;
506 i2c.en_clk_reg = RADEON_MDGPIO_EN;
507 i2c.en_data_reg = RADEON_MDGPIO_EN;
508 i2c.y_clk_reg = RADEON_MDGPIO_Y;
509 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9
JG		 510 } else {
511 i2c.mask_clk_reg = ddc_line;
512 i2c.mask_data_reg = ddc_line;
513 i2c.a_clk_reg = ddc_line;
514 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 515 i2c.en_clk_reg = ddc_line;
516 i2c.en_data_reg = ddc_line;
517 i2c.y_clk_reg = ddc_line;
518 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 519 }
520
179e8078 521 if (clk_mask && data_mask) {
be663057 522 /* system specific masks */
179e8078
AD		 523 i2c.mask_clk_mask = clk_mask;
524 i2c.mask_data_mask = data_mask;
525 i2c.a_clk_mask = clk_mask;
526 i2c.a_data_mask = data_mask;
527 i2c.en_clk_mask = clk_mask;
528 i2c.en_data_mask = data_mask;
529 i2c.y_clk_mask = clk_mask;
530 i2c.y_data_mask = data_mask;
be663057
AD		 531 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
532 (ddc_line == RADEON_MDGPIO_MASK)) {
533 /* default gpiopad masks */
534 i2c.mask_clk_mask = (0x20 << 8);
535 i2c.mask_data_mask = 0x80;
536 i2c.a_clk_mask = (0x20 << 8);
537 i2c.a_data_mask = 0x80;
538 i2c.en_clk_mask = (0x20 << 8);
539 i2c.en_data_mask = 0x80;
540 i2c.y_clk_mask = (0x20 << 8);
541 i2c.y_data_mask = 0x80;
179e8078 542 } else {
be663057 543 /* default masks for ddc pads */
286e0c94
JD		 544 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
545 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
179e8078
AD		 546 i2c.a_clk_mask = RADEON_GPIO_A_1;
547 i2c.a_data_mask = RADEON_GPIO_A_0;
548 i2c.en_clk_mask = RADEON_GPIO_EN_1;
549 i2c.en_data_mask = RADEON_GPIO_EN_0;
550 i2c.y_clk_mask = RADEON_GPIO_Y_1;
551 i2c.y_data_mask = RADEON_GPIO_Y_0;
552 }
553
40bacf16
AD		 554 switch (rdev->family) {
555 case CHIP_R100:
556 case CHIP_RV100:
557 case CHIP_RS100:
558 case CHIP_RV200:
559 case CHIP_RS200:
560 case CHIP_RS300:
561 switch (ddc_line) {
562 case RADEON_GPIO_DVI_DDC:
b28ea411 563 i2c.hw_capable = true;
40bacf16
AD		 564 break;
565 default:
566 i2c.hw_capable = false;
567 break;
568 }
569 break;
570 case CHIP_R200:
571 switch (ddc_line) {
572 case RADEON_GPIO_DVI_DDC:
573 case RADEON_GPIO_MONID:
574 i2c.hw_capable = true;
575 break;
576 default:
577 i2c.hw_capable = false;
578 break;
579 }
580 break;
581 case CHIP_RV250:
582 case CHIP_RV280:
583 switch (ddc_line) {
584 case RADEON_GPIO_VGA_DDC:
585 case RADEON_GPIO_DVI_DDC:
586 case RADEON_GPIO_CRT2_DDC:
587 i2c.hw_capable = true;
588 break;
589 default:
590 i2c.hw_capable = false;
591 break;
592 }
593 break;
594 case CHIP_R300:
595 case CHIP_R350:
596 switch (ddc_line) {
597 case RADEON_GPIO_VGA_DDC:
598 case RADEON_GPIO_DVI_DDC:
599 i2c.hw_capable = true;
600 break;
601 default:
602 i2c.hw_capable = false;
603 break;
604 }
605 break;
606 case CHIP_RV350:
607 case CHIP_RV380:
608 case CHIP_RS400:
609 case CHIP_RS480:
6a93cb25
AD		 610 switch (ddc_line) {
611 case RADEON_GPIO_VGA_DDC:
612 case RADEON_GPIO_DVI_DDC:
613 i2c.hw_capable = true;
614 break;
615 case RADEON_GPIO_MONID:
616 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
617 * reliably on some pre-r4xx hardware; not sure why.
618 */
619 i2c.hw_capable = false;
620 break;
621 default:
622 i2c.hw_capable = false;
623 break;
624 }
40bacf16
AD		 625 break;
626 default:
627 i2c.hw_capable = false;
628 break;
6a93cb25
AD		 629 }
630 i2c.mm_i2c = false;
f376b94f 631
179e8078 632 i2c.i2c_id = ddc;
8e36ed00 633 i2c.hpd = RADEON_HPD_NONE;
6a93cb25 634
771fe6b9
JG		 635 if (ddc_line)
636 i2c.valid = true;
637 else
638 i2c.valid = false;
639
640 return i2c;
641}
642
3d61bd42
AD		 643static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
644{
645 struct drm_device *dev = rdev->ddev;
646 struct radeon_i2c_bus_rec i2c;
647 u16 offset;
648 u8 id, blocks, clk, data;
649 int i;
650
651 i2c.valid = false;
652
653 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
654 if (offset) {
655 blocks = RBIOS8(offset + 2);
656 for (i = 0; i < blocks; i++) {
657 id = RBIOS8(offset + 3 + (i * 5) + 0);
658 if (id == 136) {
659 clk = RBIOS8(offset + 3 + (i * 5) + 3);
660 data = RBIOS8(offset + 3 + (i * 5) + 4);
661 /* gpiopad */
662 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
663 (1 << clk), (1 << data));
664 break;
665 }
666 }
667 }
668 return i2c;
669}
670
f376b94f
AD		 671void radeon_combios_i2c_init(struct radeon_device *rdev)
672{
673 struct drm_device *dev = rdev->ddev;
674 struct radeon_i2c_bus_rec i2c;
675
508c8d60
AD		 676 /* actual hw pads
677 * r1xx/rs2xx/rs3xx
678 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
679 * r200
680 * 0x60, 0x64, 0x68, mm
681 * r300/r350
682 * 0x60, 0x64, mm
683 * rv2xx/rv3xx/rs4xx
684 * 0x60, 0x64, 0x68, gpiopads, mm
685 */
f376b94f 686
508c8d60 687 /* 0x60 */
179e8078
AD		 688 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
689 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
508c8d60 690 /* 0x64 */
179e8078
AD		 691 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
692 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
f376b94f 693
508c8d60 694 /* mm i2c */
f376b94f
AD		 695 i2c.valid = true;
696 i2c.hw_capable = true;
697 i2c.mm_i2c = true;
179e8078
AD		 698 i2c.i2c_id = 0xa0;
699 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
700
508c8d60
AD		 701 if (rdev->family == CHIP_R300 ||
702 rdev->family == CHIP_R350) {
703 /* only 2 sw i2c pads */
704 } else if (rdev->family == CHIP_RS300 ||
705 rdev->family == CHIP_RS400 ||
706 rdev->family == CHIP_RS480) {
508c8d60 707 /* 0x68 */
179e8078
AD		 708 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
709 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
710
3d61bd42
AD		 711 /* gpiopad */
712 i2c = radeon_combios_get_i2c_info_from_table(rdev);
713 if (i2c.valid)
714 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
6dd66633
AD		 715 } else if ((rdev->family == CHIP_R200) ||
716 (rdev->family >= CHIP_R300)) {
508c8d60 717 /* 0x68 */
179e8078
AD		 718 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
719 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
720 } else {
508c8d60 721 /* 0x68 */
179e8078
AD		 722 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
723 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
508c8d60 724 /* 0x6c */
179e8078
AD		 725 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
726 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
727 }
f376b94f
AD		 728}
729
771fe6b9
JG		 730bool radeon_combios_get_clock_info(struct drm_device *dev)
731{
732 struct radeon_device *rdev = dev->dev_private;
733 uint16_t pll_info;
734 struct radeon_pll *p1pll = &rdev->clock.p1pll;
735 struct radeon_pll *p2pll = &rdev->clock.p2pll;
736 struct radeon_pll *spll = &rdev->clock.spll;
737 struct radeon_pll *mpll = &rdev->clock.mpll;
738 int8_t rev;
739 uint16_t sclk, mclk;
740
771fe6b9
JG		 741 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
742 if (pll_info) {
743 rev = RBIOS8(pll_info);
744
745 /* pixel clocks */
746 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
747 p1pll->reference_div = RBIOS16(pll_info + 0x10);
748 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
749 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
86cb2bbf
AD		 750 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
751 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
771fe6b9
JG		 752
753 if (rev > 9) {
754 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
755 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
756 } else {
757 p1pll->pll_in_min = 40;
758 p1pll->pll_in_max = 500;
759 }
760 *p2pll = *p1pll;
761
762 /* system clock */
763 spll->reference_freq = RBIOS16(pll_info + 0x1a);
764 spll->reference_div = RBIOS16(pll_info + 0x1c);
765 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
766 spll->pll_out_max = RBIOS32(pll_info + 0x22);
767
768 if (rev > 10) {
769 spll->pll_in_min = RBIOS32(pll_info + 0x48);
770 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
771 } else {
772 /* ??? */
773 spll->pll_in_min = 40;
774 spll->pll_in_max = 500;
775 }
776
777 /* memory clock */
778 mpll->reference_freq = RBIOS16(pll_info + 0x26);
779 mpll->reference_div = RBIOS16(pll_info + 0x28);
780 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
781 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
782
783 if (rev > 10) {
784 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
785 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
786 } else {
787 /* ??? */
788 mpll->pll_in_min = 40;
789 mpll->pll_in_max = 500;
790 }
791
792 /* default sclk/mclk */
793 sclk = RBIOS16(pll_info + 0xa);
794 mclk = RBIOS16(pll_info + 0x8);
795 if (sclk == 0)
796 sclk = 200 * 100;
797 if (mclk == 0)
798 mclk = 200 * 100;
799
800 rdev->clock.default_sclk = sclk;
801 rdev->clock.default_mclk = mclk;
802
b20f9bef
AD		 803 if (RBIOS32(pll_info + 0x16))
804 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
805 else
806 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
807
771fe6b9
JG		 808 return true;
809 }
810 return false;
811}
812
06b6476d
AD		 813bool radeon_combios_sideport_present(struct radeon_device *rdev)
814{
815 struct drm_device *dev = rdev->ddev;
816 u16 igp_info;
817
4c70b2ea
AD		 818 /* sideport is AMD only */
819 if (rdev->family == CHIP_RS400)
820 return false;
821
06b6476d
AD		 822 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
823
824 if (igp_info) {
825 if (RBIOS16(igp_info + 0x4))
826 return true;
827 }
828 return false;
829}
830
246263cc
AD		 831static const uint32_t default_primarydac_adj[CHIP_LAST] = {
832 0x00000808, /* r100 */
833 0x00000808, /* rv100 */
834 0x00000808, /* rs100 */
835 0x00000808, /* rv200 */
836 0x00000808, /* rs200 */
837 0x00000808, /* r200 */
838 0x00000808, /* rv250 */
839 0x00000000, /* rs300 */
840 0x00000808, /* rv280 */
841 0x00000808, /* r300 */
842 0x00000808, /* r350 */
843 0x00000808, /* rv350 */
844 0x00000808, /* rv380 */
845 0x00000808, /* r420 */
846 0x00000808, /* r423 */
847 0x00000808, /* rv410 */
848 0x00000000, /* rs400 */
849 0x00000000, /* rs480 */
850};
851
852static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
853 struct radeon_encoder_primary_dac *p_dac)
854{
855 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
856 return;
857}
858
771fe6b9
JG		 859struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
860 radeon_encoder
861 *encoder)
862{
863 struct drm_device *dev = encoder->base.dev;
864 struct radeon_device *rdev = dev->dev_private;
865 uint16_t dac_info;
866 uint8_t rev, bg, dac;
3cc0f8f4 867 struct radeon_encoder_primary_dac *p_dac;
246263cc 868 int found = 0;
771fe6b9 869
246263cc
AD		 870 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
871 GFP_KERNEL);
872
873 if (!p_dac)
771fe6b9
JG		 874 return NULL;
875
876 /* check CRT table */
877 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
878 if (dac_info) {
771fe6b9
JG		 879 rev = RBIOS8(dac_info) & 0x3;
880 if (rev < 2) {
881 bg = RBIOS8(dac_info + 0x2) & 0xf;
882 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
883 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
884 } else {
885 bg = RBIOS8(dac_info + 0x2) & 0xf;
886 dac = RBIOS8(dac_info + 0x3) & 0xf;
887 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
888 }
03ed8cf9
AD		 889 /* if the values are zeros, use the table */
890 if ((dac == 0) || (bg == 0))
891 found = 0;
892 else
3a89b4a9 893 found = 1;
771fe6b9
JG		 894 }
895
e8fc4137 896 /* quirks */
f7929f34 897 /* Radeon 7000 (RV100) */
d86a4126
TZ		 898 if (((rdev->pdev->device == 0x5159) &&
899 (rdev->pdev->subsystem_vendor == 0x174B) &&
900 (rdev->pdev->subsystem_device == 0x7c28)) ||
e8fc4137 901 /* Radeon 9100 (R200) */
d86a4126
TZ		 902 ((rdev->pdev->device == 0x514D) &&
903 (rdev->pdev->subsystem_vendor == 0x174B) &&
904 (rdev->pdev->subsystem_device == 0x7149))) {
e8fc4137
AD		 905 /* vbios value is bad, use the default */
906 found = 0;
907 }
908
246263cc
AD		 909 if (!found) /* fallback to defaults */
910 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
911
771fe6b9
JG		 912 return p_dac;
913}
914
d79766fa
AD		 915enum radeon_tv_std
916radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 917{
d79766fa 918 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 919 uint16_t tv_info;
920 enum radeon_tv_std tv_std = TV_STD_NTSC;
921
922 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
923 if (tv_info) {
924 if (RBIOS8(tv_info + 6) == 'T') {
925 switch (RBIOS8(tv_info + 7) & 0xf) {
926 case 1:
927 tv_std = TV_STD_NTSC;
40f76d81 928 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
771fe6b9
JG		 929 break;
930 case 2:
931 tv_std = TV_STD_PAL;
40f76d81 932 DRM_DEBUG_KMS("Default TV standard: PAL\n");
771fe6b9
JG		 933 break;
934 case 3:
935 tv_std = TV_STD_PAL_M;
40f76d81 936 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
771fe6b9
JG		 937 break;
938 case 4:
939 tv_std = TV_STD_PAL_60;
40f76d81 940 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
771fe6b9
JG		 941 break;
942 case 5:
943 tv_std = TV_STD_NTSC_J;
40f76d81 944 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
771fe6b9
JG		 945 break;
946 case 6:
947 tv_std = TV_STD_SCART_PAL;
40f76d81 948 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
771fe6b9
JG		 949 break;
950 default:
951 tv_std = TV_STD_NTSC;
40f76d81 952 DRM_DEBUG_KMS
771fe6b9
JG		 953 ("Unknown TV standard; defaulting to NTSC\n");
954 break;
955 }
956
957 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
958 case 0:
40f76d81 959 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
771fe6b9
JG		 960 break;
961 case 1:
40f76d81 962 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
771fe6b9
JG		 963 break;
964 case 2:
40f76d81 965 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
771fe6b9
JG		 966 break;
967 case 3:
40f76d81 968 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
771fe6b9
JG		 969 break;
970 default:
971 break;
972 }
973 }
974 }
975 return tv_std;
976}
977
978static const uint32_t default_tvdac_adj[CHIP_LAST] = {
979 0x00000000, /* r100 */
980 0x00280000, /* rv100 */
981 0x00000000, /* rs100 */
982 0x00880000, /* rv200 */
983 0x00000000, /* rs200 */
984 0x00000000, /* r200 */
985 0x00770000, /* rv250 */
986 0x00290000, /* rs300 */
987 0x00560000, /* rv280 */
988 0x00780000, /* r300 */
989 0x00770000, /* r350 */
990 0x00780000, /* rv350 */
991 0x00780000, /* rv380 */
992 0x01080000, /* r420 */
993 0x01080000, /* r423 */
994 0x01080000, /* rv410 */
995 0x00780000, /* rs400 */
996 0x00780000, /* rs480 */
997};
998
6a719e05
DA		 999static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1000 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 1001{
771fe6b9
JG		 1002 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1003 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1004 tv_dac->ps2_tvdac_adj = 0x00880000;
1005 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1006 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 1007 return;
771fe6b9
JG		 1008}
1009
1010struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1011 radeon_encoder
1012 *encoder)
1013{
1014 struct drm_device *dev = encoder->base.dev;
1015 struct radeon_device *rdev = dev->dev_private;
1016 uint16_t dac_info;
1017 uint8_t rev, bg, dac;
3cc0f8f4 1018 struct radeon_encoder_tv_dac *tv_dac;
6a719e05
DA		 1019 int found = 0;
1020
1021 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1022 if (!tv_dac)
1023 return NULL;
771fe6b9 1024
771fe6b9
JG		 1025 /* first check TV table */
1026 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1027 if (dac_info) {
771fe6b9
JG		 1028 rev = RBIOS8(dac_info + 0x3);
1029 if (rev > 4) {
1030 bg = RBIOS8(dac_info + 0xc) & 0xf;
1031 dac = RBIOS8(dac_info + 0xd) & 0xf;
1032 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1033
1034 bg = RBIOS8(dac_info + 0xe) & 0xf;
1035 dac = RBIOS8(dac_info + 0xf) & 0xf;
1036 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1037
1038 bg = RBIOS8(dac_info + 0x10) & 0xf;
1039 dac = RBIOS8(dac_info + 0x11) & 0xf;
1040 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 1041 /* if the values are all zeros, use the table */
1042 if (tv_dac->ps2_tvdac_adj)
1043 found = 1;
771fe6b9
JG		 1044 } else if (rev > 1) {
1045 bg = RBIOS8(dac_info + 0xc) & 0xf;
1046 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1047 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1048
1049 bg = RBIOS8(dac_info + 0xd) & 0xf;
1050 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1051 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1052
1053 bg = RBIOS8(dac_info + 0xe) & 0xf;
1054 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1055 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
3a89b4a9
AD		 1056 /* if the values are all zeros, use the table */
1057 if (tv_dac->ps2_tvdac_adj)
1058 found = 1;
771fe6b9 1059 }
d79766fa 1060 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 1061 }
1062 if (!found) {
771fe6b9
JG		 1063 /* then check CRT table */
1064 dac_info =
1065 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1066 if (dac_info) {
771fe6b9
JG		 1067 rev = RBIOS8(dac_info) & 0x3;
1068 if (rev < 2) {
1069 bg = RBIOS8(dac_info + 0x3) & 0xf;
1070 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1071 tv_dac->ps2_tvdac_adj =
1072 (bg << 16) | (dac << 20);
1073 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1074 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 1075 /* if the values are all zeros, use the table */
1076 if (tv_dac->ps2_tvdac_adj)
1077 found = 1;
771fe6b9
JG		 1078 } else {
1079 bg = RBIOS8(dac_info + 0x4) & 0xf;
1080 dac = RBIOS8(dac_info + 0x5) & 0xf;
1081 tv_dac->ps2_tvdac_adj =
1082 (bg << 16) | (dac << 20);
1083 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1084 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
3a89b4a9
AD		 1085 /* if the values are all zeros, use the table */
1086 if (tv_dac->ps2_tvdac_adj)
1087 found = 1;
771fe6b9 1088 }
6fe7ac3f
AD		 1089 } else {
1090 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 1091 }
1092 }
1093
6a719e05
DA		 1094 if (!found) /* fallback to defaults */
1095 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1096
771fe6b9
JG		 1097 return tv_dac;
1098}
1099
1100static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1101 radeon_device
1102 *rdev)
1103{
3cc0f8f4 1104 struct radeon_encoder_lvds *lvds;
771fe6b9
JG		 1105 uint32_t fp_vert_stretch, fp_horz_stretch;
1106 uint32_t ppll_div_sel, ppll_val;
8b5c7444 1107 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 1108
1109 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1110
1111 if (!lvds)
1112 return NULL;
1113
1114 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1115 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1116
8b5c7444
MD		 1117 /* These should be fail-safe defaults, fingers crossed */
1118 lvds->panel_pwr_delay = 200;
1119 lvds->panel_vcc_delay = 2000;
1120
1121 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1122 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1123 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1124
771fe6b9 1125 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 1126 lvds->native_mode.vdisplay =
771fe6b9
JG		 1127 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1128 RADEON_VERT_PANEL_SHIFT) + 1;
1129 else
de2103e4 1130 lvds->native_mode.vdisplay =
771fe6b9
JG		 1131 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1132
1133 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 1134 lvds->native_mode.hdisplay =
771fe6b9
JG		 1135 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1136 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1137 else
de2103e4 1138 lvds->native_mode.hdisplay =
771fe6b9
JG		 1139 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1140
de2103e4
AD		 1141 if ((lvds->native_mode.hdisplay < 640) ||
1142 (lvds->native_mode.vdisplay < 480)) {
1143 lvds->native_mode.hdisplay = 640;
1144 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 1145 }
1146
1147 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1148 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1149 if ((ppll_val & 0x000707ff) == 0x1bb)
1150 lvds->use_bios_dividers = false;
1151 else {
1152 lvds->panel_ref_divider =
1153 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1154 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1155 lvds->panel_fb_divider = ppll_val & 0x7ff;
1156
1157 if ((lvds->panel_ref_divider != 0) &&
1158 (lvds->panel_fb_divider > 3))
1159 lvds->use_bios_dividers = true;
1160 }
1161 lvds->panel_vcc_delay = 200;
1162
1163 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 1164 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1165 lvds->native_mode.vdisplay);
771fe6b9
JG		 1166
1167 return lvds;
1168}
1169
1170struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1171 *encoder)
1172{
1173 struct drm_device *dev = encoder->base.dev;
1174 struct radeon_device *rdev = dev->dev_private;
1175 uint16_t lcd_info;
1176 uint32_t panel_setup;
1177 char stmp[30];
1178 int tmp, i;
1179 struct radeon_encoder_lvds *lvds = NULL;
1180
771fe6b9
JG		 1181 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1182
1183 if (lcd_info) {
1184 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1185
1186 if (!lvds)
1187 return NULL;
1188
1189 for (i = 0; i < 24; i++)
1190 stmp[i] = RBIOS8(lcd_info + i + 1);
1191 stmp[24] = 0;
1192
1193 DRM_INFO("Panel ID String: %s\n", stmp);
1194
de2103e4
AD		 1195 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1196 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 1197
de2103e4
AD		 1198 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1199 lvds->native_mode.vdisplay);
771fe6b9
JG		 1200
1201 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
94cf6434 1202 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
771fe6b9
JG		 1203
1204 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1205 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1206 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1207
1208 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1209 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1210 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1211 if ((lvds->panel_ref_divider != 0) &&
1212 (lvds->panel_fb_divider > 3))
1213 lvds->use_bios_dividers = true;
1214
1215 panel_setup = RBIOS32(lcd_info + 0x39);
1216 lvds->lvds_gen_cntl = 0xff00;
1217 if (panel_setup & 0x1)
1218 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1219
1220 if ((panel_setup >> 4) & 0x1)
1221 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1222
1223 switch ((panel_setup >> 8) & 0x7) {
1224 case 0:
1225 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1226 break;
1227 case 1:
1228 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1229 break;
1230 case 2:
1231 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1232 break;
1233 default:
1234 break;
1235 }
1236
1237 if ((panel_setup >> 16) & 0x1)
1238 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1239
1240 if ((panel_setup >> 17) & 0x1)
1241 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1242
1243 if ((panel_setup >> 18) & 0x1)
1244 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1245
1246 if ((panel_setup >> 23) & 0x1)
1247 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1248
1249 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1250
1251 for (i = 0; i < 32; i++) {
1252 tmp = RBIOS16(lcd_info + 64 + i * 2);
1253 if (tmp == 0)
1254 break;
1255
de2103e4 1256 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
68b61a7f 1257 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
0a90a0cf
AD		 1258 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1259
1260 if (hss > lvds->native_mode.hdisplay)
1261 hss = (10 - 1) * 8;
1262
68b61a7f
AD		 1263 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1264 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1265 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
0a90a0cf 1266 hss;
68b61a7f
AD		 1267 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1268 (RBIOS8(tmp + 23) * 8);
1269
1270 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1271 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1272 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1273 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1274 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1275 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
de2103e4
AD		 1276
1277 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1278 lvds->native_mode.flags = 0;
de2103e4
AD		 1279 /* set crtc values */
1280 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1281
771fe6b9
JG		 1282 }
1283 }
6fe7ac3f 1284 } else {
771fe6b9 1285 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1286 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1287 }
03047cdf 1288
8dfaa8a7
MD		 1289 if (lvds)
1290 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1291 return lvds;
1292}
1293
1294static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1295 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1296 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1297 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1298 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1299 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1300 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1301 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1302 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1303 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1304 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1305 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1306 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1307 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1308 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1309 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1310 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1311 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1312 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1313};
1314
445282db
DA		 1315bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1316 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1317{
445282db
DA		 1318 struct drm_device *dev = encoder->base.dev;
1319 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1320 int i;
771fe6b9
JG		 1321
1322 for (i = 0; i < 4; i++) {
1323 tmds->tmds_pll[i].value =
445282db 1324 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1325 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1326 }
1327
445282db 1328 return true;
771fe6b9
JG		 1329}
1330
445282db
DA		 1331bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1332 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1333{
1334 struct drm_device *dev = encoder->base.dev;
1335 struct radeon_device *rdev = dev->dev_private;
1336 uint16_t tmds_info;
1337 int i, n;
1338 uint8_t ver;
771fe6b9 1339
771fe6b9
JG		 1340 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1341
1342 if (tmds_info) {
771fe6b9 1343 ver = RBIOS8(tmds_info);
40f76d81 1344 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
771fe6b9
JG		 1345 if (ver == 3) {
1346 n = RBIOS8(tmds_info + 5) + 1;
1347 if (n > 4)
1348 n = 4;
1349 for (i = 0; i < n; i++) {
1350 tmds->tmds_pll[i].value =
1351 RBIOS32(tmds_info + i * 10 + 0x08);
1352 tmds->tmds_pll[i].freq =
1353 RBIOS16(tmds_info + i * 10 + 0x10);
d9fdaafb 1354 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
771fe6b9
JG		 1355 tmds->tmds_pll[i].freq,
1356 tmds->tmds_pll[i].value);
1357 }
1358 } else if (ver == 4) {
1359 int stride = 0;
1360 n = RBIOS8(tmds_info + 5) + 1;
1361 if (n > 4)
1362 n = 4;
1363 for (i = 0; i < n; i++) {
1364 tmds->tmds_pll[i].value =
1365 RBIOS32(tmds_info + stride + 0x08);
1366 tmds->tmds_pll[i].freq =
1367 RBIOS16(tmds_info + stride + 0x10);
1368 if (i == 0)
1369 stride += 10;
1370 else
1371 stride += 6;
d9fdaafb 1372 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
771fe6b9
JG		 1373 tmds->tmds_pll[i].freq,
1374 tmds->tmds_pll[i].value);
1375 }
1376 }
fcec570b 1377 } else {
771fe6b9 1378 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1379 return false;
1380 }
445282db
DA		 1381 return true;
1382}
1383
fcec570b
AD		 1384bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1385 struct radeon_encoder_ext_tmds *tmds)
445282db 1386{
fcec570b
AD		 1387 struct drm_device *dev = encoder->base.dev;
1388 struct radeon_device *rdev = dev->dev_private;
1389 struct radeon_i2c_bus_rec i2c_bus;
445282db 1390
fcec570b 1391 /* default for macs */
179e8078 1392 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
f376b94f 1393 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
445282db 1394
fcec570b
AD		 1395 /* XXX some macs have duallink chips */
1396 switch (rdev->mode_info.connector_table) {
1397 case CT_POWERBOOK_EXTERNAL:
1398 case CT_MINI_EXTERNAL:
1399 default:
1400 tmds->dvo_chip = DVO_SIL164;
1401 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1402 break;
1403 }
445282db 1404
fcec570b 1405 return true;
771fe6b9
JG		 1406}
1407
fcec570b
AD		 1408bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1409 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1410{
1411 struct drm_device *dev = encoder->base.dev;
1412 struct radeon_device *rdev = dev->dev_private;
fcec570b 1413 uint16_t offset;
179e8078 1414 uint8_t ver;
fcec570b
AD		 1415 enum radeon_combios_ddc gpio;
1416 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9 1417
fcec570b
AD		 1418 tmds->i2c_bus = NULL;
1419 if (rdev->flags & RADEON_IS_IGP) {
179e8078
AD		 1420 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1421 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1422 tmds->dvo_chip = DVO_SIL164;
1423 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
fcec570b
AD		 1424 } else {
1425 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1426 if (offset) {
1427 ver = RBIOS8(offset);
40f76d81 1428 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
fcec570b
AD		 1429 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1430 tmds->slave_addr >>= 1; /* 7 bit addressing */
1431 gpio = RBIOS8(offset + 4 + 3);
179e8078
AD		 1432 if (gpio == DDC_LCD) {
1433 /* MM i2c */
40bacf16
AD		 1434 i2c_bus.valid = true;
1435 i2c_bus.hw_capable = true;
1436 i2c_bus.mm_i2c = true;
179e8078
AD		 1437 i2c_bus.i2c_id = 0xa0;
1438 } else
1439 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1440 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
fcec570b 1441 }
771fe6b9 1442 }
fcec570b
AD		 1443
1444 if (!tmds->i2c_bus) {
1445 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1446 return false;
1447 }
1448
1449 return true;
771fe6b9
JG		 1450}
1451
1452bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1453{
1454 struct radeon_device *rdev = dev->dev_private;
1455 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1456 struct radeon_hpd hpd;
771fe6b9
JG		 1457
1458 rdev->mode_info.connector_table = radeon_connector_table;
1459 if (rdev->mode_info.connector_table == CT_NONE) {
1460#ifdef CONFIG_PPC_PMAC
71a157e8 1461 if (of_machine_is_compatible("PowerBook3,3")) {
771fe6b9
JG		 1462 /* powerbook with VGA */
1463 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
71a157e8
GL		 1464 } else if (of_machine_is_compatible("PowerBook3,4") ||
1465 of_machine_is_compatible("PowerBook3,5")) {
771fe6b9
JG		 1466 /* powerbook with internal tmds */
1467 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
71a157e8
GL		 1468 } else if (of_machine_is_compatible("PowerBook5,1") ||
1469 of_machine_is_compatible("PowerBook5,2") ||
1470 of_machine_is_compatible("PowerBook5,3") ||
1471 of_machine_is_compatible("PowerBook5,4") ||
1472 of_machine_is_compatible("PowerBook5,5")) {
771fe6b9
JG		 1473 /* powerbook with external single link tmds (sil164) */
1474 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8 1475 } else if (of_machine_is_compatible("PowerBook5,6")) {
771fe6b9
JG		 1476 /* powerbook with external dual or single link tmds */
1477 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1478 } else if (of_machine_is_compatible("PowerBook5,7") ||
1479 of_machine_is_compatible("PowerBook5,8") ||
1480 of_machine_is_compatible("PowerBook5,9")) {
771fe6b9
JG		 1481 /* PowerBook6,2 ? */
1482 /* powerbook with external dual link tmds (sil1178?) */
1483 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
71a157e8
GL		 1484 } else if (of_machine_is_compatible("PowerBook4,1") ||
1485 of_machine_is_compatible("PowerBook4,2") ||
1486 of_machine_is_compatible("PowerBook4,3") ||
1487 of_machine_is_compatible("PowerBook6,3") ||
1488 of_machine_is_compatible("PowerBook6,5") ||
1489 of_machine_is_compatible("PowerBook6,7")) {
771fe6b9
JG		 1490 /* ibook */
1491 rdev->mode_info.connector_table = CT_IBOOK;
cafa59b9
AD		 1492 } else if (of_machine_is_compatible("PowerMac3,5")) {
1493 /* PowerMac G4 Silver radeon 7500 */
1494 rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
71a157e8 1495 } else if (of_machine_is_compatible("PowerMac4,4")) {
771fe6b9
JG		 1496 /* emac */
1497 rdev->mode_info.connector_table = CT_EMAC;
71a157e8 1498 } else if (of_machine_is_compatible("PowerMac10,1")) {
771fe6b9
JG		 1499 /* mini with internal tmds */
1500 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
71a157e8 1501 } else if (of_machine_is_compatible("PowerMac10,2")) {
771fe6b9
JG		 1502 /* mini with external tmds */
1503 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
71a157e8 1504 } else if (of_machine_is_compatible("PowerMac12,1")) {
771fe6b9
JG		 1505 /* PowerMac8,1 ? */
1506 /* imac g5 isight */
1507 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
aa74fbb4
AD		 1508 } else if ((rdev->pdev->device == 0x4a48) &&
1509 (rdev->pdev->subsystem_vendor == 0x1002) &&
1510 (rdev->pdev->subsystem_device == 0x4a48)) {
1511 /* Mac X800 */
1512 rdev->mode_info.connector_table = CT_MAC_X800;
7c88d2b8
AD		 1513 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1514 of_machine_is_compatible("PowerMac7,3")) &&
1515 (rdev->pdev->device == 0x4150) &&
1516 (rdev->pdev->subsystem_vendor == 0x1002) &&
1517 (rdev->pdev->subsystem_device == 0x4150)) {
1518 /* Mac G5 tower 9600 */
9fad321a 1519 rdev->mode_info.connector_table = CT_MAC_G5_9600;
6a556039
AD		 1520 } else if ((rdev->pdev->device == 0x4c66) &&
1521 (rdev->pdev->subsystem_vendor == 0x1002) &&
1522 (rdev->pdev->subsystem_device == 0x4c66)) {
1523 /* SAM440ep RV250 embedded board */
1524 rdev->mode_info.connector_table = CT_SAM440EP;
771fe6b9
JG		 1525 } else
1526#endif /* CONFIG_PPC_PMAC */
76a7142a
DA		 1527#ifdef CONFIG_PPC64
1528 if (ASIC_IS_RN50(rdev))
1529 rdev->mode_info.connector_table = CT_RN50_POWER;
1530 else
1531#endif
771fe6b9
JG		 1532 rdev->mode_info.connector_table = CT_GENERIC;
1533 }
1534
1535 switch (rdev->mode_info.connector_table) {
1536 case CT_GENERIC:
1537 DRM_INFO("Connector Table: %d (generic)\n",
1538 rdev->mode_info.connector_table);
1539 /* these are the most common settings */
1540 if (rdev->flags & RADEON_SINGLE_CRTC) {
1541 /* VGA - primary dac */
179e8078 1542 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1543 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1544 radeon_add_legacy_encoder(dev,
5137ee94 1545 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1546 ATOM_DEVICE_CRT1_SUPPORT,
1547 1),
1548 ATOM_DEVICE_CRT1_SUPPORT);
1549 radeon_add_legacy_connector(dev, 0,
1550 ATOM_DEVICE_CRT1_SUPPORT,
1551 DRM_MODE_CONNECTOR_VGA,
b75fad06 1552 &ddc_i2c,
eed45b30
AD		 1553 CONNECTOR_OBJECT_ID_VGA,
1554 &hpd);
771fe6b9
JG		 1555 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1556 /* LVDS */
179e8078 1557 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
eed45b30 1558 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1559 radeon_add_legacy_encoder(dev,
5137ee94 1560 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1561 ATOM_DEVICE_LCD1_SUPPORT,
1562 0),
1563 ATOM_DEVICE_LCD1_SUPPORT);
1564 radeon_add_legacy_connector(dev, 0,
1565 ATOM_DEVICE_LCD1_SUPPORT,
1566 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1567 &ddc_i2c,
eed45b30
AD		 1568 CONNECTOR_OBJECT_ID_LVDS,
1569 &hpd);
771fe6b9
JG		 1570
1571 /* VGA - primary dac */
179e8078 1572 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1573 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1574 radeon_add_legacy_encoder(dev,
5137ee94 1575 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1576 ATOM_DEVICE_CRT1_SUPPORT,
1577 1),
1578 ATOM_DEVICE_CRT1_SUPPORT);
1579 radeon_add_legacy_connector(dev, 1,
1580 ATOM_DEVICE_CRT1_SUPPORT,
1581 DRM_MODE_CONNECTOR_VGA,
b75fad06 1582 &ddc_i2c,
eed45b30
AD		 1583 CONNECTOR_OBJECT_ID_VGA,
1584 &hpd);
771fe6b9
JG		 1585 } else {
1586 /* DVI-I - tv dac, int tmds */
179e8078 1587 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1588 hpd.hpd = RADEON_HPD_1;
771fe6b9 1589 radeon_add_legacy_encoder(dev,
5137ee94 1590 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1591 ATOM_DEVICE_DFP1_SUPPORT,
1592 0),
1593 ATOM_DEVICE_DFP1_SUPPORT);
1594 radeon_add_legacy_encoder(dev,
5137ee94 1595 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1596 ATOM_DEVICE_CRT2_SUPPORT,
1597 2),
1598 ATOM_DEVICE_CRT2_SUPPORT);
1599 radeon_add_legacy_connector(dev, 0,
1600 ATOM_DEVICE_DFP1_SUPPORT |
1601 ATOM_DEVICE_CRT2_SUPPORT,
1602 DRM_MODE_CONNECTOR_DVII,
b75fad06 1603 &ddc_i2c,
eed45b30
AD		 1604 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1605 &hpd);
771fe6b9
JG		 1606
1607 /* VGA - primary dac */
179e8078 1608 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1609 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1610 radeon_add_legacy_encoder(dev,
5137ee94 1611 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1612 ATOM_DEVICE_CRT1_SUPPORT,
1613 1),
1614 ATOM_DEVICE_CRT1_SUPPORT);
1615 radeon_add_legacy_connector(dev, 1,
1616 ATOM_DEVICE_CRT1_SUPPORT,
1617 DRM_MODE_CONNECTOR_VGA,
b75fad06 1618 &ddc_i2c,
eed45b30
AD		 1619 CONNECTOR_OBJECT_ID_VGA,
1620 &hpd);
771fe6b9
JG		 1621 }
1622
1623 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1624 /* TV - tv dac */
eed45b30
AD		 1625 ddc_i2c.valid = false;
1626 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1627 radeon_add_legacy_encoder(dev,
5137ee94 1628 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1629 ATOM_DEVICE_TV1_SUPPORT,
1630 2),
1631 ATOM_DEVICE_TV1_SUPPORT);
1632 radeon_add_legacy_connector(dev, 2,
1633 ATOM_DEVICE_TV1_SUPPORT,
1634 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1635 &ddc_i2c,
eed45b30
AD		 1636 CONNECTOR_OBJECT_ID_SVIDEO,
1637 &hpd);
771fe6b9
JG		 1638 }
1639 break;
1640 case CT_IBOOK:
1641 DRM_INFO("Connector Table: %d (ibook)\n",
1642 rdev->mode_info.connector_table);
1643 /* LVDS */
179e8078 1644 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1645 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1646 radeon_add_legacy_encoder(dev,
5137ee94 1647 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1648 ATOM_DEVICE_LCD1_SUPPORT,
1649 0),
1650 ATOM_DEVICE_LCD1_SUPPORT);
1651 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1652 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1653 CONNECTOR_OBJECT_ID_LVDS,
1654 &hpd);
771fe6b9 1655 /* VGA - TV DAC */
179e8078 1656 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1657 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1658 radeon_add_legacy_encoder(dev,
5137ee94 1659 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1660 ATOM_DEVICE_CRT2_SUPPORT,
1661 2),
1662 ATOM_DEVICE_CRT2_SUPPORT);
1663 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1664 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1665 CONNECTOR_OBJECT_ID_VGA,
1666 &hpd);
771fe6b9 1667 /* TV - TV DAC */
eed45b30
AD		 1668 ddc_i2c.valid = false;
1669 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1670 radeon_add_legacy_encoder(dev,
5137ee94 1671 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1672 ATOM_DEVICE_TV1_SUPPORT,
1673 2),
1674 ATOM_DEVICE_TV1_SUPPORT);
1675 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1676 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1677 &ddc_i2c,
eed45b30
AD		 1678 CONNECTOR_OBJECT_ID_SVIDEO,
1679 &hpd);
771fe6b9
JG		 1680 break;
1681 case CT_POWERBOOK_EXTERNAL:
1682 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1683 rdev->mode_info.connector_table);
1684 /* LVDS */
179e8078 1685 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1686 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1687 radeon_add_legacy_encoder(dev,
5137ee94 1688 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1689 ATOM_DEVICE_LCD1_SUPPORT,
1690 0),
1691 ATOM_DEVICE_LCD1_SUPPORT);
1692 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1693 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1694 CONNECTOR_OBJECT_ID_LVDS,
1695 &hpd);
771fe6b9 1696 /* DVI-I - primary dac, ext tmds */
179e8078 1697 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1698 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9 1699 radeon_add_legacy_encoder(dev,
5137ee94 1700 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1701 ATOM_DEVICE_DFP2_SUPPORT,
1702 0),
1703 ATOM_DEVICE_DFP2_SUPPORT);
1704 radeon_add_legacy_encoder(dev,
5137ee94 1705 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1706 ATOM_DEVICE_CRT1_SUPPORT,
1707 1),
1708 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1709 /* XXX some are SL */
771fe6b9
JG		 1710 radeon_add_legacy_connector(dev, 1,
1711 ATOM_DEVICE_DFP2_SUPPORT |
1712 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1713 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1714 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1715 &hpd);
771fe6b9 1716 /* TV - TV DAC */
eed45b30
AD		 1717 ddc_i2c.valid = false;
1718 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1719 radeon_add_legacy_encoder(dev,
5137ee94 1720 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1721 ATOM_DEVICE_TV1_SUPPORT,
1722 2),
1723 ATOM_DEVICE_TV1_SUPPORT);
1724 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1725 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1726 &ddc_i2c,
eed45b30
AD		 1727 CONNECTOR_OBJECT_ID_SVIDEO,
1728 &hpd);
771fe6b9
JG		 1729 break;
1730 case CT_POWERBOOK_INTERNAL:
1731 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1732 rdev->mode_info.connector_table);
1733 /* LVDS */
179e8078 1734 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1735 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1736 radeon_add_legacy_encoder(dev,
5137ee94 1737 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1738 ATOM_DEVICE_LCD1_SUPPORT,
1739 0),
1740 ATOM_DEVICE_LCD1_SUPPORT);
1741 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1742 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1743 CONNECTOR_OBJECT_ID_LVDS,
1744 &hpd);
771fe6b9 1745 /* DVI-I - primary dac, int tmds */
179e8078 1746 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1747 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1748 radeon_add_legacy_encoder(dev,
5137ee94 1749 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1750 ATOM_DEVICE_DFP1_SUPPORT,
1751 0),
1752 ATOM_DEVICE_DFP1_SUPPORT);
1753 radeon_add_legacy_encoder(dev,
5137ee94 1754 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1755 ATOM_DEVICE_CRT1_SUPPORT,
1756 1),
1757 ATOM_DEVICE_CRT1_SUPPORT);
1758 radeon_add_legacy_connector(dev, 1,
1759 ATOM_DEVICE_DFP1_SUPPORT |
1760 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1761 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1762 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1763 &hpd);
771fe6b9 1764 /* TV - TV DAC */
eed45b30
AD		 1765 ddc_i2c.valid = false;
1766 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1767 radeon_add_legacy_encoder(dev,
5137ee94 1768 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1769 ATOM_DEVICE_TV1_SUPPORT,
1770 2),
1771 ATOM_DEVICE_TV1_SUPPORT);
1772 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1773 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1774 &ddc_i2c,
eed45b30
AD		 1775 CONNECTOR_OBJECT_ID_SVIDEO,
1776 &hpd);
771fe6b9
JG		 1777 break;
1778 case CT_POWERBOOK_VGA:
1779 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1780 rdev->mode_info.connector_table);
1781 /* LVDS */
179e8078 1782 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1783 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1784 radeon_add_legacy_encoder(dev,
5137ee94 1785 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1786 ATOM_DEVICE_LCD1_SUPPORT,
1787 0),
1788 ATOM_DEVICE_LCD1_SUPPORT);
1789 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1790 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1791 CONNECTOR_OBJECT_ID_LVDS,
1792 &hpd);
771fe6b9 1793 /* VGA - primary dac */
179e8078 1794 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1795 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1796 radeon_add_legacy_encoder(dev,
5137ee94 1797 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1798 ATOM_DEVICE_CRT1_SUPPORT,
1799 1),
1800 ATOM_DEVICE_CRT1_SUPPORT);
1801 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1802 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1803 CONNECTOR_OBJECT_ID_VGA,
1804 &hpd);
771fe6b9 1805 /* TV - TV DAC */
eed45b30
AD		 1806 ddc_i2c.valid = false;
1807 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1808 radeon_add_legacy_encoder(dev,
5137ee94 1809 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1810 ATOM_DEVICE_TV1_SUPPORT,
1811 2),
1812 ATOM_DEVICE_TV1_SUPPORT);
1813 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1814 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1815 &ddc_i2c,
eed45b30
AD		 1816 CONNECTOR_OBJECT_ID_SVIDEO,
1817 &hpd);
771fe6b9
JG		 1818 break;
1819 case CT_MINI_EXTERNAL:
1820 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1821 rdev->mode_info.connector_table);
1822 /* DVI-I - tv dac, ext tmds */
179e8078 1823 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1824 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9 1825 radeon_add_legacy_encoder(dev,
5137ee94 1826 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1827 ATOM_DEVICE_DFP2_SUPPORT,
1828 0),
1829 ATOM_DEVICE_DFP2_SUPPORT);
1830 radeon_add_legacy_encoder(dev,
5137ee94 1831 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1832 ATOM_DEVICE_CRT2_SUPPORT,
1833 2),
1834 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1835 /* XXX are any DL? */
771fe6b9
JG		 1836 radeon_add_legacy_connector(dev, 0,
1837 ATOM_DEVICE_DFP2_SUPPORT |
1838 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1839 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1840 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1841 &hpd);
771fe6b9 1842 /* TV - TV DAC */
eed45b30
AD		 1843 ddc_i2c.valid = false;
1844 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1845 radeon_add_legacy_encoder(dev,
5137ee94 1846 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1847 ATOM_DEVICE_TV1_SUPPORT,
1848 2),
1849 ATOM_DEVICE_TV1_SUPPORT);
1850 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1851 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1852 &ddc_i2c,
eed45b30
AD		 1853 CONNECTOR_OBJECT_ID_SVIDEO,
1854 &hpd);
771fe6b9
JG		 1855 break;
1856 case CT_MINI_INTERNAL:
1857 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1858 rdev->mode_info.connector_table);
1859 /* DVI-I - tv dac, int tmds */
179e8078 1860 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1861 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1862 radeon_add_legacy_encoder(dev,
5137ee94 1863 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1864 ATOM_DEVICE_DFP1_SUPPORT,
1865 0),
1866 ATOM_DEVICE_DFP1_SUPPORT);
1867 radeon_add_legacy_encoder(dev,
5137ee94 1868 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1869 ATOM_DEVICE_CRT2_SUPPORT,
1870 2),
1871 ATOM_DEVICE_CRT2_SUPPORT);
1872 radeon_add_legacy_connector(dev, 0,
1873 ATOM_DEVICE_DFP1_SUPPORT |
1874 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1875 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1876 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1877 &hpd);
771fe6b9 1878 /* TV - TV DAC */
eed45b30
AD		 1879 ddc_i2c.valid = false;
1880 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1881 radeon_add_legacy_encoder(dev,
5137ee94 1882 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1883 ATOM_DEVICE_TV1_SUPPORT,
1884 2),
1885 ATOM_DEVICE_TV1_SUPPORT);
1886 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1887 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1888 &ddc_i2c,
eed45b30
AD		 1889 CONNECTOR_OBJECT_ID_SVIDEO,
1890 &hpd);
771fe6b9
JG		 1891 break;
1892 case CT_IMAC_G5_ISIGHT:
1893 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1894 rdev->mode_info.connector_table);
1895 /* DVI-D - int tmds */
179e8078 1896 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
eed45b30 1897 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9 1898 radeon_add_legacy_encoder(dev,
5137ee94 1899 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1900 ATOM_DEVICE_DFP1_SUPPORT,
1901 0),
1902 ATOM_DEVICE_DFP1_SUPPORT);
1903 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1904 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1905 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1906 &hpd);
771fe6b9 1907 /* VGA - tv dac */
179e8078 1908 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
eed45b30 1909 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1910 radeon_add_legacy_encoder(dev,
5137ee94 1911 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1912 ATOM_DEVICE_CRT2_SUPPORT,
1913 2),
1914 ATOM_DEVICE_CRT2_SUPPORT);
1915 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1916 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1917 CONNECTOR_OBJECT_ID_VGA,
1918 &hpd);
771fe6b9 1919 /* TV - TV DAC */
eed45b30
AD		 1920 ddc_i2c.valid = false;
1921 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1922 radeon_add_legacy_encoder(dev,
5137ee94 1923 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1924 ATOM_DEVICE_TV1_SUPPORT,
1925 2),
1926 ATOM_DEVICE_TV1_SUPPORT);
1927 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1928 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1929 &ddc_i2c,
eed45b30
AD		 1930 CONNECTOR_OBJECT_ID_SVIDEO,
1931 &hpd);
771fe6b9
JG		 1932 break;
1933 case CT_EMAC:
1934 DRM_INFO("Connector Table: %d (emac)\n",
1935 rdev->mode_info.connector_table);
1936 /* VGA - primary dac */
179e8078 1937 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 1938 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1939 radeon_add_legacy_encoder(dev,
5137ee94 1940 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1941 ATOM_DEVICE_CRT1_SUPPORT,
1942 1),
1943 ATOM_DEVICE_CRT1_SUPPORT);
1944 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1945 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1946 CONNECTOR_OBJECT_ID_VGA,
1947 &hpd);
771fe6b9 1948 /* VGA - tv dac */
179e8078 1949 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
eed45b30 1950 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1951 radeon_add_legacy_encoder(dev,
5137ee94 1952 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1953 ATOM_DEVICE_CRT2_SUPPORT,
1954 2),
1955 ATOM_DEVICE_CRT2_SUPPORT);
1956 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1957 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1958 CONNECTOR_OBJECT_ID_VGA,
1959 &hpd);
771fe6b9 1960 /* TV - TV DAC */
eed45b30
AD		 1961 ddc_i2c.valid = false;
1962 hpd.hpd = RADEON_HPD_NONE;
771fe6b9 1963 radeon_add_legacy_encoder(dev,
5137ee94 1964 radeon_get_encoder_enum(dev,
771fe6b9
JG		 1965 ATOM_DEVICE_TV1_SUPPORT,
1966 2),
1967 ATOM_DEVICE_TV1_SUPPORT);
1968 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1969 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1970 &ddc_i2c,
eed45b30
AD		 1971 CONNECTOR_OBJECT_ID_SVIDEO,
1972 &hpd);
771fe6b9 1973 break;
76a7142a
DA		 1974 case CT_RN50_POWER:
1975 DRM_INFO("Connector Table: %d (rn50-power)\n",
1976 rdev->mode_info.connector_table);
1977 /* VGA - primary dac */
179e8078 1978 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
76a7142a
DA		 1979 hpd.hpd = RADEON_HPD_NONE;
1980 radeon_add_legacy_encoder(dev,
5137ee94 1981 radeon_get_encoder_enum(dev,
76a7142a
DA		 1982 ATOM_DEVICE_CRT1_SUPPORT,
1983 1),
1984 ATOM_DEVICE_CRT1_SUPPORT);
1985 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1986 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1987 CONNECTOR_OBJECT_ID_VGA,
1988 &hpd);
179e8078 1989 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
76a7142a
DA		 1990 hpd.hpd = RADEON_HPD_NONE;
1991 radeon_add_legacy_encoder(dev,
5137ee94 1992 radeon_get_encoder_enum(dev,
76a7142a
DA		 1993 ATOM_DEVICE_CRT2_SUPPORT,
1994 2),
1995 ATOM_DEVICE_CRT2_SUPPORT);
1996 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1997 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1998 CONNECTOR_OBJECT_ID_VGA,
1999 &hpd);
2000 break;
aa74fbb4
AD		 2001 case CT_MAC_X800:
2002 DRM_INFO("Connector Table: %d (mac x800)\n",
2003 rdev->mode_info.connector_table);
2004 /* DVI - primary dac, internal tmds */
2005 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2006 hpd.hpd = RADEON_HPD_1; /* ??? */
2007 radeon_add_legacy_encoder(dev,
2008 radeon_get_encoder_enum(dev,
2009 ATOM_DEVICE_DFP1_SUPPORT,
2010 0),
2011 ATOM_DEVICE_DFP1_SUPPORT);
2012 radeon_add_legacy_encoder(dev,
2013 radeon_get_encoder_enum(dev,
2014 ATOM_DEVICE_CRT1_SUPPORT,
2015 1),
2016 ATOM_DEVICE_CRT1_SUPPORT);
2017 radeon_add_legacy_connector(dev, 0,
2018 ATOM_DEVICE_DFP1_SUPPORT |
2019 ATOM_DEVICE_CRT1_SUPPORT,
2020 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2021 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2022 &hpd);
2023 /* DVI - tv dac, dvo */
2024 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2025 hpd.hpd = RADEON_HPD_2; /* ??? */
2026 radeon_add_legacy_encoder(dev,
2027 radeon_get_encoder_enum(dev,
2028 ATOM_DEVICE_DFP2_SUPPORT,
2029 0),
2030 ATOM_DEVICE_DFP2_SUPPORT);
2031 radeon_add_legacy_encoder(dev,
2032 radeon_get_encoder_enum(dev,
2033 ATOM_DEVICE_CRT2_SUPPORT,
2034 2),
2035 ATOM_DEVICE_CRT2_SUPPORT);
2036 radeon_add_legacy_connector(dev, 1,
2037 ATOM_DEVICE_DFP2_SUPPORT |
2038 ATOM_DEVICE_CRT2_SUPPORT,
2039 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2040 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2041 &hpd);
2042 break;
9fad321a
AD		 2043 case CT_MAC_G5_9600:
2044 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2045 rdev->mode_info.connector_table);
2046 /* DVI - tv dac, dvo */
2047 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2048 hpd.hpd = RADEON_HPD_1; /* ??? */
2049 radeon_add_legacy_encoder(dev,
2050 radeon_get_encoder_enum(dev,
2051 ATOM_DEVICE_DFP2_SUPPORT,
2052 0),
2053 ATOM_DEVICE_DFP2_SUPPORT);
2054 radeon_add_legacy_encoder(dev,
2055 radeon_get_encoder_enum(dev,
2056 ATOM_DEVICE_CRT2_SUPPORT,
2057 2),
2058 ATOM_DEVICE_CRT2_SUPPORT);
2059 radeon_add_legacy_connector(dev, 0,
2060 ATOM_DEVICE_DFP2_SUPPORT |
2061 ATOM_DEVICE_CRT2_SUPPORT,
2062 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2063 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2064 &hpd);
2065 /* ADC - primary dac, internal tmds */
2066 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2067 hpd.hpd = RADEON_HPD_2; /* ??? */
2068 radeon_add_legacy_encoder(dev,
2069 radeon_get_encoder_enum(dev,
2070 ATOM_DEVICE_DFP1_SUPPORT,
2071 0),
2072 ATOM_DEVICE_DFP1_SUPPORT);
2073 radeon_add_legacy_encoder(dev,
2074 radeon_get_encoder_enum(dev,
2075 ATOM_DEVICE_CRT1_SUPPORT,
2076 1),
2077 ATOM_DEVICE_CRT1_SUPPORT);
2078 radeon_add_legacy_connector(dev, 1,
2079 ATOM_DEVICE_DFP1_SUPPORT |
2080 ATOM_DEVICE_CRT1_SUPPORT,
2081 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2082 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2083 &hpd);
beb47274
AD		 2084 /* TV - TV DAC */
2085 ddc_i2c.valid = false;
2086 hpd.hpd = RADEON_HPD_NONE;
2087 radeon_add_legacy_encoder(dev,
2088 radeon_get_encoder_enum(dev,
2089 ATOM_DEVICE_TV1_SUPPORT,
2090 2),
2091 ATOM_DEVICE_TV1_SUPPORT);
2092 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2093 DRM_MODE_CONNECTOR_SVIDEO,
2094 &ddc_i2c,
2095 CONNECTOR_OBJECT_ID_SVIDEO,
2096 &hpd);
9fad321a 2097 break;
6a556039
AD		 2098 case CT_SAM440EP:
2099 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2100 rdev->mode_info.connector_table);
2101 /* LVDS */
2102 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2103 hpd.hpd = RADEON_HPD_NONE;
2104 radeon_add_legacy_encoder(dev,
2105 radeon_get_encoder_enum(dev,
2106 ATOM_DEVICE_LCD1_SUPPORT,
2107 0),
2108 ATOM_DEVICE_LCD1_SUPPORT);
2109 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2110 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2111 CONNECTOR_OBJECT_ID_LVDS,
2112 &hpd);
2113 /* DVI-I - secondary dac, int tmds */
2114 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2115 hpd.hpd = RADEON_HPD_1; /* ??? */
2116 radeon_add_legacy_encoder(dev,
2117 radeon_get_encoder_enum(dev,
2118 ATOM_DEVICE_DFP1_SUPPORT,
2119 0),
2120 ATOM_DEVICE_DFP1_SUPPORT);
2121 radeon_add_legacy_encoder(dev,
2122 radeon_get_encoder_enum(dev,
2123 ATOM_DEVICE_CRT2_SUPPORT,
2124 2),
2125 ATOM_DEVICE_CRT2_SUPPORT);
2126 radeon_add_legacy_connector(dev, 1,
2127 ATOM_DEVICE_DFP1_SUPPORT |
2128 ATOM_DEVICE_CRT2_SUPPORT,
2129 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2130 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2131 &hpd);
2132 /* VGA - primary dac */
2133 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2134 hpd.hpd = RADEON_HPD_NONE;
2135 radeon_add_legacy_encoder(dev,
2136 radeon_get_encoder_enum(dev,
2137 ATOM_DEVICE_CRT1_SUPPORT,
2138 1),
2139 ATOM_DEVICE_CRT1_SUPPORT);
2140 radeon_add_legacy_connector(dev, 2,
2141 ATOM_DEVICE_CRT1_SUPPORT,
2142 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2143 CONNECTOR_OBJECT_ID_VGA,
2144 &hpd);
2145 /* TV - TV DAC */
2146 ddc_i2c.valid = false;
2147 hpd.hpd = RADEON_HPD_NONE;
2148 radeon_add_legacy_encoder(dev,
2149 radeon_get_encoder_enum(dev,
2150 ATOM_DEVICE_TV1_SUPPORT,
2151 2),
2152 ATOM_DEVICE_TV1_SUPPORT);
2153 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2154 DRM_MODE_CONNECTOR_SVIDEO,
2155 &ddc_i2c,
2156 CONNECTOR_OBJECT_ID_SVIDEO,
2157 &hpd);
2158 break;
cafa59b9
AD		 2159 case CT_MAC_G4_SILVER:
2160 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2161 rdev->mode_info.connector_table);
2162 /* DVI-I - tv dac, int tmds */
2163 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2164 hpd.hpd = RADEON_HPD_1; /* ??? */
2165 radeon_add_legacy_encoder(dev,
2166 radeon_get_encoder_enum(dev,
2167 ATOM_DEVICE_DFP1_SUPPORT,
2168 0),
2169 ATOM_DEVICE_DFP1_SUPPORT);
2170 radeon_add_legacy_encoder(dev,
2171 radeon_get_encoder_enum(dev,
2172 ATOM_DEVICE_CRT2_SUPPORT,
2173 2),
2174 ATOM_DEVICE_CRT2_SUPPORT);
2175 radeon_add_legacy_connector(dev, 0,
2176 ATOM_DEVICE_DFP1_SUPPORT |
2177 ATOM_DEVICE_CRT2_SUPPORT,
2178 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2179 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2180 &hpd);
2181 /* VGA - primary dac */
2182 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2183 hpd.hpd = RADEON_HPD_NONE;
2184 radeon_add_legacy_encoder(dev,
2185 radeon_get_encoder_enum(dev,
2186 ATOM_DEVICE_CRT1_SUPPORT,
2187 1),
2188 ATOM_DEVICE_CRT1_SUPPORT);
2189 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2190 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2191 CONNECTOR_OBJECT_ID_VGA,
2192 &hpd);
2193 /* TV - TV DAC */
2194 ddc_i2c.valid = false;
2195 hpd.hpd = RADEON_HPD_NONE;
2196 radeon_add_legacy_encoder(dev,
2197 radeon_get_encoder_enum(dev,
2198 ATOM_DEVICE_TV1_SUPPORT,
2199 2),
2200 ATOM_DEVICE_TV1_SUPPORT);
2201 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2202 DRM_MODE_CONNECTOR_SVIDEO,
2203 &ddc_i2c,
2204 CONNECTOR_OBJECT_ID_SVIDEO,
2205 &hpd);
2206 break;
771fe6b9
JG		 2207 default:
2208 DRM_INFO("Connector table: %d (invalid)\n",
2209 rdev->mode_info.connector_table);
2210 return false;
2211 }
2212
2213 radeon_link_encoder_connector(dev);
2214
2215 return true;
2216}
2217
2218static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2219 int bios_index,
2220 enum radeon_combios_connector
2221 *legacy_connector,
eed45b30
AD		 2222 struct radeon_i2c_bus_rec *ddc_i2c,
2223 struct radeon_hpd *hpd)
771fe6b9 2224{
d86a4126 2225 struct radeon_device *rdev = dev->dev_private;
fcec570b 2226
771fe6b9
JG		 2227 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2228 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
d86a4126
TZ		 2229 if (rdev->pdev->device == 0x515e &&
2230 rdev->pdev->subsystem_vendor == 0x1014) {
771fe6b9
JG		 2231 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2232 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2233 return false;
2234 }
2235
771fe6b9 2236 /* X300 card with extra non-existent DVI port */
d86a4126
TZ		 2237 if (rdev->pdev->device == 0x5B60 &&
2238 rdev->pdev->subsystem_vendor == 0x17af &&
2239 rdev->pdev->subsystem_device == 0x201e && bios_index == 2) {
771fe6b9
JG		 2240 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2241 return false;
2242 }
2243
2244 return true;
2245}
2246
790cfb34
AD		 2247static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2248{
d86a4126
TZ		 2249 struct radeon_device *rdev = dev->dev_private;
2250
790cfb34 2251 /* Acer 5102 has non-existent TV port */
d86a4126
TZ		 2252 if (rdev->pdev->device == 0x5975 &&
2253 rdev->pdev->subsystem_vendor == 0x1025 &&
2254 rdev->pdev->subsystem_device == 0x009f)
790cfb34
AD		 2255 return false;
2256
fc7f7119 2257 /* HP dc5750 has non-existent TV port */
d86a4126
TZ		 2258 if (rdev->pdev->device == 0x5974 &&
2259 rdev->pdev->subsystem_vendor == 0x103c &&
2260 rdev->pdev->subsystem_device == 0x280a)
fc7f7119
AD		 2261 return false;
2262
fd874ad0 2263 /* MSI S270 has non-existent TV port */
d86a4126
TZ		 2264 if (rdev->pdev->device == 0x5955 &&
2265 rdev->pdev->subsystem_vendor == 0x1462 &&
2266 rdev->pdev->subsystem_device == 0x0131)
fd874ad0
AD		 2267 return false;
2268
790cfb34
AD		 2269 return true;
2270}
2271
b75fad06
AD		 2272static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2273{
2274 struct radeon_device *rdev = dev->dev_private;
2275 uint32_t ext_tmds_info;
2276
2277 if (rdev->flags & RADEON_IS_IGP) {
2278 if (is_dvi_d)
2279 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2280 else
2281 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2282 }
2283 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2284 if (ext_tmds_info) {
2285 uint8_t rev = RBIOS8(ext_tmds_info);
2286 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2287 if (rev >= 3) {
2288 if (is_dvi_d)
2289 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2290 else
2291 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2292 } else {
2293 if (flags & 1) {
2294 if (is_dvi_d)
2295 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2296 else
2297 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2298 }
2299 }
2300 }
2301 if (is_dvi_d)
2302 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2303 else
2304 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2305}
2306
771fe6b9
JG		 2307bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2308{
2309 struct radeon_device *rdev = dev->dev_private;
2310 uint32_t conn_info, entry, devices;
b75fad06 2311 uint16_t tmp, connector_object_id;
771fe6b9
JG		 2312 enum radeon_combios_ddc ddc_type;
2313 enum radeon_combios_connector connector;
2314 int i = 0;
2315 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 2316 struct radeon_hpd hpd;
771fe6b9 2317
771fe6b9
JG		 2318 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2319 if (conn_info) {
2320 for (i = 0; i < 4; i++) {
2321 entry = conn_info + 2 + i * 2;
2322
2323 if (!RBIOS16(entry))
2324 break;
2325
2326 tmp = RBIOS16(entry);
2327
2328 connector = (tmp >> 12) & 0xf;
2329
2330 ddc_type = (tmp >> 8) & 0xf;
3d61bd42
AD		 2331 if (ddc_type == 5)
2332 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2333 else
2334 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
771fe6b9 2335
eed45b30
AD		 2336 switch (connector) {
2337 case CONNECTOR_PROPRIETARY_LEGACY:
2338 case CONNECTOR_DVI_I_LEGACY:
2339 case CONNECTOR_DVI_D_LEGACY:
2340 if ((tmp >> 4) & 0x1)
2341 hpd.hpd = RADEON_HPD_2;
2342 else
2343 hpd.hpd = RADEON_HPD_1;
2344 break;
2345 default:
2346 hpd.hpd = RADEON_HPD_NONE;
2347 break;
2348 }
2349
2d152c6b 2350 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 2351 &ddc_i2c, &hpd))
2d152c6b 2352 continue;
771fe6b9
JG		 2353
2354 switch (connector) {
2355 case CONNECTOR_PROPRIETARY_LEGACY:
2356 if ((tmp >> 4) & 0x1)
2357 devices = ATOM_DEVICE_DFP2_SUPPORT;
2358 else
2359 devices = ATOM_DEVICE_DFP1_SUPPORT;
2360 radeon_add_legacy_encoder(dev,
5137ee94 2361 radeon_get_encoder_enum
771fe6b9
JG		 2362 (dev, devices, 0),
2363 devices);
2364 radeon_add_legacy_connector(dev, i, devices,
2365 legacy_connector_convert
2366 [connector],
b75fad06 2367 &ddc_i2c,
eed45b30
AD		 2368 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2369 &hpd);
771fe6b9
JG		 2370 break;
2371 case CONNECTOR_CRT_LEGACY:
2372 if (tmp & 0x1) {
2373 devices = ATOM_DEVICE_CRT2_SUPPORT;
2374 radeon_add_legacy_encoder(dev,
5137ee94 2375 radeon_get_encoder_enum
771fe6b9
JG		 2376 (dev,
2377 ATOM_DEVICE_CRT2_SUPPORT,
2378 2),
2379 ATOM_DEVICE_CRT2_SUPPORT);
2380 } else {
2381 devices = ATOM_DEVICE_CRT1_SUPPORT;
2382 radeon_add_legacy_encoder(dev,
5137ee94 2383 radeon_get_encoder_enum
771fe6b9
JG		 2384 (dev,
2385 ATOM_DEVICE_CRT1_SUPPORT,
2386 1),
2387 ATOM_DEVICE_CRT1_SUPPORT);
2388 }
2389 radeon_add_legacy_connector(dev,
2390 i,
2391 devices,
2392 legacy_connector_convert
2393 [connector],
b75fad06 2394 &ddc_i2c,
eed45b30
AD		 2395 CONNECTOR_OBJECT_ID_VGA,
2396 &hpd);
771fe6b9
JG		 2397 break;
2398 case CONNECTOR_DVI_I_LEGACY:
2399 devices = 0;
2400 if (tmp & 0x1) {
2401 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2402 radeon_add_legacy_encoder(dev,
5137ee94 2403 radeon_get_encoder_enum
771fe6b9
JG		 2404 (dev,
2405 ATOM_DEVICE_CRT2_SUPPORT,
2406 2),
2407 ATOM_DEVICE_CRT2_SUPPORT);
2408 } else {
2409 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2410 radeon_add_legacy_encoder(dev,
5137ee94 2411 radeon_get_encoder_enum
771fe6b9
JG		 2412 (dev,
2413 ATOM_DEVICE_CRT1_SUPPORT,
2414 1),
2415 ATOM_DEVICE_CRT1_SUPPORT);
2416 }
9200ee49
AD		 2417 /* RV100 board with external TDMS bit mis-set.
2418 * Actually uses internal TMDS, clear the bit.
2419 */
d86a4126
TZ		 2420 if (rdev->pdev->device == 0x5159 &&
2421 rdev->pdev->subsystem_vendor == 0x1014 &&
2422 rdev->pdev->subsystem_device == 0x029A) {
9200ee49
AD		 2423 tmp &= ~(1 << 4);
2424 }
771fe6b9
JG		 2425 if ((tmp >> 4) & 0x1) {
2426 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2427 radeon_add_legacy_encoder(dev,
5137ee94 2428 radeon_get_encoder_enum
771fe6b9
JG		 2429 (dev,
2430 ATOM_DEVICE_DFP2_SUPPORT,
2431 0),
2432 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2433 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2434 } else {
2435 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2436 radeon_add_legacy_encoder(dev,
5137ee94 2437 radeon_get_encoder_enum
771fe6b9
JG		 2438 (dev,
2439 ATOM_DEVICE_DFP1_SUPPORT,
2440 0),
2441 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2442 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2443 }
2444 radeon_add_legacy_connector(dev,
2445 i,
2446 devices,
2447 legacy_connector_convert
2448 [connector],
b75fad06 2449 &ddc_i2c,
eed45b30
AD		 2450 connector_object_id,
2451 &hpd);
771fe6b9
JG		 2452 break;
2453 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2454 if ((tmp >> 4) & 0x1) {
771fe6b9 2455 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2456 connector_object_id = combios_check_dl_dvi(dev, 1);
2457 } else {
771fe6b9 2458 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2459 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2460 }
771fe6b9 2461 radeon_add_legacy_encoder(dev,
5137ee94 2462 radeon_get_encoder_enum
771fe6b9
JG		 2463 (dev, devices, 0),
2464 devices);
2465 radeon_add_legacy_connector(dev, i, devices,
2466 legacy_connector_convert
2467 [connector],
b75fad06 2468 &ddc_i2c,
eed45b30
AD		 2469 connector_object_id,
2470 &hpd);
771fe6b9
JG		 2471 break;
2472 case CONNECTOR_CTV_LEGACY:
2473 case CONNECTOR_STV_LEGACY:
2474 radeon_add_legacy_encoder(dev,
5137ee94 2475 radeon_get_encoder_enum
771fe6b9
JG		 2476 (dev,
2477 ATOM_DEVICE_TV1_SUPPORT,
2478 2),
2479 ATOM_DEVICE_TV1_SUPPORT);
2480 radeon_add_legacy_connector(dev, i,
2481 ATOM_DEVICE_TV1_SUPPORT,
2482 legacy_connector_convert
2483 [connector],
b75fad06 2484 &ddc_i2c,
eed45b30
AD		 2485 CONNECTOR_OBJECT_ID_SVIDEO,
2486 &hpd);
771fe6b9
JG		 2487 break;
2488 default:
2489 DRM_ERROR("Unknown connector type: %d\n",
2490 connector);
2491 continue;
2492 }
2493
2494 }
2495 } else {
2496 uint16_t tmds_info =
2497 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2498 if (tmds_info) {
d9fdaafb 2499 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
771fe6b9
JG		 2500
2501 radeon_add_legacy_encoder(dev,
5137ee94 2502 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2503 ATOM_DEVICE_CRT1_SUPPORT,
2504 1),
2505 ATOM_DEVICE_CRT1_SUPPORT);
2506 radeon_add_legacy_encoder(dev,
5137ee94 2507 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2508 ATOM_DEVICE_DFP1_SUPPORT,
2509 0),
2510 ATOM_DEVICE_DFP1_SUPPORT);
2511
179e8078 2512 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
8e36ed00 2513 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 2514 radeon_add_legacy_connector(dev,
2515 0,
2516 ATOM_DEVICE_CRT1_SUPPORT |
2517 ATOM_DEVICE_DFP1_SUPPORT,
2518 DRM_MODE_CONNECTOR_DVII,
b75fad06 2519 &ddc_i2c,
eed45b30
AD		 2520 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2521 &hpd);
771fe6b9 2522 } else {
d0c403e9
AD		 2523 uint16_t crt_info =
2524 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
d9fdaafb 2525 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
d0c403e9
AD		 2526 if (crt_info) {
2527 radeon_add_legacy_encoder(dev,
5137ee94 2528 radeon_get_encoder_enum(dev,
d0c403e9
AD		 2529 ATOM_DEVICE_CRT1_SUPPORT,
2530 1),
2531 ATOM_DEVICE_CRT1_SUPPORT);
179e8078 2532 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
eed45b30 2533 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2534 radeon_add_legacy_connector(dev,
2535 0,
2536 ATOM_DEVICE_CRT1_SUPPORT,
2537 DRM_MODE_CONNECTOR_VGA,
b75fad06 2538 &ddc_i2c,
eed45b30
AD		 2539 CONNECTOR_OBJECT_ID_VGA,
2540 &hpd);
d0c403e9 2541 } else {
d9fdaafb 2542 DRM_DEBUG_KMS("No connector info found\n");
d0c403e9
AD		 2543 return false;
2544 }
771fe6b9
JG		 2545 }
2546 }
2547
2548 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2549 uint16_t lcd_info =
2550 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2551 if (lcd_info) {
2552 uint16_t lcd_ddc_info =
2553 combios_get_table_offset(dev,
2554 COMBIOS_LCD_DDC_INFO_TABLE);
2555
2556 radeon_add_legacy_encoder(dev,
5137ee94 2557 radeon_get_encoder_enum(dev,
771fe6b9
JG		 2558 ATOM_DEVICE_LCD1_SUPPORT,
2559 0),
2560 ATOM_DEVICE_LCD1_SUPPORT);
2561
2562 if (lcd_ddc_info) {
2563 ddc_type = RBIOS8(lcd_ddc_info + 2);
2564 switch (ddc_type) {
771fe6b9
JG		 2565 case DDC_LCD:
2566 ddc_i2c =
179e8078
AD		 2567 combios_setup_i2c_bus(rdev,
2568 DDC_LCD,
2569 RBIOS32(lcd_ddc_info + 3),
2570 RBIOS32(lcd_ddc_info + 7));
f376b94f 2571 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
771fe6b9
JG		 2572 break;
2573 case DDC_GPIO:
2574 ddc_i2c =
179e8078
AD		 2575 combios_setup_i2c_bus(rdev,
2576 DDC_GPIO,
2577 RBIOS32(lcd_ddc_info + 3),
2578 RBIOS32(lcd_ddc_info + 7));
f376b94f 2579 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
771fe6b9
JG		 2580 break;
2581 default:
179e8078
AD		 2582 ddc_i2c =
2583 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
771fe6b9
JG		 2584 break;
2585 }
d9fdaafb 2586 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
771fe6b9
JG		 2587 } else
2588 ddc_i2c.valid = false;
2589
eed45b30 2590 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2591 radeon_add_legacy_connector(dev,
2592 5,
2593 ATOM_DEVICE_LCD1_SUPPORT,
2594 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2595 &ddc_i2c,
eed45b30
AD		 2596 CONNECTOR_OBJECT_ID_LVDS,
2597 &hpd);
771fe6b9
JG		 2598 }
2599 }
2600
2601 /* check TV table */
2602 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2603 uint32_t tv_info =
2604 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2605 if (tv_info) {
2606 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2607 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2608 hpd.hpd = RADEON_HPD_NONE;
d294ed69 2609 ddc_i2c.valid = false;
790cfb34 2610 radeon_add_legacy_encoder(dev,
5137ee94 2611 radeon_get_encoder_enum
790cfb34
AD		 2612 (dev,
2613 ATOM_DEVICE_TV1_SUPPORT,
2614 2),
2615 ATOM_DEVICE_TV1_SUPPORT);
2616 radeon_add_legacy_connector(dev, 6,
2617 ATOM_DEVICE_TV1_SUPPORT,
2618 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2619 &ddc_i2c,
eed45b30
AD		 2620 CONNECTOR_OBJECT_ID_SVIDEO,
2621 &hpd);
790cfb34 2622 }
771fe6b9
JG		 2623 }
2624 }
2625 }
2626
2627 radeon_link_encoder_connector(dev);
2628
2629 return true;
2630}
2631
63f7d982
AD		 2632static const char *thermal_controller_names[] = {
2633 "NONE",
2634 "lm63",
2635 "adm1032",
2636};
2637
56278a8e
AD		 2638void radeon_combios_get_power_modes(struct radeon_device *rdev)
2639{
2640 struct drm_device *dev = rdev->ddev;
2641 u16 offset, misc, misc2 = 0;
77441f77 2642 u8 rev, tmp;
56278a8e 2643 int state_index = 0;
c41b9ee9 2644 struct radeon_i2c_bus_rec i2c_bus;
56278a8e 2645
a48b9b4e 2646 rdev->pm.default_power_state_index = -1;
56278a8e 2647
0975b162 2648 /* allocate 2 power states */
6396bb22
KC		 2649 rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state),
2650 GFP_KERNEL);
a7c36fd8
AD		 2651 if (rdev->pm.power_state) {
2652 /* allocate 1 clock mode per state */
2653 rdev->pm.power_state[0].clock_info =
6396bb22
KC		 2654 kcalloc(1, sizeof(struct radeon_pm_clock_info),
2655 GFP_KERNEL);
a7c36fd8 2656 rdev->pm.power_state[1].clock_info =
6396bb22
KC		 2657 kcalloc(1, sizeof(struct radeon_pm_clock_info),
2658 GFP_KERNEL);
a7c36fd8
AD		 2659 if (!rdev->pm.power_state[0].clock_info ||
2660 !rdev->pm.power_state[1].clock_info)
2661 goto pm_failed;
2662 } else
2663 goto pm_failed;
0975b162 2664
63f7d982
AD		 2665 /* check for a thermal chip */
2666 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2667 if (offset) {
2668 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
63f7d982
AD		 2669
2670 rev = RBIOS8(offset);
2671
2672 if (rev == 0) {
2673 thermal_controller = RBIOS8(offset + 3);
2674 gpio = RBIOS8(offset + 4) & 0x3f;
2675 i2c_addr = RBIOS8(offset + 5);
2676 } else if (rev == 1) {
2677 thermal_controller = RBIOS8(offset + 4);
2678 gpio = RBIOS8(offset + 5) & 0x3f;
2679 i2c_addr = RBIOS8(offset + 6);
2680 } else if (rev == 2) {
2681 thermal_controller = RBIOS8(offset + 4);
2682 gpio = RBIOS8(offset + 5) & 0x3f;
2683 i2c_addr = RBIOS8(offset + 6);
2684 clk_bit = RBIOS8(offset + 0xa);
2685 data_bit = RBIOS8(offset + 0xb);
2686 }
2687 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2688 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2689 thermal_controller_names[thermal_controller],
2690 i2c_addr >> 1);
2691 if (gpio == DDC_LCD) {
2692 /* MM i2c */
2693 i2c_bus.valid = true;
2694 i2c_bus.hw_capable = true;
2695 i2c_bus.mm_i2c = true;
2696 i2c_bus.i2c_id = 0xa0;
2697 } else if (gpio == DDC_GPIO)
2698 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2699 else
2700 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2701 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2702 if (rdev->pm.i2c_bus) {
2703 struct i2c_board_info info = { };
2704 const char *name = thermal_controller_names[thermal_controller];
2705 info.addr = i2c_addr >> 1;
992b8fe1 2706 strscpy(info.type, name, sizeof(info.type));
c7ccc1b7 2707 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
63f7d982
AD		 2708 }
2709 }
c41b9ee9
AD		 2710 } else {
2711 /* boards with a thermal chip, but no overdrive table */
2712
2713 /* Asus 9600xt has an f75375 on the monid bus */
d86a4126
TZ		 2714 if ((rdev->pdev->device == 0x4152) &&
2715 (rdev->pdev->subsystem_vendor == 0x1043) &&
2716 (rdev->pdev->subsystem_device == 0xc002)) {
c41b9ee9
AD		 2717 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2718 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2719 if (rdev->pm.i2c_bus) {
2720 struct i2c_board_info info = { };
2721 const char *name = "f75375";
2722 info.addr = 0x28;
992b8fe1 2723 strscpy(info.type, name, sizeof(info.type));
c7ccc1b7 2724 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
c41b9ee9
AD		 2725 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2726 name, info.addr);
2727 }
2728 }
63f7d982
AD		 2729 }
2730
56278a8e
AD		 2731 if (rdev->flags & RADEON_IS_MOBILITY) {
2732 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2733 if (offset) {
2734 rev = RBIOS8(offset);
56278a8e
AD		 2735 /* power mode 0 tends to be the only valid one */
2736 rdev->pm.power_state[state_index].num_clock_modes = 1;
2737 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2738 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2739 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2740 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2741 goto default_mode;
0ec0e74f
AD		 2742 rdev->pm.power_state[state_index].type =
2743 POWER_STATE_TYPE_BATTERY;
56278a8e
AD		 2744 misc = RBIOS16(offset + 0x5 + 0x0);
2745 if (rev > 4)
2746 misc2 = RBIOS16(offset + 0x5 + 0xe);
79daedc9
AD		 2747 rdev->pm.power_state[state_index].misc = misc;
2748 rdev->pm.power_state[state_index].misc2 = misc2;
56278a8e
AD		 2749 if (misc & 0x4) {
2750 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2751 if (misc & 0x8)
2752 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2753 true;
2754 else
2755 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2756 false;
2757 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2758 if (rev < 6) {
2759 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2760 RBIOS16(offset + 0x5 + 0xb) * 4;
2761 tmp = RBIOS8(offset + 0x5 + 0xd);
2762 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2763 } else {
2764 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2765 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2766 if (entries && voltage_table_offset) {
2767 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2768 RBIOS16(voltage_table_offset) * 4;
2769 tmp = RBIOS8(voltage_table_offset + 0x2);
2770 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2771 } else
2772 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2773 }
2774 switch ((misc2 & 0x700) >> 8) {
2775 case 0:
2776 default:
2777 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2778 break;
2779 case 1:
2780 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2781 break;
2782 case 2:
2783 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2784 break;
2785 case 3:
2786 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2787 break;
2788 case 4:
2789 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2790 break;
2791 }
2792 } else
2793 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2794 if (rev > 6)
79daedc9 2795 rdev->pm.power_state[state_index].pcie_lanes =
56278a8e 2796 RBIOS8(offset + 0x5 + 0x10);
d7311171 2797 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
56278a8e
AD		 2798 state_index++;
2799 } else {
2800 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2801 }
2802 } else {
2803 /* XXX figure out some good default low power mode for desktop cards */
2804 }
2805
2806default_mode:
2807 /* add the default mode */
0ec0e74f
AD		 2808 rdev->pm.power_state[state_index].type =
2809 POWER_STATE_TYPE_DEFAULT;
56278a8e
AD		 2810 rdev->pm.power_state[state_index].num_clock_modes = 1;
2811 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2812 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2813 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
84d88f4c 2814 if ((state_index > 0) &&
8de016e2 2815 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
84d88f4c
AD		 2816 rdev->pm.power_state[state_index].clock_info[0].voltage =
2817 rdev->pm.power_state[0].clock_info[0].voltage;
2818 else
2819 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
79daedc9 2820 rdev->pm.power_state[state_index].pcie_lanes = 16;
a48b9b4e
AD		 2821 rdev->pm.power_state[state_index].flags = 0;
2822 rdev->pm.default_power_state_index = state_index;
56278a8e 2823 rdev->pm.num_power_states = state_index + 1;
9038dfdf 2824
a7c36fd8
AD		 2825 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2826 rdev->pm.current_clock_mode_index = 0;
2827 return;
2828
2829pm_failed:
2830 rdev->pm.default_power_state_index = state_index;
2831 rdev->pm.num_power_states = 0;
2832
a48b9b4e
AD		 2833 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2834 rdev->pm.current_clock_mode_index = 0;
56278a8e
AD		 2835}
2836
fcec570b
AD		 2837void radeon_external_tmds_setup(struct drm_encoder *encoder)
2838{
2839 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2840 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2841
2842 if (!tmds)
2843 return;
2844
2845 switch (tmds->dvo_chip) {
2846 case DVO_SIL164:
2847 /* sil 164 */
5a6f98f5
AD		 2848 radeon_i2c_put_byte(tmds->i2c_bus,
2849 tmds->slave_addr,
2850 0x08, 0x30);
2851 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2852 tmds->slave_addr,
2853 0x09, 0x00);
5a6f98f5
AD		 2854 radeon_i2c_put_byte(tmds->i2c_bus,
2855 tmds->slave_addr,
2856 0x0a, 0x90);
2857 radeon_i2c_put_byte(tmds->i2c_bus,
2858 tmds->slave_addr,
2859 0x0c, 0x89);
2860 radeon_i2c_put_byte(tmds->i2c_bus,
fcec570b
AD		 2861 tmds->slave_addr,
2862 0x08, 0x3b);
fcec570b
AD		 2863 break;
2864 case DVO_SIL1178:
2865 /* sil 1178 - untested */
2866 /*
2867 * 0x0f, 0x44
2868 * 0x0f, 0x4c
2869 * 0x0e, 0x01
2870 * 0x0a, 0x80
2871 * 0x09, 0x30
2872 * 0x0c, 0xc9
2873 * 0x0d, 0x70
2874 * 0x08, 0x32
2875 * 0x08, 0x33
2876 */
2877 break;
2878 default:
2879 break;
2880 }
2881
2882}
2883
2884bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2885{
2886 struct drm_device *dev = encoder->dev;
2887 struct radeon_device *rdev = dev->dev_private;
2888 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2889 uint16_t offset;
2890 uint8_t blocks, slave_addr, rev;
2891 uint32_t index, id;
2892 uint32_t reg, val, and_mask, or_mask;
2893 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2894
fcec570b
AD		 2895 if (!tmds)
2896 return false;
2897
2898 if (rdev->flags & RADEON_IS_IGP) {
2899 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2900 rev = RBIOS8(offset);
2901 if (offset) {
2902 rev = RBIOS8(offset);
2903 if (rev > 1) {
2904 blocks = RBIOS8(offset + 3);
2905 index = offset + 4;
2906 while (blocks > 0) {
2907 id = RBIOS16(index);
2908 index += 2;
2909 switch (id >> 13) {
2910 case 0:
2911 reg = (id & 0x1fff) * 4;
2912 val = RBIOS32(index);
2913 index += 4;
2914 WREG32(reg, val);
2915 break;
2916 case 2:
2917 reg = (id & 0x1fff) * 4;
2918 and_mask = RBIOS32(index);
2919 index += 4;
2920 or_mask = RBIOS32(index);
2921 index += 4;
2922 val = RREG32(reg);
2923 val = (val & and_mask) | or_mask;
2924 WREG32(reg, val);
2925 break;
2926 case 3:
2927 val = RBIOS16(index);
2928 index += 2;
2929 udelay(val);
2930 break;
2931 case 4:
2932 val = RBIOS16(index);
2933 index += 2;
4de833c3 2934 mdelay(val);
fcec570b
AD		 2935 break;
2936 case 6:
2937 slave_addr = id & 0xff;
2938 slave_addr >>= 1; /* 7 bit addressing */
2939 index++;
2940 reg = RBIOS8(index);
2941 index++;
2942 val = RBIOS8(index);
2943 index++;
5a6f98f5
AD		 2944 radeon_i2c_put_byte(tmds->i2c_bus,
2945 slave_addr,
2946 reg, val);
fcec570b
AD		 2947 break;
2948 default:
2949 DRM_ERROR("Unknown id %d\n", id >> 13);
2950 break;
2951 }
2952 blocks--;
2953 }
2954 return true;
2955 }
2956 }
2957 } else {
2958 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2959 if (offset) {
2960 index = offset + 10;
2961 id = RBIOS16(index);
2962 while (id != 0xffff) {
2963 index += 2;
2964 switch (id >> 13) {
2965 case 0:
2966 reg = (id & 0x1fff) * 4;
2967 val = RBIOS32(index);
2968 WREG32(reg, val);
2969 break;
2970 case 2:
2971 reg = (id & 0x1fff) * 4;
2972 and_mask = RBIOS32(index);
2973 index += 4;
2974 or_mask = RBIOS32(index);
2975 index += 4;
2976 val = RREG32(reg);
2977 val = (val & and_mask) | or_mask;
2978 WREG32(reg, val);
2979 break;
2980 case 4:
2981 val = RBIOS16(index);
2982 index += 2;
2983 udelay(val);
2984 break;
2985 case 5:
2986 reg = id & 0x1fff;
2987 and_mask = RBIOS32(index);
2988 index += 4;
2989 or_mask = RBIOS32(index);
2990 index += 4;
2991 val = RREG32_PLL(reg);
2992 val = (val & and_mask) | or_mask;
2993 WREG32_PLL(reg, val);
2994 break;
2995 case 6:
2996 reg = id & 0x1fff;
2997 val = RBIOS8(index);
2998 index += 1;
5a6f98f5
AD		 2999 radeon_i2c_put_byte(tmds->i2c_bus,
3000 tmds->slave_addr,
3001 reg, val);
fcec570b
AD		 3002 break;
3003 default:
3004 DRM_ERROR("Unknown id %d\n", id >> 13);
3005 break;
3006 }
3007 id = RBIOS16(index);
3008 }
3009 return true;
3010 }
3011 }
3012 return false;
3013}
3014
771fe6b9
JG		 3015static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3016{
3017 struct radeon_device *rdev = dev->dev_private;
3018
3019 if (offset) {
3020 while (RBIOS16(offset)) {
3021 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3022 uint32_t addr = (RBIOS16(offset) & 0x1fff);
3023 uint32_t val, and_mask, or_mask;
3024 uint32_t tmp;
3025
3026 offset += 2;
3027 switch (cmd) {
3028 case 0:
3029 val = RBIOS32(offset);
3030 offset += 4;
3031 WREG32(addr, val);
3032 break;
3033 case 1:
3034 val = RBIOS32(offset);
3035 offset += 4;
3036 WREG32(addr, val);
3037 break;
3038 case 2:
3039 and_mask = RBIOS32(offset);
3040 offset += 4;
3041 or_mask = RBIOS32(offset);
3042 offset += 4;
3043 tmp = RREG32(addr);
3044 tmp &= and_mask;
3045 tmp |= or_mask;
3046 WREG32(addr, tmp);
3047 break;
3048 case 3:
3049 and_mask = RBIOS32(offset);
3050 offset += 4;
3051 or_mask = RBIOS32(offset);
3052 offset += 4;
3053 tmp = RREG32(addr);
3054 tmp &= and_mask;
3055 tmp |= or_mask;
3056 WREG32(addr, tmp);
3057 break;
3058 case 4:
3059 val = RBIOS16(offset);
3060 offset += 2;
3061 udelay(val);
3062 break;
3063 case 5:
3064 val = RBIOS16(offset);
3065 offset += 2;
3066 switch (addr) {
3067 case 8:
3068 while (val--) {
3069 if (!
3070 (RREG32_PLL
3071 (RADEON_CLK_PWRMGT_CNTL) &
3072 RADEON_MC_BUSY))
3073 break;
3074 }
3075 break;
3076 case 9:
3077 while (val--) {
3078 if ((RREG32(RADEON_MC_STATUS) &
3079 RADEON_MC_IDLE))
3080 break;
3081 }
3082 break;
3083 default:
3084 break;
3085 }
3086 break;
3087 default:
3088 break;
3089 }
3090 }
3091 }
3092}
3093
3094static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3095{
3096 struct radeon_device *rdev = dev->dev_private;
3097
3098 if (offset) {
3099 while (RBIOS8(offset)) {
3100 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3101 uint8_t addr = (RBIOS8(offset) & 0x3f);
3102 uint32_t val, shift, tmp;
3103 uint32_t and_mask, or_mask;
3104
3105 offset++;
3106 switch (cmd) {
3107 case 0:
3108 val = RBIOS32(offset);
3109 offset += 4;
3110 WREG32_PLL(addr, val);
3111 break;
3112 case 1:
3113 shift = RBIOS8(offset) * 8;
3114 offset++;
3115 and_mask = RBIOS8(offset) << shift;
3116 and_mask |= ~(0xff << shift);
3117 offset++;
3118 or_mask = RBIOS8(offset) << shift;
3119 offset++;
3120 tmp = RREG32_PLL(addr);
3121 tmp &= and_mask;
3122 tmp |= or_mask;
3123 WREG32_PLL(addr, tmp);
3124 break;
3125 case 2:
3126 case 3:
3127 tmp = 1000;
3128 switch (addr) {
3129 case 1:
3130 udelay(150);
3131 break;
3132 case 2:
4de833c3 3133 mdelay(1);
771fe6b9
JG		 3134 break;
3135 case 3:
3136 while (tmp--) {
3137 if (!
3138 (RREG32_PLL
3139 (RADEON_CLK_PWRMGT_CNTL) &
3140 RADEON_MC_BUSY))
3141 break;
3142 }
3143 break;
3144 case 4:
3145 while (tmp--) {
3146 if (RREG32_PLL
3147 (RADEON_CLK_PWRMGT_CNTL) &
3148 RADEON_DLL_READY)
3149 break;
3150 }
3151 break;
3152 case 5:
3153 tmp =
3154 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3155 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3156#if 0
3157 uint32_t mclk_cntl =
3158 RREG32_PLL
3159 (RADEON_MCLK_CNTL);
3160 mclk_cntl &= 0xffff0000;
3161 /*mclk_cntl |= 0x00001111;*//* ??? */
3162 WREG32_PLL(RADEON_MCLK_CNTL,
3163 mclk_cntl);
4de833c3 3164 mdelay(10);
771fe6b9
JG		 3165#endif
3166 WREG32_PLL
3167 (RADEON_CLK_PWRMGT_CNTL,
3168 tmp &
3169 ~RADEON_CG_NO1_DEBUG_0);
4de833c3 3170 mdelay(10);
771fe6b9
JG		 3171 }
3172 break;
3173 default:
3174 break;
3175 }
3176 break;
3177 default:
3178 break;
3179 }
3180 }
3181 }
3182}
3183
3184static void combios_parse_ram_reset_table(struct drm_device *dev,
3185 uint16_t offset)
3186{
3187 struct radeon_device *rdev = dev->dev_private;
3188 uint32_t tmp;
3189
3190 if (offset) {
3191 uint8_t val = RBIOS8(offset);
3192 while (val != 0xff) {
3193 offset++;
3194
3195 if (val == 0x0f) {
3196 uint32_t channel_complete_mask;
3197
3198 if (ASIC_IS_R300(rdev))
3199 channel_complete_mask =
3200 R300_MEM_PWRUP_COMPLETE;
3201 else
3202 channel_complete_mask =
3203 RADEON_MEM_PWRUP_COMPLETE;
3204 tmp = 20000;
3205 while (tmp--) {
3206 if ((RREG32(RADEON_MEM_STR_CNTL) &
3207 channel_complete_mask) ==
3208 channel_complete_mask)
3209 break;
3210 }
3211 } else {
3212 uint32_t or_mask = RBIOS16(offset);
3213 offset += 2;
3214
3215 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3216 tmp &= RADEON_SDRAM_MODE_MASK;
3217 tmp |= or_mask;
3218 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3219
3220 or_mask = val << 24;
3221 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3222 tmp &= RADEON_B3MEM_RESET_MASK;
3223 tmp |= or_mask;
3224 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3225 }
3226 val = RBIOS8(offset);
3227 }
3228 }
3229}
3230
3231static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3232 int mem_addr_mapping)
3233{
3234 struct radeon_device *rdev = dev->dev_private;
3235 uint32_t mem_cntl;
3236 uint32_t mem_size;
3237 uint32_t addr = 0;
3238
3239 mem_cntl = RREG32(RADEON_MEM_CNTL);
3240 if (mem_cntl & RV100_HALF_MODE)
3241 ram /= 2;
3242 mem_size = ram;
3243 mem_cntl &= ~(0xff << 8);
3244 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3245 WREG32(RADEON_MEM_CNTL, mem_cntl);
3246 RREG32(RADEON_MEM_CNTL);
3247
3248 /* sdram reset ? */
3249
3250 /* something like this???? */
3251 while (ram--) {
3252 addr = ram * 1024 * 1024;
3253 /* write to each page */
2ef9bdfe 3254 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
771fe6b9 3255 /* read back and verify */
2ef9bdfe 3256 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
771fe6b9
JG		 3257 return 0;
3258 }
3259
3260 return mem_size;
3261}
3262
3263static void combios_write_ram_size(struct drm_device *dev)
3264{
3265 struct radeon_device *rdev = dev->dev_private;
3266 uint8_t rev;
3267 uint16_t offset;
3268 uint32_t mem_size = 0;
3269 uint32_t mem_cntl = 0;
3270
3271 /* should do something smarter here I guess... */
3272 if (rdev->flags & RADEON_IS_IGP)
3273 return;
3274
3275 /* first check detected mem table */
3276 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3277 if (offset) {
3278 rev = RBIOS8(offset);
3279 if (rev < 3) {
3280 mem_cntl = RBIOS32(offset + 1);
3281 mem_size = RBIOS16(offset + 5);
4ce9198e
AD		 3282 if ((rdev->family < CHIP_R200) &&
3283 !ASIC_IS_RN50(rdev))
771fe6b9
JG		 3284 WREG32(RADEON_MEM_CNTL, mem_cntl);
3285 }
3286 }
3287
3288 if (!mem_size) {
3289 offset =
3290 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3291 if (offset) {
3292 rev = RBIOS8(offset - 1);
3293 if (rev < 1) {
4ce9198e
AD		 3294 if ((rdev->family < CHIP_R200)
3295 && !ASIC_IS_RN50(rdev)) {
771fe6b9
JG		 3296 int ram = 0;
3297 int mem_addr_mapping = 0;
3298
3299 while (RBIOS8(offset)) {
3300 ram = RBIOS8(offset);
3301 mem_addr_mapping =
3302 RBIOS8(offset + 1);
3303 if (mem_addr_mapping != 0x25)
3304 ram *= 2;
3305 mem_size =
3306 combios_detect_ram(dev, ram,
3307 mem_addr_mapping);
3308 if (mem_size)
3309 break;
3310 offset += 2;
3311 }
3312 } else
3313 mem_size = RBIOS8(offset);
3314 } else {
3315 mem_size = RBIOS8(offset);
3316 mem_size *= 2; /* convert to MB */
3317 }
3318 }
3319 }
3320
3321 mem_size *= (1024 * 1024); /* convert to bytes */
3322 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3323}
3324
771fe6b9
JG		 3325void radeon_combios_asic_init(struct drm_device *dev)
3326{
3327 struct radeon_device *rdev = dev->dev_private;
3328 uint16_t table;
3329
3330 /* port hardcoded mac stuff from radeonfb */
3331 if (rdev->bios == NULL)
3332 return;
3333
3334 /* ASIC INIT 1 */
3335 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3336 if (table)
3337 combios_parse_mmio_table(dev, table);
3338
3339 /* PLL INIT */
3340 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3341 if (table)
3342 combios_parse_pll_table(dev, table);
3343
3344 /* ASIC INIT 2 */
3345 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3346 if (table)
3347 combios_parse_mmio_table(dev, table);
3348
3349 if (!(rdev->flags & RADEON_IS_IGP)) {
3350 /* ASIC INIT 4 */
3351 table =
3352 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3353 if (table)
3354 combios_parse_mmio_table(dev, table);
3355
3356 /* RAM RESET */
3357 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3358 if (table)
3359 combios_parse_ram_reset_table(dev, table);
3360
3361 /* ASIC INIT 3 */
3362 table =
3363 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3364 if (table)
3365 combios_parse_mmio_table(dev, table);
3366
3367 /* write CONFIG_MEMSIZE */
3368 combios_write_ram_size(dev);
3369 }
3370
580b4fff
DA		 3371 /* quirk for rs4xx HP nx6125 laptop to make it resume
3372 * - it hangs on resume inside the dynclk 1 table.
3373 */
3374 if (rdev->family == CHIP_RS480 &&
3375 rdev->pdev->subsystem_vendor == 0x103c &&
3376 rdev->pdev->subsystem_device == 0x308b)
3377 return;
3378
52fa2bbc
AD		 3379 /* quirk for rs4xx HP dv5000 laptop to make it resume
3380 * - it hangs on resume inside the dynclk 1 table.
3381 */
3382 if (rdev->family == CHIP_RS480 &&
3383 rdev->pdev->subsystem_vendor == 0x103c &&
3384 rdev->pdev->subsystem_device == 0x30a4)
3385 return;
3386
302a8e8b
AD		 3387 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3388 * - it hangs on resume inside the dynclk 1 table.
3389 */
3390 if (rdev->family == CHIP_RS480 &&
3391 rdev->pdev->subsystem_vendor == 0x103c &&
3392 rdev->pdev->subsystem_device == 0x30ae)
3393 return;
3394
09bfda10
JM		 3395 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
3396 * - it hangs on resume inside the dynclk 1 table.
3397 */
3398 if (rdev->family == CHIP_RS480 &&
3399 rdev->pdev->subsystem_vendor == 0x103c &&
3400 rdev->pdev->subsystem_device == 0x280a)
3401 return;
acfd6ee4
AD		 3402 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume
3403 * - it hangs on resume inside the dynclk 1 table.
3404 */
3405 if (rdev->family == CHIP_RS400 &&
3406 rdev->pdev->subsystem_vendor == 0x1179 &&
3407 rdev->pdev->subsystem_device == 0xff31)
3408 return;
09bfda10 3409
771fe6b9
JG		 3410 /* DYN CLK 1 */
3411 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3412 if (table)
3413 combios_parse_pll_table(dev, table);
3414
3415}
3416
3417void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3418{
3419 struct radeon_device *rdev = dev->dev_private;
3420 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3421
3422 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3423 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3424 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3425
3426 /* let the bios control the backlight */
3427 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3428
3429 /* tell the bios not to handle mode switching */
3430 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3431 RADEON_ACC_MODE_CHANGE);
3432
3433 /* tell the bios a driver is loaded */
3434 bios_7_scratch |= RADEON_DRV_LOADED;
3435
3436 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3437 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3438 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3439}
3440
3441void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3442{
3443 struct drm_device *dev = encoder->dev;
3444 struct radeon_device *rdev = dev->dev_private;
3445 uint32_t bios_6_scratch;
3446
3447 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3448
3449 if (lock)
3450 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3451 else
3452 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3453
3454 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3455}
3456
3457void
3458radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3459 struct drm_encoder *encoder,
3460 bool connected)
3461{
3462 struct drm_device *dev = connector->dev;
3463 struct radeon_device *rdev = dev->dev_private;
3464 struct radeon_connector *radeon_connector =
3465 to_radeon_connector(connector);
3466 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3467 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3468 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3469
3470 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3471 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3472 if (connected) {
d9fdaafb 3473 DRM_DEBUG_KMS("TV1 connected\n");
771fe6b9
JG		 3474 /* fix me */
3475 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3476 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3477 bios_5_scratch |= RADEON_TV1_ON;
3478 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3479 } else {
d9fdaafb 3480 DRM_DEBUG_KMS("TV1 disconnected\n");
771fe6b9
JG		 3481 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3482 bios_5_scratch &= ~RADEON_TV1_ON;
3483 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3484 }
3485 }
3486 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3487 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3488 if (connected) {
d9fdaafb 3489 DRM_DEBUG_KMS("LCD1 connected\n");
771fe6b9
JG		 3490 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3491 bios_5_scratch |= RADEON_LCD1_ON;
3492 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3493 } else {
d9fdaafb 3494 DRM_DEBUG_KMS("LCD1 disconnected\n");
771fe6b9
JG		 3495 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3496 bios_5_scratch &= ~RADEON_LCD1_ON;
3497 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3498 }
3499 }
3500 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3501 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3502 if (connected) {
d9fdaafb 3503 DRM_DEBUG_KMS("CRT1 connected\n");
771fe6b9
JG		 3504 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3505 bios_5_scratch |= RADEON_CRT1_ON;
3506 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3507 } else {
d9fdaafb 3508 DRM_DEBUG_KMS("CRT1 disconnected\n");
771fe6b9
JG		 3509 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3510 bios_5_scratch &= ~RADEON_CRT1_ON;
3511 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3512 }
3513 }
3514 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3515 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3516 if (connected) {
d9fdaafb 3517 DRM_DEBUG_KMS("CRT2 connected\n");
771fe6b9
JG		 3518 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3519 bios_5_scratch |= RADEON_CRT2_ON;
3520 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3521 } else {
d9fdaafb 3522 DRM_DEBUG_KMS("CRT2 disconnected\n");
771fe6b9
JG		 3523 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3524 bios_5_scratch &= ~RADEON_CRT2_ON;
3525 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3526 }
3527 }
3528 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3529 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3530 if (connected) {
d9fdaafb 3531 DRM_DEBUG_KMS("DFP1 connected\n");
771fe6b9
JG		 3532 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3533 bios_5_scratch |= RADEON_DFP1_ON;
3534 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3535 } else {
d9fdaafb 3536 DRM_DEBUG_KMS("DFP1 disconnected\n");
771fe6b9
JG		 3537 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3538 bios_5_scratch &= ~RADEON_DFP1_ON;
3539 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3540 }
3541 }
3542 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3543 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3544 if (connected) {
d9fdaafb 3545 DRM_DEBUG_KMS("DFP2 connected\n");
771fe6b9
JG		 3546 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3547 bios_5_scratch |= RADEON_DFP2_ON;
3548 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3549 } else {
d9fdaafb 3550 DRM_DEBUG_KMS("DFP2 disconnected\n");
771fe6b9
JG		 3551 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3552 bios_5_scratch &= ~RADEON_DFP2_ON;
3553 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3554 }
3555 }
3556 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3557 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3558}
3559
3560void
3561radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3562{
3563 struct drm_device *dev = encoder->dev;
3564 struct radeon_device *rdev = dev->dev_private;
3565 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3566 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3567
3568 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3569 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3570 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3571 }
3572 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3573 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3574 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3575 }
3576 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3577 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3578 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3579 }
3580 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3581 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3582 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3583 }
3584 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3585 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3586 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3587 }
3588 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3589 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3590 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3591 }
3592 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3593}
3594
3595void
3596radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3597{
3598 struct drm_device *dev = encoder->dev;
3599 struct radeon_device *rdev = dev->dev_private;
3600 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3601 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3602
3603 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3604 if (on)
3605 bios_6_scratch |= RADEON_TV_DPMS_ON;
3606 else
3607 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3608 }
3609 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3610 if (on)
3611 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3612 else
3613 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3614 }
3615 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3616 if (on)
3617 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3618 else
3619 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3620 }
3621 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3622 if (on)
3623 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3624 else
3625 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3626 }
3627 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3628}
Linux 6.x block layer and io_uring tree(s)