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drm/radeon/kms: Use surfaces for scanout / cursor byte swapping on big endian.
[linux-block.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
52 struct radeon_i2c_bus_rec *i2c_bus);
53
54/* from radeon_legacy_encoder.c */
55extern void
56radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
57 uint32_t supported_device);
58
59/* old legacy ATI BIOS routines */
60
61/* COMBIOS table offsets */
62enum radeon_combios_table_offset {
63 /* absolute offset tables */
64 COMBIOS_ASIC_INIT_1_TABLE,
65 COMBIOS_BIOS_SUPPORT_TABLE,
66 COMBIOS_DAC_PROGRAMMING_TABLE,
67 COMBIOS_MAX_COLOR_DEPTH_TABLE,
68 COMBIOS_CRTC_INFO_TABLE,
69 COMBIOS_PLL_INFO_TABLE,
70 COMBIOS_TV_INFO_TABLE,
71 COMBIOS_DFP_INFO_TABLE,
72 COMBIOS_HW_CONFIG_INFO_TABLE,
73 COMBIOS_MULTIMEDIA_INFO_TABLE,
74 COMBIOS_TV_STD_PATCH_TABLE,
75 COMBIOS_LCD_INFO_TABLE,
76 COMBIOS_MOBILE_INFO_TABLE,
77 COMBIOS_PLL_INIT_TABLE,
78 COMBIOS_MEM_CONFIG_TABLE,
79 COMBIOS_SAVE_MASK_TABLE,
80 COMBIOS_HARDCODED_EDID_TABLE,
81 COMBIOS_ASIC_INIT_2_TABLE,
82 COMBIOS_CONNECTOR_INFO_TABLE,
83 COMBIOS_DYN_CLK_1_TABLE,
84 COMBIOS_RESERVED_MEM_TABLE,
85 COMBIOS_EXT_TMDS_INFO_TABLE,
86 COMBIOS_MEM_CLK_INFO_TABLE,
87 COMBIOS_EXT_DAC_INFO_TABLE,
88 COMBIOS_MISC_INFO_TABLE,
89 COMBIOS_CRT_INFO_TABLE,
90 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
91 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
92 COMBIOS_FAN_SPEED_INFO_TABLE,
93 COMBIOS_OVERDRIVE_INFO_TABLE,
94 COMBIOS_OEM_INFO_TABLE,
95 COMBIOS_DYN_CLK_2_TABLE,
96 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
97 COMBIOS_I2C_INFO_TABLE,
98 /* relative offset tables */
99 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
100 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
101 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
103 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
104 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
105 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
106 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
108 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
109 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
110};
111
112enum radeon_combios_ddc {
113 DDC_NONE_DETECTED,
114 DDC_MONID,
115 DDC_DVI,
116 DDC_VGA,
117 DDC_CRT2,
118 DDC_LCD,
119 DDC_GPIO,
120};
121
122enum radeon_combios_connector {
123 CONNECTOR_NONE_LEGACY,
124 CONNECTOR_PROPRIETARY_LEGACY,
125 CONNECTOR_CRT_LEGACY,
126 CONNECTOR_DVI_I_LEGACY,
127 CONNECTOR_DVI_D_LEGACY,
128 CONNECTOR_CTV_LEGACY,
129 CONNECTOR_STV_LEGACY,
130 CONNECTOR_UNSUPPORTED_LEGACY
131};
132
133const int legacy_connector_convert[] = {
134 DRM_MODE_CONNECTOR_Unknown,
135 DRM_MODE_CONNECTOR_DVID,
136 DRM_MODE_CONNECTOR_VGA,
137 DRM_MODE_CONNECTOR_DVII,
138 DRM_MODE_CONNECTOR_DVID,
139 DRM_MODE_CONNECTOR_Composite,
140 DRM_MODE_CONNECTOR_SVIDEO,
141 DRM_MODE_CONNECTOR_Unknown,
142};
143
144static uint16_t combios_get_table_offset(struct drm_device *dev,
145 enum radeon_combios_table_offset table)
146{
147 struct radeon_device *rdev = dev->dev_private;
148 int rev;
149 uint16_t offset = 0, check_offset;
150
151 switch (table) {
152 /* absolute offset tables */
153 case COMBIOS_ASIC_INIT_1_TABLE:
154 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
155 if (check_offset)
156 offset = check_offset;
157 break;
158 case COMBIOS_BIOS_SUPPORT_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_DAC_PROGRAMMING_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_CRTC_INFO_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_PLL_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_TV_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_DFP_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_HW_CONFIG_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_MULTIMEDIA_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_TV_STD_PATCH_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_LCD_INFO_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_MOBILE_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_PLL_INIT_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_MEM_CONFIG_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_SAVE_MASK_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_HARDCODED_EDID_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_ASIC_INIT_2_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_CONNECTOR_INFO_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_DYN_CLK_1_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_RESERVED_MEM_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_EXT_TMDS_INFO_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_MEM_CLK_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_EXT_DAC_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_MISC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_CRT_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_FAN_SPEED_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_OVERDRIVE_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OEM_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_DYN_CLK_2_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_I2C_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 /* relative offset tables */
324 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
325 check_offset =
326 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
327 if (check_offset) {
328 rev = RBIOS8(check_offset);
329 if (rev > 0) {
330 check_offset = RBIOS16(check_offset + 0x3);
331 if (check_offset)
332 offset = check_offset;
333 }
334 }
335 break;
336 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
337 check_offset =
338 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
339 if (check_offset) {
340 rev = RBIOS8(check_offset);
341 if (rev > 0) {
342 check_offset = RBIOS16(check_offset + 0x5);
343 if (check_offset)
344 offset = check_offset;
345 }
346 }
347 break;
348 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
349 check_offset =
350 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
351 if (check_offset) {
352 rev = RBIOS8(check_offset);
353 if (rev > 0) {
354 check_offset = RBIOS16(check_offset + 0x7);
355 if (check_offset)
356 offset = check_offset;
357 }
358 }
359 break;
360 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
361 check_offset =
362 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
363 if (check_offset) {
364 rev = RBIOS8(check_offset);
365 if (rev == 2) {
366 check_offset = RBIOS16(check_offset + 0x9);
367 if (check_offset)
368 offset = check_offset;
369 }
370 }
371 break;
372 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
373 check_offset =
374 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
375 if (check_offset) {
376 while (RBIOS8(check_offset++));
377 check_offset += 2;
378 if (check_offset)
379 offset = check_offset;
380 }
381 break;
382 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
383 check_offset =
384 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
385 if (check_offset) {
386 check_offset = RBIOS16(check_offset + 0x11);
387 if (check_offset)
388 offset = check_offset;
389 }
390 break;
391 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
392 check_offset =
393 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
394 if (check_offset) {
395 check_offset = RBIOS16(check_offset + 0x13);
396 if (check_offset)
397 offset = check_offset;
398 }
399 break;
400 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
401 check_offset =
402 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
403 if (check_offset) {
404 check_offset = RBIOS16(check_offset + 0x15);
405 if (check_offset)
406 offset = check_offset;
407 }
408 break;
409 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
410 check_offset =
411 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
412 if (check_offset) {
413 check_offset = RBIOS16(check_offset + 0x17);
414 if (check_offset)
415 offset = check_offset;
416 }
417 break;
418 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
419 check_offset =
420 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
421 if (check_offset) {
422 check_offset = RBIOS16(check_offset + 0x2);
423 if (check_offset)
424 offset = check_offset;
425 }
426 break;
427 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
428 check_offset =
429 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
430 if (check_offset) {
431 check_offset = RBIOS16(check_offset + 0x4);
432 if (check_offset)
433 offset = check_offset;
434 }
435 break;
436 default:
437 break;
438 }
439
440 return offset;
441
442}
443
444struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
445{
446 struct radeon_i2c_bus_rec i2c;
447
448 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
449 i2c.mask_data_mask = RADEON_GPIO_EN_0;
450 i2c.a_clk_mask = RADEON_GPIO_A_1;
451 i2c.a_data_mask = RADEON_GPIO_A_0;
452 i2c.put_clk_mask = RADEON_GPIO_EN_1;
453 i2c.put_data_mask = RADEON_GPIO_EN_0;
454 i2c.get_clk_mask = RADEON_GPIO_Y_1;
455 i2c.get_data_mask = RADEON_GPIO_Y_0;
456 if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
457 (ddc_line == RADEON_MDGPIO_EN_REG)) {
458 i2c.mask_clk_reg = ddc_line;
459 i2c.mask_data_reg = ddc_line;
460 i2c.a_clk_reg = ddc_line;
461 i2c.a_data_reg = ddc_line;
462 i2c.put_clk_reg = ddc_line;
463 i2c.put_data_reg = ddc_line;
464 i2c.get_clk_reg = ddc_line + 4;
465 i2c.get_data_reg = ddc_line + 4;
466 } else {
467 i2c.mask_clk_reg = ddc_line;
468 i2c.mask_data_reg = ddc_line;
469 i2c.a_clk_reg = ddc_line;
470 i2c.a_data_reg = ddc_line;
471 i2c.put_clk_reg = ddc_line;
472 i2c.put_data_reg = ddc_line;
473 i2c.get_clk_reg = ddc_line;
474 i2c.get_data_reg = ddc_line;
475 }
476
477 if (ddc_line)
478 i2c.valid = true;
479 else
480 i2c.valid = false;
481
482 return i2c;
483}
484
485bool radeon_combios_get_clock_info(struct drm_device *dev)
486{
487 struct radeon_device *rdev = dev->dev_private;
488 uint16_t pll_info;
489 struct radeon_pll *p1pll = &rdev->clock.p1pll;
490 struct radeon_pll *p2pll = &rdev->clock.p2pll;
491 struct radeon_pll *spll = &rdev->clock.spll;
492 struct radeon_pll *mpll = &rdev->clock.mpll;
493 int8_t rev;
494 uint16_t sclk, mclk;
495
496 if (rdev->bios == NULL)
497 return NULL;
498
499 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
500 if (pll_info) {
501 rev = RBIOS8(pll_info);
502
503 /* pixel clocks */
504 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
505 p1pll->reference_div = RBIOS16(pll_info + 0x10);
506 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
507 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
508
509 if (rev > 9) {
510 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
511 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
512 } else {
513 p1pll->pll_in_min = 40;
514 p1pll->pll_in_max = 500;
515 }
516 *p2pll = *p1pll;
517
518 /* system clock */
519 spll->reference_freq = RBIOS16(pll_info + 0x1a);
520 spll->reference_div = RBIOS16(pll_info + 0x1c);
521 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
522 spll->pll_out_max = RBIOS32(pll_info + 0x22);
523
524 if (rev > 10) {
525 spll->pll_in_min = RBIOS32(pll_info + 0x48);
526 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
527 } else {
528 /* ??? */
529 spll->pll_in_min = 40;
530 spll->pll_in_max = 500;
531 }
532
533 /* memory clock */
534 mpll->reference_freq = RBIOS16(pll_info + 0x26);
535 mpll->reference_div = RBIOS16(pll_info + 0x28);
536 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
537 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
538
539 if (rev > 10) {
540 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
541 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
542 } else {
543 /* ??? */
544 mpll->pll_in_min = 40;
545 mpll->pll_in_max = 500;
546 }
547
548 /* default sclk/mclk */
549 sclk = RBIOS16(pll_info + 0xa);
550 mclk = RBIOS16(pll_info + 0x8);
551 if (sclk == 0)
552 sclk = 200 * 100;
553 if (mclk == 0)
554 mclk = 200 * 100;
555
556 rdev->clock.default_sclk = sclk;
557 rdev->clock.default_mclk = mclk;
558
559 return true;
560 }
561 return false;
562}
563
564struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
565 radeon_encoder
566 *encoder)
567{
568 struct drm_device *dev = encoder->base.dev;
569 struct radeon_device *rdev = dev->dev_private;
570 uint16_t dac_info;
571 uint8_t rev, bg, dac;
572 struct radeon_encoder_primary_dac *p_dac = NULL;
573
574 if (rdev->bios == NULL)
575 return NULL;
576
577 /* check CRT table */
578 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
579 if (dac_info) {
580 p_dac =
581 kzalloc(sizeof(struct radeon_encoder_primary_dac),
582 GFP_KERNEL);
583
584 if (!p_dac)
585 return NULL;
586
587 rev = RBIOS8(dac_info) & 0x3;
588 if (rev < 2) {
589 bg = RBIOS8(dac_info + 0x2) & 0xf;
590 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
591 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
592 } else {
593 bg = RBIOS8(dac_info + 0x2) & 0xf;
594 dac = RBIOS8(dac_info + 0x3) & 0xf;
595 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
596 }
597
598 }
599
600 return p_dac;
601}
602
603static enum radeon_tv_std
604radeon_combios_get_tv_info(struct radeon_encoder *encoder)
605{
606 struct drm_device *dev = encoder->base.dev;
607 struct radeon_device *rdev = dev->dev_private;
608 uint16_t tv_info;
609 enum radeon_tv_std tv_std = TV_STD_NTSC;
610
611 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
612 if (tv_info) {
613 if (RBIOS8(tv_info + 6) == 'T') {
614 switch (RBIOS8(tv_info + 7) & 0xf) {
615 case 1:
616 tv_std = TV_STD_NTSC;
617 DRM_INFO("Default TV standard: NTSC\n");
618 break;
619 case 2:
620 tv_std = TV_STD_PAL;
621 DRM_INFO("Default TV standard: PAL\n");
622 break;
623 case 3:
624 tv_std = TV_STD_PAL_M;
625 DRM_INFO("Default TV standard: PAL-M\n");
626 break;
627 case 4:
628 tv_std = TV_STD_PAL_60;
629 DRM_INFO("Default TV standard: PAL-60\n");
630 break;
631 case 5:
632 tv_std = TV_STD_NTSC_J;
633 DRM_INFO("Default TV standard: NTSC-J\n");
634 break;
635 case 6:
636 tv_std = TV_STD_SCART_PAL;
637 DRM_INFO("Default TV standard: SCART-PAL\n");
638 break;
639 default:
640 tv_std = TV_STD_NTSC;
641 DRM_INFO
642 ("Unknown TV standard; defaulting to NTSC\n");
643 break;
644 }
645
646 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
647 case 0:
648 DRM_INFO("29.498928713 MHz TV ref clk\n");
649 break;
650 case 1:
651 DRM_INFO("28.636360000 MHz TV ref clk\n");
652 break;
653 case 2:
654 DRM_INFO("14.318180000 MHz TV ref clk\n");
655 break;
656 case 3:
657 DRM_INFO("27.000000000 MHz TV ref clk\n");
658 break;
659 default:
660 break;
661 }
662 }
663 }
664 return tv_std;
665}
666
667static const uint32_t default_tvdac_adj[CHIP_LAST] = {
668 0x00000000, /* r100 */
669 0x00280000, /* rv100 */
670 0x00000000, /* rs100 */
671 0x00880000, /* rv200 */
672 0x00000000, /* rs200 */
673 0x00000000, /* r200 */
674 0x00770000, /* rv250 */
675 0x00290000, /* rs300 */
676 0x00560000, /* rv280 */
677 0x00780000, /* r300 */
678 0x00770000, /* r350 */
679 0x00780000, /* rv350 */
680 0x00780000, /* rv380 */
681 0x01080000, /* r420 */
682 0x01080000, /* r423 */
683 0x01080000, /* rv410 */
684 0x00780000, /* rs400 */
685 0x00780000, /* rs480 */
686};
687
6a719e05
DA		 688static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
689 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 690{
771fe6b9
JG		 691 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
692 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
693 tv_dac->ps2_tvdac_adj = 0x00880000;
694 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
695 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 696 return;
771fe6b9
JG		 697}
698
699struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
700 radeon_encoder
701 *encoder)
702{
703 struct drm_device *dev = encoder->base.dev;
704 struct radeon_device *rdev = dev->dev_private;
705 uint16_t dac_info;
706 uint8_t rev, bg, dac;
707 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 708 int found = 0;
709
710 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
711 if (!tv_dac)
712 return NULL;
771fe6b9
JG		 713
714 if (rdev->bios == NULL)
6a719e05 715 goto out;
771fe6b9
JG		 716
717 /* first check TV table */
718 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
719 if (dac_info) {
771fe6b9
JG		 720 rev = RBIOS8(dac_info + 0x3);
721 if (rev > 4) {
722 bg = RBIOS8(dac_info + 0xc) & 0xf;
723 dac = RBIOS8(dac_info + 0xd) & 0xf;
724 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
725
726 bg = RBIOS8(dac_info + 0xe) & 0xf;
727 dac = RBIOS8(dac_info + 0xf) & 0xf;
728 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
729
730 bg = RBIOS8(dac_info + 0x10) & 0xf;
731 dac = RBIOS8(dac_info + 0x11) & 0xf;
732 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 733 found = 1;
771fe6b9
JG		 734 } else if (rev > 1) {
735 bg = RBIOS8(dac_info + 0xc) & 0xf;
736 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
737 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
738
739 bg = RBIOS8(dac_info + 0xd) & 0xf;
740 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
741 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
742
743 bg = RBIOS8(dac_info + 0xe) & 0xf;
744 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
745 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 746 found = 1;
771fe6b9 747 }
771fe6b9 748 tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
6a719e05
DA		 749 }
750 if (!found) {
771fe6b9
JG		 751 /* then check CRT table */
752 dac_info =
753 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
754 if (dac_info) {
771fe6b9
JG		 755 rev = RBIOS8(dac_info) & 0x3;
756 if (rev < 2) {
757 bg = RBIOS8(dac_info + 0x3) & 0xf;
758 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
759 tv_dac->ps2_tvdac_adj =
760 (bg << 16) | (dac << 20);
761 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
762 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 763 found = 1;
771fe6b9
JG		 764 } else {
765 bg = RBIOS8(dac_info + 0x4) & 0xf;
766 dac = RBIOS8(dac_info + 0x5) & 0xf;
767 tv_dac->ps2_tvdac_adj =
768 (bg << 16) | (dac << 20);
769 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
770 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 771 found = 1;
771fe6b9 772 }
6fe7ac3f
AD		 773 } else {
774 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 775 }
776 }
777
6a719e05
DA		 778out:
779 if (!found) /* fallback to defaults */
780 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
781
771fe6b9
JG		 782 return tv_dac;
783}
784
785static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
786 radeon_device
787 *rdev)
788{
789 struct radeon_encoder_lvds *lvds = NULL;
790 uint32_t fp_vert_stretch, fp_horz_stretch;
791 uint32_t ppll_div_sel, ppll_val;
8b5c7444 792 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 793
794 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
795
796 if (!lvds)
797 return NULL;
798
799 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
800 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
801
8b5c7444
MD		 802 /* These should be fail-safe defaults, fingers crossed */
803 lvds->panel_pwr_delay = 200;
804 lvds->panel_vcc_delay = 2000;
805
806 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
807 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
808 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
809
771fe6b9
JG		 810 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
811 lvds->native_mode.panel_yres =
812 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
813 RADEON_VERT_PANEL_SHIFT) + 1;
814 else
815 lvds->native_mode.panel_yres =
816 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
817
818 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
819 lvds->native_mode.panel_xres =
820 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
821 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
822 else
823 lvds->native_mode.panel_xres =
824 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
825
826 if ((lvds->native_mode.panel_xres < 640) ||
827 (lvds->native_mode.panel_yres < 480)) {
828 lvds->native_mode.panel_xres = 640;
829 lvds->native_mode.panel_yres = 480;
830 }
831
832 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
833 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
834 if ((ppll_val & 0x000707ff) == 0x1bb)
835 lvds->use_bios_dividers = false;
836 else {
837 lvds->panel_ref_divider =
838 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
839 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
840 lvds->panel_fb_divider = ppll_val & 0x7ff;
841
842 if ((lvds->panel_ref_divider != 0) &&
843 (lvds->panel_fb_divider > 3))
844 lvds->use_bios_dividers = true;
845 }
846 lvds->panel_vcc_delay = 200;
847
848 DRM_INFO("Panel info derived from registers\n");
849 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
850 lvds->native_mode.panel_yres);
851
852 return lvds;
853}
854
855struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
856 *encoder)
857{
858 struct drm_device *dev = encoder->base.dev;
859 struct radeon_device *rdev = dev->dev_private;
860 uint16_t lcd_info;
861 uint32_t panel_setup;
862 char stmp[30];
863 int tmp, i;
864 struct radeon_encoder_lvds *lvds = NULL;
865
8dfaa8a7
MD		 866 if (rdev->bios == NULL) {
867 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
868 goto out;
869 }
771fe6b9
JG		 870
871 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
872
873 if (lcd_info) {
874 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
875
876 if (!lvds)
877 return NULL;
878
879 for (i = 0; i < 24; i++)
880 stmp[i] = RBIOS8(lcd_info + i + 1);
881 stmp[24] = 0;
882
883 DRM_INFO("Panel ID String: %s\n", stmp);
884
885 lvds->native_mode.panel_xres = RBIOS16(lcd_info + 0x19);
886 lvds->native_mode.panel_yres = RBIOS16(lcd_info + 0x1b);
887
888 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
889 lvds->native_mode.panel_yres);
890
891 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
892 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
893 lvds->panel_vcc_delay = 2000;
894
895 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
896 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
897 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
898
899 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
900 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
901 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
902 if ((lvds->panel_ref_divider != 0) &&
903 (lvds->panel_fb_divider > 3))
904 lvds->use_bios_dividers = true;
905
906 panel_setup = RBIOS32(lcd_info + 0x39);
907 lvds->lvds_gen_cntl = 0xff00;
908 if (panel_setup & 0x1)
909 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
910
911 if ((panel_setup >> 4) & 0x1)
912 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
913
914 switch ((panel_setup >> 8) & 0x7) {
915 case 0:
916 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
917 break;
918 case 1:
919 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
920 break;
921 case 2:
922 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
923 break;
924 default:
925 break;
926 }
927
928 if ((panel_setup >> 16) & 0x1)
929 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
930
931 if ((panel_setup >> 17) & 0x1)
932 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
933
934 if ((panel_setup >> 18) & 0x1)
935 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
936
937 if ((panel_setup >> 23) & 0x1)
938 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
939
940 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
941
942 for (i = 0; i < 32; i++) {
943 tmp = RBIOS16(lcd_info + 64 + i * 2);
944 if (tmp == 0)
945 break;
946
947 if ((RBIOS16(tmp) == lvds->native_mode.panel_xres) &&
948 (RBIOS16(tmp + 2) ==
949 lvds->native_mode.panel_yres)) {
950 lvds->native_mode.hblank =
951 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
952 lvds->native_mode.hoverplus =
953 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) -
954 1) * 8;
955 lvds->native_mode.hsync_width =
956 RBIOS8(tmp + 23) * 8;
957
958 lvds->native_mode.vblank = (RBIOS16(tmp + 24) -
959 RBIOS16(tmp + 26));
960 lvds->native_mode.voverplus =
961 ((RBIOS16(tmp + 28) & 0x7ff) -
962 RBIOS16(tmp + 26));
963 lvds->native_mode.vsync_width =
964 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
965 lvds->native_mode.dotclock =
966 RBIOS16(tmp + 9) * 10;
967 lvds->native_mode.flags = 0;
968 }
969 }
6fe7ac3f 970 } else {
771fe6b9 971 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 972 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 973 }
8dfaa8a7
MD		 974out:
975 if (lvds)
976 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 977 return lvds;
978}
979
980static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
981 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
982 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
983 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
984 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
985 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
986 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
987 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
988 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
989 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
990 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
991 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
992 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
993 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
994 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
995 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
996 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
997 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RS400 */
998 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RS480 */
999};
1000
1001static struct radeon_encoder_int_tmds
1002 *radeon_legacy_get_tmds_info_from_table(struct radeon_device *rdev)
1003{
1004 int i;
1005 struct radeon_encoder_int_tmds *tmds = NULL;
1006
1007 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1008
1009 if (!tmds)
1010 return NULL;
1011
1012 for (i = 0; i < 4; i++) {
1013 tmds->tmds_pll[i].value =
1014 default_tmds_pll[rdev->family][i].value;
1015 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1016 }
1017
1018 return tmds;
1019}
1020
1021struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct
1022 radeon_encoder
1023 *encoder)
1024{
1025 struct drm_device *dev = encoder->base.dev;
1026 struct radeon_device *rdev = dev->dev_private;
1027 uint16_t tmds_info;
1028 int i, n;
1029 uint8_t ver;
1030 struct radeon_encoder_int_tmds *tmds = NULL;
1031
1032 if (rdev->bios == NULL)
1033 return radeon_legacy_get_tmds_info_from_table(rdev);
1034
1035 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1036
1037 if (tmds_info) {
1038 tmds =
1039 kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1040
1041 if (!tmds)
1042 return NULL;
1043
1044 ver = RBIOS8(tmds_info);
1045 DRM_INFO("DFP table revision: %d\n", ver);
1046 if (ver == 3) {
1047 n = RBIOS8(tmds_info + 5) + 1;
1048 if (n > 4)
1049 n = 4;
1050 for (i = 0; i < n; i++) {
1051 tmds->tmds_pll[i].value =
1052 RBIOS32(tmds_info + i * 10 + 0x08);
1053 tmds->tmds_pll[i].freq =
1054 RBIOS16(tmds_info + i * 10 + 0x10);
1055 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1056 tmds->tmds_pll[i].freq,
1057 tmds->tmds_pll[i].value);
1058 }
1059 } else if (ver == 4) {
1060 int stride = 0;
1061 n = RBIOS8(tmds_info + 5) + 1;
1062 if (n > 4)
1063 n = 4;
1064 for (i = 0; i < n; i++) {
1065 tmds->tmds_pll[i].value =
1066 RBIOS32(tmds_info + stride + 0x08);
1067 tmds->tmds_pll[i].freq =
1068 RBIOS16(tmds_info + stride + 0x10);
1069 if (i == 0)
1070 stride += 10;
1071 else
1072 stride += 6;
1073 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1074 tmds->tmds_pll[i].freq,
1075 tmds->tmds_pll[i].value);
1076 }
1077 }
1078 } else
1079 DRM_INFO("No TMDS info found in BIOS\n");
1080 return tmds;
1081}
1082
1083void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
1084{
1085 struct drm_device *dev = encoder->base.dev;
1086 struct radeon_device *rdev = dev->dev_private;
1087 uint16_t ext_tmds_info;
1088 uint8_t ver;
1089
1090 if (rdev->bios == NULL)
1091 return;
1092
1093 ext_tmds_info =
1094 combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1095 if (ext_tmds_info) {
1096 ver = RBIOS8(ext_tmds_info);
1097 DRM_INFO("External TMDS Table revision: %d\n", ver);
1098 // TODO
1099 }
1100}
1101
1102bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1103{
1104 struct radeon_device *rdev = dev->dev_private;
1105 struct radeon_i2c_bus_rec ddc_i2c;
1106
1107 rdev->mode_info.connector_table = radeon_connector_table;
1108 if (rdev->mode_info.connector_table == CT_NONE) {
1109#ifdef CONFIG_PPC_PMAC
1110 if (machine_is_compatible("PowerBook3,3")) {
1111 /* powerbook with VGA */
1112 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1113 } else if (machine_is_compatible("PowerBook3,4") ||
1114 machine_is_compatible("PowerBook3,5")) {
1115 /* powerbook with internal tmds */
1116 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1117 } else if (machine_is_compatible("PowerBook5,1") ||
1118 machine_is_compatible("PowerBook5,2") ||
1119 machine_is_compatible("PowerBook5,3") ||
1120 machine_is_compatible("PowerBook5,4") ||
1121 machine_is_compatible("PowerBook5,5")) {
1122 /* powerbook with external single link tmds (sil164) */
1123 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1124 } else if (machine_is_compatible("PowerBook5,6")) {
1125 /* powerbook with external dual or single link tmds */
1126 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1127 } else if (machine_is_compatible("PowerBook5,7") ||
1128 machine_is_compatible("PowerBook5,8") ||
1129 machine_is_compatible("PowerBook5,9")) {
1130 /* PowerBook6,2 ? */
1131 /* powerbook with external dual link tmds (sil1178?) */
1132 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1133 } else if (machine_is_compatible("PowerBook4,1") ||
1134 machine_is_compatible("PowerBook4,2") ||
1135 machine_is_compatible("PowerBook4,3") ||
1136 machine_is_compatible("PowerBook6,3") ||
1137 machine_is_compatible("PowerBook6,5") ||
1138 machine_is_compatible("PowerBook6,7")) {
1139 /* ibook */
1140 rdev->mode_info.connector_table = CT_IBOOK;
1141 } else if (machine_is_compatible("PowerMac4,4")) {
1142 /* emac */
1143 rdev->mode_info.connector_table = CT_EMAC;
1144 } else if (machine_is_compatible("PowerMac10,1")) {
1145 /* mini with internal tmds */
1146 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1147 } else if (machine_is_compatible("PowerMac10,2")) {
1148 /* mini with external tmds */
1149 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1150 } else if (machine_is_compatible("PowerMac12,1")) {
1151 /* PowerMac8,1 ? */
1152 /* imac g5 isight */
1153 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1154 } else
1155#endif /* CONFIG_PPC_PMAC */
1156 rdev->mode_info.connector_table = CT_GENERIC;
1157 }
1158
1159 switch (rdev->mode_info.connector_table) {
1160 case CT_GENERIC:
1161 DRM_INFO("Connector Table: %d (generic)\n",
1162 rdev->mode_info.connector_table);
1163 /* these are the most common settings */
1164 if (rdev->flags & RADEON_SINGLE_CRTC) {
1165 /* VGA - primary dac */
1166 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1167 radeon_add_legacy_encoder(dev,
1168 radeon_get_encoder_id(dev,
1169 ATOM_DEVICE_CRT1_SUPPORT,
1170 1),
1171 ATOM_DEVICE_CRT1_SUPPORT);
1172 radeon_add_legacy_connector(dev, 0,
1173 ATOM_DEVICE_CRT1_SUPPORT,
1174 DRM_MODE_CONNECTOR_VGA,
1175 &ddc_i2c);
1176 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1177 /* LVDS */
1178 ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
1179 radeon_add_legacy_encoder(dev,
1180 radeon_get_encoder_id(dev,
1181 ATOM_DEVICE_LCD1_SUPPORT,
1182 0),
1183 ATOM_DEVICE_LCD1_SUPPORT);
1184 radeon_add_legacy_connector(dev, 0,
1185 ATOM_DEVICE_LCD1_SUPPORT,
1186 DRM_MODE_CONNECTOR_LVDS,
1187 &ddc_i2c);
1188
1189 /* VGA - primary dac */
1190 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1191 radeon_add_legacy_encoder(dev,
1192 radeon_get_encoder_id(dev,
1193 ATOM_DEVICE_CRT1_SUPPORT,
1194 1),
1195 ATOM_DEVICE_CRT1_SUPPORT);
1196 radeon_add_legacy_connector(dev, 1,
1197 ATOM_DEVICE_CRT1_SUPPORT,
1198 DRM_MODE_CONNECTOR_VGA,
1199 &ddc_i2c);
1200 } else {
1201 /* DVI-I - tv dac, int tmds */
1202 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1203 radeon_add_legacy_encoder(dev,
1204 radeon_get_encoder_id(dev,
1205 ATOM_DEVICE_DFP1_SUPPORT,
1206 0),
1207 ATOM_DEVICE_DFP1_SUPPORT);
1208 radeon_add_legacy_encoder(dev,
1209 radeon_get_encoder_id(dev,
1210 ATOM_DEVICE_CRT2_SUPPORT,
1211 2),
1212 ATOM_DEVICE_CRT2_SUPPORT);
1213 radeon_add_legacy_connector(dev, 0,
1214 ATOM_DEVICE_DFP1_SUPPORT |
1215 ATOM_DEVICE_CRT2_SUPPORT,
1216 DRM_MODE_CONNECTOR_DVII,
1217 &ddc_i2c);
1218
1219 /* VGA - primary dac */
1220 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1221 radeon_add_legacy_encoder(dev,
1222 radeon_get_encoder_id(dev,
1223 ATOM_DEVICE_CRT1_SUPPORT,
1224 1),
1225 ATOM_DEVICE_CRT1_SUPPORT);
1226 radeon_add_legacy_connector(dev, 1,
1227 ATOM_DEVICE_CRT1_SUPPORT,
1228 DRM_MODE_CONNECTOR_VGA,
1229 &ddc_i2c);
1230 }
1231
1232 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1233 /* TV - tv dac */
1234 radeon_add_legacy_encoder(dev,
1235 radeon_get_encoder_id(dev,
1236 ATOM_DEVICE_TV1_SUPPORT,
1237 2),
1238 ATOM_DEVICE_TV1_SUPPORT);
1239 radeon_add_legacy_connector(dev, 2,
1240 ATOM_DEVICE_TV1_SUPPORT,
1241 DRM_MODE_CONNECTOR_SVIDEO,
1242 &ddc_i2c);
1243 }
1244 break;
1245 case CT_IBOOK:
1246 DRM_INFO("Connector Table: %d (ibook)\n",
1247 rdev->mode_info.connector_table);
1248 /* LVDS */
1249 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1250 radeon_add_legacy_encoder(dev,
1251 radeon_get_encoder_id(dev,
1252 ATOM_DEVICE_LCD1_SUPPORT,
1253 0),
1254 ATOM_DEVICE_LCD1_SUPPORT);
1255 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1256 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1257 /* VGA - TV DAC */
1258 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1259 radeon_add_legacy_encoder(dev,
1260 radeon_get_encoder_id(dev,
1261 ATOM_DEVICE_CRT2_SUPPORT,
1262 2),
1263 ATOM_DEVICE_CRT2_SUPPORT);
1264 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1265 DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1266 /* TV - TV DAC */
1267 radeon_add_legacy_encoder(dev,
1268 radeon_get_encoder_id(dev,
1269 ATOM_DEVICE_TV1_SUPPORT,
1270 2),
1271 ATOM_DEVICE_TV1_SUPPORT);
1272 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1273 DRM_MODE_CONNECTOR_SVIDEO,
1274 &ddc_i2c);
1275 break;
1276 case CT_POWERBOOK_EXTERNAL:
1277 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1278 rdev->mode_info.connector_table);
1279 /* LVDS */
1280 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1281 radeon_add_legacy_encoder(dev,
1282 radeon_get_encoder_id(dev,
1283 ATOM_DEVICE_LCD1_SUPPORT,
1284 0),
1285 ATOM_DEVICE_LCD1_SUPPORT);
1286 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1287 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1288 /* DVI-I - primary dac, ext tmds */
1289 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1290 radeon_add_legacy_encoder(dev,
1291 radeon_get_encoder_id(dev,
1292 ATOM_DEVICE_DFP2_SUPPORT,
1293 0),
1294 ATOM_DEVICE_DFP2_SUPPORT);
1295 radeon_add_legacy_encoder(dev,
1296 radeon_get_encoder_id(dev,
1297 ATOM_DEVICE_CRT1_SUPPORT,
1298 1),
1299 ATOM_DEVICE_CRT1_SUPPORT);
1300 radeon_add_legacy_connector(dev, 1,
1301 ATOM_DEVICE_DFP2_SUPPORT |
1302 ATOM_DEVICE_CRT1_SUPPORT,
1303 DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1304 /* TV - TV DAC */
1305 radeon_add_legacy_encoder(dev,
1306 radeon_get_encoder_id(dev,
1307 ATOM_DEVICE_TV1_SUPPORT,
1308 2),
1309 ATOM_DEVICE_TV1_SUPPORT);
1310 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1311 DRM_MODE_CONNECTOR_SVIDEO,
1312 &ddc_i2c);
1313 break;
1314 case CT_POWERBOOK_INTERNAL:
1315 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1316 rdev->mode_info.connector_table);
1317 /* LVDS */
1318 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1319 radeon_add_legacy_encoder(dev,
1320 radeon_get_encoder_id(dev,
1321 ATOM_DEVICE_LCD1_SUPPORT,
1322 0),
1323 ATOM_DEVICE_LCD1_SUPPORT);
1324 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1325 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1326 /* DVI-I - primary dac, int tmds */
1327 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1328 radeon_add_legacy_encoder(dev,
1329 radeon_get_encoder_id(dev,
1330 ATOM_DEVICE_DFP1_SUPPORT,
1331 0),
1332 ATOM_DEVICE_DFP1_SUPPORT);
1333 radeon_add_legacy_encoder(dev,
1334 radeon_get_encoder_id(dev,
1335 ATOM_DEVICE_CRT1_SUPPORT,
1336 1),
1337 ATOM_DEVICE_CRT1_SUPPORT);
1338 radeon_add_legacy_connector(dev, 1,
1339 ATOM_DEVICE_DFP1_SUPPORT |
1340 ATOM_DEVICE_CRT1_SUPPORT,
1341 DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1342 /* TV - TV DAC */
1343 radeon_add_legacy_encoder(dev,
1344 radeon_get_encoder_id(dev,
1345 ATOM_DEVICE_TV1_SUPPORT,
1346 2),
1347 ATOM_DEVICE_TV1_SUPPORT);
1348 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1349 DRM_MODE_CONNECTOR_SVIDEO,
1350 &ddc_i2c);
1351 break;
1352 case CT_POWERBOOK_VGA:
1353 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1354 rdev->mode_info.connector_table);
1355 /* LVDS */
1356 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1357 radeon_add_legacy_encoder(dev,
1358 radeon_get_encoder_id(dev,
1359 ATOM_DEVICE_LCD1_SUPPORT,
1360 0),
1361 ATOM_DEVICE_LCD1_SUPPORT);
1362 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1363 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1364 /* VGA - primary dac */
1365 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1366 radeon_add_legacy_encoder(dev,
1367 radeon_get_encoder_id(dev,
1368 ATOM_DEVICE_CRT1_SUPPORT,
1369 1),
1370 ATOM_DEVICE_CRT1_SUPPORT);
1371 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1372 DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1373 /* TV - TV DAC */
1374 radeon_add_legacy_encoder(dev,
1375 radeon_get_encoder_id(dev,
1376 ATOM_DEVICE_TV1_SUPPORT,
1377 2),
1378 ATOM_DEVICE_TV1_SUPPORT);
1379 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1380 DRM_MODE_CONNECTOR_SVIDEO,
1381 &ddc_i2c);
1382 break;
1383 case CT_MINI_EXTERNAL:
1384 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1385 rdev->mode_info.connector_table);
1386 /* DVI-I - tv dac, ext tmds */
1387 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1388 radeon_add_legacy_encoder(dev,
1389 radeon_get_encoder_id(dev,
1390 ATOM_DEVICE_DFP2_SUPPORT,
1391 0),
1392 ATOM_DEVICE_DFP2_SUPPORT);
1393 radeon_add_legacy_encoder(dev,
1394 radeon_get_encoder_id(dev,
1395 ATOM_DEVICE_CRT2_SUPPORT,
1396 2),
1397 ATOM_DEVICE_CRT2_SUPPORT);
1398 radeon_add_legacy_connector(dev, 0,
1399 ATOM_DEVICE_DFP2_SUPPORT |
1400 ATOM_DEVICE_CRT2_SUPPORT,
1401 DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1402 /* TV - TV DAC */
1403 radeon_add_legacy_encoder(dev,
1404 radeon_get_encoder_id(dev,
1405 ATOM_DEVICE_TV1_SUPPORT,
1406 2),
1407 ATOM_DEVICE_TV1_SUPPORT);
1408 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1409 DRM_MODE_CONNECTOR_SVIDEO,
1410 &ddc_i2c);
1411 break;
1412 case CT_MINI_INTERNAL:
1413 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1414 rdev->mode_info.connector_table);
1415 /* DVI-I - tv dac, int tmds */
1416 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1417 radeon_add_legacy_encoder(dev,
1418 radeon_get_encoder_id(dev,
1419 ATOM_DEVICE_DFP1_SUPPORT,
1420 0),
1421 ATOM_DEVICE_DFP1_SUPPORT);
1422 radeon_add_legacy_encoder(dev,
1423 radeon_get_encoder_id(dev,
1424 ATOM_DEVICE_CRT2_SUPPORT,
1425 2),
1426 ATOM_DEVICE_CRT2_SUPPORT);
1427 radeon_add_legacy_connector(dev, 0,
1428 ATOM_DEVICE_DFP1_SUPPORT |
1429 ATOM_DEVICE_CRT2_SUPPORT,
1430 DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1431 /* TV - TV DAC */
1432 radeon_add_legacy_encoder(dev,
1433 radeon_get_encoder_id(dev,
1434 ATOM_DEVICE_TV1_SUPPORT,
1435 2),
1436 ATOM_DEVICE_TV1_SUPPORT);
1437 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1438 DRM_MODE_CONNECTOR_SVIDEO,
1439 &ddc_i2c);
1440 break;
1441 case CT_IMAC_G5_ISIGHT:
1442 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1443 rdev->mode_info.connector_table);
1444 /* DVI-D - int tmds */
1445 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1446 radeon_add_legacy_encoder(dev,
1447 radeon_get_encoder_id(dev,
1448 ATOM_DEVICE_DFP1_SUPPORT,
1449 0),
1450 ATOM_DEVICE_DFP1_SUPPORT);
1451 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1452 DRM_MODE_CONNECTOR_DVID, &ddc_i2c);
1453 /* VGA - tv dac */
1454 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1455 radeon_add_legacy_encoder(dev,
1456 radeon_get_encoder_id(dev,
1457 ATOM_DEVICE_CRT2_SUPPORT,
1458 2),
1459 ATOM_DEVICE_CRT2_SUPPORT);
1460 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1461 DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1462 /* TV - TV DAC */
1463 radeon_add_legacy_encoder(dev,
1464 radeon_get_encoder_id(dev,
1465 ATOM_DEVICE_TV1_SUPPORT,
1466 2),
1467 ATOM_DEVICE_TV1_SUPPORT);
1468 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1469 DRM_MODE_CONNECTOR_SVIDEO,
1470 &ddc_i2c);
1471 break;
1472 case CT_EMAC:
1473 DRM_INFO("Connector Table: %d (emac)\n",
1474 rdev->mode_info.connector_table);
1475 /* VGA - primary dac */
1476 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1477 radeon_add_legacy_encoder(dev,
1478 radeon_get_encoder_id(dev,
1479 ATOM_DEVICE_CRT1_SUPPORT,
1480 1),
1481 ATOM_DEVICE_CRT1_SUPPORT);
1482 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1483 DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1484 /* VGA - tv dac */
1485 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1486 radeon_add_legacy_encoder(dev,
1487 radeon_get_encoder_id(dev,
1488 ATOM_DEVICE_CRT2_SUPPORT,
1489 2),
1490 ATOM_DEVICE_CRT2_SUPPORT);
1491 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1492 DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1493 /* TV - TV DAC */
1494 radeon_add_legacy_encoder(dev,
1495 radeon_get_encoder_id(dev,
1496 ATOM_DEVICE_TV1_SUPPORT,
1497 2),
1498 ATOM_DEVICE_TV1_SUPPORT);
1499 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1500 DRM_MODE_CONNECTOR_SVIDEO,
1501 &ddc_i2c);
1502 break;
1503 default:
1504 DRM_INFO("Connector table: %d (invalid)\n",
1505 rdev->mode_info.connector_table);
1506 return false;
1507 }
1508
1509 radeon_link_encoder_connector(dev);
1510
1511 return true;
1512}
1513
1514static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1515 int bios_index,
1516 enum radeon_combios_connector
1517 *legacy_connector,
1518 struct radeon_i2c_bus_rec *ddc_i2c)
1519{
1520 struct radeon_device *rdev = dev->dev_private;
1521
1522 /* XPRESS DDC quirks */
1523 if ((rdev->family == CHIP_RS400 ||
1524 rdev->family == CHIP_RS480) &&
1525 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1526 *ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1527 else if ((rdev->family == CHIP_RS400 ||
1528 rdev->family == CHIP_RS480) &&
1529 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1530 ddc_i2c->valid = true;
1531 ddc_i2c->mask_clk_mask = (0x20 << 8);
1532 ddc_i2c->mask_data_mask = 0x80;
1533 ddc_i2c->a_clk_mask = (0x20 << 8);
1534 ddc_i2c->a_data_mask = 0x80;
1535 ddc_i2c->put_clk_mask = (0x20 << 8);
1536 ddc_i2c->put_data_mask = 0x80;
1537 ddc_i2c->get_clk_mask = (0x20 << 8);
1538 ddc_i2c->get_data_mask = 0x80;
1539 ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK;
1540 ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK;
1541 ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A;
1542 ddc_i2c->a_data_reg = RADEON_GPIOPAD_A;
1543 ddc_i2c->put_clk_reg = RADEON_GPIOPAD_EN;
1544 ddc_i2c->put_data_reg = RADEON_GPIOPAD_EN;
1545 ddc_i2c->get_clk_reg = RADEON_LCD_GPIO_Y_REG;
1546 ddc_i2c->get_data_reg = RADEON_LCD_GPIO_Y_REG;
1547 }
1548
1549 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1550 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1551 if (dev->pdev->device == 0x515e &&
1552 dev->pdev->subsystem_vendor == 0x1014) {
1553 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1554 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1555 return false;
1556 }
1557
1558 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1559 if (dev->pdev->device == 0x5159 &&
1560 dev->pdev->subsystem_vendor == 0x1002 &&
1561 dev->pdev->subsystem_device == 0x013a) {
1562 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1563 *legacy_connector = CONNECTOR_CRT_LEGACY;
1564
1565 }
1566
1567 /* X300 card with extra non-existent DVI port */
1568 if (dev->pdev->device == 0x5B60 &&
1569 dev->pdev->subsystem_vendor == 0x17af &&
1570 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1571 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1572 return false;
1573 }
1574
1575 return true;
1576}
1577
1578bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1579{
1580 struct radeon_device *rdev = dev->dev_private;
1581 uint32_t conn_info, entry, devices;
1582 uint16_t tmp;
1583 enum radeon_combios_ddc ddc_type;
1584 enum radeon_combios_connector connector;
1585 int i = 0;
1586 struct radeon_i2c_bus_rec ddc_i2c;
1587
1588 if (rdev->bios == NULL)
1589 return false;
1590
1591 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1592 if (conn_info) {
1593 for (i = 0; i < 4; i++) {
1594 entry = conn_info + 2 + i * 2;
1595
1596 if (!RBIOS16(entry))
1597 break;
1598
1599 tmp = RBIOS16(entry);
1600
1601 connector = (tmp >> 12) & 0xf;
1602
1603 ddc_type = (tmp >> 8) & 0xf;
1604 switch (ddc_type) {
1605 case DDC_MONID:
1606 ddc_i2c =
1607 combios_setup_i2c_bus(RADEON_GPIO_MONID);
1608 break;
1609 case DDC_DVI:
1610 ddc_i2c =
1611 combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1612 break;
1613 case DDC_VGA:
1614 ddc_i2c =
1615 combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1616 break;
1617 case DDC_CRT2:
1618 ddc_i2c =
1619 combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1620 break;
1621 default:
1622 break;
1623 }
1624
1625 radeon_apply_legacy_quirks(dev, i, &connector,
1626 &ddc_i2c);
1627
1628 switch (connector) {
1629 case CONNECTOR_PROPRIETARY_LEGACY:
1630 if ((tmp >> 4) & 0x1)
1631 devices = ATOM_DEVICE_DFP2_SUPPORT;
1632 else
1633 devices = ATOM_DEVICE_DFP1_SUPPORT;
1634 radeon_add_legacy_encoder(dev,
1635 radeon_get_encoder_id
1636 (dev, devices, 0),
1637 devices);
1638 radeon_add_legacy_connector(dev, i, devices,
1639 legacy_connector_convert
1640 [connector],
1641 &ddc_i2c);
1642 break;
1643 case CONNECTOR_CRT_LEGACY:
1644 if (tmp & 0x1) {
1645 devices = ATOM_DEVICE_CRT2_SUPPORT;
1646 radeon_add_legacy_encoder(dev,
1647 radeon_get_encoder_id
1648 (dev,
1649 ATOM_DEVICE_CRT2_SUPPORT,
1650 2),
1651 ATOM_DEVICE_CRT2_SUPPORT);
1652 } else {
1653 devices = ATOM_DEVICE_CRT1_SUPPORT;
1654 radeon_add_legacy_encoder(dev,
1655 radeon_get_encoder_id
1656 (dev,
1657 ATOM_DEVICE_CRT1_SUPPORT,
1658 1),
1659 ATOM_DEVICE_CRT1_SUPPORT);
1660 }
1661 radeon_add_legacy_connector(dev,
1662 i,
1663 devices,
1664 legacy_connector_convert
1665 [connector],
1666 &ddc_i2c);
1667 break;
1668 case CONNECTOR_DVI_I_LEGACY:
1669 devices = 0;
1670 if (tmp & 0x1) {
1671 devices |= ATOM_DEVICE_CRT2_SUPPORT;
1672 radeon_add_legacy_encoder(dev,
1673 radeon_get_encoder_id
1674 (dev,
1675 ATOM_DEVICE_CRT2_SUPPORT,
1676 2),
1677 ATOM_DEVICE_CRT2_SUPPORT);
1678 } else {
1679 devices |= ATOM_DEVICE_CRT1_SUPPORT;
1680 radeon_add_legacy_encoder(dev,
1681 radeon_get_encoder_id
1682 (dev,
1683 ATOM_DEVICE_CRT1_SUPPORT,
1684 1),
1685 ATOM_DEVICE_CRT1_SUPPORT);
1686 }
1687 if ((tmp >> 4) & 0x1) {
1688 devices |= ATOM_DEVICE_DFP2_SUPPORT;
1689 radeon_add_legacy_encoder(dev,
1690 radeon_get_encoder_id
1691 (dev,
1692 ATOM_DEVICE_DFP2_SUPPORT,
1693 0),
1694 ATOM_DEVICE_DFP2_SUPPORT);
1695 } else {
1696 devices |= ATOM_DEVICE_DFP1_SUPPORT;
1697 radeon_add_legacy_encoder(dev,
1698 radeon_get_encoder_id
1699 (dev,
1700 ATOM_DEVICE_DFP1_SUPPORT,
1701 0),
1702 ATOM_DEVICE_DFP1_SUPPORT);
1703 }
1704 radeon_add_legacy_connector(dev,
1705 i,
1706 devices,
1707 legacy_connector_convert
1708 [connector],
1709 &ddc_i2c);
1710 break;
1711 case CONNECTOR_DVI_D_LEGACY:
1712 if ((tmp >> 4) & 0x1)
1713 devices = ATOM_DEVICE_DFP2_SUPPORT;
1714 else
1715 devices = ATOM_DEVICE_DFP1_SUPPORT;
1716 radeon_add_legacy_encoder(dev,
1717 radeon_get_encoder_id
1718 (dev, devices, 0),
1719 devices);
1720 radeon_add_legacy_connector(dev, i, devices,
1721 legacy_connector_convert
1722 [connector],
1723 &ddc_i2c);
1724 break;
1725 case CONNECTOR_CTV_LEGACY:
1726 case CONNECTOR_STV_LEGACY:
1727 radeon_add_legacy_encoder(dev,
1728 radeon_get_encoder_id
1729 (dev,
1730 ATOM_DEVICE_TV1_SUPPORT,
1731 2),
1732 ATOM_DEVICE_TV1_SUPPORT);
1733 radeon_add_legacy_connector(dev, i,
1734 ATOM_DEVICE_TV1_SUPPORT,
1735 legacy_connector_convert
1736 [connector],
1737 &ddc_i2c);
1738 break;
1739 default:
1740 DRM_ERROR("Unknown connector type: %d\n",
1741 connector);
1742 continue;
1743 }
1744
1745 }
1746 } else {
1747 uint16_t tmds_info =
1748 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1749 if (tmds_info) {
1750 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
1751
1752 radeon_add_legacy_encoder(dev,
1753 radeon_get_encoder_id(dev,
1754 ATOM_DEVICE_CRT1_SUPPORT,
1755 1),
1756 ATOM_DEVICE_CRT1_SUPPORT);
1757 radeon_add_legacy_encoder(dev,
1758 radeon_get_encoder_id(dev,
1759 ATOM_DEVICE_DFP1_SUPPORT,
1760 0),
1761 ATOM_DEVICE_DFP1_SUPPORT);
1762
1763 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1764 radeon_add_legacy_connector(dev,
1765 0,
1766 ATOM_DEVICE_CRT1_SUPPORT |
1767 ATOM_DEVICE_DFP1_SUPPORT,
1768 DRM_MODE_CONNECTOR_DVII,
1769 &ddc_i2c);
1770 } else {
1771 DRM_DEBUG("No connector info found\n");
1772 return false;
1773 }
1774 }
1775
1776 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
1777 uint16_t lcd_info =
1778 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1779 if (lcd_info) {
1780 uint16_t lcd_ddc_info =
1781 combios_get_table_offset(dev,
1782 COMBIOS_LCD_DDC_INFO_TABLE);
1783
1784 radeon_add_legacy_encoder(dev,
1785 radeon_get_encoder_id(dev,
1786 ATOM_DEVICE_LCD1_SUPPORT,
1787 0),
1788 ATOM_DEVICE_LCD1_SUPPORT);
1789
1790 if (lcd_ddc_info) {
1791 ddc_type = RBIOS8(lcd_ddc_info + 2);
1792 switch (ddc_type) {
1793 case DDC_MONID:
1794 ddc_i2c =
1795 combios_setup_i2c_bus
1796 (RADEON_GPIO_MONID);
1797 break;
1798 case DDC_DVI:
1799 ddc_i2c =
1800 combios_setup_i2c_bus
1801 (RADEON_GPIO_DVI_DDC);
1802 break;
1803 case DDC_VGA:
1804 ddc_i2c =
1805 combios_setup_i2c_bus
1806 (RADEON_GPIO_VGA_DDC);
1807 break;
1808 case DDC_CRT2:
1809 ddc_i2c =
1810 combios_setup_i2c_bus
1811 (RADEON_GPIO_CRT2_DDC);
1812 break;
1813 case DDC_LCD:
1814 ddc_i2c =
1815 combios_setup_i2c_bus
1816 (RADEON_LCD_GPIO_MASK);
1817 ddc_i2c.mask_clk_mask =
1818 RBIOS32(lcd_ddc_info + 3);
1819 ddc_i2c.mask_data_mask =
1820 RBIOS32(lcd_ddc_info + 7);
1821 ddc_i2c.a_clk_mask =
1822 RBIOS32(lcd_ddc_info + 3);
1823 ddc_i2c.a_data_mask =
1824 RBIOS32(lcd_ddc_info + 7);
1825 ddc_i2c.put_clk_mask =
1826 RBIOS32(lcd_ddc_info + 3);
1827 ddc_i2c.put_data_mask =
1828 RBIOS32(lcd_ddc_info + 7);
1829 ddc_i2c.get_clk_mask =
1830 RBIOS32(lcd_ddc_info + 3);
1831 ddc_i2c.get_data_mask =
1832 RBIOS32(lcd_ddc_info + 7);
1833 break;
1834 case DDC_GPIO:
1835 ddc_i2c =
1836 combios_setup_i2c_bus
1837 (RADEON_MDGPIO_EN_REG);
1838 ddc_i2c.mask_clk_mask =
1839 RBIOS32(lcd_ddc_info + 3);
1840 ddc_i2c.mask_data_mask =
1841 RBIOS32(lcd_ddc_info + 7);
1842 ddc_i2c.a_clk_mask =
1843 RBIOS32(lcd_ddc_info + 3);
1844 ddc_i2c.a_data_mask =
1845 RBIOS32(lcd_ddc_info + 7);
1846 ddc_i2c.put_clk_mask =
1847 RBIOS32(lcd_ddc_info + 3);
1848 ddc_i2c.put_data_mask =
1849 RBIOS32(lcd_ddc_info + 7);
1850 ddc_i2c.get_clk_mask =
1851 RBIOS32(lcd_ddc_info + 3);
1852 ddc_i2c.get_data_mask =
1853 RBIOS32(lcd_ddc_info + 7);
1854 break;
1855 default:
1856 ddc_i2c.valid = false;
1857 break;
1858 }
1859 DRM_DEBUG("LCD DDC Info Table found!\n");
1860 } else
1861 ddc_i2c.valid = false;
1862
1863 radeon_add_legacy_connector(dev,
1864 5,
1865 ATOM_DEVICE_LCD1_SUPPORT,
1866 DRM_MODE_CONNECTOR_LVDS,
1867 &ddc_i2c);
1868 }
1869 }
1870
1871 /* check TV table */
1872 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1873 uint32_t tv_info =
1874 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1875 if (tv_info) {
1876 if (RBIOS8(tv_info + 6) == 'T') {
1877 radeon_add_legacy_encoder(dev,
1878 radeon_get_encoder_id
1879 (dev,
1880 ATOM_DEVICE_TV1_SUPPORT,
1881 2),
1882 ATOM_DEVICE_TV1_SUPPORT);
1883 radeon_add_legacy_connector(dev, 6,
1884 ATOM_DEVICE_TV1_SUPPORT,
1885 DRM_MODE_CONNECTOR_SVIDEO,
1886 &ddc_i2c);
1887 }
1888 }
1889 }
1890
1891 radeon_link_encoder_connector(dev);
1892
1893 return true;
1894}
1895
1896static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
1897{
1898 struct radeon_device *rdev = dev->dev_private;
1899
1900 if (offset) {
1901 while (RBIOS16(offset)) {
1902 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
1903 uint32_t addr = (RBIOS16(offset) & 0x1fff);
1904 uint32_t val, and_mask, or_mask;
1905 uint32_t tmp;
1906
1907 offset += 2;
1908 switch (cmd) {
1909 case 0:
1910 val = RBIOS32(offset);
1911 offset += 4;
1912 WREG32(addr, val);
1913 break;
1914 case 1:
1915 val = RBIOS32(offset);
1916 offset += 4;
1917 WREG32(addr, val);
1918 break;
1919 case 2:
1920 and_mask = RBIOS32(offset);
1921 offset += 4;
1922 or_mask = RBIOS32(offset);
1923 offset += 4;
1924 tmp = RREG32(addr);
1925 tmp &= and_mask;
1926 tmp |= or_mask;
1927 WREG32(addr, tmp);
1928 break;
1929 case 3:
1930 and_mask = RBIOS32(offset);
1931 offset += 4;
1932 or_mask = RBIOS32(offset);
1933 offset += 4;
1934 tmp = RREG32(addr);
1935 tmp &= and_mask;
1936 tmp |= or_mask;
1937 WREG32(addr, tmp);
1938 break;
1939 case 4:
1940 val = RBIOS16(offset);
1941 offset += 2;
1942 udelay(val);
1943 break;
1944 case 5:
1945 val = RBIOS16(offset);
1946 offset += 2;
1947 switch (addr) {
1948 case 8:
1949 while (val--) {
1950 if (!
1951 (RREG32_PLL
1952 (RADEON_CLK_PWRMGT_CNTL) &
1953 RADEON_MC_BUSY))
1954 break;
1955 }
1956 break;
1957 case 9:
1958 while (val--) {
1959 if ((RREG32(RADEON_MC_STATUS) &
1960 RADEON_MC_IDLE))
1961 break;
1962 }
1963 break;
1964 default:
1965 break;
1966 }
1967 break;
1968 default:
1969 break;
1970 }
1971 }
1972 }
1973}
1974
1975static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
1976{
1977 struct radeon_device *rdev = dev->dev_private;
1978
1979 if (offset) {
1980 while (RBIOS8(offset)) {
1981 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
1982 uint8_t addr = (RBIOS8(offset) & 0x3f);
1983 uint32_t val, shift, tmp;
1984 uint32_t and_mask, or_mask;
1985
1986 offset++;
1987 switch (cmd) {
1988 case 0:
1989 val = RBIOS32(offset);
1990 offset += 4;
1991 WREG32_PLL(addr, val);
1992 break;
1993 case 1:
1994 shift = RBIOS8(offset) * 8;
1995 offset++;
1996 and_mask = RBIOS8(offset) << shift;
1997 and_mask |= ~(0xff << shift);
1998 offset++;
1999 or_mask = RBIOS8(offset) << shift;
2000 offset++;
2001 tmp = RREG32_PLL(addr);
2002 tmp &= and_mask;
2003 tmp |= or_mask;
2004 WREG32_PLL(addr, tmp);
2005 break;
2006 case 2:
2007 case 3:
2008 tmp = 1000;
2009 switch (addr) {
2010 case 1:
2011 udelay(150);
2012 break;
2013 case 2:
2014 udelay(1000);
2015 break;
2016 case 3:
2017 while (tmp--) {
2018 if (!
2019 (RREG32_PLL
2020 (RADEON_CLK_PWRMGT_CNTL) &
2021 RADEON_MC_BUSY))
2022 break;
2023 }
2024 break;
2025 case 4:
2026 while (tmp--) {
2027 if (RREG32_PLL
2028 (RADEON_CLK_PWRMGT_CNTL) &
2029 RADEON_DLL_READY)
2030 break;
2031 }
2032 break;
2033 case 5:
2034 tmp =
2035 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2036 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2037#if 0
2038 uint32_t mclk_cntl =
2039 RREG32_PLL
2040 (RADEON_MCLK_CNTL);
2041 mclk_cntl &= 0xffff0000;
2042 /*mclk_cntl |= 0x00001111;*//* ??? */
2043 WREG32_PLL(RADEON_MCLK_CNTL,
2044 mclk_cntl);
2045 udelay(10000);
2046#endif
2047 WREG32_PLL
2048 (RADEON_CLK_PWRMGT_CNTL,
2049 tmp &
2050 ~RADEON_CG_NO1_DEBUG_0);
2051 udelay(10000);
2052 }
2053 break;
2054 default:
2055 break;
2056 }
2057 break;
2058 default:
2059 break;
2060 }
2061 }
2062 }
2063}
2064
2065static void combios_parse_ram_reset_table(struct drm_device *dev,
2066 uint16_t offset)
2067{
2068 struct radeon_device *rdev = dev->dev_private;
2069 uint32_t tmp;
2070
2071 if (offset) {
2072 uint8_t val = RBIOS8(offset);
2073 while (val != 0xff) {
2074 offset++;
2075
2076 if (val == 0x0f) {
2077 uint32_t channel_complete_mask;
2078
2079 if (ASIC_IS_R300(rdev))
2080 channel_complete_mask =
2081 R300_MEM_PWRUP_COMPLETE;
2082 else
2083 channel_complete_mask =
2084 RADEON_MEM_PWRUP_COMPLETE;
2085 tmp = 20000;
2086 while (tmp--) {
2087 if ((RREG32(RADEON_MEM_STR_CNTL) &
2088 channel_complete_mask) ==
2089 channel_complete_mask)
2090 break;
2091 }
2092 } else {
2093 uint32_t or_mask = RBIOS16(offset);
2094 offset += 2;
2095
2096 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2097 tmp &= RADEON_SDRAM_MODE_MASK;
2098 tmp |= or_mask;
2099 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2100
2101 or_mask = val << 24;
2102 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2103 tmp &= RADEON_B3MEM_RESET_MASK;
2104 tmp |= or_mask;
2105 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2106 }
2107 val = RBIOS8(offset);
2108 }
2109 }
2110}
2111
2112static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2113 int mem_addr_mapping)
2114{
2115 struct radeon_device *rdev = dev->dev_private;
2116 uint32_t mem_cntl;
2117 uint32_t mem_size;
2118 uint32_t addr = 0;
2119
2120 mem_cntl = RREG32(RADEON_MEM_CNTL);
2121 if (mem_cntl & RV100_HALF_MODE)
2122 ram /= 2;
2123 mem_size = ram;
2124 mem_cntl &= ~(0xff << 8);
2125 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2126 WREG32(RADEON_MEM_CNTL, mem_cntl);
2127 RREG32(RADEON_MEM_CNTL);
2128
2129 /* sdram reset ? */
2130
2131 /* something like this???? */
2132 while (ram--) {
2133 addr = ram * 1024 * 1024;
2134 /* write to each page */
2135 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2136 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2137 /* read back and verify */
2138 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2139 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2140 return 0;
2141 }
2142
2143 return mem_size;
2144}
2145
2146static void combios_write_ram_size(struct drm_device *dev)
2147{
2148 struct radeon_device *rdev = dev->dev_private;
2149 uint8_t rev;
2150 uint16_t offset;
2151 uint32_t mem_size = 0;
2152 uint32_t mem_cntl = 0;
2153
2154 /* should do something smarter here I guess... */
2155 if (rdev->flags & RADEON_IS_IGP)
2156 return;
2157
2158 /* first check detected mem table */
2159 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2160 if (offset) {
2161 rev = RBIOS8(offset);
2162 if (rev < 3) {
2163 mem_cntl = RBIOS32(offset + 1);
2164 mem_size = RBIOS16(offset + 5);
2165 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2166 ((dev->pdev->device != 0x515e)
2167 && (dev->pdev->device != 0x5969)))
2168 WREG32(RADEON_MEM_CNTL, mem_cntl);
2169 }
2170 }
2171
2172 if (!mem_size) {
2173 offset =
2174 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2175 if (offset) {
2176 rev = RBIOS8(offset - 1);
2177 if (rev < 1) {
2178 if (((rdev->flags & RADEON_FAMILY_MASK) <
2179 CHIP_R200)
2180 && ((dev->pdev->device != 0x515e)
2181 && (dev->pdev->device != 0x5969))) {
2182 int ram = 0;
2183 int mem_addr_mapping = 0;
2184
2185 while (RBIOS8(offset)) {
2186 ram = RBIOS8(offset);
2187 mem_addr_mapping =
2188 RBIOS8(offset + 1);
2189 if (mem_addr_mapping != 0x25)
2190 ram *= 2;
2191 mem_size =
2192 combios_detect_ram(dev, ram,
2193 mem_addr_mapping);
2194 if (mem_size)
2195 break;
2196 offset += 2;
2197 }
2198 } else
2199 mem_size = RBIOS8(offset);
2200 } else {
2201 mem_size = RBIOS8(offset);
2202 mem_size *= 2; /* convert to MB */
2203 }
2204 }
2205 }
2206
2207 mem_size *= (1024 * 1024); /* convert to bytes */
2208 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2209}
2210
2211void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2212{
2213 uint16_t dyn_clk_info =
2214 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2215
2216 if (dyn_clk_info)
2217 combios_parse_pll_table(dev, dyn_clk_info);
2218}
2219
2220void radeon_combios_asic_init(struct drm_device *dev)
2221{
2222 struct radeon_device *rdev = dev->dev_private;
2223 uint16_t table;
2224
2225 /* port hardcoded mac stuff from radeonfb */
2226 if (rdev->bios == NULL)
2227 return;
2228
2229 /* ASIC INIT 1 */
2230 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2231 if (table)
2232 combios_parse_mmio_table(dev, table);
2233
2234 /* PLL INIT */
2235 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2236 if (table)
2237 combios_parse_pll_table(dev, table);
2238
2239 /* ASIC INIT 2 */
2240 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2241 if (table)
2242 combios_parse_mmio_table(dev, table);
2243
2244 if (!(rdev->flags & RADEON_IS_IGP)) {
2245 /* ASIC INIT 4 */
2246 table =
2247 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2248 if (table)
2249 combios_parse_mmio_table(dev, table);
2250
2251 /* RAM RESET */
2252 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2253 if (table)
2254 combios_parse_ram_reset_table(dev, table);
2255
2256 /* ASIC INIT 3 */
2257 table =
2258 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2259 if (table)
2260 combios_parse_mmio_table(dev, table);
2261
2262 /* write CONFIG_MEMSIZE */
2263 combios_write_ram_size(dev);
2264 }
2265
2266 /* DYN CLK 1 */
2267 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2268 if (table)
2269 combios_parse_pll_table(dev, table);
2270
2271}
2272
2273void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2274{
2275 struct radeon_device *rdev = dev->dev_private;
2276 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2277
2278 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2279 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2280 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2281
2282 /* let the bios control the backlight */
2283 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2284
2285 /* tell the bios not to handle mode switching */
2286 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2287 RADEON_ACC_MODE_CHANGE);
2288
2289 /* tell the bios a driver is loaded */
2290 bios_7_scratch |= RADEON_DRV_LOADED;
2291
2292 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2293 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2294 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2295}
2296
2297void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2298{
2299 struct drm_device *dev = encoder->dev;
2300 struct radeon_device *rdev = dev->dev_private;
2301 uint32_t bios_6_scratch;
2302
2303 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2304
2305 if (lock)
2306 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2307 else
2308 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2309
2310 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2311}
2312
2313void
2314radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2315 struct drm_encoder *encoder,
2316 bool connected)
2317{
2318 struct drm_device *dev = connector->dev;
2319 struct radeon_device *rdev = dev->dev_private;
2320 struct radeon_connector *radeon_connector =
2321 to_radeon_connector(connector);
2322 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2323 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2324 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2325
2326 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2327 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2328 if (connected) {
2329 DRM_DEBUG("TV1 connected\n");
2330 /* fix me */
2331 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2332 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2333 bios_5_scratch |= RADEON_TV1_ON;
2334 bios_5_scratch |= RADEON_ACC_REQ_TV1;
2335 } else {
2336 DRM_DEBUG("TV1 disconnected\n");
2337 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2338 bios_5_scratch &= ~RADEON_TV1_ON;
2339 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2340 }
2341 }
2342 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2343 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2344 if (connected) {
2345 DRM_DEBUG("LCD1 connected\n");
2346 bios_4_scratch |= RADEON_LCD1_ATTACHED;
2347 bios_5_scratch |= RADEON_LCD1_ON;
2348 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2349 } else {
2350 DRM_DEBUG("LCD1 disconnected\n");
2351 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2352 bios_5_scratch &= ~RADEON_LCD1_ON;
2353 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2354 }
2355 }
2356 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2357 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2358 if (connected) {
2359 DRM_DEBUG("CRT1 connected\n");
2360 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2361 bios_5_scratch |= RADEON_CRT1_ON;
2362 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2363 } else {
2364 DRM_DEBUG("CRT1 disconnected\n");
2365 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2366 bios_5_scratch &= ~RADEON_CRT1_ON;
2367 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2368 }
2369 }
2370 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2371 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2372 if (connected) {
2373 DRM_DEBUG("CRT2 connected\n");
2374 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2375 bios_5_scratch |= RADEON_CRT2_ON;
2376 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2377 } else {
2378 DRM_DEBUG("CRT2 disconnected\n");
2379 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2380 bios_5_scratch &= ~RADEON_CRT2_ON;
2381 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2382 }
2383 }
2384 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2385 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2386 if (connected) {
2387 DRM_DEBUG("DFP1 connected\n");
2388 bios_4_scratch |= RADEON_DFP1_ATTACHED;
2389 bios_5_scratch |= RADEON_DFP1_ON;
2390 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2391 } else {
2392 DRM_DEBUG("DFP1 disconnected\n");
2393 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2394 bios_5_scratch &= ~RADEON_DFP1_ON;
2395 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2396 }
2397 }
2398 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2399 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2400 if (connected) {
2401 DRM_DEBUG("DFP2 connected\n");
2402 bios_4_scratch |= RADEON_DFP2_ATTACHED;
2403 bios_5_scratch |= RADEON_DFP2_ON;
2404 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2405 } else {
2406 DRM_DEBUG("DFP2 disconnected\n");
2407 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2408 bios_5_scratch &= ~RADEON_DFP2_ON;
2409 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2410 }
2411 }
2412 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2413 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2414}
2415
2416void
2417radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2418{
2419 struct drm_device *dev = encoder->dev;
2420 struct radeon_device *rdev = dev->dev_private;
2421 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2422 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2423
2424 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2425 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2426 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
2427 }
2428 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2429 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
2430 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
2431 }
2432 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2433 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
2434 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
2435 }
2436 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2437 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
2438 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
2439 }
2440 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2441 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
2442 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
2443 }
2444 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2445 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
2446 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
2447 }
2448 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2449}
2450
2451void
2452radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2453{
2454 struct drm_device *dev = encoder->dev;
2455 struct radeon_device *rdev = dev->dev_private;
2456 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2457 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2458
2459 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
2460 if (on)
2461 bios_6_scratch |= RADEON_TV_DPMS_ON;
2462 else
2463 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
2464 }
2465 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2466 if (on)
2467 bios_6_scratch |= RADEON_CRT_DPMS_ON;
2468 else
2469 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
2470 }
2471 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2472 if (on)
2473 bios_6_scratch |= RADEON_LCD_DPMS_ON;
2474 else
2475 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
2476 }
2477 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
2478 if (on)
2479 bios_6_scratch |= RADEON_DFP_DPMS_ON;
2480 else
2481 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
2482 }
2483 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2484}
Linux 6.x block layer and io_uring tree(s)