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Merge branches 'amd-iommu/fixes' and 'dma-debug/fixes' into iommu/fixes
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_combios.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33/* not sure which of these are needed */
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif /* CONFIG_PPC_PMAC */
39
40/* from radeon_encoder.c */
41extern uint32_t
42radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46/* from radeon_connector.c */
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
b75fad06 52 struct radeon_i2c_bus_rec *i2c_bus,
eed45b30
AD		 53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
771fe6b9
JG		 55
56/* from radeon_legacy_encoder.c */
57extern void
58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
59 uint32_t supported_device);
60
61/* old legacy ATI BIOS routines */
62
63/* COMBIOS table offsets */
64enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
153 switch (table) {
154 /* absolute offset tables */
155 case COMBIOS_ASIC_INIT_1_TABLE:
156 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
157 if (check_offset)
158 offset = check_offset;
159 break;
160 case COMBIOS_BIOS_SUPPORT_TABLE:
161 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
162 if (check_offset)
163 offset = check_offset;
164 break;
165 case COMBIOS_DAC_PROGRAMMING_TABLE:
166 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
167 if (check_offset)
168 offset = check_offset;
169 break;
170 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
171 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
172 if (check_offset)
173 offset = check_offset;
174 break;
175 case COMBIOS_CRTC_INFO_TABLE:
176 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
177 if (check_offset)
178 offset = check_offset;
179 break;
180 case COMBIOS_PLL_INFO_TABLE:
181 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
182 if (check_offset)
183 offset = check_offset;
184 break;
185 case COMBIOS_TV_INFO_TABLE:
186 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
187 if (check_offset)
188 offset = check_offset;
189 break;
190 case COMBIOS_DFP_INFO_TABLE:
191 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
192 if (check_offset)
193 offset = check_offset;
194 break;
195 case COMBIOS_HW_CONFIG_INFO_TABLE:
196 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
197 if (check_offset)
198 offset = check_offset;
199 break;
200 case COMBIOS_MULTIMEDIA_INFO_TABLE:
201 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
202 if (check_offset)
203 offset = check_offset;
204 break;
205 case COMBIOS_TV_STD_PATCH_TABLE:
206 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
207 if (check_offset)
208 offset = check_offset;
209 break;
210 case COMBIOS_LCD_INFO_TABLE:
211 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
212 if (check_offset)
213 offset = check_offset;
214 break;
215 case COMBIOS_MOBILE_INFO_TABLE:
216 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
217 if (check_offset)
218 offset = check_offset;
219 break;
220 case COMBIOS_PLL_INIT_TABLE:
221 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
222 if (check_offset)
223 offset = check_offset;
224 break;
225 case COMBIOS_MEM_CONFIG_TABLE:
226 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
227 if (check_offset)
228 offset = check_offset;
229 break;
230 case COMBIOS_SAVE_MASK_TABLE:
231 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
232 if (check_offset)
233 offset = check_offset;
234 break;
235 case COMBIOS_HARDCODED_EDID_TABLE:
236 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
237 if (check_offset)
238 offset = check_offset;
239 break;
240 case COMBIOS_ASIC_INIT_2_TABLE:
241 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
242 if (check_offset)
243 offset = check_offset;
244 break;
245 case COMBIOS_CONNECTOR_INFO_TABLE:
246 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
247 if (check_offset)
248 offset = check_offset;
249 break;
250 case COMBIOS_DYN_CLK_1_TABLE:
251 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
252 if (check_offset)
253 offset = check_offset;
254 break;
255 case COMBIOS_RESERVED_MEM_TABLE:
256 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
257 if (check_offset)
258 offset = check_offset;
259 break;
260 case COMBIOS_EXT_TMDS_INFO_TABLE:
261 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
262 if (check_offset)
263 offset = check_offset;
264 break;
265 case COMBIOS_MEM_CLK_INFO_TABLE:
266 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
267 if (check_offset)
268 offset = check_offset;
269 break;
270 case COMBIOS_EXT_DAC_INFO_TABLE:
271 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
272 if (check_offset)
273 offset = check_offset;
274 break;
275 case COMBIOS_MISC_INFO_TABLE:
276 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
277 if (check_offset)
278 offset = check_offset;
279 break;
280 case COMBIOS_CRT_INFO_TABLE:
281 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
282 if (check_offset)
283 offset = check_offset;
284 break;
285 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
286 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
287 if (check_offset)
288 offset = check_offset;
289 break;
290 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
291 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
292 if (check_offset)
293 offset = check_offset;
294 break;
295 case COMBIOS_FAN_SPEED_INFO_TABLE:
296 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
297 if (check_offset)
298 offset = check_offset;
299 break;
300 case COMBIOS_OVERDRIVE_INFO_TABLE:
301 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
302 if (check_offset)
303 offset = check_offset;
304 break;
305 case COMBIOS_OEM_INFO_TABLE:
306 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
307 if (check_offset)
308 offset = check_offset;
309 break;
310 case COMBIOS_DYN_CLK_2_TABLE:
311 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
312 if (check_offset)
313 offset = check_offset;
314 break;
315 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
316 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
317 if (check_offset)
318 offset = check_offset;
319 break;
320 case COMBIOS_I2C_INFO_TABLE:
321 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
322 if (check_offset)
323 offset = check_offset;
324 break;
325 /* relative offset tables */
326 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
327 check_offset =
328 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
329 if (check_offset) {
330 rev = RBIOS8(check_offset);
331 if (rev > 0) {
332 check_offset = RBIOS16(check_offset + 0x3);
333 if (check_offset)
334 offset = check_offset;
335 }
336 }
337 break;
338 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
339 check_offset =
340 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
341 if (check_offset) {
342 rev = RBIOS8(check_offset);
343 if (rev > 0) {
344 check_offset = RBIOS16(check_offset + 0x5);
345 if (check_offset)
346 offset = check_offset;
347 }
348 }
349 break;
350 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
351 check_offset =
352 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
353 if (check_offset) {
354 rev = RBIOS8(check_offset);
355 if (rev > 0) {
356 check_offset = RBIOS16(check_offset + 0x7);
357 if (check_offset)
358 offset = check_offset;
359 }
360 }
361 break;
362 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
363 check_offset =
364 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
365 if (check_offset) {
366 rev = RBIOS8(check_offset);
367 if (rev == 2) {
368 check_offset = RBIOS16(check_offset + 0x9);
369 if (check_offset)
370 offset = check_offset;
371 }
372 }
373 break;
374 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
375 check_offset =
376 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
377 if (check_offset) {
378 while (RBIOS8(check_offset++));
379 check_offset += 2;
380 if (check_offset)
381 offset = check_offset;
382 }
383 break;
384 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
385 check_offset =
386 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
387 if (check_offset) {
388 check_offset = RBIOS16(check_offset + 0x11);
389 if (check_offset)
390 offset = check_offset;
391 }
392 break;
393 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
394 check_offset =
395 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
396 if (check_offset) {
397 check_offset = RBIOS16(check_offset + 0x13);
398 if (check_offset)
399 offset = check_offset;
400 }
401 break;
402 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
403 check_offset =
404 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
405 if (check_offset) {
406 check_offset = RBIOS16(check_offset + 0x15);
407 if (check_offset)
408 offset = check_offset;
409 }
410 break;
411 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
412 check_offset =
413 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
414 if (check_offset) {
415 check_offset = RBIOS16(check_offset + 0x17);
416 if (check_offset)
417 offset = check_offset;
418 }
419 break;
420 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
421 check_offset =
422 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
423 if (check_offset) {
424 check_offset = RBIOS16(check_offset + 0x2);
425 if (check_offset)
426 offset = check_offset;
427 }
428 break;
429 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
430 check_offset =
431 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
432 if (check_offset) {
433 check_offset = RBIOS16(check_offset + 0x4);
434 if (check_offset)
435 offset = check_offset;
436 }
437 break;
438 default:
439 break;
440 }
441
442 return offset;
443
444}
445
6a93cb25
AD		 446static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
447 int ddc_line)
771fe6b9
JG		 448{
449 struct radeon_i2c_bus_rec i2c;
450
6a93cb25
AD		 451 if (ddc_line == RADEON_GPIOPAD_MASK) {
452 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
453 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
454 i2c.a_clk_reg = RADEON_GPIOPAD_A;
455 i2c.a_data_reg = RADEON_GPIOPAD_A;
456 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
457 i2c.en_data_reg = RADEON_GPIOPAD_EN;
458 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
459 i2c.y_data_reg = RADEON_GPIOPAD_Y;
460 } else if (ddc_line == RADEON_MDGPIO_MASK) {
461 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
462 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
463 i2c.a_clk_reg = RADEON_MDGPIO_A;
464 i2c.a_data_reg = RADEON_MDGPIO_A;
465 i2c.en_clk_reg = RADEON_MDGPIO_EN;
466 i2c.en_data_reg = RADEON_MDGPIO_EN;
467 i2c.y_clk_reg = RADEON_MDGPIO_Y;
468 i2c.y_data_reg = RADEON_MDGPIO_Y;
771fe6b9 469 } else {
6a93cb25
AD		 470 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
471 i2c.mask_data_mask = RADEON_GPIO_EN_0;
472 i2c.a_clk_mask = RADEON_GPIO_A_1;
473 i2c.a_data_mask = RADEON_GPIO_A_0;
474 i2c.en_clk_mask = RADEON_GPIO_EN_1;
475 i2c.en_data_mask = RADEON_GPIO_EN_0;
476 i2c.y_clk_mask = RADEON_GPIO_Y_1;
477 i2c.y_data_mask = RADEON_GPIO_Y_0;
478
771fe6b9
JG		 479 i2c.mask_clk_reg = ddc_line;
480 i2c.mask_data_reg = ddc_line;
481 i2c.a_clk_reg = ddc_line;
482 i2c.a_data_reg = ddc_line;
9b9fe724
AD		 483 i2c.en_clk_reg = ddc_line;
484 i2c.en_data_reg = ddc_line;
485 i2c.y_clk_reg = ddc_line;
486 i2c.y_data_reg = ddc_line;
771fe6b9
JG		 487 }
488
6a93cb25
AD		 489 if (rdev->family < CHIP_R200)
490 i2c.hw_capable = false;
491 else {
492 switch (ddc_line) {
493 case RADEON_GPIO_VGA_DDC:
494 case RADEON_GPIO_DVI_DDC:
495 i2c.hw_capable = true;
496 break;
497 case RADEON_GPIO_MONID:
498 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
499 * reliably on some pre-r4xx hardware; not sure why.
500 */
501 i2c.hw_capable = false;
502 break;
503 default:
504 i2c.hw_capable = false;
505 break;
506 }
507 }
508 i2c.mm_i2c = false;
509 i2c.i2c_id = 0;
510
771fe6b9
JG		 511 if (ddc_line)
512 i2c.valid = true;
513 else
514 i2c.valid = false;
515
516 return i2c;
517}
518
519bool radeon_combios_get_clock_info(struct drm_device *dev)
520{
521 struct radeon_device *rdev = dev->dev_private;
522 uint16_t pll_info;
523 struct radeon_pll *p1pll = &rdev->clock.p1pll;
524 struct radeon_pll *p2pll = &rdev->clock.p2pll;
525 struct radeon_pll *spll = &rdev->clock.spll;
526 struct radeon_pll *mpll = &rdev->clock.mpll;
527 int8_t rev;
528 uint16_t sclk, mclk;
529
530 if (rdev->bios == NULL)
4b30b870 531 return false;
771fe6b9
JG		 532
533 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
534 if (pll_info) {
535 rev = RBIOS8(pll_info);
536
537 /* pixel clocks */
538 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
539 p1pll->reference_div = RBIOS16(pll_info + 0x10);
540 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
541 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
542
543 if (rev > 9) {
544 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
545 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
546 } else {
547 p1pll->pll_in_min = 40;
548 p1pll->pll_in_max = 500;
549 }
550 *p2pll = *p1pll;
551
552 /* system clock */
553 spll->reference_freq = RBIOS16(pll_info + 0x1a);
554 spll->reference_div = RBIOS16(pll_info + 0x1c);
555 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
556 spll->pll_out_max = RBIOS32(pll_info + 0x22);
557
558 if (rev > 10) {
559 spll->pll_in_min = RBIOS32(pll_info + 0x48);
560 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
561 } else {
562 /* ??? */
563 spll->pll_in_min = 40;
564 spll->pll_in_max = 500;
565 }
566
567 /* memory clock */
568 mpll->reference_freq = RBIOS16(pll_info + 0x26);
569 mpll->reference_div = RBIOS16(pll_info + 0x28);
570 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
571 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
572
573 if (rev > 10) {
574 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
575 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
576 } else {
577 /* ??? */
578 mpll->pll_in_min = 40;
579 mpll->pll_in_max = 500;
580 }
581
582 /* default sclk/mclk */
583 sclk = RBIOS16(pll_info + 0xa);
584 mclk = RBIOS16(pll_info + 0x8);
585 if (sclk == 0)
586 sclk = 200 * 100;
587 if (mclk == 0)
588 mclk = 200 * 100;
589
590 rdev->clock.default_sclk = sclk;
591 rdev->clock.default_mclk = mclk;
592
593 return true;
594 }
595 return false;
596}
597
06b6476d
AD		 598bool radeon_combios_sideport_present(struct radeon_device *rdev)
599{
600 struct drm_device *dev = rdev->ddev;
601 u16 igp_info;
602
603 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
604
605 if (igp_info) {
606 if (RBIOS16(igp_info + 0x4))
607 return true;
608 }
609 return false;
610}
611
246263cc
AD		 612static const uint32_t default_primarydac_adj[CHIP_LAST] = {
613 0x00000808, /* r100 */
614 0x00000808, /* rv100 */
615 0x00000808, /* rs100 */
616 0x00000808, /* rv200 */
617 0x00000808, /* rs200 */
618 0x00000808, /* r200 */
619 0x00000808, /* rv250 */
620 0x00000000, /* rs300 */
621 0x00000808, /* rv280 */
622 0x00000808, /* r300 */
623 0x00000808, /* r350 */
624 0x00000808, /* rv350 */
625 0x00000808, /* rv380 */
626 0x00000808, /* r420 */
627 0x00000808, /* r423 */
628 0x00000808, /* rv410 */
629 0x00000000, /* rs400 */
630 0x00000000, /* rs480 */
631};
632
633static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
634 struct radeon_encoder_primary_dac *p_dac)
635{
636 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
637 return;
638}
639
771fe6b9
JG		 640struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
641 radeon_encoder
642 *encoder)
643{
644 struct drm_device *dev = encoder->base.dev;
645 struct radeon_device *rdev = dev->dev_private;
646 uint16_t dac_info;
647 uint8_t rev, bg, dac;
648 struct radeon_encoder_primary_dac *p_dac = NULL;
246263cc 649 int found = 0;
771fe6b9 650
246263cc
AD		 651 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
652 GFP_KERNEL);
653
654 if (!p_dac)
771fe6b9
JG		 655 return NULL;
656
246263cc
AD		 657 if (rdev->bios == NULL)
658 goto out;
659
771fe6b9
JG		 660 /* check CRT table */
661 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
662 if (dac_info) {
771fe6b9
JG		 663 rev = RBIOS8(dac_info) & 0x3;
664 if (rev < 2) {
665 bg = RBIOS8(dac_info + 0x2) & 0xf;
666 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
667 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
668 } else {
669 bg = RBIOS8(dac_info + 0x2) & 0xf;
670 dac = RBIOS8(dac_info + 0x3) & 0xf;
671 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
672 }
246263cc 673 found = 1;
771fe6b9
JG		 674 }
675
246263cc
AD		 676out:
677 if (!found) /* fallback to defaults */
678 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
679
771fe6b9
JG		 680 return p_dac;
681}
682
d79766fa
AD		 683enum radeon_tv_std
684radeon_combios_get_tv_info(struct radeon_device *rdev)
771fe6b9 685{
d79766fa 686 struct drm_device *dev = rdev->ddev;
771fe6b9
JG		 687 uint16_t tv_info;
688 enum radeon_tv_std tv_std = TV_STD_NTSC;
689
11f3b59e
MD		 690 if (rdev->bios == NULL)
691 return tv_std;
692
771fe6b9
JG		 693 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
694 if (tv_info) {
695 if (RBIOS8(tv_info + 6) == 'T') {
696 switch (RBIOS8(tv_info + 7) & 0xf) {
697 case 1:
698 tv_std = TV_STD_NTSC;
699 DRM_INFO("Default TV standard: NTSC\n");
700 break;
701 case 2:
702 tv_std = TV_STD_PAL;
703 DRM_INFO("Default TV standard: PAL\n");
704 break;
705 case 3:
706 tv_std = TV_STD_PAL_M;
707 DRM_INFO("Default TV standard: PAL-M\n");
708 break;
709 case 4:
710 tv_std = TV_STD_PAL_60;
711 DRM_INFO("Default TV standard: PAL-60\n");
712 break;
713 case 5:
714 tv_std = TV_STD_NTSC_J;
715 DRM_INFO("Default TV standard: NTSC-J\n");
716 break;
717 case 6:
718 tv_std = TV_STD_SCART_PAL;
719 DRM_INFO("Default TV standard: SCART-PAL\n");
720 break;
721 default:
722 tv_std = TV_STD_NTSC;
723 DRM_INFO
724 ("Unknown TV standard; defaulting to NTSC\n");
725 break;
726 }
727
728 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
729 case 0:
730 DRM_INFO("29.498928713 MHz TV ref clk\n");
731 break;
732 case 1:
733 DRM_INFO("28.636360000 MHz TV ref clk\n");
734 break;
735 case 2:
736 DRM_INFO("14.318180000 MHz TV ref clk\n");
737 break;
738 case 3:
739 DRM_INFO("27.000000000 MHz TV ref clk\n");
740 break;
741 default:
742 break;
743 }
744 }
745 }
746 return tv_std;
747}
748
749static const uint32_t default_tvdac_adj[CHIP_LAST] = {
750 0x00000000, /* r100 */
751 0x00280000, /* rv100 */
752 0x00000000, /* rs100 */
753 0x00880000, /* rv200 */
754 0x00000000, /* rs200 */
755 0x00000000, /* r200 */
756 0x00770000, /* rv250 */
757 0x00290000, /* rs300 */
758 0x00560000, /* rv280 */
759 0x00780000, /* r300 */
760 0x00770000, /* r350 */
761 0x00780000, /* rv350 */
762 0x00780000, /* rv380 */
763 0x01080000, /* r420 */
764 0x01080000, /* r423 */
765 0x01080000, /* rv410 */
766 0x00780000, /* rs400 */
767 0x00780000, /* rs480 */
768};
769
6a719e05
DA		 770static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
771 struct radeon_encoder_tv_dac *tv_dac)
771fe6b9 772{
771fe6b9
JG		 773 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
774 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
775 tv_dac->ps2_tvdac_adj = 0x00880000;
776 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
777 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 778 return;
771fe6b9
JG		 779}
780
781struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
782 radeon_encoder
783 *encoder)
784{
785 struct drm_device *dev = encoder->base.dev;
786 struct radeon_device *rdev = dev->dev_private;
787 uint16_t dac_info;
788 uint8_t rev, bg, dac;
789 struct radeon_encoder_tv_dac *tv_dac = NULL;
6a719e05
DA		 790 int found = 0;
791
792 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
793 if (!tv_dac)
794 return NULL;
771fe6b9
JG		 795
796 if (rdev->bios == NULL)
6a719e05 797 goto out;
771fe6b9
JG		 798
799 /* first check TV table */
800 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
801 if (dac_info) {
771fe6b9
JG		 802 rev = RBIOS8(dac_info + 0x3);
803 if (rev > 4) {
804 bg = RBIOS8(dac_info + 0xc) & 0xf;
805 dac = RBIOS8(dac_info + 0xd) & 0xf;
806 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
807
808 bg = RBIOS8(dac_info + 0xe) & 0xf;
809 dac = RBIOS8(dac_info + 0xf) & 0xf;
810 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
811
812 bg = RBIOS8(dac_info + 0x10) & 0xf;
813 dac = RBIOS8(dac_info + 0x11) & 0xf;
814 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 815 found = 1;
771fe6b9
JG		 816 } else if (rev > 1) {
817 bg = RBIOS8(dac_info + 0xc) & 0xf;
818 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
819 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
820
821 bg = RBIOS8(dac_info + 0xd) & 0xf;
822 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
823 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
824
825 bg = RBIOS8(dac_info + 0xe) & 0xf;
826 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
827 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
6a719e05 828 found = 1;
771fe6b9 829 }
d79766fa 830 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
6a719e05
DA		 831 }
832 if (!found) {
771fe6b9
JG		 833 /* then check CRT table */
834 dac_info =
835 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
836 if (dac_info) {
771fe6b9
JG		 837 rev = RBIOS8(dac_info) & 0x3;
838 if (rev < 2) {
839 bg = RBIOS8(dac_info + 0x3) & 0xf;
840 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
841 tv_dac->ps2_tvdac_adj =
842 (bg << 16) | (dac << 20);
843 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
844 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 845 found = 1;
771fe6b9
JG		 846 } else {
847 bg = RBIOS8(dac_info + 0x4) & 0xf;
848 dac = RBIOS8(dac_info + 0x5) & 0xf;
849 tv_dac->ps2_tvdac_adj =
850 (bg << 16) | (dac << 20);
851 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
852 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
6a719e05 853 found = 1;
771fe6b9 854 }
6fe7ac3f
AD		 855 } else {
856 DRM_INFO("No TV DAC info found in BIOS\n");
771fe6b9
JG		 857 }
858 }
859
6a719e05
DA		 860out:
861 if (!found) /* fallback to defaults */
862 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
863
771fe6b9
JG		 864 return tv_dac;
865}
866
867static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
868 radeon_device
869 *rdev)
870{
871 struct radeon_encoder_lvds *lvds = NULL;
872 uint32_t fp_vert_stretch, fp_horz_stretch;
873 uint32_t ppll_div_sel, ppll_val;
8b5c7444 874 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
771fe6b9
JG		 875
876 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
877
878 if (!lvds)
879 return NULL;
880
881 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
882 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
883
8b5c7444
MD		 884 /* These should be fail-safe defaults, fingers crossed */
885 lvds->panel_pwr_delay = 200;
886 lvds->panel_vcc_delay = 2000;
887
888 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
889 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
890 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
891
771fe6b9 892 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
de2103e4 893 lvds->native_mode.vdisplay =
771fe6b9
JG		 894 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
895 RADEON_VERT_PANEL_SHIFT) + 1;
896 else
de2103e4 897 lvds->native_mode.vdisplay =
771fe6b9
JG		 898 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
899
900 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
de2103e4 901 lvds->native_mode.hdisplay =
771fe6b9
JG		 902 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
903 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
904 else
de2103e4 905 lvds->native_mode.hdisplay =
771fe6b9
JG		 906 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
907
de2103e4
AD		 908 if ((lvds->native_mode.hdisplay < 640) ||
909 (lvds->native_mode.vdisplay < 480)) {
910 lvds->native_mode.hdisplay = 640;
911 lvds->native_mode.vdisplay = 480;
771fe6b9
JG		 912 }
913
914 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
915 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
916 if ((ppll_val & 0x000707ff) == 0x1bb)
917 lvds->use_bios_dividers = false;
918 else {
919 lvds->panel_ref_divider =
920 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
921 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
922 lvds->panel_fb_divider = ppll_val & 0x7ff;
923
924 if ((lvds->panel_ref_divider != 0) &&
925 (lvds->panel_fb_divider > 3))
926 lvds->use_bios_dividers = true;
927 }
928 lvds->panel_vcc_delay = 200;
929
930 DRM_INFO("Panel info derived from registers\n");
de2103e4
AD		 931 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
932 lvds->native_mode.vdisplay);
771fe6b9
JG		 933
934 return lvds;
935}
936
937struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
938 *encoder)
939{
940 struct drm_device *dev = encoder->base.dev;
941 struct radeon_device *rdev = dev->dev_private;
942 uint16_t lcd_info;
943 uint32_t panel_setup;
944 char stmp[30];
945 int tmp, i;
946 struct radeon_encoder_lvds *lvds = NULL;
947
8dfaa8a7
MD		 948 if (rdev->bios == NULL) {
949 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
950 goto out;
951 }
771fe6b9
JG		 952
953 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
954
955 if (lcd_info) {
956 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
957
958 if (!lvds)
959 return NULL;
960
961 for (i = 0; i < 24; i++)
962 stmp[i] = RBIOS8(lcd_info + i + 1);
963 stmp[24] = 0;
964
965 DRM_INFO("Panel ID String: %s\n", stmp);
966
de2103e4
AD		 967 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
968 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
771fe6b9 969
de2103e4
AD		 970 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
971 lvds->native_mode.vdisplay);
771fe6b9
JG		 972
973 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
974 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
975 lvds->panel_vcc_delay = 2000;
976
977 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
978 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
979 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
980
981 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
982 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
983 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
984 if ((lvds->panel_ref_divider != 0) &&
985 (lvds->panel_fb_divider > 3))
986 lvds->use_bios_dividers = true;
987
988 panel_setup = RBIOS32(lcd_info + 0x39);
989 lvds->lvds_gen_cntl = 0xff00;
990 if (panel_setup & 0x1)
991 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
992
993 if ((panel_setup >> 4) & 0x1)
994 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
995
996 switch ((panel_setup >> 8) & 0x7) {
997 case 0:
998 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
999 break;
1000 case 1:
1001 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1002 break;
1003 case 2:
1004 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1005 break;
1006 default:
1007 break;
1008 }
1009
1010 if ((panel_setup >> 16) & 0x1)
1011 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1012
1013 if ((panel_setup >> 17) & 0x1)
1014 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1015
1016 if ((panel_setup >> 18) & 0x1)
1017 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1018
1019 if ((panel_setup >> 23) & 0x1)
1020 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1021
1022 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1023
1024 for (i = 0; i < 32; i++) {
1025 tmp = RBIOS16(lcd_info + 64 + i * 2);
1026 if (tmp == 0)
1027 break;
1028
de2103e4 1029 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
771fe6b9 1030 (RBIOS16(tmp + 2) ==
de2103e4
AD		 1031 lvds->native_mode.vdisplay)) {
1032 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1033 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1034 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1035 RBIOS16(tmp + 21)) * 8;
1036
1037 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1038 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1039 lvds->native_mode.vsync_end =
1040 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1041 (RBIOS16(tmp + 28) & 0x7ff);
1042
1043 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
771fe6b9 1044 lvds->native_mode.flags = 0;
de2103e4
AD		 1045 /* set crtc values */
1046 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1047
771fe6b9
JG		 1048 }
1049 }
6fe7ac3f 1050 } else {
771fe6b9 1051 DRM_INFO("No panel info found in BIOS\n");
8dfaa8a7 1052 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
6fe7ac3f 1053 }
8dfaa8a7
MD		 1054out:
1055 if (lvds)
1056 encoder->native_mode = lvds->native_mode;
771fe6b9
JG		 1057 return lvds;
1058}
1059
1060static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1061 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1062 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1063 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1064 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1065 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1066 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1067 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1068 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1069 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1070 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1071 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1072 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1073 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1074 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1075 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1076 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
fcec570b
AD		 1077 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1078 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
771fe6b9
JG		 1079};
1080
445282db
DA		 1081bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1082 struct radeon_encoder_int_tmds *tmds)
771fe6b9 1083{
445282db
DA		 1084 struct drm_device *dev = encoder->base.dev;
1085 struct radeon_device *rdev = dev->dev_private;
771fe6b9 1086 int i;
771fe6b9
JG		 1087
1088 for (i = 0; i < 4; i++) {
1089 tmds->tmds_pll[i].value =
445282db 1090 default_tmds_pll[rdev->family][i].value;
771fe6b9
JG		 1091 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1092 }
1093
445282db 1094 return true;
771fe6b9
JG		 1095}
1096
445282db
DA		 1097bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1098 struct radeon_encoder_int_tmds *tmds)
771fe6b9
JG		 1099{
1100 struct drm_device *dev = encoder->base.dev;
1101 struct radeon_device *rdev = dev->dev_private;
1102 uint16_t tmds_info;
1103 int i, n;
1104 uint8_t ver;
771fe6b9
JG		 1105
1106 if (rdev->bios == NULL)
445282db 1107 return false;
771fe6b9
JG		 1108
1109 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1110
1111 if (tmds_info) {
771fe6b9
JG		 1112 ver = RBIOS8(tmds_info);
1113 DRM_INFO("DFP table revision: %d\n", ver);
1114 if (ver == 3) {
1115 n = RBIOS8(tmds_info + 5) + 1;
1116 if (n > 4)
1117 n = 4;
1118 for (i = 0; i < n; i++) {
1119 tmds->tmds_pll[i].value =
1120 RBIOS32(tmds_info + i * 10 + 0x08);
1121 tmds->tmds_pll[i].freq =
1122 RBIOS16(tmds_info + i * 10 + 0x10);
1123 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1124 tmds->tmds_pll[i].freq,
1125 tmds->tmds_pll[i].value);
1126 }
1127 } else if (ver == 4) {
1128 int stride = 0;
1129 n = RBIOS8(tmds_info + 5) + 1;
1130 if (n > 4)
1131 n = 4;
1132 for (i = 0; i < n; i++) {
1133 tmds->tmds_pll[i].value =
1134 RBIOS32(tmds_info + stride + 0x08);
1135 tmds->tmds_pll[i].freq =
1136 RBIOS16(tmds_info + stride + 0x10);
1137 if (i == 0)
1138 stride += 10;
1139 else
1140 stride += 6;
1141 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1142 tmds->tmds_pll[i].freq,
1143 tmds->tmds_pll[i].value);
1144 }
1145 }
fcec570b 1146 } else {
771fe6b9 1147 DRM_INFO("No TMDS info found in BIOS\n");
fcec570b
AD		 1148 return false;
1149 }
445282db
DA		 1150 return true;
1151}
1152
fcec570b
AD		 1153bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1154 struct radeon_encoder_ext_tmds *tmds)
445282db 1155{
fcec570b
AD		 1156 struct drm_device *dev = encoder->base.dev;
1157 struct radeon_device *rdev = dev->dev_private;
1158 struct radeon_i2c_bus_rec i2c_bus;
445282db 1159
fcec570b 1160 /* default for macs */
6a93cb25 1161 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1162 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
445282db 1163
fcec570b
AD		 1164 /* XXX some macs have duallink chips */
1165 switch (rdev->mode_info.connector_table) {
1166 case CT_POWERBOOK_EXTERNAL:
1167 case CT_MINI_EXTERNAL:
1168 default:
1169 tmds->dvo_chip = DVO_SIL164;
1170 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1171 break;
1172 }
445282db 1173
fcec570b 1174 return true;
771fe6b9
JG		 1175}
1176
fcec570b
AD		 1177bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1178 struct radeon_encoder_ext_tmds *tmds)
771fe6b9
JG		 1179{
1180 struct drm_device *dev = encoder->base.dev;
1181 struct radeon_device *rdev = dev->dev_private;
fcec570b
AD		 1182 uint16_t offset;
1183 uint8_t ver, id, blocks, clk, data;
1184 int i;
1185 enum radeon_combios_ddc gpio;
1186 struct radeon_i2c_bus_rec i2c_bus;
771fe6b9
JG		 1187
1188 if (rdev->bios == NULL)
fcec570b 1189 return false;
771fe6b9 1190
fcec570b
AD		 1191 tmds->i2c_bus = NULL;
1192 if (rdev->flags & RADEON_IS_IGP) {
1193 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1194 if (offset) {
1195 ver = RBIOS8(offset);
1196 DRM_INFO("GPIO Table revision: %d\n", ver);
1197 blocks = RBIOS8(offset + 2);
1198 for (i = 0; i < blocks; i++) {
1199 id = RBIOS8(offset + 3 + (i * 5) + 0);
1200 if (id == 136) {
1201 clk = RBIOS8(offset + 3 + (i * 5) + 3);
1202 data = RBIOS8(offset + 3 + (i * 5) + 4);
1203 i2c_bus.valid = true;
1204 i2c_bus.mask_clk_mask = (1 << clk);
1205 i2c_bus.mask_data_mask = (1 << data);
1206 i2c_bus.a_clk_mask = (1 << clk);
1207 i2c_bus.a_data_mask = (1 << data);
1208 i2c_bus.en_clk_mask = (1 << clk);
1209 i2c_bus.en_data_mask = (1 << data);
1210 i2c_bus.y_clk_mask = (1 << clk);
1211 i2c_bus.y_data_mask = (1 << data);
1212 i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1213 i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1214 i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1215 i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1216 i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1217 i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1218 i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1219 i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1220 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1221 tmds->dvo_chip = DVO_SIL164;
1222 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1223 break;
1224 }
1225 }
1226 }
1227 } else {
1228 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1229 if (offset) {
1230 ver = RBIOS8(offset);
1231 DRM_INFO("External TMDS Table revision: %d\n", ver);
1232 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1233 tmds->slave_addr >>= 1; /* 7 bit addressing */
1234 gpio = RBIOS8(offset + 4 + 3);
1235 switch (gpio) {
1236 case DDC_MONID:
6a93cb25 1237 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b
AD		 1238 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1239 break;
1240 case DDC_DVI:
6a93cb25 1241 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b
AD		 1242 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1243 break;
1244 case DDC_VGA:
6a93cb25 1245 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
fcec570b
AD		 1246 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1247 break;
1248 case DDC_CRT2:
1249 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1250 if (rdev->family >= CHIP_R300)
6a93cb25 1251 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
fcec570b 1252 else
6a93cb25 1253 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
fcec570b
AD		 1254 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1255 break;
1256 case DDC_LCD: /* MM i2c */
1257 DRM_ERROR("MM i2c requires hw i2c engine\n");
1258 break;
1259 default:
1260 DRM_ERROR("Unsupported gpio %d\n", gpio);
1261 break;
1262 }
1263 }
771fe6b9 1264 }
fcec570b
AD		 1265
1266 if (!tmds->i2c_bus) {
1267 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1268 return false;
1269 }
1270
1271 return true;
771fe6b9
JG		 1272}
1273
1274bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1275{
1276 struct radeon_device *rdev = dev->dev_private;
1277 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1278 struct radeon_hpd hpd;
771fe6b9
JG		 1279
1280 rdev->mode_info.connector_table = radeon_connector_table;
1281 if (rdev->mode_info.connector_table == CT_NONE) {
1282#ifdef CONFIG_PPC_PMAC
1283 if (machine_is_compatible("PowerBook3,3")) {
1284 /* powerbook with VGA */
1285 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1286 } else if (machine_is_compatible("PowerBook3,4") ||
1287 machine_is_compatible("PowerBook3,5")) {
1288 /* powerbook with internal tmds */
1289 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1290 } else if (machine_is_compatible("PowerBook5,1") ||
1291 machine_is_compatible("PowerBook5,2") ||
1292 machine_is_compatible("PowerBook5,3") ||
1293 machine_is_compatible("PowerBook5,4") ||
1294 machine_is_compatible("PowerBook5,5")) {
1295 /* powerbook with external single link tmds (sil164) */
1296 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1297 } else if (machine_is_compatible("PowerBook5,6")) {
1298 /* powerbook with external dual or single link tmds */
1299 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1300 } else if (machine_is_compatible("PowerBook5,7") ||
1301 machine_is_compatible("PowerBook5,8") ||
1302 machine_is_compatible("PowerBook5,9")) {
1303 /* PowerBook6,2 ? */
1304 /* powerbook with external dual link tmds (sil1178?) */
1305 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1306 } else if (machine_is_compatible("PowerBook4,1") ||
1307 machine_is_compatible("PowerBook4,2") ||
1308 machine_is_compatible("PowerBook4,3") ||
1309 machine_is_compatible("PowerBook6,3") ||
1310 machine_is_compatible("PowerBook6,5") ||
1311 machine_is_compatible("PowerBook6,7")) {
1312 /* ibook */
1313 rdev->mode_info.connector_table = CT_IBOOK;
1314 } else if (machine_is_compatible("PowerMac4,4")) {
1315 /* emac */
1316 rdev->mode_info.connector_table = CT_EMAC;
1317 } else if (machine_is_compatible("PowerMac10,1")) {
1318 /* mini with internal tmds */
1319 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1320 } else if (machine_is_compatible("PowerMac10,2")) {
1321 /* mini with external tmds */
1322 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1323 } else if (machine_is_compatible("PowerMac12,1")) {
1324 /* PowerMac8,1 ? */
1325 /* imac g5 isight */
1326 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1327 } else
1328#endif /* CONFIG_PPC_PMAC */
1329 rdev->mode_info.connector_table = CT_GENERIC;
1330 }
1331
1332 switch (rdev->mode_info.connector_table) {
1333 case CT_GENERIC:
1334 DRM_INFO("Connector Table: %d (generic)\n",
1335 rdev->mode_info.connector_table);
1336 /* these are the most common settings */
1337 if (rdev->flags & RADEON_SINGLE_CRTC) {
1338 /* VGA - primary dac */
6a93cb25 1339 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1340 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1341 radeon_add_legacy_encoder(dev,
1342 radeon_get_encoder_id(dev,
1343 ATOM_DEVICE_CRT1_SUPPORT,
1344 1),
1345 ATOM_DEVICE_CRT1_SUPPORT);
1346 radeon_add_legacy_connector(dev, 0,
1347 ATOM_DEVICE_CRT1_SUPPORT,
1348 DRM_MODE_CONNECTOR_VGA,
b75fad06 1349 &ddc_i2c,
eed45b30
AD		 1350 CONNECTOR_OBJECT_ID_VGA,
1351 &hpd);
771fe6b9
JG		 1352 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1353 /* LVDS */
6a93cb25 1354 ddc_i2c = combios_setup_i2c_bus(rdev, 0);
eed45b30 1355 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1356 radeon_add_legacy_encoder(dev,
1357 radeon_get_encoder_id(dev,
1358 ATOM_DEVICE_LCD1_SUPPORT,
1359 0),
1360 ATOM_DEVICE_LCD1_SUPPORT);
1361 radeon_add_legacy_connector(dev, 0,
1362 ATOM_DEVICE_LCD1_SUPPORT,
1363 DRM_MODE_CONNECTOR_LVDS,
b75fad06 1364 &ddc_i2c,
eed45b30
AD		 1365 CONNECTOR_OBJECT_ID_LVDS,
1366 &hpd);
771fe6b9
JG		 1367
1368 /* VGA - primary dac */
6a93cb25 1369 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1370 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1371 radeon_add_legacy_encoder(dev,
1372 radeon_get_encoder_id(dev,
1373 ATOM_DEVICE_CRT1_SUPPORT,
1374 1),
1375 ATOM_DEVICE_CRT1_SUPPORT);
1376 radeon_add_legacy_connector(dev, 1,
1377 ATOM_DEVICE_CRT1_SUPPORT,
1378 DRM_MODE_CONNECTOR_VGA,
b75fad06 1379 &ddc_i2c,
eed45b30
AD		 1380 CONNECTOR_OBJECT_ID_VGA,
1381 &hpd);
771fe6b9
JG		 1382 } else {
1383 /* DVI-I - tv dac, int tmds */
6a93cb25 1384 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1385 hpd.hpd = RADEON_HPD_1;
771fe6b9
JG		 1386 radeon_add_legacy_encoder(dev,
1387 radeon_get_encoder_id(dev,
1388 ATOM_DEVICE_DFP1_SUPPORT,
1389 0),
1390 ATOM_DEVICE_DFP1_SUPPORT);
1391 radeon_add_legacy_encoder(dev,
1392 radeon_get_encoder_id(dev,
1393 ATOM_DEVICE_CRT2_SUPPORT,
1394 2),
1395 ATOM_DEVICE_CRT2_SUPPORT);
1396 radeon_add_legacy_connector(dev, 0,
1397 ATOM_DEVICE_DFP1_SUPPORT |
1398 ATOM_DEVICE_CRT2_SUPPORT,
1399 DRM_MODE_CONNECTOR_DVII,
b75fad06 1400 &ddc_i2c,
eed45b30
AD		 1401 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1402 &hpd);
771fe6b9
JG		 1403
1404 /* VGA - primary dac */
6a93cb25 1405 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1406 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1407 radeon_add_legacy_encoder(dev,
1408 radeon_get_encoder_id(dev,
1409 ATOM_DEVICE_CRT1_SUPPORT,
1410 1),
1411 ATOM_DEVICE_CRT1_SUPPORT);
1412 radeon_add_legacy_connector(dev, 1,
1413 ATOM_DEVICE_CRT1_SUPPORT,
1414 DRM_MODE_CONNECTOR_VGA,
b75fad06 1415 &ddc_i2c,
eed45b30
AD		 1416 CONNECTOR_OBJECT_ID_VGA,
1417 &hpd);
771fe6b9
JG		 1418 }
1419
1420 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1421 /* TV - tv dac */
eed45b30
AD		 1422 ddc_i2c.valid = false;
1423 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1424 radeon_add_legacy_encoder(dev,
1425 radeon_get_encoder_id(dev,
1426 ATOM_DEVICE_TV1_SUPPORT,
1427 2),
1428 ATOM_DEVICE_TV1_SUPPORT);
1429 radeon_add_legacy_connector(dev, 2,
1430 ATOM_DEVICE_TV1_SUPPORT,
1431 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1432 &ddc_i2c,
eed45b30
AD		 1433 CONNECTOR_OBJECT_ID_SVIDEO,
1434 &hpd);
771fe6b9
JG		 1435 }
1436 break;
1437 case CT_IBOOK:
1438 DRM_INFO("Connector Table: %d (ibook)\n",
1439 rdev->mode_info.connector_table);
1440 /* LVDS */
6a93cb25 1441 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1442 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1443 radeon_add_legacy_encoder(dev,
1444 radeon_get_encoder_id(dev,
1445 ATOM_DEVICE_LCD1_SUPPORT,
1446 0),
1447 ATOM_DEVICE_LCD1_SUPPORT);
1448 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1449 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1450 CONNECTOR_OBJECT_ID_LVDS,
1451 &hpd);
771fe6b9 1452 /* VGA - TV DAC */
6a93cb25 1453 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1454 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1455 radeon_add_legacy_encoder(dev,
1456 radeon_get_encoder_id(dev,
1457 ATOM_DEVICE_CRT2_SUPPORT,
1458 2),
1459 ATOM_DEVICE_CRT2_SUPPORT);
1460 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1461 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1462 CONNECTOR_OBJECT_ID_VGA,
1463 &hpd);
771fe6b9 1464 /* TV - TV DAC */
eed45b30
AD		 1465 ddc_i2c.valid = false;
1466 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1467 radeon_add_legacy_encoder(dev,
1468 radeon_get_encoder_id(dev,
1469 ATOM_DEVICE_TV1_SUPPORT,
1470 2),
1471 ATOM_DEVICE_TV1_SUPPORT);
1472 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1473 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1474 &ddc_i2c,
eed45b30
AD		 1475 CONNECTOR_OBJECT_ID_SVIDEO,
1476 &hpd);
771fe6b9
JG		 1477 break;
1478 case CT_POWERBOOK_EXTERNAL:
1479 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1480 rdev->mode_info.connector_table);
1481 /* LVDS */
6a93cb25 1482 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1483 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1484 radeon_add_legacy_encoder(dev,
1485 radeon_get_encoder_id(dev,
1486 ATOM_DEVICE_LCD1_SUPPORT,
1487 0),
1488 ATOM_DEVICE_LCD1_SUPPORT);
1489 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1490 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1491 CONNECTOR_OBJECT_ID_LVDS,
1492 &hpd);
771fe6b9 1493 /* DVI-I - primary dac, ext tmds */
6a93cb25 1494 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1495 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1496 radeon_add_legacy_encoder(dev,
1497 radeon_get_encoder_id(dev,
1498 ATOM_DEVICE_DFP2_SUPPORT,
1499 0),
1500 ATOM_DEVICE_DFP2_SUPPORT);
1501 radeon_add_legacy_encoder(dev,
1502 radeon_get_encoder_id(dev,
1503 ATOM_DEVICE_CRT1_SUPPORT,
1504 1),
1505 ATOM_DEVICE_CRT1_SUPPORT);
b75fad06 1506 /* XXX some are SL */
771fe6b9
JG		 1507 radeon_add_legacy_connector(dev, 1,
1508 ATOM_DEVICE_DFP2_SUPPORT |
1509 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1510 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1511 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1512 &hpd);
771fe6b9 1513 /* TV - TV DAC */
eed45b30
AD		 1514 ddc_i2c.valid = false;
1515 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1516 radeon_add_legacy_encoder(dev,
1517 radeon_get_encoder_id(dev,
1518 ATOM_DEVICE_TV1_SUPPORT,
1519 2),
1520 ATOM_DEVICE_TV1_SUPPORT);
1521 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1522 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1523 &ddc_i2c,
eed45b30
AD		 1524 CONNECTOR_OBJECT_ID_SVIDEO,
1525 &hpd);
771fe6b9
JG		 1526 break;
1527 case CT_POWERBOOK_INTERNAL:
1528 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1529 rdev->mode_info.connector_table);
1530 /* LVDS */
6a93cb25 1531 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1532 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1533 radeon_add_legacy_encoder(dev,
1534 radeon_get_encoder_id(dev,
1535 ATOM_DEVICE_LCD1_SUPPORT,
1536 0),
1537 ATOM_DEVICE_LCD1_SUPPORT);
1538 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1539 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1540 CONNECTOR_OBJECT_ID_LVDS,
1541 &hpd);
771fe6b9 1542 /* DVI-I - primary dac, int tmds */
6a93cb25 1543 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1544 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1545 radeon_add_legacy_encoder(dev,
1546 radeon_get_encoder_id(dev,
1547 ATOM_DEVICE_DFP1_SUPPORT,
1548 0),
1549 ATOM_DEVICE_DFP1_SUPPORT);
1550 radeon_add_legacy_encoder(dev,
1551 radeon_get_encoder_id(dev,
1552 ATOM_DEVICE_CRT1_SUPPORT,
1553 1),
1554 ATOM_DEVICE_CRT1_SUPPORT);
1555 radeon_add_legacy_connector(dev, 1,
1556 ATOM_DEVICE_DFP1_SUPPORT |
1557 ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1558 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1559 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1560 &hpd);
771fe6b9 1561 /* TV - TV DAC */
eed45b30
AD		 1562 ddc_i2c.valid = false;
1563 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1564 radeon_add_legacy_encoder(dev,
1565 radeon_get_encoder_id(dev,
1566 ATOM_DEVICE_TV1_SUPPORT,
1567 2),
1568 ATOM_DEVICE_TV1_SUPPORT);
1569 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1570 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1571 &ddc_i2c,
eed45b30
AD		 1572 CONNECTOR_OBJECT_ID_SVIDEO,
1573 &hpd);
771fe6b9
JG		 1574 break;
1575 case CT_POWERBOOK_VGA:
1576 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1577 rdev->mode_info.connector_table);
1578 /* LVDS */
6a93cb25 1579 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1580 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1581 radeon_add_legacy_encoder(dev,
1582 radeon_get_encoder_id(dev,
1583 ATOM_DEVICE_LCD1_SUPPORT,
1584 0),
1585 ATOM_DEVICE_LCD1_SUPPORT);
1586 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
b75fad06 1587 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
eed45b30
AD		 1588 CONNECTOR_OBJECT_ID_LVDS,
1589 &hpd);
771fe6b9 1590 /* VGA - primary dac */
6a93cb25 1591 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1592 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1593 radeon_add_legacy_encoder(dev,
1594 radeon_get_encoder_id(dev,
1595 ATOM_DEVICE_CRT1_SUPPORT,
1596 1),
1597 ATOM_DEVICE_CRT1_SUPPORT);
1598 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1599 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1600 CONNECTOR_OBJECT_ID_VGA,
1601 &hpd);
771fe6b9 1602 /* TV - TV DAC */
eed45b30
AD		 1603 ddc_i2c.valid = false;
1604 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1605 radeon_add_legacy_encoder(dev,
1606 radeon_get_encoder_id(dev,
1607 ATOM_DEVICE_TV1_SUPPORT,
1608 2),
1609 ATOM_DEVICE_TV1_SUPPORT);
1610 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1611 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1612 &ddc_i2c,
eed45b30
AD		 1613 CONNECTOR_OBJECT_ID_SVIDEO,
1614 &hpd);
771fe6b9
JG		 1615 break;
1616 case CT_MINI_EXTERNAL:
1617 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1618 rdev->mode_info.connector_table);
1619 /* DVI-I - tv dac, ext tmds */
6a93cb25 1620 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1621 hpd.hpd = RADEON_HPD_2; /* ??? */
771fe6b9
JG		 1622 radeon_add_legacy_encoder(dev,
1623 radeon_get_encoder_id(dev,
1624 ATOM_DEVICE_DFP2_SUPPORT,
1625 0),
1626 ATOM_DEVICE_DFP2_SUPPORT);
1627 radeon_add_legacy_encoder(dev,
1628 radeon_get_encoder_id(dev,
1629 ATOM_DEVICE_CRT2_SUPPORT,
1630 2),
1631 ATOM_DEVICE_CRT2_SUPPORT);
b75fad06 1632 /* XXX are any DL? */
771fe6b9
JG		 1633 radeon_add_legacy_connector(dev, 0,
1634 ATOM_DEVICE_DFP2_SUPPORT |
1635 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1636 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1637 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1638 &hpd);
771fe6b9 1639 /* TV - TV DAC */
eed45b30
AD		 1640 ddc_i2c.valid = false;
1641 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1642 radeon_add_legacy_encoder(dev,
1643 radeon_get_encoder_id(dev,
1644 ATOM_DEVICE_TV1_SUPPORT,
1645 2),
1646 ATOM_DEVICE_TV1_SUPPORT);
1647 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1648 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1649 &ddc_i2c,
eed45b30
AD		 1650 CONNECTOR_OBJECT_ID_SVIDEO,
1651 &hpd);
771fe6b9
JG		 1652 break;
1653 case CT_MINI_INTERNAL:
1654 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1655 rdev->mode_info.connector_table);
1656 /* DVI-I - tv dac, int tmds */
6a93cb25 1657 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1658 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1659 radeon_add_legacy_encoder(dev,
1660 radeon_get_encoder_id(dev,
1661 ATOM_DEVICE_DFP1_SUPPORT,
1662 0),
1663 ATOM_DEVICE_DFP1_SUPPORT);
1664 radeon_add_legacy_encoder(dev,
1665 radeon_get_encoder_id(dev,
1666 ATOM_DEVICE_CRT2_SUPPORT,
1667 2),
1668 ATOM_DEVICE_CRT2_SUPPORT);
1669 radeon_add_legacy_connector(dev, 0,
1670 ATOM_DEVICE_DFP1_SUPPORT |
1671 ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1672 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
eed45b30
AD		 1673 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1674 &hpd);
771fe6b9 1675 /* TV - TV DAC */
eed45b30
AD		 1676 ddc_i2c.valid = false;
1677 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1678 radeon_add_legacy_encoder(dev,
1679 radeon_get_encoder_id(dev,
1680 ATOM_DEVICE_TV1_SUPPORT,
1681 2),
1682 ATOM_DEVICE_TV1_SUPPORT);
1683 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1684 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1685 &ddc_i2c,
eed45b30
AD		 1686 CONNECTOR_OBJECT_ID_SVIDEO,
1687 &hpd);
771fe6b9
JG		 1688 break;
1689 case CT_IMAC_G5_ISIGHT:
1690 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1691 rdev->mode_info.connector_table);
1692 /* DVI-D - int tmds */
6a93cb25 1693 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
eed45b30 1694 hpd.hpd = RADEON_HPD_1; /* ??? */
771fe6b9
JG		 1695 radeon_add_legacy_encoder(dev,
1696 radeon_get_encoder_id(dev,
1697 ATOM_DEVICE_DFP1_SUPPORT,
1698 0),
1699 ATOM_DEVICE_DFP1_SUPPORT);
1700 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
b75fad06 1701 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
eed45b30
AD		 1702 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1703 &hpd);
771fe6b9 1704 /* VGA - tv dac */
6a93cb25 1705 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 1706 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1707 radeon_add_legacy_encoder(dev,
1708 radeon_get_encoder_id(dev,
1709 ATOM_DEVICE_CRT2_SUPPORT,
1710 2),
1711 ATOM_DEVICE_CRT2_SUPPORT);
1712 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1713 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1714 CONNECTOR_OBJECT_ID_VGA,
1715 &hpd);
771fe6b9 1716 /* TV - TV DAC */
eed45b30
AD		 1717 ddc_i2c.valid = false;
1718 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1719 radeon_add_legacy_encoder(dev,
1720 radeon_get_encoder_id(dev,
1721 ATOM_DEVICE_TV1_SUPPORT,
1722 2),
1723 ATOM_DEVICE_TV1_SUPPORT);
1724 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1725 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1726 &ddc_i2c,
eed45b30
AD		 1727 CONNECTOR_OBJECT_ID_SVIDEO,
1728 &hpd);
771fe6b9
JG		 1729 break;
1730 case CT_EMAC:
1731 DRM_INFO("Connector Table: %d (emac)\n",
1732 rdev->mode_info.connector_table);
1733 /* VGA - primary dac */
6a93cb25 1734 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 1735 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1736 radeon_add_legacy_encoder(dev,
1737 radeon_get_encoder_id(dev,
1738 ATOM_DEVICE_CRT1_SUPPORT,
1739 1),
1740 ATOM_DEVICE_CRT1_SUPPORT);
1741 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
b75fad06 1742 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1743 CONNECTOR_OBJECT_ID_VGA,
1744 &hpd);
771fe6b9 1745 /* VGA - tv dac */
6a93cb25 1746 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
eed45b30 1747 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1748 radeon_add_legacy_encoder(dev,
1749 radeon_get_encoder_id(dev,
1750 ATOM_DEVICE_CRT2_SUPPORT,
1751 2),
1752 ATOM_DEVICE_CRT2_SUPPORT);
1753 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
b75fad06 1754 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
eed45b30
AD		 1755 CONNECTOR_OBJECT_ID_VGA,
1756 &hpd);
771fe6b9 1757 /* TV - TV DAC */
eed45b30
AD		 1758 ddc_i2c.valid = false;
1759 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 1760 radeon_add_legacy_encoder(dev,
1761 radeon_get_encoder_id(dev,
1762 ATOM_DEVICE_TV1_SUPPORT,
1763 2),
1764 ATOM_DEVICE_TV1_SUPPORT);
1765 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1766 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 1767 &ddc_i2c,
eed45b30
AD		 1768 CONNECTOR_OBJECT_ID_SVIDEO,
1769 &hpd);
771fe6b9
JG		 1770 break;
1771 default:
1772 DRM_INFO("Connector table: %d (invalid)\n",
1773 rdev->mode_info.connector_table);
1774 return false;
1775 }
1776
1777 radeon_link_encoder_connector(dev);
1778
1779 return true;
1780}
1781
1782static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1783 int bios_index,
1784 enum radeon_combios_connector
1785 *legacy_connector,
eed45b30
AD		 1786 struct radeon_i2c_bus_rec *ddc_i2c,
1787 struct radeon_hpd *hpd)
771fe6b9
JG		 1788{
1789 struct radeon_device *rdev = dev->dev_private;
1790
1791 /* XPRESS DDC quirks */
1792 if ((rdev->family == CHIP_RS400 ||
1793 rdev->family == CHIP_RS480) &&
1794 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1795 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 1796 else if ((rdev->family == CHIP_RS400 ||
1797 rdev->family == CHIP_RS480) &&
1798 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
6a93cb25 1799 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 1800 ddc_i2c->mask_clk_mask = (0x20 << 8);
1801 ddc_i2c->mask_data_mask = 0x80;
1802 ddc_i2c->a_clk_mask = (0x20 << 8);
1803 ddc_i2c->a_data_mask = 0x80;
9b9fe724
AD		 1804 ddc_i2c->en_clk_mask = (0x20 << 8);
1805 ddc_i2c->en_data_mask = 0x80;
1806 ddc_i2c->y_clk_mask = (0x20 << 8);
1807 ddc_i2c->y_data_mask = 0x80;
771fe6b9
JG		 1808 }
1809
fcec570b
AD		 1810 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1811 if ((rdev->family >= CHIP_R300) &&
1812 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
6a93cb25 1813 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
fcec570b 1814
771fe6b9
JG		 1815 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1816 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1817 if (dev->pdev->device == 0x515e &&
1818 dev->pdev->subsystem_vendor == 0x1014) {
1819 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1820 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1821 return false;
1822 }
1823
1824 /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1825 if (dev->pdev->device == 0x5159 &&
1826 dev->pdev->subsystem_vendor == 0x1002 &&
1827 dev->pdev->subsystem_device == 0x013a) {
1828 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1829 *legacy_connector = CONNECTOR_CRT_LEGACY;
1830
1831 }
1832
1833 /* X300 card with extra non-existent DVI port */
1834 if (dev->pdev->device == 0x5B60 &&
1835 dev->pdev->subsystem_vendor == 0x17af &&
1836 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1837 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1838 return false;
1839 }
1840
1841 return true;
1842}
1843
790cfb34
AD		 1844static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1845{
1846 /* Acer 5102 has non-existent TV port */
1847 if (dev->pdev->device == 0x5975 &&
1848 dev->pdev->subsystem_vendor == 0x1025 &&
1849 dev->pdev->subsystem_device == 0x009f)
1850 return false;
1851
fc7f7119
AD		 1852 /* HP dc5750 has non-existent TV port */
1853 if (dev->pdev->device == 0x5974 &&
1854 dev->pdev->subsystem_vendor == 0x103c &&
1855 dev->pdev->subsystem_device == 0x280a)
1856 return false;
1857
fd874ad0
AD		 1858 /* MSI S270 has non-existent TV port */
1859 if (dev->pdev->device == 0x5955 &&
1860 dev->pdev->subsystem_vendor == 0x1462 &&
1861 dev->pdev->subsystem_device == 0x0131)
1862 return false;
1863
790cfb34
AD		 1864 return true;
1865}
1866
b75fad06
AD		 1867static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1868{
1869 struct radeon_device *rdev = dev->dev_private;
1870 uint32_t ext_tmds_info;
1871
1872 if (rdev->flags & RADEON_IS_IGP) {
1873 if (is_dvi_d)
1874 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1875 else
1876 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1877 }
1878 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1879 if (ext_tmds_info) {
1880 uint8_t rev = RBIOS8(ext_tmds_info);
1881 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1882 if (rev >= 3) {
1883 if (is_dvi_d)
1884 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1885 else
1886 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1887 } else {
1888 if (flags & 1) {
1889 if (is_dvi_d)
1890 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1891 else
1892 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1893 }
1894 }
1895 }
1896 if (is_dvi_d)
1897 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1898 else
1899 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1900}
1901
771fe6b9
JG		 1902bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1903{
1904 struct radeon_device *rdev = dev->dev_private;
1905 uint32_t conn_info, entry, devices;
b75fad06 1906 uint16_t tmp, connector_object_id;
771fe6b9
JG		 1907 enum radeon_combios_ddc ddc_type;
1908 enum radeon_combios_connector connector;
1909 int i = 0;
1910 struct radeon_i2c_bus_rec ddc_i2c;
eed45b30 1911 struct radeon_hpd hpd;
771fe6b9
JG		 1912
1913 if (rdev->bios == NULL)
1914 return false;
1915
1916 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1917 if (conn_info) {
1918 for (i = 0; i < 4; i++) {
1919 entry = conn_info + 2 + i * 2;
1920
1921 if (!RBIOS16(entry))
1922 break;
1923
1924 tmp = RBIOS16(entry);
1925
1926 connector = (tmp >> 12) & 0xf;
1927
1928 ddc_type = (tmp >> 8) & 0xf;
1929 switch (ddc_type) {
1930 case DDC_MONID:
1931 ddc_i2c =
6a93cb25 1932 combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 1933 break;
1934 case DDC_DVI:
1935 ddc_i2c =
6a93cb25 1936 combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 1937 break;
1938 case DDC_VGA:
1939 ddc_i2c =
6a93cb25 1940 combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 1941 break;
1942 case DDC_CRT2:
1943 ddc_i2c =
6a93cb25 1944 combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 1945 break;
1946 default:
1947 break;
1948 }
1949
eed45b30
AD		 1950 switch (connector) {
1951 case CONNECTOR_PROPRIETARY_LEGACY:
1952 case CONNECTOR_DVI_I_LEGACY:
1953 case CONNECTOR_DVI_D_LEGACY:
1954 if ((tmp >> 4) & 0x1)
1955 hpd.hpd = RADEON_HPD_2;
1956 else
1957 hpd.hpd = RADEON_HPD_1;
1958 break;
1959 default:
1960 hpd.hpd = RADEON_HPD_NONE;
1961 break;
1962 }
1963
2d152c6b 1964 if (!radeon_apply_legacy_quirks(dev, i, &connector,
eed45b30 1965 &ddc_i2c, &hpd))
2d152c6b 1966 continue;
771fe6b9
JG		 1967
1968 switch (connector) {
1969 case CONNECTOR_PROPRIETARY_LEGACY:
1970 if ((tmp >> 4) & 0x1)
1971 devices = ATOM_DEVICE_DFP2_SUPPORT;
1972 else
1973 devices = ATOM_DEVICE_DFP1_SUPPORT;
1974 radeon_add_legacy_encoder(dev,
1975 radeon_get_encoder_id
1976 (dev, devices, 0),
1977 devices);
1978 radeon_add_legacy_connector(dev, i, devices,
1979 legacy_connector_convert
1980 [connector],
b75fad06 1981 &ddc_i2c,
eed45b30
AD		 1982 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1983 &hpd);
771fe6b9
JG		 1984 break;
1985 case CONNECTOR_CRT_LEGACY:
1986 if (tmp & 0x1) {
1987 devices = ATOM_DEVICE_CRT2_SUPPORT;
1988 radeon_add_legacy_encoder(dev,
1989 radeon_get_encoder_id
1990 (dev,
1991 ATOM_DEVICE_CRT2_SUPPORT,
1992 2),
1993 ATOM_DEVICE_CRT2_SUPPORT);
1994 } else {
1995 devices = ATOM_DEVICE_CRT1_SUPPORT;
1996 radeon_add_legacy_encoder(dev,
1997 radeon_get_encoder_id
1998 (dev,
1999 ATOM_DEVICE_CRT1_SUPPORT,
2000 1),
2001 ATOM_DEVICE_CRT1_SUPPORT);
2002 }
2003 radeon_add_legacy_connector(dev,
2004 i,
2005 devices,
2006 legacy_connector_convert
2007 [connector],
b75fad06 2008 &ddc_i2c,
eed45b30
AD		 2009 CONNECTOR_OBJECT_ID_VGA,
2010 &hpd);
771fe6b9
JG		 2011 break;
2012 case CONNECTOR_DVI_I_LEGACY:
2013 devices = 0;
2014 if (tmp & 0x1) {
2015 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2016 radeon_add_legacy_encoder(dev,
2017 radeon_get_encoder_id
2018 (dev,
2019 ATOM_DEVICE_CRT2_SUPPORT,
2020 2),
2021 ATOM_DEVICE_CRT2_SUPPORT);
2022 } else {
2023 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2024 radeon_add_legacy_encoder(dev,
2025 radeon_get_encoder_id
2026 (dev,
2027 ATOM_DEVICE_CRT1_SUPPORT,
2028 1),
2029 ATOM_DEVICE_CRT1_SUPPORT);
2030 }
2031 if ((tmp >> 4) & 0x1) {
2032 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2033 radeon_add_legacy_encoder(dev,
2034 radeon_get_encoder_id
2035 (dev,
2036 ATOM_DEVICE_DFP2_SUPPORT,
2037 0),
2038 ATOM_DEVICE_DFP2_SUPPORT);
b75fad06 2039 connector_object_id = combios_check_dl_dvi(dev, 0);
771fe6b9
JG		 2040 } else {
2041 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2042 radeon_add_legacy_encoder(dev,
2043 radeon_get_encoder_id
2044 (dev,
2045 ATOM_DEVICE_DFP1_SUPPORT,
2046 0),
2047 ATOM_DEVICE_DFP1_SUPPORT);
b75fad06 2048 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
771fe6b9
JG		 2049 }
2050 radeon_add_legacy_connector(dev,
2051 i,
2052 devices,
2053 legacy_connector_convert
2054 [connector],
b75fad06 2055 &ddc_i2c,
eed45b30
AD		 2056 connector_object_id,
2057 &hpd);
771fe6b9
JG		 2058 break;
2059 case CONNECTOR_DVI_D_LEGACY:
b75fad06 2060 if ((tmp >> 4) & 0x1) {
771fe6b9 2061 devices = ATOM_DEVICE_DFP2_SUPPORT;
b75fad06
AD		 2062 connector_object_id = combios_check_dl_dvi(dev, 1);
2063 } else {
771fe6b9 2064 devices = ATOM_DEVICE_DFP1_SUPPORT;
b75fad06
AD		 2065 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2066 }
771fe6b9
JG		 2067 radeon_add_legacy_encoder(dev,
2068 radeon_get_encoder_id
2069 (dev, devices, 0),
2070 devices);
2071 radeon_add_legacy_connector(dev, i, devices,
2072 legacy_connector_convert
2073 [connector],
b75fad06 2074 &ddc_i2c,
eed45b30
AD		 2075 connector_object_id,
2076 &hpd);
771fe6b9
JG		 2077 break;
2078 case CONNECTOR_CTV_LEGACY:
2079 case CONNECTOR_STV_LEGACY:
2080 radeon_add_legacy_encoder(dev,
2081 radeon_get_encoder_id
2082 (dev,
2083 ATOM_DEVICE_TV1_SUPPORT,
2084 2),
2085 ATOM_DEVICE_TV1_SUPPORT);
2086 radeon_add_legacy_connector(dev, i,
2087 ATOM_DEVICE_TV1_SUPPORT,
2088 legacy_connector_convert
2089 [connector],
b75fad06 2090 &ddc_i2c,
eed45b30
AD		 2091 CONNECTOR_OBJECT_ID_SVIDEO,
2092 &hpd);
771fe6b9
JG		 2093 break;
2094 default:
2095 DRM_ERROR("Unknown connector type: %d\n",
2096 connector);
2097 continue;
2098 }
2099
2100 }
2101 } else {
2102 uint16_t tmds_info =
2103 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2104 if (tmds_info) {
2105 DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2106
2107 radeon_add_legacy_encoder(dev,
2108 radeon_get_encoder_id(dev,
2109 ATOM_DEVICE_CRT1_SUPPORT,
2110 1),
2111 ATOM_DEVICE_CRT1_SUPPORT);
2112 radeon_add_legacy_encoder(dev,
2113 radeon_get_encoder_id(dev,
2114 ATOM_DEVICE_DFP1_SUPPORT,
2115 0),
2116 ATOM_DEVICE_DFP1_SUPPORT);
2117
6a93cb25 2118 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
eed45b30 2119 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2120 radeon_add_legacy_connector(dev,
2121 0,
2122 ATOM_DEVICE_CRT1_SUPPORT |
2123 ATOM_DEVICE_DFP1_SUPPORT,
2124 DRM_MODE_CONNECTOR_DVII,
b75fad06 2125 &ddc_i2c,
eed45b30
AD		 2126 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2127 &hpd);
771fe6b9 2128 } else {
d0c403e9
AD		 2129 uint16_t crt_info =
2130 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2131 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2132 if (crt_info) {
2133 radeon_add_legacy_encoder(dev,
2134 radeon_get_encoder_id(dev,
2135 ATOM_DEVICE_CRT1_SUPPORT,
2136 1),
2137 ATOM_DEVICE_CRT1_SUPPORT);
6a93cb25 2138 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
eed45b30 2139 hpd.hpd = RADEON_HPD_NONE;
d0c403e9
AD		 2140 radeon_add_legacy_connector(dev,
2141 0,
2142 ATOM_DEVICE_CRT1_SUPPORT,
2143 DRM_MODE_CONNECTOR_VGA,
b75fad06 2144 &ddc_i2c,
eed45b30
AD		 2145 CONNECTOR_OBJECT_ID_VGA,
2146 &hpd);
d0c403e9
AD		 2147 } else {
2148 DRM_DEBUG("No connector info found\n");
2149 return false;
2150 }
771fe6b9
JG		 2151 }
2152 }
2153
2154 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2155 uint16_t lcd_info =
2156 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2157 if (lcd_info) {
2158 uint16_t lcd_ddc_info =
2159 combios_get_table_offset(dev,
2160 COMBIOS_LCD_DDC_INFO_TABLE);
2161
2162 radeon_add_legacy_encoder(dev,
2163 radeon_get_encoder_id(dev,
2164 ATOM_DEVICE_LCD1_SUPPORT,
2165 0),
2166 ATOM_DEVICE_LCD1_SUPPORT);
2167
2168 if (lcd_ddc_info) {
2169 ddc_type = RBIOS8(lcd_ddc_info + 2);
2170 switch (ddc_type) {
2171 case DDC_MONID:
2172 ddc_i2c =
2173 combios_setup_i2c_bus
6a93cb25 2174 (rdev, RADEON_GPIO_MONID);
771fe6b9
JG		 2175 break;
2176 case DDC_DVI:
2177 ddc_i2c =
2178 combios_setup_i2c_bus
6a93cb25 2179 (rdev, RADEON_GPIO_DVI_DDC);
771fe6b9
JG		 2180 break;
2181 case DDC_VGA:
2182 ddc_i2c =
2183 combios_setup_i2c_bus
6a93cb25 2184 (rdev, RADEON_GPIO_VGA_DDC);
771fe6b9
JG		 2185 break;
2186 case DDC_CRT2:
2187 ddc_i2c =
2188 combios_setup_i2c_bus
6a93cb25 2189 (rdev, RADEON_GPIO_CRT2_DDC);
771fe6b9
JG		 2190 break;
2191 case DDC_LCD:
2192 ddc_i2c =
2193 combios_setup_i2c_bus
6a93cb25 2194 (rdev, RADEON_GPIOPAD_MASK);
771fe6b9
JG		 2195 ddc_i2c.mask_clk_mask =
2196 RBIOS32(lcd_ddc_info + 3);
2197 ddc_i2c.mask_data_mask =
2198 RBIOS32(lcd_ddc_info + 7);
2199 ddc_i2c.a_clk_mask =
2200 RBIOS32(lcd_ddc_info + 3);
2201 ddc_i2c.a_data_mask =
2202 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2203 ddc_i2c.en_clk_mask =
771fe6b9 2204 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2205 ddc_i2c.en_data_mask =
771fe6b9 2206 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2207 ddc_i2c.y_clk_mask =
771fe6b9 2208 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2209 ddc_i2c.y_data_mask =
771fe6b9
JG		 2210 RBIOS32(lcd_ddc_info + 7);
2211 break;
2212 case DDC_GPIO:
2213 ddc_i2c =
2214 combios_setup_i2c_bus
6a93cb25 2215 (rdev, RADEON_MDGPIO_MASK);
771fe6b9
JG		 2216 ddc_i2c.mask_clk_mask =
2217 RBIOS32(lcd_ddc_info + 3);
2218 ddc_i2c.mask_data_mask =
2219 RBIOS32(lcd_ddc_info + 7);
2220 ddc_i2c.a_clk_mask =
2221 RBIOS32(lcd_ddc_info + 3);
2222 ddc_i2c.a_data_mask =
2223 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2224 ddc_i2c.en_clk_mask =
771fe6b9 2225 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2226 ddc_i2c.en_data_mask =
771fe6b9 2227 RBIOS32(lcd_ddc_info + 7);
9b9fe724 2228 ddc_i2c.y_clk_mask =
771fe6b9 2229 RBIOS32(lcd_ddc_info + 3);
9b9fe724 2230 ddc_i2c.y_data_mask =
771fe6b9
JG		 2231 RBIOS32(lcd_ddc_info + 7);
2232 break;
2233 default:
2234 ddc_i2c.valid = false;
2235 break;
2236 }
2237 DRM_DEBUG("LCD DDC Info Table found!\n");
2238 } else
2239 ddc_i2c.valid = false;
2240
eed45b30 2241 hpd.hpd = RADEON_HPD_NONE;
771fe6b9
JG		 2242 radeon_add_legacy_connector(dev,
2243 5,
2244 ATOM_DEVICE_LCD1_SUPPORT,
2245 DRM_MODE_CONNECTOR_LVDS,
b75fad06 2246 &ddc_i2c,
eed45b30
AD		 2247 CONNECTOR_OBJECT_ID_LVDS,
2248 &hpd);
771fe6b9
JG		 2249 }
2250 }
2251
2252 /* check TV table */
2253 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2254 uint32_t tv_info =
2255 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2256 if (tv_info) {
2257 if (RBIOS8(tv_info + 6) == 'T') {
790cfb34 2258 if (radeon_apply_legacy_tv_quirks(dev)) {
eed45b30 2259 hpd.hpd = RADEON_HPD_NONE;
790cfb34
AD		 2260 radeon_add_legacy_encoder(dev,
2261 radeon_get_encoder_id
2262 (dev,
2263 ATOM_DEVICE_TV1_SUPPORT,
2264 2),
2265 ATOM_DEVICE_TV1_SUPPORT);
2266 radeon_add_legacy_connector(dev, 6,
2267 ATOM_DEVICE_TV1_SUPPORT,
2268 DRM_MODE_CONNECTOR_SVIDEO,
b75fad06 2269 &ddc_i2c,
eed45b30
AD		 2270 CONNECTOR_OBJECT_ID_SVIDEO,
2271 &hpd);
790cfb34 2272 }
771fe6b9
JG		 2273 }
2274 }
2275 }
2276
2277 radeon_link_encoder_connector(dev);
2278
2279 return true;
2280}
2281
fcec570b
AD		 2282void radeon_external_tmds_setup(struct drm_encoder *encoder)
2283{
2284 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2285 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2286
2287 if (!tmds)
2288 return;
2289
2290 switch (tmds->dvo_chip) {
2291 case DVO_SIL164:
2292 /* sil 164 */
2293 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2294 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2295 tmds->slave_addr,
2296 0x08, 0x30);
2297 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2298 tmds->slave_addr,
2299 0x09, 0x00);
2300 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2301 tmds->slave_addr,
2302 0x0a, 0x90);
2303 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2304 tmds->slave_addr,
2305 0x0c, 0x89);
2306 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2307 tmds->slave_addr,
2308 0x08, 0x3b);
2309 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2310 break;
2311 case DVO_SIL1178:
2312 /* sil 1178 - untested */
2313 /*
2314 * 0x0f, 0x44
2315 * 0x0f, 0x4c
2316 * 0x0e, 0x01
2317 * 0x0a, 0x80
2318 * 0x09, 0x30
2319 * 0x0c, 0xc9
2320 * 0x0d, 0x70
2321 * 0x08, 0x32
2322 * 0x08, 0x33
2323 */
2324 break;
2325 default:
2326 break;
2327 }
2328
2329}
2330
2331bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2332{
2333 struct drm_device *dev = encoder->dev;
2334 struct radeon_device *rdev = dev->dev_private;
2335 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2336 uint16_t offset;
2337 uint8_t blocks, slave_addr, rev;
2338 uint32_t index, id;
2339 uint32_t reg, val, and_mask, or_mask;
2340 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2341
2342 if (rdev->bios == NULL)
2343 return false;
2344
2345 if (!tmds)
2346 return false;
2347
2348 if (rdev->flags & RADEON_IS_IGP) {
2349 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2350 rev = RBIOS8(offset);
2351 if (offset) {
2352 rev = RBIOS8(offset);
2353 if (rev > 1) {
2354 blocks = RBIOS8(offset + 3);
2355 index = offset + 4;
2356 while (blocks > 0) {
2357 id = RBIOS16(index);
2358 index += 2;
2359 switch (id >> 13) {
2360 case 0:
2361 reg = (id & 0x1fff) * 4;
2362 val = RBIOS32(index);
2363 index += 4;
2364 WREG32(reg, val);
2365 break;
2366 case 2:
2367 reg = (id & 0x1fff) * 4;
2368 and_mask = RBIOS32(index);
2369 index += 4;
2370 or_mask = RBIOS32(index);
2371 index += 4;
2372 val = RREG32(reg);
2373 val = (val & and_mask) | or_mask;
2374 WREG32(reg, val);
2375 break;
2376 case 3:
2377 val = RBIOS16(index);
2378 index += 2;
2379 udelay(val);
2380 break;
2381 case 4:
2382 val = RBIOS16(index);
2383 index += 2;
2384 udelay(val * 1000);
2385 break;
2386 case 6:
2387 slave_addr = id & 0xff;
2388 slave_addr >>= 1; /* 7 bit addressing */
2389 index++;
2390 reg = RBIOS8(index);
2391 index++;
2392 val = RBIOS8(index);
2393 index++;
2394 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2395 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2396 slave_addr,
2397 reg, val);
2398 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2399 break;
2400 default:
2401 DRM_ERROR("Unknown id %d\n", id >> 13);
2402 break;
2403 }
2404 blocks--;
2405 }
2406 return true;
2407 }
2408 }
2409 } else {
2410 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2411 if (offset) {
2412 index = offset + 10;
2413 id = RBIOS16(index);
2414 while (id != 0xffff) {
2415 index += 2;
2416 switch (id >> 13) {
2417 case 0:
2418 reg = (id & 0x1fff) * 4;
2419 val = RBIOS32(index);
2420 WREG32(reg, val);
2421 break;
2422 case 2:
2423 reg = (id & 0x1fff) * 4;
2424 and_mask = RBIOS32(index);
2425 index += 4;
2426 or_mask = RBIOS32(index);
2427 index += 4;
2428 val = RREG32(reg);
2429 val = (val & and_mask) | or_mask;
2430 WREG32(reg, val);
2431 break;
2432 case 4:
2433 val = RBIOS16(index);
2434 index += 2;
2435 udelay(val);
2436 break;
2437 case 5:
2438 reg = id & 0x1fff;
2439 and_mask = RBIOS32(index);
2440 index += 4;
2441 or_mask = RBIOS32(index);
2442 index += 4;
2443 val = RREG32_PLL(reg);
2444 val = (val & and_mask) | or_mask;
2445 WREG32_PLL(reg, val);
2446 break;
2447 case 6:
2448 reg = id & 0x1fff;
2449 val = RBIOS8(index);
2450 index += 1;
2451 radeon_i2c_do_lock(tmds->i2c_bus, 1);
2452 radeon_i2c_sw_put_byte(tmds->i2c_bus,
2453 tmds->slave_addr,
2454 reg, val);
2455 radeon_i2c_do_lock(tmds->i2c_bus, 0);
2456 break;
2457 default:
2458 DRM_ERROR("Unknown id %d\n", id >> 13);
2459 break;
2460 }
2461 id = RBIOS16(index);
2462 }
2463 return true;
2464 }
2465 }
2466 return false;
2467}
2468
771fe6b9
JG		 2469static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2470{
2471 struct radeon_device *rdev = dev->dev_private;
2472
2473 if (offset) {
2474 while (RBIOS16(offset)) {
2475 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2476 uint32_t addr = (RBIOS16(offset) & 0x1fff);
2477 uint32_t val, and_mask, or_mask;
2478 uint32_t tmp;
2479
2480 offset += 2;
2481 switch (cmd) {
2482 case 0:
2483 val = RBIOS32(offset);
2484 offset += 4;
2485 WREG32(addr, val);
2486 break;
2487 case 1:
2488 val = RBIOS32(offset);
2489 offset += 4;
2490 WREG32(addr, val);
2491 break;
2492 case 2:
2493 and_mask = RBIOS32(offset);
2494 offset += 4;
2495 or_mask = RBIOS32(offset);
2496 offset += 4;
2497 tmp = RREG32(addr);
2498 tmp &= and_mask;
2499 tmp |= or_mask;
2500 WREG32(addr, tmp);
2501 break;
2502 case 3:
2503 and_mask = RBIOS32(offset);
2504 offset += 4;
2505 or_mask = RBIOS32(offset);
2506 offset += 4;
2507 tmp = RREG32(addr);
2508 tmp &= and_mask;
2509 tmp |= or_mask;
2510 WREG32(addr, tmp);
2511 break;
2512 case 4:
2513 val = RBIOS16(offset);
2514 offset += 2;
2515 udelay(val);
2516 break;
2517 case 5:
2518 val = RBIOS16(offset);
2519 offset += 2;
2520 switch (addr) {
2521 case 8:
2522 while (val--) {
2523 if (!
2524 (RREG32_PLL
2525 (RADEON_CLK_PWRMGT_CNTL) &
2526 RADEON_MC_BUSY))
2527 break;
2528 }
2529 break;
2530 case 9:
2531 while (val--) {
2532 if ((RREG32(RADEON_MC_STATUS) &
2533 RADEON_MC_IDLE))
2534 break;
2535 }
2536 break;
2537 default:
2538 break;
2539 }
2540 break;
2541 default:
2542 break;
2543 }
2544 }
2545 }
2546}
2547
2548static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2549{
2550 struct radeon_device *rdev = dev->dev_private;
2551
2552 if (offset) {
2553 while (RBIOS8(offset)) {
2554 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2555 uint8_t addr = (RBIOS8(offset) & 0x3f);
2556 uint32_t val, shift, tmp;
2557 uint32_t and_mask, or_mask;
2558
2559 offset++;
2560 switch (cmd) {
2561 case 0:
2562 val = RBIOS32(offset);
2563 offset += 4;
2564 WREG32_PLL(addr, val);
2565 break;
2566 case 1:
2567 shift = RBIOS8(offset) * 8;
2568 offset++;
2569 and_mask = RBIOS8(offset) << shift;
2570 and_mask |= ~(0xff << shift);
2571 offset++;
2572 or_mask = RBIOS8(offset) << shift;
2573 offset++;
2574 tmp = RREG32_PLL(addr);
2575 tmp &= and_mask;
2576 tmp |= or_mask;
2577 WREG32_PLL(addr, tmp);
2578 break;
2579 case 2:
2580 case 3:
2581 tmp = 1000;
2582 switch (addr) {
2583 case 1:
2584 udelay(150);
2585 break;
2586 case 2:
2587 udelay(1000);
2588 break;
2589 case 3:
2590 while (tmp--) {
2591 if (!
2592 (RREG32_PLL
2593 (RADEON_CLK_PWRMGT_CNTL) &
2594 RADEON_MC_BUSY))
2595 break;
2596 }
2597 break;
2598 case 4:
2599 while (tmp--) {
2600 if (RREG32_PLL
2601 (RADEON_CLK_PWRMGT_CNTL) &
2602 RADEON_DLL_READY)
2603 break;
2604 }
2605 break;
2606 case 5:
2607 tmp =
2608 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2609 if (tmp & RADEON_CG_NO1_DEBUG_0) {
2610#if 0
2611 uint32_t mclk_cntl =
2612 RREG32_PLL
2613 (RADEON_MCLK_CNTL);
2614 mclk_cntl &= 0xffff0000;
2615 /*mclk_cntl |= 0x00001111;*//* ??? */
2616 WREG32_PLL(RADEON_MCLK_CNTL,
2617 mclk_cntl);
2618 udelay(10000);
2619#endif
2620 WREG32_PLL
2621 (RADEON_CLK_PWRMGT_CNTL,
2622 tmp &
2623 ~RADEON_CG_NO1_DEBUG_0);
2624 udelay(10000);
2625 }
2626 break;
2627 default:
2628 break;
2629 }
2630 break;
2631 default:
2632 break;
2633 }
2634 }
2635 }
2636}
2637
2638static void combios_parse_ram_reset_table(struct drm_device *dev,
2639 uint16_t offset)
2640{
2641 struct radeon_device *rdev = dev->dev_private;
2642 uint32_t tmp;
2643
2644 if (offset) {
2645 uint8_t val = RBIOS8(offset);
2646 while (val != 0xff) {
2647 offset++;
2648
2649 if (val == 0x0f) {
2650 uint32_t channel_complete_mask;
2651
2652 if (ASIC_IS_R300(rdev))
2653 channel_complete_mask =
2654 R300_MEM_PWRUP_COMPLETE;
2655 else
2656 channel_complete_mask =
2657 RADEON_MEM_PWRUP_COMPLETE;
2658 tmp = 20000;
2659 while (tmp--) {
2660 if ((RREG32(RADEON_MEM_STR_CNTL) &
2661 channel_complete_mask) ==
2662 channel_complete_mask)
2663 break;
2664 }
2665 } else {
2666 uint32_t or_mask = RBIOS16(offset);
2667 offset += 2;
2668
2669 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2670 tmp &= RADEON_SDRAM_MODE_MASK;
2671 tmp |= or_mask;
2672 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2673
2674 or_mask = val << 24;
2675 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2676 tmp &= RADEON_B3MEM_RESET_MASK;
2677 tmp |= or_mask;
2678 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2679 }
2680 val = RBIOS8(offset);
2681 }
2682 }
2683}
2684
2685static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2686 int mem_addr_mapping)
2687{
2688 struct radeon_device *rdev = dev->dev_private;
2689 uint32_t mem_cntl;
2690 uint32_t mem_size;
2691 uint32_t addr = 0;
2692
2693 mem_cntl = RREG32(RADEON_MEM_CNTL);
2694 if (mem_cntl & RV100_HALF_MODE)
2695 ram /= 2;
2696 mem_size = ram;
2697 mem_cntl &= ~(0xff << 8);
2698 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2699 WREG32(RADEON_MEM_CNTL, mem_cntl);
2700 RREG32(RADEON_MEM_CNTL);
2701
2702 /* sdram reset ? */
2703
2704 /* something like this???? */
2705 while (ram--) {
2706 addr = ram * 1024 * 1024;
2707 /* write to each page */
2708 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2709 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2710 /* read back and verify */
2711 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2712 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2713 return 0;
2714 }
2715
2716 return mem_size;
2717}
2718
2719static void combios_write_ram_size(struct drm_device *dev)
2720{
2721 struct radeon_device *rdev = dev->dev_private;
2722 uint8_t rev;
2723 uint16_t offset;
2724 uint32_t mem_size = 0;
2725 uint32_t mem_cntl = 0;
2726
2727 /* should do something smarter here I guess... */
2728 if (rdev->flags & RADEON_IS_IGP)
2729 return;
2730
2731 /* first check detected mem table */
2732 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2733 if (offset) {
2734 rev = RBIOS8(offset);
2735 if (rev < 3) {
2736 mem_cntl = RBIOS32(offset + 1);
2737 mem_size = RBIOS16(offset + 5);
2738 if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2739 ((dev->pdev->device != 0x515e)
2740 && (dev->pdev->device != 0x5969)))
2741 WREG32(RADEON_MEM_CNTL, mem_cntl);
2742 }
2743 }
2744
2745 if (!mem_size) {
2746 offset =
2747 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2748 if (offset) {
2749 rev = RBIOS8(offset - 1);
2750 if (rev < 1) {
2751 if (((rdev->flags & RADEON_FAMILY_MASK) <
2752 CHIP_R200)
2753 && ((dev->pdev->device != 0x515e)
2754 && (dev->pdev->device != 0x5969))) {
2755 int ram = 0;
2756 int mem_addr_mapping = 0;
2757
2758 while (RBIOS8(offset)) {
2759 ram = RBIOS8(offset);
2760 mem_addr_mapping =
2761 RBIOS8(offset + 1);
2762 if (mem_addr_mapping != 0x25)
2763 ram *= 2;
2764 mem_size =
2765 combios_detect_ram(dev, ram,
2766 mem_addr_mapping);
2767 if (mem_size)
2768 break;
2769 offset += 2;
2770 }
2771 } else
2772 mem_size = RBIOS8(offset);
2773 } else {
2774 mem_size = RBIOS8(offset);
2775 mem_size *= 2; /* convert to MB */
2776 }
2777 }
2778 }
2779
2780 mem_size *= (1024 * 1024); /* convert to bytes */
2781 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2782}
2783
2784void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2785{
2786 uint16_t dyn_clk_info =
2787 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2788
2789 if (dyn_clk_info)
2790 combios_parse_pll_table(dev, dyn_clk_info);
2791}
2792
2793void radeon_combios_asic_init(struct drm_device *dev)
2794{
2795 struct radeon_device *rdev = dev->dev_private;
2796 uint16_t table;
2797
2798 /* port hardcoded mac stuff from radeonfb */
2799 if (rdev->bios == NULL)
2800 return;
2801
2802 /* ASIC INIT 1 */
2803 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2804 if (table)
2805 combios_parse_mmio_table(dev, table);
2806
2807 /* PLL INIT */
2808 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2809 if (table)
2810 combios_parse_pll_table(dev, table);
2811
2812 /* ASIC INIT 2 */
2813 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2814 if (table)
2815 combios_parse_mmio_table(dev, table);
2816
2817 if (!(rdev->flags & RADEON_IS_IGP)) {
2818 /* ASIC INIT 4 */
2819 table =
2820 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2821 if (table)
2822 combios_parse_mmio_table(dev, table);
2823
2824 /* RAM RESET */
2825 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2826 if (table)
2827 combios_parse_ram_reset_table(dev, table);
2828
2829 /* ASIC INIT 3 */
2830 table =
2831 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2832 if (table)
2833 combios_parse_mmio_table(dev, table);
2834
2835 /* write CONFIG_MEMSIZE */
2836 combios_write_ram_size(dev);
2837 }
2838
2839 /* DYN CLK 1 */
2840 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2841 if (table)
2842 combios_parse_pll_table(dev, table);
2843
2844}
2845
2846void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2847{
2848 struct radeon_device *rdev = dev->dev_private;
2849 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2850
2851 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2852 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2853 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2854
2855 /* let the bios control the backlight */
2856 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2857
2858 /* tell the bios not to handle mode switching */
2859 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2860 RADEON_ACC_MODE_CHANGE);
2861
2862 /* tell the bios a driver is loaded */
2863 bios_7_scratch |= RADEON_DRV_LOADED;
2864
2865 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2866 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2867 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2868}
2869
2870void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2871{
2872 struct drm_device *dev = encoder->dev;
2873 struct radeon_device *rdev = dev->dev_private;
2874 uint32_t bios_6_scratch;
2875
2876 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2877
2878 if (lock)
2879 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2880 else
2881 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2882
2883 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2884}
2885
2886void
2887radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2888 struct drm_encoder *encoder,
2889 bool connected)
2890{
2891 struct drm_device *dev = connector->dev;
2892 struct radeon_device *rdev = dev->dev_private;
2893 struct radeon_connector *radeon_connector =
2894 to_radeon_connector(connector);
2895 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2896 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2897 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2898
2899 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2900 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2901 if (connected) {
2902 DRM_DEBUG("TV1 connected\n");
2903 /* fix me */
2904 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2905 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2906 bios_5_scratch |= RADEON_TV1_ON;
2907 bios_5_scratch |= RADEON_ACC_REQ_TV1;
2908 } else {
2909 DRM_DEBUG("TV1 disconnected\n");
2910 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2911 bios_5_scratch &= ~RADEON_TV1_ON;
2912 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2913 }
2914 }
2915 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2916 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2917 if (connected) {
2918 DRM_DEBUG("LCD1 connected\n");
2919 bios_4_scratch |= RADEON_LCD1_ATTACHED;
2920 bios_5_scratch |= RADEON_LCD1_ON;
2921 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2922 } else {
2923 DRM_DEBUG("LCD1 disconnected\n");
2924 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2925 bios_5_scratch &= ~RADEON_LCD1_ON;
2926 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2927 }
2928 }
2929 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2930 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2931 if (connected) {
2932 DRM_DEBUG("CRT1 connected\n");
2933 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2934 bios_5_scratch |= RADEON_CRT1_ON;
2935 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2936 } else {
2937 DRM_DEBUG("CRT1 disconnected\n");
2938 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2939 bios_5_scratch &= ~RADEON_CRT1_ON;
2940 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2941 }
2942 }
2943 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2944 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2945 if (connected) {
2946 DRM_DEBUG("CRT2 connected\n");
2947 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2948 bios_5_scratch |= RADEON_CRT2_ON;
2949 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2950 } else {
2951 DRM_DEBUG("CRT2 disconnected\n");
2952 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2953 bios_5_scratch &= ~RADEON_CRT2_ON;
2954 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2955 }
2956 }
2957 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2958 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2959 if (connected) {
2960 DRM_DEBUG("DFP1 connected\n");
2961 bios_4_scratch |= RADEON_DFP1_ATTACHED;
2962 bios_5_scratch |= RADEON_DFP1_ON;
2963 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2964 } else {
2965 DRM_DEBUG("DFP1 disconnected\n");
2966 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2967 bios_5_scratch &= ~RADEON_DFP1_ON;
2968 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2969 }
2970 }
2971 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2972 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2973 if (connected) {
2974 DRM_DEBUG("DFP2 connected\n");
2975 bios_4_scratch |= RADEON_DFP2_ATTACHED;
2976 bios_5_scratch |= RADEON_DFP2_ON;
2977 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2978 } else {
2979 DRM_DEBUG("DFP2 disconnected\n");
2980 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2981 bios_5_scratch &= ~RADEON_DFP2_ON;
2982 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2983 }
2984 }
2985 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2986 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2987}
2988
2989void
2990radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2991{
2992 struct drm_device *dev = encoder->dev;
2993 struct radeon_device *rdev = dev->dev_private;
2994 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2995 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2996
2997 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2998 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2999 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3000 }
3001 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3002 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3003 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3004 }
3005 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3006 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3007 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3008 }
3009 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3010 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3011 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3012 }
3013 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3014 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3015 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3016 }
3017 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3018 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3019 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3020 }
3021 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3022}
3023
3024void
3025radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3026{
3027 struct drm_device *dev = encoder->dev;
3028 struct radeon_device *rdev = dev->dev_private;
3029 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3030 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3031
3032 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3033 if (on)
3034 bios_6_scratch |= RADEON_TV_DPMS_ON;
3035 else
3036 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3037 }
3038 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3039 if (on)
3040 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3041 else
3042 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3043 }
3044 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3045 if (on)
3046 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3047 else
3048 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3049 }
3050 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3051 if (on)
3052 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3053 else
3054 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3055 }
3056 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3057}
Linux 6.x block layer and io_uring tree(s)