Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2004 ATI Technologies Inc., Markham, Ontario | |
3 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
4 | * Copyright 2008 Red Hat Inc. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | */ | |
27 | #include "drmP.h" | |
28 | #include "radeon_drm.h" | |
29 | #include "radeon.h" | |
30 | #include "atom.h" | |
31 | ||
32 | #ifdef CONFIG_PPC_PMAC | |
33 | /* not sure which of these are needed */ | |
34 | #include <asm/machdep.h> | |
35 | #include <asm/pmac_feature.h> | |
36 | #include <asm/prom.h> | |
37 | #include <asm/pci-bridge.h> | |
38 | #endif /* CONFIG_PPC_PMAC */ | |
39 | ||
40 | /* from radeon_encoder.c */ | |
41 | extern uint32_t | |
5137ee94 AD |
42 | radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, |
43 | uint8_t dac); | |
771fe6b9 JG |
44 | extern void radeon_link_encoder_connector(struct drm_device *dev); |
45 | ||
46 | /* from radeon_connector.c */ | |
47 | extern void | |
48 | radeon_add_legacy_connector(struct drm_device *dev, | |
49 | uint32_t connector_id, | |
50 | uint32_t supported_device, | |
51 | int connector_type, | |
b75fad06 | 52 | struct radeon_i2c_bus_rec *i2c_bus, |
eed45b30 AD |
53 | uint16_t connector_object_id, |
54 | struct radeon_hpd *hpd); | |
771fe6b9 JG |
55 | |
56 | /* from radeon_legacy_encoder.c */ | |
57 | extern void | |
5137ee94 | 58 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, |
771fe6b9 JG |
59 | uint32_t supported_device); |
60 | ||
61 | /* old legacy ATI BIOS routines */ | |
62 | ||
63 | /* COMBIOS table offsets */ | |
64 | enum radeon_combios_table_offset { | |
65 | /* absolute offset tables */ | |
66 | COMBIOS_ASIC_INIT_1_TABLE, | |
67 | COMBIOS_BIOS_SUPPORT_TABLE, | |
68 | COMBIOS_DAC_PROGRAMMING_TABLE, | |
69 | COMBIOS_MAX_COLOR_DEPTH_TABLE, | |
70 | COMBIOS_CRTC_INFO_TABLE, | |
71 | COMBIOS_PLL_INFO_TABLE, | |
72 | COMBIOS_TV_INFO_TABLE, | |
73 | COMBIOS_DFP_INFO_TABLE, | |
74 | COMBIOS_HW_CONFIG_INFO_TABLE, | |
75 | COMBIOS_MULTIMEDIA_INFO_TABLE, | |
76 | COMBIOS_TV_STD_PATCH_TABLE, | |
77 | COMBIOS_LCD_INFO_TABLE, | |
78 | COMBIOS_MOBILE_INFO_TABLE, | |
79 | COMBIOS_PLL_INIT_TABLE, | |
80 | COMBIOS_MEM_CONFIG_TABLE, | |
81 | COMBIOS_SAVE_MASK_TABLE, | |
82 | COMBIOS_HARDCODED_EDID_TABLE, | |
83 | COMBIOS_ASIC_INIT_2_TABLE, | |
84 | COMBIOS_CONNECTOR_INFO_TABLE, | |
85 | COMBIOS_DYN_CLK_1_TABLE, | |
86 | COMBIOS_RESERVED_MEM_TABLE, | |
87 | COMBIOS_EXT_TMDS_INFO_TABLE, | |
88 | COMBIOS_MEM_CLK_INFO_TABLE, | |
89 | COMBIOS_EXT_DAC_INFO_TABLE, | |
90 | COMBIOS_MISC_INFO_TABLE, | |
91 | COMBIOS_CRT_INFO_TABLE, | |
92 | COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, | |
93 | COMBIOS_COMPONENT_VIDEO_INFO_TABLE, | |
94 | COMBIOS_FAN_SPEED_INFO_TABLE, | |
95 | COMBIOS_OVERDRIVE_INFO_TABLE, | |
96 | COMBIOS_OEM_INFO_TABLE, | |
97 | COMBIOS_DYN_CLK_2_TABLE, | |
98 | COMBIOS_POWER_CONNECTOR_INFO_TABLE, | |
99 | COMBIOS_I2C_INFO_TABLE, | |
100 | /* relative offset tables */ | |
101 | COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ | |
102 | COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ | |
103 | COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ | |
104 | COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ | |
105 | COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ | |
106 | COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ | |
107 | COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ | |
108 | COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ | |
109 | COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ | |
110 | COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ | |
111 | COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ | |
112 | }; | |
113 | ||
114 | enum radeon_combios_ddc { | |
115 | DDC_NONE_DETECTED, | |
116 | DDC_MONID, | |
117 | DDC_DVI, | |
118 | DDC_VGA, | |
119 | DDC_CRT2, | |
120 | DDC_LCD, | |
121 | DDC_GPIO, | |
122 | }; | |
123 | ||
124 | enum radeon_combios_connector { | |
125 | CONNECTOR_NONE_LEGACY, | |
126 | CONNECTOR_PROPRIETARY_LEGACY, | |
127 | CONNECTOR_CRT_LEGACY, | |
128 | CONNECTOR_DVI_I_LEGACY, | |
129 | CONNECTOR_DVI_D_LEGACY, | |
130 | CONNECTOR_CTV_LEGACY, | |
131 | CONNECTOR_STV_LEGACY, | |
132 | CONNECTOR_UNSUPPORTED_LEGACY | |
133 | }; | |
134 | ||
135 | const int legacy_connector_convert[] = { | |
136 | DRM_MODE_CONNECTOR_Unknown, | |
137 | DRM_MODE_CONNECTOR_DVID, | |
138 | DRM_MODE_CONNECTOR_VGA, | |
139 | DRM_MODE_CONNECTOR_DVII, | |
140 | DRM_MODE_CONNECTOR_DVID, | |
141 | DRM_MODE_CONNECTOR_Composite, | |
142 | DRM_MODE_CONNECTOR_SVIDEO, | |
143 | DRM_MODE_CONNECTOR_Unknown, | |
144 | }; | |
145 | ||
146 | static uint16_t combios_get_table_offset(struct drm_device *dev, | |
147 | enum radeon_combios_table_offset table) | |
148 | { | |
149 | struct radeon_device *rdev = dev->dev_private; | |
150 | int rev; | |
151 | uint16_t offset = 0, check_offset; | |
152 | ||
03047cdf MD |
153 | if (!rdev->bios) |
154 | return 0; | |
155 | ||
771fe6b9 JG |
156 | switch (table) { |
157 | /* absolute offset tables */ | |
158 | case COMBIOS_ASIC_INIT_1_TABLE: | |
159 | check_offset = RBIOS16(rdev->bios_header_start + 0xc); | |
160 | if (check_offset) | |
161 | offset = check_offset; | |
162 | break; | |
163 | case COMBIOS_BIOS_SUPPORT_TABLE: | |
164 | check_offset = RBIOS16(rdev->bios_header_start + 0x14); | |
165 | if (check_offset) | |
166 | offset = check_offset; | |
167 | break; | |
168 | case COMBIOS_DAC_PROGRAMMING_TABLE: | |
169 | check_offset = RBIOS16(rdev->bios_header_start + 0x2a); | |
170 | if (check_offset) | |
171 | offset = check_offset; | |
172 | break; | |
173 | case COMBIOS_MAX_COLOR_DEPTH_TABLE: | |
174 | check_offset = RBIOS16(rdev->bios_header_start + 0x2c); | |
175 | if (check_offset) | |
176 | offset = check_offset; | |
177 | break; | |
178 | case COMBIOS_CRTC_INFO_TABLE: | |
179 | check_offset = RBIOS16(rdev->bios_header_start + 0x2e); | |
180 | if (check_offset) | |
181 | offset = check_offset; | |
182 | break; | |
183 | case COMBIOS_PLL_INFO_TABLE: | |
184 | check_offset = RBIOS16(rdev->bios_header_start + 0x30); | |
185 | if (check_offset) | |
186 | offset = check_offset; | |
187 | break; | |
188 | case COMBIOS_TV_INFO_TABLE: | |
189 | check_offset = RBIOS16(rdev->bios_header_start + 0x32); | |
190 | if (check_offset) | |
191 | offset = check_offset; | |
192 | break; | |
193 | case COMBIOS_DFP_INFO_TABLE: | |
194 | check_offset = RBIOS16(rdev->bios_header_start + 0x34); | |
195 | if (check_offset) | |
196 | offset = check_offset; | |
197 | break; | |
198 | case COMBIOS_HW_CONFIG_INFO_TABLE: | |
199 | check_offset = RBIOS16(rdev->bios_header_start + 0x36); | |
200 | if (check_offset) | |
201 | offset = check_offset; | |
202 | break; | |
203 | case COMBIOS_MULTIMEDIA_INFO_TABLE: | |
204 | check_offset = RBIOS16(rdev->bios_header_start + 0x38); | |
205 | if (check_offset) | |
206 | offset = check_offset; | |
207 | break; | |
208 | case COMBIOS_TV_STD_PATCH_TABLE: | |
209 | check_offset = RBIOS16(rdev->bios_header_start + 0x3e); | |
210 | if (check_offset) | |
211 | offset = check_offset; | |
212 | break; | |
213 | case COMBIOS_LCD_INFO_TABLE: | |
214 | check_offset = RBIOS16(rdev->bios_header_start + 0x40); | |
215 | if (check_offset) | |
216 | offset = check_offset; | |
217 | break; | |
218 | case COMBIOS_MOBILE_INFO_TABLE: | |
219 | check_offset = RBIOS16(rdev->bios_header_start + 0x42); | |
220 | if (check_offset) | |
221 | offset = check_offset; | |
222 | break; | |
223 | case COMBIOS_PLL_INIT_TABLE: | |
224 | check_offset = RBIOS16(rdev->bios_header_start + 0x46); | |
225 | if (check_offset) | |
226 | offset = check_offset; | |
227 | break; | |
228 | case COMBIOS_MEM_CONFIG_TABLE: | |
229 | check_offset = RBIOS16(rdev->bios_header_start + 0x48); | |
230 | if (check_offset) | |
231 | offset = check_offset; | |
232 | break; | |
233 | case COMBIOS_SAVE_MASK_TABLE: | |
234 | check_offset = RBIOS16(rdev->bios_header_start + 0x4a); | |
235 | if (check_offset) | |
236 | offset = check_offset; | |
237 | break; | |
238 | case COMBIOS_HARDCODED_EDID_TABLE: | |
239 | check_offset = RBIOS16(rdev->bios_header_start + 0x4c); | |
240 | if (check_offset) | |
241 | offset = check_offset; | |
242 | break; | |
243 | case COMBIOS_ASIC_INIT_2_TABLE: | |
244 | check_offset = RBIOS16(rdev->bios_header_start + 0x4e); | |
245 | if (check_offset) | |
246 | offset = check_offset; | |
247 | break; | |
248 | case COMBIOS_CONNECTOR_INFO_TABLE: | |
249 | check_offset = RBIOS16(rdev->bios_header_start + 0x50); | |
250 | if (check_offset) | |
251 | offset = check_offset; | |
252 | break; | |
253 | case COMBIOS_DYN_CLK_1_TABLE: | |
254 | check_offset = RBIOS16(rdev->bios_header_start + 0x52); | |
255 | if (check_offset) | |
256 | offset = check_offset; | |
257 | break; | |
258 | case COMBIOS_RESERVED_MEM_TABLE: | |
259 | check_offset = RBIOS16(rdev->bios_header_start + 0x54); | |
260 | if (check_offset) | |
261 | offset = check_offset; | |
262 | break; | |
263 | case COMBIOS_EXT_TMDS_INFO_TABLE: | |
264 | check_offset = RBIOS16(rdev->bios_header_start + 0x58); | |
265 | if (check_offset) | |
266 | offset = check_offset; | |
267 | break; | |
268 | case COMBIOS_MEM_CLK_INFO_TABLE: | |
269 | check_offset = RBIOS16(rdev->bios_header_start + 0x5a); | |
270 | if (check_offset) | |
271 | offset = check_offset; | |
272 | break; | |
273 | case COMBIOS_EXT_DAC_INFO_TABLE: | |
274 | check_offset = RBIOS16(rdev->bios_header_start + 0x5c); | |
275 | if (check_offset) | |
276 | offset = check_offset; | |
277 | break; | |
278 | case COMBIOS_MISC_INFO_TABLE: | |
279 | check_offset = RBIOS16(rdev->bios_header_start + 0x5e); | |
280 | if (check_offset) | |
281 | offset = check_offset; | |
282 | break; | |
283 | case COMBIOS_CRT_INFO_TABLE: | |
284 | check_offset = RBIOS16(rdev->bios_header_start + 0x60); | |
285 | if (check_offset) | |
286 | offset = check_offset; | |
287 | break; | |
288 | case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: | |
289 | check_offset = RBIOS16(rdev->bios_header_start + 0x62); | |
290 | if (check_offset) | |
291 | offset = check_offset; | |
292 | break; | |
293 | case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: | |
294 | check_offset = RBIOS16(rdev->bios_header_start + 0x64); | |
295 | if (check_offset) | |
296 | offset = check_offset; | |
297 | break; | |
298 | case COMBIOS_FAN_SPEED_INFO_TABLE: | |
299 | check_offset = RBIOS16(rdev->bios_header_start + 0x66); | |
300 | if (check_offset) | |
301 | offset = check_offset; | |
302 | break; | |
303 | case COMBIOS_OVERDRIVE_INFO_TABLE: | |
304 | check_offset = RBIOS16(rdev->bios_header_start + 0x68); | |
305 | if (check_offset) | |
306 | offset = check_offset; | |
307 | break; | |
308 | case COMBIOS_OEM_INFO_TABLE: | |
309 | check_offset = RBIOS16(rdev->bios_header_start + 0x6a); | |
310 | if (check_offset) | |
311 | offset = check_offset; | |
312 | break; | |
313 | case COMBIOS_DYN_CLK_2_TABLE: | |
314 | check_offset = RBIOS16(rdev->bios_header_start + 0x6c); | |
315 | if (check_offset) | |
316 | offset = check_offset; | |
317 | break; | |
318 | case COMBIOS_POWER_CONNECTOR_INFO_TABLE: | |
319 | check_offset = RBIOS16(rdev->bios_header_start + 0x6e); | |
320 | if (check_offset) | |
321 | offset = check_offset; | |
322 | break; | |
323 | case COMBIOS_I2C_INFO_TABLE: | |
324 | check_offset = RBIOS16(rdev->bios_header_start + 0x70); | |
325 | if (check_offset) | |
326 | offset = check_offset; | |
327 | break; | |
328 | /* relative offset tables */ | |
329 | case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ | |
330 | check_offset = | |
331 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); | |
332 | if (check_offset) { | |
333 | rev = RBIOS8(check_offset); | |
334 | if (rev > 0) { | |
335 | check_offset = RBIOS16(check_offset + 0x3); | |
336 | if (check_offset) | |
337 | offset = check_offset; | |
338 | } | |
339 | } | |
340 | break; | |
341 | case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ | |
342 | check_offset = | |
343 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); | |
344 | if (check_offset) { | |
345 | rev = RBIOS8(check_offset); | |
346 | if (rev > 0) { | |
347 | check_offset = RBIOS16(check_offset + 0x5); | |
348 | if (check_offset) | |
349 | offset = check_offset; | |
350 | } | |
351 | } | |
352 | break; | |
353 | case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ | |
354 | check_offset = | |
355 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); | |
356 | if (check_offset) { | |
357 | rev = RBIOS8(check_offset); | |
358 | if (rev > 0) { | |
359 | check_offset = RBIOS16(check_offset + 0x7); | |
360 | if (check_offset) | |
361 | offset = check_offset; | |
362 | } | |
363 | } | |
364 | break; | |
365 | case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ | |
366 | check_offset = | |
367 | combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); | |
368 | if (check_offset) { | |
369 | rev = RBIOS8(check_offset); | |
370 | if (rev == 2) { | |
371 | check_offset = RBIOS16(check_offset + 0x9); | |
372 | if (check_offset) | |
373 | offset = check_offset; | |
374 | } | |
375 | } | |
376 | break; | |
377 | case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ | |
378 | check_offset = | |
379 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); | |
380 | if (check_offset) { | |
381 | while (RBIOS8(check_offset++)); | |
382 | check_offset += 2; | |
383 | if (check_offset) | |
384 | offset = check_offset; | |
385 | } | |
386 | break; | |
387 | case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ | |
388 | check_offset = | |
389 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); | |
390 | if (check_offset) { | |
391 | check_offset = RBIOS16(check_offset + 0x11); | |
392 | if (check_offset) | |
393 | offset = check_offset; | |
394 | } | |
395 | break; | |
396 | case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ | |
397 | check_offset = | |
398 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); | |
399 | if (check_offset) { | |
400 | check_offset = RBIOS16(check_offset + 0x13); | |
401 | if (check_offset) | |
402 | offset = check_offset; | |
403 | } | |
404 | break; | |
405 | case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ | |
406 | check_offset = | |
407 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); | |
408 | if (check_offset) { | |
409 | check_offset = RBIOS16(check_offset + 0x15); | |
410 | if (check_offset) | |
411 | offset = check_offset; | |
412 | } | |
413 | break; | |
414 | case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ | |
415 | check_offset = | |
416 | combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); | |
417 | if (check_offset) { | |
418 | check_offset = RBIOS16(check_offset + 0x17); | |
419 | if (check_offset) | |
420 | offset = check_offset; | |
421 | } | |
422 | break; | |
423 | case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ | |
424 | check_offset = | |
425 | combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); | |
426 | if (check_offset) { | |
427 | check_offset = RBIOS16(check_offset + 0x2); | |
428 | if (check_offset) | |
429 | offset = check_offset; | |
430 | } | |
431 | break; | |
432 | case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ | |
433 | check_offset = | |
434 | combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); | |
435 | if (check_offset) { | |
436 | check_offset = RBIOS16(check_offset + 0x4); | |
437 | if (check_offset) | |
438 | offset = check_offset; | |
439 | } | |
440 | break; | |
441 | default: | |
442 | break; | |
443 | } | |
444 | ||
445 | return offset; | |
446 | ||
447 | } | |
448 | ||
3c537889 AD |
449 | bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) |
450 | { | |
fafcf94e | 451 | int edid_info, size; |
3c537889 | 452 | struct edid *edid; |
7466f4cc | 453 | unsigned char *raw; |
3c537889 AD |
454 | edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); |
455 | if (!edid_info) | |
456 | return false; | |
457 | ||
7466f4cc | 458 | raw = rdev->bios + edid_info; |
fafcf94e AD |
459 | size = EDID_LENGTH * (raw[0x7e] + 1); |
460 | edid = kmalloc(size, GFP_KERNEL); | |
3c537889 AD |
461 | if (edid == NULL) |
462 | return false; | |
463 | ||
fafcf94e | 464 | memcpy((unsigned char *)edid, raw, size); |
3c537889 AD |
465 | |
466 | if (!drm_edid_is_valid(edid)) { | |
467 | kfree(edid); | |
468 | return false; | |
469 | } | |
470 | ||
471 | rdev->mode_info.bios_hardcoded_edid = edid; | |
fafcf94e | 472 | rdev->mode_info.bios_hardcoded_edid_size = size; |
3c537889 AD |
473 | return true; |
474 | } | |
475 | ||
c324acd5 | 476 | /* this is used for atom LCDs as well */ |
3c537889 | 477 | struct edid * |
c324acd5 | 478 | radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) |
3c537889 | 479 | { |
fafcf94e AD |
480 | struct edid *edid; |
481 | ||
482 | if (rdev->mode_info.bios_hardcoded_edid) { | |
483 | edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); | |
484 | if (edid) { | |
485 | memcpy((unsigned char *)edid, | |
486 | (unsigned char *)rdev->mode_info.bios_hardcoded_edid, | |
487 | rdev->mode_info.bios_hardcoded_edid_size); | |
488 | return edid; | |
489 | } | |
490 | } | |
3c537889 AD |
491 | return NULL; |
492 | } | |
493 | ||
6a93cb25 | 494 | static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, |
179e8078 AD |
495 | enum radeon_combios_ddc ddc, |
496 | u32 clk_mask, | |
497 | u32 data_mask) | |
771fe6b9 JG |
498 | { |
499 | struct radeon_i2c_bus_rec i2c; | |
179e8078 AD |
500 | int ddc_line = 0; |
501 | ||
502 | /* ddc id = mask reg | |
503 | * DDC_NONE_DETECTED = none | |
504 | * DDC_DVI = RADEON_GPIO_DVI_DDC | |
505 | * DDC_VGA = RADEON_GPIO_VGA_DDC | |
506 | * DDC_LCD = RADEON_GPIOPAD_MASK | |
507 | * DDC_GPIO = RADEON_MDGPIO_MASK | |
508c8d60 | 508 | * r1xx |
179e8078 AD |
509 | * DDC_MONID = RADEON_GPIO_MONID |
510 | * DDC_CRT2 = RADEON_GPIO_CRT2_DDC | |
508c8d60 | 511 | * r200 |
179e8078 AD |
512 | * DDC_MONID = RADEON_GPIO_MONID |
513 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC | |
508c8d60 AD |
514 | * r300/r350 |
515 | * DDC_MONID = RADEON_GPIO_DVI_DDC | |
516 | * DDC_CRT2 = RADEON_GPIO_DVI_DDC | |
517 | * rv2xx/rv3xx | |
518 | * DDC_MONID = RADEON_GPIO_MONID | |
519 | * DDC_CRT2 = RADEON_GPIO_MONID | |
179e8078 AD |
520 | * rs3xx/rs4xx |
521 | * DDC_MONID = RADEON_GPIOPAD_MASK | |
522 | * DDC_CRT2 = RADEON_GPIO_MONID | |
523 | */ | |
524 | switch (ddc) { | |
525 | case DDC_NONE_DETECTED: | |
526 | default: | |
527 | ddc_line = 0; | |
528 | break; | |
529 | case DDC_DVI: | |
530 | ddc_line = RADEON_GPIO_DVI_DDC; | |
531 | break; | |
532 | case DDC_VGA: | |
533 | ddc_line = RADEON_GPIO_VGA_DDC; | |
534 | break; | |
535 | case DDC_LCD: | |
536 | ddc_line = RADEON_GPIOPAD_MASK; | |
537 | break; | |
538 | case DDC_GPIO: | |
539 | ddc_line = RADEON_MDGPIO_MASK; | |
540 | break; | |
541 | case DDC_MONID: | |
542 | if (rdev->family == CHIP_RS300 || | |
543 | rdev->family == CHIP_RS400 || | |
544 | rdev->family == CHIP_RS480) | |
545 | ddc_line = RADEON_GPIOPAD_MASK; | |
508c8d60 | 546 | else if (rdev->family == CHIP_R300 || |
776f2b7c | 547 | rdev->family == CHIP_R350) { |
508c8d60 | 548 | ddc_line = RADEON_GPIO_DVI_DDC; |
776f2b7c AD |
549 | ddc = DDC_DVI; |
550 | } else | |
179e8078 AD |
551 | ddc_line = RADEON_GPIO_MONID; |
552 | break; | |
553 | case DDC_CRT2: | |
508c8d60 AD |
554 | if (rdev->family == CHIP_R200 || |
555 | rdev->family == CHIP_R300 || | |
776f2b7c | 556 | rdev->family == CHIP_R350) { |
179e8078 | 557 | ddc_line = RADEON_GPIO_DVI_DDC; |
776f2b7c AD |
558 | ddc = DDC_DVI; |
559 | } else if (rdev->family == CHIP_RS300 || | |
560 | rdev->family == CHIP_RS400 || | |
561 | rdev->family == CHIP_RS480) | |
508c8d60 | 562 | ddc_line = RADEON_GPIO_MONID; |
776f2b7c AD |
563 | else if (rdev->family >= CHIP_RV350) { |
564 | ddc_line = RADEON_GPIO_MONID; | |
565 | ddc = DDC_MONID; | |
566 | } else | |
179e8078 AD |
567 | ddc_line = RADEON_GPIO_CRT2_DDC; |
568 | break; | |
569 | } | |
771fe6b9 | 570 | |
6a93cb25 AD |
571 | if (ddc_line == RADEON_GPIOPAD_MASK) { |
572 | i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; | |
573 | i2c.mask_data_reg = RADEON_GPIOPAD_MASK; | |
574 | i2c.a_clk_reg = RADEON_GPIOPAD_A; | |
575 | i2c.a_data_reg = RADEON_GPIOPAD_A; | |
576 | i2c.en_clk_reg = RADEON_GPIOPAD_EN; | |
577 | i2c.en_data_reg = RADEON_GPIOPAD_EN; | |
578 | i2c.y_clk_reg = RADEON_GPIOPAD_Y; | |
579 | i2c.y_data_reg = RADEON_GPIOPAD_Y; | |
580 | } else if (ddc_line == RADEON_MDGPIO_MASK) { | |
581 | i2c.mask_clk_reg = RADEON_MDGPIO_MASK; | |
582 | i2c.mask_data_reg = RADEON_MDGPIO_MASK; | |
583 | i2c.a_clk_reg = RADEON_MDGPIO_A; | |
584 | i2c.a_data_reg = RADEON_MDGPIO_A; | |
585 | i2c.en_clk_reg = RADEON_MDGPIO_EN; | |
586 | i2c.en_data_reg = RADEON_MDGPIO_EN; | |
587 | i2c.y_clk_reg = RADEON_MDGPIO_Y; | |
588 | i2c.y_data_reg = RADEON_MDGPIO_Y; | |
771fe6b9 JG |
589 | } else { |
590 | i2c.mask_clk_reg = ddc_line; | |
591 | i2c.mask_data_reg = ddc_line; | |
592 | i2c.a_clk_reg = ddc_line; | |
593 | i2c.a_data_reg = ddc_line; | |
9b9fe724 AD |
594 | i2c.en_clk_reg = ddc_line; |
595 | i2c.en_data_reg = ddc_line; | |
596 | i2c.y_clk_reg = ddc_line; | |
597 | i2c.y_data_reg = ddc_line; | |
771fe6b9 JG |
598 | } |
599 | ||
179e8078 | 600 | if (clk_mask && data_mask) { |
be663057 | 601 | /* system specific masks */ |
179e8078 AD |
602 | i2c.mask_clk_mask = clk_mask; |
603 | i2c.mask_data_mask = data_mask; | |
604 | i2c.a_clk_mask = clk_mask; | |
605 | i2c.a_data_mask = data_mask; | |
606 | i2c.en_clk_mask = clk_mask; | |
607 | i2c.en_data_mask = data_mask; | |
608 | i2c.y_clk_mask = clk_mask; | |
609 | i2c.y_data_mask = data_mask; | |
be663057 AD |
610 | } else if ((ddc_line == RADEON_GPIOPAD_MASK) || |
611 | (ddc_line == RADEON_MDGPIO_MASK)) { | |
612 | /* default gpiopad masks */ | |
613 | i2c.mask_clk_mask = (0x20 << 8); | |
614 | i2c.mask_data_mask = 0x80; | |
615 | i2c.a_clk_mask = (0x20 << 8); | |
616 | i2c.a_data_mask = 0x80; | |
617 | i2c.en_clk_mask = (0x20 << 8); | |
618 | i2c.en_data_mask = 0x80; | |
619 | i2c.y_clk_mask = (0x20 << 8); | |
620 | i2c.y_data_mask = 0x80; | |
179e8078 | 621 | } else { |
be663057 | 622 | /* default masks for ddc pads */ |
286e0c94 JD |
623 | i2c.mask_clk_mask = RADEON_GPIO_MASK_1; |
624 | i2c.mask_data_mask = RADEON_GPIO_MASK_0; | |
179e8078 AD |
625 | i2c.a_clk_mask = RADEON_GPIO_A_1; |
626 | i2c.a_data_mask = RADEON_GPIO_A_0; | |
627 | i2c.en_clk_mask = RADEON_GPIO_EN_1; | |
628 | i2c.en_data_mask = RADEON_GPIO_EN_0; | |
629 | i2c.y_clk_mask = RADEON_GPIO_Y_1; | |
630 | i2c.y_data_mask = RADEON_GPIO_Y_0; | |
631 | } | |
632 | ||
40bacf16 AD |
633 | switch (rdev->family) { |
634 | case CHIP_R100: | |
635 | case CHIP_RV100: | |
636 | case CHIP_RS100: | |
637 | case CHIP_RV200: | |
638 | case CHIP_RS200: | |
639 | case CHIP_RS300: | |
640 | switch (ddc_line) { | |
641 | case RADEON_GPIO_DVI_DDC: | |
b28ea411 | 642 | i2c.hw_capable = true; |
40bacf16 AD |
643 | break; |
644 | default: | |
645 | i2c.hw_capable = false; | |
646 | break; | |
647 | } | |
648 | break; | |
649 | case CHIP_R200: | |
650 | switch (ddc_line) { | |
651 | case RADEON_GPIO_DVI_DDC: | |
652 | case RADEON_GPIO_MONID: | |
653 | i2c.hw_capable = true; | |
654 | break; | |
655 | default: | |
656 | i2c.hw_capable = false; | |
657 | break; | |
658 | } | |
659 | break; | |
660 | case CHIP_RV250: | |
661 | case CHIP_RV280: | |
662 | switch (ddc_line) { | |
663 | case RADEON_GPIO_VGA_DDC: | |
664 | case RADEON_GPIO_DVI_DDC: | |
665 | case RADEON_GPIO_CRT2_DDC: | |
666 | i2c.hw_capable = true; | |
667 | break; | |
668 | default: | |
669 | i2c.hw_capable = false; | |
670 | break; | |
671 | } | |
672 | break; | |
673 | case CHIP_R300: | |
674 | case CHIP_R350: | |
675 | switch (ddc_line) { | |
676 | case RADEON_GPIO_VGA_DDC: | |
677 | case RADEON_GPIO_DVI_DDC: | |
678 | i2c.hw_capable = true; | |
679 | break; | |
680 | default: | |
681 | i2c.hw_capable = false; | |
682 | break; | |
683 | } | |
684 | break; | |
685 | case CHIP_RV350: | |
686 | case CHIP_RV380: | |
687 | case CHIP_RS400: | |
688 | case CHIP_RS480: | |
6a93cb25 AD |
689 | switch (ddc_line) { |
690 | case RADEON_GPIO_VGA_DDC: | |
691 | case RADEON_GPIO_DVI_DDC: | |
692 | i2c.hw_capable = true; | |
693 | break; | |
694 | case RADEON_GPIO_MONID: | |
695 | /* hw i2c on RADEON_GPIO_MONID doesn't seem to work | |
696 | * reliably on some pre-r4xx hardware; not sure why. | |
697 | */ | |
698 | i2c.hw_capable = false; | |
699 | break; | |
700 | default: | |
701 | i2c.hw_capable = false; | |
702 | break; | |
703 | } | |
40bacf16 AD |
704 | break; |
705 | default: | |
706 | i2c.hw_capable = false; | |
707 | break; | |
6a93cb25 AD |
708 | } |
709 | i2c.mm_i2c = false; | |
f376b94f | 710 | |
179e8078 | 711 | i2c.i2c_id = ddc; |
8e36ed00 | 712 | i2c.hpd = RADEON_HPD_NONE; |
6a93cb25 | 713 | |
771fe6b9 JG |
714 | if (ddc_line) |
715 | i2c.valid = true; | |
716 | else | |
717 | i2c.valid = false; | |
718 | ||
719 | return i2c; | |
720 | } | |
721 | ||
f376b94f AD |
722 | void radeon_combios_i2c_init(struct radeon_device *rdev) |
723 | { | |
724 | struct drm_device *dev = rdev->ddev; | |
725 | struct radeon_i2c_bus_rec i2c; | |
726 | ||
508c8d60 AD |
727 | /* actual hw pads |
728 | * r1xx/rs2xx/rs3xx | |
729 | * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm | |
730 | * r200 | |
731 | * 0x60, 0x64, 0x68, mm | |
732 | * r300/r350 | |
733 | * 0x60, 0x64, mm | |
734 | * rv2xx/rv3xx/rs4xx | |
735 | * 0x60, 0x64, 0x68, gpiopads, mm | |
736 | */ | |
f376b94f | 737 | |
508c8d60 | 738 | /* 0x60 */ |
179e8078 AD |
739 | i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
740 | rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); | |
508c8d60 | 741 | /* 0x64 */ |
179e8078 AD |
742 | i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
743 | rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); | |
f376b94f | 744 | |
508c8d60 | 745 | /* mm i2c */ |
f376b94f AD |
746 | i2c.valid = true; |
747 | i2c.hw_capable = true; | |
748 | i2c.mm_i2c = true; | |
179e8078 AD |
749 | i2c.i2c_id = 0xa0; |
750 | rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); | |
751 | ||
508c8d60 AD |
752 | if (rdev->family == CHIP_R300 || |
753 | rdev->family == CHIP_R350) { | |
754 | /* only 2 sw i2c pads */ | |
755 | } else if (rdev->family == CHIP_RS300 || | |
756 | rdev->family == CHIP_RS400 || | |
757 | rdev->family == CHIP_RS480) { | |
179e8078 AD |
758 | u16 offset; |
759 | u8 id, blocks, clk, data; | |
760 | int i; | |
761 | ||
508c8d60 | 762 | /* 0x68 */ |
179e8078 AD |
763 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
764 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); | |
765 | ||
766 | offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); | |
767 | if (offset) { | |
768 | blocks = RBIOS8(offset + 2); | |
769 | for (i = 0; i < blocks; i++) { | |
770 | id = RBIOS8(offset + 3 + (i * 5) + 0); | |
771 | if (id == 136) { | |
772 | clk = RBIOS8(offset + 3 + (i * 5) + 3); | |
773 | data = RBIOS8(offset + 3 + (i * 5) + 4); | |
508c8d60 | 774 | /* gpiopad */ |
179e8078 | 775 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, |
791cfe26 | 776 | (1 << clk), (1 << data)); |
179e8078 AD |
777 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); |
778 | break; | |
779 | } | |
780 | } | |
781 | } | |
6dd66633 AD |
782 | } else if ((rdev->family == CHIP_R200) || |
783 | (rdev->family >= CHIP_R300)) { | |
508c8d60 | 784 | /* 0x68 */ |
179e8078 AD |
785 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
786 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); | |
787 | } else { | |
508c8d60 | 788 | /* 0x68 */ |
179e8078 AD |
789 | i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
790 | rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); | |
508c8d60 | 791 | /* 0x6c */ |
179e8078 AD |
792 | i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
793 | rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); | |
794 | } | |
f376b94f AD |
795 | } |
796 | ||
771fe6b9 JG |
797 | bool radeon_combios_get_clock_info(struct drm_device *dev) |
798 | { | |
799 | struct radeon_device *rdev = dev->dev_private; | |
800 | uint16_t pll_info; | |
801 | struct radeon_pll *p1pll = &rdev->clock.p1pll; | |
802 | struct radeon_pll *p2pll = &rdev->clock.p2pll; | |
803 | struct radeon_pll *spll = &rdev->clock.spll; | |
804 | struct radeon_pll *mpll = &rdev->clock.mpll; | |
805 | int8_t rev; | |
806 | uint16_t sclk, mclk; | |
807 | ||
771fe6b9 JG |
808 | pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); |
809 | if (pll_info) { | |
810 | rev = RBIOS8(pll_info); | |
811 | ||
812 | /* pixel clocks */ | |
813 | p1pll->reference_freq = RBIOS16(pll_info + 0xe); | |
814 | p1pll->reference_div = RBIOS16(pll_info + 0x10); | |
815 | p1pll->pll_out_min = RBIOS32(pll_info + 0x12); | |
816 | p1pll->pll_out_max = RBIOS32(pll_info + 0x16); | |
86cb2bbf AD |
817 | p1pll->lcd_pll_out_min = p1pll->pll_out_min; |
818 | p1pll->lcd_pll_out_max = p1pll->pll_out_max; | |
771fe6b9 JG |
819 | |
820 | if (rev > 9) { | |
821 | p1pll->pll_in_min = RBIOS32(pll_info + 0x36); | |
822 | p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); | |
823 | } else { | |
824 | p1pll->pll_in_min = 40; | |
825 | p1pll->pll_in_max = 500; | |
826 | } | |
827 | *p2pll = *p1pll; | |
828 | ||
829 | /* system clock */ | |
830 | spll->reference_freq = RBIOS16(pll_info + 0x1a); | |
831 | spll->reference_div = RBIOS16(pll_info + 0x1c); | |
832 | spll->pll_out_min = RBIOS32(pll_info + 0x1e); | |
833 | spll->pll_out_max = RBIOS32(pll_info + 0x22); | |
834 | ||
835 | if (rev > 10) { | |
836 | spll->pll_in_min = RBIOS32(pll_info + 0x48); | |
837 | spll->pll_in_max = RBIOS32(pll_info + 0x4c); | |
838 | } else { | |
839 | /* ??? */ | |
840 | spll->pll_in_min = 40; | |
841 | spll->pll_in_max = 500; | |
842 | } | |
843 | ||
844 | /* memory clock */ | |
845 | mpll->reference_freq = RBIOS16(pll_info + 0x26); | |
846 | mpll->reference_div = RBIOS16(pll_info + 0x28); | |
847 | mpll->pll_out_min = RBIOS32(pll_info + 0x2a); | |
848 | mpll->pll_out_max = RBIOS32(pll_info + 0x2e); | |
849 | ||
850 | if (rev > 10) { | |
851 | mpll->pll_in_min = RBIOS32(pll_info + 0x5a); | |
852 | mpll->pll_in_max = RBIOS32(pll_info + 0x5e); | |
853 | } else { | |
854 | /* ??? */ | |
855 | mpll->pll_in_min = 40; | |
856 | mpll->pll_in_max = 500; | |
857 | } | |
858 | ||
859 | /* default sclk/mclk */ | |
860 | sclk = RBIOS16(pll_info + 0xa); | |
861 | mclk = RBIOS16(pll_info + 0x8); | |
862 | if (sclk == 0) | |
863 | sclk = 200 * 100; | |
864 | if (mclk == 0) | |
865 | mclk = 200 * 100; | |
866 | ||
867 | rdev->clock.default_sclk = sclk; | |
868 | rdev->clock.default_mclk = mclk; | |
869 | ||
b20f9bef AD |
870 | if (RBIOS32(pll_info + 0x16)) |
871 | rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); | |
872 | else | |
873 | rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ | |
874 | ||
771fe6b9 JG |
875 | return true; |
876 | } | |
877 | return false; | |
878 | } | |
879 | ||
06b6476d AD |
880 | bool radeon_combios_sideport_present(struct radeon_device *rdev) |
881 | { | |
882 | struct drm_device *dev = rdev->ddev; | |
883 | u16 igp_info; | |
884 | ||
4c70b2ea AD |
885 | /* sideport is AMD only */ |
886 | if (rdev->family == CHIP_RS400) | |
887 | return false; | |
888 | ||
06b6476d AD |
889 | igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); |
890 | ||
891 | if (igp_info) { | |
892 | if (RBIOS16(igp_info + 0x4)) | |
893 | return true; | |
894 | } | |
895 | return false; | |
896 | } | |
897 | ||
246263cc AD |
898 | static const uint32_t default_primarydac_adj[CHIP_LAST] = { |
899 | 0x00000808, /* r100 */ | |
900 | 0x00000808, /* rv100 */ | |
901 | 0x00000808, /* rs100 */ | |
902 | 0x00000808, /* rv200 */ | |
903 | 0x00000808, /* rs200 */ | |
904 | 0x00000808, /* r200 */ | |
905 | 0x00000808, /* rv250 */ | |
906 | 0x00000000, /* rs300 */ | |
907 | 0x00000808, /* rv280 */ | |
908 | 0x00000808, /* r300 */ | |
909 | 0x00000808, /* r350 */ | |
910 | 0x00000808, /* rv350 */ | |
911 | 0x00000808, /* rv380 */ | |
912 | 0x00000808, /* r420 */ | |
913 | 0x00000808, /* r423 */ | |
914 | 0x00000808, /* rv410 */ | |
915 | 0x00000000, /* rs400 */ | |
916 | 0x00000000, /* rs480 */ | |
917 | }; | |
918 | ||
919 | static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, | |
920 | struct radeon_encoder_primary_dac *p_dac) | |
921 | { | |
922 | p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; | |
923 | return; | |
924 | } | |
925 | ||
771fe6b9 JG |
926 | struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct |
927 | radeon_encoder | |
928 | *encoder) | |
929 | { | |
930 | struct drm_device *dev = encoder->base.dev; | |
931 | struct radeon_device *rdev = dev->dev_private; | |
932 | uint16_t dac_info; | |
933 | uint8_t rev, bg, dac; | |
934 | struct radeon_encoder_primary_dac *p_dac = NULL; | |
246263cc | 935 | int found = 0; |
771fe6b9 | 936 | |
246263cc AD |
937 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), |
938 | GFP_KERNEL); | |
939 | ||
940 | if (!p_dac) | |
771fe6b9 JG |
941 | return NULL; |
942 | ||
943 | /* check CRT table */ | |
944 | dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); | |
945 | if (dac_info) { | |
771fe6b9 JG |
946 | rev = RBIOS8(dac_info) & 0x3; |
947 | if (rev < 2) { | |
948 | bg = RBIOS8(dac_info + 0x2) & 0xf; | |
949 | dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; | |
950 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); | |
951 | } else { | |
952 | bg = RBIOS8(dac_info + 0x2) & 0xf; | |
953 | dac = RBIOS8(dac_info + 0x3) & 0xf; | |
954 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); | |
955 | } | |
3a89b4a9 AD |
956 | /* if the values are all zeros, use the table */ |
957 | if (p_dac->ps2_pdac_adj) | |
958 | found = 1; | |
771fe6b9 JG |
959 | } |
960 | ||
246263cc AD |
961 | if (!found) /* fallback to defaults */ |
962 | radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); | |
963 | ||
771fe6b9 JG |
964 | return p_dac; |
965 | } | |
966 | ||
d79766fa AD |
967 | enum radeon_tv_std |
968 | radeon_combios_get_tv_info(struct radeon_device *rdev) | |
771fe6b9 | 969 | { |
d79766fa | 970 | struct drm_device *dev = rdev->ddev; |
771fe6b9 JG |
971 | uint16_t tv_info; |
972 | enum radeon_tv_std tv_std = TV_STD_NTSC; | |
973 | ||
974 | tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); | |
975 | if (tv_info) { | |
976 | if (RBIOS8(tv_info + 6) == 'T') { | |
977 | switch (RBIOS8(tv_info + 7) & 0xf) { | |
978 | case 1: | |
979 | tv_std = TV_STD_NTSC; | |
40f76d81 | 980 | DRM_DEBUG_KMS("Default TV standard: NTSC\n"); |
771fe6b9 JG |
981 | break; |
982 | case 2: | |
983 | tv_std = TV_STD_PAL; | |
40f76d81 | 984 | DRM_DEBUG_KMS("Default TV standard: PAL\n"); |
771fe6b9 JG |
985 | break; |
986 | case 3: | |
987 | tv_std = TV_STD_PAL_M; | |
40f76d81 | 988 | DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); |
771fe6b9 JG |
989 | break; |
990 | case 4: | |
991 | tv_std = TV_STD_PAL_60; | |
40f76d81 | 992 | DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); |
771fe6b9 JG |
993 | break; |
994 | case 5: | |
995 | tv_std = TV_STD_NTSC_J; | |
40f76d81 | 996 | DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); |
771fe6b9 JG |
997 | break; |
998 | case 6: | |
999 | tv_std = TV_STD_SCART_PAL; | |
40f76d81 | 1000 | DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); |
771fe6b9 JG |
1001 | break; |
1002 | default: | |
1003 | tv_std = TV_STD_NTSC; | |
40f76d81 | 1004 | DRM_DEBUG_KMS |
771fe6b9 JG |
1005 | ("Unknown TV standard; defaulting to NTSC\n"); |
1006 | break; | |
1007 | } | |
1008 | ||
1009 | switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { | |
1010 | case 0: | |
40f76d81 | 1011 | DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); |
771fe6b9 JG |
1012 | break; |
1013 | case 1: | |
40f76d81 | 1014 | DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); |
771fe6b9 JG |
1015 | break; |
1016 | case 2: | |
40f76d81 | 1017 | DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); |
771fe6b9 JG |
1018 | break; |
1019 | case 3: | |
40f76d81 | 1020 | DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); |
771fe6b9 JG |
1021 | break; |
1022 | default: | |
1023 | break; | |
1024 | } | |
1025 | } | |
1026 | } | |
1027 | return tv_std; | |
1028 | } | |
1029 | ||
1030 | static const uint32_t default_tvdac_adj[CHIP_LAST] = { | |
1031 | 0x00000000, /* r100 */ | |
1032 | 0x00280000, /* rv100 */ | |
1033 | 0x00000000, /* rs100 */ | |
1034 | 0x00880000, /* rv200 */ | |
1035 | 0x00000000, /* rs200 */ | |
1036 | 0x00000000, /* r200 */ | |
1037 | 0x00770000, /* rv250 */ | |
1038 | 0x00290000, /* rs300 */ | |
1039 | 0x00560000, /* rv280 */ | |
1040 | 0x00780000, /* r300 */ | |
1041 | 0x00770000, /* r350 */ | |
1042 | 0x00780000, /* rv350 */ | |
1043 | 0x00780000, /* rv380 */ | |
1044 | 0x01080000, /* r420 */ | |
1045 | 0x01080000, /* r423 */ | |
1046 | 0x01080000, /* rv410 */ | |
1047 | 0x00780000, /* rs400 */ | |
1048 | 0x00780000, /* rs480 */ | |
1049 | }; | |
1050 | ||
6a719e05 DA |
1051 | static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, |
1052 | struct radeon_encoder_tv_dac *tv_dac) | |
771fe6b9 | 1053 | { |
771fe6b9 JG |
1054 | tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; |
1055 | if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) | |
1056 | tv_dac->ps2_tvdac_adj = 0x00880000; | |
1057 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; | |
1058 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; | |
6a719e05 | 1059 | return; |
771fe6b9 JG |
1060 | } |
1061 | ||
1062 | struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct | |
1063 | radeon_encoder | |
1064 | *encoder) | |
1065 | { | |
1066 | struct drm_device *dev = encoder->base.dev; | |
1067 | struct radeon_device *rdev = dev->dev_private; | |
1068 | uint16_t dac_info; | |
1069 | uint8_t rev, bg, dac; | |
1070 | struct radeon_encoder_tv_dac *tv_dac = NULL; | |
6a719e05 DA |
1071 | int found = 0; |
1072 | ||
1073 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); | |
1074 | if (!tv_dac) | |
1075 | return NULL; | |
771fe6b9 | 1076 | |
771fe6b9 JG |
1077 | /* first check TV table */ |
1078 | dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); | |
1079 | if (dac_info) { | |
771fe6b9 JG |
1080 | rev = RBIOS8(dac_info + 0x3); |
1081 | if (rev > 4) { | |
1082 | bg = RBIOS8(dac_info + 0xc) & 0xf; | |
1083 | dac = RBIOS8(dac_info + 0xd) & 0xf; | |
1084 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); | |
1085 | ||
1086 | bg = RBIOS8(dac_info + 0xe) & 0xf; | |
1087 | dac = RBIOS8(dac_info + 0xf) & 0xf; | |
1088 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); | |
1089 | ||
1090 | bg = RBIOS8(dac_info + 0x10) & 0xf; | |
1091 | dac = RBIOS8(dac_info + 0x11) & 0xf; | |
1092 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); | |
3a89b4a9 AD |
1093 | /* if the values are all zeros, use the table */ |
1094 | if (tv_dac->ps2_tvdac_adj) | |
1095 | found = 1; | |
771fe6b9 JG |
1096 | } else if (rev > 1) { |
1097 | bg = RBIOS8(dac_info + 0xc) & 0xf; | |
1098 | dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; | |
1099 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); | |
1100 | ||
1101 | bg = RBIOS8(dac_info + 0xd) & 0xf; | |
1102 | dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; | |
1103 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); | |
1104 | ||
1105 | bg = RBIOS8(dac_info + 0xe) & 0xf; | |
1106 | dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; | |
1107 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); | |
3a89b4a9 AD |
1108 | /* if the values are all zeros, use the table */ |
1109 | if (tv_dac->ps2_tvdac_adj) | |
1110 | found = 1; | |
771fe6b9 | 1111 | } |
d79766fa | 1112 | tv_dac->tv_std = radeon_combios_get_tv_info(rdev); |
6a719e05 DA |
1113 | } |
1114 | if (!found) { | |
771fe6b9 JG |
1115 | /* then check CRT table */ |
1116 | dac_info = | |
1117 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); | |
1118 | if (dac_info) { | |
771fe6b9 JG |
1119 | rev = RBIOS8(dac_info) & 0x3; |
1120 | if (rev < 2) { | |
1121 | bg = RBIOS8(dac_info + 0x3) & 0xf; | |
1122 | dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; | |
1123 | tv_dac->ps2_tvdac_adj = | |
1124 | (bg << 16) | (dac << 20); | |
1125 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; | |
1126 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; | |
3a89b4a9 AD |
1127 | /* if the values are all zeros, use the table */ |
1128 | if (tv_dac->ps2_tvdac_adj) | |
1129 | found = 1; | |
771fe6b9 JG |
1130 | } else { |
1131 | bg = RBIOS8(dac_info + 0x4) & 0xf; | |
1132 | dac = RBIOS8(dac_info + 0x5) & 0xf; | |
1133 | tv_dac->ps2_tvdac_adj = | |
1134 | (bg << 16) | (dac << 20); | |
1135 | tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; | |
1136 | tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; | |
3a89b4a9 AD |
1137 | /* if the values are all zeros, use the table */ |
1138 | if (tv_dac->ps2_tvdac_adj) | |
1139 | found = 1; | |
771fe6b9 | 1140 | } |
6fe7ac3f AD |
1141 | } else { |
1142 | DRM_INFO("No TV DAC info found in BIOS\n"); | |
771fe6b9 JG |
1143 | } |
1144 | } | |
1145 | ||
6a719e05 DA |
1146 | if (!found) /* fallback to defaults */ |
1147 | radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); | |
1148 | ||
771fe6b9 JG |
1149 | return tv_dac; |
1150 | } | |
1151 | ||
1152 | static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct | |
1153 | radeon_device | |
1154 | *rdev) | |
1155 | { | |
1156 | struct radeon_encoder_lvds *lvds = NULL; | |
1157 | uint32_t fp_vert_stretch, fp_horz_stretch; | |
1158 | uint32_t ppll_div_sel, ppll_val; | |
8b5c7444 | 1159 | uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); |
771fe6b9 JG |
1160 | |
1161 | lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); | |
1162 | ||
1163 | if (!lvds) | |
1164 | return NULL; | |
1165 | ||
1166 | fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); | |
1167 | fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); | |
1168 | ||
8b5c7444 MD |
1169 | /* These should be fail-safe defaults, fingers crossed */ |
1170 | lvds->panel_pwr_delay = 200; | |
1171 | lvds->panel_vcc_delay = 2000; | |
1172 | ||
1173 | lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); | |
1174 | lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; | |
1175 | lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; | |
1176 | ||
771fe6b9 | 1177 | if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) |
de2103e4 | 1178 | lvds->native_mode.vdisplay = |
771fe6b9 JG |
1179 | ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> |
1180 | RADEON_VERT_PANEL_SHIFT) + 1; | |
1181 | else | |
de2103e4 | 1182 | lvds->native_mode.vdisplay = |
771fe6b9 JG |
1183 | (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; |
1184 | ||
1185 | if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) | |
de2103e4 | 1186 | lvds->native_mode.hdisplay = |
771fe6b9 JG |
1187 | (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> |
1188 | RADEON_HORZ_PANEL_SHIFT) + 1) * 8; | |
1189 | else | |
de2103e4 | 1190 | lvds->native_mode.hdisplay = |
771fe6b9 JG |
1191 | ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; |
1192 | ||
de2103e4 AD |
1193 | if ((lvds->native_mode.hdisplay < 640) || |
1194 | (lvds->native_mode.vdisplay < 480)) { | |
1195 | lvds->native_mode.hdisplay = 640; | |
1196 | lvds->native_mode.vdisplay = 480; | |
771fe6b9 JG |
1197 | } |
1198 | ||
1199 | ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; | |
1200 | ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); | |
1201 | if ((ppll_val & 0x000707ff) == 0x1bb) | |
1202 | lvds->use_bios_dividers = false; | |
1203 | else { | |
1204 | lvds->panel_ref_divider = | |
1205 | RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; | |
1206 | lvds->panel_post_divider = (ppll_val >> 16) & 0x7; | |
1207 | lvds->panel_fb_divider = ppll_val & 0x7ff; | |
1208 | ||
1209 | if ((lvds->panel_ref_divider != 0) && | |
1210 | (lvds->panel_fb_divider > 3)) | |
1211 | lvds->use_bios_dividers = true; | |
1212 | } | |
1213 | lvds->panel_vcc_delay = 200; | |
1214 | ||
1215 | DRM_INFO("Panel info derived from registers\n"); | |
de2103e4 AD |
1216 | DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, |
1217 | lvds->native_mode.vdisplay); | |
771fe6b9 JG |
1218 | |
1219 | return lvds; | |
1220 | } | |
1221 | ||
1222 | struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder | |
1223 | *encoder) | |
1224 | { | |
1225 | struct drm_device *dev = encoder->base.dev; | |
1226 | struct radeon_device *rdev = dev->dev_private; | |
1227 | uint16_t lcd_info; | |
1228 | uint32_t panel_setup; | |
1229 | char stmp[30]; | |
1230 | int tmp, i; | |
1231 | struct radeon_encoder_lvds *lvds = NULL; | |
1232 | ||
771fe6b9 JG |
1233 | lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); |
1234 | ||
1235 | if (lcd_info) { | |
1236 | lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); | |
1237 | ||
1238 | if (!lvds) | |
1239 | return NULL; | |
1240 | ||
1241 | for (i = 0; i < 24; i++) | |
1242 | stmp[i] = RBIOS8(lcd_info + i + 1); | |
1243 | stmp[24] = 0; | |
1244 | ||
1245 | DRM_INFO("Panel ID String: %s\n", stmp); | |
1246 | ||
de2103e4 AD |
1247 | lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); |
1248 | lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); | |
771fe6b9 | 1249 | |
de2103e4 AD |
1250 | DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, |
1251 | lvds->native_mode.vdisplay); | |
771fe6b9 JG |
1252 | |
1253 | lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); | |
94cf6434 | 1254 | lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); |
771fe6b9 JG |
1255 | |
1256 | lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); | |
1257 | lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; | |
1258 | lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; | |
1259 | ||
1260 | lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); | |
1261 | lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); | |
1262 | lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); | |
1263 | if ((lvds->panel_ref_divider != 0) && | |
1264 | (lvds->panel_fb_divider > 3)) | |
1265 | lvds->use_bios_dividers = true; | |
1266 | ||
1267 | panel_setup = RBIOS32(lcd_info + 0x39); | |
1268 | lvds->lvds_gen_cntl = 0xff00; | |
1269 | if (panel_setup & 0x1) | |
1270 | lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; | |
1271 | ||
1272 | if ((panel_setup >> 4) & 0x1) | |
1273 | lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; | |
1274 | ||
1275 | switch ((panel_setup >> 8) & 0x7) { | |
1276 | case 0: | |
1277 | lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; | |
1278 | break; | |
1279 | case 1: | |
1280 | lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; | |
1281 | break; | |
1282 | case 2: | |
1283 | lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; | |
1284 | break; | |
1285 | default: | |
1286 | break; | |
1287 | } | |
1288 | ||
1289 | if ((panel_setup >> 16) & 0x1) | |
1290 | lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; | |
1291 | ||
1292 | if ((panel_setup >> 17) & 0x1) | |
1293 | lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; | |
1294 | ||
1295 | if ((panel_setup >> 18) & 0x1) | |
1296 | lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; | |
1297 | ||
1298 | if ((panel_setup >> 23) & 0x1) | |
1299 | lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; | |
1300 | ||
1301 | lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); | |
1302 | ||
1303 | for (i = 0; i < 32; i++) { | |
1304 | tmp = RBIOS16(lcd_info + 64 + i * 2); | |
1305 | if (tmp == 0) | |
1306 | break; | |
1307 | ||
de2103e4 | 1308 | if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && |
68b61a7f AD |
1309 | (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { |
1310 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + | |
1311 | (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; | |
1312 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + | |
1313 | (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; | |
1314 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + | |
1315 | (RBIOS8(tmp + 23) * 8); | |
1316 | ||
1317 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + | |
1318 | (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); | |
1319 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + | |
1320 | ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); | |
1321 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + | |
1322 | ((RBIOS16(tmp + 28) & 0xf800) >> 11); | |
de2103e4 AD |
1323 | |
1324 | lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; | |
771fe6b9 | 1325 | lvds->native_mode.flags = 0; |
de2103e4 AD |
1326 | /* set crtc values */ |
1327 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); | |
1328 | ||
771fe6b9 JG |
1329 | } |
1330 | } | |
6fe7ac3f | 1331 | } else { |
771fe6b9 | 1332 | DRM_INFO("No panel info found in BIOS\n"); |
8dfaa8a7 | 1333 | lvds = radeon_legacy_get_lvds_info_from_regs(rdev); |
6fe7ac3f | 1334 | } |
03047cdf | 1335 | |
8dfaa8a7 MD |
1336 | if (lvds) |
1337 | encoder->native_mode = lvds->native_mode; | |
771fe6b9 JG |
1338 | return lvds; |
1339 | } | |
1340 | ||
1341 | static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { | |
1342 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ | |
1343 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ | |
1344 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ | |
1345 | {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ | |
1346 | {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ | |
1347 | {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ | |
1348 | {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ | |
1349 | {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ | |
1350 | {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ | |
1351 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ | |
1352 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ | |
1353 | {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ | |
1354 | {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ | |
1355 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ | |
1356 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ | |
1357 | {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ | |
fcec570b AD |
1358 | { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ |
1359 | { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ | |
771fe6b9 JG |
1360 | }; |
1361 | ||
445282db DA |
1362 | bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, |
1363 | struct radeon_encoder_int_tmds *tmds) | |
771fe6b9 | 1364 | { |
445282db DA |
1365 | struct drm_device *dev = encoder->base.dev; |
1366 | struct radeon_device *rdev = dev->dev_private; | |
771fe6b9 | 1367 | int i; |
771fe6b9 JG |
1368 | |
1369 | for (i = 0; i < 4; i++) { | |
1370 | tmds->tmds_pll[i].value = | |
445282db | 1371 | default_tmds_pll[rdev->family][i].value; |
771fe6b9 JG |
1372 | tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; |
1373 | } | |
1374 | ||
445282db | 1375 | return true; |
771fe6b9 JG |
1376 | } |
1377 | ||
445282db DA |
1378 | bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, |
1379 | struct radeon_encoder_int_tmds *tmds) | |
771fe6b9 JG |
1380 | { |
1381 | struct drm_device *dev = encoder->base.dev; | |
1382 | struct radeon_device *rdev = dev->dev_private; | |
1383 | uint16_t tmds_info; | |
1384 | int i, n; | |
1385 | uint8_t ver; | |
771fe6b9 | 1386 | |
771fe6b9 JG |
1387 | tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
1388 | ||
1389 | if (tmds_info) { | |
771fe6b9 | 1390 | ver = RBIOS8(tmds_info); |
40f76d81 | 1391 | DRM_DEBUG_KMS("DFP table revision: %d\n", ver); |
771fe6b9 JG |
1392 | if (ver == 3) { |
1393 | n = RBIOS8(tmds_info + 5) + 1; | |
1394 | if (n > 4) | |
1395 | n = 4; | |
1396 | for (i = 0; i < n; i++) { | |
1397 | tmds->tmds_pll[i].value = | |
1398 | RBIOS32(tmds_info + i * 10 + 0x08); | |
1399 | tmds->tmds_pll[i].freq = | |
1400 | RBIOS16(tmds_info + i * 10 + 0x10); | |
d9fdaafb | 1401 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
771fe6b9 JG |
1402 | tmds->tmds_pll[i].freq, |
1403 | tmds->tmds_pll[i].value); | |
1404 | } | |
1405 | } else if (ver == 4) { | |
1406 | int stride = 0; | |
1407 | n = RBIOS8(tmds_info + 5) + 1; | |
1408 | if (n > 4) | |
1409 | n = 4; | |
1410 | for (i = 0; i < n; i++) { | |
1411 | tmds->tmds_pll[i].value = | |
1412 | RBIOS32(tmds_info + stride + 0x08); | |
1413 | tmds->tmds_pll[i].freq = | |
1414 | RBIOS16(tmds_info + stride + 0x10); | |
1415 | if (i == 0) | |
1416 | stride += 10; | |
1417 | else | |
1418 | stride += 6; | |
d9fdaafb | 1419 | DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
771fe6b9 JG |
1420 | tmds->tmds_pll[i].freq, |
1421 | tmds->tmds_pll[i].value); | |
1422 | } | |
1423 | } | |
fcec570b | 1424 | } else { |
771fe6b9 | 1425 | DRM_INFO("No TMDS info found in BIOS\n"); |
fcec570b AD |
1426 | return false; |
1427 | } | |
445282db DA |
1428 | return true; |
1429 | } | |
1430 | ||
fcec570b AD |
1431 | bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, |
1432 | struct radeon_encoder_ext_tmds *tmds) | |
445282db | 1433 | { |
fcec570b AD |
1434 | struct drm_device *dev = encoder->base.dev; |
1435 | struct radeon_device *rdev = dev->dev_private; | |
1436 | struct radeon_i2c_bus_rec i2c_bus; | |
445282db | 1437 | |
fcec570b | 1438 | /* default for macs */ |
179e8078 | 1439 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
f376b94f | 1440 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
445282db | 1441 | |
fcec570b AD |
1442 | /* XXX some macs have duallink chips */ |
1443 | switch (rdev->mode_info.connector_table) { | |
1444 | case CT_POWERBOOK_EXTERNAL: | |
1445 | case CT_MINI_EXTERNAL: | |
1446 | default: | |
1447 | tmds->dvo_chip = DVO_SIL164; | |
1448 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ | |
1449 | break; | |
1450 | } | |
445282db | 1451 | |
fcec570b | 1452 | return true; |
771fe6b9 JG |
1453 | } |
1454 | ||
fcec570b AD |
1455 | bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, |
1456 | struct radeon_encoder_ext_tmds *tmds) | |
771fe6b9 JG |
1457 | { |
1458 | struct drm_device *dev = encoder->base.dev; | |
1459 | struct radeon_device *rdev = dev->dev_private; | |
fcec570b | 1460 | uint16_t offset; |
179e8078 | 1461 | uint8_t ver; |
fcec570b AD |
1462 | enum radeon_combios_ddc gpio; |
1463 | struct radeon_i2c_bus_rec i2c_bus; | |
771fe6b9 | 1464 | |
fcec570b AD |
1465 | tmds->i2c_bus = NULL; |
1466 | if (rdev->flags & RADEON_IS_IGP) { | |
179e8078 AD |
1467 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
1468 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); | |
1469 | tmds->dvo_chip = DVO_SIL164; | |
1470 | tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ | |
fcec570b AD |
1471 | } else { |
1472 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); | |
1473 | if (offset) { | |
1474 | ver = RBIOS8(offset); | |
40f76d81 | 1475 | DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); |
fcec570b AD |
1476 | tmds->slave_addr = RBIOS8(offset + 4 + 2); |
1477 | tmds->slave_addr >>= 1; /* 7 bit addressing */ | |
1478 | gpio = RBIOS8(offset + 4 + 3); | |
179e8078 AD |
1479 | if (gpio == DDC_LCD) { |
1480 | /* MM i2c */ | |
40bacf16 AD |
1481 | i2c_bus.valid = true; |
1482 | i2c_bus.hw_capable = true; | |
1483 | i2c_bus.mm_i2c = true; | |
179e8078 AD |
1484 | i2c_bus.i2c_id = 0xa0; |
1485 | } else | |
1486 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); | |
1487 | tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); | |
fcec570b | 1488 | } |
771fe6b9 | 1489 | } |
fcec570b AD |
1490 | |
1491 | if (!tmds->i2c_bus) { | |
1492 | DRM_INFO("No valid Ext TMDS info found in BIOS\n"); | |
1493 | return false; | |
1494 | } | |
1495 | ||
1496 | return true; | |
771fe6b9 JG |
1497 | } |
1498 | ||
1499 | bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) | |
1500 | { | |
1501 | struct radeon_device *rdev = dev->dev_private; | |
1502 | struct radeon_i2c_bus_rec ddc_i2c; | |
eed45b30 | 1503 | struct radeon_hpd hpd; |
771fe6b9 JG |
1504 | |
1505 | rdev->mode_info.connector_table = radeon_connector_table; | |
1506 | if (rdev->mode_info.connector_table == CT_NONE) { | |
1507 | #ifdef CONFIG_PPC_PMAC | |
71a157e8 | 1508 | if (of_machine_is_compatible("PowerBook3,3")) { |
771fe6b9 JG |
1509 | /* powerbook with VGA */ |
1510 | rdev->mode_info.connector_table = CT_POWERBOOK_VGA; | |
71a157e8 GL |
1511 | } else if (of_machine_is_compatible("PowerBook3,4") || |
1512 | of_machine_is_compatible("PowerBook3,5")) { | |
771fe6b9 JG |
1513 | /* powerbook with internal tmds */ |
1514 | rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; | |
71a157e8 GL |
1515 | } else if (of_machine_is_compatible("PowerBook5,1") || |
1516 | of_machine_is_compatible("PowerBook5,2") || | |
1517 | of_machine_is_compatible("PowerBook5,3") || | |
1518 | of_machine_is_compatible("PowerBook5,4") || | |
1519 | of_machine_is_compatible("PowerBook5,5")) { | |
771fe6b9 JG |
1520 | /* powerbook with external single link tmds (sil164) */ |
1521 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; | |
71a157e8 | 1522 | } else if (of_machine_is_compatible("PowerBook5,6")) { |
771fe6b9 JG |
1523 | /* powerbook with external dual or single link tmds */ |
1524 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; | |
71a157e8 GL |
1525 | } else if (of_machine_is_compatible("PowerBook5,7") || |
1526 | of_machine_is_compatible("PowerBook5,8") || | |
1527 | of_machine_is_compatible("PowerBook5,9")) { | |
771fe6b9 JG |
1528 | /* PowerBook6,2 ? */ |
1529 | /* powerbook with external dual link tmds (sil1178?) */ | |
1530 | rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; | |
71a157e8 GL |
1531 | } else if (of_machine_is_compatible("PowerBook4,1") || |
1532 | of_machine_is_compatible("PowerBook4,2") || | |
1533 | of_machine_is_compatible("PowerBook4,3") || | |
1534 | of_machine_is_compatible("PowerBook6,3") || | |
1535 | of_machine_is_compatible("PowerBook6,5") || | |
1536 | of_machine_is_compatible("PowerBook6,7")) { | |
771fe6b9 JG |
1537 | /* ibook */ |
1538 | rdev->mode_info.connector_table = CT_IBOOK; | |
71a157e8 | 1539 | } else if (of_machine_is_compatible("PowerMac4,4")) { |
771fe6b9 JG |
1540 | /* emac */ |
1541 | rdev->mode_info.connector_table = CT_EMAC; | |
71a157e8 | 1542 | } else if (of_machine_is_compatible("PowerMac10,1")) { |
771fe6b9 JG |
1543 | /* mini with internal tmds */ |
1544 | rdev->mode_info.connector_table = CT_MINI_INTERNAL; | |
71a157e8 | 1545 | } else if (of_machine_is_compatible("PowerMac10,2")) { |
771fe6b9 JG |
1546 | /* mini with external tmds */ |
1547 | rdev->mode_info.connector_table = CT_MINI_EXTERNAL; | |
71a157e8 | 1548 | } else if (of_machine_is_compatible("PowerMac12,1")) { |
771fe6b9 JG |
1549 | /* PowerMac8,1 ? */ |
1550 | /* imac g5 isight */ | |
1551 | rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; | |
aa74fbb4 AD |
1552 | } else if ((rdev->pdev->device == 0x4a48) && |
1553 | (rdev->pdev->subsystem_vendor == 0x1002) && | |
1554 | (rdev->pdev->subsystem_device == 0x4a48)) { | |
1555 | /* Mac X800 */ | |
1556 | rdev->mode_info.connector_table = CT_MAC_X800; | |
7c88d2b8 AD |
1557 | } else if ((of_machine_is_compatible("PowerMac7,2") || |
1558 | of_machine_is_compatible("PowerMac7,3")) && | |
1559 | (rdev->pdev->device == 0x4150) && | |
1560 | (rdev->pdev->subsystem_vendor == 0x1002) && | |
1561 | (rdev->pdev->subsystem_device == 0x4150)) { | |
1562 | /* Mac G5 tower 9600 */ | |
9fad321a | 1563 | rdev->mode_info.connector_table = CT_MAC_G5_9600; |
771fe6b9 JG |
1564 | } else |
1565 | #endif /* CONFIG_PPC_PMAC */ | |
76a7142a DA |
1566 | #ifdef CONFIG_PPC64 |
1567 | if (ASIC_IS_RN50(rdev)) | |
1568 | rdev->mode_info.connector_table = CT_RN50_POWER; | |
1569 | else | |
1570 | #endif | |
771fe6b9 JG |
1571 | rdev->mode_info.connector_table = CT_GENERIC; |
1572 | } | |
1573 | ||
1574 | switch (rdev->mode_info.connector_table) { | |
1575 | case CT_GENERIC: | |
1576 | DRM_INFO("Connector Table: %d (generic)\n", | |
1577 | rdev->mode_info.connector_table); | |
1578 | /* these are the most common settings */ | |
1579 | if (rdev->flags & RADEON_SINGLE_CRTC) { | |
1580 | /* VGA - primary dac */ | |
179e8078 | 1581 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
eed45b30 | 1582 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1583 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1584 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1585 | ATOM_DEVICE_CRT1_SUPPORT, |
1586 | 1), | |
1587 | ATOM_DEVICE_CRT1_SUPPORT); | |
1588 | radeon_add_legacy_connector(dev, 0, | |
1589 | ATOM_DEVICE_CRT1_SUPPORT, | |
1590 | DRM_MODE_CONNECTOR_VGA, | |
b75fad06 | 1591 | &ddc_i2c, |
eed45b30 AD |
1592 | CONNECTOR_OBJECT_ID_VGA, |
1593 | &hpd); | |
771fe6b9 JG |
1594 | } else if (rdev->flags & RADEON_IS_MOBILITY) { |
1595 | /* LVDS */ | |
179e8078 | 1596 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); |
eed45b30 | 1597 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1598 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1599 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1600 | ATOM_DEVICE_LCD1_SUPPORT, |
1601 | 0), | |
1602 | ATOM_DEVICE_LCD1_SUPPORT); | |
1603 | radeon_add_legacy_connector(dev, 0, | |
1604 | ATOM_DEVICE_LCD1_SUPPORT, | |
1605 | DRM_MODE_CONNECTOR_LVDS, | |
b75fad06 | 1606 | &ddc_i2c, |
eed45b30 AD |
1607 | CONNECTOR_OBJECT_ID_LVDS, |
1608 | &hpd); | |
771fe6b9 JG |
1609 | |
1610 | /* VGA - primary dac */ | |
179e8078 | 1611 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
eed45b30 | 1612 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1613 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1614 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1615 | ATOM_DEVICE_CRT1_SUPPORT, |
1616 | 1), | |
1617 | ATOM_DEVICE_CRT1_SUPPORT); | |
1618 | radeon_add_legacy_connector(dev, 1, | |
1619 | ATOM_DEVICE_CRT1_SUPPORT, | |
1620 | DRM_MODE_CONNECTOR_VGA, | |
b75fad06 | 1621 | &ddc_i2c, |
eed45b30 AD |
1622 | CONNECTOR_OBJECT_ID_VGA, |
1623 | &hpd); | |
771fe6b9 JG |
1624 | } else { |
1625 | /* DVI-I - tv dac, int tmds */ | |
179e8078 | 1626 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
eed45b30 | 1627 | hpd.hpd = RADEON_HPD_1; |
771fe6b9 | 1628 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1629 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1630 | ATOM_DEVICE_DFP1_SUPPORT, |
1631 | 0), | |
1632 | ATOM_DEVICE_DFP1_SUPPORT); | |
1633 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 1634 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1635 | ATOM_DEVICE_CRT2_SUPPORT, |
1636 | 2), | |
1637 | ATOM_DEVICE_CRT2_SUPPORT); | |
1638 | radeon_add_legacy_connector(dev, 0, | |
1639 | ATOM_DEVICE_DFP1_SUPPORT | | |
1640 | ATOM_DEVICE_CRT2_SUPPORT, | |
1641 | DRM_MODE_CONNECTOR_DVII, | |
b75fad06 | 1642 | &ddc_i2c, |
eed45b30 AD |
1643 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1644 | &hpd); | |
771fe6b9 JG |
1645 | |
1646 | /* VGA - primary dac */ | |
179e8078 | 1647 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
eed45b30 | 1648 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1649 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1650 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1651 | ATOM_DEVICE_CRT1_SUPPORT, |
1652 | 1), | |
1653 | ATOM_DEVICE_CRT1_SUPPORT); | |
1654 | radeon_add_legacy_connector(dev, 1, | |
1655 | ATOM_DEVICE_CRT1_SUPPORT, | |
1656 | DRM_MODE_CONNECTOR_VGA, | |
b75fad06 | 1657 | &ddc_i2c, |
eed45b30 AD |
1658 | CONNECTOR_OBJECT_ID_VGA, |
1659 | &hpd); | |
771fe6b9 JG |
1660 | } |
1661 | ||
1662 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { | |
1663 | /* TV - tv dac */ | |
eed45b30 AD |
1664 | ddc_i2c.valid = false; |
1665 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 1666 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1667 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1668 | ATOM_DEVICE_TV1_SUPPORT, |
1669 | 2), | |
1670 | ATOM_DEVICE_TV1_SUPPORT); | |
1671 | radeon_add_legacy_connector(dev, 2, | |
1672 | ATOM_DEVICE_TV1_SUPPORT, | |
1673 | DRM_MODE_CONNECTOR_SVIDEO, | |
b75fad06 | 1674 | &ddc_i2c, |
eed45b30 AD |
1675 | CONNECTOR_OBJECT_ID_SVIDEO, |
1676 | &hpd); | |
771fe6b9 JG |
1677 | } |
1678 | break; | |
1679 | case CT_IBOOK: | |
1680 | DRM_INFO("Connector Table: %d (ibook)\n", | |
1681 | rdev->mode_info.connector_table); | |
1682 | /* LVDS */ | |
179e8078 | 1683 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
eed45b30 | 1684 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1685 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1686 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1687 | ATOM_DEVICE_LCD1_SUPPORT, |
1688 | 0), | |
1689 | ATOM_DEVICE_LCD1_SUPPORT); | |
1690 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, | |
b75fad06 | 1691 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
eed45b30 AD |
1692 | CONNECTOR_OBJECT_ID_LVDS, |
1693 | &hpd); | |
771fe6b9 | 1694 | /* VGA - TV DAC */ |
179e8078 | 1695 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
eed45b30 | 1696 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1697 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1698 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1699 | ATOM_DEVICE_CRT2_SUPPORT, |
1700 | 2), | |
1701 | ATOM_DEVICE_CRT2_SUPPORT); | |
1702 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, | |
b75fad06 | 1703 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
eed45b30 AD |
1704 | CONNECTOR_OBJECT_ID_VGA, |
1705 | &hpd); | |
771fe6b9 | 1706 | /* TV - TV DAC */ |
eed45b30 AD |
1707 | ddc_i2c.valid = false; |
1708 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 1709 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1710 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1711 | ATOM_DEVICE_TV1_SUPPORT, |
1712 | 2), | |
1713 | ATOM_DEVICE_TV1_SUPPORT); | |
1714 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, | |
1715 | DRM_MODE_CONNECTOR_SVIDEO, | |
b75fad06 | 1716 | &ddc_i2c, |
eed45b30 AD |
1717 | CONNECTOR_OBJECT_ID_SVIDEO, |
1718 | &hpd); | |
771fe6b9 JG |
1719 | break; |
1720 | case CT_POWERBOOK_EXTERNAL: | |
1721 | DRM_INFO("Connector Table: %d (powerbook external tmds)\n", | |
1722 | rdev->mode_info.connector_table); | |
1723 | /* LVDS */ | |
179e8078 | 1724 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
eed45b30 | 1725 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1726 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1727 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1728 | ATOM_DEVICE_LCD1_SUPPORT, |
1729 | 0), | |
1730 | ATOM_DEVICE_LCD1_SUPPORT); | |
1731 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, | |
b75fad06 | 1732 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
eed45b30 AD |
1733 | CONNECTOR_OBJECT_ID_LVDS, |
1734 | &hpd); | |
771fe6b9 | 1735 | /* DVI-I - primary dac, ext tmds */ |
179e8078 | 1736 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
eed45b30 | 1737 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
771fe6b9 | 1738 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1739 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1740 | ATOM_DEVICE_DFP2_SUPPORT, |
1741 | 0), | |
1742 | ATOM_DEVICE_DFP2_SUPPORT); | |
1743 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 1744 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1745 | ATOM_DEVICE_CRT1_SUPPORT, |
1746 | 1), | |
1747 | ATOM_DEVICE_CRT1_SUPPORT); | |
b75fad06 | 1748 | /* XXX some are SL */ |
771fe6b9 JG |
1749 | radeon_add_legacy_connector(dev, 1, |
1750 | ATOM_DEVICE_DFP2_SUPPORT | | |
1751 | ATOM_DEVICE_CRT1_SUPPORT, | |
b75fad06 | 1752 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
eed45b30 AD |
1753 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, |
1754 | &hpd); | |
771fe6b9 | 1755 | /* TV - TV DAC */ |
eed45b30 AD |
1756 | ddc_i2c.valid = false; |
1757 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 1758 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1759 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1760 | ATOM_DEVICE_TV1_SUPPORT, |
1761 | 2), | |
1762 | ATOM_DEVICE_TV1_SUPPORT); | |
1763 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, | |
1764 | DRM_MODE_CONNECTOR_SVIDEO, | |
b75fad06 | 1765 | &ddc_i2c, |
eed45b30 AD |
1766 | CONNECTOR_OBJECT_ID_SVIDEO, |
1767 | &hpd); | |
771fe6b9 JG |
1768 | break; |
1769 | case CT_POWERBOOK_INTERNAL: | |
1770 | DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", | |
1771 | rdev->mode_info.connector_table); | |
1772 | /* LVDS */ | |
179e8078 | 1773 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
eed45b30 | 1774 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1775 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1776 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1777 | ATOM_DEVICE_LCD1_SUPPORT, |
1778 | 0), | |
1779 | ATOM_DEVICE_LCD1_SUPPORT); | |
1780 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, | |
b75fad06 | 1781 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
eed45b30 AD |
1782 | CONNECTOR_OBJECT_ID_LVDS, |
1783 | &hpd); | |
771fe6b9 | 1784 | /* DVI-I - primary dac, int tmds */ |
179e8078 | 1785 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
eed45b30 | 1786 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
771fe6b9 | 1787 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1788 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1789 | ATOM_DEVICE_DFP1_SUPPORT, |
1790 | 0), | |
1791 | ATOM_DEVICE_DFP1_SUPPORT); | |
1792 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 1793 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1794 | ATOM_DEVICE_CRT1_SUPPORT, |
1795 | 1), | |
1796 | ATOM_DEVICE_CRT1_SUPPORT); | |
1797 | radeon_add_legacy_connector(dev, 1, | |
1798 | ATOM_DEVICE_DFP1_SUPPORT | | |
1799 | ATOM_DEVICE_CRT1_SUPPORT, | |
b75fad06 | 1800 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
eed45b30 AD |
1801 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1802 | &hpd); | |
771fe6b9 | 1803 | /* TV - TV DAC */ |
eed45b30 AD |
1804 | ddc_i2c.valid = false; |
1805 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 1806 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1807 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1808 | ATOM_DEVICE_TV1_SUPPORT, |
1809 | 2), | |
1810 | ATOM_DEVICE_TV1_SUPPORT); | |
1811 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, | |
1812 | DRM_MODE_CONNECTOR_SVIDEO, | |
b75fad06 | 1813 | &ddc_i2c, |
eed45b30 AD |
1814 | CONNECTOR_OBJECT_ID_SVIDEO, |
1815 | &hpd); | |
771fe6b9 JG |
1816 | break; |
1817 | case CT_POWERBOOK_VGA: | |
1818 | DRM_INFO("Connector Table: %d (powerbook vga)\n", | |
1819 | rdev->mode_info.connector_table); | |
1820 | /* LVDS */ | |
179e8078 | 1821 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
eed45b30 | 1822 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1823 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1824 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1825 | ATOM_DEVICE_LCD1_SUPPORT, |
1826 | 0), | |
1827 | ATOM_DEVICE_LCD1_SUPPORT); | |
1828 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, | |
b75fad06 | 1829 | DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, |
eed45b30 AD |
1830 | CONNECTOR_OBJECT_ID_LVDS, |
1831 | &hpd); | |
771fe6b9 | 1832 | /* VGA - primary dac */ |
179e8078 | 1833 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
eed45b30 | 1834 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1835 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1836 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1837 | ATOM_DEVICE_CRT1_SUPPORT, |
1838 | 1), | |
1839 | ATOM_DEVICE_CRT1_SUPPORT); | |
1840 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, | |
b75fad06 | 1841 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
eed45b30 AD |
1842 | CONNECTOR_OBJECT_ID_VGA, |
1843 | &hpd); | |
771fe6b9 | 1844 | /* TV - TV DAC */ |
eed45b30 AD |
1845 | ddc_i2c.valid = false; |
1846 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 1847 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1848 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1849 | ATOM_DEVICE_TV1_SUPPORT, |
1850 | 2), | |
1851 | ATOM_DEVICE_TV1_SUPPORT); | |
1852 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, | |
1853 | DRM_MODE_CONNECTOR_SVIDEO, | |
b75fad06 | 1854 | &ddc_i2c, |
eed45b30 AD |
1855 | CONNECTOR_OBJECT_ID_SVIDEO, |
1856 | &hpd); | |
771fe6b9 JG |
1857 | break; |
1858 | case CT_MINI_EXTERNAL: | |
1859 | DRM_INFO("Connector Table: %d (mini external tmds)\n", | |
1860 | rdev->mode_info.connector_table); | |
1861 | /* DVI-I - tv dac, ext tmds */ | |
179e8078 | 1862 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
eed45b30 | 1863 | hpd.hpd = RADEON_HPD_2; /* ??? */ |
771fe6b9 | 1864 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1865 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1866 | ATOM_DEVICE_DFP2_SUPPORT, |
1867 | 0), | |
1868 | ATOM_DEVICE_DFP2_SUPPORT); | |
1869 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 1870 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1871 | ATOM_DEVICE_CRT2_SUPPORT, |
1872 | 2), | |
1873 | ATOM_DEVICE_CRT2_SUPPORT); | |
b75fad06 | 1874 | /* XXX are any DL? */ |
771fe6b9 JG |
1875 | radeon_add_legacy_connector(dev, 0, |
1876 | ATOM_DEVICE_DFP2_SUPPORT | | |
1877 | ATOM_DEVICE_CRT2_SUPPORT, | |
b75fad06 | 1878 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
eed45b30 AD |
1879 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1880 | &hpd); | |
771fe6b9 | 1881 | /* TV - TV DAC */ |
eed45b30 AD |
1882 | ddc_i2c.valid = false; |
1883 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 1884 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1885 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1886 | ATOM_DEVICE_TV1_SUPPORT, |
1887 | 2), | |
1888 | ATOM_DEVICE_TV1_SUPPORT); | |
1889 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, | |
1890 | DRM_MODE_CONNECTOR_SVIDEO, | |
b75fad06 | 1891 | &ddc_i2c, |
eed45b30 AD |
1892 | CONNECTOR_OBJECT_ID_SVIDEO, |
1893 | &hpd); | |
771fe6b9 JG |
1894 | break; |
1895 | case CT_MINI_INTERNAL: | |
1896 | DRM_INFO("Connector Table: %d (mini internal tmds)\n", | |
1897 | rdev->mode_info.connector_table); | |
1898 | /* DVI-I - tv dac, int tmds */ | |
179e8078 | 1899 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
eed45b30 | 1900 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
771fe6b9 | 1901 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1902 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1903 | ATOM_DEVICE_DFP1_SUPPORT, |
1904 | 0), | |
1905 | ATOM_DEVICE_DFP1_SUPPORT); | |
1906 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 1907 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1908 | ATOM_DEVICE_CRT2_SUPPORT, |
1909 | 2), | |
1910 | ATOM_DEVICE_CRT2_SUPPORT); | |
1911 | radeon_add_legacy_connector(dev, 0, | |
1912 | ATOM_DEVICE_DFP1_SUPPORT | | |
1913 | ATOM_DEVICE_CRT2_SUPPORT, | |
b75fad06 | 1914 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
eed45b30 AD |
1915 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
1916 | &hpd); | |
771fe6b9 | 1917 | /* TV - TV DAC */ |
eed45b30 AD |
1918 | ddc_i2c.valid = false; |
1919 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 1920 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1921 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1922 | ATOM_DEVICE_TV1_SUPPORT, |
1923 | 2), | |
1924 | ATOM_DEVICE_TV1_SUPPORT); | |
1925 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, | |
1926 | DRM_MODE_CONNECTOR_SVIDEO, | |
b75fad06 | 1927 | &ddc_i2c, |
eed45b30 AD |
1928 | CONNECTOR_OBJECT_ID_SVIDEO, |
1929 | &hpd); | |
771fe6b9 JG |
1930 | break; |
1931 | case CT_IMAC_G5_ISIGHT: | |
1932 | DRM_INFO("Connector Table: %d (imac g5 isight)\n", | |
1933 | rdev->mode_info.connector_table); | |
1934 | /* DVI-D - int tmds */ | |
179e8078 | 1935 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
eed45b30 | 1936 | hpd.hpd = RADEON_HPD_1; /* ??? */ |
771fe6b9 | 1937 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1938 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1939 | ATOM_DEVICE_DFP1_SUPPORT, |
1940 | 0), | |
1941 | ATOM_DEVICE_DFP1_SUPPORT); | |
1942 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, | |
b75fad06 | 1943 | DRM_MODE_CONNECTOR_DVID, &ddc_i2c, |
eed45b30 AD |
1944 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, |
1945 | &hpd); | |
771fe6b9 | 1946 | /* VGA - tv dac */ |
179e8078 | 1947 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
eed45b30 | 1948 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1949 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1950 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1951 | ATOM_DEVICE_CRT2_SUPPORT, |
1952 | 2), | |
1953 | ATOM_DEVICE_CRT2_SUPPORT); | |
1954 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, | |
b75fad06 | 1955 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
eed45b30 AD |
1956 | CONNECTOR_OBJECT_ID_VGA, |
1957 | &hpd); | |
771fe6b9 | 1958 | /* TV - TV DAC */ |
eed45b30 AD |
1959 | ddc_i2c.valid = false; |
1960 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 1961 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1962 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1963 | ATOM_DEVICE_TV1_SUPPORT, |
1964 | 2), | |
1965 | ATOM_DEVICE_TV1_SUPPORT); | |
1966 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, | |
1967 | DRM_MODE_CONNECTOR_SVIDEO, | |
b75fad06 | 1968 | &ddc_i2c, |
eed45b30 AD |
1969 | CONNECTOR_OBJECT_ID_SVIDEO, |
1970 | &hpd); | |
771fe6b9 JG |
1971 | break; |
1972 | case CT_EMAC: | |
1973 | DRM_INFO("Connector Table: %d (emac)\n", | |
1974 | rdev->mode_info.connector_table); | |
1975 | /* VGA - primary dac */ | |
179e8078 | 1976 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
eed45b30 | 1977 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1978 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1979 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1980 | ATOM_DEVICE_CRT1_SUPPORT, |
1981 | 1), | |
1982 | ATOM_DEVICE_CRT1_SUPPORT); | |
1983 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, | |
b75fad06 | 1984 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
eed45b30 AD |
1985 | CONNECTOR_OBJECT_ID_VGA, |
1986 | &hpd); | |
771fe6b9 | 1987 | /* VGA - tv dac */ |
179e8078 | 1988 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
eed45b30 | 1989 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 | 1990 | radeon_add_legacy_encoder(dev, |
5137ee94 | 1991 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
1992 | ATOM_DEVICE_CRT2_SUPPORT, |
1993 | 2), | |
1994 | ATOM_DEVICE_CRT2_SUPPORT); | |
1995 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, | |
b75fad06 | 1996 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
eed45b30 AD |
1997 | CONNECTOR_OBJECT_ID_VGA, |
1998 | &hpd); | |
771fe6b9 | 1999 | /* TV - TV DAC */ |
eed45b30 AD |
2000 | ddc_i2c.valid = false; |
2001 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 2002 | radeon_add_legacy_encoder(dev, |
5137ee94 | 2003 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
2004 | ATOM_DEVICE_TV1_SUPPORT, |
2005 | 2), | |
2006 | ATOM_DEVICE_TV1_SUPPORT); | |
2007 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, | |
2008 | DRM_MODE_CONNECTOR_SVIDEO, | |
b75fad06 | 2009 | &ddc_i2c, |
eed45b30 AD |
2010 | CONNECTOR_OBJECT_ID_SVIDEO, |
2011 | &hpd); | |
771fe6b9 | 2012 | break; |
76a7142a DA |
2013 | case CT_RN50_POWER: |
2014 | DRM_INFO("Connector Table: %d (rn50-power)\n", | |
2015 | rdev->mode_info.connector_table); | |
2016 | /* VGA - primary dac */ | |
179e8078 | 2017 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
76a7142a DA |
2018 | hpd.hpd = RADEON_HPD_NONE; |
2019 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2020 | radeon_get_encoder_enum(dev, |
76a7142a DA |
2021 | ATOM_DEVICE_CRT1_SUPPORT, |
2022 | 1), | |
2023 | ATOM_DEVICE_CRT1_SUPPORT); | |
2024 | radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, | |
2025 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, | |
2026 | CONNECTOR_OBJECT_ID_VGA, | |
2027 | &hpd); | |
179e8078 | 2028 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
76a7142a DA |
2029 | hpd.hpd = RADEON_HPD_NONE; |
2030 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2031 | radeon_get_encoder_enum(dev, |
76a7142a DA |
2032 | ATOM_DEVICE_CRT2_SUPPORT, |
2033 | 2), | |
2034 | ATOM_DEVICE_CRT2_SUPPORT); | |
2035 | radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, | |
2036 | DRM_MODE_CONNECTOR_VGA, &ddc_i2c, | |
2037 | CONNECTOR_OBJECT_ID_VGA, | |
2038 | &hpd); | |
2039 | break; | |
aa74fbb4 AD |
2040 | case CT_MAC_X800: |
2041 | DRM_INFO("Connector Table: %d (mac x800)\n", | |
2042 | rdev->mode_info.connector_table); | |
2043 | /* DVI - primary dac, internal tmds */ | |
2044 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); | |
2045 | hpd.hpd = RADEON_HPD_1; /* ??? */ | |
2046 | radeon_add_legacy_encoder(dev, | |
2047 | radeon_get_encoder_enum(dev, | |
2048 | ATOM_DEVICE_DFP1_SUPPORT, | |
2049 | 0), | |
2050 | ATOM_DEVICE_DFP1_SUPPORT); | |
2051 | radeon_add_legacy_encoder(dev, | |
2052 | radeon_get_encoder_enum(dev, | |
2053 | ATOM_DEVICE_CRT1_SUPPORT, | |
2054 | 1), | |
2055 | ATOM_DEVICE_CRT1_SUPPORT); | |
2056 | radeon_add_legacy_connector(dev, 0, | |
2057 | ATOM_DEVICE_DFP1_SUPPORT | | |
2058 | ATOM_DEVICE_CRT1_SUPPORT, | |
2059 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, | |
2060 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, | |
2061 | &hpd); | |
2062 | /* DVI - tv dac, dvo */ | |
2063 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); | |
2064 | hpd.hpd = RADEON_HPD_2; /* ??? */ | |
2065 | radeon_add_legacy_encoder(dev, | |
2066 | radeon_get_encoder_enum(dev, | |
2067 | ATOM_DEVICE_DFP2_SUPPORT, | |
2068 | 0), | |
2069 | ATOM_DEVICE_DFP2_SUPPORT); | |
2070 | radeon_add_legacy_encoder(dev, | |
2071 | radeon_get_encoder_enum(dev, | |
2072 | ATOM_DEVICE_CRT2_SUPPORT, | |
2073 | 2), | |
2074 | ATOM_DEVICE_CRT2_SUPPORT); | |
2075 | radeon_add_legacy_connector(dev, 1, | |
2076 | ATOM_DEVICE_DFP2_SUPPORT | | |
2077 | ATOM_DEVICE_CRT2_SUPPORT, | |
2078 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, | |
2079 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, | |
2080 | &hpd); | |
2081 | break; | |
9fad321a AD |
2082 | case CT_MAC_G5_9600: |
2083 | DRM_INFO("Connector Table: %d (mac g5 9600)\n", | |
2084 | rdev->mode_info.connector_table); | |
2085 | /* DVI - tv dac, dvo */ | |
2086 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); | |
2087 | hpd.hpd = RADEON_HPD_1; /* ??? */ | |
2088 | radeon_add_legacy_encoder(dev, | |
2089 | radeon_get_encoder_enum(dev, | |
2090 | ATOM_DEVICE_DFP2_SUPPORT, | |
2091 | 0), | |
2092 | ATOM_DEVICE_DFP2_SUPPORT); | |
2093 | radeon_add_legacy_encoder(dev, | |
2094 | radeon_get_encoder_enum(dev, | |
2095 | ATOM_DEVICE_CRT2_SUPPORT, | |
2096 | 2), | |
2097 | ATOM_DEVICE_CRT2_SUPPORT); | |
2098 | radeon_add_legacy_connector(dev, 0, | |
2099 | ATOM_DEVICE_DFP2_SUPPORT | | |
2100 | ATOM_DEVICE_CRT2_SUPPORT, | |
2101 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, | |
2102 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, | |
2103 | &hpd); | |
2104 | /* ADC - primary dac, internal tmds */ | |
2105 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); | |
2106 | hpd.hpd = RADEON_HPD_2; /* ??? */ | |
2107 | radeon_add_legacy_encoder(dev, | |
2108 | radeon_get_encoder_enum(dev, | |
2109 | ATOM_DEVICE_DFP1_SUPPORT, | |
2110 | 0), | |
2111 | ATOM_DEVICE_DFP1_SUPPORT); | |
2112 | radeon_add_legacy_encoder(dev, | |
2113 | radeon_get_encoder_enum(dev, | |
2114 | ATOM_DEVICE_CRT1_SUPPORT, | |
2115 | 1), | |
2116 | ATOM_DEVICE_CRT1_SUPPORT); | |
2117 | radeon_add_legacy_connector(dev, 1, | |
2118 | ATOM_DEVICE_DFP1_SUPPORT | | |
2119 | ATOM_DEVICE_CRT1_SUPPORT, | |
2120 | DRM_MODE_CONNECTOR_DVII, &ddc_i2c, | |
2121 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, | |
2122 | &hpd); | |
beb47274 AD |
2123 | /* TV - TV DAC */ |
2124 | ddc_i2c.valid = false; | |
2125 | hpd.hpd = RADEON_HPD_NONE; | |
2126 | radeon_add_legacy_encoder(dev, | |
2127 | radeon_get_encoder_enum(dev, | |
2128 | ATOM_DEVICE_TV1_SUPPORT, | |
2129 | 2), | |
2130 | ATOM_DEVICE_TV1_SUPPORT); | |
2131 | radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, | |
2132 | DRM_MODE_CONNECTOR_SVIDEO, | |
2133 | &ddc_i2c, | |
2134 | CONNECTOR_OBJECT_ID_SVIDEO, | |
2135 | &hpd); | |
9fad321a | 2136 | break; |
771fe6b9 JG |
2137 | default: |
2138 | DRM_INFO("Connector table: %d (invalid)\n", | |
2139 | rdev->mode_info.connector_table); | |
2140 | return false; | |
2141 | } | |
2142 | ||
2143 | radeon_link_encoder_connector(dev); | |
2144 | ||
2145 | return true; | |
2146 | } | |
2147 | ||
2148 | static bool radeon_apply_legacy_quirks(struct drm_device *dev, | |
2149 | int bios_index, | |
2150 | enum radeon_combios_connector | |
2151 | *legacy_connector, | |
eed45b30 AD |
2152 | struct radeon_i2c_bus_rec *ddc_i2c, |
2153 | struct radeon_hpd *hpd) | |
771fe6b9 | 2154 | { |
fcec570b | 2155 | |
771fe6b9 JG |
2156 | /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, |
2157 | one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ | |
2158 | if (dev->pdev->device == 0x515e && | |
2159 | dev->pdev->subsystem_vendor == 0x1014) { | |
2160 | if (*legacy_connector == CONNECTOR_CRT_LEGACY && | |
2161 | ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) | |
2162 | return false; | |
2163 | } | |
2164 | ||
771fe6b9 JG |
2165 | /* X300 card with extra non-existent DVI port */ |
2166 | if (dev->pdev->device == 0x5B60 && | |
2167 | dev->pdev->subsystem_vendor == 0x17af && | |
2168 | dev->pdev->subsystem_device == 0x201e && bios_index == 2) { | |
2169 | if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) | |
2170 | return false; | |
2171 | } | |
2172 | ||
2173 | return true; | |
2174 | } | |
2175 | ||
790cfb34 AD |
2176 | static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) |
2177 | { | |
2178 | /* Acer 5102 has non-existent TV port */ | |
2179 | if (dev->pdev->device == 0x5975 && | |
2180 | dev->pdev->subsystem_vendor == 0x1025 && | |
2181 | dev->pdev->subsystem_device == 0x009f) | |
2182 | return false; | |
2183 | ||
fc7f7119 AD |
2184 | /* HP dc5750 has non-existent TV port */ |
2185 | if (dev->pdev->device == 0x5974 && | |
2186 | dev->pdev->subsystem_vendor == 0x103c && | |
2187 | dev->pdev->subsystem_device == 0x280a) | |
2188 | return false; | |
2189 | ||
fd874ad0 AD |
2190 | /* MSI S270 has non-existent TV port */ |
2191 | if (dev->pdev->device == 0x5955 && | |
2192 | dev->pdev->subsystem_vendor == 0x1462 && | |
2193 | dev->pdev->subsystem_device == 0x0131) | |
2194 | return false; | |
2195 | ||
790cfb34 AD |
2196 | return true; |
2197 | } | |
2198 | ||
b75fad06 AD |
2199 | static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) |
2200 | { | |
2201 | struct radeon_device *rdev = dev->dev_private; | |
2202 | uint32_t ext_tmds_info; | |
2203 | ||
2204 | if (rdev->flags & RADEON_IS_IGP) { | |
2205 | if (is_dvi_d) | |
2206 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; | |
2207 | else | |
2208 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; | |
2209 | } | |
2210 | ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); | |
2211 | if (ext_tmds_info) { | |
2212 | uint8_t rev = RBIOS8(ext_tmds_info); | |
2213 | uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); | |
2214 | if (rev >= 3) { | |
2215 | if (is_dvi_d) | |
2216 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; | |
2217 | else | |
2218 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; | |
2219 | } else { | |
2220 | if (flags & 1) { | |
2221 | if (is_dvi_d) | |
2222 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; | |
2223 | else | |
2224 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; | |
2225 | } | |
2226 | } | |
2227 | } | |
2228 | if (is_dvi_d) | |
2229 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; | |
2230 | else | |
2231 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; | |
2232 | } | |
2233 | ||
771fe6b9 JG |
2234 | bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) |
2235 | { | |
2236 | struct radeon_device *rdev = dev->dev_private; | |
2237 | uint32_t conn_info, entry, devices; | |
b75fad06 | 2238 | uint16_t tmp, connector_object_id; |
771fe6b9 JG |
2239 | enum radeon_combios_ddc ddc_type; |
2240 | enum radeon_combios_connector connector; | |
2241 | int i = 0; | |
2242 | struct radeon_i2c_bus_rec ddc_i2c; | |
eed45b30 | 2243 | struct radeon_hpd hpd; |
771fe6b9 | 2244 | |
771fe6b9 JG |
2245 | conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); |
2246 | if (conn_info) { | |
2247 | for (i = 0; i < 4; i++) { | |
2248 | entry = conn_info + 2 + i * 2; | |
2249 | ||
2250 | if (!RBIOS16(entry)) | |
2251 | break; | |
2252 | ||
2253 | tmp = RBIOS16(entry); | |
2254 | ||
2255 | connector = (tmp >> 12) & 0xf; | |
2256 | ||
2257 | ddc_type = (tmp >> 8) & 0xf; | |
179e8078 | 2258 | ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
771fe6b9 | 2259 | |
eed45b30 AD |
2260 | switch (connector) { |
2261 | case CONNECTOR_PROPRIETARY_LEGACY: | |
2262 | case CONNECTOR_DVI_I_LEGACY: | |
2263 | case CONNECTOR_DVI_D_LEGACY: | |
2264 | if ((tmp >> 4) & 0x1) | |
2265 | hpd.hpd = RADEON_HPD_2; | |
2266 | else | |
2267 | hpd.hpd = RADEON_HPD_1; | |
2268 | break; | |
2269 | default: | |
2270 | hpd.hpd = RADEON_HPD_NONE; | |
2271 | break; | |
2272 | } | |
2273 | ||
2d152c6b | 2274 | if (!radeon_apply_legacy_quirks(dev, i, &connector, |
eed45b30 | 2275 | &ddc_i2c, &hpd)) |
2d152c6b | 2276 | continue; |
771fe6b9 JG |
2277 | |
2278 | switch (connector) { | |
2279 | case CONNECTOR_PROPRIETARY_LEGACY: | |
2280 | if ((tmp >> 4) & 0x1) | |
2281 | devices = ATOM_DEVICE_DFP2_SUPPORT; | |
2282 | else | |
2283 | devices = ATOM_DEVICE_DFP1_SUPPORT; | |
2284 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2285 | radeon_get_encoder_enum |
771fe6b9 JG |
2286 | (dev, devices, 0), |
2287 | devices); | |
2288 | radeon_add_legacy_connector(dev, i, devices, | |
2289 | legacy_connector_convert | |
2290 | [connector], | |
b75fad06 | 2291 | &ddc_i2c, |
eed45b30 AD |
2292 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, |
2293 | &hpd); | |
771fe6b9 JG |
2294 | break; |
2295 | case CONNECTOR_CRT_LEGACY: | |
2296 | if (tmp & 0x1) { | |
2297 | devices = ATOM_DEVICE_CRT2_SUPPORT; | |
2298 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2299 | radeon_get_encoder_enum |
771fe6b9 JG |
2300 | (dev, |
2301 | ATOM_DEVICE_CRT2_SUPPORT, | |
2302 | 2), | |
2303 | ATOM_DEVICE_CRT2_SUPPORT); | |
2304 | } else { | |
2305 | devices = ATOM_DEVICE_CRT1_SUPPORT; | |
2306 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2307 | radeon_get_encoder_enum |
771fe6b9 JG |
2308 | (dev, |
2309 | ATOM_DEVICE_CRT1_SUPPORT, | |
2310 | 1), | |
2311 | ATOM_DEVICE_CRT1_SUPPORT); | |
2312 | } | |
2313 | radeon_add_legacy_connector(dev, | |
2314 | i, | |
2315 | devices, | |
2316 | legacy_connector_convert | |
2317 | [connector], | |
b75fad06 | 2318 | &ddc_i2c, |
eed45b30 AD |
2319 | CONNECTOR_OBJECT_ID_VGA, |
2320 | &hpd); | |
771fe6b9 JG |
2321 | break; |
2322 | case CONNECTOR_DVI_I_LEGACY: | |
2323 | devices = 0; | |
2324 | if (tmp & 0x1) { | |
2325 | devices |= ATOM_DEVICE_CRT2_SUPPORT; | |
2326 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2327 | radeon_get_encoder_enum |
771fe6b9 JG |
2328 | (dev, |
2329 | ATOM_DEVICE_CRT2_SUPPORT, | |
2330 | 2), | |
2331 | ATOM_DEVICE_CRT2_SUPPORT); | |
2332 | } else { | |
2333 | devices |= ATOM_DEVICE_CRT1_SUPPORT; | |
2334 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2335 | radeon_get_encoder_enum |
771fe6b9 JG |
2336 | (dev, |
2337 | ATOM_DEVICE_CRT1_SUPPORT, | |
2338 | 1), | |
2339 | ATOM_DEVICE_CRT1_SUPPORT); | |
2340 | } | |
2341 | if ((tmp >> 4) & 0x1) { | |
2342 | devices |= ATOM_DEVICE_DFP2_SUPPORT; | |
2343 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2344 | radeon_get_encoder_enum |
771fe6b9 JG |
2345 | (dev, |
2346 | ATOM_DEVICE_DFP2_SUPPORT, | |
2347 | 0), | |
2348 | ATOM_DEVICE_DFP2_SUPPORT); | |
b75fad06 | 2349 | connector_object_id = combios_check_dl_dvi(dev, 0); |
771fe6b9 JG |
2350 | } else { |
2351 | devices |= ATOM_DEVICE_DFP1_SUPPORT; | |
2352 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2353 | radeon_get_encoder_enum |
771fe6b9 JG |
2354 | (dev, |
2355 | ATOM_DEVICE_DFP1_SUPPORT, | |
2356 | 0), | |
2357 | ATOM_DEVICE_DFP1_SUPPORT); | |
b75fad06 | 2358 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
771fe6b9 JG |
2359 | } |
2360 | radeon_add_legacy_connector(dev, | |
2361 | i, | |
2362 | devices, | |
2363 | legacy_connector_convert | |
2364 | [connector], | |
b75fad06 | 2365 | &ddc_i2c, |
eed45b30 AD |
2366 | connector_object_id, |
2367 | &hpd); | |
771fe6b9 JG |
2368 | break; |
2369 | case CONNECTOR_DVI_D_LEGACY: | |
b75fad06 | 2370 | if ((tmp >> 4) & 0x1) { |
771fe6b9 | 2371 | devices = ATOM_DEVICE_DFP2_SUPPORT; |
b75fad06 AD |
2372 | connector_object_id = combios_check_dl_dvi(dev, 1); |
2373 | } else { | |
771fe6b9 | 2374 | devices = ATOM_DEVICE_DFP1_SUPPORT; |
b75fad06 AD |
2375 | connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
2376 | } | |
771fe6b9 | 2377 | radeon_add_legacy_encoder(dev, |
5137ee94 | 2378 | radeon_get_encoder_enum |
771fe6b9 JG |
2379 | (dev, devices, 0), |
2380 | devices); | |
2381 | radeon_add_legacy_connector(dev, i, devices, | |
2382 | legacy_connector_convert | |
2383 | [connector], | |
b75fad06 | 2384 | &ddc_i2c, |
eed45b30 AD |
2385 | connector_object_id, |
2386 | &hpd); | |
771fe6b9 JG |
2387 | break; |
2388 | case CONNECTOR_CTV_LEGACY: | |
2389 | case CONNECTOR_STV_LEGACY: | |
2390 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2391 | radeon_get_encoder_enum |
771fe6b9 JG |
2392 | (dev, |
2393 | ATOM_DEVICE_TV1_SUPPORT, | |
2394 | 2), | |
2395 | ATOM_DEVICE_TV1_SUPPORT); | |
2396 | radeon_add_legacy_connector(dev, i, | |
2397 | ATOM_DEVICE_TV1_SUPPORT, | |
2398 | legacy_connector_convert | |
2399 | [connector], | |
b75fad06 | 2400 | &ddc_i2c, |
eed45b30 AD |
2401 | CONNECTOR_OBJECT_ID_SVIDEO, |
2402 | &hpd); | |
771fe6b9 JG |
2403 | break; |
2404 | default: | |
2405 | DRM_ERROR("Unknown connector type: %d\n", | |
2406 | connector); | |
2407 | continue; | |
2408 | } | |
2409 | ||
2410 | } | |
2411 | } else { | |
2412 | uint16_t tmds_info = | |
2413 | combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); | |
2414 | if (tmds_info) { | |
d9fdaafb | 2415 | DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); |
771fe6b9 JG |
2416 | |
2417 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2418 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
2419 | ATOM_DEVICE_CRT1_SUPPORT, |
2420 | 1), | |
2421 | ATOM_DEVICE_CRT1_SUPPORT); | |
2422 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2423 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
2424 | ATOM_DEVICE_DFP1_SUPPORT, |
2425 | 0), | |
2426 | ATOM_DEVICE_DFP1_SUPPORT); | |
2427 | ||
179e8078 | 2428 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
8e36ed00 | 2429 | hpd.hpd = RADEON_HPD_1; |
771fe6b9 JG |
2430 | radeon_add_legacy_connector(dev, |
2431 | 0, | |
2432 | ATOM_DEVICE_CRT1_SUPPORT | | |
2433 | ATOM_DEVICE_DFP1_SUPPORT, | |
2434 | DRM_MODE_CONNECTOR_DVII, | |
b75fad06 | 2435 | &ddc_i2c, |
eed45b30 AD |
2436 | CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
2437 | &hpd); | |
771fe6b9 | 2438 | } else { |
d0c403e9 AD |
2439 | uint16_t crt_info = |
2440 | combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); | |
d9fdaafb | 2441 | DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); |
d0c403e9 AD |
2442 | if (crt_info) { |
2443 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2444 | radeon_get_encoder_enum(dev, |
d0c403e9 AD |
2445 | ATOM_DEVICE_CRT1_SUPPORT, |
2446 | 1), | |
2447 | ATOM_DEVICE_CRT1_SUPPORT); | |
179e8078 | 2448 | ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
eed45b30 | 2449 | hpd.hpd = RADEON_HPD_NONE; |
d0c403e9 AD |
2450 | radeon_add_legacy_connector(dev, |
2451 | 0, | |
2452 | ATOM_DEVICE_CRT1_SUPPORT, | |
2453 | DRM_MODE_CONNECTOR_VGA, | |
b75fad06 | 2454 | &ddc_i2c, |
eed45b30 AD |
2455 | CONNECTOR_OBJECT_ID_VGA, |
2456 | &hpd); | |
d0c403e9 | 2457 | } else { |
d9fdaafb | 2458 | DRM_DEBUG_KMS("No connector info found\n"); |
d0c403e9 AD |
2459 | return false; |
2460 | } | |
771fe6b9 JG |
2461 | } |
2462 | } | |
2463 | ||
2464 | if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { | |
2465 | uint16_t lcd_info = | |
2466 | combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); | |
2467 | if (lcd_info) { | |
2468 | uint16_t lcd_ddc_info = | |
2469 | combios_get_table_offset(dev, | |
2470 | COMBIOS_LCD_DDC_INFO_TABLE); | |
2471 | ||
2472 | radeon_add_legacy_encoder(dev, | |
5137ee94 | 2473 | radeon_get_encoder_enum(dev, |
771fe6b9 JG |
2474 | ATOM_DEVICE_LCD1_SUPPORT, |
2475 | 0), | |
2476 | ATOM_DEVICE_LCD1_SUPPORT); | |
2477 | ||
2478 | if (lcd_ddc_info) { | |
2479 | ddc_type = RBIOS8(lcd_ddc_info + 2); | |
2480 | switch (ddc_type) { | |
771fe6b9 JG |
2481 | case DDC_LCD: |
2482 | ddc_i2c = | |
179e8078 AD |
2483 | combios_setup_i2c_bus(rdev, |
2484 | DDC_LCD, | |
2485 | RBIOS32(lcd_ddc_info + 3), | |
2486 | RBIOS32(lcd_ddc_info + 7)); | |
f376b94f | 2487 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
771fe6b9 JG |
2488 | break; |
2489 | case DDC_GPIO: | |
2490 | ddc_i2c = | |
179e8078 AD |
2491 | combios_setup_i2c_bus(rdev, |
2492 | DDC_GPIO, | |
2493 | RBIOS32(lcd_ddc_info + 3), | |
2494 | RBIOS32(lcd_ddc_info + 7)); | |
f376b94f | 2495 | radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
771fe6b9 JG |
2496 | break; |
2497 | default: | |
179e8078 AD |
2498 | ddc_i2c = |
2499 | combios_setup_i2c_bus(rdev, ddc_type, 0, 0); | |
771fe6b9 JG |
2500 | break; |
2501 | } | |
d9fdaafb | 2502 | DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); |
771fe6b9 JG |
2503 | } else |
2504 | ddc_i2c.valid = false; | |
2505 | ||
eed45b30 | 2506 | hpd.hpd = RADEON_HPD_NONE; |
771fe6b9 JG |
2507 | radeon_add_legacy_connector(dev, |
2508 | 5, | |
2509 | ATOM_DEVICE_LCD1_SUPPORT, | |
2510 | DRM_MODE_CONNECTOR_LVDS, | |
b75fad06 | 2511 | &ddc_i2c, |
eed45b30 AD |
2512 | CONNECTOR_OBJECT_ID_LVDS, |
2513 | &hpd); | |
771fe6b9 JG |
2514 | } |
2515 | } | |
2516 | ||
2517 | /* check TV table */ | |
2518 | if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { | |
2519 | uint32_t tv_info = | |
2520 | combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); | |
2521 | if (tv_info) { | |
2522 | if (RBIOS8(tv_info + 6) == 'T') { | |
790cfb34 | 2523 | if (radeon_apply_legacy_tv_quirks(dev)) { |
eed45b30 | 2524 | hpd.hpd = RADEON_HPD_NONE; |
d294ed69 | 2525 | ddc_i2c.valid = false; |
790cfb34 | 2526 | radeon_add_legacy_encoder(dev, |
5137ee94 | 2527 | radeon_get_encoder_enum |
790cfb34 AD |
2528 | (dev, |
2529 | ATOM_DEVICE_TV1_SUPPORT, | |
2530 | 2), | |
2531 | ATOM_DEVICE_TV1_SUPPORT); | |
2532 | radeon_add_legacy_connector(dev, 6, | |
2533 | ATOM_DEVICE_TV1_SUPPORT, | |
2534 | DRM_MODE_CONNECTOR_SVIDEO, | |
b75fad06 | 2535 | &ddc_i2c, |
eed45b30 AD |
2536 | CONNECTOR_OBJECT_ID_SVIDEO, |
2537 | &hpd); | |
790cfb34 | 2538 | } |
771fe6b9 JG |
2539 | } |
2540 | } | |
2541 | } | |
2542 | ||
2543 | radeon_link_encoder_connector(dev); | |
2544 | ||
2545 | return true; | |
2546 | } | |
2547 | ||
63f7d982 AD |
2548 | static const char *thermal_controller_names[] = { |
2549 | "NONE", | |
2550 | "lm63", | |
2551 | "adm1032", | |
2552 | }; | |
2553 | ||
56278a8e AD |
2554 | void radeon_combios_get_power_modes(struct radeon_device *rdev) |
2555 | { | |
2556 | struct drm_device *dev = rdev->ddev; | |
2557 | u16 offset, misc, misc2 = 0; | |
2558 | u8 rev, blocks, tmp; | |
2559 | int state_index = 0; | |
c41b9ee9 | 2560 | struct radeon_i2c_bus_rec i2c_bus; |
56278a8e | 2561 | |
a48b9b4e | 2562 | rdev->pm.default_power_state_index = -1; |
56278a8e | 2563 | |
0975b162 AD |
2564 | /* allocate 2 power states */ |
2565 | rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL); | |
a7c36fd8 AD |
2566 | if (rdev->pm.power_state) { |
2567 | /* allocate 1 clock mode per state */ | |
2568 | rdev->pm.power_state[0].clock_info = | |
2569 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); | |
2570 | rdev->pm.power_state[1].clock_info = | |
2571 | kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); | |
2572 | if (!rdev->pm.power_state[0].clock_info || | |
2573 | !rdev->pm.power_state[1].clock_info) | |
2574 | goto pm_failed; | |
2575 | } else | |
2576 | goto pm_failed; | |
0975b162 | 2577 | |
63f7d982 AD |
2578 | /* check for a thermal chip */ |
2579 | offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); | |
2580 | if (offset) { | |
2581 | u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; | |
63f7d982 AD |
2582 | |
2583 | rev = RBIOS8(offset); | |
2584 | ||
2585 | if (rev == 0) { | |
2586 | thermal_controller = RBIOS8(offset + 3); | |
2587 | gpio = RBIOS8(offset + 4) & 0x3f; | |
2588 | i2c_addr = RBIOS8(offset + 5); | |
2589 | } else if (rev == 1) { | |
2590 | thermal_controller = RBIOS8(offset + 4); | |
2591 | gpio = RBIOS8(offset + 5) & 0x3f; | |
2592 | i2c_addr = RBIOS8(offset + 6); | |
2593 | } else if (rev == 2) { | |
2594 | thermal_controller = RBIOS8(offset + 4); | |
2595 | gpio = RBIOS8(offset + 5) & 0x3f; | |
2596 | i2c_addr = RBIOS8(offset + 6); | |
2597 | clk_bit = RBIOS8(offset + 0xa); | |
2598 | data_bit = RBIOS8(offset + 0xb); | |
2599 | } | |
2600 | if ((thermal_controller > 0) && (thermal_controller < 3)) { | |
2601 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", | |
2602 | thermal_controller_names[thermal_controller], | |
2603 | i2c_addr >> 1); | |
2604 | if (gpio == DDC_LCD) { | |
2605 | /* MM i2c */ | |
2606 | i2c_bus.valid = true; | |
2607 | i2c_bus.hw_capable = true; | |
2608 | i2c_bus.mm_i2c = true; | |
2609 | i2c_bus.i2c_id = 0xa0; | |
2610 | } else if (gpio == DDC_GPIO) | |
2611 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); | |
2612 | else | |
2613 | i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); | |
2614 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); | |
2615 | if (rdev->pm.i2c_bus) { | |
2616 | struct i2c_board_info info = { }; | |
2617 | const char *name = thermal_controller_names[thermal_controller]; | |
2618 | info.addr = i2c_addr >> 1; | |
2619 | strlcpy(info.type, name, sizeof(info.type)); | |
2620 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); | |
2621 | } | |
2622 | } | |
c41b9ee9 AD |
2623 | } else { |
2624 | /* boards with a thermal chip, but no overdrive table */ | |
2625 | ||
2626 | /* Asus 9600xt has an f75375 on the monid bus */ | |
2627 | if ((dev->pdev->device == 0x4152) && | |
2628 | (dev->pdev->subsystem_vendor == 0x1043) && | |
2629 | (dev->pdev->subsystem_device == 0xc002)) { | |
2630 | i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); | |
2631 | rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); | |
2632 | if (rdev->pm.i2c_bus) { | |
2633 | struct i2c_board_info info = { }; | |
2634 | const char *name = "f75375"; | |
2635 | info.addr = 0x28; | |
2636 | strlcpy(info.type, name, sizeof(info.type)); | |
2637 | i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); | |
2638 | DRM_INFO("Possible %s thermal controller at 0x%02x\n", | |
2639 | name, info.addr); | |
2640 | } | |
2641 | } | |
63f7d982 AD |
2642 | } |
2643 | ||
56278a8e AD |
2644 | if (rdev->flags & RADEON_IS_MOBILITY) { |
2645 | offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); | |
2646 | if (offset) { | |
2647 | rev = RBIOS8(offset); | |
2648 | blocks = RBIOS8(offset + 0x2); | |
2649 | /* power mode 0 tends to be the only valid one */ | |
2650 | rdev->pm.power_state[state_index].num_clock_modes = 1; | |
2651 | rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); | |
2652 | rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); | |
2653 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | |
2654 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | |
2655 | goto default_mode; | |
0ec0e74f AD |
2656 | rdev->pm.power_state[state_index].type = |
2657 | POWER_STATE_TYPE_BATTERY; | |
56278a8e AD |
2658 | misc = RBIOS16(offset + 0x5 + 0x0); |
2659 | if (rev > 4) | |
2660 | misc2 = RBIOS16(offset + 0x5 + 0xe); | |
79daedc9 AD |
2661 | rdev->pm.power_state[state_index].misc = misc; |
2662 | rdev->pm.power_state[state_index].misc2 = misc2; | |
56278a8e AD |
2663 | if (misc & 0x4) { |
2664 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; | |
2665 | if (misc & 0x8) | |
2666 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
2667 | true; | |
2668 | else | |
2669 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
2670 | false; | |
2671 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; | |
2672 | if (rev < 6) { | |
2673 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = | |
2674 | RBIOS16(offset + 0x5 + 0xb) * 4; | |
2675 | tmp = RBIOS8(offset + 0x5 + 0xd); | |
2676 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); | |
2677 | } else { | |
2678 | u8 entries = RBIOS8(offset + 0x5 + 0xb); | |
2679 | u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); | |
2680 | if (entries && voltage_table_offset) { | |
2681 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = | |
2682 | RBIOS16(voltage_table_offset) * 4; | |
2683 | tmp = RBIOS8(voltage_table_offset + 0x2); | |
2684 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); | |
2685 | } else | |
2686 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; | |
2687 | } | |
2688 | switch ((misc2 & 0x700) >> 8) { | |
2689 | case 0: | |
2690 | default: | |
2691 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; | |
2692 | break; | |
2693 | case 1: | |
2694 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; | |
2695 | break; | |
2696 | case 2: | |
2697 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; | |
2698 | break; | |
2699 | case 3: | |
2700 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; | |
2701 | break; | |
2702 | case 4: | |
2703 | rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; | |
2704 | break; | |
2705 | } | |
2706 | } else | |
2707 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; | |
2708 | if (rev > 6) | |
79daedc9 | 2709 | rdev->pm.power_state[state_index].pcie_lanes = |
56278a8e | 2710 | RBIOS8(offset + 0x5 + 0x10); |
d7311171 | 2711 | rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
56278a8e AD |
2712 | state_index++; |
2713 | } else { | |
2714 | /* XXX figure out some good default low power mode for mobility cards w/out power tables */ | |
2715 | } | |
2716 | } else { | |
2717 | /* XXX figure out some good default low power mode for desktop cards */ | |
2718 | } | |
2719 | ||
2720 | default_mode: | |
2721 | /* add the default mode */ | |
0ec0e74f AD |
2722 | rdev->pm.power_state[state_index].type = |
2723 | POWER_STATE_TYPE_DEFAULT; | |
56278a8e AD |
2724 | rdev->pm.power_state[state_index].num_clock_modes = 1; |
2725 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; | |
2726 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; | |
2727 | rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; | |
84d88f4c | 2728 | if ((state_index > 0) && |
8de016e2 | 2729 | (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) |
84d88f4c AD |
2730 | rdev->pm.power_state[state_index].clock_info[0].voltage = |
2731 | rdev->pm.power_state[0].clock_info[0].voltage; | |
2732 | else | |
2733 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; | |
79daedc9 | 2734 | rdev->pm.power_state[state_index].pcie_lanes = 16; |
a48b9b4e AD |
2735 | rdev->pm.power_state[state_index].flags = 0; |
2736 | rdev->pm.default_power_state_index = state_index; | |
56278a8e | 2737 | rdev->pm.num_power_states = state_index + 1; |
9038dfdf | 2738 | |
a7c36fd8 AD |
2739 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
2740 | rdev->pm.current_clock_mode_index = 0; | |
2741 | return; | |
2742 | ||
2743 | pm_failed: | |
2744 | rdev->pm.default_power_state_index = state_index; | |
2745 | rdev->pm.num_power_states = 0; | |
2746 | ||
a48b9b4e AD |
2747 | rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
2748 | rdev->pm.current_clock_mode_index = 0; | |
56278a8e AD |
2749 | } |
2750 | ||
fcec570b AD |
2751 | void radeon_external_tmds_setup(struct drm_encoder *encoder) |
2752 | { | |
2753 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2754 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; | |
2755 | ||
2756 | if (!tmds) | |
2757 | return; | |
2758 | ||
2759 | switch (tmds->dvo_chip) { | |
2760 | case DVO_SIL164: | |
2761 | /* sil 164 */ | |
5a6f98f5 AD |
2762 | radeon_i2c_put_byte(tmds->i2c_bus, |
2763 | tmds->slave_addr, | |
2764 | 0x08, 0x30); | |
2765 | radeon_i2c_put_byte(tmds->i2c_bus, | |
fcec570b AD |
2766 | tmds->slave_addr, |
2767 | 0x09, 0x00); | |
5a6f98f5 AD |
2768 | radeon_i2c_put_byte(tmds->i2c_bus, |
2769 | tmds->slave_addr, | |
2770 | 0x0a, 0x90); | |
2771 | radeon_i2c_put_byte(tmds->i2c_bus, | |
2772 | tmds->slave_addr, | |
2773 | 0x0c, 0x89); | |
2774 | radeon_i2c_put_byte(tmds->i2c_bus, | |
fcec570b AD |
2775 | tmds->slave_addr, |
2776 | 0x08, 0x3b); | |
fcec570b AD |
2777 | break; |
2778 | case DVO_SIL1178: | |
2779 | /* sil 1178 - untested */ | |
2780 | /* | |
2781 | * 0x0f, 0x44 | |
2782 | * 0x0f, 0x4c | |
2783 | * 0x0e, 0x01 | |
2784 | * 0x0a, 0x80 | |
2785 | * 0x09, 0x30 | |
2786 | * 0x0c, 0xc9 | |
2787 | * 0x0d, 0x70 | |
2788 | * 0x08, 0x32 | |
2789 | * 0x08, 0x33 | |
2790 | */ | |
2791 | break; | |
2792 | default: | |
2793 | break; | |
2794 | } | |
2795 | ||
2796 | } | |
2797 | ||
2798 | bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) | |
2799 | { | |
2800 | struct drm_device *dev = encoder->dev; | |
2801 | struct radeon_device *rdev = dev->dev_private; | |
2802 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2803 | uint16_t offset; | |
2804 | uint8_t blocks, slave_addr, rev; | |
2805 | uint32_t index, id; | |
2806 | uint32_t reg, val, and_mask, or_mask; | |
2807 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; | |
2808 | ||
fcec570b AD |
2809 | if (!tmds) |
2810 | return false; | |
2811 | ||
2812 | if (rdev->flags & RADEON_IS_IGP) { | |
2813 | offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); | |
2814 | rev = RBIOS8(offset); | |
2815 | if (offset) { | |
2816 | rev = RBIOS8(offset); | |
2817 | if (rev > 1) { | |
2818 | blocks = RBIOS8(offset + 3); | |
2819 | index = offset + 4; | |
2820 | while (blocks > 0) { | |
2821 | id = RBIOS16(index); | |
2822 | index += 2; | |
2823 | switch (id >> 13) { | |
2824 | case 0: | |
2825 | reg = (id & 0x1fff) * 4; | |
2826 | val = RBIOS32(index); | |
2827 | index += 4; | |
2828 | WREG32(reg, val); | |
2829 | break; | |
2830 | case 2: | |
2831 | reg = (id & 0x1fff) * 4; | |
2832 | and_mask = RBIOS32(index); | |
2833 | index += 4; | |
2834 | or_mask = RBIOS32(index); | |
2835 | index += 4; | |
2836 | val = RREG32(reg); | |
2837 | val = (val & and_mask) | or_mask; | |
2838 | WREG32(reg, val); | |
2839 | break; | |
2840 | case 3: | |
2841 | val = RBIOS16(index); | |
2842 | index += 2; | |
2843 | udelay(val); | |
2844 | break; | |
2845 | case 4: | |
2846 | val = RBIOS16(index); | |
2847 | index += 2; | |
2848 | udelay(val * 1000); | |
2849 | break; | |
2850 | case 6: | |
2851 | slave_addr = id & 0xff; | |
2852 | slave_addr >>= 1; /* 7 bit addressing */ | |
2853 | index++; | |
2854 | reg = RBIOS8(index); | |
2855 | index++; | |
2856 | val = RBIOS8(index); | |
2857 | index++; | |
5a6f98f5 AD |
2858 | radeon_i2c_put_byte(tmds->i2c_bus, |
2859 | slave_addr, | |
2860 | reg, val); | |
fcec570b AD |
2861 | break; |
2862 | default: | |
2863 | DRM_ERROR("Unknown id %d\n", id >> 13); | |
2864 | break; | |
2865 | } | |
2866 | blocks--; | |
2867 | } | |
2868 | return true; | |
2869 | } | |
2870 | } | |
2871 | } else { | |
2872 | offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); | |
2873 | if (offset) { | |
2874 | index = offset + 10; | |
2875 | id = RBIOS16(index); | |
2876 | while (id != 0xffff) { | |
2877 | index += 2; | |
2878 | switch (id >> 13) { | |
2879 | case 0: | |
2880 | reg = (id & 0x1fff) * 4; | |
2881 | val = RBIOS32(index); | |
2882 | WREG32(reg, val); | |
2883 | break; | |
2884 | case 2: | |
2885 | reg = (id & 0x1fff) * 4; | |
2886 | and_mask = RBIOS32(index); | |
2887 | index += 4; | |
2888 | or_mask = RBIOS32(index); | |
2889 | index += 4; | |
2890 | val = RREG32(reg); | |
2891 | val = (val & and_mask) | or_mask; | |
2892 | WREG32(reg, val); | |
2893 | break; | |
2894 | case 4: | |
2895 | val = RBIOS16(index); | |
2896 | index += 2; | |
2897 | udelay(val); | |
2898 | break; | |
2899 | case 5: | |
2900 | reg = id & 0x1fff; | |
2901 | and_mask = RBIOS32(index); | |
2902 | index += 4; | |
2903 | or_mask = RBIOS32(index); | |
2904 | index += 4; | |
2905 | val = RREG32_PLL(reg); | |
2906 | val = (val & and_mask) | or_mask; | |
2907 | WREG32_PLL(reg, val); | |
2908 | break; | |
2909 | case 6: | |
2910 | reg = id & 0x1fff; | |
2911 | val = RBIOS8(index); | |
2912 | index += 1; | |
5a6f98f5 AD |
2913 | radeon_i2c_put_byte(tmds->i2c_bus, |
2914 | tmds->slave_addr, | |
2915 | reg, val); | |
fcec570b AD |
2916 | break; |
2917 | default: | |
2918 | DRM_ERROR("Unknown id %d\n", id >> 13); | |
2919 | break; | |
2920 | } | |
2921 | id = RBIOS16(index); | |
2922 | } | |
2923 | return true; | |
2924 | } | |
2925 | } | |
2926 | return false; | |
2927 | } | |
2928 | ||
771fe6b9 JG |
2929 | static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) |
2930 | { | |
2931 | struct radeon_device *rdev = dev->dev_private; | |
2932 | ||
2933 | if (offset) { | |
2934 | while (RBIOS16(offset)) { | |
2935 | uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); | |
2936 | uint32_t addr = (RBIOS16(offset) & 0x1fff); | |
2937 | uint32_t val, and_mask, or_mask; | |
2938 | uint32_t tmp; | |
2939 | ||
2940 | offset += 2; | |
2941 | switch (cmd) { | |
2942 | case 0: | |
2943 | val = RBIOS32(offset); | |
2944 | offset += 4; | |
2945 | WREG32(addr, val); | |
2946 | break; | |
2947 | case 1: | |
2948 | val = RBIOS32(offset); | |
2949 | offset += 4; | |
2950 | WREG32(addr, val); | |
2951 | break; | |
2952 | case 2: | |
2953 | and_mask = RBIOS32(offset); | |
2954 | offset += 4; | |
2955 | or_mask = RBIOS32(offset); | |
2956 | offset += 4; | |
2957 | tmp = RREG32(addr); | |
2958 | tmp &= and_mask; | |
2959 | tmp |= or_mask; | |
2960 | WREG32(addr, tmp); | |
2961 | break; | |
2962 | case 3: | |
2963 | and_mask = RBIOS32(offset); | |
2964 | offset += 4; | |
2965 | or_mask = RBIOS32(offset); | |
2966 | offset += 4; | |
2967 | tmp = RREG32(addr); | |
2968 | tmp &= and_mask; | |
2969 | tmp |= or_mask; | |
2970 | WREG32(addr, tmp); | |
2971 | break; | |
2972 | case 4: | |
2973 | val = RBIOS16(offset); | |
2974 | offset += 2; | |
2975 | udelay(val); | |
2976 | break; | |
2977 | case 5: | |
2978 | val = RBIOS16(offset); | |
2979 | offset += 2; | |
2980 | switch (addr) { | |
2981 | case 8: | |
2982 | while (val--) { | |
2983 | if (! | |
2984 | (RREG32_PLL | |
2985 | (RADEON_CLK_PWRMGT_CNTL) & | |
2986 | RADEON_MC_BUSY)) | |
2987 | break; | |
2988 | } | |
2989 | break; | |
2990 | case 9: | |
2991 | while (val--) { | |
2992 | if ((RREG32(RADEON_MC_STATUS) & | |
2993 | RADEON_MC_IDLE)) | |
2994 | break; | |
2995 | } | |
2996 | break; | |
2997 | default: | |
2998 | break; | |
2999 | } | |
3000 | break; | |
3001 | default: | |
3002 | break; | |
3003 | } | |
3004 | } | |
3005 | } | |
3006 | } | |
3007 | ||
3008 | static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) | |
3009 | { | |
3010 | struct radeon_device *rdev = dev->dev_private; | |
3011 | ||
3012 | if (offset) { | |
3013 | while (RBIOS8(offset)) { | |
3014 | uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); | |
3015 | uint8_t addr = (RBIOS8(offset) & 0x3f); | |
3016 | uint32_t val, shift, tmp; | |
3017 | uint32_t and_mask, or_mask; | |
3018 | ||
3019 | offset++; | |
3020 | switch (cmd) { | |
3021 | case 0: | |
3022 | val = RBIOS32(offset); | |
3023 | offset += 4; | |
3024 | WREG32_PLL(addr, val); | |
3025 | break; | |
3026 | case 1: | |
3027 | shift = RBIOS8(offset) * 8; | |
3028 | offset++; | |
3029 | and_mask = RBIOS8(offset) << shift; | |
3030 | and_mask |= ~(0xff << shift); | |
3031 | offset++; | |
3032 | or_mask = RBIOS8(offset) << shift; | |
3033 | offset++; | |
3034 | tmp = RREG32_PLL(addr); | |
3035 | tmp &= and_mask; | |
3036 | tmp |= or_mask; | |
3037 | WREG32_PLL(addr, tmp); | |
3038 | break; | |
3039 | case 2: | |
3040 | case 3: | |
3041 | tmp = 1000; | |
3042 | switch (addr) { | |
3043 | case 1: | |
3044 | udelay(150); | |
3045 | break; | |
3046 | case 2: | |
3047 | udelay(1000); | |
3048 | break; | |
3049 | case 3: | |
3050 | while (tmp--) { | |
3051 | if (! | |
3052 | (RREG32_PLL | |
3053 | (RADEON_CLK_PWRMGT_CNTL) & | |
3054 | RADEON_MC_BUSY)) | |
3055 | break; | |
3056 | } | |
3057 | break; | |
3058 | case 4: | |
3059 | while (tmp--) { | |
3060 | if (RREG32_PLL | |
3061 | (RADEON_CLK_PWRMGT_CNTL) & | |
3062 | RADEON_DLL_READY) | |
3063 | break; | |
3064 | } | |
3065 | break; | |
3066 | case 5: | |
3067 | tmp = | |
3068 | RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); | |
3069 | if (tmp & RADEON_CG_NO1_DEBUG_0) { | |
3070 | #if 0 | |
3071 | uint32_t mclk_cntl = | |
3072 | RREG32_PLL | |
3073 | (RADEON_MCLK_CNTL); | |
3074 | mclk_cntl &= 0xffff0000; | |
3075 | /*mclk_cntl |= 0x00001111;*//* ??? */ | |
3076 | WREG32_PLL(RADEON_MCLK_CNTL, | |
3077 | mclk_cntl); | |
3078 | udelay(10000); | |
3079 | #endif | |
3080 | WREG32_PLL | |
3081 | (RADEON_CLK_PWRMGT_CNTL, | |
3082 | tmp & | |
3083 | ~RADEON_CG_NO1_DEBUG_0); | |
3084 | udelay(10000); | |
3085 | } | |
3086 | break; | |
3087 | default: | |
3088 | break; | |
3089 | } | |
3090 | break; | |
3091 | default: | |
3092 | break; | |
3093 | } | |
3094 | } | |
3095 | } | |
3096 | } | |
3097 | ||
3098 | static void combios_parse_ram_reset_table(struct drm_device *dev, | |
3099 | uint16_t offset) | |
3100 | { | |
3101 | struct radeon_device *rdev = dev->dev_private; | |
3102 | uint32_t tmp; | |
3103 | ||
3104 | if (offset) { | |
3105 | uint8_t val = RBIOS8(offset); | |
3106 | while (val != 0xff) { | |
3107 | offset++; | |
3108 | ||
3109 | if (val == 0x0f) { | |
3110 | uint32_t channel_complete_mask; | |
3111 | ||
3112 | if (ASIC_IS_R300(rdev)) | |
3113 | channel_complete_mask = | |
3114 | R300_MEM_PWRUP_COMPLETE; | |
3115 | else | |
3116 | channel_complete_mask = | |
3117 | RADEON_MEM_PWRUP_COMPLETE; | |
3118 | tmp = 20000; | |
3119 | while (tmp--) { | |
3120 | if ((RREG32(RADEON_MEM_STR_CNTL) & | |
3121 | channel_complete_mask) == | |
3122 | channel_complete_mask) | |
3123 | break; | |
3124 | } | |
3125 | } else { | |
3126 | uint32_t or_mask = RBIOS16(offset); | |
3127 | offset += 2; | |
3128 | ||
3129 | tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); | |
3130 | tmp &= RADEON_SDRAM_MODE_MASK; | |
3131 | tmp |= or_mask; | |
3132 | WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); | |
3133 | ||
3134 | or_mask = val << 24; | |
3135 | tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); | |
3136 | tmp &= RADEON_B3MEM_RESET_MASK; | |
3137 | tmp |= or_mask; | |
3138 | WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); | |
3139 | } | |
3140 | val = RBIOS8(offset); | |
3141 | } | |
3142 | } | |
3143 | } | |
3144 | ||
3145 | static uint32_t combios_detect_ram(struct drm_device *dev, int ram, | |
3146 | int mem_addr_mapping) | |
3147 | { | |
3148 | struct radeon_device *rdev = dev->dev_private; | |
3149 | uint32_t mem_cntl; | |
3150 | uint32_t mem_size; | |
3151 | uint32_t addr = 0; | |
3152 | ||
3153 | mem_cntl = RREG32(RADEON_MEM_CNTL); | |
3154 | if (mem_cntl & RV100_HALF_MODE) | |
3155 | ram /= 2; | |
3156 | mem_size = ram; | |
3157 | mem_cntl &= ~(0xff << 8); | |
3158 | mem_cntl |= (mem_addr_mapping & 0xff) << 8; | |
3159 | WREG32(RADEON_MEM_CNTL, mem_cntl); | |
3160 | RREG32(RADEON_MEM_CNTL); | |
3161 | ||
3162 | /* sdram reset ? */ | |
3163 | ||
3164 | /* something like this???? */ | |
3165 | while (ram--) { | |
3166 | addr = ram * 1024 * 1024; | |
3167 | /* write to each page */ | |
3168 | WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); | |
3169 | WREG32(RADEON_MM_DATA, 0xdeadbeef); | |
3170 | /* read back and verify */ | |
3171 | WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER); | |
3172 | if (RREG32(RADEON_MM_DATA) != 0xdeadbeef) | |
3173 | return 0; | |
3174 | } | |
3175 | ||
3176 | return mem_size; | |
3177 | } | |
3178 | ||
3179 | static void combios_write_ram_size(struct drm_device *dev) | |
3180 | { | |
3181 | struct radeon_device *rdev = dev->dev_private; | |
3182 | uint8_t rev; | |
3183 | uint16_t offset; | |
3184 | uint32_t mem_size = 0; | |
3185 | uint32_t mem_cntl = 0; | |
3186 | ||
3187 | /* should do something smarter here I guess... */ | |
3188 | if (rdev->flags & RADEON_IS_IGP) | |
3189 | return; | |
3190 | ||
3191 | /* first check detected mem table */ | |
3192 | offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); | |
3193 | if (offset) { | |
3194 | rev = RBIOS8(offset); | |
3195 | if (rev < 3) { | |
3196 | mem_cntl = RBIOS32(offset + 1); | |
3197 | mem_size = RBIOS16(offset + 5); | |
4ce9198e AD |
3198 | if ((rdev->family < CHIP_R200) && |
3199 | !ASIC_IS_RN50(rdev)) | |
771fe6b9 JG |
3200 | WREG32(RADEON_MEM_CNTL, mem_cntl); |
3201 | } | |
3202 | } | |
3203 | ||
3204 | if (!mem_size) { | |
3205 | offset = | |
3206 | combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); | |
3207 | if (offset) { | |
3208 | rev = RBIOS8(offset - 1); | |
3209 | if (rev < 1) { | |
4ce9198e AD |
3210 | if ((rdev->family < CHIP_R200) |
3211 | && !ASIC_IS_RN50(rdev)) { | |
771fe6b9 JG |
3212 | int ram = 0; |
3213 | int mem_addr_mapping = 0; | |
3214 | ||
3215 | while (RBIOS8(offset)) { | |
3216 | ram = RBIOS8(offset); | |
3217 | mem_addr_mapping = | |
3218 | RBIOS8(offset + 1); | |
3219 | if (mem_addr_mapping != 0x25) | |
3220 | ram *= 2; | |
3221 | mem_size = | |
3222 | combios_detect_ram(dev, ram, | |
3223 | mem_addr_mapping); | |
3224 | if (mem_size) | |
3225 | break; | |
3226 | offset += 2; | |
3227 | } | |
3228 | } else | |
3229 | mem_size = RBIOS8(offset); | |
3230 | } else { | |
3231 | mem_size = RBIOS8(offset); | |
3232 | mem_size *= 2; /* convert to MB */ | |
3233 | } | |
3234 | } | |
3235 | } | |
3236 | ||
3237 | mem_size *= (1024 * 1024); /* convert to bytes */ | |
3238 | WREG32(RADEON_CONFIG_MEMSIZE, mem_size); | |
3239 | } | |
3240 | ||
3241 | void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable) | |
3242 | { | |
3243 | uint16_t dyn_clk_info = | |
3244 | combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); | |
3245 | ||
3246 | if (dyn_clk_info) | |
3247 | combios_parse_pll_table(dev, dyn_clk_info); | |
3248 | } | |
3249 | ||
3250 | void radeon_combios_asic_init(struct drm_device *dev) | |
3251 | { | |
3252 | struct radeon_device *rdev = dev->dev_private; | |
3253 | uint16_t table; | |
3254 | ||
3255 | /* port hardcoded mac stuff from radeonfb */ | |
3256 | if (rdev->bios == NULL) | |
3257 | return; | |
3258 | ||
3259 | /* ASIC INIT 1 */ | |
3260 | table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); | |
3261 | if (table) | |
3262 | combios_parse_mmio_table(dev, table); | |
3263 | ||
3264 | /* PLL INIT */ | |
3265 | table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); | |
3266 | if (table) | |
3267 | combios_parse_pll_table(dev, table); | |
3268 | ||
3269 | /* ASIC INIT 2 */ | |
3270 | table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); | |
3271 | if (table) | |
3272 | combios_parse_mmio_table(dev, table); | |
3273 | ||
3274 | if (!(rdev->flags & RADEON_IS_IGP)) { | |
3275 | /* ASIC INIT 4 */ | |
3276 | table = | |
3277 | combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); | |
3278 | if (table) | |
3279 | combios_parse_mmio_table(dev, table); | |
3280 | ||
3281 | /* RAM RESET */ | |
3282 | table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); | |
3283 | if (table) | |
3284 | combios_parse_ram_reset_table(dev, table); | |
3285 | ||
3286 | /* ASIC INIT 3 */ | |
3287 | table = | |
3288 | combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); | |
3289 | if (table) | |
3290 | combios_parse_mmio_table(dev, table); | |
3291 | ||
3292 | /* write CONFIG_MEMSIZE */ | |
3293 | combios_write_ram_size(dev); | |
3294 | } | |
3295 | ||
580b4fff DA |
3296 | /* quirk for rs4xx HP nx6125 laptop to make it resume |
3297 | * - it hangs on resume inside the dynclk 1 table. | |
3298 | */ | |
3299 | if (rdev->family == CHIP_RS480 && | |
3300 | rdev->pdev->subsystem_vendor == 0x103c && | |
3301 | rdev->pdev->subsystem_device == 0x308b) | |
3302 | return; | |
3303 | ||
52fa2bbc AD |
3304 | /* quirk for rs4xx HP dv5000 laptop to make it resume |
3305 | * - it hangs on resume inside the dynclk 1 table. | |
3306 | */ | |
3307 | if (rdev->family == CHIP_RS480 && | |
3308 | rdev->pdev->subsystem_vendor == 0x103c && | |
3309 | rdev->pdev->subsystem_device == 0x30a4) | |
3310 | return; | |
3311 | ||
302a8e8b AD |
3312 | /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume |
3313 | * - it hangs on resume inside the dynclk 1 table. | |
3314 | */ | |
3315 | if (rdev->family == CHIP_RS480 && | |
3316 | rdev->pdev->subsystem_vendor == 0x103c && | |
3317 | rdev->pdev->subsystem_device == 0x30ae) | |
3318 | return; | |
3319 | ||
771fe6b9 JG |
3320 | /* DYN CLK 1 */ |
3321 | table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); | |
3322 | if (table) | |
3323 | combios_parse_pll_table(dev, table); | |
3324 | ||
3325 | } | |
3326 | ||
3327 | void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) | |
3328 | { | |
3329 | struct radeon_device *rdev = dev->dev_private; | |
3330 | uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; | |
3331 | ||
3332 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); | |
3333 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); | |
3334 | bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); | |
3335 | ||
3336 | /* let the bios control the backlight */ | |
3337 | bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; | |
3338 | ||
3339 | /* tell the bios not to handle mode switching */ | |
3340 | bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | | |
3341 | RADEON_ACC_MODE_CHANGE); | |
3342 | ||
3343 | /* tell the bios a driver is loaded */ | |
3344 | bios_7_scratch |= RADEON_DRV_LOADED; | |
3345 | ||
3346 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); | |
3347 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
3348 | WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); | |
3349 | } | |
3350 | ||
3351 | void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) | |
3352 | { | |
3353 | struct drm_device *dev = encoder->dev; | |
3354 | struct radeon_device *rdev = dev->dev_private; | |
3355 | uint32_t bios_6_scratch; | |
3356 | ||
3357 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); | |
3358 | ||
3359 | if (lock) | |
3360 | bios_6_scratch |= RADEON_DRIVER_CRITICAL; | |
3361 | else | |
3362 | bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; | |
3363 | ||
3364 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
3365 | } | |
3366 | ||
3367 | void | |
3368 | radeon_combios_connected_scratch_regs(struct drm_connector *connector, | |
3369 | struct drm_encoder *encoder, | |
3370 | bool connected) | |
3371 | { | |
3372 | struct drm_device *dev = connector->dev; | |
3373 | struct radeon_device *rdev = dev->dev_private; | |
3374 | struct radeon_connector *radeon_connector = | |
3375 | to_radeon_connector(connector); | |
3376 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
3377 | uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); | |
3378 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); | |
3379 | ||
3380 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && | |
3381 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { | |
3382 | if (connected) { | |
d9fdaafb | 3383 | DRM_DEBUG_KMS("TV1 connected\n"); |
771fe6b9 JG |
3384 | /* fix me */ |
3385 | bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; | |
3386 | /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ | |
3387 | bios_5_scratch |= RADEON_TV1_ON; | |
3388 | bios_5_scratch |= RADEON_ACC_REQ_TV1; | |
3389 | } else { | |
d9fdaafb | 3390 | DRM_DEBUG_KMS("TV1 disconnected\n"); |
771fe6b9 JG |
3391 | bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; |
3392 | bios_5_scratch &= ~RADEON_TV1_ON; | |
3393 | bios_5_scratch &= ~RADEON_ACC_REQ_TV1; | |
3394 | } | |
3395 | } | |
3396 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && | |
3397 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { | |
3398 | if (connected) { | |
d9fdaafb | 3399 | DRM_DEBUG_KMS("LCD1 connected\n"); |
771fe6b9 JG |
3400 | bios_4_scratch |= RADEON_LCD1_ATTACHED; |
3401 | bios_5_scratch |= RADEON_LCD1_ON; | |
3402 | bios_5_scratch |= RADEON_ACC_REQ_LCD1; | |
3403 | } else { | |
d9fdaafb | 3404 | DRM_DEBUG_KMS("LCD1 disconnected\n"); |
771fe6b9 JG |
3405 | bios_4_scratch &= ~RADEON_LCD1_ATTACHED; |
3406 | bios_5_scratch &= ~RADEON_LCD1_ON; | |
3407 | bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; | |
3408 | } | |
3409 | } | |
3410 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && | |
3411 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { | |
3412 | if (connected) { | |
d9fdaafb | 3413 | DRM_DEBUG_KMS("CRT1 connected\n"); |
771fe6b9 JG |
3414 | bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; |
3415 | bios_5_scratch |= RADEON_CRT1_ON; | |
3416 | bios_5_scratch |= RADEON_ACC_REQ_CRT1; | |
3417 | } else { | |
d9fdaafb | 3418 | DRM_DEBUG_KMS("CRT1 disconnected\n"); |
771fe6b9 JG |
3419 | bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; |
3420 | bios_5_scratch &= ~RADEON_CRT1_ON; | |
3421 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; | |
3422 | } | |
3423 | } | |
3424 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && | |
3425 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { | |
3426 | if (connected) { | |
d9fdaafb | 3427 | DRM_DEBUG_KMS("CRT2 connected\n"); |
771fe6b9 JG |
3428 | bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; |
3429 | bios_5_scratch |= RADEON_CRT2_ON; | |
3430 | bios_5_scratch |= RADEON_ACC_REQ_CRT2; | |
3431 | } else { | |
d9fdaafb | 3432 | DRM_DEBUG_KMS("CRT2 disconnected\n"); |
771fe6b9 JG |
3433 | bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; |
3434 | bios_5_scratch &= ~RADEON_CRT2_ON; | |
3435 | bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; | |
3436 | } | |
3437 | } | |
3438 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && | |
3439 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { | |
3440 | if (connected) { | |
d9fdaafb | 3441 | DRM_DEBUG_KMS("DFP1 connected\n"); |
771fe6b9 JG |
3442 | bios_4_scratch |= RADEON_DFP1_ATTACHED; |
3443 | bios_5_scratch |= RADEON_DFP1_ON; | |
3444 | bios_5_scratch |= RADEON_ACC_REQ_DFP1; | |
3445 | } else { | |
d9fdaafb | 3446 | DRM_DEBUG_KMS("DFP1 disconnected\n"); |
771fe6b9 JG |
3447 | bios_4_scratch &= ~RADEON_DFP1_ATTACHED; |
3448 | bios_5_scratch &= ~RADEON_DFP1_ON; | |
3449 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; | |
3450 | } | |
3451 | } | |
3452 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && | |
3453 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { | |
3454 | if (connected) { | |
d9fdaafb | 3455 | DRM_DEBUG_KMS("DFP2 connected\n"); |
771fe6b9 JG |
3456 | bios_4_scratch |= RADEON_DFP2_ATTACHED; |
3457 | bios_5_scratch |= RADEON_DFP2_ON; | |
3458 | bios_5_scratch |= RADEON_ACC_REQ_DFP2; | |
3459 | } else { | |
d9fdaafb | 3460 | DRM_DEBUG_KMS("DFP2 disconnected\n"); |
771fe6b9 JG |
3461 | bios_4_scratch &= ~RADEON_DFP2_ATTACHED; |
3462 | bios_5_scratch &= ~RADEON_DFP2_ON; | |
3463 | bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; | |
3464 | } | |
3465 | } | |
3466 | WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); | |
3467 | WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); | |
3468 | } | |
3469 | ||
3470 | void | |
3471 | radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) | |
3472 | { | |
3473 | struct drm_device *dev = encoder->dev; | |
3474 | struct radeon_device *rdev = dev->dev_private; | |
3475 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
3476 | uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); | |
3477 | ||
3478 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
3479 | bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; | |
3480 | bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); | |
3481 | } | |
3482 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
3483 | bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; | |
3484 | bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); | |
3485 | } | |
3486 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
3487 | bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; | |
3488 | bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); | |
3489 | } | |
3490 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
3491 | bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; | |
3492 | bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); | |
3493 | } | |
3494 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { | |
3495 | bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; | |
3496 | bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); | |
3497 | } | |
3498 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { | |
3499 | bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; | |
3500 | bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); | |
3501 | } | |
3502 | WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); | |
3503 | } | |
3504 | ||
3505 | void | |
3506 | radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) | |
3507 | { | |
3508 | struct drm_device *dev = encoder->dev; | |
3509 | struct radeon_device *rdev = dev->dev_private; | |
3510 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
3511 | uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); | |
3512 | ||
3513 | if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { | |
3514 | if (on) | |
3515 | bios_6_scratch |= RADEON_TV_DPMS_ON; | |
3516 | else | |
3517 | bios_6_scratch &= ~RADEON_TV_DPMS_ON; | |
3518 | } | |
3519 | if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { | |
3520 | if (on) | |
3521 | bios_6_scratch |= RADEON_CRT_DPMS_ON; | |
3522 | else | |
3523 | bios_6_scratch &= ~RADEON_CRT_DPMS_ON; | |
3524 | } | |
3525 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
3526 | if (on) | |
3527 | bios_6_scratch |= RADEON_LCD_DPMS_ON; | |
3528 | else | |
3529 | bios_6_scratch &= ~RADEON_LCD_DPMS_ON; | |
3530 | } | |
3531 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | |
3532 | if (on) | |
3533 | bios_6_scratch |= RADEON_DFP_DPMS_ON; | |
3534 | else | |
3535 | bios_6_scratch &= ~RADEON_DFP_DPMS_ON; | |
3536 | } | |
3537 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
3538 | } |