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drm: really make debug levels match in edid failure code
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_clocks.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "radeon_drm.h"
30#include "radeon_reg.h"
31#include "radeon.h"
32#include "atom.h"
33
34/* 10 khz */
7433874e 35uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
771fe6b9
JG		 36{
37 struct radeon_pll *spll = &rdev->clock.spll;
38 uint32_t fb_div, ref_div, post_div, sclk;
39
40 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
41 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK;
42 fb_div <<= 1;
43 fb_div *= spll->reference_freq;
44
45 ref_div =
46 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
4b30b870
DA		 47
48 if (ref_div == 0)
49 return 0;
50
771fe6b9
JG		 51 sclk = fb_div / ref_div;
52
53 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
54 if (post_div == 2)
55 sclk >>= 1;
56 else if (post_div == 3)
57 sclk >>= 2;
58 else if (post_div == 4)
38678d35 59 sclk >>= 3;
771fe6b9
JG		 60
61 return sclk;
62}
63
64/* 10 khz */
5ea597f3 65uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
771fe6b9
JG		 66{
67 struct radeon_pll *mpll = &rdev->clock.mpll;
68 uint32_t fb_div, ref_div, post_div, mclk;
69
70 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
71 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK;
72 fb_div <<= 1;
73 fb_div *= mpll->reference_freq;
74
75 ref_div =
76 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
4b30b870
DA		 77
78 if (ref_div == 0)
79 return 0;
80
771fe6b9
JG		 81 mclk = fb_div / ref_div;
82
83 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
84 if (post_div == 2)
85 mclk >>= 1;
86 else if (post_div == 3)
87 mclk >>= 2;
88 else if (post_div == 4)
38678d35 89 mclk >>= 3;
771fe6b9
JG		 90
91 return mclk;
92}
93
7b044f40
BH		 94#ifdef CONFIG_OF
95/*
96 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
97 * tree. Hopefully, ATI OF driver is kind enough to fill these
98 */
99static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
100{
101 struct radeon_device *rdev = dev->dev_private;
102 struct device_node *dp = rdev->pdev->dev.of_node;
103 const u32 *val;
104 struct radeon_pll *p1pll = &rdev->clock.p1pll;
105 struct radeon_pll *p2pll = &rdev->clock.p2pll;
106 struct radeon_pll *spll = &rdev->clock.spll;
107 struct radeon_pll *mpll = &rdev->clock.mpll;
108
109 if (dp == NULL)
110 return false;
111 val = of_get_property(dp, "ATY,RefCLK", NULL);
112 if (!val || !*val) {
113 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
114 return false;
115 }
116 p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
117 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
118 if (p1pll->reference_div < 2)
119 p1pll->reference_div = 12;
b20f9bef 120 p2pll->reference_div = p1pll->reference_div;
7b044f40
BH		 121
122 /* These aren't in the device-tree */
123 if (rdev->family >= CHIP_R420) {
124 p1pll->pll_in_min = 100;
125 p1pll->pll_in_max = 1350;
126 p1pll->pll_out_min = 20000;
127 p1pll->pll_out_max = 50000;
128 p2pll->pll_in_min = 100;
129 p2pll->pll_in_max = 1350;
130 p2pll->pll_out_min = 20000;
131 p2pll->pll_out_max = 50000;
132 } else {
133 p1pll->pll_in_min = 40;
134 p1pll->pll_in_max = 500;
135 p1pll->pll_out_min = 12500;
136 p1pll->pll_out_max = 35000;
137 p2pll->pll_in_min = 40;
138 p2pll->pll_in_max = 500;
139 p2pll->pll_out_min = 12500;
140 p2pll->pll_out_max = 35000;
141 }
b20f9bef
AD		 142 /* not sure what the max should be in all cases */
143 rdev->clock.max_pixel_clock = 35000;
7b044f40
BH		 144
145 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
146 spll->reference_div = mpll->reference_div =
147 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
148 RADEON_M_SPLL_REF_DIV_MASK;
149
150 val = of_get_property(dp, "ATY,SCLK", NULL);
151 if (val && *val)
152 rdev->clock.default_sclk = (*val) / 10;
153 else
154 rdev->clock.default_sclk =
155 radeon_legacy_get_engine_clock(rdev);
b20f9bef 156
7b044f40
BH		 157 val = of_get_property(dp, "ATY,MCLK", NULL);
158 if (val && *val)
159 rdev->clock.default_mclk = (*val) / 10;
160 else
161 rdev->clock.default_mclk =
162 radeon_legacy_get_memory_clock(rdev);
163
164 DRM_INFO("Using device-tree clock info\n");
b20f9bef 165
7b044f40
BH		 166 return true;
167}
168#else
169static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
170{
171 return false;
172}
173#endif /* CONFIG_OF */
174
771fe6b9
JG		 175void radeon_get_clock_info(struct drm_device *dev)
176{
177 struct radeon_device *rdev = dev->dev_private;
178 struct radeon_pll *p1pll = &rdev->clock.p1pll;
179 struct radeon_pll *p2pll = &rdev->clock.p2pll;
bcc1c2a1 180 struct radeon_pll *dcpll = &rdev->clock.dcpll;
771fe6b9
JG		 181 struct radeon_pll *spll = &rdev->clock.spll;
182 struct radeon_pll *mpll = &rdev->clock.mpll;
183 int ret;
184
185 if (rdev->is_atom_bios)
186 ret = radeon_atom_get_clock_info(dev);
187 else
188 ret = radeon_combios_get_clock_info(dev);
7b044f40
BH		 189 if (!ret)
190 ret = radeon_read_clocks_OF(dev);
771fe6b9
JG		 191
192 if (ret) {
2a008d0c
AD		 193 if (p1pll->reference_div < 2) {
194 if (!ASIC_IS_AVIVO(rdev)) {
195 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
196 if (ASIC_IS_R300(rdev))
197 p1pll->reference_div =
198 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
199 else
200 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
201 if (p1pll->reference_div < 2)
202 p1pll->reference_div = 12;
203 } else
204 p1pll->reference_div = 12;
205 }
771fe6b9
JG		 206 if (p2pll->reference_div < 2)
207 p2pll->reference_div = 12;
3ce0a23d
JG		 208 if (rdev->family < CHIP_RS600) {
209 if (spll->reference_div < 2)
210 spll->reference_div =
211 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
212 RADEON_M_SPLL_REF_DIV_MASK;
213 }
771fe6b9
JG		 214 if (mpll->reference_div < 2)
215 mpll->reference_div = spll->reference_div;
216 } else {
217 if (ASIC_IS_AVIVO(rdev)) {
218 /* TODO FALLBACK */
219 } else {
220 DRM_INFO("Using generic clock info\n");
221
222 if (rdev->flags & RADEON_IS_IGP) {
223 p1pll->reference_freq = 1432;
224 p2pll->reference_freq = 1432;
225 spll->reference_freq = 1432;
226 mpll->reference_freq = 1432;
227 } else {
228 p1pll->reference_freq = 2700;
229 p2pll->reference_freq = 2700;
230 spll->reference_freq = 2700;
231 mpll->reference_freq = 2700;
232 }
233 p1pll->reference_div =
234 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
235 if (p1pll->reference_div < 2)
236 p1pll->reference_div = 12;
237 p2pll->reference_div = p1pll->reference_div;
238
239 if (rdev->family >= CHIP_R420) {
240 p1pll->pll_in_min = 100;
241 p1pll->pll_in_max = 1350;
242 p1pll->pll_out_min = 20000;
243 p1pll->pll_out_max = 50000;
244 p2pll->pll_in_min = 100;
245 p2pll->pll_in_max = 1350;
246 p2pll->pll_out_min = 20000;
247 p2pll->pll_out_max = 50000;
248 } else {
249 p1pll->pll_in_min = 40;
250 p1pll->pll_in_max = 500;
251 p1pll->pll_out_min = 12500;
252 p1pll->pll_out_max = 35000;
253 p2pll->pll_in_min = 40;
254 p2pll->pll_in_max = 500;
255 p2pll->pll_out_min = 12500;
256 p2pll->pll_out_max = 35000;
257 }
258
259 spll->reference_div =
260 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
261 RADEON_M_SPLL_REF_DIV_MASK;
262 mpll->reference_div = spll->reference_div;
263 rdev->clock.default_sclk =
264 radeon_legacy_get_engine_clock(rdev);
265 rdev->clock.default_mclk =
266 radeon_legacy_get_memory_clock(rdev);
267 }
268 }
269
270 /* pixel clocks */
271 if (ASIC_IS_AVIVO(rdev)) {
272 p1pll->min_post_div = 2;
273 p1pll->max_post_div = 0x7f;
274 p1pll->min_frac_feedback_div = 0;
275 p1pll->max_frac_feedback_div = 9;
276 p2pll->min_post_div = 2;
277 p2pll->max_post_div = 0x7f;
278 p2pll->min_frac_feedback_div = 0;
279 p2pll->max_frac_feedback_div = 9;
280 } else {
281 p1pll->min_post_div = 1;
282 p1pll->max_post_div = 16;
283 p1pll->min_frac_feedback_div = 0;
284 p1pll->max_frac_feedback_div = 0;
285 p2pll->min_post_div = 1;
286 p2pll->max_post_div = 12;
287 p2pll->min_frac_feedback_div = 0;
288 p2pll->max_frac_feedback_div = 0;
289 }
290
bcc1c2a1
AD		 291 /* dcpll is DCE4 only */
292 dcpll->min_post_div = 2;
293 dcpll->max_post_div = 0x7f;
294 dcpll->min_frac_feedback_div = 0;
295 dcpll->max_frac_feedback_div = 9;
296 dcpll->min_ref_div = 2;
297 dcpll->max_ref_div = 0x3ff;
298 dcpll->min_feedback_div = 4;
299 dcpll->max_feedback_div = 0xfff;
300 dcpll->best_vco = 0;
301
771fe6b9
JG		 302 p1pll->min_ref_div = 2;
303 p1pll->max_ref_div = 0x3ff;
304 p1pll->min_feedback_div = 4;
305 p1pll->max_feedback_div = 0x7ff;
306 p1pll->best_vco = 0;
307
308 p2pll->min_ref_div = 2;
309 p2pll->max_ref_div = 0x3ff;
310 p2pll->min_feedback_div = 4;
311 p2pll->max_feedback_div = 0x7ff;
312 p2pll->best_vco = 0;
313
314 /* system clock */
315 spll->min_post_div = 1;
316 spll->max_post_div = 1;
317 spll->min_ref_div = 2;
318 spll->max_ref_div = 0xff;
319 spll->min_feedback_div = 4;
320 spll->max_feedback_div = 0xff;
321 spll->best_vco = 0;
322
323 /* memory clock */
324 mpll->min_post_div = 1;
325 mpll->max_post_div = 1;
326 mpll->min_ref_div = 2;
327 mpll->max_ref_div = 0xff;
328 mpll->min_feedback_div = 4;
329 mpll->max_feedback_div = 0xff;
330 mpll->best_vco = 0;
331
8807286e
AD		 332 if (!rdev->clock.default_sclk)
333 rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
334 if ((!rdev->clock.default_mclk) && rdev->asic->get_memory_clock)
335 rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
336
337 rdev->pm.current_sclk = rdev->clock.default_sclk;
338 rdev->pm.current_mclk = rdev->clock.default_mclk;
339
771fe6b9
JG		 340}
341
342/* 10 khz */
343static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
344 uint32_t req_clock,
345 int *fb_div, int *post_div)
346{
347 struct radeon_pll *spll = &rdev->clock.spll;
348 int ref_div = spll->reference_div;
349
350 if (!ref_div)
351 ref_div =
352 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
353 RADEON_M_SPLL_REF_DIV_MASK;
354
355 if (req_clock < 15000) {
356 *post_div = 8;
357 req_clock *= 8;
358 } else if (req_clock < 30000) {
359 *post_div = 4;
360 req_clock *= 4;
361 } else if (req_clock < 60000) {
362 *post_div = 2;
363 req_clock *= 2;
364 } else
365 *post_div = 1;
366
367 req_clock *= ref_div;
368 req_clock += spll->reference_freq;
369 req_clock /= (2 * spll->reference_freq);
370
371 *fb_div = req_clock & 0xff;
372
373 req_clock = (req_clock & 0xffff) << 1;
374 req_clock *= spll->reference_freq;
375 req_clock /= ref_div;
376 req_clock /= *post_div;
377
378 return req_clock;
379}
380
381/* 10 khz */
382void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
383 uint32_t eng_clock)
384{
385 uint32_t tmp;
386 int fb_div, post_div;
387
388 /* XXX: wait for idle */
389
390 eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
391
392 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
393 tmp &= ~RADEON_DONT_USE_XTALIN;
394 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
395
396 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
397 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
398 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
399
400 udelay(10);
401
402 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
403 tmp |= RADEON_SPLL_SLEEP;
404 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
405
406 udelay(2);
407
408 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
409 tmp |= RADEON_SPLL_RESET;
410 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
411
412 udelay(200);
413
414 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
415 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
416 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
417 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
418
419 /* XXX: verify on different asics */
420 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
421 tmp &= ~RADEON_SPLL_PVG_MASK;
422 if ((eng_clock * post_div) >= 90000)
423 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
424 else
425 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
426 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
427
428 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
429 tmp &= ~RADEON_SPLL_SLEEP;
430 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
431
432 udelay(2);
433
434 tmp = RREG32_PLL(RADEON_SPLL_CNTL);
435 tmp &= ~RADEON_SPLL_RESET;
436 WREG32_PLL(RADEON_SPLL_CNTL, tmp);
437
438 udelay(200);
439
440 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
441 tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
442 switch (post_div) {
443 case 1:
444 default:
445 tmp |= 1;
446 break;
447 case 2:
448 tmp |= 2;
449 break;
450 case 4:
451 tmp |= 3;
452 break;
453 case 8:
454 tmp |= 4;
455 break;
456 }
457 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
458
459 udelay(20);
460
461 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
462 tmp |= RADEON_DONT_USE_XTALIN;
463 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
464
465 udelay(10);
466}
467
468void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
469{
470 uint32_t tmp;
471
472 if (enable) {
473 if (rdev->flags & RADEON_SINGLE_CRTC) {
474 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
475 if ((RREG32(RADEON_CONFIG_CNTL) &
476 RADEON_CFG_ATI_REV_ID_MASK) >
477 RADEON_CFG_ATI_REV_A13) {
478 tmp &=
479 ~(RADEON_SCLK_FORCE_CP |
480 RADEON_SCLK_FORCE_RB);
481 }
482 tmp &=
483 ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
484 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
485 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
486 RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
487 RADEON_SCLK_FORCE_TDM);
488 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
489 } else if (ASIC_IS_R300(rdev)) {
490 if ((rdev->family == CHIP_RS400) ||
491 (rdev->family == CHIP_RS480)) {
492 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
493 tmp &=
494 ~(RADEON_SCLK_FORCE_DISP2 |
495 RADEON_SCLK_FORCE_CP |
496 RADEON_SCLK_FORCE_HDP |
497 RADEON_SCLK_FORCE_DISP1 |
498 RADEON_SCLK_FORCE_TOP |
499 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
500 | RADEON_SCLK_FORCE_IDCT |
501 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
502 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
503 | R300_SCLK_FORCE_US |
504 RADEON_SCLK_FORCE_TV_SCLK |
505 R300_SCLK_FORCE_SU |
506 RADEON_SCLK_FORCE_OV0);
507 tmp |= RADEON_DYN_STOP_LAT_MASK;
508 tmp |=
509 RADEON_SCLK_FORCE_TOP |
510 RADEON_SCLK_FORCE_VIP;
511 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
512
513 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
514 tmp &= ~RADEON_SCLK_MORE_FORCEON;
515 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
516 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
517
518 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
519 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
520 RADEON_PIXCLK_DAC_ALWAYS_ONb);
521 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
522
523 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
524 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
525 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
526 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
527 R300_DVOCLK_ALWAYS_ONb |
528 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
529 RADEON_PIXCLK_GV_ALWAYS_ONb |
530 R300_PIXCLK_DVO_ALWAYS_ONb |
531 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
532 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
533 R300_PIXCLK_TRANS_ALWAYS_ONb |
534 R300_PIXCLK_TVO_ALWAYS_ONb |
535 R300_P2G2CLK_ALWAYS_ONb |
aa96e341 536 R300_P2G2CLK_DAC_ALWAYS_ONb);
771fe6b9
JG		 537 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
538 } else if (rdev->family >= CHIP_RV350) {
539 tmp = RREG32_PLL(R300_SCLK_CNTL2);
540 tmp &= ~(R300_SCLK_FORCE_TCL |
541 R300_SCLK_FORCE_GA |
542 R300_SCLK_FORCE_CBA);
543 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
544 R300_SCLK_GA_MAX_DYN_STOP_LAT |
545 R300_SCLK_CBA_MAX_DYN_STOP_LAT);
546 WREG32_PLL(R300_SCLK_CNTL2, tmp);
547
548 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
549 tmp &=
550 ~(RADEON_SCLK_FORCE_DISP2 |
551 RADEON_SCLK_FORCE_CP |
552 RADEON_SCLK_FORCE_HDP |
553 RADEON_SCLK_FORCE_DISP1 |
554 RADEON_SCLK_FORCE_TOP |
555 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
556 | RADEON_SCLK_FORCE_IDCT |
557 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
558 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
559 | R300_SCLK_FORCE_US |
560 RADEON_SCLK_FORCE_TV_SCLK |
561 R300_SCLK_FORCE_SU |
562 RADEON_SCLK_FORCE_OV0);
563 tmp |= RADEON_DYN_STOP_LAT_MASK;
564 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
565
566 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
567 tmp &= ~RADEON_SCLK_MORE_FORCEON;
568 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
569 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
570
571 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
572 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
573 RADEON_PIXCLK_DAC_ALWAYS_ONb);
574 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
575
576 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
577 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
578 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
579 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
580 R300_DVOCLK_ALWAYS_ONb |
581 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
582 RADEON_PIXCLK_GV_ALWAYS_ONb |
583 R300_PIXCLK_DVO_ALWAYS_ONb |
584 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
585 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
586 R300_PIXCLK_TRANS_ALWAYS_ONb |
587 R300_PIXCLK_TVO_ALWAYS_ONb |
588 R300_P2G2CLK_ALWAYS_ONb |
aa96e341 589 R300_P2G2CLK_DAC_ALWAYS_ONb);
771fe6b9
JG		 590 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
591
592 tmp = RREG32_PLL(RADEON_MCLK_MISC);
593 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
594 RADEON_IO_MCLK_DYN_ENABLE);
595 WREG32_PLL(RADEON_MCLK_MISC, tmp);
596
597 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
598 tmp |= (RADEON_FORCEON_MCLKA |
599 RADEON_FORCEON_MCLKB);
600
601 tmp &= ~(RADEON_FORCEON_YCLKA |
602 RADEON_FORCEON_YCLKB |
603 RADEON_FORCEON_MC);
604
605 /* Some releases of vbios have set DISABLE_MC_MCLKA
606 and DISABLE_MC_MCLKB bits in the vbios table. Setting these
607 bits will cause H/W hang when reading video memory with dynamic clocking
608 enabled. */
609 if ((tmp & R300_DISABLE_MC_MCLKA) &&
610 (tmp & R300_DISABLE_MC_MCLKB)) {
611 /* If both bits are set, then check the active channels */
612 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
613 if (rdev->mc.vram_width == 64) {
614 if (RREG32(RADEON_MEM_CNTL) &
615 R300_MEM_USE_CD_CH_ONLY)
616 tmp &=
617 ~R300_DISABLE_MC_MCLKB;
618 else
619 tmp &=
620 ~R300_DISABLE_MC_MCLKA;
621 } else {
622 tmp &= ~(R300_DISABLE_MC_MCLKA |
623 R300_DISABLE_MC_MCLKB);
624 }
625 }
626
627 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
628 } else {
629 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
630 tmp &= ~(R300_SCLK_FORCE_VAP);
631 tmp |= RADEON_SCLK_FORCE_CP;
632 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
633 udelay(15000);
634
635 tmp = RREG32_PLL(R300_SCLK_CNTL2);
636 tmp &= ~(R300_SCLK_FORCE_TCL |
637 R300_SCLK_FORCE_GA |
638 R300_SCLK_FORCE_CBA);
639 WREG32_PLL(R300_SCLK_CNTL2, tmp);
640 }
641 } else {
642 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
643
644 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
645 RADEON_DISP_DYN_STOP_LAT_MASK |
646 RADEON_DYN_STOP_MODE_MASK);
647
648 tmp |= (RADEON_ENGIN_DYNCLK_MODE |
649 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
650 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
651 udelay(15000);
652
653 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
654 tmp |= RADEON_SCLK_DYN_START_CNTL;
655 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
656 udelay(15000);
657
658 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
659 to lockup randomly, leave them as set by BIOS.
660 */
661 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
662 /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
663 tmp &= ~RADEON_SCLK_FORCEON_MASK;
664
665 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */
666 if (((rdev->family == CHIP_RV250) &&
667 ((RREG32(RADEON_CONFIG_CNTL) &
668 RADEON_CFG_ATI_REV_ID_MASK) <
669 RADEON_CFG_ATI_REV_A13))
670 || ((rdev->family == CHIP_RV100)
671 &&
672 ((RREG32(RADEON_CONFIG_CNTL) &
673 RADEON_CFG_ATI_REV_ID_MASK) <=
674 RADEON_CFG_ATI_REV_A13))) {
675 tmp |= RADEON_SCLK_FORCE_CP;
676 tmp |= RADEON_SCLK_FORCE_VIP;
677 }
678
679 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
680
681 if ((rdev->family == CHIP_RV200) ||
682 (rdev->family == CHIP_RV250) ||
683 (rdev->family == CHIP_RV280)) {
684 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
685 tmp &= ~RADEON_SCLK_MORE_FORCEON;
686
687 /* RV200::A11 A12 RV250::A11 A12 */
688 if (((rdev->family == CHIP_RV200) ||
689 (rdev->family == CHIP_RV250)) &&
690 ((RREG32(RADEON_CONFIG_CNTL) &
691 RADEON_CFG_ATI_REV_ID_MASK) <
692 RADEON_CFG_ATI_REV_A13)) {
693 tmp |= RADEON_SCLK_MORE_FORCEON;
694 }
695 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
696 udelay(15000);
697 }
698
699 /* RV200::A11 A12, RV250::A11 A12 */
700 if (((rdev->family == CHIP_RV200) ||
701 (rdev->family == CHIP_RV250)) &&
702 ((RREG32(RADEON_CONFIG_CNTL) &
703 RADEON_CFG_ATI_REV_ID_MASK) <
704 RADEON_CFG_ATI_REV_A13)) {
705 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
706 tmp |= RADEON_TCL_BYPASS_DISABLE;
707 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
708 }
709 udelay(15000);
710
711 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
712 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
713 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
714 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
715 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
716 RADEON_PIXCLK_GV_ALWAYS_ONb |
717 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
718 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
719 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
720
721 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
722 udelay(15000);
723
724 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
725 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
726 RADEON_PIXCLK_DAC_ALWAYS_ONb);
727
728 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
729 udelay(15000);
730 }
731 } else {
732 /* Turn everything OFF (ForceON to everything) */
733 if (rdev->flags & RADEON_SINGLE_CRTC) {
734 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
735 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
736 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP
737 | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
738 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
739 RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
740 RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
741 RADEON_SCLK_FORCE_RB);
742 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
743 } else if ((rdev->family == CHIP_RS400) ||
744 (rdev->family == CHIP_RS480)) {
745 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
746 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
747 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
748 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
749 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
750 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
751 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
752 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
753 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
754 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
755
756 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
757 tmp |= RADEON_SCLK_MORE_FORCEON;
758 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
759
760 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
761 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
762 RADEON_PIXCLK_DAC_ALWAYS_ONb |
763 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
764 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
765
766 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
767 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
768 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
769 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
770 R300_DVOCLK_ALWAYS_ONb |
771 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
772 RADEON_PIXCLK_GV_ALWAYS_ONb |
773 R300_PIXCLK_DVO_ALWAYS_ONb |
774 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
775 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
776 R300_PIXCLK_TRANS_ALWAYS_ONb |
777 R300_PIXCLK_TVO_ALWAYS_ONb |
778 R300_P2G2CLK_ALWAYS_ONb |
aa96e341 779 R300_P2G2CLK_DAC_ALWAYS_ONb |
771fe6b9
JG		 780 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
781 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
782 } else if (rdev->family >= CHIP_RV350) {
783 /* for RV350/M10, no delays are required. */
784 tmp = RREG32_PLL(R300_SCLK_CNTL2);
785 tmp |= (R300_SCLK_FORCE_TCL |
786 R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA);
787 WREG32_PLL(R300_SCLK_CNTL2, tmp);
788
789 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
790 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
791 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
792 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
793 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
794 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
795 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
796 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
797 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
798 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
799
800 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
801 tmp |= RADEON_SCLK_MORE_FORCEON;
802 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
803
804 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
805 tmp |= (RADEON_FORCEON_MCLKA |
806 RADEON_FORCEON_MCLKB |
807 RADEON_FORCEON_YCLKA |
808 RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC);
809 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
810
811 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
812 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
813 RADEON_PIXCLK_DAC_ALWAYS_ONb |
814 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
815 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
816
817 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
818 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
819 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
820 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
821 R300_DVOCLK_ALWAYS_ONb |
822 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
823 RADEON_PIXCLK_GV_ALWAYS_ONb |
824 R300_PIXCLK_DVO_ALWAYS_ONb |
825 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
826 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
827 R300_PIXCLK_TRANS_ALWAYS_ONb |
828 R300_PIXCLK_TVO_ALWAYS_ONb |
829 R300_P2G2CLK_ALWAYS_ONb |
aa96e341 830 R300_P2G2CLK_DAC_ALWAYS_ONb |
771fe6b9
JG		 831 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
832 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
833 } else {
834 tmp = RREG32_PLL(RADEON_SCLK_CNTL);
835 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
836 tmp |= RADEON_SCLK_FORCE_SE;
837
838 if (rdev->flags & RADEON_SINGLE_CRTC) {
839 tmp |= (RADEON_SCLK_FORCE_RB |
840 RADEON_SCLK_FORCE_TDM |
841 RADEON_SCLK_FORCE_TAM |
842 RADEON_SCLK_FORCE_PB |
843 RADEON_SCLK_FORCE_RE |
844 RADEON_SCLK_FORCE_VIP |
845 RADEON_SCLK_FORCE_IDCT |
846 RADEON_SCLK_FORCE_TOP |
847 RADEON_SCLK_FORCE_DISP1 |
848 RADEON_SCLK_FORCE_DISP2 |
849 RADEON_SCLK_FORCE_HDP);
850 } else if ((rdev->family == CHIP_R300) ||
851 (rdev->family == CHIP_R350)) {
852 tmp |= (RADEON_SCLK_FORCE_HDP |
853 RADEON_SCLK_FORCE_DISP1 |
854 RADEON_SCLK_FORCE_DISP2 |
855 RADEON_SCLK_FORCE_TOP |
856 RADEON_SCLK_FORCE_IDCT |
857 RADEON_SCLK_FORCE_VIP);
858 }
859 WREG32_PLL(RADEON_SCLK_CNTL, tmp);
860
861 udelay(16000);
862
863 if ((rdev->family == CHIP_R300) ||
864 (rdev->family == CHIP_R350)) {
865 tmp = RREG32_PLL(R300_SCLK_CNTL2);
866 tmp |= (R300_SCLK_FORCE_TCL |
867 R300_SCLK_FORCE_GA |
868 R300_SCLK_FORCE_CBA);
869 WREG32_PLL(R300_SCLK_CNTL2, tmp);
870 udelay(16000);
871 }
872
873 if (rdev->flags & RADEON_IS_IGP) {
874 tmp = RREG32_PLL(RADEON_MCLK_CNTL);
875 tmp &= ~(RADEON_FORCEON_MCLKA |
876 RADEON_FORCEON_YCLKA);
877 WREG32_PLL(RADEON_MCLK_CNTL, tmp);
878 udelay(16000);
879 }
880
881 if ((rdev->family == CHIP_RV200) ||
882 (rdev->family == CHIP_RV250) ||
883 (rdev->family == CHIP_RV280)) {
884 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
885 tmp |= RADEON_SCLK_MORE_FORCEON;
886 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
887 udelay(16000);
888 }
889
890 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
891 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
892 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
893 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
894 RADEON_PIXCLK_GV_ALWAYS_ONb |
895 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
896 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
897 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
898
899 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
900 udelay(16000);
901
902 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
903 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
904 RADEON_PIXCLK_DAC_ALWAYS_ONb);
905 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
906 }
907 }
908}
909
Linux 6.x block layer and io_uring tree(s)