Commit | Line | Data |
---|---|---|
771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
760285e7 | 28 | #include <drm/drmP.h> |
771fe6b9 JG |
29 | #include "radeon_reg.h" |
30 | #include "radeon.h" | |
31 | #include "atom.h" | |
32 | ||
5a0e3ad6 | 33 | #include <linux/slab.h> |
268ba0a9 | 34 | #include <linux/acpi.h> |
771fe6b9 JG |
35 | /* |
36 | * BIOS. | |
37 | */ | |
b442962a AD |
38 | |
39 | /* If you boot an IGP board with a discrete card as the primary, | |
40 | * the IGP rom is not accessible via the rom bar as the IGP rom is | |
41 | * part of the system bios. On boot, the system bios puts a | |
42 | * copy of the igp rom at the start of vram if a discrete card is | |
43 | * present. | |
44 | */ | |
45 | static bool igp_read_bios_from_vram(struct radeon_device *rdev) | |
46 | { | |
47 | uint8_t __iomem *bios; | |
48 | resource_size_t vram_base; | |
49 | resource_size_t size = 256 * 1024; /* ??? */ | |
50 | ||
8b5d8dec DA |
51 | if (!(rdev->flags & RADEON_IS_IGP)) |
52 | if (!radeon_card_posted(rdev)) | |
53 | return false; | |
54 | ||
b442962a | 55 | rdev->bios = NULL; |
01d73a69 | 56 | vram_base = pci_resource_start(rdev->pdev, 0); |
b442962a AD |
57 | bios = ioremap(vram_base, size); |
58 | if (!bios) { | |
b442962a AD |
59 | return false; |
60 | } | |
61 | ||
62 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { | |
63 | iounmap(bios); | |
b442962a AD |
64 | return false; |
65 | } | |
66 | rdev->bios = kmalloc(size, GFP_KERNEL); | |
67 | if (rdev->bios == NULL) { | |
68 | iounmap(bios); | |
b442962a AD |
69 | return false; |
70 | } | |
6a9ee8af | 71 | memcpy_fromio(rdev->bios, bios, size); |
b442962a AD |
72 | iounmap(bios); |
73 | return true; | |
74 | } | |
75 | ||
771fe6b9 JG |
76 | static bool radeon_read_bios(struct radeon_device *rdev) |
77 | { | |
f2c9e560 | 78 | uint8_t __iomem *bios, val1, val2; |
771fe6b9 JG |
79 | size_t size; |
80 | ||
81 | rdev->bios = NULL; | |
b442962a | 82 | /* XXX: some cards may return 0 for rom size? ddx has a workaround */ |
771fe6b9 JG |
83 | bios = pci_map_rom(rdev->pdev, &size); |
84 | if (!bios) { | |
85 | return false; | |
86 | } | |
87 | ||
f2c9e560 DM |
88 | val1 = readb(&bios[0]); |
89 | val2 = readb(&bios[1]); | |
90 | ||
91 | if (size == 0 || val1 != 0x55 || val2 != 0xaa) { | |
771fe6b9 JG |
92 | pci_unmap_rom(rdev->pdev, bios); |
93 | return false; | |
94 | } | |
f2c9e560 | 95 | rdev->bios = kzalloc(size, GFP_KERNEL); |
771fe6b9 JG |
96 | if (rdev->bios == NULL) { |
97 | pci_unmap_rom(rdev->pdev, bios); | |
98 | return false; | |
99 | } | |
f2c9e560 | 100 | memcpy_fromio(rdev->bios, bios, size); |
771fe6b9 JG |
101 | pci_unmap_rom(rdev->pdev, bios); |
102 | return true; | |
103 | } | |
104 | ||
06a08570 MG |
105 | static bool radeon_read_platform_bios(struct radeon_device *rdev) |
106 | { | |
107 | uint8_t __iomem *bios; | |
108 | size_t size; | |
109 | ||
110 | rdev->bios = NULL; | |
111 | ||
112 | bios = pci_platform_rom(rdev->pdev, &size); | |
113 | if (!bios) { | |
114 | return false; | |
115 | } | |
116 | ||
117 | if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { | |
118 | return false; | |
119 | } | |
120 | rdev->bios = kmemdup(bios, size, GFP_KERNEL); | |
121 | if (rdev->bios == NULL) { | |
122 | return false; | |
123 | } | |
124 | ||
125 | return true; | |
126 | } | |
127 | ||
c61e2775 | 128 | #ifdef CONFIG_ACPI |
6a9ee8af DA |
129 | /* ATRM is used to get the BIOS on the discrete cards in |
130 | * dual-gpu systems. | |
131 | */ | |
c61e2775 AD |
132 | /* retrieve the ROM in 4k blocks */ |
133 | #define ATRM_BIOS_PAGE 4096 | |
134 | /** | |
135 | * radeon_atrm_call - fetch a chunk of the vbios | |
136 | * | |
137 | * @atrm_handle: acpi ATRM handle | |
138 | * @bios: vbios image pointer | |
139 | * @offset: offset of vbios image data to fetch | |
140 | * @len: length of vbios image data to fetch | |
141 | * | |
142 | * Executes ATRM to fetch a chunk of the discrete | |
143 | * vbios image on PX systems (all asics). | |
144 | * Returns the length of the buffer fetched. | |
145 | */ | |
146 | static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, | |
147 | int offset, int len) | |
148 | { | |
149 | acpi_status status; | |
150 | union acpi_object atrm_arg_elements[2], *obj; | |
151 | struct acpi_object_list atrm_arg; | |
152 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; | |
153 | ||
154 | atrm_arg.count = 2; | |
155 | atrm_arg.pointer = &atrm_arg_elements[0]; | |
156 | ||
157 | atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; | |
158 | atrm_arg_elements[0].integer.value = offset; | |
159 | ||
160 | atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; | |
161 | atrm_arg_elements[1].integer.value = len; | |
162 | ||
163 | status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); | |
164 | if (ACPI_FAILURE(status)) { | |
165 | printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); | |
166 | return -ENODEV; | |
167 | } | |
168 | ||
169 | obj = (union acpi_object *)buffer.pointer; | |
170 | memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); | |
171 | len = obj->buffer.length; | |
172 | kfree(buffer.pointer); | |
173 | return len; | |
174 | } | |
175 | ||
6a9ee8af DA |
176 | static bool radeon_atrm_get_bios(struct radeon_device *rdev) |
177 | { | |
178 | int ret; | |
b271a988 | 179 | int size = 256 * 1024; |
6a9ee8af | 180 | int i; |
c61e2775 AD |
181 | struct pci_dev *pdev = NULL; |
182 | acpi_handle dhandle, atrm_handle; | |
183 | acpi_status status; | |
184 | bool found = false; | |
185 | ||
186 | /* ATRM is for the discrete card only */ | |
187 | if (rdev->flags & RADEON_IS_IGP) | |
188 | return false; | |
189 | ||
190 | while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { | |
3a83f992 | 191 | dhandle = ACPI_HANDLE(&pdev->dev); |
c61e2775 AD |
192 | if (!dhandle) |
193 | continue; | |
6a9ee8af | 194 | |
c61e2775 AD |
195 | status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); |
196 | if (!ACPI_FAILURE(status)) { | |
197 | found = true; | |
198 | break; | |
199 | } | |
200 | } | |
201 | ||
d8ade352 AD |
202 | if (!found) { |
203 | while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { | |
204 | dhandle = ACPI_HANDLE(&pdev->dev); | |
205 | if (!dhandle) | |
206 | continue; | |
207 | ||
208 | status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); | |
209 | if (!ACPI_FAILURE(status)) { | |
210 | found = true; | |
211 | break; | |
212 | } | |
213 | } | |
214 | } | |
215 | ||
c61e2775 | 216 | if (!found) |
6a9ee8af DA |
217 | return false; |
218 | ||
219 | rdev->bios = kmalloc(size, GFP_KERNEL); | |
220 | if (!rdev->bios) { | |
221 | DRM_ERROR("Unable to allocate bios\n"); | |
222 | return false; | |
223 | } | |
224 | ||
225 | for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { | |
c61e2775 AD |
226 | ret = radeon_atrm_call(atrm_handle, |
227 | rdev->bios, | |
228 | (i * ATRM_BIOS_PAGE), | |
229 | ATRM_BIOS_PAGE); | |
211fa4fc | 230 | if (ret < ATRM_BIOS_PAGE) |
6a9ee8af DA |
231 | break; |
232 | } | |
233 | ||
234 | if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { | |
235 | kfree(rdev->bios); | |
236 | return false; | |
237 | } | |
238 | return true; | |
239 | } | |
c61e2775 AD |
240 | #else |
241 | static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) | |
242 | { | |
243 | return false; | |
244 | } | |
245 | #endif | |
0ec80d64 | 246 | |
c901bcdd AD |
247 | static bool ni_read_disabled_bios(struct radeon_device *rdev) |
248 | { | |
249 | u32 bus_cntl; | |
250 | u32 d1vga_control; | |
251 | u32 d2vga_control; | |
252 | u32 vga_render_control; | |
253 | u32 rom_cntl; | |
254 | bool r; | |
255 | ||
256 | bus_cntl = RREG32(R600_BUS_CNTL); | |
257 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); | |
258 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
259 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
260 | rom_cntl = RREG32(R600_ROM_CNTL); | |
261 | ||
262 | /* enable the rom */ | |
263 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); | |
5153550a AD |
264 | if (!ASIC_IS_NODCE(rdev)) { |
265 | /* Disable VGA mode */ | |
266 | WREG32(AVIVO_D1VGA_CONTROL, | |
267 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
268 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
269 | WREG32(AVIVO_D2VGA_CONTROL, | |
270 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
271 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
272 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
273 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
274 | } | |
c901bcdd AD |
275 | WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); |
276 | ||
277 | r = radeon_read_bios(rdev); | |
278 | ||
279 | /* restore regs */ | |
280 | WREG32(R600_BUS_CNTL, bus_cntl); | |
5153550a AD |
281 | if (!ASIC_IS_NODCE(rdev)) { |
282 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); | |
283 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
284 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
285 | } | |
c901bcdd AD |
286 | WREG32(R600_ROM_CNTL, rom_cntl); |
287 | return r; | |
288 | } | |
289 | ||
771fe6b9 JG |
290 | static bool r700_read_disabled_bios(struct radeon_device *rdev) |
291 | { | |
292 | uint32_t viph_control; | |
293 | uint32_t bus_cntl; | |
294 | uint32_t d1vga_control; | |
295 | uint32_t d2vga_control; | |
296 | uint32_t vga_render_control; | |
297 | uint32_t rom_cntl; | |
298 | uint32_t cg_spll_func_cntl = 0; | |
299 | uint32_t cg_spll_status; | |
300 | bool r; | |
301 | ||
302 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
0ec80d64 | 303 | bus_cntl = RREG32(R600_BUS_CNTL); |
771fe6b9 JG |
304 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
305 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
306 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
307 | rom_cntl = RREG32(R600_ROM_CNTL); | |
308 | ||
309 | /* disable VIP */ | |
310 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
311 | /* enable the rom */ | |
0ec80d64 | 312 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
771fe6b9 JG |
313 | /* Disable VGA mode */ |
314 | WREG32(AVIVO_D1VGA_CONTROL, | |
315 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
316 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
317 | WREG32(AVIVO_D2VGA_CONTROL, | |
318 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
319 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
320 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
321 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
322 | ||
323 | if (rdev->family == CHIP_RV730) { | |
324 | cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); | |
325 | ||
326 | /* enable bypass mode */ | |
327 | WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | | |
328 | R600_SPLL_BYPASS_EN)); | |
329 | ||
330 | /* wait for SPLL_CHG_STATUS to change to 1 */ | |
331 | cg_spll_status = 0; | |
332 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) | |
333 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); | |
334 | ||
335 | WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); | |
336 | } else | |
337 | WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); | |
338 | ||
339 | r = radeon_read_bios(rdev); | |
340 | ||
341 | /* restore regs */ | |
342 | if (rdev->family == CHIP_RV730) { | |
343 | WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); | |
344 | ||
345 | /* wait for SPLL_CHG_STATUS to change to 1 */ | |
346 | cg_spll_status = 0; | |
347 | while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) | |
348 | cg_spll_status = RREG32(R600_CG_SPLL_STATUS); | |
349 | } | |
350 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
0ec80d64 | 351 | WREG32(R600_BUS_CNTL, bus_cntl); |
771fe6b9 JG |
352 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
353 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
354 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
355 | WREG32(R600_ROM_CNTL, rom_cntl); | |
356 | return r; | |
357 | } | |
358 | ||
359 | static bool r600_read_disabled_bios(struct radeon_device *rdev) | |
360 | { | |
361 | uint32_t viph_control; | |
362 | uint32_t bus_cntl; | |
363 | uint32_t d1vga_control; | |
364 | uint32_t d2vga_control; | |
365 | uint32_t vga_render_control; | |
366 | uint32_t rom_cntl; | |
367 | uint32_t general_pwrmgt; | |
368 | uint32_t low_vid_lower_gpio_cntl; | |
369 | uint32_t medium_vid_lower_gpio_cntl; | |
370 | uint32_t high_vid_lower_gpio_cntl; | |
371 | uint32_t ctxsw_vid_lower_gpio_cntl; | |
372 | uint32_t lower_gpio_enable; | |
373 | bool r; | |
374 | ||
375 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
0ec80d64 | 376 | bus_cntl = RREG32(R600_BUS_CNTL); |
771fe6b9 JG |
377 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
378 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
379 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
380 | rom_cntl = RREG32(R600_ROM_CNTL); | |
381 | general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); | |
382 | low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); | |
383 | medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); | |
384 | high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); | |
385 | ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); | |
386 | lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); | |
387 | ||
388 | /* disable VIP */ | |
389 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
390 | /* enable the rom */ | |
0ec80d64 | 391 | WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); |
771fe6b9 JG |
392 | /* Disable VGA mode */ |
393 | WREG32(AVIVO_D1VGA_CONTROL, | |
394 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
395 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
396 | WREG32(AVIVO_D2VGA_CONTROL, | |
397 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
398 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
399 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
400 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
401 | ||
402 | WREG32(R600_ROM_CNTL, | |
403 | ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | | |
404 | (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | | |
405 | R600_SCK_OVERWRITE)); | |
406 | ||
407 | WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); | |
408 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, | |
409 | (low_vid_lower_gpio_cntl & ~0x400)); | |
410 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, | |
411 | (medium_vid_lower_gpio_cntl & ~0x400)); | |
412 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, | |
413 | (high_vid_lower_gpio_cntl & ~0x400)); | |
414 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, | |
415 | (ctxsw_vid_lower_gpio_cntl & ~0x400)); | |
416 | WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); | |
417 | ||
418 | r = radeon_read_bios(rdev); | |
419 | ||
420 | /* restore regs */ | |
421 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
0ec80d64 | 422 | WREG32(R600_BUS_CNTL, bus_cntl); |
771fe6b9 JG |
423 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
424 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
425 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
426 | WREG32(R600_ROM_CNTL, rom_cntl); | |
427 | WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); | |
428 | WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); | |
429 | WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); | |
430 | WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); | |
431 | WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); | |
432 | WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); | |
433 | return r; | |
434 | } | |
435 | ||
436 | static bool avivo_read_disabled_bios(struct radeon_device *rdev) | |
437 | { | |
438 | uint32_t seprom_cntl1; | |
439 | uint32_t viph_control; | |
440 | uint32_t bus_cntl; | |
441 | uint32_t d1vga_control; | |
442 | uint32_t d2vga_control; | |
443 | uint32_t vga_render_control; | |
444 | uint32_t gpiopad_a; | |
445 | uint32_t gpiopad_en; | |
446 | uint32_t gpiopad_mask; | |
447 | bool r; | |
448 | ||
449 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); | |
450 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
4171424e | 451 | bus_cntl = RREG32(RV370_BUS_CNTL); |
771fe6b9 JG |
452 | d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
453 | d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); | |
454 | vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); | |
455 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); | |
456 | gpiopad_en = RREG32(RADEON_GPIOPAD_EN); | |
457 | gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); | |
458 | ||
459 | WREG32(RADEON_SEPROM_CNTL1, | |
460 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | | |
461 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); | |
462 | WREG32(RADEON_GPIOPAD_A, 0); | |
463 | WREG32(RADEON_GPIOPAD_EN, 0); | |
464 | WREG32(RADEON_GPIOPAD_MASK, 0); | |
465 | ||
466 | /* disable VIP */ | |
467 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
468 | ||
469 | /* enable the rom */ | |
4171424e | 470 | WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); |
771fe6b9 JG |
471 | |
472 | /* Disable VGA mode */ | |
473 | WREG32(AVIVO_D1VGA_CONTROL, | |
474 | (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
475 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
476 | WREG32(AVIVO_D2VGA_CONTROL, | |
477 | (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | | |
478 | AVIVO_DVGA_CONTROL_TIMING_SELECT))); | |
479 | WREG32(AVIVO_VGA_RENDER_CONTROL, | |
480 | (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); | |
481 | ||
482 | r = radeon_read_bios(rdev); | |
483 | ||
484 | /* restore regs */ | |
485 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); | |
486 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
4171424e | 487 | WREG32(RV370_BUS_CNTL, bus_cntl); |
771fe6b9 JG |
488 | WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
489 | WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); | |
490 | WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); | |
491 | WREG32(RADEON_GPIOPAD_A, gpiopad_a); | |
492 | WREG32(RADEON_GPIOPAD_EN, gpiopad_en); | |
493 | WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); | |
494 | return r; | |
495 | } | |
496 | ||
497 | static bool legacy_read_disabled_bios(struct radeon_device *rdev) | |
498 | { | |
499 | uint32_t seprom_cntl1; | |
500 | uint32_t viph_control; | |
501 | uint32_t bus_cntl; | |
502 | uint32_t crtc_gen_cntl; | |
503 | uint32_t crtc2_gen_cntl; | |
504 | uint32_t crtc_ext_cntl; | |
505 | uint32_t fp2_gen_cntl; | |
506 | bool r; | |
507 | ||
508 | seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); | |
509 | viph_control = RREG32(RADEON_VIPH_CONTROL); | |
4171424e AD |
510 | if (rdev->flags & RADEON_IS_PCIE) |
511 | bus_cntl = RREG32(RV370_BUS_CNTL); | |
512 | else | |
513 | bus_cntl = RREG32(RADEON_BUS_CNTL); | |
771fe6b9 JG |
514 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
515 | crtc2_gen_cntl = 0; | |
516 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); | |
517 | fp2_gen_cntl = 0; | |
518 | ||
ffbab09b | 519 | if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
771fe6b9 JG |
520 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
521 | } | |
522 | ||
523 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
524 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); | |
525 | } | |
526 | ||
527 | WREG32(RADEON_SEPROM_CNTL1, | |
528 | ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | | |
529 | (0xc << RADEON_SCK_PRESCALE_SHIFT))); | |
530 | ||
531 | /* disable VIP */ | |
532 | WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); | |
533 | ||
534 | /* enable the rom */ | |
4171424e AD |
535 | if (rdev->flags & RADEON_IS_PCIE) |
536 | WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); | |
537 | else | |
538 | WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); | |
771fe6b9 JG |
539 | |
540 | /* Turn off mem requests and CRTC for both controllers */ | |
541 | WREG32(RADEON_CRTC_GEN_CNTL, | |
542 | ((crtc_gen_cntl & ~RADEON_CRTC_EN) | | |
543 | (RADEON_CRTC_DISP_REQ_EN_B | | |
544 | RADEON_CRTC_EXT_DISP_EN))); | |
545 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
546 | WREG32(RADEON_CRTC2_GEN_CNTL, | |
547 | ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | | |
548 | RADEON_CRTC2_DISP_REQ_EN_B)); | |
549 | } | |
550 | /* Turn off CRTC */ | |
551 | WREG32(RADEON_CRTC_EXT_CNTL, | |
552 | ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | | |
553 | (RADEON_CRTC_SYNC_TRISTAT | | |
554 | RADEON_CRTC_DISPLAY_DIS))); | |
555 | ||
ffbab09b | 556 | if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
771fe6b9 JG |
557 | WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); |
558 | } | |
559 | ||
560 | r = radeon_read_bios(rdev); | |
561 | ||
562 | /* restore regs */ | |
563 | WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); | |
564 | WREG32(RADEON_VIPH_CONTROL, viph_control); | |
4171424e AD |
565 | if (rdev->flags & RADEON_IS_PCIE) |
566 | WREG32(RV370_BUS_CNTL, bus_cntl); | |
567 | else | |
568 | WREG32(RADEON_BUS_CNTL, bus_cntl); | |
771fe6b9 JG |
569 | WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
570 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
571 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); | |
572 | } | |
573 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); | |
ffbab09b | 574 | if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
771fe6b9 JG |
575 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
576 | } | |
577 | return r; | |
578 | } | |
579 | ||
580 | static bool radeon_read_disabled_bios(struct radeon_device *rdev) | |
581 | { | |
b442962a AD |
582 | if (rdev->flags & RADEON_IS_IGP) |
583 | return igp_read_bios_from_vram(rdev); | |
c901bcdd AD |
584 | else if (rdev->family >= CHIP_BARTS) |
585 | return ni_read_disabled_bios(rdev); | |
b442962a | 586 | else if (rdev->family >= CHIP_RV770) |
771fe6b9 JG |
587 | return r700_read_disabled_bios(rdev); |
588 | else if (rdev->family >= CHIP_R600) | |
589 | return r600_read_disabled_bios(rdev); | |
590 | else if (rdev->family >= CHIP_RS600) | |
591 | return avivo_read_disabled_bios(rdev); | |
592 | else | |
593 | return legacy_read_disabled_bios(rdev); | |
594 | } | |
595 | ||
268ba0a9 DL |
596 | #ifdef CONFIG_ACPI |
597 | static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) | |
598 | { | |
599 | bool ret = false; | |
600 | struct acpi_table_header *hdr; | |
7c3906d0 | 601 | acpi_size tbl_size; |
268ba0a9 DL |
602 | UEFI_ACPI_VFCT *vfct; |
603 | GOP_VBIOS_CONTENT *vbios; | |
604 | VFCT_IMAGE_HEADER *vhdr; | |
605 | ||
7c3906d0 | 606 | if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) |
268ba0a9 DL |
607 | return false; |
608 | if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { | |
609 | DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); | |
610 | goto out_unmap; | |
611 | } | |
612 | ||
613 | vfct = (UEFI_ACPI_VFCT *)hdr; | |
614 | if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { | |
615 | DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); | |
616 | goto out_unmap; | |
617 | } | |
618 | ||
619 | vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); | |
620 | vhdr = &vbios->VbiosHeader; | |
621 | DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", | |
622 | vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, | |
623 | vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); | |
624 | ||
625 | if (vhdr->PCIBus != rdev->pdev->bus->number || | |
626 | vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || | |
627 | vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || | |
628 | vhdr->VendorID != rdev->pdev->vendor || | |
629 | vhdr->DeviceID != rdev->pdev->device) { | |
630 | DRM_INFO("ACPI VFCT table is not for this card\n"); | |
631 | goto out_unmap; | |
10d9b4ed | 632 | } |
268ba0a9 DL |
633 | |
634 | if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { | |
635 | DRM_ERROR("ACPI VFCT image truncated\n"); | |
636 | goto out_unmap; | |
637 | } | |
638 | ||
639 | rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); | |
640 | ret = !!rdev->bios; | |
641 | ||
642 | out_unmap: | |
268ba0a9 DL |
643 | return ret; |
644 | } | |
645 | #else | |
646 | static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) | |
647 | { | |
648 | return false; | |
649 | } | |
650 | #endif | |
6a9ee8af | 651 | |
771fe6b9 JG |
652 | bool radeon_get_bios(struct radeon_device *rdev) |
653 | { | |
654 | bool r; | |
655 | uint16_t tmp; | |
656 | ||
6a9ee8af | 657 | r = radeon_atrm_get_bios(rdev); |
268ba0a9 DL |
658 | if (r == false) |
659 | r = radeon_acpi_vfct_bios(rdev); | |
6a9ee8af | 660 | if (r == false) |
b442962a | 661 | r = igp_read_bios_from_vram(rdev); |
6a9ee8af | 662 | if (r == false) |
b442962a | 663 | r = radeon_read_bios(rdev); |
c9cb57fe | 664 | if (r == false) |
771fe6b9 | 665 | r = radeon_read_disabled_bios(rdev); |
c9cb57fe | 666 | if (r == false) |
06a08570 | 667 | r = radeon_read_platform_bios(rdev); |
771fe6b9 JG |
668 | if (r == false || rdev->bios == NULL) { |
669 | DRM_ERROR("Unable to locate a BIOS ROM\n"); | |
670 | rdev->bios = NULL; | |
671 | return false; | |
672 | } | |
673 | if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { | |
6a9ee8af | 674 | printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); |
771fe6b9 JG |
675 | goto free_bios; |
676 | } | |
677 | ||
e3439895 DA |
678 | tmp = RBIOS16(0x18); |
679 | if (RBIOS8(tmp + 0x14) != 0x0) { | |
680 | DRM_INFO("Not an x86 BIOS ROM, not using.\n"); | |
681 | goto free_bios; | |
682 | } | |
683 | ||
771fe6b9 JG |
684 | rdev->bios_header_start = RBIOS16(0x48); |
685 | if (!rdev->bios_header_start) { | |
686 | goto free_bios; | |
687 | } | |
688 | tmp = rdev->bios_header_start + 4; | |
689 | if (!memcmp(rdev->bios + tmp, "ATOM", 4) || | |
690 | !memcmp(rdev->bios + tmp, "MOTA", 4)) { | |
691 | rdev->is_atom_bios = true; | |
692 | } else { | |
693 | rdev->is_atom_bios = false; | |
694 | } | |
695 | ||
696 | DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); | |
697 | return true; | |
698 | free_bios: | |
699 | kfree(rdev->bios); | |
700 | rdev->bios = NULL; | |
701 | return false; | |
702 | } |