[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_benchmark.c

/*
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Jerome Glisse
 */
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
#include "radeon_reg.h"
#include "radeon.h"

#define RADEON_BENCHMARK_COPY_BLIT 1
#define RADEON_BENCHMARK_COPY_DMA  0

#define RADEON_BENCHMARK_ITERATIONS 1024
#define RADEON_BENCHMARK_COMMON_MODES_N 17

static int radeon_benchmark_do_move(struct radeon_device *rdev, unsigned size,
				    uint64_t saddr, uint64_t daddr,
				    int flag, int n,
				    struct reservation_object *resv)
{
	unsigned long start_jiffies;
	unsigned long end_jiffies;
	struct radeon_fence *fence = NULL;
	int i, r;

	start_jiffies = jiffies;
	for (i = 0; i < n; i++) {
		switch (flag) {
		case RADEON_BENCHMARK_COPY_DMA:
			fence = radeon_copy_dma(rdev, saddr, daddr,
						size / RADEON_GPU_PAGE_SIZE,
						resv);
			break;
		case RADEON_BENCHMARK_COPY_BLIT:
			fence = radeon_copy_blit(rdev, saddr, daddr,
						 size / RADEON_GPU_PAGE_SIZE,
						 resv);
			break;
		default:
			DRM_ERROR("Unknown copy method\n");
			return -EINVAL;
		}
		if (IS_ERR(fence))
			return PTR_ERR(fence);

		r = radeon_fence_wait(fence, false);
		radeon_fence_unref(&fence);
		if (r)
			return r;
	}
	end_jiffies = jiffies;
	return jiffies_to_msecs(end_jiffies - start_jiffies);
}


static void radeon_benchmark_log_results(int n, unsigned size,
					 unsigned int time,
					 unsigned sdomain, unsigned ddomain,
					 char *kind)
{
	unsigned int throughput = (n * (size >> 10)) / time;
	DRM_INFO("radeon: %s %u bo moves of %u kB from"
		 " %d to %d in %u ms, throughput: %u Mb/s or %u MB/s\n",
		 kind, n, size >> 10, sdomain, ddomain, time,
		 throughput * 8, throughput);
}

static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size,
				  unsigned sdomain, unsigned ddomain)
{
	struct radeon_bo *dobj = NULL;
	struct radeon_bo *sobj = NULL;
	uint64_t saddr, daddr;
	int r, n;
	int time;

	n = RADEON_BENCHMARK_ITERATIONS;
	r = radeon_bo_create(rdev, size, PAGE_SIZE, true, sdomain, 0, NULL, NULL, &sobj);
	if (r) {
		goto out_cleanup;
	}
	r = radeon_bo_reserve(sobj, false);
	if (unlikely(r != 0))
		goto out_cleanup;
	r = radeon_bo_pin(sobj, sdomain, &saddr);
	radeon_bo_unreserve(sobj);
	if (r) {
		goto out_cleanup;
	}
	r = radeon_bo_create(rdev, size, PAGE_SIZE, true, ddomain, 0, NULL, NULL, &dobj);
	if (r) {
		goto out_cleanup;
	}
	r = radeon_bo_reserve(dobj, false);
	if (unlikely(r != 0))
		goto out_cleanup;
	r = radeon_bo_pin(dobj, ddomain, &daddr);
	radeon_bo_unreserve(dobj);
	if (r) {
		goto out_cleanup;
	}

	if (rdev->asic->copy.dma) {
		time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
						RADEON_BENCHMARK_COPY_DMA, n,
						dobj->tbo.resv);
		if (time < 0)
			goto out_cleanup;
		if (time > 0)
			radeon_benchmark_log_results(n, size, time,
						     sdomain, ddomain, "dma");
	}

	if (rdev->asic->copy.blit) {
		time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
						RADEON_BENCHMARK_COPY_BLIT, n,
						dobj->tbo.resv);
		if (time < 0)
			goto out_cleanup;
		if (time > 0)
			radeon_benchmark_log_results(n, size, time,
						     sdomain, ddomain, "blit");
	}

out_cleanup:
	if (sobj) {
		r = radeon_bo_reserve(sobj, false);
		if (likely(r == 0)) {
			radeon_bo_unpin(sobj);
			radeon_bo_unreserve(sobj);
		}
		radeon_bo_unref(&sobj);
	}
	if (dobj) {
		r = radeon_bo_reserve(dobj, false);
		if (likely(r == 0)) {
			radeon_bo_unpin(dobj);
			radeon_bo_unreserve(dobj);
		}
		radeon_bo_unref(&dobj);
	}

	if (r) {
		DRM_ERROR("Error while benchmarking BO move.\n");
	}
}

void radeon_benchmark(struct radeon_device *rdev, int test_number)
{
	int i;
	int common_modes[RADEON_BENCHMARK_COMMON_MODES_N] = {
		640 * 480 * 4,
		720 * 480 * 4,
		800 * 600 * 4,
		848 * 480 * 4,
		1024 * 768 * 4,
		1152 * 768 * 4,
		1280 * 720 * 4,
		1280 * 800 * 4,
		1280 * 854 * 4,
		1280 * 960 * 4,
		1280 * 1024 * 4,
		1440 * 900 * 4,
		1400 * 1050 * 4,
		1680 * 1050 * 4,
		1600 * 1200 * 4,
		1920 * 1080 * 4,
		1920 * 1200 * 4
	};

	switch (test_number) {
	case 1:
		/* simple test, VRAM to GTT and GTT to VRAM */
		radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_GTT,
				      RADEON_GEM_DOMAIN_VRAM);
		radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_VRAM,
				      RADEON_GEM_DOMAIN_GTT);
		break;
	case 2:
		/* simple test, VRAM to VRAM */
		radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_VRAM,
				      RADEON_GEM_DOMAIN_VRAM);
		break;
	case 3:
		/* GTT to VRAM, buffer size sweep, powers of 2 */
		for (i = 1; i <= 16384; i <<= 1)
			radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
					      RADEON_GEM_DOMAIN_GTT,
					      RADEON_GEM_DOMAIN_VRAM);
		break;
	case 4:
		/* VRAM to GTT, buffer size sweep, powers of 2 */
		for (i = 1; i <= 16384; i <<= 1)
			radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
					      RADEON_GEM_DOMAIN_VRAM,
					      RADEON_GEM_DOMAIN_GTT);
		break;
	case 5:
		/* VRAM to VRAM, buffer size sweep, powers of 2 */
		for (i = 1; i <= 16384; i <<= 1)
			radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
					      RADEON_GEM_DOMAIN_VRAM,
					      RADEON_GEM_DOMAIN_VRAM);
		break;
	case 6:
		/* GTT to VRAM, buffer size sweep, common modes */
		for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
			radeon_benchmark_move(rdev, common_modes[i],
					      RADEON_GEM_DOMAIN_GTT,
					      RADEON_GEM_DOMAIN_VRAM);
		break;
	case 7:
		/* VRAM to GTT, buffer size sweep, common modes */
		for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
			radeon_benchmark_move(rdev, common_modes[i],
					      RADEON_GEM_DOMAIN_VRAM,
					      RADEON_GEM_DOMAIN_GTT);
		break;
	case 8:
		/* VRAM to VRAM, buffer size sweep, common modes */
		for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
			radeon_benchmark_move(rdev, common_modes[i],
					      RADEON_GEM_DOMAIN_VRAM,
					      RADEON_GEM_DOMAIN_VRAM);
		break;

	default:
		DRM_ERROR("Unknown benchmark\n");
	}
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright 2009 Jerome Glisse.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Jerome Glisse
	23	*/
	24	#include <drm/drmP.h>
	25	#include <drm/radeon_drm.h>
	26	#include "radeon_reg.h"
	27	#include "radeon.h"
	28
cc340515 IH	29	#define RADEON_BENCHMARK_COPY_BLIT 1
	30	#define RADEON_BENCHMARK_COPY_DMA 0
	31
	32	#define RADEON_BENCHMARK_ITERATIONS 1024
638dd7db	33	#define RADEON_BENCHMARK_COMMON_MODES_N 17
cc340515 IH	34
	35	static int radeon_benchmark_do_move(struct radeon_device *rdev, unsigned size,
	36	uint64_t saddr, uint64_t daddr,
3f5e1b4f IH	37	int flag, int n,
3f5e1b4f IH	38	struct reservation_object *resv)
cc340515 IH	39	{
	40	unsigned long start_jiffies;
	41	unsigned long end_jiffies;
	42	struct radeon_fence *fence = NULL;
	43	int i, r;
	44
	45	start_jiffies = jiffies;
	46	for (i = 0; i < n; i++) {
cc340515 IH	47	switch (flag) {
cc340515 IH	48	case RADEON_BENCHMARK_COPY_DMA:
57d20a43 CK	49	fence = radeon_copy_dma(rdev, saddr, daddr,
57d20a43 CK	50	size / RADEON_GPU_PAGE_SIZE,
3f5e1b4f	51	resv);
cc340515 IH	52	break;
cc340515 IH	53	case RADEON_BENCHMARK_COPY_BLIT:
57d20a43 CK	54	fence = radeon_copy_blit(rdev, saddr, daddr,
57d20a43 CK	55	size / RADEON_GPU_PAGE_SIZE,
3f5e1b4f	56	resv);
cc340515 IH	57	break;
	58	default:
	59	DRM_ERROR("Unknown copy method\n");
57d20a43	60	return -EINVAL;
cc340515	61	}
57d20a43 CK	62	if (IS_ERR(fence))
	63	return PTR_ERR(fence);
	64
cc340515	65	r = radeon_fence_wait(fence, false);
cc340515	66	radeon_fence_unref(&fence);
57d20a43 CK	67	if (r)
57d20a43 CK	68	return r;
cc340515 IH	69	}
cc340515 IH	70	end_jiffies = jiffies;
57d20a43	71	return jiffies_to_msecs(end_jiffies - start_jiffies);
cc340515 IH	72	}
	73
	74
	75	static void radeon_benchmark_log_results(int n, unsigned size,
	76	unsigned int time,
	77	unsigned sdomain, unsigned ddomain,
	78	char *kind)
	79	{
	80	unsigned int throughput = (n * (size >> 10)) / time;
	81	DRM_INFO("radeon: %s %u bo moves of %u kB from"
	82	" %d to %d in %u ms, throughput: %u Mb/s or %u MB/s\n",
	83	kind, n, size >> 10, sdomain, ddomain, time,
	84	throughput * 8, throughput);
	85	}
	86
	87	static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size,
	88	unsigned sdomain, unsigned ddomain)
771fe6b9	89	{
4c788679 JG	90	struct radeon_bo *dobj = NULL;
4c788679 JG	91	struct radeon_bo *sobj = NULL;
771fe6b9	92	uint64_t saddr, daddr;
cc340515	93	int r, n;
bfba1658	94	int time;
771fe6b9	95
cc340515	96	n = RADEON_BENCHMARK_ITERATIONS;
831b6966	97	r = radeon_bo_create(rdev, size, PAGE_SIZE, true, sdomain, 0, NULL, NULL, &sobj);
771fe6b9 JG	98	if (r) {
	99	goto out_cleanup;
	100	}
4c788679 JG	101	r = radeon_bo_reserve(sobj, false);
	102	if (unlikely(r != 0))
	103	goto out_cleanup;
	104	r = radeon_bo_pin(sobj, sdomain, &saddr);
	105	radeon_bo_unreserve(sobj);
771fe6b9 JG	106	if (r) {
	107	goto out_cleanup;
	108	}
831b6966	109	r = radeon_bo_create(rdev, size, PAGE_SIZE, true, ddomain, 0, NULL, NULL, &dobj);
771fe6b9 JG	110	if (r) {
	111	goto out_cleanup;
	112	}
4c788679 JG	113	r = radeon_bo_reserve(dobj, false);
	114	if (unlikely(r != 0))
	115	goto out_cleanup;
	116	r = radeon_bo_pin(dobj, ddomain, &daddr);
	117	radeon_bo_unreserve(dobj);
771fe6b9 JG	118	if (r) {
	119	goto out_cleanup;
	120	}
c60a284c	121
271e53dc	122	if (rdev->asic->copy.dma) {
cc340515	123	time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
3f5e1b4f IH	124	RADEON_BENCHMARK_COPY_DMA, n,
3f5e1b4f IH	125	dobj->tbo.resv);
cc340515	126	if (time < 0)
771fe6b9	127	goto out_cleanup;
cc340515 IH	128	if (time > 0)
	129	radeon_benchmark_log_results(n, size, time,
	130	sdomain, ddomain, "dma");
771fe6b9	131	}
cc340515	132
fa8d387d AD	133	if (rdev->asic->copy.blit) {
fa8d387d AD	134	time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
3f5e1b4f IH	135	RADEON_BENCHMARK_COPY_BLIT, n,
3f5e1b4f IH	136	dobj->tbo.resv);
fa8d387d AD	137	if (time < 0)
	138	goto out_cleanup;
	139	if (time > 0)
	140	radeon_benchmark_log_results(n, size, time,
	141	sdomain, ddomain, "blit");
	142	}
cc340515	143
771fe6b9 JG	144	out_cleanup:
771fe6b9 JG	145	if (sobj) {
4c788679 JG	146	r = radeon_bo_reserve(sobj, false);
	147	if (likely(r == 0)) {
	148	radeon_bo_unpin(sobj);
	149	radeon_bo_unreserve(sobj);
	150	}
	151	radeon_bo_unref(&sobj);
771fe6b9 JG	152	}
771fe6b9 JG	153	if (dobj) {
4c788679 JG	154	r = radeon_bo_reserve(dobj, false);
	155	if (likely(r == 0)) {
	156	radeon_bo_unpin(dobj);
	157	radeon_bo_unreserve(dobj);
	158	}
	159	radeon_bo_unref(&dobj);
771fe6b9	160	}
cc340515	161
771fe6b9	162	if (r) {
cc340515	163	DRM_ERROR("Error while benchmarking BO move.\n");
771fe6b9 JG	164	}
	165	}
	166
638dd7db	167	void radeon_benchmark(struct radeon_device *rdev, int test_number)
771fe6b9	168	{
638dd7db IH	169	int i;
	170	int common_modes[RADEON_BENCHMARK_COMMON_MODES_N] = {
	171	640 * 480 * 4,
	172	720 * 480 * 4,
	173	800 * 600 * 4,
	174	848 * 480 * 4,
	175	1024 * 768 * 4,
	176	1152 * 768 * 4,
	177	1280 * 720 * 4,
	178	1280 * 800 * 4,
	179	1280 * 854 * 4,
	180	1280 * 960 * 4,
	181	1280 * 1024 * 4,
	182	1440 * 900 * 4,
	183	1400 * 1050 * 4,
	184	1680 * 1050 * 4,
	185	1600 * 1200 * 4,
	186	1920 * 1080 * 4,
	187	1920 * 1200 * 4
	188	};
	189
	190	switch (test_number) {
	191	case 1:
	192	/* simple test, VRAM to GTT and GTT to VRAM */
	193	radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_GTT,
	194	RADEON_GEM_DOMAIN_VRAM);
	195	radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_VRAM,
	196	RADEON_GEM_DOMAIN_GTT);
	197	break;
	198	case 2:
	199	/* simple test, VRAM to VRAM */
	200	radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_VRAM,
	201	RADEON_GEM_DOMAIN_VRAM);
	202	break;
	203	case 3:
	204	/* GTT to VRAM, buffer size sweep, powers of 2 */
6d75e83e IH	205	for (i = 1; i <= 16384; i <<= 1)
6d75e83e IH	206	radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
638dd7db IH	207	RADEON_GEM_DOMAIN_GTT,
	208	RADEON_GEM_DOMAIN_VRAM);
	209	break;
	210	case 4:
	211	/* VRAM to GTT, buffer size sweep, powers of 2 */
6d75e83e IH	212	for (i = 1; i <= 16384; i <<= 1)
6d75e83e IH	213	radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
638dd7db IH	214	RADEON_GEM_DOMAIN_VRAM,
	215	RADEON_GEM_DOMAIN_GTT);
	216	break;
	217	case 5:
	218	/* VRAM to VRAM, buffer size sweep, powers of 2 */
6d75e83e IH	219	for (i = 1; i <= 16384; i <<= 1)
6d75e83e IH	220	radeon_benchmark_move(rdev, i * RADEON_GPU_PAGE_SIZE,
638dd7db IH	221	RADEON_GEM_DOMAIN_VRAM,
	222	RADEON_GEM_DOMAIN_VRAM);
	223	break;
	224	case 6:
	225	/* GTT to VRAM, buffer size sweep, common modes */
d7d0a75c	226	for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
638dd7db IH	227	radeon_benchmark_move(rdev, common_modes[i],
	228	RADEON_GEM_DOMAIN_GTT,
	229	RADEON_GEM_DOMAIN_VRAM);
	230	break;
	231	case 7:
	232	/* VRAM to GTT, buffer size sweep, common modes */
d7d0a75c	233	for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
638dd7db IH	234	radeon_benchmark_move(rdev, common_modes[i],
	235	RADEON_GEM_DOMAIN_VRAM,
	236	RADEON_GEM_DOMAIN_GTT);
	237	break;
	238	case 8:
	239	/* VRAM to VRAM, buffer size sweep, common modes */
d7d0a75c	240	for (i = 0; i < RADEON_BENCHMARK_COMMON_MODES_N; i++)
638dd7db IH	241	radeon_benchmark_move(rdev, common_modes[i],
	242	RADEON_GEM_DOMAIN_VRAM,
	243	RADEON_GEM_DOMAIN_VRAM);
	244	break;
	245
	246	default:
	247	DRM_ERROR("Unknown benchmark\n");
	248	}
771fe6b9	249	}