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771fe6b9 JG |
1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | */ | |
26 | #include "drmP.h" | |
27 | #include "radeon_drm.h" | |
28 | #include "radeon.h" | |
29 | ||
30 | #include "atom.h" | |
31 | #include "atom-bits.h" | |
32 | ||
33 | /* from radeon_encoder.c */ | |
34 | extern uint32_t | |
35 | radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, | |
36 | uint8_t dac); | |
37 | extern void radeon_link_encoder_connector(struct drm_device *dev); | |
38 | extern void | |
39 | radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, | |
40 | uint32_t supported_device); | |
41 | ||
42 | /* from radeon_connector.c */ | |
43 | extern void | |
44 | radeon_add_atom_connector(struct drm_device *dev, | |
45 | uint32_t connector_id, | |
46 | uint32_t supported_device, | |
47 | int connector_type, | |
48 | struct radeon_i2c_bus_rec *i2c_bus, | |
b75fad06 | 49 | bool linkb, uint32_t igp_lane_info, |
eed45b30 AD |
50 | uint16_t connector_object_id, |
51 | struct radeon_hpd *hpd); | |
771fe6b9 JG |
52 | |
53 | /* from radeon_legacy_encoder.c */ | |
54 | extern void | |
55 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, | |
56 | uint32_t supported_device); | |
57 | ||
58 | union atom_supported_devices { | |
59 | struct _ATOM_SUPPORTED_DEVICES_INFO info; | |
60 | struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; | |
61 | struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; | |
62 | }; | |
63 | ||
eed45b30 AD |
64 | static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, |
65 | uint8_t id) | |
771fe6b9 | 66 | { |
771fe6b9 | 67 | struct atom_context *ctx = rdev->mode_info.atom_context; |
6a93cb25 | 68 | ATOM_GPIO_I2C_ASSIGMENT *gpio; |
771fe6b9 JG |
69 | struct radeon_i2c_bus_rec i2c; |
70 | int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); | |
71 | struct _ATOM_GPIO_I2C_INFO *i2c_info; | |
72 | uint16_t data_offset; | |
d3f420d1 | 73 | int i; |
771fe6b9 JG |
74 | |
75 | memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); | |
76 | i2c.valid = false; | |
77 | ||
78 | atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset); | |
79 | ||
80 | i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); | |
81 | ||
6a93cb25 | 82 | |
d3f420d1 AD |
83 | for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
84 | gpio = &i2c_info->asGPIO_Info[i]; | |
85 | ||
86 | if (gpio->sucI2cId.ucAccess == id) { | |
87 | i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; | |
88 | i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; | |
89 | i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; | |
90 | i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; | |
91 | i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; | |
92 | i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; | |
93 | i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; | |
94 | i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; | |
95 | i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); | |
96 | i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); | |
97 | i2c.en_clk_mask = (1 << gpio->ucClkEnShift); | |
98 | i2c.en_data_mask = (1 << gpio->ucDataEnShift); | |
99 | i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); | |
100 | i2c.y_data_mask = (1 << gpio->ucDataY_Shift); | |
101 | i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); | |
102 | i2c.a_data_mask = (1 << gpio->ucDataA_Shift); | |
103 | ||
104 | if (gpio->sucI2cId.sbfAccess.bfHW_Capable) | |
105 | i2c.hw_capable = true; | |
106 | else | |
107 | i2c.hw_capable = false; | |
6a93cb25 | 108 | |
d3f420d1 AD |
109 | if (gpio->sucI2cId.ucAccess == 0xa0) |
110 | i2c.mm_i2c = true; | |
111 | else | |
112 | i2c.mm_i2c = false; | |
6a93cb25 | 113 | |
d3f420d1 AD |
114 | i2c.i2c_id = gpio->sucI2cId.ucAccess; |
115 | ||
116 | i2c.valid = true; | |
1d3d51b6 | 117 | break; |
d3f420d1 AD |
118 | } |
119 | } | |
771fe6b9 JG |
120 | |
121 | return i2c; | |
122 | } | |
123 | ||
eed45b30 AD |
124 | static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev, |
125 | u8 id) | |
126 | { | |
127 | struct atom_context *ctx = rdev->mode_info.atom_context; | |
128 | struct radeon_gpio_rec gpio; | |
129 | int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); | |
130 | struct _ATOM_GPIO_PIN_LUT *gpio_info; | |
131 | ATOM_GPIO_PIN_ASSIGNMENT *pin; | |
132 | u16 data_offset, size; | |
133 | int i, num_indices; | |
134 | ||
135 | memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); | |
136 | gpio.valid = false; | |
137 | ||
138 | atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset); | |
139 | ||
140 | gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); | |
141 | ||
142 | num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT); | |
143 | ||
144 | for (i = 0; i < num_indices; i++) { | |
145 | pin = &gpio_info->asGPIO_Pin[i]; | |
146 | if (id == pin->ucGPIO_ID) { | |
147 | gpio.id = pin->ucGPIO_ID; | |
148 | gpio.reg = pin->usGpioPin_AIndex * 4; | |
149 | gpio.mask = (1 << pin->ucGpioPinBitShift); | |
150 | gpio.valid = true; | |
151 | break; | |
152 | } | |
153 | } | |
154 | ||
155 | return gpio; | |
156 | } | |
157 | ||
158 | static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, | |
159 | struct radeon_gpio_rec *gpio) | |
160 | { | |
161 | struct radeon_hpd hpd; | |
162 | hpd.gpio = *gpio; | |
163 | if (gpio->reg == AVIVO_DC_GPIO_HPD_A) { | |
164 | switch(gpio->mask) { | |
165 | case (1 << 0): | |
166 | hpd.hpd = RADEON_HPD_1; | |
167 | break; | |
168 | case (1 << 8): | |
169 | hpd.hpd = RADEON_HPD_2; | |
170 | break; | |
171 | case (1 << 16): | |
172 | hpd.hpd = RADEON_HPD_3; | |
173 | break; | |
174 | case (1 << 24): | |
175 | hpd.hpd = RADEON_HPD_4; | |
176 | break; | |
177 | case (1 << 26): | |
178 | hpd.hpd = RADEON_HPD_5; | |
179 | break; | |
180 | case (1 << 28): | |
181 | hpd.hpd = RADEON_HPD_6; | |
182 | break; | |
183 | default: | |
184 | hpd.hpd = RADEON_HPD_NONE; | |
185 | break; | |
186 | } | |
187 | } else | |
188 | hpd.hpd = RADEON_HPD_NONE; | |
189 | return hpd; | |
190 | } | |
191 | ||
771fe6b9 JG |
192 | static bool radeon_atom_apply_quirks(struct drm_device *dev, |
193 | uint32_t supported_device, | |
194 | int *connector_type, | |
848577ee | 195 | struct radeon_i2c_bus_rec *i2c_bus, |
eed45b30 AD |
196 | uint16_t *line_mux, |
197 | struct radeon_hpd *hpd) | |
771fe6b9 JG |
198 | { |
199 | ||
200 | /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ | |
201 | if ((dev->pdev->device == 0x791e) && | |
202 | (dev->pdev->subsystem_vendor == 0x1043) && | |
203 | (dev->pdev->subsystem_device == 0x826d)) { | |
204 | if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && | |
205 | (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) | |
206 | *connector_type = DRM_MODE_CONNECTOR_DVID; | |
207 | } | |
208 | ||
209 | /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ | |
210 | if ((dev->pdev->device == 0x7941) && | |
211 | (dev->pdev->subsystem_vendor == 0x147b) && | |
212 | (dev->pdev->subsystem_device == 0x2412)) { | |
213 | if (*connector_type == DRM_MODE_CONNECTOR_DVII) | |
214 | return false; | |
215 | } | |
216 | ||
217 | /* Falcon NW laptop lists vga ddc line for LVDS */ | |
218 | if ((dev->pdev->device == 0x5653) && | |
219 | (dev->pdev->subsystem_vendor == 0x1462) && | |
220 | (dev->pdev->subsystem_device == 0x0291)) { | |
848577ee | 221 | if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { |
771fe6b9 | 222 | i2c_bus->valid = false; |
848577ee AD |
223 | *line_mux = 53; |
224 | } | |
771fe6b9 JG |
225 | } |
226 | ||
4e3f9b78 AD |
227 | /* HIS X1300 is DVI+VGA, not DVI+DVI */ |
228 | if ((dev->pdev->device == 0x7146) && | |
229 | (dev->pdev->subsystem_vendor == 0x17af) && | |
230 | (dev->pdev->subsystem_device == 0x2058)) { | |
231 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) | |
232 | return false; | |
233 | } | |
234 | ||
aa1a750e DA |
235 | /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ |
236 | if ((dev->pdev->device == 0x7142) && | |
237 | (dev->pdev->subsystem_vendor == 0x1458) && | |
238 | (dev->pdev->subsystem_device == 0x2134)) { | |
239 | if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) | |
240 | return false; | |
241 | } | |
242 | ||
243 | ||
771fe6b9 JG |
244 | /* Funky macbooks */ |
245 | if ((dev->pdev->device == 0x71C5) && | |
246 | (dev->pdev->subsystem_vendor == 0x106b) && | |
247 | (dev->pdev->subsystem_device == 0x0080)) { | |
248 | if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || | |
249 | (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) | |
250 | return false; | |
251 | } | |
252 | ||
771fe6b9 JG |
253 | /* ASUS HD 3600 XT board lists the DVI port as HDMI */ |
254 | if ((dev->pdev->device == 0x9598) && | |
255 | (dev->pdev->subsystem_vendor == 0x1043) && | |
256 | (dev->pdev->subsystem_device == 0x01da)) { | |
705af9c7 | 257 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { |
d42571ef | 258 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
705af9c7 AD |
259 | } |
260 | } | |
261 | ||
262 | /* ASUS HD 3450 board lists the DVI port as HDMI */ | |
263 | if ((dev->pdev->device == 0x95C5) && | |
264 | (dev->pdev->subsystem_vendor == 0x1043) && | |
265 | (dev->pdev->subsystem_device == 0x01e2)) { | |
266 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { | |
d42571ef | 267 | *connector_type = DRM_MODE_CONNECTOR_DVII; |
771fe6b9 JG |
268 | } |
269 | } | |
270 | ||
705af9c7 AD |
271 | /* some BIOSes seem to report DAC on HDMI - usually this is a board with |
272 | * HDMI + VGA reporting as HDMI | |
273 | */ | |
274 | if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { | |
275 | if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { | |
276 | *connector_type = DRM_MODE_CONNECTOR_VGA; | |
277 | *line_mux = 0; | |
278 | } | |
279 | } | |
280 | ||
3e5f8ff3 AD |
281 | /* Acer laptop reports DVI-D as DVI-I */ |
282 | if ((dev->pdev->device == 0x95c4) && | |
283 | (dev->pdev->subsystem_vendor == 0x1025) && | |
284 | (dev->pdev->subsystem_device == 0x013c)) { | |
285 | if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && | |
286 | (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) | |
287 | *connector_type = DRM_MODE_CONNECTOR_DVID; | |
288 | } | |
289 | ||
771fe6b9 JG |
290 | return true; |
291 | } | |
292 | ||
293 | const int supported_devices_connector_convert[] = { | |
294 | DRM_MODE_CONNECTOR_Unknown, | |
295 | DRM_MODE_CONNECTOR_VGA, | |
296 | DRM_MODE_CONNECTOR_DVII, | |
297 | DRM_MODE_CONNECTOR_DVID, | |
298 | DRM_MODE_CONNECTOR_DVIA, | |
299 | DRM_MODE_CONNECTOR_SVIDEO, | |
300 | DRM_MODE_CONNECTOR_Composite, | |
301 | DRM_MODE_CONNECTOR_LVDS, | |
302 | DRM_MODE_CONNECTOR_Unknown, | |
303 | DRM_MODE_CONNECTOR_Unknown, | |
304 | DRM_MODE_CONNECTOR_HDMIA, | |
305 | DRM_MODE_CONNECTOR_HDMIB, | |
306 | DRM_MODE_CONNECTOR_Unknown, | |
307 | DRM_MODE_CONNECTOR_Unknown, | |
308 | DRM_MODE_CONNECTOR_9PinDIN, | |
309 | DRM_MODE_CONNECTOR_DisplayPort | |
310 | }; | |
311 | ||
b75fad06 AD |
312 | const uint16_t supported_devices_connector_object_id_convert[] = { |
313 | CONNECTOR_OBJECT_ID_NONE, | |
314 | CONNECTOR_OBJECT_ID_VGA, | |
315 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ | |
316 | CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ | |
317 | CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ | |
318 | CONNECTOR_OBJECT_ID_COMPOSITE, | |
319 | CONNECTOR_OBJECT_ID_SVIDEO, | |
320 | CONNECTOR_OBJECT_ID_LVDS, | |
321 | CONNECTOR_OBJECT_ID_9PIN_DIN, | |
322 | CONNECTOR_OBJECT_ID_9PIN_DIN, | |
323 | CONNECTOR_OBJECT_ID_DISPLAYPORT, | |
324 | CONNECTOR_OBJECT_ID_HDMI_TYPE_A, | |
325 | CONNECTOR_OBJECT_ID_HDMI_TYPE_B, | |
326 | CONNECTOR_OBJECT_ID_SVIDEO | |
327 | }; | |
328 | ||
771fe6b9 JG |
329 | const int object_connector_convert[] = { |
330 | DRM_MODE_CONNECTOR_Unknown, | |
331 | DRM_MODE_CONNECTOR_DVII, | |
332 | DRM_MODE_CONNECTOR_DVII, | |
333 | DRM_MODE_CONNECTOR_DVID, | |
334 | DRM_MODE_CONNECTOR_DVID, | |
335 | DRM_MODE_CONNECTOR_VGA, | |
336 | DRM_MODE_CONNECTOR_Composite, | |
337 | DRM_MODE_CONNECTOR_SVIDEO, | |
338 | DRM_MODE_CONNECTOR_Unknown, | |
705af9c7 | 339 | DRM_MODE_CONNECTOR_Unknown, |
771fe6b9 JG |
340 | DRM_MODE_CONNECTOR_9PinDIN, |
341 | DRM_MODE_CONNECTOR_Unknown, | |
342 | DRM_MODE_CONNECTOR_HDMIA, | |
343 | DRM_MODE_CONNECTOR_HDMIB, | |
771fe6b9 JG |
344 | DRM_MODE_CONNECTOR_LVDS, |
345 | DRM_MODE_CONNECTOR_9PinDIN, | |
346 | DRM_MODE_CONNECTOR_Unknown, | |
347 | DRM_MODE_CONNECTOR_Unknown, | |
348 | DRM_MODE_CONNECTOR_Unknown, | |
196c58d2 AD |
349 | DRM_MODE_CONNECTOR_DisplayPort, |
350 | DRM_MODE_CONNECTOR_eDP, | |
351 | DRM_MODE_CONNECTOR_Unknown | |
771fe6b9 JG |
352 | }; |
353 | ||
354 | bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) | |
355 | { | |
356 | struct radeon_device *rdev = dev->dev_private; | |
357 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
358 | struct atom_context *ctx = mode_info->atom_context; | |
359 | int index = GetIndexIntoMasterTable(DATA, Object_Header); | |
eed45b30 AD |
360 | u16 size, data_offset; |
361 | u8 frev, crev; | |
771fe6b9 JG |
362 | ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
363 | ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; | |
364 | ATOM_OBJECT_HEADER *obj_header; | |
365 | int i, j, path_size, device_support; | |
366 | int connector_type; | |
eed45b30 | 367 | u16 igp_lane_info, conn_id, connector_object_id; |
771fe6b9 JG |
368 | bool linkb; |
369 | struct radeon_i2c_bus_rec ddc_bus; | |
eed45b30 AD |
370 | struct radeon_gpio_rec gpio; |
371 | struct radeon_hpd hpd; | |
372 | ||
771fe6b9 JG |
373 | atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); |
374 | ||
375 | if (data_offset == 0) | |
376 | return false; | |
377 | ||
378 | if (crev < 2) | |
379 | return false; | |
380 | ||
381 | obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); | |
382 | path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) | |
383 | (ctx->bios + data_offset + | |
384 | le16_to_cpu(obj_header->usDisplayPathTableOffset)); | |
385 | con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) | |
386 | (ctx->bios + data_offset + | |
387 | le16_to_cpu(obj_header->usConnectorObjectTableOffset)); | |
388 | device_support = le16_to_cpu(obj_header->usDeviceSupport); | |
389 | ||
390 | path_size = 0; | |
391 | for (i = 0; i < path_obj->ucNumOfDispPath; i++) { | |
392 | uint8_t *addr = (uint8_t *) path_obj->asDispPath; | |
393 | ATOM_DISPLAY_OBJECT_PATH *path; | |
394 | addr += path_size; | |
395 | path = (ATOM_DISPLAY_OBJECT_PATH *) addr; | |
396 | path_size += le16_to_cpu(path->usSize); | |
397 | linkb = false; | |
771fe6b9 JG |
398 | if (device_support & le16_to_cpu(path->usDeviceTag)) { |
399 | uint8_t con_obj_id, con_obj_num, con_obj_type; | |
400 | ||
401 | con_obj_id = | |
402 | (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) | |
403 | >> OBJECT_ID_SHIFT; | |
404 | con_obj_num = | |
405 | (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) | |
406 | >> ENUM_ID_SHIFT; | |
407 | con_obj_type = | |
408 | (le16_to_cpu(path->usConnObjectId) & | |
409 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; | |
410 | ||
4bbd4973 DA |
411 | /* TODO CV support */ |
412 | if (le16_to_cpu(path->usDeviceTag) == | |
413 | ATOM_DEVICE_CV_SUPPORT) | |
771fe6b9 JG |
414 | continue; |
415 | ||
ee59f2b4 AD |
416 | /* IGP chips */ |
417 | if ((rdev->flags & RADEON_IS_IGP) && | |
771fe6b9 JG |
418 | (con_obj_id == |
419 | CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { | |
420 | uint16_t igp_offset = 0; | |
421 | ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; | |
422 | ||
423 | index = | |
424 | GetIndexIntoMasterTable(DATA, | |
425 | IntegratedSystemInfo); | |
426 | ||
427 | atom_parse_data_header(ctx, index, &size, &frev, | |
428 | &crev, &igp_offset); | |
429 | ||
430 | if (crev >= 2) { | |
431 | igp_obj = | |
432 | (ATOM_INTEGRATED_SYSTEM_INFO_V2 | |
433 | *) (ctx->bios + igp_offset); | |
434 | ||
435 | if (igp_obj) { | |
436 | uint32_t slot_config, ct; | |
437 | ||
438 | if (con_obj_num == 1) | |
439 | slot_config = | |
440 | igp_obj-> | |
441 | ulDDISlot1Config; | |
442 | else | |
443 | slot_config = | |
444 | igp_obj-> | |
445 | ulDDISlot2Config; | |
446 | ||
447 | ct = (slot_config >> 16) & 0xff; | |
448 | connector_type = | |
449 | object_connector_convert | |
450 | [ct]; | |
b75fad06 | 451 | connector_object_id = ct; |
771fe6b9 JG |
452 | igp_lane_info = |
453 | slot_config & 0xffff; | |
454 | } else | |
455 | continue; | |
456 | } else | |
457 | continue; | |
458 | } else { | |
459 | igp_lane_info = 0; | |
460 | connector_type = | |
461 | object_connector_convert[con_obj_id]; | |
b75fad06 | 462 | connector_object_id = con_obj_id; |
771fe6b9 JG |
463 | } |
464 | ||
465 | if (connector_type == DRM_MODE_CONNECTOR_Unknown) | |
466 | continue; | |
467 | ||
468 | for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); | |
469 | j++) { | |
470 | uint8_t enc_obj_id, enc_obj_num, enc_obj_type; | |
471 | ||
472 | enc_obj_id = | |
473 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
474 | OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; | |
475 | enc_obj_num = | |
476 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
477 | ENUM_ID_MASK) >> ENUM_ID_SHIFT; | |
478 | enc_obj_type = | |
479 | (le16_to_cpu(path->usGraphicObjIds[j]) & | |
480 | OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; | |
481 | ||
482 | /* FIXME: add support for router objects */ | |
483 | if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { | |
484 | if (enc_obj_num == 2) | |
485 | linkb = true; | |
486 | else | |
487 | linkb = false; | |
488 | ||
489 | radeon_add_atom_encoder(dev, | |
490 | enc_obj_id, | |
491 | le16_to_cpu | |
492 | (path-> | |
493 | usDeviceTag)); | |
494 | ||
495 | } | |
496 | } | |
497 | ||
eed45b30 | 498 | /* look up gpio for ddc, hpd */ |
771fe6b9 | 499 | if ((le16_to_cpu(path->usDeviceTag) & |
eed45b30 | 500 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { |
771fe6b9 JG |
501 | for (j = 0; j < con_obj->ucNumberOfObjects; j++) { |
502 | if (le16_to_cpu(path->usConnObjectId) == | |
503 | le16_to_cpu(con_obj->asObjects[j]. | |
504 | usObjectID)) { | |
505 | ATOM_COMMON_RECORD_HEADER | |
506 | *record = | |
507 | (ATOM_COMMON_RECORD_HEADER | |
508 | *) | |
509 | (ctx->bios + data_offset + | |
510 | le16_to_cpu(con_obj-> | |
511 | asObjects[j]. | |
512 | usRecordOffset)); | |
513 | ATOM_I2C_RECORD *i2c_record; | |
eed45b30 | 514 | ATOM_HPD_INT_RECORD *hpd_record; |
d3f420d1 | 515 | ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; |
eed45b30 | 516 | hpd.hpd = RADEON_HPD_NONE; |
6a93cb25 | 517 | |
771fe6b9 JG |
518 | while (record->ucRecordType > 0 |
519 | && record-> | |
520 | ucRecordType <= | |
521 | ATOM_MAX_OBJECT_RECORD_NUMBER) { | |
eed45b30 | 522 | switch (record->ucRecordType) { |
771fe6b9 JG |
523 | case ATOM_I2C_RECORD_TYPE: |
524 | i2c_record = | |
eed45b30 AD |
525 | (ATOM_I2C_RECORD *) |
526 | record; | |
d3f420d1 AD |
527 | i2c_config = |
528 | (ATOM_I2C_ID_CONFIG_ACCESS *) | |
529 | &i2c_record->sucI2cId; | |
eed45b30 | 530 | ddc_bus = radeon_lookup_i2c_gpio(rdev, |
d3f420d1 AD |
531 | i2c_config-> |
532 | ucAccess); | |
eed45b30 AD |
533 | break; |
534 | case ATOM_HPD_INT_RECORD_TYPE: | |
535 | hpd_record = | |
536 | (ATOM_HPD_INT_RECORD *) | |
537 | record; | |
538 | gpio = radeon_lookup_gpio(rdev, | |
539 | hpd_record->ucHPDIntGPIOID); | |
540 | hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); | |
541 | hpd.plugged_state = hpd_record->ucPlugged_PinState; | |
771fe6b9 JG |
542 | break; |
543 | } | |
544 | record = | |
545 | (ATOM_COMMON_RECORD_HEADER | |
546 | *) ((char *)record | |
547 | + | |
548 | record-> | |
549 | ucRecordSize); | |
550 | } | |
551 | break; | |
552 | } | |
553 | } | |
eed45b30 AD |
554 | } else { |
555 | hpd.hpd = RADEON_HPD_NONE; | |
771fe6b9 | 556 | ddc_bus.valid = false; |
eed45b30 | 557 | } |
771fe6b9 | 558 | |
705af9c7 AD |
559 | conn_id = le16_to_cpu(path->usConnObjectId); |
560 | ||
561 | if (!radeon_atom_apply_quirks | |
562 | (dev, le16_to_cpu(path->usDeviceTag), &connector_type, | |
eed45b30 | 563 | &ddc_bus, &conn_id, &hpd)) |
705af9c7 AD |
564 | continue; |
565 | ||
771fe6b9 | 566 | radeon_add_atom_connector(dev, |
705af9c7 | 567 | conn_id, |
771fe6b9 JG |
568 | le16_to_cpu(path-> |
569 | usDeviceTag), | |
570 | connector_type, &ddc_bus, | |
b75fad06 | 571 | linkb, igp_lane_info, |
eed45b30 AD |
572 | connector_object_id, |
573 | &hpd); | |
771fe6b9 JG |
574 | |
575 | } | |
576 | } | |
577 | ||
578 | radeon_link_encoder_connector(dev); | |
579 | ||
580 | return true; | |
581 | } | |
582 | ||
b75fad06 AD |
583 | static uint16_t atombios_get_connector_object_id(struct drm_device *dev, |
584 | int connector_type, | |
585 | uint16_t devices) | |
586 | { | |
587 | struct radeon_device *rdev = dev->dev_private; | |
588 | ||
589 | if (rdev->flags & RADEON_IS_IGP) { | |
590 | return supported_devices_connector_object_id_convert | |
591 | [connector_type]; | |
592 | } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || | |
593 | (connector_type == DRM_MODE_CONNECTOR_DVID)) && | |
594 | (devices & ATOM_DEVICE_DFP2_SUPPORT)) { | |
595 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
596 | struct atom_context *ctx = mode_info->atom_context; | |
597 | int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); | |
598 | uint16_t size, data_offset; | |
599 | uint8_t frev, crev; | |
600 | ATOM_XTMDS_INFO *xtmds; | |
601 | ||
602 | atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); | |
603 | xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); | |
604 | ||
605 | if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { | |
606 | if (connector_type == DRM_MODE_CONNECTOR_DVII) | |
607 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; | |
608 | else | |
609 | return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; | |
610 | } else { | |
611 | if (connector_type == DRM_MODE_CONNECTOR_DVII) | |
612 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; | |
613 | else | |
614 | return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; | |
615 | } | |
616 | } else { | |
617 | return supported_devices_connector_object_id_convert | |
618 | [connector_type]; | |
619 | } | |
620 | } | |
621 | ||
771fe6b9 JG |
622 | struct bios_connector { |
623 | bool valid; | |
705af9c7 | 624 | uint16_t line_mux; |
771fe6b9 JG |
625 | uint16_t devices; |
626 | int connector_type; | |
627 | struct radeon_i2c_bus_rec ddc_bus; | |
eed45b30 | 628 | struct radeon_hpd hpd; |
771fe6b9 JG |
629 | }; |
630 | ||
631 | bool radeon_get_atom_connector_info_from_supported_devices_table(struct | |
632 | drm_device | |
633 | *dev) | |
634 | { | |
635 | struct radeon_device *rdev = dev->dev_private; | |
636 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
637 | struct atom_context *ctx = mode_info->atom_context; | |
638 | int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); | |
639 | uint16_t size, data_offset; | |
640 | uint8_t frev, crev; | |
641 | uint16_t device_support; | |
642 | uint8_t dac; | |
643 | union atom_supported_devices *supported_devices; | |
eed45b30 | 644 | int i, j, max_device; |
771fe6b9 JG |
645 | struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE]; |
646 | ||
647 | atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); | |
648 | ||
649 | supported_devices = | |
650 | (union atom_supported_devices *)(ctx->bios + data_offset); | |
651 | ||
652 | device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); | |
653 | ||
eed45b30 AD |
654 | if (frev > 1) |
655 | max_device = ATOM_MAX_SUPPORTED_DEVICE; | |
656 | else | |
657 | max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; | |
658 | ||
659 | for (i = 0; i < max_device; i++) { | |
771fe6b9 JG |
660 | ATOM_CONNECTOR_INFO_I2C ci = |
661 | supported_devices->info.asConnInfo[i]; | |
662 | ||
663 | bios_connectors[i].valid = false; | |
664 | ||
665 | if (!(device_support & (1 << i))) { | |
666 | continue; | |
667 | } | |
668 | ||
669 | if (i == ATOM_DEVICE_CV_INDEX) { | |
670 | DRM_DEBUG("Skipping Component Video\n"); | |
671 | continue; | |
672 | } | |
673 | ||
771fe6b9 JG |
674 | bios_connectors[i].connector_type = |
675 | supported_devices_connector_convert[ci.sucConnectorInfo. | |
676 | sbfAccess. | |
677 | bfConnectorType]; | |
678 | ||
679 | if (bios_connectors[i].connector_type == | |
680 | DRM_MODE_CONNECTOR_Unknown) | |
681 | continue; | |
682 | ||
683 | dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; | |
684 | ||
d3f420d1 AD |
685 | bios_connectors[i].line_mux = |
686 | ci.sucI2cId.ucAccess; | |
771fe6b9 JG |
687 | |
688 | /* give tv unique connector ids */ | |
689 | if (i == ATOM_DEVICE_TV1_INDEX) { | |
690 | bios_connectors[i].ddc_bus.valid = false; | |
691 | bios_connectors[i].line_mux = 50; | |
692 | } else if (i == ATOM_DEVICE_TV2_INDEX) { | |
693 | bios_connectors[i].ddc_bus.valid = false; | |
694 | bios_connectors[i].line_mux = 51; | |
695 | } else if (i == ATOM_DEVICE_CV_INDEX) { | |
696 | bios_connectors[i].ddc_bus.valid = false; | |
697 | bios_connectors[i].line_mux = 52; | |
698 | } else | |
699 | bios_connectors[i].ddc_bus = | |
eed45b30 AD |
700 | radeon_lookup_i2c_gpio(rdev, |
701 | bios_connectors[i].line_mux); | |
702 | ||
703 | if ((crev > 1) && (frev > 1)) { | |
704 | u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; | |
705 | switch (isb) { | |
706 | case 0x4: | |
707 | bios_connectors[i].hpd.hpd = RADEON_HPD_1; | |
708 | break; | |
709 | case 0xa: | |
710 | bios_connectors[i].hpd.hpd = RADEON_HPD_2; | |
711 | break; | |
712 | default: | |
713 | bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; | |
714 | break; | |
715 | } | |
716 | } else { | |
717 | if (i == ATOM_DEVICE_DFP1_INDEX) | |
718 | bios_connectors[i].hpd.hpd = RADEON_HPD_1; | |
719 | else if (i == ATOM_DEVICE_DFP2_INDEX) | |
720 | bios_connectors[i].hpd.hpd = RADEON_HPD_2; | |
721 | else | |
722 | bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; | |
723 | } | |
771fe6b9 JG |
724 | |
725 | /* Always set the connector type to VGA for CRT1/CRT2. if they are | |
726 | * shared with a DVI port, we'll pick up the DVI connector when we | |
727 | * merge the outputs. Some bioses incorrectly list VGA ports as DVI. | |
728 | */ | |
729 | if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) | |
730 | bios_connectors[i].connector_type = | |
731 | DRM_MODE_CONNECTOR_VGA; | |
732 | ||
733 | if (!radeon_atom_apply_quirks | |
734 | (dev, (1 << i), &bios_connectors[i].connector_type, | |
eed45b30 AD |
735 | &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, |
736 | &bios_connectors[i].hpd)) | |
771fe6b9 JG |
737 | continue; |
738 | ||
739 | bios_connectors[i].valid = true; | |
740 | bios_connectors[i].devices = (1 << i); | |
741 | ||
742 | if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) | |
743 | radeon_add_atom_encoder(dev, | |
744 | radeon_get_encoder_id(dev, | |
745 | (1 << i), | |
746 | dac), | |
747 | (1 << i)); | |
748 | else | |
749 | radeon_add_legacy_encoder(dev, | |
750 | radeon_get_encoder_id(dev, | |
f56cd64f | 751 | (1 << i), |
771fe6b9 JG |
752 | dac), |
753 | (1 << i)); | |
754 | } | |
755 | ||
756 | /* combine shared connectors */ | |
eed45b30 | 757 | for (i = 0; i < max_device; i++) { |
771fe6b9 | 758 | if (bios_connectors[i].valid) { |
eed45b30 | 759 | for (j = 0; j < max_device; j++) { |
771fe6b9 JG |
760 | if (bios_connectors[j].valid && (i != j)) { |
761 | if (bios_connectors[i].line_mux == | |
762 | bios_connectors[j].line_mux) { | |
f56cd64f AD |
763 | /* make sure not to combine LVDS */ |
764 | if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
765 | bios_connectors[i].line_mux = 53; | |
766 | bios_connectors[i].ddc_bus.valid = false; | |
767 | continue; | |
768 | } | |
769 | if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { | |
770 | bios_connectors[j].line_mux = 53; | |
771 | bios_connectors[j].ddc_bus.valid = false; | |
772 | continue; | |
773 | } | |
774 | /* combine analog and digital for DVI-I */ | |
775 | if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && | |
776 | (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || | |
777 | ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && | |
778 | (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { | |
779 | bios_connectors[i].devices |= | |
780 | bios_connectors[j].devices; | |
781 | bios_connectors[i].connector_type = | |
782 | DRM_MODE_CONNECTOR_DVII; | |
783 | if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) | |
eed45b30 AD |
784 | bios_connectors[i].hpd = |
785 | bios_connectors[j].hpd; | |
f56cd64f | 786 | bios_connectors[j].valid = false; |
771fe6b9 JG |
787 | } |
788 | } | |
789 | } | |
790 | } | |
791 | } | |
792 | } | |
793 | ||
794 | /* add the connectors */ | |
eed45b30 | 795 | for (i = 0; i < max_device; i++) { |
b75fad06 AD |
796 | if (bios_connectors[i].valid) { |
797 | uint16_t connector_object_id = | |
798 | atombios_get_connector_object_id(dev, | |
799 | bios_connectors[i].connector_type, | |
800 | bios_connectors[i].devices); | |
771fe6b9 JG |
801 | radeon_add_atom_connector(dev, |
802 | bios_connectors[i].line_mux, | |
803 | bios_connectors[i].devices, | |
804 | bios_connectors[i]. | |
805 | connector_type, | |
806 | &bios_connectors[i].ddc_bus, | |
b75fad06 | 807 | false, 0, |
eed45b30 AD |
808 | connector_object_id, |
809 | &bios_connectors[i].hpd); | |
b75fad06 | 810 | } |
771fe6b9 JG |
811 | } |
812 | ||
813 | radeon_link_encoder_connector(dev); | |
814 | ||
815 | return true; | |
816 | } | |
817 | ||
818 | union firmware_info { | |
819 | ATOM_FIRMWARE_INFO info; | |
820 | ATOM_FIRMWARE_INFO_V1_2 info_12; | |
821 | ATOM_FIRMWARE_INFO_V1_3 info_13; | |
822 | ATOM_FIRMWARE_INFO_V1_4 info_14; | |
823 | }; | |
824 | ||
825 | bool radeon_atom_get_clock_info(struct drm_device *dev) | |
826 | { | |
827 | struct radeon_device *rdev = dev->dev_private; | |
828 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
829 | int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); | |
830 | union firmware_info *firmware_info; | |
831 | uint8_t frev, crev; | |
832 | struct radeon_pll *p1pll = &rdev->clock.p1pll; | |
833 | struct radeon_pll *p2pll = &rdev->clock.p2pll; | |
834 | struct radeon_pll *spll = &rdev->clock.spll; | |
835 | struct radeon_pll *mpll = &rdev->clock.mpll; | |
836 | uint16_t data_offset; | |
837 | ||
838 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, | |
839 | &crev, &data_offset); | |
840 | ||
841 | firmware_info = | |
842 | (union firmware_info *)(mode_info->atom_context->bios + | |
843 | data_offset); | |
844 | ||
845 | if (firmware_info) { | |
846 | /* pixel clocks */ | |
847 | p1pll->reference_freq = | |
848 | le16_to_cpu(firmware_info->info.usReferenceClock); | |
849 | p1pll->reference_div = 0; | |
850 | ||
bc293e58 MF |
851 | if (crev < 2) |
852 | p1pll->pll_out_min = | |
853 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); | |
854 | else | |
855 | p1pll->pll_out_min = | |
856 | le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); | |
771fe6b9 JG |
857 | p1pll->pll_out_max = |
858 | le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); | |
859 | ||
860 | if (p1pll->pll_out_min == 0) { | |
861 | if (ASIC_IS_AVIVO(rdev)) | |
862 | p1pll->pll_out_min = 64800; | |
863 | else | |
864 | p1pll->pll_out_min = 20000; | |
8f552a66 AD |
865 | } else if (p1pll->pll_out_min > 64800) { |
866 | /* Limiting the pll output range is a good thing generally as | |
867 | * it limits the number of possible pll combinations for a given | |
868 | * frequency presumably to the ones that work best on each card. | |
869 | * However, certain duallink DVI monitors seem to like | |
870 | * pll combinations that would be limited by this at least on | |
871 | * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per | |
872 | * family. | |
873 | */ | |
b27b6375 AD |
874 | if (!radeon_new_pll) |
875 | p1pll->pll_out_min = 64800; | |
771fe6b9 JG |
876 | } |
877 | ||
878 | p1pll->pll_in_min = | |
879 | le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); | |
880 | p1pll->pll_in_max = | |
881 | le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); | |
882 | ||
883 | *p2pll = *p1pll; | |
884 | ||
885 | /* system clock */ | |
886 | spll->reference_freq = | |
887 | le16_to_cpu(firmware_info->info.usReferenceClock); | |
888 | spll->reference_div = 0; | |
889 | ||
890 | spll->pll_out_min = | |
891 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); | |
892 | spll->pll_out_max = | |
893 | le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); | |
894 | ||
895 | /* ??? */ | |
896 | if (spll->pll_out_min == 0) { | |
897 | if (ASIC_IS_AVIVO(rdev)) | |
898 | spll->pll_out_min = 64800; | |
899 | else | |
900 | spll->pll_out_min = 20000; | |
901 | } | |
902 | ||
903 | spll->pll_in_min = | |
904 | le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); | |
905 | spll->pll_in_max = | |
906 | le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); | |
907 | ||
908 | /* memory clock */ | |
909 | mpll->reference_freq = | |
910 | le16_to_cpu(firmware_info->info.usReferenceClock); | |
911 | mpll->reference_div = 0; | |
912 | ||
913 | mpll->pll_out_min = | |
914 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); | |
915 | mpll->pll_out_max = | |
916 | le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); | |
917 | ||
918 | /* ??? */ | |
919 | if (mpll->pll_out_min == 0) { | |
920 | if (ASIC_IS_AVIVO(rdev)) | |
921 | mpll->pll_out_min = 64800; | |
922 | else | |
923 | mpll->pll_out_min = 20000; | |
924 | } | |
925 | ||
926 | mpll->pll_in_min = | |
927 | le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); | |
928 | mpll->pll_in_max = | |
929 | le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); | |
930 | ||
931 | rdev->clock.default_sclk = | |
932 | le32_to_cpu(firmware_info->info.ulDefaultEngineClock); | |
933 | rdev->clock.default_mclk = | |
934 | le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); | |
935 | ||
936 | return true; | |
937 | } | |
938 | return false; | |
939 | } | |
940 | ||
06b6476d AD |
941 | union igp_info { |
942 | struct _ATOM_INTEGRATED_SYSTEM_INFO info; | |
943 | struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; | |
944 | }; | |
945 | ||
946 | bool radeon_atombios_sideport_present(struct radeon_device *rdev) | |
947 | { | |
948 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
949 | int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); | |
950 | union igp_info *igp_info; | |
951 | u8 frev, crev; | |
952 | u16 data_offset; | |
953 | ||
954 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, | |
955 | &crev, &data_offset); | |
956 | ||
957 | igp_info = (union igp_info *)(mode_info->atom_context->bios + | |
958 | data_offset); | |
959 | ||
960 | if (igp_info) { | |
961 | switch (crev) { | |
962 | case 1: | |
963 | if (igp_info->info.ucMemoryType & 0xf0) | |
964 | return true; | |
965 | break; | |
966 | case 2: | |
967 | if (igp_info->info_2.ucMemoryType & 0x0f) | |
968 | return true; | |
969 | break; | |
970 | default: | |
971 | DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); | |
972 | break; | |
973 | } | |
974 | } | |
975 | return false; | |
976 | } | |
977 | ||
445282db DA |
978 | bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, |
979 | struct radeon_encoder_int_tmds *tmds) | |
771fe6b9 JG |
980 | { |
981 | struct drm_device *dev = encoder->base.dev; | |
982 | struct radeon_device *rdev = dev->dev_private; | |
983 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
984 | int index = GetIndexIntoMasterTable(DATA, TMDS_Info); | |
985 | uint16_t data_offset; | |
986 | struct _ATOM_TMDS_INFO *tmds_info; | |
987 | uint8_t frev, crev; | |
988 | uint16_t maxfreq; | |
989 | int i; | |
771fe6b9 JG |
990 | |
991 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, | |
992 | &crev, &data_offset); | |
993 | ||
994 | tmds_info = | |
995 | (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + | |
996 | data_offset); | |
997 | ||
998 | if (tmds_info) { | |
771fe6b9 JG |
999 | maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); |
1000 | for (i = 0; i < 4; i++) { | |
1001 | tmds->tmds_pll[i].freq = | |
1002 | le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); | |
1003 | tmds->tmds_pll[i].value = | |
1004 | tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; | |
1005 | tmds->tmds_pll[i].value |= | |
1006 | (tmds_info->asMiscInfo[i]. | |
1007 | ucPLL_VCO_Gain & 0x3f) << 6; | |
1008 | tmds->tmds_pll[i].value |= | |
1009 | (tmds_info->asMiscInfo[i]. | |
1010 | ucPLL_DutyCycle & 0xf) << 12; | |
1011 | tmds->tmds_pll[i].value |= | |
1012 | (tmds_info->asMiscInfo[i]. | |
1013 | ucPLL_VoltageSwing & 0xf) << 16; | |
1014 | ||
1015 | DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n", | |
1016 | tmds->tmds_pll[i].freq, | |
1017 | tmds->tmds_pll[i].value); | |
1018 | ||
1019 | if (maxfreq == tmds->tmds_pll[i].freq) { | |
1020 | tmds->tmds_pll[i].freq = 0xffffffff; | |
1021 | break; | |
1022 | } | |
1023 | } | |
445282db | 1024 | return true; |
771fe6b9 | 1025 | } |
445282db | 1026 | return false; |
771fe6b9 JG |
1027 | } |
1028 | ||
ebbe1cb9 AD |
1029 | static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct |
1030 | radeon_encoder | |
1031 | *encoder, | |
1032 | int id) | |
1033 | { | |
1034 | struct drm_device *dev = encoder->base.dev; | |
1035 | struct radeon_device *rdev = dev->dev_private; | |
1036 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1037 | int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); | |
1038 | uint16_t data_offset; | |
1039 | struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; | |
1040 | uint8_t frev, crev; | |
1041 | struct radeon_atom_ss *ss = NULL; | |
279b215e | 1042 | int i; |
ebbe1cb9 AD |
1043 | |
1044 | if (id > ATOM_MAX_SS_ENTRY) | |
1045 | return NULL; | |
1046 | ||
1047 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, | |
1048 | &crev, &data_offset); | |
1049 | ||
1050 | ss_info = | |
1051 | (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); | |
1052 | ||
1053 | if (ss_info) { | |
1054 | ss = | |
1055 | kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL); | |
1056 | ||
1057 | if (!ss) | |
1058 | return NULL; | |
1059 | ||
279b215e AD |
1060 | for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) { |
1061 | if (ss_info->asSS_Info[i].ucSS_Id == id) { | |
1062 | ss->percentage = | |
1063 | le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage); | |
1064 | ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType; | |
1065 | ss->step = ss_info->asSS_Info[i].ucSS_Step; | |
1066 | ss->delay = ss_info->asSS_Info[i].ucSS_Delay; | |
1067 | ss->range = ss_info->asSS_Info[i].ucSS_Range; | |
1068 | ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div; | |
1d3d51b6 | 1069 | break; |
279b215e AD |
1070 | } |
1071 | } | |
ebbe1cb9 AD |
1072 | } |
1073 | return ss; | |
1074 | } | |
1075 | ||
09397278 AD |
1076 | static void radeon_atom_apply_lvds_quirks(struct drm_device *dev, |
1077 | struct radeon_encoder_atom_dig *lvds) | |
1078 | { | |
1079 | ||
1080 | /* Toshiba A300-1BU laptop panel doesn't like new pll divider algo */ | |
1081 | if ((dev->pdev->device == 0x95c4) && | |
1082 | (dev->pdev->subsystem_vendor == 0x1179) && | |
1083 | (dev->pdev->subsystem_device == 0xff50)) { | |
1084 | if ((lvds->native_mode.hdisplay == 1280) && | |
1085 | (lvds->native_mode.vdisplay == 800)) | |
1086 | lvds->pll_algo = PLL_ALGO_LEGACY; | |
1087 | } | |
1088 | ||
1089 | } | |
1090 | ||
771fe6b9 JG |
1091 | union lvds_info { |
1092 | struct _ATOM_LVDS_INFO info; | |
1093 | struct _ATOM_LVDS_INFO_V12 info_12; | |
1094 | }; | |
1095 | ||
1096 | struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct | |
1097 | radeon_encoder | |
1098 | *encoder) | |
1099 | { | |
1100 | struct drm_device *dev = encoder->base.dev; | |
1101 | struct radeon_device *rdev = dev->dev_private; | |
1102 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1103 | int index = GetIndexIntoMasterTable(DATA, LVDS_Info); | |
7dde8a19 | 1104 | uint16_t data_offset, misc; |
771fe6b9 JG |
1105 | union lvds_info *lvds_info; |
1106 | uint8_t frev, crev; | |
1107 | struct radeon_encoder_atom_dig *lvds = NULL; | |
1108 | ||
1109 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, | |
1110 | &crev, &data_offset); | |
1111 | ||
1112 | lvds_info = | |
1113 | (union lvds_info *)(mode_info->atom_context->bios + data_offset); | |
1114 | ||
1115 | if (lvds_info) { | |
1116 | lvds = | |
1117 | kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); | |
1118 | ||
1119 | if (!lvds) | |
1120 | return NULL; | |
1121 | ||
de2103e4 | 1122 | lvds->native_mode.clock = |
771fe6b9 | 1123 | le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; |
de2103e4 | 1124 | lvds->native_mode.hdisplay = |
771fe6b9 | 1125 | le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); |
de2103e4 | 1126 | lvds->native_mode.vdisplay = |
771fe6b9 | 1127 | le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); |
de2103e4 AD |
1128 | lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
1129 | le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); | |
1130 | lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + | |
1131 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); | |
1132 | lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + | |
1133 | le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); | |
1134 | lvds->native_mode.vtotal = lvds->native_mode.vdisplay + | |
1135 | le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); | |
1136 | lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + | |
1137 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); | |
1138 | lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + | |
1139 | le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); | |
771fe6b9 JG |
1140 | lvds->panel_pwr_delay = |
1141 | le16_to_cpu(lvds_info->info.usOffDelayInMs); | |
1142 | lvds->lvds_misc = lvds_info->info.ucLVDS_Misc; | |
7dde8a19 AD |
1143 | |
1144 | misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); | |
1145 | if (misc & ATOM_VSYNC_POLARITY) | |
1146 | lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
1147 | if (misc & ATOM_HSYNC_POLARITY) | |
1148 | lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
1149 | if (misc & ATOM_COMPOSITESYNC) | |
1150 | lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; | |
1151 | if (misc & ATOM_INTERLACE) | |
1152 | lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
1153 | if (misc & ATOM_DOUBLE_CLOCK_MODE) | |
1154 | lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; | |
1155 | ||
de2103e4 AD |
1156 | /* set crtc values */ |
1157 | drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); | |
771fe6b9 | 1158 | |
ebbe1cb9 AD |
1159 | lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id); |
1160 | ||
7c27f87d AD |
1161 | if (ASIC_IS_AVIVO(rdev)) { |
1162 | if (radeon_new_pll) | |
1163 | lvds->pll_algo = PLL_ALGO_AVIVO; | |
1164 | else | |
1165 | lvds->pll_algo = PLL_ALGO_LEGACY; | |
1166 | } else | |
1167 | lvds->pll_algo = PLL_ALGO_LEGACY; | |
1168 | ||
09397278 AD |
1169 | /* LVDS quirks */ |
1170 | radeon_atom_apply_lvds_quirks(dev, lvds); | |
1171 | ||
771fe6b9 JG |
1172 | encoder->native_mode = lvds->native_mode; |
1173 | } | |
1174 | return lvds; | |
1175 | } | |
1176 | ||
6fe7ac3f AD |
1177 | struct radeon_encoder_primary_dac * |
1178 | radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) | |
1179 | { | |
1180 | struct drm_device *dev = encoder->base.dev; | |
1181 | struct radeon_device *rdev = dev->dev_private; | |
1182 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1183 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); | |
1184 | uint16_t data_offset; | |
1185 | struct _COMPASSIONATE_DATA *dac_info; | |
1186 | uint8_t frev, crev; | |
1187 | uint8_t bg, dac; | |
6fe7ac3f AD |
1188 | struct radeon_encoder_primary_dac *p_dac = NULL; |
1189 | ||
1190 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); | |
1191 | ||
1192 | dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); | |
1193 | ||
1194 | if (dac_info) { | |
1195 | p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); | |
1196 | ||
1197 | if (!p_dac) | |
1198 | return NULL; | |
1199 | ||
1200 | bg = dac_info->ucDAC1_BG_Adjustment; | |
1201 | dac = dac_info->ucDAC1_DAC_Adjustment; | |
1202 | p_dac->ps2_pdac_adj = (bg << 8) | (dac); | |
1203 | ||
1204 | } | |
1205 | return p_dac; | |
1206 | } | |
1207 | ||
4ce001ab | 1208 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
5a9bcacc | 1209 | struct drm_display_mode *mode) |
4ce001ab DA |
1210 | { |
1211 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1212 | ATOM_ANALOG_TV_INFO *tv_info; | |
1213 | ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; | |
1214 | ATOM_DTD_FORMAT *dtd_timings; | |
1215 | int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); | |
1216 | u8 frev, crev; | |
5a9bcacc | 1217 | u16 data_offset, misc; |
4ce001ab DA |
1218 | |
1219 | atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset); | |
1220 | ||
1221 | switch (crev) { | |
1222 | case 1: | |
1223 | tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); | |
1224 | if (index > MAX_SUPPORTED_TV_TIMING) | |
1225 | return false; | |
1226 | ||
5a9bcacc AD |
1227 | mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); |
1228 | mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); | |
1229 | mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); | |
1230 | mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + | |
1231 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); | |
1232 | ||
1233 | mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); | |
1234 | mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); | |
1235 | mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); | |
1236 | mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + | |
1237 | le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); | |
1238 | ||
1239 | mode->flags = 0; | |
1240 | misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); | |
1241 | if (misc & ATOM_VSYNC_POLARITY) | |
1242 | mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
1243 | if (misc & ATOM_HSYNC_POLARITY) | |
1244 | mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
1245 | if (misc & ATOM_COMPOSITESYNC) | |
1246 | mode->flags |= DRM_MODE_FLAG_CSYNC; | |
1247 | if (misc & ATOM_INTERLACE) | |
1248 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
1249 | if (misc & ATOM_DOUBLE_CLOCK_MODE) | |
1250 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; | |
1251 | ||
1252 | mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; | |
4ce001ab DA |
1253 | |
1254 | if (index == 1) { | |
1255 | /* PAL timings appear to have wrong values for totals */ | |
5a9bcacc AD |
1256 | mode->crtc_htotal -= 1; |
1257 | mode->crtc_vtotal -= 1; | |
4ce001ab DA |
1258 | } |
1259 | break; | |
1260 | case 2: | |
1261 | tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); | |
1262 | if (index > MAX_SUPPORTED_TV_TIMING_V1_2) | |
1263 | return false; | |
1264 | ||
1265 | dtd_timings = &tv_info_v1_2->aModeTimings[index]; | |
5a9bcacc AD |
1266 | mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + |
1267 | le16_to_cpu(dtd_timings->usHBlanking_Time); | |
1268 | mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); | |
1269 | mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + | |
1270 | le16_to_cpu(dtd_timings->usHSyncOffset); | |
1271 | mode->crtc_hsync_end = mode->crtc_hsync_start + | |
1272 | le16_to_cpu(dtd_timings->usHSyncWidth); | |
1273 | ||
1274 | mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + | |
1275 | le16_to_cpu(dtd_timings->usVBlanking_Time); | |
1276 | mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); | |
1277 | mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + | |
1278 | le16_to_cpu(dtd_timings->usVSyncOffset); | |
1279 | mode->crtc_vsync_end = mode->crtc_vsync_start + | |
1280 | le16_to_cpu(dtd_timings->usVSyncWidth); | |
1281 | ||
1282 | mode->flags = 0; | |
1283 | misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); | |
1284 | if (misc & ATOM_VSYNC_POLARITY) | |
1285 | mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
1286 | if (misc & ATOM_HSYNC_POLARITY) | |
1287 | mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
1288 | if (misc & ATOM_COMPOSITESYNC) | |
1289 | mode->flags |= DRM_MODE_FLAG_CSYNC; | |
1290 | if (misc & ATOM_INTERLACE) | |
1291 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
1292 | if (misc & ATOM_DOUBLE_CLOCK_MODE) | |
1293 | mode->flags |= DRM_MODE_FLAG_DBLSCAN; | |
1294 | ||
1295 | mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10; | |
4ce001ab DA |
1296 | break; |
1297 | } | |
1298 | return true; | |
1299 | } | |
1300 | ||
d79766fa AD |
1301 | enum radeon_tv_std |
1302 | radeon_atombios_get_tv_info(struct radeon_device *rdev) | |
1303 | { | |
1304 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1305 | int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); | |
1306 | uint16_t data_offset; | |
1307 | uint8_t frev, crev; | |
1308 | struct _ATOM_ANALOG_TV_INFO *tv_info; | |
1309 | enum radeon_tv_std tv_std = TV_STD_NTSC; | |
1310 | ||
1311 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); | |
1312 | ||
1313 | tv_info = (struct _ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); | |
1314 | ||
1315 | switch (tv_info->ucTV_BootUpDefaultStandard) { | |
1316 | case ATOM_TV_NTSC: | |
1317 | tv_std = TV_STD_NTSC; | |
1318 | DRM_INFO("Default TV standard: NTSC\n"); | |
1319 | break; | |
1320 | case ATOM_TV_NTSCJ: | |
1321 | tv_std = TV_STD_NTSC_J; | |
1322 | DRM_INFO("Default TV standard: NTSC-J\n"); | |
1323 | break; | |
1324 | case ATOM_TV_PAL: | |
1325 | tv_std = TV_STD_PAL; | |
1326 | DRM_INFO("Default TV standard: PAL\n"); | |
1327 | break; | |
1328 | case ATOM_TV_PALM: | |
1329 | tv_std = TV_STD_PAL_M; | |
1330 | DRM_INFO("Default TV standard: PAL-M\n"); | |
1331 | break; | |
1332 | case ATOM_TV_PALN: | |
1333 | tv_std = TV_STD_PAL_N; | |
1334 | DRM_INFO("Default TV standard: PAL-N\n"); | |
1335 | break; | |
1336 | case ATOM_TV_PALCN: | |
1337 | tv_std = TV_STD_PAL_CN; | |
1338 | DRM_INFO("Default TV standard: PAL-CN\n"); | |
1339 | break; | |
1340 | case ATOM_TV_PAL60: | |
1341 | tv_std = TV_STD_PAL_60; | |
1342 | DRM_INFO("Default TV standard: PAL-60\n"); | |
1343 | break; | |
1344 | case ATOM_TV_SECAM: | |
1345 | tv_std = TV_STD_SECAM; | |
1346 | DRM_INFO("Default TV standard: SECAM\n"); | |
1347 | break; | |
1348 | default: | |
1349 | tv_std = TV_STD_NTSC; | |
1350 | DRM_INFO("Unknown TV standard; defaulting to NTSC\n"); | |
1351 | break; | |
1352 | } | |
1353 | return tv_std; | |
1354 | } | |
1355 | ||
6fe7ac3f AD |
1356 | struct radeon_encoder_tv_dac * |
1357 | radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) | |
1358 | { | |
1359 | struct drm_device *dev = encoder->base.dev; | |
1360 | struct radeon_device *rdev = dev->dev_private; | |
1361 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1362 | int index = GetIndexIntoMasterTable(DATA, CompassionateData); | |
1363 | uint16_t data_offset; | |
1364 | struct _COMPASSIONATE_DATA *dac_info; | |
1365 | uint8_t frev, crev; | |
1366 | uint8_t bg, dac; | |
6fe7ac3f AD |
1367 | struct radeon_encoder_tv_dac *tv_dac = NULL; |
1368 | ||
1369 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); | |
1370 | ||
1371 | dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); | |
1372 | ||
1373 | if (dac_info) { | |
1374 | tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); | |
1375 | ||
1376 | if (!tv_dac) | |
1377 | return NULL; | |
1378 | ||
1379 | bg = dac_info->ucDAC2_CRT2_BG_Adjustment; | |
1380 | dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; | |
1381 | tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); | |
1382 | ||
1383 | bg = dac_info->ucDAC2_PAL_BG_Adjustment; | |
1384 | dac = dac_info->ucDAC2_PAL_DAC_Adjustment; | |
1385 | tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); | |
1386 | ||
1387 | bg = dac_info->ucDAC2_NTSC_BG_Adjustment; | |
1388 | dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; | |
1389 | tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); | |
1390 | ||
d79766fa | 1391 | tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); |
6fe7ac3f AD |
1392 | } |
1393 | return tv_dac; | |
1394 | } | |
1395 | ||
56278a8e AD |
1396 | union power_info { |
1397 | struct _ATOM_POWERPLAY_INFO info; | |
1398 | struct _ATOM_POWERPLAY_INFO_V2 info_2; | |
1399 | struct _ATOM_POWERPLAY_INFO_V3 info_3; | |
1400 | struct _ATOM_PPLIB_POWERPLAYTABLE info_4; | |
1401 | }; | |
1402 | ||
1403 | void radeon_atombios_get_power_modes(struct radeon_device *rdev) | |
1404 | { | |
1405 | struct radeon_mode_info *mode_info = &rdev->mode_info; | |
1406 | int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); | |
1407 | u16 data_offset; | |
1408 | u8 frev, crev; | |
1409 | u32 misc, misc2 = 0, sclk, mclk; | |
1410 | union power_info *power_info; | |
1411 | struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; | |
1412 | struct _ATOM_PPLIB_STATE *power_state; | |
1413 | int num_modes = 0, i, j; | |
1414 | int state_index = 0, mode_index = 0; | |
1415 | ||
1416 | atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); | |
1417 | ||
1418 | power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); | |
1419 | ||
1420 | rdev->pm.default_power_state = NULL; | |
1421 | rdev->pm.current_power_state = NULL; | |
1422 | ||
1423 | if (power_info) { | |
1424 | if (frev < 4) { | |
1425 | num_modes = power_info->info.ucNumOfPowerModeEntries; | |
1426 | if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) | |
1427 | num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; | |
1428 | for (i = 0; i < num_modes; i++) { | |
1429 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; | |
1430 | switch (frev) { | |
1431 | case 1: | |
1432 | rdev->pm.power_state[state_index].num_clock_modes = 1; | |
1433 | rdev->pm.power_state[state_index].clock_info[0].mclk = | |
1434 | le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); | |
1435 | rdev->pm.power_state[state_index].clock_info[0].sclk = | |
1436 | le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); | |
1437 | /* skip invalid modes */ | |
1438 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | |
1439 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | |
1440 | continue; | |
1441 | /* skip overclock modes for now */ | |
1442 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk > | |
1443 | rdev->clock.default_mclk) || | |
1444 | (rdev->pm.power_state[state_index].clock_info[0].sclk > | |
1445 | rdev->clock.default_sclk)) | |
1446 | continue; | |
1447 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = | |
1448 | power_info->info.asPowerPlayInfo[i].ucNumPciELanes; | |
1449 | misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); | |
1450 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { | |
1451 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
1452 | VOLTAGE_GPIO; | |
1453 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = | |
1454 | radeon_lookup_gpio(rdev, | |
1455 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); | |
1456 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) | |
1457 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1458 | true; | |
1459 | else | |
1460 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1461 | false; | |
1462 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { | |
1463 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
1464 | VOLTAGE_VDDC; | |
1465 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = | |
1466 | power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; | |
1467 | } | |
1468 | if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { | |
1469 | rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; | |
1470 | rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; | |
1471 | rdev->pm.power_state[state_index].default_clock_mode = | |
1472 | &rdev->pm.power_state[state_index].clock_info[0]; | |
1473 | rdev->pm.power_state[state_index].current_clock_mode = | |
1474 | &rdev->pm.power_state[state_index].clock_info[0]; | |
1475 | } | |
1476 | state_index++; | |
1477 | break; | |
1478 | case 2: | |
1479 | rdev->pm.power_state[state_index].num_clock_modes = 1; | |
1480 | rdev->pm.power_state[state_index].clock_info[0].mclk = | |
1481 | le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); | |
1482 | rdev->pm.power_state[state_index].clock_info[0].sclk = | |
1483 | le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); | |
1484 | /* skip invalid modes */ | |
1485 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | |
1486 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | |
1487 | continue; | |
1488 | /* skip overclock modes for now */ | |
1489 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk > | |
1490 | rdev->clock.default_mclk) || | |
1491 | (rdev->pm.power_state[state_index].clock_info[0].sclk > | |
1492 | rdev->clock.default_sclk)) | |
1493 | continue; | |
1494 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = | |
1495 | power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; | |
1496 | misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); | |
1497 | misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); | |
1498 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { | |
1499 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
1500 | VOLTAGE_GPIO; | |
1501 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = | |
1502 | radeon_lookup_gpio(rdev, | |
1503 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); | |
1504 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) | |
1505 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1506 | true; | |
1507 | else | |
1508 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1509 | false; | |
1510 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { | |
1511 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
1512 | VOLTAGE_VDDC; | |
1513 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = | |
1514 | power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; | |
1515 | } | |
1516 | if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { | |
1517 | rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; | |
1518 | rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; | |
1519 | rdev->pm.power_state[state_index].default_clock_mode = | |
1520 | &rdev->pm.power_state[state_index].clock_info[0]; | |
1521 | rdev->pm.power_state[state_index].current_clock_mode = | |
1522 | &rdev->pm.power_state[state_index].clock_info[0]; | |
1523 | } | |
1524 | state_index++; | |
1525 | break; | |
1526 | case 3: | |
1527 | rdev->pm.power_state[state_index].num_clock_modes = 1; | |
1528 | rdev->pm.power_state[state_index].clock_info[0].mclk = | |
1529 | le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); | |
1530 | rdev->pm.power_state[state_index].clock_info[0].sclk = | |
1531 | le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); | |
1532 | /* skip invalid modes */ | |
1533 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || | |
1534 | (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) | |
1535 | continue; | |
1536 | /* skip overclock modes for now */ | |
1537 | if ((rdev->pm.power_state[state_index].clock_info[0].mclk > | |
1538 | rdev->clock.default_mclk) || | |
1539 | (rdev->pm.power_state[state_index].clock_info[0].sclk > | |
1540 | rdev->clock.default_sclk)) | |
1541 | continue; | |
1542 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = | |
1543 | power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; | |
1544 | misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); | |
1545 | misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); | |
1546 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { | |
1547 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
1548 | VOLTAGE_GPIO; | |
1549 | rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = | |
1550 | radeon_lookup_gpio(rdev, | |
1551 | power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); | |
1552 | if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) | |
1553 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1554 | true; | |
1555 | else | |
1556 | rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = | |
1557 | false; | |
1558 | } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { | |
1559 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = | |
1560 | VOLTAGE_VDDC; | |
1561 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = | |
1562 | power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; | |
1563 | if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { | |
1564 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = | |
1565 | true; | |
1566 | rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = | |
1567 | power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; | |
1568 | } | |
1569 | } | |
1570 | if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { | |
1571 | rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; | |
1572 | rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; | |
1573 | rdev->pm.power_state[state_index].default_clock_mode = | |
1574 | &rdev->pm.power_state[state_index].clock_info[0]; | |
1575 | rdev->pm.power_state[state_index].current_clock_mode = | |
1576 | &rdev->pm.power_state[state_index].clock_info[0]; | |
1577 | } | |
1578 | state_index++; | |
1579 | break; | |
1580 | } | |
1581 | } | |
1582 | } else if (frev == 4) { | |
1583 | for (i = 0; i < power_info->info_4.ucNumStates; i++) { | |
1584 | mode_index = 0; | |
1585 | power_state = (struct _ATOM_PPLIB_STATE *) | |
1586 | (mode_info->atom_context->bios + | |
1587 | data_offset + | |
1588 | le16_to_cpu(power_info->info_4.usStateArrayOffset) + | |
1589 | i * power_info->info_4.ucStateEntrySize); | |
1590 | non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) | |
1591 | (mode_info->atom_context->bios + | |
1592 | data_offset + | |
1593 | le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) + | |
1594 | (power_state->ucNonClockStateIndex * | |
1595 | power_info->info_4.ucNonClockSize)); | |
1596 | misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); | |
1597 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = | |
1598 | ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> | |
1599 | ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; | |
1600 | for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) { | |
1601 | if (rdev->flags & RADEON_IS_IGP) { | |
1602 | struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info = | |
1603 | (struct _ATOM_PPLIB_RS780_CLOCK_INFO *) | |
1604 | (mode_info->atom_context->bios + | |
1605 | data_offset + | |
1606 | le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) + | |
1607 | (power_state->ucClockStateIndices[j] * | |
1608 | power_info->info_4.ucClockInfoSize)); | |
1609 | sclk = le16_to_cpu(clock_info->usLowEngineClockLow); | |
1610 | sclk |= clock_info->ucLowEngineClockHigh << 16; | |
1611 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; | |
1612 | /* skip invalid modes */ | |
1613 | if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) | |
1614 | continue; | |
1615 | /* skip overclock modes for now */ | |
1616 | if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk > | |
1617 | rdev->clock.default_sclk) | |
1618 | continue; | |
1619 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = | |
1620 | VOLTAGE_SW; | |
1621 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = | |
1622 | clock_info->usVDDC; | |
1623 | mode_index++; | |
1624 | } else { | |
1625 | struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info = | |
1626 | (struct _ATOM_PPLIB_R600_CLOCK_INFO *) | |
1627 | (mode_info->atom_context->bios + | |
1628 | data_offset + | |
1629 | le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) + | |
1630 | (power_state->ucClockStateIndices[j] * | |
1631 | power_info->info_4.ucClockInfoSize)); | |
1632 | sclk = le16_to_cpu(clock_info->usEngineClockLow); | |
1633 | sclk |= clock_info->ucEngineClockHigh << 16; | |
1634 | mclk = le16_to_cpu(clock_info->usMemoryClockLow); | |
1635 | mclk |= clock_info->ucMemoryClockHigh << 16; | |
1636 | rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; | |
1637 | rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; | |
1638 | /* skip invalid modes */ | |
1639 | if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || | |
1640 | (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) | |
1641 | continue; | |
1642 | /* skip overclock modes for now */ | |
1643 | if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk > | |
1644 | rdev->clock.default_mclk) || | |
1645 | (rdev->pm.power_state[state_index].clock_info[mode_index].sclk > | |
1646 | rdev->clock.default_sclk)) | |
1647 | continue; | |
1648 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = | |
1649 | VOLTAGE_SW; | |
1650 | rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = | |
1651 | clock_info->usVDDC; | |
1652 | mode_index++; | |
1653 | } | |
1654 | } | |
1655 | rdev->pm.power_state[state_index].num_clock_modes = mode_index; | |
1656 | if (mode_index) { | |
1657 | misc2 = le16_to_cpu(non_clock_info->usClassification); | |
1658 | if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { | |
1659 | rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; | |
1660 | rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; | |
1661 | rdev->pm.power_state[state_index].default_clock_mode = | |
1662 | &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; | |
1663 | rdev->pm.power_state[state_index].current_clock_mode = | |
1664 | &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; | |
1665 | } | |
1666 | state_index++; | |
1667 | } | |
1668 | } | |
1669 | } | |
1670 | } else { | |
1671 | /* XXX figure out some good default low power mode for cards w/out power tables */ | |
1672 | } | |
1673 | ||
1674 | if (rdev->pm.default_power_state == NULL) { | |
1675 | /* add the default mode */ | |
1676 | rdev->pm.power_state[state_index].num_clock_modes = 1; | |
1677 | rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; | |
1678 | rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; | |
1679 | rdev->pm.power_state[state_index].default_clock_mode = | |
1680 | &rdev->pm.power_state[state_index].clock_info[0]; | |
1681 | rdev->pm.power_state[state_index].current_clock_mode = | |
1682 | &rdev->pm.power_state[state_index].clock_info[0]; | |
1683 | rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; | |
1684 | if (rdev->asic->get_pcie_lanes) | |
1685 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); | |
1686 | else | |
1687 | rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; | |
1688 | rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; | |
1689 | rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; | |
1690 | state_index++; | |
1691 | } | |
1692 | rdev->pm.num_power_states = state_index; | |
1693 | } | |
1694 | ||
771fe6b9 JG |
1695 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) |
1696 | { | |
1697 | DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; | |
1698 | int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); | |
1699 | ||
1700 | args.ucEnable = enable; | |
1701 | ||
1702 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1703 | } | |
1704 | ||
1705 | void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable) | |
1706 | { | |
1707 | ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args; | |
1708 | int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt); | |
1709 | ||
1710 | args.ucEnable = enable; | |
1711 | ||
1712 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1713 | } | |
1714 | ||
7433874e RM |
1715 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) |
1716 | { | |
1717 | GET_ENGINE_CLOCK_PS_ALLOCATION args; | |
1718 | int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); | |
1719 | ||
1720 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1721 | return args.ulReturnEngineClock; | |
1722 | } | |
1723 | ||
1724 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) | |
1725 | { | |
1726 | GET_MEMORY_CLOCK_PS_ALLOCATION args; | |
1727 | int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); | |
1728 | ||
1729 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1730 | return args.ulReturnMemoryClock; | |
1731 | } | |
1732 | ||
771fe6b9 JG |
1733 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, |
1734 | uint32_t eng_clock) | |
1735 | { | |
1736 | SET_ENGINE_CLOCK_PS_ALLOCATION args; | |
1737 | int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); | |
1738 | ||
1739 | args.ulTargetEngineClock = eng_clock; /* 10 khz */ | |
1740 | ||
1741 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1742 | } | |
1743 | ||
1744 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, | |
1745 | uint32_t mem_clock) | |
1746 | { | |
1747 | SET_MEMORY_CLOCK_PS_ALLOCATION args; | |
1748 | int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); | |
1749 | ||
1750 | if (rdev->flags & RADEON_IS_IGP) | |
1751 | return; | |
1752 | ||
1753 | args.ulTargetMemoryClock = mem_clock; /* 10 khz */ | |
1754 | ||
1755 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); | |
1756 | } | |
1757 | ||
1758 | void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) | |
1759 | { | |
1760 | struct radeon_device *rdev = dev->dev_private; | |
1761 | uint32_t bios_2_scratch, bios_6_scratch; | |
1762 | ||
1763 | if (rdev->family >= CHIP_R600) { | |
4ce001ab | 1764 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
771fe6b9 JG |
1765 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
1766 | } else { | |
4ce001ab | 1767 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
771fe6b9 JG |
1768 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
1769 | } | |
1770 | ||
1771 | /* let the bios control the backlight */ | |
1772 | bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; | |
1773 | ||
1774 | /* tell the bios not to handle mode switching */ | |
1775 | bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE); | |
1776 | ||
1777 | if (rdev->family >= CHIP_R600) { | |
1778 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); | |
1779 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); | |
1780 | } else { | |
1781 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); | |
1782 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
1783 | } | |
1784 | ||
1785 | } | |
1786 | ||
f657c2a7 YZ |
1787 | void radeon_save_bios_scratch_regs(struct radeon_device *rdev) |
1788 | { | |
1789 | uint32_t scratch_reg; | |
1790 | int i; | |
1791 | ||
1792 | if (rdev->family >= CHIP_R600) | |
1793 | scratch_reg = R600_BIOS_0_SCRATCH; | |
1794 | else | |
1795 | scratch_reg = RADEON_BIOS_0_SCRATCH; | |
1796 | ||
1797 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) | |
1798 | rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); | |
1799 | } | |
1800 | ||
1801 | void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) | |
1802 | { | |
1803 | uint32_t scratch_reg; | |
1804 | int i; | |
1805 | ||
1806 | if (rdev->family >= CHIP_R600) | |
1807 | scratch_reg = R600_BIOS_0_SCRATCH; | |
1808 | else | |
1809 | scratch_reg = RADEON_BIOS_0_SCRATCH; | |
1810 | ||
1811 | for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) | |
1812 | WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); | |
1813 | } | |
1814 | ||
771fe6b9 JG |
1815 | void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) |
1816 | { | |
1817 | struct drm_device *dev = encoder->dev; | |
1818 | struct radeon_device *rdev = dev->dev_private; | |
1819 | uint32_t bios_6_scratch; | |
1820 | ||
1821 | if (rdev->family >= CHIP_R600) | |
1822 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); | |
1823 | else | |
1824 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); | |
1825 | ||
1826 | if (lock) | |
1827 | bios_6_scratch |= ATOM_S6_CRITICAL_STATE; | |
1828 | else | |
1829 | bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; | |
1830 | ||
1831 | if (rdev->family >= CHIP_R600) | |
1832 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); | |
1833 | else | |
1834 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
1835 | } | |
1836 | ||
1837 | /* at some point we may want to break this out into individual functions */ | |
1838 | void | |
1839 | radeon_atombios_connected_scratch_regs(struct drm_connector *connector, | |
1840 | struct drm_encoder *encoder, | |
1841 | bool connected) | |
1842 | { | |
1843 | struct drm_device *dev = connector->dev; | |
1844 | struct radeon_device *rdev = dev->dev_private; | |
1845 | struct radeon_connector *radeon_connector = | |
1846 | to_radeon_connector(connector); | |
1847 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
1848 | uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; | |
1849 | ||
1850 | if (rdev->family >= CHIP_R600) { | |
1851 | bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); | |
1852 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); | |
1853 | bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); | |
1854 | } else { | |
1855 | bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); | |
1856 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); | |
1857 | bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); | |
1858 | } | |
1859 | ||
1860 | if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && | |
1861 | (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { | |
1862 | if (connected) { | |
1863 | DRM_DEBUG("TV1 connected\n"); | |
1864 | bios_3_scratch |= ATOM_S3_TV1_ACTIVE; | |
1865 | bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; | |
1866 | } else { | |
1867 | DRM_DEBUG("TV1 disconnected\n"); | |
1868 | bios_0_scratch &= ~ATOM_S0_TV1_MASK; | |
1869 | bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; | |
1870 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; | |
1871 | } | |
1872 | } | |
1873 | if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && | |
1874 | (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { | |
1875 | if (connected) { | |
1876 | DRM_DEBUG("CV connected\n"); | |
1877 | bios_3_scratch |= ATOM_S3_CV_ACTIVE; | |
1878 | bios_6_scratch |= ATOM_S6_ACC_REQ_CV; | |
1879 | } else { | |
1880 | DRM_DEBUG("CV disconnected\n"); | |
1881 | bios_0_scratch &= ~ATOM_S0_CV_MASK; | |
1882 | bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; | |
1883 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; | |
1884 | } | |
1885 | } | |
1886 | if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && | |
1887 | (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { | |
1888 | if (connected) { | |
1889 | DRM_DEBUG("LCD1 connected\n"); | |
1890 | bios_0_scratch |= ATOM_S0_LCD1; | |
1891 | bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; | |
1892 | bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; | |
1893 | } else { | |
1894 | DRM_DEBUG("LCD1 disconnected\n"); | |
1895 | bios_0_scratch &= ~ATOM_S0_LCD1; | |
1896 | bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; | |
1897 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; | |
1898 | } | |
1899 | } | |
1900 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && | |
1901 | (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { | |
1902 | if (connected) { | |
1903 | DRM_DEBUG("CRT1 connected\n"); | |
1904 | bios_0_scratch |= ATOM_S0_CRT1_COLOR; | |
1905 | bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; | |
1906 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; | |
1907 | } else { | |
1908 | DRM_DEBUG("CRT1 disconnected\n"); | |
1909 | bios_0_scratch &= ~ATOM_S0_CRT1_MASK; | |
1910 | bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; | |
1911 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; | |
1912 | } | |
1913 | } | |
1914 | if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && | |
1915 | (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { | |
1916 | if (connected) { | |
1917 | DRM_DEBUG("CRT2 connected\n"); | |
1918 | bios_0_scratch |= ATOM_S0_CRT2_COLOR; | |
1919 | bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; | |
1920 | bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; | |
1921 | } else { | |
1922 | DRM_DEBUG("CRT2 disconnected\n"); | |
1923 | bios_0_scratch &= ~ATOM_S0_CRT2_MASK; | |
1924 | bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; | |
1925 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; | |
1926 | } | |
1927 | } | |
1928 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && | |
1929 | (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { | |
1930 | if (connected) { | |
1931 | DRM_DEBUG("DFP1 connected\n"); | |
1932 | bios_0_scratch |= ATOM_S0_DFP1; | |
1933 | bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; | |
1934 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; | |
1935 | } else { | |
1936 | DRM_DEBUG("DFP1 disconnected\n"); | |
1937 | bios_0_scratch &= ~ATOM_S0_DFP1; | |
1938 | bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; | |
1939 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; | |
1940 | } | |
1941 | } | |
1942 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && | |
1943 | (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { | |
1944 | if (connected) { | |
1945 | DRM_DEBUG("DFP2 connected\n"); | |
1946 | bios_0_scratch |= ATOM_S0_DFP2; | |
1947 | bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; | |
1948 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; | |
1949 | } else { | |
1950 | DRM_DEBUG("DFP2 disconnected\n"); | |
1951 | bios_0_scratch &= ~ATOM_S0_DFP2; | |
1952 | bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; | |
1953 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; | |
1954 | } | |
1955 | } | |
1956 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && | |
1957 | (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { | |
1958 | if (connected) { | |
1959 | DRM_DEBUG("DFP3 connected\n"); | |
1960 | bios_0_scratch |= ATOM_S0_DFP3; | |
1961 | bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; | |
1962 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; | |
1963 | } else { | |
1964 | DRM_DEBUG("DFP3 disconnected\n"); | |
1965 | bios_0_scratch &= ~ATOM_S0_DFP3; | |
1966 | bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; | |
1967 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; | |
1968 | } | |
1969 | } | |
1970 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && | |
1971 | (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { | |
1972 | if (connected) { | |
1973 | DRM_DEBUG("DFP4 connected\n"); | |
1974 | bios_0_scratch |= ATOM_S0_DFP4; | |
1975 | bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; | |
1976 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; | |
1977 | } else { | |
1978 | DRM_DEBUG("DFP4 disconnected\n"); | |
1979 | bios_0_scratch &= ~ATOM_S0_DFP4; | |
1980 | bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; | |
1981 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; | |
1982 | } | |
1983 | } | |
1984 | if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && | |
1985 | (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { | |
1986 | if (connected) { | |
1987 | DRM_DEBUG("DFP5 connected\n"); | |
1988 | bios_0_scratch |= ATOM_S0_DFP5; | |
1989 | bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; | |
1990 | bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; | |
1991 | } else { | |
1992 | DRM_DEBUG("DFP5 disconnected\n"); | |
1993 | bios_0_scratch &= ~ATOM_S0_DFP5; | |
1994 | bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; | |
1995 | bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; | |
1996 | } | |
1997 | } | |
1998 | ||
1999 | if (rdev->family >= CHIP_R600) { | |
2000 | WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); | |
2001 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); | |
2002 | WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); | |
2003 | } else { | |
2004 | WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); | |
2005 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); | |
2006 | WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); | |
2007 | } | |
2008 | } | |
2009 | ||
2010 | void | |
2011 | radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) | |
2012 | { | |
2013 | struct drm_device *dev = encoder->dev; | |
2014 | struct radeon_device *rdev = dev->dev_private; | |
2015 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2016 | uint32_t bios_3_scratch; | |
2017 | ||
2018 | if (rdev->family >= CHIP_R600) | |
2019 | bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); | |
2020 | else | |
2021 | bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); | |
2022 | ||
2023 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
2024 | bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; | |
2025 | bios_3_scratch |= (crtc << 18); | |
2026 | } | |
2027 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { | |
2028 | bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; | |
2029 | bios_3_scratch |= (crtc << 24); | |
2030 | } | |
2031 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
2032 | bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; | |
2033 | bios_3_scratch |= (crtc << 16); | |
2034 | } | |
2035 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
2036 | bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; | |
2037 | bios_3_scratch |= (crtc << 20); | |
2038 | } | |
2039 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
2040 | bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; | |
2041 | bios_3_scratch |= (crtc << 17); | |
2042 | } | |
2043 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { | |
2044 | bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; | |
2045 | bios_3_scratch |= (crtc << 19); | |
2046 | } | |
2047 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { | |
2048 | bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; | |
2049 | bios_3_scratch |= (crtc << 23); | |
2050 | } | |
2051 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { | |
2052 | bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; | |
2053 | bios_3_scratch |= (crtc << 25); | |
2054 | } | |
2055 | ||
2056 | if (rdev->family >= CHIP_R600) | |
2057 | WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); | |
2058 | else | |
2059 | WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); | |
2060 | } | |
2061 | ||
2062 | void | |
2063 | radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) | |
2064 | { | |
2065 | struct drm_device *dev = encoder->dev; | |
2066 | struct radeon_device *rdev = dev->dev_private; | |
2067 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
2068 | uint32_t bios_2_scratch; | |
2069 | ||
2070 | if (rdev->family >= CHIP_R600) | |
2071 | bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); | |
2072 | else | |
2073 | bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); | |
2074 | ||
2075 | if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { | |
2076 | if (on) | |
2077 | bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; | |
2078 | else | |
2079 | bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; | |
2080 | } | |
2081 | if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { | |
2082 | if (on) | |
2083 | bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; | |
2084 | else | |
2085 | bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; | |
2086 | } | |
2087 | if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { | |
2088 | if (on) | |
2089 | bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; | |
2090 | else | |
2091 | bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; | |
2092 | } | |
2093 | if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { | |
2094 | if (on) | |
2095 | bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; | |
2096 | else | |
2097 | bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; | |
2098 | } | |
2099 | if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { | |
2100 | if (on) | |
2101 | bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; | |
2102 | else | |
2103 | bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; | |
2104 | } | |
2105 | if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { | |
2106 | if (on) | |
2107 | bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; | |
2108 | else | |
2109 | bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; | |
2110 | } | |
2111 | if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { | |
2112 | if (on) | |
2113 | bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; | |
2114 | else | |
2115 | bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; | |
2116 | } | |
2117 | if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { | |
2118 | if (on) | |
2119 | bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; | |
2120 | else | |
2121 | bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; | |
2122 | } | |
2123 | if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { | |
2124 | if (on) | |
2125 | bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; | |
2126 | else | |
2127 | bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; | |
2128 | } | |
2129 | if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { | |
2130 | if (on) | |
2131 | bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; | |
2132 | else | |
2133 | bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; | |
2134 | } | |
2135 | ||
2136 | if (rdev->family >= CHIP_R600) | |
2137 | WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); | |
2138 | else | |
2139 | WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); | |
2140 | } |