projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 771fe6b9 JG |
1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
| 3 | * Copyright 2008 Red Hat Inc. | |
| 4 | * Copyright 2009 Jerome Glisse. | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 7 | * copy of this software and associated documentation files (the "Software"), | |
| 8 | * to deal in the Software without restriction, including without limitation | |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 11 | * Software is furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 23 | * | |
| 24 | * Authors: Dave Airlie | |
| 25 | * Alex Deucher | |
| 26 | * Jerome Glisse | |
| 27 | */ | |
| 28 | #ifndef __RADEON_ASIC_H__ | |
| 29 | #define __RADEON_ASIC_H__ | |
| 30 | ||
| 31 | /* | |
| 32 | * common functions | |
| 33 | */ | |
| 7433874e | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 5ea597f3 | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
| 38 | ||
| 7433874e | 39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
| 771fe6b9 | 40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| 7433874e | 41 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
| 771fe6b9 JG |
42 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
| 43 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); | |
| 44 | ||
| 37e9b6a6 AD |
45 | void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); |
| 46 | void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); | |
| 47 | ||
| 48 | ||
| 771fe6b9 | 49 | /* |
| 44ca7478 | 50 | * r100,rv100,rs100,rv200,rs200 |
| 771fe6b9 | 51 | */ |
| 2b497502 DV |
52 | struct r100_mc_save { |
| 53 | u32 GENMO_WT; | |
| 54 | u32 CRTC_EXT_CNTL; | |
| 55 | u32 CRTC_GEN_CNTL; | |
| 56 | u32 CRTC2_GEN_CNTL; | |
| 57 | u32 CUR_OFFSET; | |
| 58 | u32 CUR2_OFFSET; | |
| 59 | }; | |
| 60 | int r100_init(struct radeon_device *rdev); | |
| 61 | void r100_fini(struct radeon_device *rdev); | |
| 62 | int r100_suspend(struct radeon_device *rdev); | |
| 63 | int r100_resume(struct radeon_device *rdev); | |
| 28d52043 | 64 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
| e32eb50d | 65 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| a2d07b74 | 66 | int r100_asic_reset(struct radeon_device *rdev); |
| 7ed220d7 | 67 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 JG |
68 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| 69 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| f712812e | 70 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| 771fe6b9 JG |
71 | int r100_irq_set(struct radeon_device *rdev); |
| 72 | int r100_irq_process(struct radeon_device *rdev); | |
| 73 | void r100_fence_ring_emit(struct radeon_device *rdev, | |
| 74 | struct radeon_fence *fence); | |
| 15d3332f | 75 | void r100_semaphore_ring_emit(struct radeon_device *rdev, |
| e32eb50d | 76 | struct radeon_ring *cp, |
| 15d3332f | 77 | struct radeon_semaphore *semaphore, |
| 7b1f2485 | 78 | bool emit_wait); |
| 771fe6b9 JG |
79 | int r100_cs_parse(struct radeon_cs_parser *p); |
| 80 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 81 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 82 | int r100_copy_blit(struct radeon_device *rdev, | |
| 83 | uint64_t src_offset, | |
| 84 | uint64_t dst_offset, | |
| 003cefe0 | 85 | unsigned num_gpu_pages, |
| 876dc9f3 | 86 | struct radeon_fence **fence); |
| e024e110 DA |
87 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
| 88 | uint32_t tiling_flags, uint32_t pitch, | |
| 89 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 90 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
| c93bb85b | 91 | void r100_bandwidth_update(struct radeon_device *rdev); |
| 3ce0a23d | 92 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| e32eb50d | 93 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 429770b3 AD |
94 | void r100_hpd_init(struct radeon_device *rdev); |
| 95 | void r100_hpd_fini(struct radeon_device *rdev); | |
| 96 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 97 | void r100_hpd_set_polarity(struct radeon_device *rdev, | |
| 98 | enum radeon_hpd_id hpd); | |
| 2b497502 DV |
99 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
| 100 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
| 101 | void r100_cp_disable(struct radeon_device *rdev); | |
| 102 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
| 103 | void r100_cp_fini(struct radeon_device *rdev); | |
| 104 | int r100_pci_gart_init(struct radeon_device *rdev); | |
| 105 | void r100_pci_gart_fini(struct radeon_device *rdev); | |
| 106 | int r100_pci_gart_enable(struct radeon_device *rdev); | |
| 107 | void r100_pci_gart_disable(struct radeon_device *rdev); | |
| 108 | int r100_debugfs_mc_info_init(struct radeon_device *rdev); | |
| 109 | int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
| f712812e | 110 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 2b497502 DV |
111 | void r100_irq_disable(struct radeon_device *rdev); |
| 112 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 113 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
| 114 | void r100_vram_init_sizes(struct radeon_device *rdev); | |
| 2b497502 DV |
115 | int r100_cp_reset(struct radeon_device *rdev); |
| 116 | void r100_vga_render_disable(struct radeon_device *rdev); | |
| 4c712e6c | 117 | void r100_restore_sanity(struct radeon_device *rdev); |
| 2b497502 DV |
118 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| 119 | struct radeon_cs_packet *pkt, | |
| 120 | struct radeon_bo *robj); | |
| 121 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |
| 122 | struct radeon_cs_packet *pkt, | |
| 123 | const unsigned *auth, unsigned n, | |
| 124 | radeon_packet0_check_t check); | |
| 125 | int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
| 126 | struct radeon_cs_packet *pkt, | |
| 127 | unsigned idx); | |
| 128 | void r100_enable_bm(struct radeon_device *rdev); | |
| 129 | void r100_set_common_regs(struct radeon_device *rdev); | |
| 90aca4d2 | 130 | void r100_bm_disable(struct radeon_device *rdev); |
| def9ba9c | 131 | extern bool r100_gui_idle(struct radeon_device *rdev); |
| 49e02b73 AD |
132 | extern void r100_pm_misc(struct radeon_device *rdev); |
| 133 | extern void r100_pm_prepare(struct radeon_device *rdev); | |
| 134 | extern void r100_pm_finish(struct radeon_device *rdev); | |
| ce8f5370 AD |
135 | extern void r100_pm_init_profile(struct radeon_device *rdev); |
| 136 | extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); | |
| 6f34be50 AD |
137 | extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 138 | extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 139 | extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); | |
| 3ae19b75 | 140 | extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 89e5181f | 141 | extern int r100_mc_wait_for_idle(struct radeon_device *rdev); |
| bae6b562 | 142 | |
| 44ca7478 PN |
143 | /* |
| 144 | * r200,rv250,rs300,rv280 | |
| 145 | */ | |
| 146 | extern int r200_copy_dma(struct radeon_device *rdev, | |
| 187f3da3 DV |
147 | uint64_t src_offset, |
| 148 | uint64_t dst_offset, | |
| 003cefe0 | 149 | unsigned num_gpu_pages, |
| 876dc9f3 | 150 | struct radeon_fence **fence); |
| 187f3da3 | 151 | void r200_set_safe_registers(struct radeon_device *rdev); |
| 771fe6b9 JG |
152 | |
| 153 | /* | |
| 154 | * r300,r350,rv350,rv380 | |
| 155 | */ | |
| 207bf9e9 JG |
156 | extern int r300_init(struct radeon_device *rdev); |
| 157 | extern void r300_fini(struct radeon_device *rdev); | |
| 158 | extern int r300_suspend(struct radeon_device *rdev); | |
| 159 | extern int r300_resume(struct radeon_device *rdev); | |
| a2d07b74 | 160 | extern int r300_asic_reset(struct radeon_device *rdev); |
| f712812e | 161 | extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| 207bf9e9 JG |
162 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
| 163 | struct radeon_fence *fence); | |
| 164 | extern int r300_cs_parse(struct radeon_cs_parser *p); | |
| 165 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 166 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 207bf9e9 | 167 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| c836a412 | 168 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
| 187f3da3 DV |
169 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
| 170 | extern void r300_mc_program(struct radeon_device *rdev); | |
| 171 | extern void r300_mc_init(struct radeon_device *rdev); | |
| 172 | extern void r300_clock_startup(struct radeon_device *rdev); | |
| 173 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
| 174 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); | |
| 175 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
| 176 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
| 177 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); | |
| 89e5181f | 178 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
| 44ca7478 | 179 | |
| 771fe6b9 JG |
180 | /* |
| 181 | * r420,r423,rv410 | |
| 182 | */ | |
| 9f022ddf JG |
183 | extern int r420_init(struct radeon_device *rdev); |
| 184 | extern void r420_fini(struct radeon_device *rdev); | |
| 185 | extern int r420_suspend(struct radeon_device *rdev); | |
| 186 | extern int r420_resume(struct radeon_device *rdev); | |
| ce8f5370 | 187 | extern void r420_pm_init_profile(struct radeon_device *rdev); |
| 187f3da3 DV |
188 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
| 189 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
| 190 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); | |
| 191 | extern void r420_pipes_init(struct radeon_device *rdev); | |
| 771fe6b9 JG |
192 | |
| 193 | /* | |
| 194 | * rs400,rs480 | |
| 195 | */ | |
| ca6ffc64 JG |
196 | extern int rs400_init(struct radeon_device *rdev); |
| 197 | extern void rs400_fini(struct radeon_device *rdev); | |
| 198 | extern int rs400_suspend(struct radeon_device *rdev); | |
| 199 | extern int rs400_resume(struct radeon_device *rdev); | |
| 771fe6b9 JG |
200 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
| 201 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 202 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 203 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 187f3da3 DV |
204 | int rs400_gart_init(struct radeon_device *rdev); |
| 205 | int rs400_gart_enable(struct radeon_device *rdev); | |
| 206 | void rs400_gart_adjust_size(struct radeon_device *rdev); | |
| 207 | void rs400_gart_disable(struct radeon_device *rdev); | |
| 208 | void rs400_gart_fini(struct radeon_device *rdev); | |
| 89e5181f | 209 | extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); |
| 187f3da3 | 210 | |
| 771fe6b9 JG |
211 | /* |
| 212 | * rs600. | |
| 213 | */ | |
| 90aca4d2 | 214 | extern int rs600_asic_reset(struct radeon_device *rdev); |
| c010f800 JG |
215 | extern int rs600_init(struct radeon_device *rdev); |
| 216 | extern void rs600_fini(struct radeon_device *rdev); | |
| 217 | extern int rs600_suspend(struct radeon_device *rdev); | |
| 218 | extern int rs600_resume(struct radeon_device *rdev); | |
| 771fe6b9 | 219 | int rs600_irq_set(struct radeon_device *rdev); |
| 7ed220d7 | 220 | int rs600_irq_process(struct radeon_device *rdev); |
| 187f3da3 | 221 | void rs600_irq_disable(struct radeon_device *rdev); |
| 7ed220d7 | 222 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 771fe6b9 JG |
223 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| 224 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
| 225 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
| 226 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 227 | void rs600_bandwidth_update(struct radeon_device *rdev); |
| 429770b3 AD |
228 | void rs600_hpd_init(struct radeon_device *rdev); |
| 229 | void rs600_hpd_fini(struct radeon_device *rdev); | |
| 230 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 231 | void rs600_hpd_set_polarity(struct radeon_device *rdev, | |
| 232 | enum radeon_hpd_id hpd); | |
| 49e02b73 AD |
233 | extern void rs600_pm_misc(struct radeon_device *rdev); |
| 234 | extern void rs600_pm_prepare(struct radeon_device *rdev); | |
| 235 | extern void rs600_pm_finish(struct radeon_device *rdev); | |
| 6f34be50 AD |
236 | extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 237 | extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 238 | extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); | |
| 187f3da3 | 239 | void rs600_set_safe_registers(struct radeon_device *rdev); |
| 3ae19b75 | 240 | extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 89e5181f | 241 | extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
| 429770b3 | 242 | |
| 771fe6b9 JG |
243 | /* |
| 244 | * rs690,rs740 | |
| 245 | */ | |
| 3bc68535 JG |
246 | int rs690_init(struct radeon_device *rdev); |
| 247 | void rs690_fini(struct radeon_device *rdev); | |
| 248 | int rs690_resume(struct radeon_device *rdev); | |
| 249 | int rs690_suspend(struct radeon_device *rdev); | |
| 771fe6b9 JG |
250 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 251 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| c93bb85b | 252 | void rs690_bandwidth_update(struct radeon_device *rdev); |
| 187f3da3 DV |
253 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
| 254 | struct drm_display_mode *mode1, | |
| 255 | struct drm_display_mode *mode2); | |
| 89e5181f | 256 | extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
257 | |
| 258 | /* | |
| 259 | * rv515 | |
| 260 | */ | |
| 187f3da3 | 261 | struct rv515_mc_save { |
| 187f3da3 DV |
262 | u32 vga_render_control; |
| 263 | u32 vga_hdp_control; | |
| 187f3da3 | 264 | }; |
| 81ee8fb6 | 265 | |
| 068a117c | 266 | int rv515_init(struct radeon_device *rdev); |
| d39c3b89 | 267 | void rv515_fini(struct radeon_device *rdev); |
| 771fe6b9 JG |
268 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 269 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| f712812e | 270 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
| c93bb85b | 271 | void rv515_bandwidth_update(struct radeon_device *rdev); |
| d39c3b89 JG |
272 | int rv515_resume(struct radeon_device *rdev); |
| 273 | int rv515_suspend(struct radeon_device *rdev); | |
| 187f3da3 DV |
274 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
| 275 | void rv515_vga_render_disable(struct radeon_device *rdev); | |
| 276 | void rv515_set_safe_registers(struct radeon_device *rdev); | |
| 277 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 278 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
| 279 | void rv515_clock_startup(struct radeon_device *rdev); | |
| 280 | void rv515_debugfs(struct radeon_device *rdev); | |
| 89e5181f | 281 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
282 | |
| 283 | /* | |
| 284 | * r520,rv530,rv560,rv570,r580 | |
| 285 | */ | |
| d39c3b89 | 286 | int r520_init(struct radeon_device *rdev); |
| f0ed1f65 | 287 | int r520_resume(struct radeon_device *rdev); |
| 89e5181f | 288 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
| 771fe6b9 JG |
289 | |
| 290 | /* | |
| 3ce0a23d | 291 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
| 771fe6b9 | 292 | */ |
| 3ce0a23d JG |
293 | int r600_init(struct radeon_device *rdev); |
| 294 | void r600_fini(struct radeon_device *rdev); | |
| 295 | int r600_suspend(struct radeon_device *rdev); | |
| 296 | int r600_resume(struct radeon_device *rdev); | |
| 28d52043 | 297 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
| 3ce0a23d JG |
298 | int r600_wb_init(struct radeon_device *rdev); |
| 299 | void r600_wb_fini(struct radeon_device *rdev); | |
| 3ce0a23d | 300 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 771fe6b9 JG |
301 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| 302 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
| 3ce0a23d JG |
303 | int r600_cs_parse(struct radeon_cs_parser *p); |
| 304 | void r600_fence_ring_emit(struct radeon_device *rdev, | |
| 305 | struct radeon_fence *fence); | |
| 15d3332f | 306 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
| e32eb50d | 307 | struct radeon_ring *cp, |
| 15d3332f | 308 | struct radeon_semaphore *semaphore, |
| 7b1f2485 | 309 | bool emit_wait); |
| e32eb50d | 310 | bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| a2d07b74 | 311 | int r600_asic_reset(struct radeon_device *rdev); |
| 3ce0a23d JG |
312 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 313 | uint32_t tiling_flags, uint32_t pitch, | |
| 314 | uint32_t offset, uint32_t obj_size); | |
| 9479c54f | 315 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
| f712812e | 316 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
| 3ce0a23d | 317 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| e32eb50d | 318 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
| 3ce0a23d JG |
319 | int r600_copy_blit(struct radeon_device *rdev, |
| 320 | uint64_t src_offset, uint64_t dst_offset, | |
| 876dc9f3 | 321 | unsigned num_gpu_pages, struct radeon_fence **fence); |
| 429770b3 AD |
322 | void r600_hpd_init(struct radeon_device *rdev); |
| 323 | void r600_hpd_fini(struct radeon_device *rdev); | |
| 324 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 325 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
| 326 | enum radeon_hpd_id hpd); | |
| 062b389c | 327 | extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); |
| def9ba9c | 328 | extern bool r600_gui_idle(struct radeon_device *rdev); |
| 49e02b73 | 329 | extern void r600_pm_misc(struct radeon_device *rdev); |
| ce8f5370 AD |
330 | extern void r600_pm_init_profile(struct radeon_device *rdev); |
| 331 | extern void rs780_pm_init_profile(struct radeon_device *rdev); | |
| 332 | extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); | |
| 3313e3d4 AD |
333 | extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| 334 | extern int r600_get_pcie_lanes(struct radeon_device *rdev); | |
| 3574dda4 DV |
335 | bool r600_card_posted(struct radeon_device *rdev); |
| 336 | void r600_cp_stop(struct radeon_device *rdev); | |
| 337 | int r600_cp_start(struct radeon_device *rdev); | |
| e32eb50d | 338 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); |
| 3574dda4 DV |
339 | int r600_cp_resume(struct radeon_device *rdev); |
| 340 | void r600_cp_fini(struct radeon_device *rdev); | |
| 341 | int r600_count_pipe_bits(uint32_t val); | |
| 342 | int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
| 343 | int r600_pcie_gart_init(struct radeon_device *rdev); | |
| 344 | void r600_scratch_init(struct radeon_device *rdev); | |
| 345 | int r600_blit_init(struct radeon_device *rdev); | |
| 346 | void r600_blit_fini(struct radeon_device *rdev); | |
| 347 | int r600_init_microcode(struct radeon_device *rdev); | |
| 348 | /* r600 irq */ | |
| 349 | int r600_irq_process(struct radeon_device *rdev); | |
| 350 | int r600_irq_init(struct radeon_device *rdev); | |
| 351 | void r600_irq_fini(struct radeon_device *rdev); | |
| 352 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
| 353 | int r600_irq_set(struct radeon_device *rdev); | |
| 354 | void r600_irq_suspend(struct radeon_device *rdev); | |
| 355 | void r600_disable_interrupts(struct radeon_device *rdev); | |
| 356 | void r600_rlc_stop(struct radeon_device *rdev); | |
| 357 | /* r600 audio */ | |
| 358 | int r600_audio_init(struct radeon_device *rdev); | |
| 3574dda4 | 359 | void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
| 3299de95 | 360 | struct r600_audio r600_audio_status(struct radeon_device *rdev); |
| 3574dda4 | 361 | void r600_audio_fini(struct radeon_device *rdev); |
| 3574dda4 DV |
362 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
| 363 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); | |
| 4546b2c1 | 364 | /* r600 blit */ |
| f237750f | 365 | int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, |
| 220907d9 CK |
366 | struct radeon_fence **fence, struct radeon_sa_bo **vb, |
| 367 | struct radeon_semaphore **sem); | |
| 876dc9f3 | 368 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, |
| 220907d9 | 369 | struct radeon_sa_bo *vb, struct radeon_semaphore *sem); |
| 4546b2c1 DV |
370 | void r600_kms_blit_copy(struct radeon_device *rdev, |
| 371 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
| f237750f CK |
372 | unsigned num_gpu_pages, |
| 373 | struct radeon_sa_bo *vb); | |
| 89e5181f | 374 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
| 6759a0a7 | 375 | uint64_t r600_get_gpu_clock(struct radeon_device *rdev); |
| 3ce0a23d | 376 | |
| 3ce0a23d JG |
377 | /* |
| 378 | * rv770,rv730,rv710,rv740 | |
| 379 | */ | |
| 380 | int rv770_init(struct radeon_device *rdev); | |
| 381 | void rv770_fini(struct radeon_device *rdev); | |
| 382 | int rv770_suspend(struct radeon_device *rdev); | |
| 383 | int rv770_resume(struct radeon_device *rdev); | |
| 3574dda4 DV |
384 | void rv770_pm_misc(struct radeon_device *rdev); |
| 385 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 386 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
| 387 | void r700_cp_stop(struct radeon_device *rdev); | |
| 388 | void r700_cp_fini(struct radeon_device *rdev); | |
| 3ce0a23d | 389 | |
| bcc1c2a1 AD |
390 | /* |
| 391 | * evergreen | |
| 392 | */ | |
| 3574dda4 | 393 | struct evergreen_mc_save { |
| 3574dda4 DV |
394 | u32 vga_render_control; |
| 395 | u32 vga_hdp_control; | |
| 62444b74 | 396 | bool crtc_enabled[RADEON_MAX_CRTCS]; |
| 3574dda4 | 397 | }; |
| 81ee8fb6 | 398 | |
| 0fcdb61e | 399 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| bcc1c2a1 AD |
400 | int evergreen_init(struct radeon_device *rdev); |
| 401 | void evergreen_fini(struct radeon_device *rdev); | |
| 402 | int evergreen_suspend(struct radeon_device *rdev); | |
| 403 | int evergreen_resume(struct radeon_device *rdev); | |
| e32eb50d | 404 | bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
| a2d07b74 | 405 | int evergreen_asic_reset(struct radeon_device *rdev); |
| bcc1c2a1 | 406 | void evergreen_bandwidth_update(struct radeon_device *rdev); |
| 12920591 | 407 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| bcc1c2a1 AD |
408 | void evergreen_hpd_init(struct radeon_device *rdev); |
| 409 | void evergreen_hpd_fini(struct radeon_device *rdev); | |
| 410 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
| 411 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, | |
| 412 | enum radeon_hpd_id hpd); | |
| 45f9a39b AD |
413 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
| 414 | int evergreen_irq_set(struct radeon_device *rdev); | |
| 415 | int evergreen_irq_process(struct radeon_device *rdev); | |
| cb5fcbd5 | 416 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
| 49e02b73 AD |
417 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
| 418 | extern void evergreen_pm_prepare(struct radeon_device *rdev); | |
| 419 | extern void evergreen_pm_finish(struct radeon_device *rdev); | |
| a4c9e2ee | 420 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
| 6f34be50 AD |
421 | extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); |
| 422 | extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
| 423 | extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); | |
| 3ae19b75 | 424 | extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
| 3574dda4 DV |
425 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
| 426 | int evergreen_blit_init(struct radeon_device *rdev); | |
| 89e5181f | 427 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
| 4546b2c1 | 428 | |
| e3487629 AD |
429 | /* |
| 430 | * cayman | |
| 431 | */ | |
| b40e7e16 AD |
432 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
| 433 | struct radeon_fence *fence); | |
| e3487629 AD |
434 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 435 | int cayman_init(struct radeon_device *rdev); | |
| 436 | void cayman_fini(struct radeon_device *rdev); | |
| 437 | int cayman_suspend(struct radeon_device *rdev); | |
| 438 | int cayman_resume(struct radeon_device *rdev); | |
| e3487629 | 439 | int cayman_asic_reset(struct radeon_device *rdev); |
| 721604a1 JG |
440 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
| 441 | int cayman_vm_init(struct radeon_device *rdev); | |
| 442 | void cayman_vm_fini(struct radeon_device *rdev); | |
| 721604a1 | 443 | void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm); |
| 9b40e5d8 | 444 | void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ib *ib); |
| 721604a1 JG |
445 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, |
| 446 | struct radeon_vm *vm, | |
| 447 | uint32_t flags); | |
| 448 | void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm, | |
| 449 | unsigned pfn, uint64_t addr, uint32_t flags); | |
| 450 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 45f9a39b | 451 | |
| 43b3cd99 AD |
452 | /* DCE6 - SI */ |
| 453 | void dce6_bandwidth_update(struct radeon_device *rdev); | |
| 454 | ||
| 02779c08 AD |
455 | /* |
| 456 | * si | |
| 457 | */ | |
| 458 | void si_fence_ring_emit(struct radeon_device *rdev, | |
| 459 | struct radeon_fence *fence); | |
| 460 | void si_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
| 461 | int si_init(struct radeon_device *rdev); | |
| 462 | void si_fini(struct radeon_device *rdev); | |
| 463 | int si_suspend(struct radeon_device *rdev); | |
| 464 | int si_resume(struct radeon_device *rdev); | |
| 465 | bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
| 466 | int si_asic_reset(struct radeon_device *rdev); | |
| 467 | void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
| 468 | int si_irq_set(struct radeon_device *rdev); | |
| 469 | int si_irq_process(struct radeon_device *rdev); | |
| 470 | int si_vm_init(struct radeon_device *rdev); | |
| 471 | void si_vm_fini(struct radeon_device *rdev); | |
| ee60e29f | 472 | void si_vm_flush(struct radeon_device *rdev, struct radeon_ib *ib); |
| 02779c08 | 473 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); |
| 6759a0a7 | 474 | uint64_t si_get_gpu_clock(struct radeon_device *rdev); |
| 02779c08 | 475 | |
| 771fe6b9 | 476 | #endif |