Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_ASIC_H__ | |
29 | #define __RADEON_ASIC_H__ | |
30 | ||
31 | /* | |
32 | * common functions | |
33 | */ | |
7433874e | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
771fe6b9 | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
5ea597f3 | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
771fe6b9 JG |
37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
38 | ||
7433874e | 39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
771fe6b9 | 40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
7433874e | 41 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
771fe6b9 JG |
42 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
43 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); | |
44 | ||
45 | /* | |
44ca7478 | 46 | * r100,rv100,rs100,rv200,rs200 |
771fe6b9 | 47 | */ |
2b497502 DV |
48 | struct r100_mc_save { |
49 | u32 GENMO_WT; | |
50 | u32 CRTC_EXT_CNTL; | |
51 | u32 CRTC_GEN_CNTL; | |
52 | u32 CRTC2_GEN_CNTL; | |
53 | u32 CUR_OFFSET; | |
54 | u32 CUR2_OFFSET; | |
55 | }; | |
56 | int r100_init(struct radeon_device *rdev); | |
57 | void r100_fini(struct radeon_device *rdev); | |
58 | int r100_suspend(struct radeon_device *rdev); | |
59 | int r100_resume(struct radeon_device *rdev); | |
28d52043 | 60 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
e32eb50d | 61 | bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
a2d07b74 | 62 | int r100_asic_reset(struct radeon_device *rdev); |
7ed220d7 | 63 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
64 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
65 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
f712812e | 66 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
771fe6b9 JG |
67 | int r100_irq_set(struct radeon_device *rdev); |
68 | int r100_irq_process(struct radeon_device *rdev); | |
69 | void r100_fence_ring_emit(struct radeon_device *rdev, | |
70 | struct radeon_fence *fence); | |
15d3332f | 71 | void r100_semaphore_ring_emit(struct radeon_device *rdev, |
e32eb50d | 72 | struct radeon_ring *cp, |
15d3332f | 73 | struct radeon_semaphore *semaphore, |
7b1f2485 | 74 | bool emit_wait); |
771fe6b9 JG |
75 | int r100_cs_parse(struct radeon_cs_parser *p); |
76 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
77 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); | |
78 | int r100_copy_blit(struct radeon_device *rdev, | |
79 | uint64_t src_offset, | |
80 | uint64_t dst_offset, | |
003cefe0 | 81 | unsigned num_gpu_pages, |
876dc9f3 | 82 | struct radeon_fence **fence); |
e024e110 DA |
83 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
84 | uint32_t tiling_flags, uint32_t pitch, | |
85 | uint32_t offset, uint32_t obj_size); | |
9479c54f | 86 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
c93bb85b | 87 | void r100_bandwidth_update(struct radeon_device *rdev); |
3ce0a23d | 88 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
e32eb50d | 89 | int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
429770b3 AD |
90 | void r100_hpd_init(struct radeon_device *rdev); |
91 | void r100_hpd_fini(struct radeon_device *rdev); | |
92 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
93 | void r100_hpd_set_polarity(struct radeon_device *rdev, | |
94 | enum radeon_hpd_id hpd); | |
2b497502 DV |
95 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); |
96 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
97 | void r100_cp_disable(struct radeon_device *rdev); | |
98 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
99 | void r100_cp_fini(struct radeon_device *rdev); | |
100 | int r100_pci_gart_init(struct radeon_device *rdev); | |
101 | void r100_pci_gart_fini(struct radeon_device *rdev); | |
102 | int r100_pci_gart_enable(struct radeon_device *rdev); | |
103 | void r100_pci_gart_disable(struct radeon_device *rdev); | |
104 | int r100_debugfs_mc_info_init(struct radeon_device *rdev); | |
105 | int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
f712812e | 106 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
2b497502 DV |
107 | void r100_irq_disable(struct radeon_device *rdev); |
108 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
109 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
110 | void r100_vram_init_sizes(struct radeon_device *rdev); | |
2b497502 DV |
111 | int r100_cp_reset(struct radeon_device *rdev); |
112 | void r100_vga_render_disable(struct radeon_device *rdev); | |
4c712e6c | 113 | void r100_restore_sanity(struct radeon_device *rdev); |
2b497502 DV |
114 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
115 | struct radeon_cs_packet *pkt, | |
116 | struct radeon_bo *robj); | |
117 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |
118 | struct radeon_cs_packet *pkt, | |
119 | const unsigned *auth, unsigned n, | |
120 | radeon_packet0_check_t check); | |
121 | int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
122 | struct radeon_cs_packet *pkt, | |
123 | unsigned idx); | |
124 | void r100_enable_bm(struct radeon_device *rdev); | |
125 | void r100_set_common_regs(struct radeon_device *rdev); | |
90aca4d2 | 126 | void r100_bm_disable(struct radeon_device *rdev); |
def9ba9c | 127 | extern bool r100_gui_idle(struct radeon_device *rdev); |
49e02b73 AD |
128 | extern void r100_pm_misc(struct radeon_device *rdev); |
129 | extern void r100_pm_prepare(struct radeon_device *rdev); | |
130 | extern void r100_pm_finish(struct radeon_device *rdev); | |
ce8f5370 AD |
131 | extern void r100_pm_init_profile(struct radeon_device *rdev); |
132 | extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); | |
6f34be50 AD |
133 | extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); |
134 | extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
135 | extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); | |
3ae19b75 | 136 | extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); |
89e5181f | 137 | extern int r100_mc_wait_for_idle(struct radeon_device *rdev); |
bae6b562 | 138 | |
44ca7478 PN |
139 | /* |
140 | * r200,rv250,rs300,rv280 | |
141 | */ | |
142 | extern int r200_copy_dma(struct radeon_device *rdev, | |
187f3da3 DV |
143 | uint64_t src_offset, |
144 | uint64_t dst_offset, | |
003cefe0 | 145 | unsigned num_gpu_pages, |
876dc9f3 | 146 | struct radeon_fence **fence); |
187f3da3 | 147 | void r200_set_safe_registers(struct radeon_device *rdev); |
771fe6b9 JG |
148 | |
149 | /* | |
150 | * r300,r350,rv350,rv380 | |
151 | */ | |
207bf9e9 JG |
152 | extern int r300_init(struct radeon_device *rdev); |
153 | extern void r300_fini(struct radeon_device *rdev); | |
154 | extern int r300_suspend(struct radeon_device *rdev); | |
155 | extern int r300_resume(struct radeon_device *rdev); | |
a2d07b74 | 156 | extern int r300_asic_reset(struct radeon_device *rdev); |
f712812e | 157 | extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
207bf9e9 JG |
158 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
159 | struct radeon_fence *fence); | |
160 | extern int r300_cs_parse(struct radeon_cs_parser *p); | |
161 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
162 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
207bf9e9 | 163 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
c836a412 | 164 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
187f3da3 DV |
165 | extern void r300_set_reg_safe(struct radeon_device *rdev); |
166 | extern void r300_mc_program(struct radeon_device *rdev); | |
167 | extern void r300_mc_init(struct radeon_device *rdev); | |
168 | extern void r300_clock_startup(struct radeon_device *rdev); | |
169 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
170 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); | |
171 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
172 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
173 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); | |
89e5181f | 174 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); |
44ca7478 | 175 | |
771fe6b9 JG |
176 | /* |
177 | * r420,r423,rv410 | |
178 | */ | |
9f022ddf JG |
179 | extern int r420_init(struct radeon_device *rdev); |
180 | extern void r420_fini(struct radeon_device *rdev); | |
181 | extern int r420_suspend(struct radeon_device *rdev); | |
182 | extern int r420_resume(struct radeon_device *rdev); | |
ce8f5370 | 183 | extern void r420_pm_init_profile(struct radeon_device *rdev); |
187f3da3 DV |
184 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
185 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
186 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); | |
187 | extern void r420_pipes_init(struct radeon_device *rdev); | |
771fe6b9 JG |
188 | |
189 | /* | |
190 | * rs400,rs480 | |
191 | */ | |
ca6ffc64 JG |
192 | extern int rs400_init(struct radeon_device *rdev); |
193 | extern void rs400_fini(struct radeon_device *rdev); | |
194 | extern int rs400_suspend(struct radeon_device *rdev); | |
195 | extern int rs400_resume(struct radeon_device *rdev); | |
771fe6b9 JG |
196 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
197 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
198 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
199 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
187f3da3 DV |
200 | int rs400_gart_init(struct radeon_device *rdev); |
201 | int rs400_gart_enable(struct radeon_device *rdev); | |
202 | void rs400_gart_adjust_size(struct radeon_device *rdev); | |
203 | void rs400_gart_disable(struct radeon_device *rdev); | |
204 | void rs400_gart_fini(struct radeon_device *rdev); | |
89e5181f | 205 | extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); |
187f3da3 | 206 | |
771fe6b9 JG |
207 | /* |
208 | * rs600. | |
209 | */ | |
90aca4d2 | 210 | extern int rs600_asic_reset(struct radeon_device *rdev); |
c010f800 JG |
211 | extern int rs600_init(struct radeon_device *rdev); |
212 | extern void rs600_fini(struct radeon_device *rdev); | |
213 | extern int rs600_suspend(struct radeon_device *rdev); | |
214 | extern int rs600_resume(struct radeon_device *rdev); | |
771fe6b9 | 215 | int rs600_irq_set(struct radeon_device *rdev); |
7ed220d7 | 216 | int rs600_irq_process(struct radeon_device *rdev); |
187f3da3 | 217 | void rs600_irq_disable(struct radeon_device *rdev); |
7ed220d7 | 218 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
219 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
220 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
221 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); | |
222 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
c93bb85b | 223 | void rs600_bandwidth_update(struct radeon_device *rdev); |
429770b3 AD |
224 | void rs600_hpd_init(struct radeon_device *rdev); |
225 | void rs600_hpd_fini(struct radeon_device *rdev); | |
226 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
227 | void rs600_hpd_set_polarity(struct radeon_device *rdev, | |
228 | enum radeon_hpd_id hpd); | |
49e02b73 AD |
229 | extern void rs600_pm_misc(struct radeon_device *rdev); |
230 | extern void rs600_pm_prepare(struct radeon_device *rdev); | |
231 | extern void rs600_pm_finish(struct radeon_device *rdev); | |
6f34be50 AD |
232 | extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); |
233 | extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
234 | extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); | |
187f3da3 | 235 | void rs600_set_safe_registers(struct radeon_device *rdev); |
3ae19b75 | 236 | extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); |
89e5181f | 237 | extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
429770b3 | 238 | |
771fe6b9 JG |
239 | /* |
240 | * rs690,rs740 | |
241 | */ | |
3bc68535 JG |
242 | int rs690_init(struct radeon_device *rdev); |
243 | void rs690_fini(struct radeon_device *rdev); | |
244 | int rs690_resume(struct radeon_device *rdev); | |
245 | int rs690_suspend(struct radeon_device *rdev); | |
771fe6b9 JG |
246 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
247 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
c93bb85b | 248 | void rs690_bandwidth_update(struct radeon_device *rdev); |
187f3da3 DV |
249 | void rs690_line_buffer_adjust(struct radeon_device *rdev, |
250 | struct drm_display_mode *mode1, | |
251 | struct drm_display_mode *mode2); | |
89e5181f | 252 | extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); |
771fe6b9 JG |
253 | |
254 | /* | |
255 | * rv515 | |
256 | */ | |
187f3da3 DV |
257 | struct rv515_mc_save { |
258 | u32 d1vga_control; | |
259 | u32 d2vga_control; | |
260 | u32 vga_render_control; | |
261 | u32 vga_hdp_control; | |
262 | u32 d1crtc_control; | |
263 | u32 d2crtc_control; | |
264 | }; | |
068a117c | 265 | int rv515_init(struct radeon_device *rdev); |
d39c3b89 | 266 | void rv515_fini(struct radeon_device *rdev); |
771fe6b9 JG |
267 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
268 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
f712812e | 269 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
c93bb85b | 270 | void rv515_bandwidth_update(struct radeon_device *rdev); |
d39c3b89 JG |
271 | int rv515_resume(struct radeon_device *rdev); |
272 | int rv515_suspend(struct radeon_device *rdev); | |
187f3da3 DV |
273 | void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
274 | void rv515_vga_render_disable(struct radeon_device *rdev); | |
275 | void rv515_set_safe_registers(struct radeon_device *rdev); | |
276 | void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); | |
277 | void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
278 | void rv515_clock_startup(struct radeon_device *rdev); | |
279 | void rv515_debugfs(struct radeon_device *rdev); | |
89e5181f | 280 | int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
771fe6b9 JG |
281 | |
282 | /* | |
283 | * r520,rv530,rv560,rv570,r580 | |
284 | */ | |
d39c3b89 | 285 | int r520_init(struct radeon_device *rdev); |
f0ed1f65 | 286 | int r520_resume(struct radeon_device *rdev); |
89e5181f | 287 | int r520_mc_wait_for_idle(struct radeon_device *rdev); |
771fe6b9 JG |
288 | |
289 | /* | |
3ce0a23d | 290 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
771fe6b9 | 291 | */ |
3ce0a23d JG |
292 | int r600_init(struct radeon_device *rdev); |
293 | void r600_fini(struct radeon_device *rdev); | |
294 | int r600_suspend(struct radeon_device *rdev); | |
295 | int r600_resume(struct radeon_device *rdev); | |
28d52043 | 296 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
3ce0a23d JG |
297 | int r600_wb_init(struct radeon_device *rdev); |
298 | void r600_wb_fini(struct radeon_device *rdev); | |
3ce0a23d | 299 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
771fe6b9 JG |
300 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
301 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
3ce0a23d JG |
302 | int r600_cs_parse(struct radeon_cs_parser *p); |
303 | void r600_fence_ring_emit(struct radeon_device *rdev, | |
304 | struct radeon_fence *fence); | |
15d3332f | 305 | void r600_semaphore_ring_emit(struct radeon_device *rdev, |
e32eb50d | 306 | struct radeon_ring *cp, |
15d3332f | 307 | struct radeon_semaphore *semaphore, |
7b1f2485 | 308 | bool emit_wait); |
e32eb50d | 309 | bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
a2d07b74 | 310 | int r600_asic_reset(struct radeon_device *rdev); |
3ce0a23d JG |
311 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
312 | uint32_t tiling_flags, uint32_t pitch, | |
313 | uint32_t offset, uint32_t obj_size); | |
9479c54f | 314 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
f712812e | 315 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
3ce0a23d | 316 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
e32eb50d | 317 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
3ce0a23d JG |
318 | int r600_copy_blit(struct radeon_device *rdev, |
319 | uint64_t src_offset, uint64_t dst_offset, | |
876dc9f3 | 320 | unsigned num_gpu_pages, struct radeon_fence **fence); |
429770b3 AD |
321 | void r600_hpd_init(struct radeon_device *rdev); |
322 | void r600_hpd_fini(struct radeon_device *rdev); | |
323 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
324 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
325 | enum radeon_hpd_id hpd); | |
062b389c | 326 | extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); |
def9ba9c | 327 | extern bool r600_gui_idle(struct radeon_device *rdev); |
49e02b73 | 328 | extern void r600_pm_misc(struct radeon_device *rdev); |
ce8f5370 AD |
329 | extern void r600_pm_init_profile(struct radeon_device *rdev); |
330 | extern void rs780_pm_init_profile(struct radeon_device *rdev); | |
331 | extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); | |
3313e3d4 AD |
332 | extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
333 | extern int r600_get_pcie_lanes(struct radeon_device *rdev); | |
3574dda4 DV |
334 | bool r600_card_posted(struct radeon_device *rdev); |
335 | void r600_cp_stop(struct radeon_device *rdev); | |
336 | int r600_cp_start(struct radeon_device *rdev); | |
e32eb50d | 337 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); |
3574dda4 DV |
338 | int r600_cp_resume(struct radeon_device *rdev); |
339 | void r600_cp_fini(struct radeon_device *rdev); | |
340 | int r600_count_pipe_bits(uint32_t val); | |
341 | int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
342 | int r600_pcie_gart_init(struct radeon_device *rdev); | |
343 | void r600_scratch_init(struct radeon_device *rdev); | |
344 | int r600_blit_init(struct radeon_device *rdev); | |
345 | void r600_blit_fini(struct radeon_device *rdev); | |
346 | int r600_init_microcode(struct radeon_device *rdev); | |
347 | /* r600 irq */ | |
348 | int r600_irq_process(struct radeon_device *rdev); | |
349 | int r600_irq_init(struct radeon_device *rdev); | |
350 | void r600_irq_fini(struct radeon_device *rdev); | |
351 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
352 | int r600_irq_set(struct radeon_device *rdev); | |
353 | void r600_irq_suspend(struct radeon_device *rdev); | |
354 | void r600_disable_interrupts(struct radeon_device *rdev); | |
355 | void r600_rlc_stop(struct radeon_device *rdev); | |
356 | /* r600 audio */ | |
357 | int r600_audio_init(struct radeon_device *rdev); | |
3574dda4 | 358 | void r600_audio_set_clock(struct drm_encoder *encoder, int clock); |
3299de95 | 359 | struct r600_audio r600_audio_status(struct radeon_device *rdev); |
3574dda4 | 360 | void r600_audio_fini(struct radeon_device *rdev); |
3574dda4 DV |
361 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
362 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); | |
4546b2c1 | 363 | /* r600 blit */ |
f237750f | 364 | int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, |
220907d9 CK |
365 | struct radeon_fence **fence, struct radeon_sa_bo **vb, |
366 | struct radeon_semaphore **sem); | |
876dc9f3 | 367 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, |
220907d9 | 368 | struct radeon_sa_bo *vb, struct radeon_semaphore *sem); |
4546b2c1 DV |
369 | void r600_kms_blit_copy(struct radeon_device *rdev, |
370 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
f237750f CK |
371 | unsigned num_gpu_pages, |
372 | struct radeon_sa_bo *vb); | |
89e5181f | 373 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
3ce0a23d | 374 | |
3ce0a23d JG |
375 | /* |
376 | * rv770,rv730,rv710,rv740 | |
377 | */ | |
378 | int rv770_init(struct radeon_device *rdev); | |
379 | void rv770_fini(struct radeon_device *rdev); | |
380 | int rv770_suspend(struct radeon_device *rdev); | |
381 | int rv770_resume(struct radeon_device *rdev); | |
3574dda4 DV |
382 | void rv770_pm_misc(struct radeon_device *rdev); |
383 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
384 | void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
385 | void r700_cp_stop(struct radeon_device *rdev); | |
386 | void r700_cp_fini(struct radeon_device *rdev); | |
3ce0a23d | 387 | |
bcc1c2a1 AD |
388 | /* |
389 | * evergreen | |
390 | */ | |
3574dda4 DV |
391 | struct evergreen_mc_save { |
392 | u32 vga_control[6]; | |
393 | u32 vga_render_control; | |
394 | u32 vga_hdp_control; | |
395 | u32 crtc_control[6]; | |
396 | }; | |
0fcdb61e | 397 | void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); |
bcc1c2a1 AD |
398 | int evergreen_init(struct radeon_device *rdev); |
399 | void evergreen_fini(struct radeon_device *rdev); | |
400 | int evergreen_suspend(struct radeon_device *rdev); | |
401 | int evergreen_resume(struct radeon_device *rdev); | |
e32eb50d | 402 | bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
a2d07b74 | 403 | int evergreen_asic_reset(struct radeon_device *rdev); |
bcc1c2a1 | 404 | void evergreen_bandwidth_update(struct radeon_device *rdev); |
12920591 | 405 | void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
bcc1c2a1 AD |
406 | void evergreen_hpd_init(struct radeon_device *rdev); |
407 | void evergreen_hpd_fini(struct radeon_device *rdev); | |
408 | bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
409 | void evergreen_hpd_set_polarity(struct radeon_device *rdev, | |
410 | enum radeon_hpd_id hpd); | |
45f9a39b AD |
411 | u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); |
412 | int evergreen_irq_set(struct radeon_device *rdev); | |
413 | int evergreen_irq_process(struct radeon_device *rdev); | |
cb5fcbd5 | 414 | extern int evergreen_cs_parse(struct radeon_cs_parser *p); |
49e02b73 AD |
415 | extern void evergreen_pm_misc(struct radeon_device *rdev); |
416 | extern void evergreen_pm_prepare(struct radeon_device *rdev); | |
417 | extern void evergreen_pm_finish(struct radeon_device *rdev); | |
a4c9e2ee | 418 | extern void sumo_pm_init_profile(struct radeon_device *rdev); |
6f34be50 AD |
419 | extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); |
420 | extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
421 | extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); | |
3ae19b75 | 422 | extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); |
3574dda4 DV |
423 | void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
424 | int evergreen_blit_init(struct radeon_device *rdev); | |
89e5181f | 425 | int evergreen_mc_wait_for_idle(struct radeon_device *rdev); |
4546b2c1 | 426 | |
e3487629 AD |
427 | /* |
428 | * cayman | |
429 | */ | |
b40e7e16 AD |
430 | void cayman_fence_ring_emit(struct radeon_device *rdev, |
431 | struct radeon_fence *fence); | |
e3487629 AD |
432 | void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); |
433 | int cayman_init(struct radeon_device *rdev); | |
434 | void cayman_fini(struct radeon_device *rdev); | |
435 | int cayman_suspend(struct radeon_device *rdev); | |
436 | int cayman_resume(struct radeon_device *rdev); | |
e3487629 | 437 | int cayman_asic_reset(struct radeon_device *rdev); |
721604a1 JG |
438 | void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
439 | int cayman_vm_init(struct radeon_device *rdev); | |
440 | void cayman_vm_fini(struct radeon_device *rdev); | |
441 | int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id); | |
442 | void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm); | |
443 | void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm); | |
444 | uint32_t cayman_vm_page_flags(struct radeon_device *rdev, | |
445 | struct radeon_vm *vm, | |
446 | uint32_t flags); | |
447 | void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm, | |
448 | unsigned pfn, uint64_t addr, uint32_t flags); | |
449 | int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); | |
45f9a39b | 450 | |
43b3cd99 AD |
451 | /* DCE6 - SI */ |
452 | void dce6_bandwidth_update(struct radeon_device *rdev); | |
453 | ||
02779c08 AD |
454 | /* |
455 | * si | |
456 | */ | |
457 | void si_fence_ring_emit(struct radeon_device *rdev, | |
458 | struct radeon_fence *fence); | |
459 | void si_pcie_gart_tlb_flush(struct radeon_device *rdev); | |
460 | int si_init(struct radeon_device *rdev); | |
461 | void si_fini(struct radeon_device *rdev); | |
462 | int si_suspend(struct radeon_device *rdev); | |
463 | int si_resume(struct radeon_device *rdev); | |
464 | bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | |
465 | int si_asic_reset(struct radeon_device *rdev); | |
466 | void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
467 | int si_irq_set(struct radeon_device *rdev); | |
468 | int si_irq_process(struct radeon_device *rdev); | |
469 | int si_vm_init(struct radeon_device *rdev); | |
470 | void si_vm_fini(struct radeon_device *rdev); | |
471 | int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id); | |
472 | void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm); | |
473 | void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm); | |
474 | int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); | |
475 | ||
771fe6b9 | 476 | #endif |