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0a10c851 DV |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | ||
29 | #include <linux/console.h> | |
2ef79416 | 30 | #include <linux/pci.h> |
f9183127 SR |
31 | #include <linux/vgaarb.h> |
32 | ||
0a10c851 | 33 | #include <drm/radeon_drm.h> |
f9183127 SR |
34 | |
35 | #include "atom.h" | |
0a10c851 DV |
36 | #include "radeon.h" |
37 | #include "radeon_asic.h" | |
f9183127 | 38 | #include "radeon_reg.h" |
0a10c851 DV |
39 | |
40 | /* | |
41 | * Registers accessors functions. | |
42 | */ | |
abf1dc67 AD |
43 | /** |
44 | * radeon_invalid_rreg - dummy reg read function | |
45 | * | |
46 | * @rdev: radeon device pointer | |
47 | * @reg: offset of register | |
48 | * | |
49 | * Dummy register read function. Used for register blocks | |
50 | * that certain asics don't have (all asics). | |
51 | * Returns the value in the register. | |
52 | */ | |
0a10c851 DV |
53 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
54 | { | |
55 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
56 | BUG_ON(1); | |
57 | return 0; | |
58 | } | |
59 | ||
abf1dc67 AD |
60 | /** |
61 | * radeon_invalid_wreg - dummy reg write function | |
62 | * | |
63 | * @rdev: radeon device pointer | |
64 | * @reg: offset of register | |
65 | * @v: value to write to the register | |
66 | * | |
67 | * Dummy register read function. Used for register blocks | |
68 | * that certain asics don't have (all asics). | |
69 | */ | |
0a10c851 DV |
70 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
71 | { | |
72 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
73 | reg, v); | |
74 | BUG_ON(1); | |
75 | } | |
76 | ||
abf1dc67 AD |
77 | /** |
78 | * radeon_register_accessor_init - sets up the register accessor callbacks | |
79 | * | |
80 | * @rdev: radeon device pointer | |
81 | * | |
82 | * Sets up the register accessor callbacks for various register | |
83 | * apertures. Not all asics have all apertures (all asics). | |
84 | */ | |
0a10c851 DV |
85 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
86 | { | |
87 | rdev->mc_rreg = &radeon_invalid_rreg; | |
88 | rdev->mc_wreg = &radeon_invalid_wreg; | |
89 | rdev->pll_rreg = &radeon_invalid_rreg; | |
90 | rdev->pll_wreg = &radeon_invalid_wreg; | |
91 | rdev->pciep_rreg = &radeon_invalid_rreg; | |
92 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
93 | ||
94 | /* Don't change order as we are overridding accessor. */ | |
95 | if (rdev->family < CHIP_RV515) { | |
96 | rdev->pcie_reg_mask = 0xff; | |
97 | } else { | |
98 | rdev->pcie_reg_mask = 0x7ff; | |
99 | } | |
100 | /* FIXME: not sure here */ | |
101 | if (rdev->family <= CHIP_R580) { | |
102 | rdev->pll_rreg = &r100_pll_rreg; | |
103 | rdev->pll_wreg = &r100_pll_wreg; | |
104 | } | |
105 | if (rdev->family >= CHIP_R420) { | |
106 | rdev->mc_rreg = &r420_mc_rreg; | |
107 | rdev->mc_wreg = &r420_mc_wreg; | |
108 | } | |
109 | if (rdev->family >= CHIP_RV515) { | |
110 | rdev->mc_rreg = &rv515_mc_rreg; | |
111 | rdev->mc_wreg = &rv515_mc_wreg; | |
112 | } | |
113 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
114 | rdev->mc_rreg = &rs400_mc_rreg; | |
115 | rdev->mc_wreg = &rs400_mc_wreg; | |
116 | } | |
117 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
118 | rdev->mc_rreg = &rs690_mc_rreg; | |
119 | rdev->mc_wreg = &rs690_mc_wreg; | |
120 | } | |
121 | if (rdev->family == CHIP_RS600) { | |
122 | rdev->mc_rreg = &rs600_mc_rreg; | |
123 | rdev->mc_wreg = &rs600_mc_wreg; | |
124 | } | |
65337e60 SL |
125 | if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { |
126 | rdev->mc_rreg = &rs780_mc_rreg; | |
127 | rdev->mc_wreg = &rs780_mc_wreg; | |
128 | } | |
6e2c3c0a AD |
129 | |
130 | if (rdev->family >= CHIP_BONAIRE) { | |
131 | rdev->pciep_rreg = &cik_pciep_rreg; | |
132 | rdev->pciep_wreg = &cik_pciep_wreg; | |
133 | } else if (rdev->family >= CHIP_R600) { | |
0a10c851 DV |
134 | rdev->pciep_rreg = &r600_pciep_rreg; |
135 | rdev->pciep_wreg = &r600_pciep_wreg; | |
136 | } | |
137 | } | |
138 | ||
18b53e90 AD |
139 | static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev, |
140 | u32 reg, u32 *val) | |
141 | { | |
142 | return -EINVAL; | |
143 | } | |
0a10c851 DV |
144 | |
145 | /* helper to disable agp */ | |
abf1dc67 AD |
146 | /** |
147 | * radeon_agp_disable - AGP disable helper function | |
148 | * | |
149 | * @rdev: radeon device pointer | |
150 | * | |
151 | * Removes AGP flags and changes the gart callbacks on AGP | |
152 | * cards when using the internal gart rather than AGP (all asics). | |
153 | */ | |
0a10c851 DV |
154 | void radeon_agp_disable(struct radeon_device *rdev) |
155 | { | |
156 | rdev->flags &= ~RADEON_IS_AGP; | |
157 | if (rdev->family >= CHIP_R600) { | |
158 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
159 | rdev->flags |= RADEON_IS_PCIE; | |
160 | } else if (rdev->family >= CHIP_RV515 || | |
161 | rdev->family == CHIP_RV380 || | |
162 | rdev->family == CHIP_RV410 || | |
163 | rdev->family == CHIP_R423) { | |
164 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
165 | rdev->flags |= RADEON_IS_PCIE; | |
c5b3b850 | 166 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
cb658906 | 167 | rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; |
c5b3b850 | 168 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; |
0a10c851 DV |
169 | } else { |
170 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
171 | rdev->flags |= RADEON_IS_PCI; | |
c5b3b850 | 172 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
cb658906 | 173 | rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; |
c5b3b850 | 174 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; |
0a10c851 DV |
175 | } |
176 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
177 | } | |
178 | ||
179 | /* | |
180 | * ASIC | |
181 | */ | |
76a0df85 | 182 | |
d26678da | 183 | static const struct radeon_asic_ring r100_gfx_ring = { |
76a0df85 CK |
184 | .ib_execute = &r100_ring_ib_execute, |
185 | .emit_fence = &r100_fence_ring_emit, | |
186 | .emit_semaphore = &r100_semaphore_ring_emit, | |
187 | .cs_parse = &r100_cs_parse, | |
188 | .ring_start = &r100_ring_start, | |
189 | .ring_test = &r100_ring_test, | |
190 | .ib_test = &r100_ib_test, | |
191 | .is_lockup = &r100_gpu_is_lockup, | |
ea31bf69 AD |
192 | .get_rptr = &r100_gfx_get_rptr, |
193 | .get_wptr = &r100_gfx_get_wptr, | |
194 | .set_wptr = &r100_gfx_set_wptr, | |
76a0df85 CK |
195 | }; |
196 | ||
48e7a5f1 DV |
197 | static struct radeon_asic r100_asic = { |
198 | .init = &r100_init, | |
199 | .fini = &r100_fini, | |
200 | .suspend = &r100_suspend, | |
201 | .resume = &r100_resume, | |
202 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 203 | .asic_reset = &r100_asic_reset, |
124764f1 | 204 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
205 | .gui_idle = &r100_gui_idle, |
206 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
18b53e90 | 207 | .get_allowed_info_register = radeon_invalid_get_allowed_info_register, |
c5b3b850 AD |
208 | .gart = { |
209 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
cb658906 | 210 | .get_page_entry = &r100_pci_gart_get_page_entry, |
c5b3b850 AD |
211 | .set_page = &r100_pci_gart_set_page, |
212 | }, | |
4c87bc26 | 213 | .ring = { |
76a0df85 | 214 | [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring |
4c87bc26 | 215 | }, |
b35ea4ab AD |
216 | .irq = { |
217 | .set = &r100_irq_set, | |
218 | .process = &r100_irq_process, | |
219 | }, | |
c79a49ca AD |
220 | .display = { |
221 | .bandwidth_update = &r100_bandwidth_update, | |
222 | .get_vblank_counter = &r100_get_vblank_counter, | |
223 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 224 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 225 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 226 | }, |
27cd7769 AD |
227 | .copy = { |
228 | .blit = &r100_copy_blit, | |
229 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
230 | .dma = NULL, | |
231 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
232 | .copy = &r100_copy_blit, | |
233 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
234 | }, | |
9e6f3d02 AD |
235 | .surface = { |
236 | .set_reg = r100_set_surface_reg, | |
237 | .clear_reg = r100_clear_surface_reg, | |
238 | }, | |
901ea57d AD |
239 | .hpd = { |
240 | .init = &r100_hpd_init, | |
241 | .fini = &r100_hpd_fini, | |
242 | .sense = &r100_hpd_sense, | |
243 | .set_polarity = &r100_hpd_set_polarity, | |
244 | }, | |
a02fa397 AD |
245 | .pm = { |
246 | .misc = &r100_pm_misc, | |
247 | .prepare = &r100_pm_prepare, | |
248 | .finish = &r100_pm_finish, | |
249 | .init_profile = &r100_pm_init_profile, | |
250 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
251 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
252 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
253 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
254 | .set_memory_clock = NULL, | |
255 | .get_pcie_lanes = NULL, | |
256 | .set_pcie_lanes = NULL, | |
257 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 258 | }, |
0f9e006c | 259 | .pflip = { |
0f9e006c | 260 | .page_flip = &r100_page_flip, |
157fa14d | 261 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 262 | }, |
48e7a5f1 DV |
263 | }; |
264 | ||
265 | static struct radeon_asic r200_asic = { | |
266 | .init = &r100_init, | |
267 | .fini = &r100_fini, | |
268 | .suspend = &r100_suspend, | |
269 | .resume = &r100_resume, | |
270 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 271 | .asic_reset = &r100_asic_reset, |
124764f1 | 272 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
273 | .gui_idle = &r100_gui_idle, |
274 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
18b53e90 | 275 | .get_allowed_info_register = radeon_invalid_get_allowed_info_register, |
c5b3b850 AD |
276 | .gart = { |
277 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
cb658906 | 278 | .get_page_entry = &r100_pci_gart_get_page_entry, |
c5b3b850 AD |
279 | .set_page = &r100_pci_gart_set_page, |
280 | }, | |
4c87bc26 | 281 | .ring = { |
76a0df85 | 282 | [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring |
4c87bc26 | 283 | }, |
b35ea4ab AD |
284 | .irq = { |
285 | .set = &r100_irq_set, | |
286 | .process = &r100_irq_process, | |
287 | }, | |
c79a49ca AD |
288 | .display = { |
289 | .bandwidth_update = &r100_bandwidth_update, | |
290 | .get_vblank_counter = &r100_get_vblank_counter, | |
291 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 292 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 293 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 294 | }, |
27cd7769 AD |
295 | .copy = { |
296 | .blit = &r100_copy_blit, | |
297 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
298 | .dma = &r200_copy_dma, | |
299 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
300 | .copy = &r100_copy_blit, | |
301 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
302 | }, | |
9e6f3d02 AD |
303 | .surface = { |
304 | .set_reg = r100_set_surface_reg, | |
305 | .clear_reg = r100_clear_surface_reg, | |
306 | }, | |
901ea57d AD |
307 | .hpd = { |
308 | .init = &r100_hpd_init, | |
309 | .fini = &r100_hpd_fini, | |
310 | .sense = &r100_hpd_sense, | |
311 | .set_polarity = &r100_hpd_set_polarity, | |
312 | }, | |
a02fa397 AD |
313 | .pm = { |
314 | .misc = &r100_pm_misc, | |
315 | .prepare = &r100_pm_prepare, | |
316 | .finish = &r100_pm_finish, | |
317 | .init_profile = &r100_pm_init_profile, | |
318 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
319 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
320 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
321 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
322 | .set_memory_clock = NULL, | |
323 | .get_pcie_lanes = NULL, | |
324 | .set_pcie_lanes = NULL, | |
325 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 326 | }, |
0f9e006c | 327 | .pflip = { |
0f9e006c | 328 | .page_flip = &r100_page_flip, |
157fa14d | 329 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 330 | }, |
48e7a5f1 DV |
331 | }; |
332 | ||
d26678da | 333 | static const struct radeon_asic_ring r300_gfx_ring = { |
76a0df85 CK |
334 | .ib_execute = &r100_ring_ib_execute, |
335 | .emit_fence = &r300_fence_ring_emit, | |
336 | .emit_semaphore = &r100_semaphore_ring_emit, | |
337 | .cs_parse = &r300_cs_parse, | |
338 | .ring_start = &r300_ring_start, | |
339 | .ring_test = &r100_ring_test, | |
340 | .ib_test = &r100_ib_test, | |
341 | .is_lockup = &r100_gpu_is_lockup, | |
ea31bf69 AD |
342 | .get_rptr = &r100_gfx_get_rptr, |
343 | .get_wptr = &r100_gfx_get_wptr, | |
344 | .set_wptr = &r100_gfx_set_wptr, | |
76a0df85 CK |
345 | }; |
346 | ||
d26678da | 347 | static const struct radeon_asic_ring rv515_gfx_ring = { |
d8a74e18 AD |
348 | .ib_execute = &r100_ring_ib_execute, |
349 | .emit_fence = &r300_fence_ring_emit, | |
350 | .emit_semaphore = &r100_semaphore_ring_emit, | |
351 | .cs_parse = &r300_cs_parse, | |
352 | .ring_start = &rv515_ring_start, | |
353 | .ring_test = &r100_ring_test, | |
354 | .ib_test = &r100_ib_test, | |
355 | .is_lockup = &r100_gpu_is_lockup, | |
356 | .get_rptr = &r100_gfx_get_rptr, | |
357 | .get_wptr = &r100_gfx_get_wptr, | |
358 | .set_wptr = &r100_gfx_set_wptr, | |
359 | }; | |
360 | ||
48e7a5f1 DV |
361 | static struct radeon_asic r300_asic = { |
362 | .init = &r300_init, | |
363 | .fini = &r300_fini, | |
364 | .suspend = &r300_suspend, | |
365 | .resume = &r300_resume, | |
366 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 367 | .asic_reset = &r300_asic_reset, |
124764f1 | 368 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
369 | .gui_idle = &r100_gui_idle, |
370 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
18b53e90 | 371 | .get_allowed_info_register = radeon_invalid_get_allowed_info_register, |
c5b3b850 AD |
372 | .gart = { |
373 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
cb658906 | 374 | .get_page_entry = &r100_pci_gart_get_page_entry, |
c5b3b850 AD |
375 | .set_page = &r100_pci_gart_set_page, |
376 | }, | |
4c87bc26 | 377 | .ring = { |
76a0df85 | 378 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 379 | }, |
b35ea4ab AD |
380 | .irq = { |
381 | .set = &r100_irq_set, | |
382 | .process = &r100_irq_process, | |
383 | }, | |
c79a49ca AD |
384 | .display = { |
385 | .bandwidth_update = &r100_bandwidth_update, | |
386 | .get_vblank_counter = &r100_get_vblank_counter, | |
387 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 388 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 389 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 390 | }, |
27cd7769 AD |
391 | .copy = { |
392 | .blit = &r100_copy_blit, | |
393 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
394 | .dma = &r200_copy_dma, | |
395 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
396 | .copy = &r100_copy_blit, | |
397 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
398 | }, | |
9e6f3d02 AD |
399 | .surface = { |
400 | .set_reg = r100_set_surface_reg, | |
401 | .clear_reg = r100_clear_surface_reg, | |
402 | }, | |
901ea57d AD |
403 | .hpd = { |
404 | .init = &r100_hpd_init, | |
405 | .fini = &r100_hpd_fini, | |
406 | .sense = &r100_hpd_sense, | |
407 | .set_polarity = &r100_hpd_set_polarity, | |
408 | }, | |
a02fa397 AD |
409 | .pm = { |
410 | .misc = &r100_pm_misc, | |
411 | .prepare = &r100_pm_prepare, | |
412 | .finish = &r100_pm_finish, | |
413 | .init_profile = &r100_pm_init_profile, | |
414 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
415 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
416 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
417 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
418 | .set_memory_clock = NULL, | |
419 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
420 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
421 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 422 | }, |
0f9e006c | 423 | .pflip = { |
0f9e006c | 424 | .page_flip = &r100_page_flip, |
157fa14d | 425 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 426 | }, |
48e7a5f1 DV |
427 | }; |
428 | ||
429 | static struct radeon_asic r300_asic_pcie = { | |
430 | .init = &r300_init, | |
431 | .fini = &r300_fini, | |
432 | .suspend = &r300_suspend, | |
433 | .resume = &r300_resume, | |
434 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 435 | .asic_reset = &r300_asic_reset, |
124764f1 | 436 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
437 | .gui_idle = &r100_gui_idle, |
438 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
18b53e90 | 439 | .get_allowed_info_register = radeon_invalid_get_allowed_info_register, |
c5b3b850 AD |
440 | .gart = { |
441 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
cb658906 | 442 | .get_page_entry = &rv370_pcie_gart_get_page_entry, |
c5b3b850 AD |
443 | .set_page = &rv370_pcie_gart_set_page, |
444 | }, | |
4c87bc26 | 445 | .ring = { |
76a0df85 | 446 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 447 | }, |
b35ea4ab AD |
448 | .irq = { |
449 | .set = &r100_irq_set, | |
450 | .process = &r100_irq_process, | |
451 | }, | |
c79a49ca AD |
452 | .display = { |
453 | .bandwidth_update = &r100_bandwidth_update, | |
454 | .get_vblank_counter = &r100_get_vblank_counter, | |
455 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 456 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 457 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 458 | }, |
27cd7769 AD |
459 | .copy = { |
460 | .blit = &r100_copy_blit, | |
461 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
462 | .dma = &r200_copy_dma, | |
463 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
464 | .copy = &r100_copy_blit, | |
465 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
466 | }, | |
9e6f3d02 AD |
467 | .surface = { |
468 | .set_reg = r100_set_surface_reg, | |
469 | .clear_reg = r100_clear_surface_reg, | |
470 | }, | |
901ea57d AD |
471 | .hpd = { |
472 | .init = &r100_hpd_init, | |
473 | .fini = &r100_hpd_fini, | |
474 | .sense = &r100_hpd_sense, | |
475 | .set_polarity = &r100_hpd_set_polarity, | |
476 | }, | |
a02fa397 AD |
477 | .pm = { |
478 | .misc = &r100_pm_misc, | |
479 | .prepare = &r100_pm_prepare, | |
480 | .finish = &r100_pm_finish, | |
481 | .init_profile = &r100_pm_init_profile, | |
482 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
483 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
484 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
485 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
486 | .set_memory_clock = NULL, | |
487 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
488 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
489 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 490 | }, |
0f9e006c | 491 | .pflip = { |
0f9e006c | 492 | .page_flip = &r100_page_flip, |
157fa14d | 493 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 494 | }, |
48e7a5f1 DV |
495 | }; |
496 | ||
497 | static struct radeon_asic r420_asic = { | |
498 | .init = &r420_init, | |
499 | .fini = &r420_fini, | |
500 | .suspend = &r420_suspend, | |
501 | .resume = &r420_resume, | |
502 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 503 | .asic_reset = &r300_asic_reset, |
124764f1 | 504 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
505 | .gui_idle = &r100_gui_idle, |
506 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
18b53e90 | 507 | .get_allowed_info_register = radeon_invalid_get_allowed_info_register, |
c5b3b850 AD |
508 | .gart = { |
509 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
cb658906 | 510 | .get_page_entry = &rv370_pcie_gart_get_page_entry, |
c5b3b850 AD |
511 | .set_page = &rv370_pcie_gart_set_page, |
512 | }, | |
4c87bc26 | 513 | .ring = { |
76a0df85 | 514 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 515 | }, |
b35ea4ab AD |
516 | .irq = { |
517 | .set = &r100_irq_set, | |
518 | .process = &r100_irq_process, | |
519 | }, | |
c79a49ca AD |
520 | .display = { |
521 | .bandwidth_update = &r100_bandwidth_update, | |
522 | .get_vblank_counter = &r100_get_vblank_counter, | |
523 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 524 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 525 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 526 | }, |
27cd7769 AD |
527 | .copy = { |
528 | .blit = &r100_copy_blit, | |
529 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
530 | .dma = &r200_copy_dma, | |
531 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
532 | .copy = &r100_copy_blit, | |
533 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
534 | }, | |
9e6f3d02 AD |
535 | .surface = { |
536 | .set_reg = r100_set_surface_reg, | |
537 | .clear_reg = r100_clear_surface_reg, | |
538 | }, | |
901ea57d AD |
539 | .hpd = { |
540 | .init = &r100_hpd_init, | |
541 | .fini = &r100_hpd_fini, | |
542 | .sense = &r100_hpd_sense, | |
543 | .set_polarity = &r100_hpd_set_polarity, | |
544 | }, | |
a02fa397 AD |
545 | .pm = { |
546 | .misc = &r100_pm_misc, | |
547 | .prepare = &r100_pm_prepare, | |
548 | .finish = &r100_pm_finish, | |
549 | .init_profile = &r420_pm_init_profile, | |
550 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
551 | .get_engine_clock = &radeon_atom_get_engine_clock, |
552 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
553 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
554 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
555 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
556 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
557 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 558 | }, |
0f9e006c | 559 | .pflip = { |
0f9e006c | 560 | .page_flip = &r100_page_flip, |
157fa14d | 561 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 562 | }, |
48e7a5f1 DV |
563 | }; |
564 | ||
565 | static struct radeon_asic rs400_asic = { | |
566 | .init = &rs400_init, | |
567 | .fini = &rs400_fini, | |
568 | .suspend = &rs400_suspend, | |
569 | .resume = &rs400_resume, | |
570 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 571 | .asic_reset = &r300_asic_reset, |
124764f1 | 572 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
573 | .gui_idle = &r100_gui_idle, |
574 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, | |
18b53e90 | 575 | .get_allowed_info_register = radeon_invalid_get_allowed_info_register, |
c5b3b850 AD |
576 | .gart = { |
577 | .tlb_flush = &rs400_gart_tlb_flush, | |
cb658906 | 578 | .get_page_entry = &rs400_gart_get_page_entry, |
c5b3b850 AD |
579 | .set_page = &rs400_gart_set_page, |
580 | }, | |
4c87bc26 | 581 | .ring = { |
76a0df85 | 582 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 583 | }, |
b35ea4ab AD |
584 | .irq = { |
585 | .set = &r100_irq_set, | |
586 | .process = &r100_irq_process, | |
587 | }, | |
c79a49ca AD |
588 | .display = { |
589 | .bandwidth_update = &r100_bandwidth_update, | |
590 | .get_vblank_counter = &r100_get_vblank_counter, | |
591 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 592 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 593 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 594 | }, |
27cd7769 AD |
595 | .copy = { |
596 | .blit = &r100_copy_blit, | |
597 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
598 | .dma = &r200_copy_dma, | |
599 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
600 | .copy = &r100_copy_blit, | |
601 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
602 | }, | |
9e6f3d02 AD |
603 | .surface = { |
604 | .set_reg = r100_set_surface_reg, | |
605 | .clear_reg = r100_clear_surface_reg, | |
606 | }, | |
901ea57d AD |
607 | .hpd = { |
608 | .init = &r100_hpd_init, | |
609 | .fini = &r100_hpd_fini, | |
610 | .sense = &r100_hpd_sense, | |
611 | .set_polarity = &r100_hpd_set_polarity, | |
612 | }, | |
a02fa397 AD |
613 | .pm = { |
614 | .misc = &r100_pm_misc, | |
615 | .prepare = &r100_pm_prepare, | |
616 | .finish = &r100_pm_finish, | |
617 | .init_profile = &r100_pm_init_profile, | |
618 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
619 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
620 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
621 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
622 | .set_memory_clock = NULL, | |
623 | .get_pcie_lanes = NULL, | |
624 | .set_pcie_lanes = NULL, | |
625 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 626 | }, |
0f9e006c | 627 | .pflip = { |
0f9e006c | 628 | .page_flip = &r100_page_flip, |
157fa14d | 629 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 630 | }, |
48e7a5f1 DV |
631 | }; |
632 | ||
633 | static struct radeon_asic rs600_asic = { | |
634 | .init = &rs600_init, | |
635 | .fini = &rs600_fini, | |
636 | .suspend = &rs600_suspend, | |
637 | .resume = &rs600_resume, | |
638 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 639 | .asic_reset = &rs600_asic_reset, |
124764f1 | 640 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
641 | .gui_idle = &r100_gui_idle, |
642 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, | |
18b53e90 | 643 | .get_allowed_info_register = radeon_invalid_get_allowed_info_register, |
c5b3b850 AD |
644 | .gart = { |
645 | .tlb_flush = &rs600_gart_tlb_flush, | |
cb658906 | 646 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
647 | .set_page = &rs600_gart_set_page, |
648 | }, | |
4c87bc26 | 649 | .ring = { |
76a0df85 | 650 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 651 | }, |
b35ea4ab AD |
652 | .irq = { |
653 | .set = &rs600_irq_set, | |
654 | .process = &rs600_irq_process, | |
655 | }, | |
c79a49ca AD |
656 | .display = { |
657 | .bandwidth_update = &rs600_bandwidth_update, | |
658 | .get_vblank_counter = &rs600_get_vblank_counter, | |
659 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 660 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 661 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 662 | }, |
27cd7769 AD |
663 | .copy = { |
664 | .blit = &r100_copy_blit, | |
665 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
666 | .dma = &r200_copy_dma, | |
667 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
668 | .copy = &r100_copy_blit, | |
669 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
670 | }, | |
9e6f3d02 AD |
671 | .surface = { |
672 | .set_reg = r100_set_surface_reg, | |
673 | .clear_reg = r100_clear_surface_reg, | |
674 | }, | |
901ea57d AD |
675 | .hpd = { |
676 | .init = &rs600_hpd_init, | |
677 | .fini = &rs600_hpd_fini, | |
678 | .sense = &rs600_hpd_sense, | |
679 | .set_polarity = &rs600_hpd_set_polarity, | |
680 | }, | |
a02fa397 AD |
681 | .pm = { |
682 | .misc = &rs600_pm_misc, | |
683 | .prepare = &rs600_pm_prepare, | |
684 | .finish = &rs600_pm_finish, | |
685 | .init_profile = &r420_pm_init_profile, | |
686 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
687 | .get_engine_clock = &radeon_atom_get_engine_clock, |
688 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
689 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
690 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
691 | .get_pcie_lanes = NULL, | |
692 | .set_pcie_lanes = NULL, | |
693 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 694 | }, |
0f9e006c | 695 | .pflip = { |
0f9e006c | 696 | .page_flip = &rs600_page_flip, |
157fa14d | 697 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 698 | }, |
48e7a5f1 DV |
699 | }; |
700 | ||
701 | static struct radeon_asic rs690_asic = { | |
702 | .init = &rs690_init, | |
703 | .fini = &rs690_fini, | |
704 | .suspend = &rs690_suspend, | |
705 | .resume = &rs690_resume, | |
706 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 707 | .asic_reset = &rs600_asic_reset, |
124764f1 | 708 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
709 | .gui_idle = &r100_gui_idle, |
710 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, | |
18b53e90 | 711 | .get_allowed_info_register = radeon_invalid_get_allowed_info_register, |
c5b3b850 AD |
712 | .gart = { |
713 | .tlb_flush = &rs400_gart_tlb_flush, | |
cb658906 | 714 | .get_page_entry = &rs400_gart_get_page_entry, |
c5b3b850 AD |
715 | .set_page = &rs400_gart_set_page, |
716 | }, | |
4c87bc26 | 717 | .ring = { |
76a0df85 | 718 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 719 | }, |
b35ea4ab AD |
720 | .irq = { |
721 | .set = &rs600_irq_set, | |
722 | .process = &rs600_irq_process, | |
723 | }, | |
c79a49ca AD |
724 | .display = { |
725 | .get_vblank_counter = &rs600_get_vblank_counter, | |
726 | .bandwidth_update = &rs690_bandwidth_update, | |
727 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 728 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 729 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 730 | }, |
27cd7769 AD |
731 | .copy = { |
732 | .blit = &r100_copy_blit, | |
733 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
734 | .dma = &r200_copy_dma, | |
735 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
736 | .copy = &r200_copy_dma, | |
737 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
738 | }, | |
9e6f3d02 AD |
739 | .surface = { |
740 | .set_reg = r100_set_surface_reg, | |
741 | .clear_reg = r100_clear_surface_reg, | |
742 | }, | |
901ea57d AD |
743 | .hpd = { |
744 | .init = &rs600_hpd_init, | |
745 | .fini = &rs600_hpd_fini, | |
746 | .sense = &rs600_hpd_sense, | |
747 | .set_polarity = &rs600_hpd_set_polarity, | |
748 | }, | |
a02fa397 AD |
749 | .pm = { |
750 | .misc = &rs600_pm_misc, | |
751 | .prepare = &rs600_pm_prepare, | |
752 | .finish = &rs600_pm_finish, | |
753 | .init_profile = &r420_pm_init_profile, | |
754 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
755 | .get_engine_clock = &radeon_atom_get_engine_clock, |
756 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
757 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
758 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
759 | .get_pcie_lanes = NULL, | |
760 | .set_pcie_lanes = NULL, | |
761 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 762 | }, |
0f9e006c | 763 | .pflip = { |
0f9e006c | 764 | .page_flip = &rs600_page_flip, |
157fa14d | 765 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 766 | }, |
48e7a5f1 DV |
767 | }; |
768 | ||
769 | static struct radeon_asic rv515_asic = { | |
770 | .init = &rv515_init, | |
771 | .fini = &rv515_fini, | |
772 | .suspend = &rv515_suspend, | |
773 | .resume = &rv515_resume, | |
774 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 775 | .asic_reset = &rs600_asic_reset, |
124764f1 | 776 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
777 | .gui_idle = &r100_gui_idle, |
778 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, | |
18b53e90 | 779 | .get_allowed_info_register = radeon_invalid_get_allowed_info_register, |
c5b3b850 AD |
780 | .gart = { |
781 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
cb658906 | 782 | .get_page_entry = &rv370_pcie_gart_get_page_entry, |
c5b3b850 AD |
783 | .set_page = &rv370_pcie_gart_set_page, |
784 | }, | |
4c87bc26 | 785 | .ring = { |
d8a74e18 | 786 | [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring |
4c87bc26 | 787 | }, |
b35ea4ab AD |
788 | .irq = { |
789 | .set = &rs600_irq_set, | |
790 | .process = &rs600_irq_process, | |
791 | }, | |
c79a49ca AD |
792 | .display = { |
793 | .get_vblank_counter = &rs600_get_vblank_counter, | |
794 | .bandwidth_update = &rv515_bandwidth_update, | |
795 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 796 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 797 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 798 | }, |
27cd7769 AD |
799 | .copy = { |
800 | .blit = &r100_copy_blit, | |
801 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
802 | .dma = &r200_copy_dma, | |
803 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
804 | .copy = &r100_copy_blit, | |
805 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
806 | }, | |
9e6f3d02 AD |
807 | .surface = { |
808 | .set_reg = r100_set_surface_reg, | |
809 | .clear_reg = r100_clear_surface_reg, | |
810 | }, | |
901ea57d AD |
811 | .hpd = { |
812 | .init = &rs600_hpd_init, | |
813 | .fini = &rs600_hpd_fini, | |
814 | .sense = &rs600_hpd_sense, | |
815 | .set_polarity = &rs600_hpd_set_polarity, | |
816 | }, | |
a02fa397 AD |
817 | .pm = { |
818 | .misc = &rs600_pm_misc, | |
819 | .prepare = &rs600_pm_prepare, | |
820 | .finish = &rs600_pm_finish, | |
821 | .init_profile = &r420_pm_init_profile, | |
822 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
823 | .get_engine_clock = &radeon_atom_get_engine_clock, |
824 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
825 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
826 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
827 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
828 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
829 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 830 | }, |
0f9e006c | 831 | .pflip = { |
0f9e006c | 832 | .page_flip = &rs600_page_flip, |
157fa14d | 833 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 834 | }, |
48e7a5f1 DV |
835 | }; |
836 | ||
837 | static struct radeon_asic r520_asic = { | |
838 | .init = &r520_init, | |
839 | .fini = &rv515_fini, | |
840 | .suspend = &rv515_suspend, | |
841 | .resume = &r520_resume, | |
842 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 843 | .asic_reset = &rs600_asic_reset, |
124764f1 | 844 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
845 | .gui_idle = &r100_gui_idle, |
846 | .mc_wait_for_idle = &r520_mc_wait_for_idle, | |
18b53e90 | 847 | .get_allowed_info_register = radeon_invalid_get_allowed_info_register, |
c5b3b850 AD |
848 | .gart = { |
849 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
cb658906 | 850 | .get_page_entry = &rv370_pcie_gart_get_page_entry, |
c5b3b850 AD |
851 | .set_page = &rv370_pcie_gart_set_page, |
852 | }, | |
4c87bc26 | 853 | .ring = { |
d8a74e18 | 854 | [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring |
4c87bc26 | 855 | }, |
b35ea4ab AD |
856 | .irq = { |
857 | .set = &rs600_irq_set, | |
858 | .process = &rs600_irq_process, | |
859 | }, | |
c79a49ca AD |
860 | .display = { |
861 | .bandwidth_update = &rv515_bandwidth_update, | |
862 | .get_vblank_counter = &rs600_get_vblank_counter, | |
863 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 864 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 865 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 866 | }, |
27cd7769 AD |
867 | .copy = { |
868 | .blit = &r100_copy_blit, | |
869 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
870 | .dma = &r200_copy_dma, | |
871 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
872 | .copy = &r100_copy_blit, | |
873 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
874 | }, | |
9e6f3d02 AD |
875 | .surface = { |
876 | .set_reg = r100_set_surface_reg, | |
877 | .clear_reg = r100_clear_surface_reg, | |
878 | }, | |
901ea57d AD |
879 | .hpd = { |
880 | .init = &rs600_hpd_init, | |
881 | .fini = &rs600_hpd_fini, | |
882 | .sense = &rs600_hpd_sense, | |
883 | .set_polarity = &rs600_hpd_set_polarity, | |
884 | }, | |
a02fa397 AD |
885 | .pm = { |
886 | .misc = &rs600_pm_misc, | |
887 | .prepare = &rs600_pm_prepare, | |
888 | .finish = &rs600_pm_finish, | |
889 | .init_profile = &r420_pm_init_profile, | |
890 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
891 | .get_engine_clock = &radeon_atom_get_engine_clock, |
892 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
893 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
894 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
895 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
896 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
897 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 898 | }, |
0f9e006c | 899 | .pflip = { |
0f9e006c | 900 | .page_flip = &rs600_page_flip, |
157fa14d | 901 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 902 | }, |
48e7a5f1 DV |
903 | }; |
904 | ||
d26678da | 905 | static const struct radeon_asic_ring r600_gfx_ring = { |
76a0df85 CK |
906 | .ib_execute = &r600_ring_ib_execute, |
907 | .emit_fence = &r600_fence_ring_emit, | |
908 | .emit_semaphore = &r600_semaphore_ring_emit, | |
909 | .cs_parse = &r600_cs_parse, | |
910 | .ring_test = &r600_ring_test, | |
911 | .ib_test = &r600_ib_test, | |
912 | .is_lockup = &r600_gfx_is_lockup, | |
ea31bf69 AD |
913 | .get_rptr = &r600_gfx_get_rptr, |
914 | .get_wptr = &r600_gfx_get_wptr, | |
915 | .set_wptr = &r600_gfx_set_wptr, | |
76a0df85 CK |
916 | }; |
917 | ||
d26678da | 918 | static const struct radeon_asic_ring r600_dma_ring = { |
76a0df85 CK |
919 | .ib_execute = &r600_dma_ring_ib_execute, |
920 | .emit_fence = &r600_dma_fence_ring_emit, | |
921 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
922 | .cs_parse = &r600_dma_cs_parse, | |
923 | .ring_test = &r600_dma_ring_test, | |
924 | .ib_test = &r600_dma_ib_test, | |
925 | .is_lockup = &r600_dma_is_lockup, | |
2e1e6dad CK |
926 | .get_rptr = &r600_dma_get_rptr, |
927 | .get_wptr = &r600_dma_get_wptr, | |
928 | .set_wptr = &r600_dma_set_wptr, | |
76a0df85 CK |
929 | }; |
930 | ||
48e7a5f1 DV |
931 | static struct radeon_asic r600_asic = { |
932 | .init = &r600_init, | |
933 | .fini = &r600_fini, | |
934 | .suspend = &r600_suspend, | |
935 | .resume = &r600_resume, | |
48e7a5f1 | 936 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 937 | .asic_reset = &r600_asic_reset, |
124764f1 | 938 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
939 | .gui_idle = &r600_gui_idle, |
940 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 941 | .get_xclk = &r600_get_xclk, |
d0418894 | 942 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c6d2ac2c | 943 | .get_allowed_info_register = r600_get_allowed_info_register, |
c5b3b850 AD |
944 | .gart = { |
945 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
cb658906 | 946 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
947 | .set_page = &rs600_gart_set_page, |
948 | }, | |
4c87bc26 | 949 | .ring = { |
76a0df85 CK |
950 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
951 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
4c87bc26 | 952 | }, |
b35ea4ab AD |
953 | .irq = { |
954 | .set = &r600_irq_set, | |
955 | .process = &r600_irq_process, | |
956 | }, | |
c79a49ca AD |
957 | .display = { |
958 | .bandwidth_update = &rv515_bandwidth_update, | |
959 | .get_vblank_counter = &rs600_get_vblank_counter, | |
960 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 961 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 962 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 963 | }, |
27cd7769 | 964 | .copy = { |
8dddb993 | 965 | .blit = &r600_copy_cpdma, |
27cd7769 | 966 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
4d75658b AD |
967 | .dma = &r600_copy_dma, |
968 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 969 | .copy = &r600_copy_cpdma, |
aeea40cb | 970 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
27cd7769 | 971 | }, |
9e6f3d02 AD |
972 | .surface = { |
973 | .set_reg = r600_set_surface_reg, | |
974 | .clear_reg = r600_clear_surface_reg, | |
975 | }, | |
901ea57d AD |
976 | .hpd = { |
977 | .init = &r600_hpd_init, | |
978 | .fini = &r600_hpd_fini, | |
979 | .sense = &r600_hpd_sense, | |
980 | .set_polarity = &r600_hpd_set_polarity, | |
981 | }, | |
a02fa397 AD |
982 | .pm = { |
983 | .misc = &r600_pm_misc, | |
984 | .prepare = &rs600_pm_prepare, | |
985 | .finish = &rs600_pm_finish, | |
986 | .init_profile = &r600_pm_init_profile, | |
987 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
988 | .get_engine_clock = &radeon_atom_get_engine_clock, |
989 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
990 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
991 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
992 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
993 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
994 | .set_clock_gating = NULL, | |
6bd1c385 | 995 | .get_temperature = &rv6xx_get_temp, |
a02fa397 | 996 | }, |
0f9e006c | 997 | .pflip = { |
0f9e006c | 998 | .page_flip = &rs600_page_flip, |
157fa14d | 999 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 1000 | }, |
48e7a5f1 DV |
1001 | }; |
1002 | ||
d26678da | 1003 | static const struct radeon_asic_ring rv6xx_uvd_ring = { |
856754c3 CK |
1004 | .ib_execute = &uvd_v1_0_ib_execute, |
1005 | .emit_fence = &uvd_v1_0_fence_emit, | |
1006 | .emit_semaphore = &uvd_v1_0_semaphore_emit, | |
1007 | .cs_parse = &radeon_uvd_cs_parse, | |
1008 | .ring_test = &uvd_v1_0_ring_test, | |
1009 | .ib_test = &uvd_v1_0_ib_test, | |
1010 | .is_lockup = &radeon_ring_test_lockup, | |
1011 | .get_rptr = &uvd_v1_0_get_rptr, | |
1012 | .get_wptr = &uvd_v1_0_get_wptr, | |
1013 | .set_wptr = &uvd_v1_0_set_wptr, | |
1014 | }; | |
1015 | ||
ca361b65 AD |
1016 | static struct radeon_asic rv6xx_asic = { |
1017 | .init = &r600_init, | |
1018 | .fini = &r600_fini, | |
1019 | .suspend = &r600_suspend, | |
1020 | .resume = &r600_resume, | |
1021 | .vga_set_state = &r600_vga_set_state, | |
1022 | .asic_reset = &r600_asic_reset, | |
124764f1 | 1023 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
ca361b65 AD |
1024 | .gui_idle = &r600_gui_idle, |
1025 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
1026 | .get_xclk = &r600_get_xclk, | |
1027 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | |
c6d2ac2c | 1028 | .get_allowed_info_register = r600_get_allowed_info_register, |
ca361b65 AD |
1029 | .gart = { |
1030 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
cb658906 | 1031 | .get_page_entry = &rs600_gart_get_page_entry, |
ca361b65 AD |
1032 | .set_page = &rs600_gart_set_page, |
1033 | }, | |
1034 | .ring = { | |
76a0df85 CK |
1035 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1036 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
856754c3 | 1037 | [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, |
ca361b65 AD |
1038 | }, |
1039 | .irq = { | |
1040 | .set = &r600_irq_set, | |
1041 | .process = &r600_irq_process, | |
1042 | }, | |
1043 | .display = { | |
1044 | .bandwidth_update = &rv515_bandwidth_update, | |
1045 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1046 | .wait_for_vblank = &avivo_wait_for_vblank, | |
1047 | .set_backlight_level = &atombios_set_backlight_level, | |
1048 | .get_backlight_level = &atombios_get_backlight_level, | |
1049 | }, | |
1050 | .copy = { | |
8dddb993 | 1051 | .blit = &r600_copy_cpdma, |
ca361b65 AD |
1052 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1053 | .dma = &r600_copy_dma, | |
1054 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 1055 | .copy = &r600_copy_cpdma, |
aeea40cb | 1056 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
ca361b65 AD |
1057 | }, |
1058 | .surface = { | |
1059 | .set_reg = r600_set_surface_reg, | |
1060 | .clear_reg = r600_clear_surface_reg, | |
1061 | }, | |
1062 | .hpd = { | |
1063 | .init = &r600_hpd_init, | |
1064 | .fini = &r600_hpd_fini, | |
1065 | .sense = &r600_hpd_sense, | |
1066 | .set_polarity = &r600_hpd_set_polarity, | |
1067 | }, | |
1068 | .pm = { | |
1069 | .misc = &r600_pm_misc, | |
1070 | .prepare = &rs600_pm_prepare, | |
1071 | .finish = &rs600_pm_finish, | |
1072 | .init_profile = &r600_pm_init_profile, | |
1073 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1074 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1075 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1076 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1077 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1078 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1079 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1080 | .set_clock_gating = NULL, | |
1081 | .get_temperature = &rv6xx_get_temp, | |
1b9ba70a | 1082 | .set_uvd_clocks = &r600_set_uvd_clocks, |
ca361b65 | 1083 | }, |
4a6369e9 AD |
1084 | .dpm = { |
1085 | .init = &rv6xx_dpm_init, | |
1086 | .setup_asic = &rv6xx_setup_asic, | |
1087 | .enable = &rv6xx_dpm_enable, | |
a4643ba3 | 1088 | .late_enable = &r600_dpm_late_enable, |
4a6369e9 | 1089 | .disable = &rv6xx_dpm_disable, |
98243917 | 1090 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
4a6369e9 | 1091 | .set_power_state = &rv6xx_dpm_set_power_state, |
98243917 | 1092 | .post_set_power_state = &r600_dpm_post_set_power_state, |
4a6369e9 AD |
1093 | .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, |
1094 | .fini = &rv6xx_dpm_fini, | |
1095 | .get_sclk = &rv6xx_dpm_get_sclk, | |
1096 | .get_mclk = &rv6xx_dpm_get_mclk, | |
1097 | .print_power_state = &rv6xx_dpm_print_power_state, | |
242916a5 | 1098 | .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, |
f4f85a8c | 1099 | .force_performance_level = &rv6xx_dpm_force_performance_level, |
d0a04d3b AD |
1100 | .get_current_sclk = &rv6xx_dpm_get_current_sclk, |
1101 | .get_current_mclk = &rv6xx_dpm_get_current_mclk, | |
4a6369e9 | 1102 | }, |
ca361b65 | 1103 | .pflip = { |
ca361b65 | 1104 | .page_flip = &rs600_page_flip, |
157fa14d | 1105 | .page_flip_pending = &rs600_page_flip_pending, |
ca361b65 AD |
1106 | }, |
1107 | }; | |
1108 | ||
f47299c5 AD |
1109 | static struct radeon_asic rs780_asic = { |
1110 | .init = &r600_init, | |
1111 | .fini = &r600_fini, | |
1112 | .suspend = &r600_suspend, | |
1113 | .resume = &r600_resume, | |
f47299c5 | 1114 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 1115 | .asic_reset = &r600_asic_reset, |
124764f1 | 1116 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1117 | .gui_idle = &r600_gui_idle, |
1118 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 1119 | .get_xclk = &r600_get_xclk, |
d0418894 | 1120 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c6d2ac2c | 1121 | .get_allowed_info_register = r600_get_allowed_info_register, |
c5b3b850 AD |
1122 | .gart = { |
1123 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
cb658906 | 1124 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1125 | .set_page = &rs600_gart_set_page, |
1126 | }, | |
4c87bc26 | 1127 | .ring = { |
76a0df85 CK |
1128 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1129 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
856754c3 | 1130 | [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, |
4c87bc26 | 1131 | }, |
b35ea4ab AD |
1132 | .irq = { |
1133 | .set = &r600_irq_set, | |
1134 | .process = &r600_irq_process, | |
1135 | }, | |
c79a49ca AD |
1136 | .display = { |
1137 | .bandwidth_update = &rs690_bandwidth_update, | |
1138 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1139 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1140 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1141 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1142 | }, |
27cd7769 | 1143 | .copy = { |
8dddb993 | 1144 | .blit = &r600_copy_cpdma, |
27cd7769 | 1145 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
4d75658b AD |
1146 | .dma = &r600_copy_dma, |
1147 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 1148 | .copy = &r600_copy_cpdma, |
aeea40cb | 1149 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
27cd7769 | 1150 | }, |
9e6f3d02 AD |
1151 | .surface = { |
1152 | .set_reg = r600_set_surface_reg, | |
1153 | .clear_reg = r600_clear_surface_reg, | |
1154 | }, | |
901ea57d AD |
1155 | .hpd = { |
1156 | .init = &r600_hpd_init, | |
1157 | .fini = &r600_hpd_fini, | |
1158 | .sense = &r600_hpd_sense, | |
1159 | .set_polarity = &r600_hpd_set_polarity, | |
1160 | }, | |
a02fa397 AD |
1161 | .pm = { |
1162 | .misc = &r600_pm_misc, | |
1163 | .prepare = &rs600_pm_prepare, | |
1164 | .finish = &rs600_pm_finish, | |
1165 | .init_profile = &rs780_pm_init_profile, | |
1166 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1167 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1168 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1169 | .get_memory_clock = NULL, | |
1170 | .set_memory_clock = NULL, | |
1171 | .get_pcie_lanes = NULL, | |
1172 | .set_pcie_lanes = NULL, | |
1173 | .set_clock_gating = NULL, | |
6bd1c385 | 1174 | .get_temperature = &rv6xx_get_temp, |
1b9ba70a | 1175 | .set_uvd_clocks = &r600_set_uvd_clocks, |
a02fa397 | 1176 | }, |
9d67006e AD |
1177 | .dpm = { |
1178 | .init = &rs780_dpm_init, | |
1179 | .setup_asic = &rs780_dpm_setup_asic, | |
1180 | .enable = &rs780_dpm_enable, | |
a4643ba3 | 1181 | .late_enable = &r600_dpm_late_enable, |
9d67006e | 1182 | .disable = &rs780_dpm_disable, |
98243917 | 1183 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
9d67006e | 1184 | .set_power_state = &rs780_dpm_set_power_state, |
98243917 | 1185 | .post_set_power_state = &r600_dpm_post_set_power_state, |
9d67006e AD |
1186 | .display_configuration_changed = &rs780_dpm_display_configuration_changed, |
1187 | .fini = &rs780_dpm_fini, | |
1188 | .get_sclk = &rs780_dpm_get_sclk, | |
1189 | .get_mclk = &rs780_dpm_get_mclk, | |
1190 | .print_power_state = &rs780_dpm_print_power_state, | |
444bddc4 | 1191 | .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, |
63580c3e | 1192 | .force_performance_level = &rs780_dpm_force_performance_level, |
3c94566c AD |
1193 | .get_current_sclk = &rs780_dpm_get_current_sclk, |
1194 | .get_current_mclk = &rs780_dpm_get_current_mclk, | |
9d67006e | 1195 | }, |
0f9e006c | 1196 | .pflip = { |
0f9e006c | 1197 | .page_flip = &rs600_page_flip, |
157fa14d | 1198 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 1199 | }, |
f47299c5 AD |
1200 | }; |
1201 | ||
d26678da | 1202 | static const struct radeon_asic_ring rv770_uvd_ring = { |
e409b128 CK |
1203 | .ib_execute = &uvd_v1_0_ib_execute, |
1204 | .emit_fence = &uvd_v2_2_fence_emit, | |
013ead48 | 1205 | .emit_semaphore = &uvd_v2_2_semaphore_emit, |
76a0df85 | 1206 | .cs_parse = &radeon_uvd_cs_parse, |
e409b128 CK |
1207 | .ring_test = &uvd_v1_0_ring_test, |
1208 | .ib_test = &uvd_v1_0_ib_test, | |
76a0df85 | 1209 | .is_lockup = &radeon_ring_test_lockup, |
e409b128 CK |
1210 | .get_rptr = &uvd_v1_0_get_rptr, |
1211 | .get_wptr = &uvd_v1_0_get_wptr, | |
1212 | .set_wptr = &uvd_v1_0_set_wptr, | |
76a0df85 CK |
1213 | }; |
1214 | ||
48e7a5f1 DV |
1215 | static struct radeon_asic rv770_asic = { |
1216 | .init = &rv770_init, | |
1217 | .fini = &rv770_fini, | |
1218 | .suspend = &rv770_suspend, | |
1219 | .resume = &rv770_resume, | |
a2d07b74 | 1220 | .asic_reset = &r600_asic_reset, |
48e7a5f1 | 1221 | .vga_set_state = &r600_vga_set_state, |
124764f1 | 1222 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1223 | .gui_idle = &r600_gui_idle, |
1224 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 1225 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1226 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c6d2ac2c | 1227 | .get_allowed_info_register = r600_get_allowed_info_register, |
c5b3b850 AD |
1228 | .gart = { |
1229 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
cb658906 | 1230 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1231 | .set_page = &rs600_gart_set_page, |
1232 | }, | |
4c87bc26 | 1233 | .ring = { |
76a0df85 CK |
1234 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1235 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
1236 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1237 | }, |
b35ea4ab AD |
1238 | .irq = { |
1239 | .set = &r600_irq_set, | |
1240 | .process = &r600_irq_process, | |
1241 | }, | |
c79a49ca AD |
1242 | .display = { |
1243 | .bandwidth_update = &rv515_bandwidth_update, | |
1244 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1245 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1246 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1247 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1248 | }, |
27cd7769 | 1249 | .copy = { |
8dddb993 | 1250 | .blit = &r600_copy_cpdma, |
27cd7769 | 1251 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
43fb7787 | 1252 | .dma = &rv770_copy_dma, |
4d75658b | 1253 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
43fb7787 | 1254 | .copy = &rv770_copy_dma, |
2d6cc729 | 1255 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
27cd7769 | 1256 | }, |
9e6f3d02 AD |
1257 | .surface = { |
1258 | .set_reg = r600_set_surface_reg, | |
1259 | .clear_reg = r600_clear_surface_reg, | |
1260 | }, | |
901ea57d AD |
1261 | .hpd = { |
1262 | .init = &r600_hpd_init, | |
1263 | .fini = &r600_hpd_fini, | |
1264 | .sense = &r600_hpd_sense, | |
1265 | .set_polarity = &r600_hpd_set_polarity, | |
1266 | }, | |
a02fa397 AD |
1267 | .pm = { |
1268 | .misc = &rv770_pm_misc, | |
1269 | .prepare = &rs600_pm_prepare, | |
1270 | .finish = &rs600_pm_finish, | |
1271 | .init_profile = &r600_pm_init_profile, | |
1272 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1273 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1274 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1275 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1276 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1277 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1278 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1279 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
ef0e6e65 | 1280 | .set_uvd_clocks = &rv770_set_uvd_clocks, |
6bd1c385 | 1281 | .get_temperature = &rv770_get_temp, |
a02fa397 | 1282 | }, |
66229b20 AD |
1283 | .dpm = { |
1284 | .init = &rv770_dpm_init, | |
1285 | .setup_asic = &rv770_dpm_setup_asic, | |
1286 | .enable = &rv770_dpm_enable, | |
a3f11245 | 1287 | .late_enable = &rv770_dpm_late_enable, |
66229b20 | 1288 | .disable = &rv770_dpm_disable, |
98243917 | 1289 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
66229b20 | 1290 | .set_power_state = &rv770_dpm_set_power_state, |
98243917 | 1291 | .post_set_power_state = &r600_dpm_post_set_power_state, |
66229b20 AD |
1292 | .display_configuration_changed = &rv770_dpm_display_configuration_changed, |
1293 | .fini = &rv770_dpm_fini, | |
1294 | .get_sclk = &rv770_dpm_get_sclk, | |
1295 | .get_mclk = &rv770_dpm_get_mclk, | |
1296 | .print_power_state = &rv770_dpm_print_power_state, | |
bd210d11 | 1297 | .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1298 | .force_performance_level = &rv770_dpm_force_performance_level, |
b06195d9 | 1299 | .vblank_too_short = &rv770_dpm_vblank_too_short, |
296deb71 AD |
1300 | .get_current_sclk = &rv770_dpm_get_current_sclk, |
1301 | .get_current_mclk = &rv770_dpm_get_current_mclk, | |
66229b20 | 1302 | }, |
0f9e006c | 1303 | .pflip = { |
0f9e006c | 1304 | .page_flip = &rv770_page_flip, |
157fa14d | 1305 | .page_flip_pending = &rv770_page_flip_pending, |
0f9e006c | 1306 | }, |
48e7a5f1 DV |
1307 | }; |
1308 | ||
d26678da | 1309 | static const struct radeon_asic_ring evergreen_gfx_ring = { |
76a0df85 CK |
1310 | .ib_execute = &evergreen_ring_ib_execute, |
1311 | .emit_fence = &r600_fence_ring_emit, | |
1312 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1313 | .cs_parse = &evergreen_cs_parse, | |
1314 | .ring_test = &r600_ring_test, | |
1315 | .ib_test = &r600_ib_test, | |
1316 | .is_lockup = &evergreen_gfx_is_lockup, | |
ea31bf69 AD |
1317 | .get_rptr = &r600_gfx_get_rptr, |
1318 | .get_wptr = &r600_gfx_get_wptr, | |
1319 | .set_wptr = &r600_gfx_set_wptr, | |
76a0df85 CK |
1320 | }; |
1321 | ||
d26678da | 1322 | static const struct radeon_asic_ring evergreen_dma_ring = { |
76a0df85 CK |
1323 | .ib_execute = &evergreen_dma_ring_ib_execute, |
1324 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1325 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1326 | .cs_parse = &evergreen_dma_cs_parse, | |
1327 | .ring_test = &r600_dma_ring_test, | |
1328 | .ib_test = &r600_dma_ib_test, | |
1329 | .is_lockup = &evergreen_dma_is_lockup, | |
2e1e6dad CK |
1330 | .get_rptr = &r600_dma_get_rptr, |
1331 | .get_wptr = &r600_dma_get_wptr, | |
1332 | .set_wptr = &r600_dma_set_wptr, | |
76a0df85 CK |
1333 | }; |
1334 | ||
48e7a5f1 DV |
1335 | static struct radeon_asic evergreen_asic = { |
1336 | .init = &evergreen_init, | |
1337 | .fini = &evergreen_fini, | |
1338 | .suspend = &evergreen_suspend, | |
1339 | .resume = &evergreen_resume, | |
a2d07b74 | 1340 | .asic_reset = &evergreen_asic_reset, |
48e7a5f1 | 1341 | .vga_set_state = &r600_vga_set_state, |
124764f1 | 1342 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1343 | .gui_idle = &r600_gui_idle, |
1344 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1345 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1346 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
ff609975 | 1347 | .get_allowed_info_register = evergreen_get_allowed_info_register, |
c5b3b850 AD |
1348 | .gart = { |
1349 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
cb658906 | 1350 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1351 | .set_page = &rs600_gart_set_page, |
1352 | }, | |
4c87bc26 | 1353 | .ring = { |
76a0df85 CK |
1354 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1355 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1356 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1357 | }, |
b35ea4ab AD |
1358 | .irq = { |
1359 | .set = &evergreen_irq_set, | |
1360 | .process = &evergreen_irq_process, | |
1361 | }, | |
c79a49ca AD |
1362 | .display = { |
1363 | .bandwidth_update = &evergreen_bandwidth_update, | |
1364 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1365 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1366 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1367 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1368 | }, |
27cd7769 | 1369 | .copy = { |
8dddb993 | 1370 | .blit = &r600_copy_cpdma, |
27cd7769 | 1371 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1372 | .dma = &evergreen_copy_dma, |
1373 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1374 | .copy = &evergreen_copy_dma, |
1375 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1376 | }, |
9e6f3d02 AD |
1377 | .surface = { |
1378 | .set_reg = r600_set_surface_reg, | |
1379 | .clear_reg = r600_clear_surface_reg, | |
1380 | }, | |
901ea57d AD |
1381 | .hpd = { |
1382 | .init = &evergreen_hpd_init, | |
1383 | .fini = &evergreen_hpd_fini, | |
1384 | .sense = &evergreen_hpd_sense, | |
1385 | .set_polarity = &evergreen_hpd_set_polarity, | |
1386 | }, | |
a02fa397 AD |
1387 | .pm = { |
1388 | .misc = &evergreen_pm_misc, | |
1389 | .prepare = &evergreen_pm_prepare, | |
1390 | .finish = &evergreen_pm_finish, | |
1391 | .init_profile = &r600_pm_init_profile, | |
1392 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1393 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1394 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1395 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1396 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1397 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1398 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1399 | .set_clock_gating = NULL, | |
a8b4925c | 1400 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1401 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1402 | }, |
dc50ba7f AD |
1403 | .dpm = { |
1404 | .init = &cypress_dpm_init, | |
1405 | .setup_asic = &cypress_dpm_setup_asic, | |
1406 | .enable = &cypress_dpm_enable, | |
a3f11245 | 1407 | .late_enable = &rv770_dpm_late_enable, |
dc50ba7f | 1408 | .disable = &cypress_dpm_disable, |
98243917 | 1409 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
dc50ba7f | 1410 | .set_power_state = &cypress_dpm_set_power_state, |
98243917 | 1411 | .post_set_power_state = &r600_dpm_post_set_power_state, |
dc50ba7f AD |
1412 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1413 | .fini = &cypress_dpm_fini, | |
1414 | .get_sclk = &rv770_dpm_get_sclk, | |
1415 | .get_mclk = &rv770_dpm_get_mclk, | |
1416 | .print_power_state = &rv770_dpm_print_power_state, | |
bd210d11 | 1417 | .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1418 | .force_performance_level = &rv770_dpm_force_performance_level, |
d0b54bdc | 1419 | .vblank_too_short = &cypress_dpm_vblank_too_short, |
296deb71 AD |
1420 | .get_current_sclk = &rv770_dpm_get_current_sclk, |
1421 | .get_current_mclk = &rv770_dpm_get_current_mclk, | |
dc50ba7f | 1422 | }, |
0f9e006c | 1423 | .pflip = { |
0f9e006c | 1424 | .page_flip = &evergreen_page_flip, |
157fa14d | 1425 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1426 | }, |
48e7a5f1 DV |
1427 | }; |
1428 | ||
958261d1 AD |
1429 | static struct radeon_asic sumo_asic = { |
1430 | .init = &evergreen_init, | |
1431 | .fini = &evergreen_fini, | |
1432 | .suspend = &evergreen_suspend, | |
1433 | .resume = &evergreen_resume, | |
958261d1 AD |
1434 | .asic_reset = &evergreen_asic_reset, |
1435 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1436 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1437 | .gui_idle = &r600_gui_idle, |
1438 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1439 | .get_xclk = &r600_get_xclk, |
d0418894 | 1440 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
ff609975 | 1441 | .get_allowed_info_register = evergreen_get_allowed_info_register, |
c5b3b850 AD |
1442 | .gart = { |
1443 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
cb658906 | 1444 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1445 | .set_page = &rs600_gart_set_page, |
1446 | }, | |
4c87bc26 | 1447 | .ring = { |
76a0df85 CK |
1448 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1449 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1450 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1451 | }, |
b35ea4ab AD |
1452 | .irq = { |
1453 | .set = &evergreen_irq_set, | |
1454 | .process = &evergreen_irq_process, | |
1455 | }, | |
c79a49ca AD |
1456 | .display = { |
1457 | .bandwidth_update = &evergreen_bandwidth_update, | |
1458 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1459 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1460 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1461 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1462 | }, |
27cd7769 | 1463 | .copy = { |
8dddb993 | 1464 | .blit = &r600_copy_cpdma, |
27cd7769 | 1465 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1466 | .dma = &evergreen_copy_dma, |
1467 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1468 | .copy = &evergreen_copy_dma, |
1469 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1470 | }, |
9e6f3d02 AD |
1471 | .surface = { |
1472 | .set_reg = r600_set_surface_reg, | |
1473 | .clear_reg = r600_clear_surface_reg, | |
1474 | }, | |
901ea57d AD |
1475 | .hpd = { |
1476 | .init = &evergreen_hpd_init, | |
1477 | .fini = &evergreen_hpd_fini, | |
1478 | .sense = &evergreen_hpd_sense, | |
1479 | .set_polarity = &evergreen_hpd_set_polarity, | |
1480 | }, | |
a02fa397 AD |
1481 | .pm = { |
1482 | .misc = &evergreen_pm_misc, | |
1483 | .prepare = &evergreen_pm_prepare, | |
1484 | .finish = &evergreen_pm_finish, | |
1485 | .init_profile = &sumo_pm_init_profile, | |
1486 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1487 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1488 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1489 | .get_memory_clock = NULL, | |
1490 | .set_memory_clock = NULL, | |
1491 | .get_pcie_lanes = NULL, | |
1492 | .set_pcie_lanes = NULL, | |
1493 | .set_clock_gating = NULL, | |
23d33ba3 | 1494 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
6bd1c385 | 1495 | .get_temperature = &sumo_get_temp, |
a02fa397 | 1496 | }, |
80ea2c12 AD |
1497 | .dpm = { |
1498 | .init = &sumo_dpm_init, | |
1499 | .setup_asic = &sumo_dpm_setup_asic, | |
1500 | .enable = &sumo_dpm_enable, | |
14ec9fab | 1501 | .late_enable = &sumo_dpm_late_enable, |
80ea2c12 | 1502 | .disable = &sumo_dpm_disable, |
422a56bc | 1503 | .pre_set_power_state = &sumo_dpm_pre_set_power_state, |
80ea2c12 | 1504 | .set_power_state = &sumo_dpm_set_power_state, |
422a56bc | 1505 | .post_set_power_state = &sumo_dpm_post_set_power_state, |
80ea2c12 AD |
1506 | .display_configuration_changed = &sumo_dpm_display_configuration_changed, |
1507 | .fini = &sumo_dpm_fini, | |
1508 | .get_sclk = &sumo_dpm_get_sclk, | |
1509 | .get_mclk = &sumo_dpm_get_mclk, | |
1510 | .print_power_state = &sumo_dpm_print_power_state, | |
fb70160c | 1511 | .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, |
5d5e5591 | 1512 | .force_performance_level = &sumo_dpm_force_performance_level, |
2f8e1eb7 AD |
1513 | .get_current_sclk = &sumo_dpm_get_current_sclk, |
1514 | .get_current_mclk = &sumo_dpm_get_current_mclk, | |
c57a8308 | 1515 | .get_current_vddc = &sumo_dpm_get_current_vddc, |
80ea2c12 | 1516 | }, |
0f9e006c | 1517 | .pflip = { |
0f9e006c | 1518 | .page_flip = &evergreen_page_flip, |
157fa14d | 1519 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1520 | }, |
958261d1 AD |
1521 | }; |
1522 | ||
a43b7665 AD |
1523 | static struct radeon_asic btc_asic = { |
1524 | .init = &evergreen_init, | |
1525 | .fini = &evergreen_fini, | |
1526 | .suspend = &evergreen_suspend, | |
1527 | .resume = &evergreen_resume, | |
a43b7665 AD |
1528 | .asic_reset = &evergreen_asic_reset, |
1529 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1530 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1531 | .gui_idle = &r600_gui_idle, |
1532 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1533 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1534 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
ff609975 | 1535 | .get_allowed_info_register = evergreen_get_allowed_info_register, |
c5b3b850 AD |
1536 | .gart = { |
1537 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
cb658906 | 1538 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1539 | .set_page = &rs600_gart_set_page, |
1540 | }, | |
4c87bc26 | 1541 | .ring = { |
76a0df85 CK |
1542 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1543 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1544 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1545 | }, |
b35ea4ab AD |
1546 | .irq = { |
1547 | .set = &evergreen_irq_set, | |
1548 | .process = &evergreen_irq_process, | |
1549 | }, | |
c79a49ca AD |
1550 | .display = { |
1551 | .bandwidth_update = &evergreen_bandwidth_update, | |
1552 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1553 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1554 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1555 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1556 | }, |
27cd7769 | 1557 | .copy = { |
8dddb993 | 1558 | .blit = &r600_copy_cpdma, |
27cd7769 | 1559 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1560 | .dma = &evergreen_copy_dma, |
1561 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1562 | .copy = &evergreen_copy_dma, |
1563 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1564 | }, |
9e6f3d02 AD |
1565 | .surface = { |
1566 | .set_reg = r600_set_surface_reg, | |
1567 | .clear_reg = r600_clear_surface_reg, | |
1568 | }, | |
901ea57d AD |
1569 | .hpd = { |
1570 | .init = &evergreen_hpd_init, | |
1571 | .fini = &evergreen_hpd_fini, | |
1572 | .sense = &evergreen_hpd_sense, | |
1573 | .set_polarity = &evergreen_hpd_set_polarity, | |
1574 | }, | |
a02fa397 AD |
1575 | .pm = { |
1576 | .misc = &evergreen_pm_misc, | |
1577 | .prepare = &evergreen_pm_prepare, | |
1578 | .finish = &evergreen_pm_finish, | |
27810fb2 | 1579 | .init_profile = &btc_pm_init_profile, |
a02fa397 | 1580 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
798bcf73 AD |
1581 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1582 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1583 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1584 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1585 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1586 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
798bcf73 | 1587 | .set_clock_gating = NULL, |
a8b4925c | 1588 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1589 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1590 | }, |
6596afd4 AD |
1591 | .dpm = { |
1592 | .init = &btc_dpm_init, | |
1593 | .setup_asic = &btc_dpm_setup_asic, | |
1594 | .enable = &btc_dpm_enable, | |
a3f11245 | 1595 | .late_enable = &rv770_dpm_late_enable, |
6596afd4 | 1596 | .disable = &btc_dpm_disable, |
e8a9539f | 1597 | .pre_set_power_state = &btc_dpm_pre_set_power_state, |
6596afd4 | 1598 | .set_power_state = &btc_dpm_set_power_state, |
e8a9539f | 1599 | .post_set_power_state = &btc_dpm_post_set_power_state, |
6596afd4 AD |
1600 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1601 | .fini = &btc_dpm_fini, | |
e8a9539f AD |
1602 | .get_sclk = &btc_dpm_get_sclk, |
1603 | .get_mclk = &btc_dpm_get_mclk, | |
6596afd4 | 1604 | .print_power_state = &rv770_dpm_print_power_state, |
9f3f63f2 | 1605 | .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1606 | .force_performance_level = &rv770_dpm_force_performance_level, |
a84301c6 | 1607 | .vblank_too_short = &btc_dpm_vblank_too_short, |
99550ee9 AD |
1608 | .get_current_sclk = &btc_dpm_get_current_sclk, |
1609 | .get_current_mclk = &btc_dpm_get_current_mclk, | |
6596afd4 | 1610 | }, |
0f9e006c | 1611 | .pflip = { |
0f9e006c | 1612 | .page_flip = &evergreen_page_flip, |
157fa14d | 1613 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1614 | }, |
a43b7665 AD |
1615 | }; |
1616 | ||
d26678da | 1617 | static const struct radeon_asic_ring cayman_gfx_ring = { |
76a0df85 CK |
1618 | .ib_execute = &cayman_ring_ib_execute, |
1619 | .ib_parse = &evergreen_ib_parse, | |
1620 | .emit_fence = &cayman_fence_ring_emit, | |
1621 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1622 | .cs_parse = &evergreen_cs_parse, | |
1623 | .ring_test = &r600_ring_test, | |
1624 | .ib_test = &r600_ib_test, | |
1625 | .is_lockup = &cayman_gfx_is_lockup, | |
1626 | .vm_flush = &cayman_vm_flush, | |
ea31bf69 AD |
1627 | .get_rptr = &cayman_gfx_get_rptr, |
1628 | .get_wptr = &cayman_gfx_get_wptr, | |
1629 | .set_wptr = &cayman_gfx_set_wptr, | |
76a0df85 CK |
1630 | }; |
1631 | ||
d26678da | 1632 | static const struct radeon_asic_ring cayman_dma_ring = { |
76a0df85 CK |
1633 | .ib_execute = &cayman_dma_ring_ib_execute, |
1634 | .ib_parse = &evergreen_dma_ib_parse, | |
1635 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1636 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1637 | .cs_parse = &evergreen_dma_cs_parse, | |
1638 | .ring_test = &r600_dma_ring_test, | |
1639 | .ib_test = &r600_dma_ib_test, | |
1640 | .is_lockup = &cayman_dma_is_lockup, | |
1641 | .vm_flush = &cayman_dma_vm_flush, | |
ea31bf69 AD |
1642 | .get_rptr = &cayman_dma_get_rptr, |
1643 | .get_wptr = &cayman_dma_get_wptr, | |
1644 | .set_wptr = &cayman_dma_set_wptr | |
76a0df85 CK |
1645 | }; |
1646 | ||
d26678da | 1647 | static const struct radeon_asic_ring cayman_uvd_ring = { |
e409b128 CK |
1648 | .ib_execute = &uvd_v1_0_ib_execute, |
1649 | .emit_fence = &uvd_v2_2_fence_emit, | |
1650 | .emit_semaphore = &uvd_v3_1_semaphore_emit, | |
76a0df85 | 1651 | .cs_parse = &radeon_uvd_cs_parse, |
e409b128 CK |
1652 | .ring_test = &uvd_v1_0_ring_test, |
1653 | .ib_test = &uvd_v1_0_ib_test, | |
76a0df85 | 1654 | .is_lockup = &radeon_ring_test_lockup, |
e409b128 CK |
1655 | .get_rptr = &uvd_v1_0_get_rptr, |
1656 | .get_wptr = &uvd_v1_0_get_wptr, | |
1657 | .set_wptr = &uvd_v1_0_set_wptr, | |
76a0df85 CK |
1658 | }; |
1659 | ||
e3487629 AD |
1660 | static struct radeon_asic cayman_asic = { |
1661 | .init = &cayman_init, | |
1662 | .fini = &cayman_fini, | |
1663 | .suspend = &cayman_suspend, | |
1664 | .resume = &cayman_resume, | |
e3487629 AD |
1665 | .asic_reset = &cayman_asic_reset, |
1666 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1667 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1668 | .gui_idle = &r600_gui_idle, |
1669 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1670 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1671 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
e66582f9 | 1672 | .get_allowed_info_register = cayman_get_allowed_info_register, |
c5b3b850 AD |
1673 | .gart = { |
1674 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
cb658906 | 1675 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1676 | .set_page = &rs600_gart_set_page, |
1677 | }, | |
05b07147 CK |
1678 | .vm = { |
1679 | .init = &cayman_vm_init, | |
1680 | .fini = &cayman_vm_fini, | |
03f62abd CK |
1681 | .copy_pages = &cayman_dma_vm_copy_pages, |
1682 | .write_pages = &cayman_dma_vm_write_pages, | |
1683 | .set_pages = &cayman_dma_vm_set_pages, | |
1684 | .pad_ib = &cayman_dma_vm_pad_ib, | |
05b07147 | 1685 | }, |
4c87bc26 | 1686 | .ring = { |
76a0df85 CK |
1687 | [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, |
1688 | [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, | |
1689 | [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, | |
1690 | [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, | |
1691 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, | |
1692 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
4c87bc26 | 1693 | }, |
b35ea4ab AD |
1694 | .irq = { |
1695 | .set = &evergreen_irq_set, | |
1696 | .process = &evergreen_irq_process, | |
1697 | }, | |
c79a49ca AD |
1698 | .display = { |
1699 | .bandwidth_update = &evergreen_bandwidth_update, | |
1700 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1701 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1702 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1703 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1704 | }, |
27cd7769 | 1705 | .copy = { |
8dddb993 | 1706 | .blit = &r600_copy_cpdma, |
27cd7769 | 1707 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
f60cbd11 AD |
1708 | .dma = &evergreen_copy_dma, |
1709 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1710 | .copy = &evergreen_copy_dma, |
1711 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1712 | }, |
9e6f3d02 AD |
1713 | .surface = { |
1714 | .set_reg = r600_set_surface_reg, | |
1715 | .clear_reg = r600_clear_surface_reg, | |
1716 | }, | |
901ea57d AD |
1717 | .hpd = { |
1718 | .init = &evergreen_hpd_init, | |
1719 | .fini = &evergreen_hpd_fini, | |
1720 | .sense = &evergreen_hpd_sense, | |
1721 | .set_polarity = &evergreen_hpd_set_polarity, | |
1722 | }, | |
a02fa397 AD |
1723 | .pm = { |
1724 | .misc = &evergreen_pm_misc, | |
1725 | .prepare = &evergreen_pm_prepare, | |
1726 | .finish = &evergreen_pm_finish, | |
27810fb2 | 1727 | .init_profile = &btc_pm_init_profile, |
a02fa397 | 1728 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
798bcf73 AD |
1729 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1730 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1731 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1732 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1733 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1734 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
798bcf73 | 1735 | .set_clock_gating = NULL, |
a8b4925c | 1736 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1737 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1738 | }, |
69e0b57a AD |
1739 | .dpm = { |
1740 | .init = &ni_dpm_init, | |
1741 | .setup_asic = &ni_dpm_setup_asic, | |
1742 | .enable = &ni_dpm_enable, | |
a3f11245 | 1743 | .late_enable = &rv770_dpm_late_enable, |
69e0b57a | 1744 | .disable = &ni_dpm_disable, |
fee3d744 | 1745 | .pre_set_power_state = &ni_dpm_pre_set_power_state, |
69e0b57a | 1746 | .set_power_state = &ni_dpm_set_power_state, |
fee3d744 | 1747 | .post_set_power_state = &ni_dpm_post_set_power_state, |
69e0b57a AD |
1748 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1749 | .fini = &ni_dpm_fini, | |
1750 | .get_sclk = &ni_dpm_get_sclk, | |
1751 | .get_mclk = &ni_dpm_get_mclk, | |
1752 | .print_power_state = &ni_dpm_print_power_state, | |
bdf0c4f0 | 1753 | .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, |
170a47f0 | 1754 | .force_performance_level = &ni_dpm_force_performance_level, |
76ad73e5 | 1755 | .vblank_too_short = &ni_dpm_vblank_too_short, |
1d633e3a AD |
1756 | .get_current_sclk = &ni_dpm_get_current_sclk, |
1757 | .get_current_mclk = &ni_dpm_get_current_mclk, | |
69e0b57a | 1758 | }, |
0f9e006c | 1759 | .pflip = { |
0f9e006c | 1760 | .page_flip = &evergreen_page_flip, |
157fa14d | 1761 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1762 | }, |
e3487629 AD |
1763 | }; |
1764 | ||
d26678da | 1765 | static const struct radeon_asic_ring trinity_vce_ring = { |
a918efab CK |
1766 | .ib_execute = &radeon_vce_ib_execute, |
1767 | .emit_fence = &radeon_vce_fence_emit, | |
1768 | .emit_semaphore = &radeon_vce_semaphore_emit, | |
1769 | .cs_parse = &radeon_vce_cs_parse, | |
1770 | .ring_test = &radeon_vce_ring_test, | |
1771 | .ib_test = &radeon_vce_ib_test, | |
1772 | .is_lockup = &radeon_ring_test_lockup, | |
1773 | .get_rptr = &vce_v1_0_get_rptr, | |
1774 | .get_wptr = &vce_v1_0_get_wptr, | |
1775 | .set_wptr = &vce_v1_0_set_wptr, | |
1776 | }; | |
1777 | ||
be63fe8c AD |
1778 | static struct radeon_asic trinity_asic = { |
1779 | .init = &cayman_init, | |
1780 | .fini = &cayman_fini, | |
1781 | .suspend = &cayman_suspend, | |
1782 | .resume = &cayman_resume, | |
be63fe8c AD |
1783 | .asic_reset = &cayman_asic_reset, |
1784 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1785 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
be63fe8c AD |
1786 | .gui_idle = &r600_gui_idle, |
1787 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1788 | .get_xclk = &r600_get_xclk, |
d0418894 | 1789 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
e66582f9 | 1790 | .get_allowed_info_register = cayman_get_allowed_info_register, |
be63fe8c AD |
1791 | .gart = { |
1792 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
cb658906 | 1793 | .get_page_entry = &rs600_gart_get_page_entry, |
be63fe8c AD |
1794 | .set_page = &rs600_gart_set_page, |
1795 | }, | |
05b07147 CK |
1796 | .vm = { |
1797 | .init = &cayman_vm_init, | |
1798 | .fini = &cayman_vm_fini, | |
03f62abd CK |
1799 | .copy_pages = &cayman_dma_vm_copy_pages, |
1800 | .write_pages = &cayman_dma_vm_write_pages, | |
1801 | .set_pages = &cayman_dma_vm_set_pages, | |
1802 | .pad_ib = &cayman_dma_vm_pad_ib, | |
05b07147 | 1803 | }, |
be63fe8c | 1804 | .ring = { |
76a0df85 CK |
1805 | [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, |
1806 | [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, | |
1807 | [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, | |
1808 | [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, | |
1809 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, | |
1810 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
a918efab CK |
1811 | [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, |
1812 | [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, | |
be63fe8c AD |
1813 | }, |
1814 | .irq = { | |
1815 | .set = &evergreen_irq_set, | |
1816 | .process = &evergreen_irq_process, | |
1817 | }, | |
1818 | .display = { | |
1819 | .bandwidth_update = &dce6_bandwidth_update, | |
1820 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1821 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1822 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1823 | .get_backlight_level = &atombios_get_backlight_level, |
be63fe8c AD |
1824 | }, |
1825 | .copy = { | |
8dddb993 | 1826 | .blit = &r600_copy_cpdma, |
be63fe8c | 1827 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
f60cbd11 AD |
1828 | .dma = &evergreen_copy_dma, |
1829 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1830 | .copy = &evergreen_copy_dma, |
1831 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
be63fe8c AD |
1832 | }, |
1833 | .surface = { | |
1834 | .set_reg = r600_set_surface_reg, | |
1835 | .clear_reg = r600_clear_surface_reg, | |
1836 | }, | |
1837 | .hpd = { | |
1838 | .init = &evergreen_hpd_init, | |
1839 | .fini = &evergreen_hpd_fini, | |
1840 | .sense = &evergreen_hpd_sense, | |
1841 | .set_polarity = &evergreen_hpd_set_polarity, | |
1842 | }, | |
1843 | .pm = { | |
1844 | .misc = &evergreen_pm_misc, | |
1845 | .prepare = &evergreen_pm_prepare, | |
1846 | .finish = &evergreen_pm_finish, | |
1847 | .init_profile = &sumo_pm_init_profile, | |
1848 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1849 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1850 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1851 | .get_memory_clock = NULL, | |
1852 | .set_memory_clock = NULL, | |
1853 | .get_pcie_lanes = NULL, | |
1854 | .set_pcie_lanes = NULL, | |
1855 | .set_clock_gating = NULL, | |
23d33ba3 | 1856 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
0fda42ac | 1857 | .set_vce_clocks = &tn_set_vce_clocks, |
29a15221 | 1858 | .get_temperature = &tn_get_temp, |
be63fe8c | 1859 | }, |
d70229f7 AD |
1860 | .dpm = { |
1861 | .init = &trinity_dpm_init, | |
1862 | .setup_asic = &trinity_dpm_setup_asic, | |
1863 | .enable = &trinity_dpm_enable, | |
bda44c1a | 1864 | .late_enable = &trinity_dpm_late_enable, |
d70229f7 | 1865 | .disable = &trinity_dpm_disable, |
a284c48a | 1866 | .pre_set_power_state = &trinity_dpm_pre_set_power_state, |
d70229f7 | 1867 | .set_power_state = &trinity_dpm_set_power_state, |
a284c48a | 1868 | .post_set_power_state = &trinity_dpm_post_set_power_state, |
d70229f7 AD |
1869 | .display_configuration_changed = &trinity_dpm_display_configuration_changed, |
1870 | .fini = &trinity_dpm_fini, | |
1871 | .get_sclk = &trinity_dpm_get_sclk, | |
1872 | .get_mclk = &trinity_dpm_get_mclk, | |
1873 | .print_power_state = &trinity_dpm_print_power_state, | |
490ab931 | 1874 | .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, |
9b5de596 | 1875 | .force_performance_level = &trinity_dpm_force_performance_level, |
11877060 | 1876 | .enable_bapm = &trinity_dpm_enable_bapm, |
7ce9cdae AD |
1877 | .get_current_sclk = &trinity_dpm_get_current_sclk, |
1878 | .get_current_mclk = &trinity_dpm_get_current_mclk, | |
d70229f7 | 1879 | }, |
be63fe8c | 1880 | .pflip = { |
be63fe8c | 1881 | .page_flip = &evergreen_page_flip, |
157fa14d | 1882 | .page_flip_pending = &evergreen_page_flip_pending, |
be63fe8c AD |
1883 | }, |
1884 | }; | |
1885 | ||
d26678da | 1886 | static const struct radeon_asic_ring si_gfx_ring = { |
76a0df85 CK |
1887 | .ib_execute = &si_ring_ib_execute, |
1888 | .ib_parse = &si_ib_parse, | |
1889 | .emit_fence = &si_fence_ring_emit, | |
1890 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1891 | .cs_parse = NULL, | |
1892 | .ring_test = &r600_ring_test, | |
1893 | .ib_test = &r600_ib_test, | |
1894 | .is_lockup = &si_gfx_is_lockup, | |
1895 | .vm_flush = &si_vm_flush, | |
ea31bf69 AD |
1896 | .get_rptr = &cayman_gfx_get_rptr, |
1897 | .get_wptr = &cayman_gfx_get_wptr, | |
1898 | .set_wptr = &cayman_gfx_set_wptr, | |
76a0df85 CK |
1899 | }; |
1900 | ||
d26678da | 1901 | static const struct radeon_asic_ring si_dma_ring = { |
76a0df85 CK |
1902 | .ib_execute = &cayman_dma_ring_ib_execute, |
1903 | .ib_parse = &evergreen_dma_ib_parse, | |
1904 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1905 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1906 | .cs_parse = NULL, | |
1907 | .ring_test = &r600_dma_ring_test, | |
1908 | .ib_test = &r600_dma_ib_test, | |
1909 | .is_lockup = &si_dma_is_lockup, | |
1910 | .vm_flush = &si_dma_vm_flush, | |
ea31bf69 AD |
1911 | .get_rptr = &cayman_dma_get_rptr, |
1912 | .get_wptr = &cayman_dma_get_wptr, | |
1913 | .set_wptr = &cayman_dma_set_wptr, | |
76a0df85 CK |
1914 | }; |
1915 | ||
02779c08 AD |
1916 | static struct radeon_asic si_asic = { |
1917 | .init = &si_init, | |
1918 | .fini = &si_fini, | |
1919 | .suspend = &si_suspend, | |
1920 | .resume = &si_resume, | |
02779c08 AD |
1921 | .asic_reset = &si_asic_reset, |
1922 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1923 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
02779c08 AD |
1924 | .gui_idle = &r600_gui_idle, |
1925 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1926 | .get_xclk = &si_get_xclk, |
d0418894 | 1927 | .get_gpu_clock_counter = &si_get_gpu_clock_counter, |
4af692f6 | 1928 | .get_allowed_info_register = si_get_allowed_info_register, |
02779c08 AD |
1929 | .gart = { |
1930 | .tlb_flush = &si_pcie_gart_tlb_flush, | |
cb658906 | 1931 | .get_page_entry = &rs600_gart_get_page_entry, |
02779c08 AD |
1932 | .set_page = &rs600_gart_set_page, |
1933 | }, | |
05b07147 CK |
1934 | .vm = { |
1935 | .init = &si_vm_init, | |
1936 | .fini = &si_vm_fini, | |
03f62abd CK |
1937 | .copy_pages = &si_dma_vm_copy_pages, |
1938 | .write_pages = &si_dma_vm_write_pages, | |
1939 | .set_pages = &si_dma_vm_set_pages, | |
1940 | .pad_ib = &cayman_dma_vm_pad_ib, | |
05b07147 | 1941 | }, |
02779c08 | 1942 | .ring = { |
76a0df85 CK |
1943 | [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, |
1944 | [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, | |
1945 | [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, | |
1946 | [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, | |
1947 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, | |
1948 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
a918efab CK |
1949 | [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring, |
1950 | [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring, | |
02779c08 AD |
1951 | }, |
1952 | .irq = { | |
1953 | .set = &si_irq_set, | |
1954 | .process = &si_irq_process, | |
1955 | }, | |
1956 | .display = { | |
1957 | .bandwidth_update = &dce6_bandwidth_update, | |
1958 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1959 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1960 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1961 | .get_backlight_level = &atombios_get_backlight_level, |
02779c08 AD |
1962 | }, |
1963 | .copy = { | |
5c722739 | 1964 | .blit = &r600_copy_cpdma, |
02779c08 | 1965 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
8c5fd7ef AD |
1966 | .dma = &si_copy_dma, |
1967 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1968 | .copy = &si_copy_dma, |
1969 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
02779c08 AD |
1970 | }, |
1971 | .surface = { | |
1972 | .set_reg = r600_set_surface_reg, | |
1973 | .clear_reg = r600_clear_surface_reg, | |
1974 | }, | |
1975 | .hpd = { | |
1976 | .init = &evergreen_hpd_init, | |
1977 | .fini = &evergreen_hpd_fini, | |
1978 | .sense = &evergreen_hpd_sense, | |
1979 | .set_polarity = &evergreen_hpd_set_polarity, | |
1980 | }, | |
1981 | .pm = { | |
1982 | .misc = &evergreen_pm_misc, | |
1983 | .prepare = &evergreen_pm_prepare, | |
1984 | .finish = &evergreen_pm_finish, | |
1985 | .init_profile = &sumo_pm_init_profile, | |
1986 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1987 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1988 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1989 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1990 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1991 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1992 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
02779c08 | 1993 | .set_clock_gating = NULL, |
2539eb02 | 1994 | .set_uvd_clocks = &si_set_uvd_clocks, |
b7af630c | 1995 | .set_vce_clocks = &si_set_vce_clocks, |
6bd1c385 | 1996 | .get_temperature = &si_get_temp, |
02779c08 | 1997 | }, |
a9e61410 AD |
1998 | .dpm = { |
1999 | .init = &si_dpm_init, | |
2000 | .setup_asic = &si_dpm_setup_asic, | |
2001 | .enable = &si_dpm_enable, | |
963c115d | 2002 | .late_enable = &si_dpm_late_enable, |
a9e61410 AD |
2003 | .disable = &si_dpm_disable, |
2004 | .pre_set_power_state = &si_dpm_pre_set_power_state, | |
2005 | .set_power_state = &si_dpm_set_power_state, | |
2006 | .post_set_power_state = &si_dpm_post_set_power_state, | |
2007 | .display_configuration_changed = &si_dpm_display_configuration_changed, | |
2008 | .fini = &si_dpm_fini, | |
2009 | .get_sclk = &ni_dpm_get_sclk, | |
2010 | .get_mclk = &ni_dpm_get_mclk, | |
2011 | .print_power_state = &ni_dpm_print_power_state, | |
7982128c | 2012 | .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, |
a160a6a3 | 2013 | .force_performance_level = &si_dpm_force_performance_level, |
f4dec318 | 2014 | .vblank_too_short = &ni_dpm_vblank_too_short, |
5e8150a6 AD |
2015 | .fan_ctrl_set_mode = &si_fan_ctrl_set_mode, |
2016 | .fan_ctrl_get_mode = &si_fan_ctrl_get_mode, | |
2017 | .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent, | |
2018 | .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent, | |
ca1110bc AD |
2019 | .get_current_sclk = &si_dpm_get_current_sclk, |
2020 | .get_current_mclk = &si_dpm_get_current_mclk, | |
a9e61410 | 2021 | }, |
02779c08 | 2022 | .pflip = { |
02779c08 | 2023 | .page_flip = &evergreen_page_flip, |
157fa14d | 2024 | .page_flip_pending = &evergreen_page_flip_pending, |
02779c08 AD |
2025 | }, |
2026 | }; | |
2027 | ||
d26678da | 2028 | static const struct radeon_asic_ring ci_gfx_ring = { |
76a0df85 CK |
2029 | .ib_execute = &cik_ring_ib_execute, |
2030 | .ib_parse = &cik_ib_parse, | |
2031 | .emit_fence = &cik_fence_gfx_ring_emit, | |
2032 | .emit_semaphore = &cik_semaphore_ring_emit, | |
2033 | .cs_parse = NULL, | |
2034 | .ring_test = &cik_ring_test, | |
2035 | .ib_test = &cik_ib_test, | |
2036 | .is_lockup = &cik_gfx_is_lockup, | |
2037 | .vm_flush = &cik_vm_flush, | |
ea31bf69 AD |
2038 | .get_rptr = &cik_gfx_get_rptr, |
2039 | .get_wptr = &cik_gfx_get_wptr, | |
2040 | .set_wptr = &cik_gfx_set_wptr, | |
76a0df85 CK |
2041 | }; |
2042 | ||
d26678da | 2043 | static const struct radeon_asic_ring ci_cp_ring = { |
76a0df85 CK |
2044 | .ib_execute = &cik_ring_ib_execute, |
2045 | .ib_parse = &cik_ib_parse, | |
2046 | .emit_fence = &cik_fence_compute_ring_emit, | |
2047 | .emit_semaphore = &cik_semaphore_ring_emit, | |
2048 | .cs_parse = NULL, | |
2049 | .ring_test = &cik_ring_test, | |
2050 | .ib_test = &cik_ib_test, | |
2051 | .is_lockup = &cik_gfx_is_lockup, | |
2052 | .vm_flush = &cik_vm_flush, | |
ea31bf69 AD |
2053 | .get_rptr = &cik_compute_get_rptr, |
2054 | .get_wptr = &cik_compute_get_wptr, | |
2055 | .set_wptr = &cik_compute_set_wptr, | |
76a0df85 CK |
2056 | }; |
2057 | ||
d26678da | 2058 | static const struct radeon_asic_ring ci_dma_ring = { |
76a0df85 CK |
2059 | .ib_execute = &cik_sdma_ring_ib_execute, |
2060 | .ib_parse = &cik_ib_parse, | |
2061 | .emit_fence = &cik_sdma_fence_ring_emit, | |
2062 | .emit_semaphore = &cik_sdma_semaphore_ring_emit, | |
2063 | .cs_parse = NULL, | |
2064 | .ring_test = &cik_sdma_ring_test, | |
2065 | .ib_test = &cik_sdma_ib_test, | |
2066 | .is_lockup = &cik_sdma_is_lockup, | |
2067 | .vm_flush = &cik_dma_vm_flush, | |
ea31bf69 AD |
2068 | .get_rptr = &cik_sdma_get_rptr, |
2069 | .get_wptr = &cik_sdma_get_wptr, | |
2070 | .set_wptr = &cik_sdma_set_wptr, | |
76a0df85 CK |
2071 | }; |
2072 | ||
d26678da | 2073 | static const struct radeon_asic_ring ci_vce_ring = { |
d93f7937 CK |
2074 | .ib_execute = &radeon_vce_ib_execute, |
2075 | .emit_fence = &radeon_vce_fence_emit, | |
2076 | .emit_semaphore = &radeon_vce_semaphore_emit, | |
2077 | .cs_parse = &radeon_vce_cs_parse, | |
2078 | .ring_test = &radeon_vce_ring_test, | |
2079 | .ib_test = &radeon_vce_ib_test, | |
2080 | .is_lockup = &radeon_ring_test_lockup, | |
2081 | .get_rptr = &vce_v1_0_get_rptr, | |
2082 | .get_wptr = &vce_v1_0_get_wptr, | |
2083 | .set_wptr = &vce_v1_0_set_wptr, | |
2084 | }; | |
2085 | ||
0672e27b AD |
2086 | static struct radeon_asic ci_asic = { |
2087 | .init = &cik_init, | |
2088 | .fini = &cik_fini, | |
2089 | .suspend = &cik_suspend, | |
2090 | .resume = &cik_resume, | |
2091 | .asic_reset = &cik_asic_reset, | |
2092 | .vga_set_state = &r600_vga_set_state, | |
72a9987e | 2093 | .mmio_hdp_flush = &r600_mmio_hdp_flush, |
0672e27b AD |
2094 | .gui_idle = &r600_gui_idle, |
2095 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
2096 | .get_xclk = &cik_get_xclk, | |
2097 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | |
353eec2a | 2098 | .get_allowed_info_register = cik_get_allowed_info_register, |
0672e27b AD |
2099 | .gart = { |
2100 | .tlb_flush = &cik_pcie_gart_tlb_flush, | |
cb658906 | 2101 | .get_page_entry = &rs600_gart_get_page_entry, |
0672e27b AD |
2102 | .set_page = &rs600_gart_set_page, |
2103 | }, | |
2104 | .vm = { | |
2105 | .init = &cik_vm_init, | |
2106 | .fini = &cik_vm_fini, | |
03f62abd CK |
2107 | .copy_pages = &cik_sdma_vm_copy_pages, |
2108 | .write_pages = &cik_sdma_vm_write_pages, | |
2109 | .set_pages = &cik_sdma_vm_set_pages, | |
2110 | .pad_ib = &cik_sdma_vm_pad_ib, | |
0672e27b AD |
2111 | }, |
2112 | .ring = { | |
76a0df85 CK |
2113 | [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, |
2114 | [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, | |
2115 | [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, | |
2116 | [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, | |
2117 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, | |
2118 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
d93f7937 CK |
2119 | [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, |
2120 | [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, | |
0672e27b AD |
2121 | }, |
2122 | .irq = { | |
2123 | .set = &cik_irq_set, | |
2124 | .process = &cik_irq_process, | |
2125 | }, | |
2126 | .display = { | |
2127 | .bandwidth_update = &dce8_bandwidth_update, | |
2128 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2129 | .wait_for_vblank = &dce4_wait_for_vblank, | |
7272c9d2 SL |
2130 | .set_backlight_level = &atombios_set_backlight_level, |
2131 | .get_backlight_level = &atombios_get_backlight_level, | |
0672e27b AD |
2132 | }, |
2133 | .copy = { | |
7819678f | 2134 | .blit = &cik_copy_cpdma, |
0672e27b AD |
2135 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
2136 | .dma = &cik_copy_dma, | |
2137 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
b5be1a83 CK |
2138 | .copy = &cik_copy_dma, |
2139 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
0672e27b AD |
2140 | }, |
2141 | .surface = { | |
2142 | .set_reg = r600_set_surface_reg, | |
2143 | .clear_reg = r600_clear_surface_reg, | |
2144 | }, | |
2145 | .hpd = { | |
2146 | .init = &evergreen_hpd_init, | |
2147 | .fini = &evergreen_hpd_fini, | |
2148 | .sense = &evergreen_hpd_sense, | |
2149 | .set_polarity = &evergreen_hpd_set_polarity, | |
2150 | }, | |
2151 | .pm = { | |
2152 | .misc = &evergreen_pm_misc, | |
2153 | .prepare = &evergreen_pm_prepare, | |
2154 | .finish = &evergreen_pm_finish, | |
2155 | .init_profile = &sumo_pm_init_profile, | |
2156 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2157 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2158 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2159 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
2160 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
2161 | .get_pcie_lanes = NULL, | |
2162 | .set_pcie_lanes = NULL, | |
2163 | .set_clock_gating = NULL, | |
2164 | .set_uvd_clocks = &cik_set_uvd_clocks, | |
5ad6bf91 | 2165 | .set_vce_clocks = &cik_set_vce_clocks, |
286d9cc6 | 2166 | .get_temperature = &ci_get_temp, |
0672e27b | 2167 | }, |
cc8dbbb4 AD |
2168 | .dpm = { |
2169 | .init = &ci_dpm_init, | |
2170 | .setup_asic = &ci_dpm_setup_asic, | |
2171 | .enable = &ci_dpm_enable, | |
90208427 | 2172 | .late_enable = &ci_dpm_late_enable, |
cc8dbbb4 AD |
2173 | .disable = &ci_dpm_disable, |
2174 | .pre_set_power_state = &ci_dpm_pre_set_power_state, | |
2175 | .set_power_state = &ci_dpm_set_power_state, | |
2176 | .post_set_power_state = &ci_dpm_post_set_power_state, | |
2177 | .display_configuration_changed = &ci_dpm_display_configuration_changed, | |
2178 | .fini = &ci_dpm_fini, | |
2179 | .get_sclk = &ci_dpm_get_sclk, | |
2180 | .get_mclk = &ci_dpm_get_mclk, | |
2181 | .print_power_state = &ci_dpm_print_power_state, | |
94b4adc5 | 2182 | .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, |
89536fd6 | 2183 | .force_performance_level = &ci_dpm_force_performance_level, |
5496131e | 2184 | .vblank_too_short = &ci_dpm_vblank_too_short, |
942bdf7f | 2185 | .powergate_uvd = &ci_dpm_powergate_uvd, |
36689e57 OC |
2186 | .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode, |
2187 | .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode, | |
2188 | .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent, | |
2189 | .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent, | |
dbbd3c81 AD |
2190 | .get_current_sclk = &ci_dpm_get_current_sclk, |
2191 | .get_current_mclk = &ci_dpm_get_current_mclk, | |
cc8dbbb4 | 2192 | }, |
0672e27b | 2193 | .pflip = { |
0672e27b | 2194 | .page_flip = &evergreen_page_flip, |
157fa14d | 2195 | .page_flip_pending = &evergreen_page_flip_pending, |
0672e27b AD |
2196 | }, |
2197 | }; | |
2198 | ||
2199 | static struct radeon_asic kv_asic = { | |
2200 | .init = &cik_init, | |
2201 | .fini = &cik_fini, | |
2202 | .suspend = &cik_suspend, | |
2203 | .resume = &cik_resume, | |
2204 | .asic_reset = &cik_asic_reset, | |
2205 | .vga_set_state = &r600_vga_set_state, | |
72a9987e | 2206 | .mmio_hdp_flush = &r600_mmio_hdp_flush, |
0672e27b AD |
2207 | .gui_idle = &r600_gui_idle, |
2208 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
2209 | .get_xclk = &cik_get_xclk, | |
2210 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | |
353eec2a | 2211 | .get_allowed_info_register = cik_get_allowed_info_register, |
0672e27b AD |
2212 | .gart = { |
2213 | .tlb_flush = &cik_pcie_gart_tlb_flush, | |
cb658906 | 2214 | .get_page_entry = &rs600_gart_get_page_entry, |
0672e27b AD |
2215 | .set_page = &rs600_gart_set_page, |
2216 | }, | |
2217 | .vm = { | |
2218 | .init = &cik_vm_init, | |
2219 | .fini = &cik_vm_fini, | |
03f62abd CK |
2220 | .copy_pages = &cik_sdma_vm_copy_pages, |
2221 | .write_pages = &cik_sdma_vm_write_pages, | |
2222 | .set_pages = &cik_sdma_vm_set_pages, | |
2223 | .pad_ib = &cik_sdma_vm_pad_ib, | |
0672e27b AD |
2224 | }, |
2225 | .ring = { | |
76a0df85 CK |
2226 | [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, |
2227 | [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, | |
2228 | [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, | |
2229 | [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, | |
2230 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, | |
2231 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
d93f7937 CK |
2232 | [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, |
2233 | [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, | |
0672e27b AD |
2234 | }, |
2235 | .irq = { | |
2236 | .set = &cik_irq_set, | |
2237 | .process = &cik_irq_process, | |
2238 | }, | |
2239 | .display = { | |
2240 | .bandwidth_update = &dce8_bandwidth_update, | |
2241 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2242 | .wait_for_vblank = &dce4_wait_for_vblank, | |
7272c9d2 SL |
2243 | .set_backlight_level = &atombios_set_backlight_level, |
2244 | .get_backlight_level = &atombios_get_backlight_level, | |
0672e27b AD |
2245 | }, |
2246 | .copy = { | |
7819678f | 2247 | .blit = &cik_copy_cpdma, |
0672e27b AD |
2248 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
2249 | .dma = &cik_copy_dma, | |
2250 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2251 | .copy = &cik_copy_dma, | |
2252 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2253 | }, | |
2254 | .surface = { | |
2255 | .set_reg = r600_set_surface_reg, | |
2256 | .clear_reg = r600_clear_surface_reg, | |
2257 | }, | |
2258 | .hpd = { | |
2259 | .init = &evergreen_hpd_init, | |
2260 | .fini = &evergreen_hpd_fini, | |
2261 | .sense = &evergreen_hpd_sense, | |
2262 | .set_polarity = &evergreen_hpd_set_polarity, | |
2263 | }, | |
2264 | .pm = { | |
2265 | .misc = &evergreen_pm_misc, | |
2266 | .prepare = &evergreen_pm_prepare, | |
2267 | .finish = &evergreen_pm_finish, | |
2268 | .init_profile = &sumo_pm_init_profile, | |
2269 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2270 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2271 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2272 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
2273 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
2274 | .get_pcie_lanes = NULL, | |
2275 | .set_pcie_lanes = NULL, | |
2276 | .set_clock_gating = NULL, | |
2277 | .set_uvd_clocks = &cik_set_uvd_clocks, | |
5ad6bf91 | 2278 | .set_vce_clocks = &cik_set_vce_clocks, |
286d9cc6 | 2279 | .get_temperature = &kv_get_temp, |
0672e27b | 2280 | }, |
41a524ab AD |
2281 | .dpm = { |
2282 | .init = &kv_dpm_init, | |
2283 | .setup_asic = &kv_dpm_setup_asic, | |
2284 | .enable = &kv_dpm_enable, | |
d8852c34 | 2285 | .late_enable = &kv_dpm_late_enable, |
41a524ab AD |
2286 | .disable = &kv_dpm_disable, |
2287 | .pre_set_power_state = &kv_dpm_pre_set_power_state, | |
2288 | .set_power_state = &kv_dpm_set_power_state, | |
2289 | .post_set_power_state = &kv_dpm_post_set_power_state, | |
2290 | .display_configuration_changed = &kv_dpm_display_configuration_changed, | |
2291 | .fini = &kv_dpm_fini, | |
2292 | .get_sclk = &kv_dpm_get_sclk, | |
2293 | .get_mclk = &kv_dpm_get_mclk, | |
2294 | .print_power_state = &kv_dpm_print_power_state, | |
ae3e40e8 | 2295 | .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, |
2b4c8022 | 2296 | .force_performance_level = &kv_dpm_force_performance_level, |
77df508a | 2297 | .powergate_uvd = &kv_dpm_powergate_uvd, |
b7a5ae97 | 2298 | .enable_bapm = &kv_dpm_enable_bapm, |
9b23bad0 AD |
2299 | .get_current_sclk = &kv_dpm_get_current_sclk, |
2300 | .get_current_mclk = &kv_dpm_get_current_mclk, | |
41a524ab | 2301 | }, |
0672e27b | 2302 | .pflip = { |
0672e27b | 2303 | .page_flip = &evergreen_page_flip, |
157fa14d | 2304 | .page_flip_pending = &evergreen_page_flip_pending, |
0672e27b AD |
2305 | }, |
2306 | }; | |
2307 | ||
abf1dc67 AD |
2308 | /** |
2309 | * radeon_asic_init - register asic specific callbacks | |
2310 | * | |
2311 | * @rdev: radeon device pointer | |
2312 | * | |
2313 | * Registers the appropriate asic specific callbacks for each | |
2314 | * chip family. Also sets other asics specific info like the number | |
2315 | * of crtcs and the register aperture accessors (all asics). | |
2316 | * Returns 0 for success. | |
2317 | */ | |
0a10c851 DV |
2318 | int radeon_asic_init(struct radeon_device *rdev) |
2319 | { | |
2320 | radeon_register_accessor_init(rdev); | |
ba7e05e9 AD |
2321 | |
2322 | /* set the number of crtcs */ | |
2323 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
2324 | rdev->num_crtc = 1; | |
2325 | else | |
2326 | rdev->num_crtc = 2; | |
2327 | ||
948bee3f | 2328 | rdev->has_uvd = false; |
e3ebfcfa | 2329 | rdev->has_vce = false; |
948bee3f | 2330 | |
0a10c851 DV |
2331 | switch (rdev->family) { |
2332 | case CHIP_R100: | |
2333 | case CHIP_RV100: | |
2334 | case CHIP_RS100: | |
2335 | case CHIP_RV200: | |
2336 | case CHIP_RS200: | |
2337 | rdev->asic = &r100_asic; | |
2338 | break; | |
2339 | case CHIP_R200: | |
2340 | case CHIP_RV250: | |
2341 | case CHIP_RS300: | |
2342 | case CHIP_RV280: | |
2343 | rdev->asic = &r200_asic; | |
2344 | break; | |
2345 | case CHIP_R300: | |
2346 | case CHIP_R350: | |
2347 | case CHIP_RV350: | |
2348 | case CHIP_RV380: | |
2349 | if (rdev->flags & RADEON_IS_PCIE) | |
2350 | rdev->asic = &r300_asic_pcie; | |
2351 | else | |
2352 | rdev->asic = &r300_asic; | |
2353 | break; | |
2354 | case CHIP_R420: | |
2355 | case CHIP_R423: | |
2356 | case CHIP_RV410: | |
2357 | rdev->asic = &r420_asic; | |
07bb084c AD |
2358 | /* handle macs */ |
2359 | if (rdev->bios == NULL) { | |
798bcf73 AD |
2360 | rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; |
2361 | rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; | |
2362 | rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; | |
2363 | rdev->asic->pm.set_memory_clock = NULL; | |
37e9b6a6 | 2364 | rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; |
07bb084c | 2365 | } |
0a10c851 DV |
2366 | break; |
2367 | case CHIP_RS400: | |
2368 | case CHIP_RS480: | |
2369 | rdev->asic = &rs400_asic; | |
2370 | break; | |
2371 | case CHIP_RS600: | |
2372 | rdev->asic = &rs600_asic; | |
2373 | break; | |
2374 | case CHIP_RS690: | |
2375 | case CHIP_RS740: | |
2376 | rdev->asic = &rs690_asic; | |
2377 | break; | |
2378 | case CHIP_RV515: | |
2379 | rdev->asic = &rv515_asic; | |
2380 | break; | |
2381 | case CHIP_R520: | |
2382 | case CHIP_RV530: | |
2383 | case CHIP_RV560: | |
2384 | case CHIP_RV570: | |
2385 | case CHIP_R580: | |
2386 | rdev->asic = &r520_asic; | |
2387 | break; | |
2388 | case CHIP_R600: | |
ca361b65 AD |
2389 | rdev->asic = &r600_asic; |
2390 | break; | |
0a10c851 DV |
2391 | case CHIP_RV610: |
2392 | case CHIP_RV630: | |
2393 | case CHIP_RV620: | |
2394 | case CHIP_RV635: | |
2395 | case CHIP_RV670: | |
ca361b65 AD |
2396 | rdev->asic = &rv6xx_asic; |
2397 | rdev->has_uvd = true; | |
f47299c5 | 2398 | break; |
0a10c851 DV |
2399 | case CHIP_RS780: |
2400 | case CHIP_RS880: | |
f47299c5 | 2401 | rdev->asic = &rs780_asic; |
bdc99722 | 2402 | /* 760G/780V/880V don't have UVD */ |
22dfe0ae GC |
2403 | if ((rdev->pdev->device == 0x9616) || |
2404 | (rdev->pdev->device == 0x9611) || | |
2405 | (rdev->pdev->device == 0x9613) || | |
2406 | (rdev->pdev->device == 0x9711) || | |
bdc99722 AD |
2407 | (rdev->pdev->device == 0x9713)) |
2408 | rdev->has_uvd = false; | |
2409 | else | |
2410 | rdev->has_uvd = true; | |
0a10c851 DV |
2411 | break; |
2412 | case CHIP_RV770: | |
2413 | case CHIP_RV730: | |
2414 | case CHIP_RV710: | |
2415 | case CHIP_RV740: | |
2416 | rdev->asic = &rv770_asic; | |
948bee3f | 2417 | rdev->has_uvd = true; |
0a10c851 DV |
2418 | break; |
2419 | case CHIP_CEDAR: | |
2420 | case CHIP_REDWOOD: | |
2421 | case CHIP_JUNIPER: | |
2422 | case CHIP_CYPRESS: | |
2423 | case CHIP_HEMLOCK: | |
ba7e05e9 AD |
2424 | /* set num crtcs */ |
2425 | if (rdev->family == CHIP_CEDAR) | |
2426 | rdev->num_crtc = 4; | |
2427 | else | |
2428 | rdev->num_crtc = 6; | |
0a10c851 | 2429 | rdev->asic = &evergreen_asic; |
948bee3f | 2430 | rdev->has_uvd = true; |
0a10c851 | 2431 | break; |
958261d1 | 2432 | case CHIP_PALM: |
89da5a37 AD |
2433 | case CHIP_SUMO: |
2434 | case CHIP_SUMO2: | |
958261d1 | 2435 | rdev->asic = &sumo_asic; |
948bee3f | 2436 | rdev->has_uvd = true; |
958261d1 | 2437 | break; |
a43b7665 AD |
2438 | case CHIP_BARTS: |
2439 | case CHIP_TURKS: | |
2440 | case CHIP_CAICOS: | |
ba7e05e9 AD |
2441 | /* set num crtcs */ |
2442 | if (rdev->family == CHIP_CAICOS) | |
2443 | rdev->num_crtc = 4; | |
2444 | else | |
2445 | rdev->num_crtc = 6; | |
a43b7665 | 2446 | rdev->asic = &btc_asic; |
948bee3f | 2447 | rdev->has_uvd = true; |
a43b7665 | 2448 | break; |
e3487629 AD |
2449 | case CHIP_CAYMAN: |
2450 | rdev->asic = &cayman_asic; | |
ba7e05e9 AD |
2451 | /* set num crtcs */ |
2452 | rdev->num_crtc = 6; | |
948bee3f | 2453 | rdev->has_uvd = true; |
e3487629 | 2454 | break; |
be63fe8c AD |
2455 | case CHIP_ARUBA: |
2456 | rdev->asic = &trinity_asic; | |
2457 | /* set num crtcs */ | |
2458 | rdev->num_crtc = 4; | |
948bee3f | 2459 | rdev->has_uvd = true; |
e3ebfcfa | 2460 | rdev->has_vce = true; |
d55a43a3 AD |
2461 | rdev->cg_flags = |
2462 | RADEON_CG_SUPPORT_VCE_MGCG; | |
be63fe8c | 2463 | break; |
02779c08 AD |
2464 | case CHIP_TAHITI: |
2465 | case CHIP_PITCAIRN: | |
2466 | case CHIP_VERDE: | |
e737a14c | 2467 | case CHIP_OLAND: |
86a45cac | 2468 | case CHIP_HAINAN: |
02779c08 AD |
2469 | rdev->asic = &si_asic; |
2470 | /* set num crtcs */ | |
86a45cac AD |
2471 | if (rdev->family == CHIP_HAINAN) |
2472 | rdev->num_crtc = 0; | |
2473 | else if (rdev->family == CHIP_OLAND) | |
e737a14c AD |
2474 | rdev->num_crtc = 2; |
2475 | else | |
2476 | rdev->num_crtc = 6; | |
e3ebfcfa | 2477 | if (rdev->family == CHIP_HAINAN) { |
948bee3f | 2478 | rdev->has_uvd = false; |
e3ebfcfa | 2479 | rdev->has_vce = false; |
7e6435c1 AD |
2480 | } else if (rdev->family == CHIP_OLAND) { |
2481 | rdev->has_uvd = true; | |
2482 | rdev->has_vce = false; | |
e3ebfcfa | 2483 | } else { |
948bee3f | 2484 | rdev->has_uvd = true; |
e3ebfcfa JG |
2485 | rdev->has_vce = true; |
2486 | } | |
0116e1ef AD |
2487 | switch (rdev->family) { |
2488 | case CHIP_TAHITI: | |
2489 | rdev->cg_flags = | |
090f4b6a | 2490 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2491 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2492 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2493 | RADEON_CG_SUPPORT_GFX_CGLS | |
2494 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2495 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2496 | RADEON_CG_SUPPORT_MC_MGCG | | |
2497 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2498 | RADEON_CG_SUPPORT_BIF_LS | | |
2499 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2500 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2501 | RADEON_CG_SUPPORT_HDP_LS | | |
2502 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2503 | rdev->pg_flags = 0; | |
2504 | break; | |
2505 | case CHIP_PITCAIRN: | |
2506 | rdev->cg_flags = | |
090f4b6a | 2507 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2508 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2509 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2510 | RADEON_CG_SUPPORT_GFX_CGLS | |
2511 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2512 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2513 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2514 | RADEON_CG_SUPPORT_MC_LS | | |
2515 | RADEON_CG_SUPPORT_MC_MGCG | | |
2516 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2517 | RADEON_CG_SUPPORT_BIF_LS | | |
2518 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2519 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2520 | RADEON_CG_SUPPORT_HDP_LS | | |
2521 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2522 | rdev->pg_flags = 0; | |
2523 | break; | |
2524 | case CHIP_VERDE: | |
2525 | rdev->cg_flags = | |
090f4b6a | 2526 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2527 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2528 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2529 | RADEON_CG_SUPPORT_GFX_CGLS | |
2530 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2531 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2532 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2533 | RADEON_CG_SUPPORT_MC_LS | | |
2534 | RADEON_CG_SUPPORT_MC_MGCG | | |
2535 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2536 | RADEON_CG_SUPPORT_BIF_LS | | |
2537 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2538 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2539 | RADEON_CG_SUPPORT_HDP_LS | | |
2540 | RADEON_CG_SUPPORT_HDP_MGCG; | |
ca6ebb39 | 2541 | rdev->pg_flags = 0 | |
2b19d17f | 2542 | /*RADEON_PG_SUPPORT_GFX_PG | */ |
ca6ebb39 | 2543 | RADEON_PG_SUPPORT_SDMA; |
0116e1ef AD |
2544 | break; |
2545 | case CHIP_OLAND: | |
2546 | rdev->cg_flags = | |
090f4b6a | 2547 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2548 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2549 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2550 | RADEON_CG_SUPPORT_GFX_CGLS | |
2551 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2552 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2553 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2554 | RADEON_CG_SUPPORT_MC_LS | | |
2555 | RADEON_CG_SUPPORT_MC_MGCG | | |
2556 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2557 | RADEON_CG_SUPPORT_BIF_LS | | |
2558 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2559 | RADEON_CG_SUPPORT_HDP_LS | | |
2560 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2561 | rdev->pg_flags = 0; | |
2562 | break; | |
2563 | case CHIP_HAINAN: | |
2564 | rdev->cg_flags = | |
090f4b6a | 2565 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2566 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2567 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2568 | RADEON_CG_SUPPORT_GFX_CGLS | |
2569 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2570 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2571 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2572 | RADEON_CG_SUPPORT_MC_LS | | |
2573 | RADEON_CG_SUPPORT_MC_MGCG | | |
2574 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2575 | RADEON_CG_SUPPORT_BIF_LS | | |
2576 | RADEON_CG_SUPPORT_HDP_LS | | |
2577 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2578 | rdev->pg_flags = 0; | |
2579 | break; | |
2580 | default: | |
2581 | rdev->cg_flags = 0; | |
2582 | rdev->pg_flags = 0; | |
2583 | break; | |
2584 | } | |
02779c08 | 2585 | break; |
0672e27b | 2586 | case CHIP_BONAIRE: |
41971b37 | 2587 | case CHIP_HAWAII: |
0672e27b AD |
2588 | rdev->asic = &ci_asic; |
2589 | rdev->num_crtc = 6; | |
22c775ce | 2590 | rdev->has_uvd = true; |
e3ebfcfa | 2591 | rdev->has_vce = true; |
41971b37 AD |
2592 | if (rdev->family == CHIP_BONAIRE) { |
2593 | rdev->cg_flags = | |
2594 | RADEON_CG_SUPPORT_GFX_MGCG | | |
2595 | RADEON_CG_SUPPORT_GFX_MGLS | | |
6960948d | 2596 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
41971b37 AD |
2597 | RADEON_CG_SUPPORT_GFX_CGLS | |
2598 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2599 | RADEON_CG_SUPPORT_GFX_CGTS_LS | | |
2600 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2601 | RADEON_CG_SUPPORT_MC_LS | | |
2602 | RADEON_CG_SUPPORT_MC_MGCG | | |
2603 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2604 | RADEON_CG_SUPPORT_SDMA_LS | | |
2605 | RADEON_CG_SUPPORT_BIF_LS | | |
2606 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2607 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2608 | RADEON_CG_SUPPORT_HDP_LS | | |
2609 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2610 | rdev->pg_flags = 0; | |
2611 | } else { | |
2612 | rdev->cg_flags = | |
2613 | RADEON_CG_SUPPORT_GFX_MGCG | | |
2614 | RADEON_CG_SUPPORT_GFX_MGLS | | |
6960948d | 2615 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
41971b37 AD |
2616 | RADEON_CG_SUPPORT_GFX_CGLS | |
2617 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2618 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2619 | RADEON_CG_SUPPORT_MC_LS | | |
2620 | RADEON_CG_SUPPORT_MC_MGCG | | |
2621 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2622 | RADEON_CG_SUPPORT_SDMA_LS | | |
2623 | RADEON_CG_SUPPORT_BIF_LS | | |
2624 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2625 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2626 | RADEON_CG_SUPPORT_HDP_LS | | |
2627 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2628 | rdev->pg_flags = 0; | |
2629 | } | |
0672e27b AD |
2630 | break; |
2631 | case CHIP_KAVERI: | |
2632 | case CHIP_KABINI: | |
b0a9f22a | 2633 | case CHIP_MULLINS: |
0672e27b AD |
2634 | rdev->asic = &kv_asic; |
2635 | /* set num crtcs */ | |
473359bc | 2636 | if (rdev->family == CHIP_KAVERI) { |
0672e27b | 2637 | rdev->num_crtc = 4; |
473359bc | 2638 | rdev->cg_flags = |
773dc10a | 2639 | RADEON_CG_SUPPORT_GFX_MGCG | |
473359bc | 2640 | RADEON_CG_SUPPORT_GFX_MGLS | |
6960948d | 2641 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
473359bc AD |
2642 | RADEON_CG_SUPPORT_GFX_CGLS | |
2643 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2644 | RADEON_CG_SUPPORT_GFX_CGTS_LS | | |
2645 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2646 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2647 | RADEON_CG_SUPPORT_SDMA_LS | | |
2648 | RADEON_CG_SUPPORT_BIF_LS | | |
2649 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2650 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2651 | RADEON_CG_SUPPORT_HDP_LS | | |
2652 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2653 | rdev->pg_flags = 0; | |
2b19d17f | 2654 | /*RADEON_PG_SUPPORT_GFX_PG | |
473359bc AD |
2655 | RADEON_PG_SUPPORT_GFX_SMG | |
2656 | RADEON_PG_SUPPORT_GFX_DMG | | |
2657 | RADEON_PG_SUPPORT_UVD | | |
2658 | RADEON_PG_SUPPORT_VCE | | |
2659 | RADEON_PG_SUPPORT_CP | | |
2660 | RADEON_PG_SUPPORT_GDS | | |
2661 | RADEON_PG_SUPPORT_RLC_SMU_HS | | |
2662 | RADEON_PG_SUPPORT_ACP | | |
2663 | RADEON_PG_SUPPORT_SAMU;*/ | |
2664 | } else { | |
0672e27b | 2665 | rdev->num_crtc = 2; |
473359bc | 2666 | rdev->cg_flags = |
773dc10a | 2667 | RADEON_CG_SUPPORT_GFX_MGCG | |
473359bc | 2668 | RADEON_CG_SUPPORT_GFX_MGLS | |
6960948d | 2669 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
473359bc AD |
2670 | RADEON_CG_SUPPORT_GFX_CGLS | |
2671 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2672 | RADEON_CG_SUPPORT_GFX_CGTS_LS | | |
2673 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2674 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2675 | RADEON_CG_SUPPORT_SDMA_LS | | |
2676 | RADEON_CG_SUPPORT_BIF_LS | | |
2677 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2678 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2679 | RADEON_CG_SUPPORT_HDP_LS | | |
2680 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2681 | rdev->pg_flags = 0; | |
2b19d17f | 2682 | /*RADEON_PG_SUPPORT_GFX_PG | |
473359bc AD |
2683 | RADEON_PG_SUPPORT_GFX_SMG | |
2684 | RADEON_PG_SUPPORT_UVD | | |
2685 | RADEON_PG_SUPPORT_VCE | | |
2686 | RADEON_PG_SUPPORT_CP | | |
2687 | RADEON_PG_SUPPORT_GDS | | |
2688 | RADEON_PG_SUPPORT_RLC_SMU_HS | | |
2689 | RADEON_PG_SUPPORT_SAMU;*/ | |
2690 | } | |
22c775ce | 2691 | rdev->has_uvd = true; |
e3ebfcfa | 2692 | rdev->has_vce = true; |
0672e27b | 2693 | break; |
0a10c851 DV |
2694 | default: |
2695 | /* FIXME: not supported yet */ | |
2696 | return -EINVAL; | |
2697 | } | |
2698 | ||
2699 | if (rdev->flags & RADEON_IS_IGP) { | |
798bcf73 AD |
2700 | rdev->asic->pm.get_memory_clock = NULL; |
2701 | rdev->asic->pm.set_memory_clock = NULL; | |
0a10c851 DV |
2702 | } |
2703 | ||
f1a0a67a JG |
2704 | if (!radeon_uvd) |
2705 | rdev->has_uvd = false; | |
fabb5935 JG |
2706 | if (!radeon_vce) |
2707 | rdev->has_vce = false; | |
f1a0a67a | 2708 | |
0a10c851 DV |
2709 | return 0; |
2710 | } | |
2711 |