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drm/radeon: separate ring and IB handling
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
abf1dc67
AD		 43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
0a10c851
DV		 53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
abf1dc67
AD		 60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
0a10c851
DV		 70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
abf1dc67
AD		 77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
0a10c851
DV		 85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
65337e60
SL		 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
6e2c3c0a
AD		 129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
0a10c851
DV		 134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
139
140/* helper to disable agp */
abf1dc67
AD		 141/**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
0a10c851
DV		 149void radeon_agp_disable(struct radeon_device *rdev)
150{
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
c5b3b850
AD		 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0a10c851
DV		 163 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
c5b3b850
AD		 166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0a10c851
DV		 168 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170}
171
172/*
173 * ASIC
174 */
76a0df85
CK		 175
176static struct radeon_asic_ring r100_gfx_ring = {
177 .ib_execute = &r100_ring_ib_execute,
178 .emit_fence = &r100_fence_ring_emit,
179 .emit_semaphore = &r100_semaphore_ring_emit,
180 .cs_parse = &r100_cs_parse,
181 .ring_start = &r100_ring_start,
182 .ring_test = &r100_ring_test,
183 .ib_test = &r100_ib_test,
184 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 185 .get_rptr = &r100_gfx_get_rptr,
186 .get_wptr = &r100_gfx_get_wptr,
187 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 188};
189
48e7a5f1
DV		 190static struct radeon_asic r100_asic = {
191 .init = &r100_init,
192 .fini = &r100_fini,
193 .suspend = &r100_suspend,
194 .resume = &r100_resume,
195 .vga_set_state = &r100_vga_set_state,
a2d07b74 196 .asic_reset = &r100_asic_reset,
54e88e06
AD		 197 .ioctl_wait_idle = NULL,
198 .gui_idle = &r100_gui_idle,
199 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 200 .gart = {
201 .tlb_flush = &r100_pci_gart_tlb_flush,
202 .set_page = &r100_pci_gart_set_page,
203 },
4c87bc26 204 .ring = {
76a0df85 205 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 206 },
b35ea4ab
AD		 207 .irq = {
208 .set = &r100_irq_set,
209 .process = &r100_irq_process,
210 },
c79a49ca
AD		 211 .display = {
212 .bandwidth_update = &r100_bandwidth_update,
213 .get_vblank_counter = &r100_get_vblank_counter,
214 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 215 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 216 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 217 },
27cd7769
AD		 218 .copy = {
219 .blit = &r100_copy_blit,
220 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
221 .dma = NULL,
222 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
223 .copy = &r100_copy_blit,
224 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
225 },
9e6f3d02
AD		 226 .surface = {
227 .set_reg = r100_set_surface_reg,
228 .clear_reg = r100_clear_surface_reg,
229 },
901ea57d
AD		 230 .hpd = {
231 .init = &r100_hpd_init,
232 .fini = &r100_hpd_fini,
233 .sense = &r100_hpd_sense,
234 .set_polarity = &r100_hpd_set_polarity,
235 },
a02fa397
AD		 236 .pm = {
237 .misc = &r100_pm_misc,
238 .prepare = &r100_pm_prepare,
239 .finish = &r100_pm_finish,
240 .init_profile = &r100_pm_init_profile,
241 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 242 .get_engine_clock = &radeon_legacy_get_engine_clock,
243 .set_engine_clock = &radeon_legacy_set_engine_clock,
244 .get_memory_clock = &radeon_legacy_get_memory_clock,
245 .set_memory_clock = NULL,
246 .get_pcie_lanes = NULL,
247 .set_pcie_lanes = NULL,
248 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 249 },
0f9e006c 250 .pflip = {
0f9e006c 251 .page_flip = &r100_page_flip,
157fa14d 252 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 253 },
48e7a5f1
DV		 254};
255
256static struct radeon_asic r200_asic = {
257 .init = &r100_init,
258 .fini = &r100_fini,
259 .suspend = &r100_suspend,
260 .resume = &r100_resume,
261 .vga_set_state = &r100_vga_set_state,
a2d07b74 262 .asic_reset = &r100_asic_reset,
54e88e06
AD		 263 .ioctl_wait_idle = NULL,
264 .gui_idle = &r100_gui_idle,
265 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 266 .gart = {
267 .tlb_flush = &r100_pci_gart_tlb_flush,
268 .set_page = &r100_pci_gart_set_page,
269 },
4c87bc26 270 .ring = {
76a0df85 271 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 272 },
b35ea4ab
AD		 273 .irq = {
274 .set = &r100_irq_set,
275 .process = &r100_irq_process,
276 },
c79a49ca
AD		 277 .display = {
278 .bandwidth_update = &r100_bandwidth_update,
279 .get_vblank_counter = &r100_get_vblank_counter,
280 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 281 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 282 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 283 },
27cd7769
AD		 284 .copy = {
285 .blit = &r100_copy_blit,
286 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
287 .dma = &r200_copy_dma,
288 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
289 .copy = &r100_copy_blit,
290 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
291 },
9e6f3d02
AD		 292 .surface = {
293 .set_reg = r100_set_surface_reg,
294 .clear_reg = r100_clear_surface_reg,
295 },
901ea57d
AD		 296 .hpd = {
297 .init = &r100_hpd_init,
298 .fini = &r100_hpd_fini,
299 .sense = &r100_hpd_sense,
300 .set_polarity = &r100_hpd_set_polarity,
301 },
a02fa397
AD		 302 .pm = {
303 .misc = &r100_pm_misc,
304 .prepare = &r100_pm_prepare,
305 .finish = &r100_pm_finish,
306 .init_profile = &r100_pm_init_profile,
307 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 308 .get_engine_clock = &radeon_legacy_get_engine_clock,
309 .set_engine_clock = &radeon_legacy_set_engine_clock,
310 .get_memory_clock = &radeon_legacy_get_memory_clock,
311 .set_memory_clock = NULL,
312 .get_pcie_lanes = NULL,
313 .set_pcie_lanes = NULL,
314 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 315 },
0f9e006c 316 .pflip = {
0f9e006c 317 .page_flip = &r100_page_flip,
157fa14d 318 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 319 },
48e7a5f1
DV		 320};
321
76a0df85
CK		 322static struct radeon_asic_ring r300_gfx_ring = {
323 .ib_execute = &r100_ring_ib_execute,
324 .emit_fence = &r300_fence_ring_emit,
325 .emit_semaphore = &r100_semaphore_ring_emit,
326 .cs_parse = &r300_cs_parse,
327 .ring_start = &r300_ring_start,
328 .ring_test = &r100_ring_test,
329 .ib_test = &r100_ib_test,
330 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 331 .get_rptr = &r100_gfx_get_rptr,
332 .get_wptr = &r100_gfx_get_wptr,
333 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 334};
335
48e7a5f1
DV		 336static struct radeon_asic r300_asic = {
337 .init = &r300_init,
338 .fini = &r300_fini,
339 .suspend = &r300_suspend,
340 .resume = &r300_resume,
341 .vga_set_state = &r100_vga_set_state,
a2d07b74 342 .asic_reset = &r300_asic_reset,
54e88e06
AD		 343 .ioctl_wait_idle = NULL,
344 .gui_idle = &r100_gui_idle,
345 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 346 .gart = {
347 .tlb_flush = &r100_pci_gart_tlb_flush,
348 .set_page = &r100_pci_gart_set_page,
349 },
4c87bc26 350 .ring = {
76a0df85 351 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 352 },
b35ea4ab
AD		 353 .irq = {
354 .set = &r100_irq_set,
355 .process = &r100_irq_process,
356 },
c79a49ca
AD		 357 .display = {
358 .bandwidth_update = &r100_bandwidth_update,
359 .get_vblank_counter = &r100_get_vblank_counter,
360 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 361 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 362 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 363 },
27cd7769
AD		 364 .copy = {
365 .blit = &r100_copy_blit,
366 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
367 .dma = &r200_copy_dma,
368 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
369 .copy = &r100_copy_blit,
370 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
371 },
9e6f3d02
AD		 372 .surface = {
373 .set_reg = r100_set_surface_reg,
374 .clear_reg = r100_clear_surface_reg,
375 },
901ea57d
AD		 376 .hpd = {
377 .init = &r100_hpd_init,
378 .fini = &r100_hpd_fini,
379 .sense = &r100_hpd_sense,
380 .set_polarity = &r100_hpd_set_polarity,
381 },
a02fa397
AD		 382 .pm = {
383 .misc = &r100_pm_misc,
384 .prepare = &r100_pm_prepare,
385 .finish = &r100_pm_finish,
386 .init_profile = &r100_pm_init_profile,
387 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 388 .get_engine_clock = &radeon_legacy_get_engine_clock,
389 .set_engine_clock = &radeon_legacy_set_engine_clock,
390 .get_memory_clock = &radeon_legacy_get_memory_clock,
391 .set_memory_clock = NULL,
392 .get_pcie_lanes = &rv370_get_pcie_lanes,
393 .set_pcie_lanes = &rv370_set_pcie_lanes,
394 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 395 },
0f9e006c 396 .pflip = {
0f9e006c 397 .page_flip = &r100_page_flip,
157fa14d 398 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 399 },
48e7a5f1
DV		 400};
401
402static struct radeon_asic r300_asic_pcie = {
403 .init = &r300_init,
404 .fini = &r300_fini,
405 .suspend = &r300_suspend,
406 .resume = &r300_resume,
407 .vga_set_state = &r100_vga_set_state,
a2d07b74 408 .asic_reset = &r300_asic_reset,
54e88e06
AD		 409 .ioctl_wait_idle = NULL,
410 .gui_idle = &r100_gui_idle,
411 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 412 .gart = {
413 .tlb_flush = &rv370_pcie_gart_tlb_flush,
414 .set_page = &rv370_pcie_gart_set_page,
415 },
4c87bc26 416 .ring = {
76a0df85 417 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 418 },
b35ea4ab
AD		 419 .irq = {
420 .set = &r100_irq_set,
421 .process = &r100_irq_process,
422 },
c79a49ca
AD		 423 .display = {
424 .bandwidth_update = &r100_bandwidth_update,
425 .get_vblank_counter = &r100_get_vblank_counter,
426 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 427 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 428 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 429 },
27cd7769
AD		 430 .copy = {
431 .blit = &r100_copy_blit,
432 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
433 .dma = &r200_copy_dma,
434 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
435 .copy = &r100_copy_blit,
436 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
437 },
9e6f3d02
AD		 438 .surface = {
439 .set_reg = r100_set_surface_reg,
440 .clear_reg = r100_clear_surface_reg,
441 },
901ea57d
AD		 442 .hpd = {
443 .init = &r100_hpd_init,
444 .fini = &r100_hpd_fini,
445 .sense = &r100_hpd_sense,
446 .set_polarity = &r100_hpd_set_polarity,
447 },
a02fa397
AD		 448 .pm = {
449 .misc = &r100_pm_misc,
450 .prepare = &r100_pm_prepare,
451 .finish = &r100_pm_finish,
452 .init_profile = &r100_pm_init_profile,
453 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 454 .get_engine_clock = &radeon_legacy_get_engine_clock,
455 .set_engine_clock = &radeon_legacy_set_engine_clock,
456 .get_memory_clock = &radeon_legacy_get_memory_clock,
457 .set_memory_clock = NULL,
458 .get_pcie_lanes = &rv370_get_pcie_lanes,
459 .set_pcie_lanes = &rv370_set_pcie_lanes,
460 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 461 },
0f9e006c 462 .pflip = {
0f9e006c 463 .page_flip = &r100_page_flip,
157fa14d 464 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 465 },
48e7a5f1
DV		 466};
467
468static struct radeon_asic r420_asic = {
469 .init = &r420_init,
470 .fini = &r420_fini,
471 .suspend = &r420_suspend,
472 .resume = &r420_resume,
473 .vga_set_state = &r100_vga_set_state,
a2d07b74 474 .asic_reset = &r300_asic_reset,
54e88e06
AD		 475 .ioctl_wait_idle = NULL,
476 .gui_idle = &r100_gui_idle,
477 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 478 .gart = {
479 .tlb_flush = &rv370_pcie_gart_tlb_flush,
480 .set_page = &rv370_pcie_gart_set_page,
481 },
4c87bc26 482 .ring = {
76a0df85 483 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 484 },
b35ea4ab
AD		 485 .irq = {
486 .set = &r100_irq_set,
487 .process = &r100_irq_process,
488 },
c79a49ca
AD		 489 .display = {
490 .bandwidth_update = &r100_bandwidth_update,
491 .get_vblank_counter = &r100_get_vblank_counter,
492 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 493 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 494 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 495 },
27cd7769
AD		 496 .copy = {
497 .blit = &r100_copy_blit,
498 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
499 .dma = &r200_copy_dma,
500 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
501 .copy = &r100_copy_blit,
502 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
503 },
9e6f3d02
AD		 504 .surface = {
505 .set_reg = r100_set_surface_reg,
506 .clear_reg = r100_clear_surface_reg,
507 },
901ea57d
AD		 508 .hpd = {
509 .init = &r100_hpd_init,
510 .fini = &r100_hpd_fini,
511 .sense = &r100_hpd_sense,
512 .set_polarity = &r100_hpd_set_polarity,
513 },
a02fa397
AD		 514 .pm = {
515 .misc = &r100_pm_misc,
516 .prepare = &r100_pm_prepare,
517 .finish = &r100_pm_finish,
518 .init_profile = &r420_pm_init_profile,
519 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 520 .get_engine_clock = &radeon_atom_get_engine_clock,
521 .set_engine_clock = &radeon_atom_set_engine_clock,
522 .get_memory_clock = &radeon_atom_get_memory_clock,
523 .set_memory_clock = &radeon_atom_set_memory_clock,
524 .get_pcie_lanes = &rv370_get_pcie_lanes,
525 .set_pcie_lanes = &rv370_set_pcie_lanes,
526 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 527 },
0f9e006c 528 .pflip = {
0f9e006c 529 .page_flip = &r100_page_flip,
157fa14d 530 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 531 },
48e7a5f1
DV		 532};
533
534static struct radeon_asic rs400_asic = {
535 .init = &rs400_init,
536 .fini = &rs400_fini,
537 .suspend = &rs400_suspend,
538 .resume = &rs400_resume,
539 .vga_set_state = &r100_vga_set_state,
a2d07b74 540 .asic_reset = &r300_asic_reset,
54e88e06
AD		 541 .ioctl_wait_idle = NULL,
542 .gui_idle = &r100_gui_idle,
543 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
c5b3b850
AD		 544 .gart = {
545 .tlb_flush = &rs400_gart_tlb_flush,
546 .set_page = &rs400_gart_set_page,
547 },
4c87bc26 548 .ring = {
76a0df85 549 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 550 },
b35ea4ab
AD		 551 .irq = {
552 .set = &r100_irq_set,
553 .process = &r100_irq_process,
554 },
c79a49ca
AD		 555 .display = {
556 .bandwidth_update = &r100_bandwidth_update,
557 .get_vblank_counter = &r100_get_vblank_counter,
558 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 559 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 560 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 561 },
27cd7769
AD		 562 .copy = {
563 .blit = &r100_copy_blit,
564 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
565 .dma = &r200_copy_dma,
566 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
567 .copy = &r100_copy_blit,
568 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
569 },
9e6f3d02
AD		 570 .surface = {
571 .set_reg = r100_set_surface_reg,
572 .clear_reg = r100_clear_surface_reg,
573 },
901ea57d
AD		 574 .hpd = {
575 .init = &r100_hpd_init,
576 .fini = &r100_hpd_fini,
577 .sense = &r100_hpd_sense,
578 .set_polarity = &r100_hpd_set_polarity,
579 },
a02fa397
AD		 580 .pm = {
581 .misc = &r100_pm_misc,
582 .prepare = &r100_pm_prepare,
583 .finish = &r100_pm_finish,
584 .init_profile = &r100_pm_init_profile,
585 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 586 .get_engine_clock = &radeon_legacy_get_engine_clock,
587 .set_engine_clock = &radeon_legacy_set_engine_clock,
588 .get_memory_clock = &radeon_legacy_get_memory_clock,
589 .set_memory_clock = NULL,
590 .get_pcie_lanes = NULL,
591 .set_pcie_lanes = NULL,
592 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 593 },
0f9e006c 594 .pflip = {
0f9e006c 595 .page_flip = &r100_page_flip,
157fa14d 596 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 597 },
48e7a5f1
DV		 598};
599
600static struct radeon_asic rs600_asic = {
601 .init = &rs600_init,
602 .fini = &rs600_fini,
603 .suspend = &rs600_suspend,
604 .resume = &rs600_resume,
605 .vga_set_state = &r100_vga_set_state,
90aca4d2 606 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 607 .ioctl_wait_idle = NULL,
608 .gui_idle = &r100_gui_idle,
609 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
c5b3b850
AD		 610 .gart = {
611 .tlb_flush = &rs600_gart_tlb_flush,
612 .set_page = &rs600_gart_set_page,
613 },
4c87bc26 614 .ring = {
76a0df85 615 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 616 },
b35ea4ab
AD		 617 .irq = {
618 .set = &rs600_irq_set,
619 .process = &rs600_irq_process,
620 },
c79a49ca
AD		 621 .display = {
622 .bandwidth_update = &rs600_bandwidth_update,
623 .get_vblank_counter = &rs600_get_vblank_counter,
624 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 625 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 626 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 627 .hdmi_enable = &r600_hdmi_enable,
628 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 629 },
27cd7769
AD		 630 .copy = {
631 .blit = &r100_copy_blit,
632 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
633 .dma = &r200_copy_dma,
634 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
635 .copy = &r100_copy_blit,
636 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
637 },
9e6f3d02
AD		 638 .surface = {
639 .set_reg = r100_set_surface_reg,
640 .clear_reg = r100_clear_surface_reg,
641 },
901ea57d
AD		 642 .hpd = {
643 .init = &rs600_hpd_init,
644 .fini = &rs600_hpd_fini,
645 .sense = &rs600_hpd_sense,
646 .set_polarity = &rs600_hpd_set_polarity,
647 },
a02fa397
AD		 648 .pm = {
649 .misc = &rs600_pm_misc,
650 .prepare = &rs600_pm_prepare,
651 .finish = &rs600_pm_finish,
652 .init_profile = &r420_pm_init_profile,
653 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 654 .get_engine_clock = &radeon_atom_get_engine_clock,
655 .set_engine_clock = &radeon_atom_set_engine_clock,
656 .get_memory_clock = &radeon_atom_get_memory_clock,
657 .set_memory_clock = &radeon_atom_set_memory_clock,
658 .get_pcie_lanes = NULL,
659 .set_pcie_lanes = NULL,
660 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 661 },
0f9e006c 662 .pflip = {
0f9e006c 663 .page_flip = &rs600_page_flip,
157fa14d 664 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 665 },
48e7a5f1
DV		 666};
667
668static struct radeon_asic rs690_asic = {
669 .init = &rs690_init,
670 .fini = &rs690_fini,
671 .suspend = &rs690_suspend,
672 .resume = &rs690_resume,
673 .vga_set_state = &r100_vga_set_state,
90aca4d2 674 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 675 .ioctl_wait_idle = NULL,
676 .gui_idle = &r100_gui_idle,
677 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
c5b3b850
AD		 678 .gart = {
679 .tlb_flush = &rs400_gart_tlb_flush,
680 .set_page = &rs400_gart_set_page,
681 },
4c87bc26 682 .ring = {
76a0df85 683 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 684 },
b35ea4ab
AD		 685 .irq = {
686 .set = &rs600_irq_set,
687 .process = &rs600_irq_process,
688 },
c79a49ca
AD		 689 .display = {
690 .get_vblank_counter = &rs600_get_vblank_counter,
691 .bandwidth_update = &rs690_bandwidth_update,
692 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 693 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 694 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 695 .hdmi_enable = &r600_hdmi_enable,
696 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 697 },
27cd7769
AD		 698 .copy = {
699 .blit = &r100_copy_blit,
700 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
701 .dma = &r200_copy_dma,
702 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
703 .copy = &r200_copy_dma,
704 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
705 },
9e6f3d02
AD		 706 .surface = {
707 .set_reg = r100_set_surface_reg,
708 .clear_reg = r100_clear_surface_reg,
709 },
901ea57d
AD		 710 .hpd = {
711 .init = &rs600_hpd_init,
712 .fini = &rs600_hpd_fini,
713 .sense = &rs600_hpd_sense,
714 .set_polarity = &rs600_hpd_set_polarity,
715 },
a02fa397
AD		 716 .pm = {
717 .misc = &rs600_pm_misc,
718 .prepare = &rs600_pm_prepare,
719 .finish = &rs600_pm_finish,
720 .init_profile = &r420_pm_init_profile,
721 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 722 .get_engine_clock = &radeon_atom_get_engine_clock,
723 .set_engine_clock = &radeon_atom_set_engine_clock,
724 .get_memory_clock = &radeon_atom_get_memory_clock,
725 .set_memory_clock = &radeon_atom_set_memory_clock,
726 .get_pcie_lanes = NULL,
727 .set_pcie_lanes = NULL,
728 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 729 },
0f9e006c 730 .pflip = {
0f9e006c 731 .page_flip = &rs600_page_flip,
157fa14d 732 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 733 },
48e7a5f1
DV		 734};
735
736static struct radeon_asic rv515_asic = {
737 .init = &rv515_init,
738 .fini = &rv515_fini,
739 .suspend = &rv515_suspend,
740 .resume = &rv515_resume,
741 .vga_set_state = &r100_vga_set_state,
90aca4d2 742 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 743 .ioctl_wait_idle = NULL,
744 .gui_idle = &r100_gui_idle,
745 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
c5b3b850
AD		 746 .gart = {
747 .tlb_flush = &rv370_pcie_gart_tlb_flush,
748 .set_page = &rv370_pcie_gart_set_page,
749 },
4c87bc26 750 .ring = {
76a0df85 751 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 752 },
b35ea4ab
AD		 753 .irq = {
754 .set = &rs600_irq_set,
755 .process = &rs600_irq_process,
756 },
c79a49ca
AD		 757 .display = {
758 .get_vblank_counter = &rs600_get_vblank_counter,
759 .bandwidth_update = &rv515_bandwidth_update,
760 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 761 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 762 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 763 },
27cd7769
AD		 764 .copy = {
765 .blit = &r100_copy_blit,
766 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
767 .dma = &r200_copy_dma,
768 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
769 .copy = &r100_copy_blit,
770 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
771 },
9e6f3d02
AD		 772 .surface = {
773 .set_reg = r100_set_surface_reg,
774 .clear_reg = r100_clear_surface_reg,
775 },
901ea57d
AD		 776 .hpd = {
777 .init = &rs600_hpd_init,
778 .fini = &rs600_hpd_fini,
779 .sense = &rs600_hpd_sense,
780 .set_polarity = &rs600_hpd_set_polarity,
781 },
a02fa397
AD		 782 .pm = {
783 .misc = &rs600_pm_misc,
784 .prepare = &rs600_pm_prepare,
785 .finish = &rs600_pm_finish,
786 .init_profile = &r420_pm_init_profile,
787 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 788 .get_engine_clock = &radeon_atom_get_engine_clock,
789 .set_engine_clock = &radeon_atom_set_engine_clock,
790 .get_memory_clock = &radeon_atom_get_memory_clock,
791 .set_memory_clock = &radeon_atom_set_memory_clock,
792 .get_pcie_lanes = &rv370_get_pcie_lanes,
793 .set_pcie_lanes = &rv370_set_pcie_lanes,
794 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 795 },
0f9e006c 796 .pflip = {
0f9e006c 797 .page_flip = &rs600_page_flip,
157fa14d 798 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 799 },
48e7a5f1
DV		 800};
801
802static struct radeon_asic r520_asic = {
803 .init = &r520_init,
804 .fini = &rv515_fini,
805 .suspend = &rv515_suspend,
806 .resume = &r520_resume,
807 .vga_set_state = &r100_vga_set_state,
90aca4d2 808 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 809 .ioctl_wait_idle = NULL,
810 .gui_idle = &r100_gui_idle,
811 .mc_wait_for_idle = &r520_mc_wait_for_idle,
c5b3b850
AD		 812 .gart = {
813 .tlb_flush = &rv370_pcie_gart_tlb_flush,
814 .set_page = &rv370_pcie_gart_set_page,
815 },
4c87bc26 816 .ring = {
76a0df85 817 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 818 },
b35ea4ab
AD		 819 .irq = {
820 .set = &rs600_irq_set,
821 .process = &rs600_irq_process,
822 },
c79a49ca
AD		 823 .display = {
824 .bandwidth_update = &rv515_bandwidth_update,
825 .get_vblank_counter = &rs600_get_vblank_counter,
826 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 827 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 828 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 829 },
27cd7769
AD		 830 .copy = {
831 .blit = &r100_copy_blit,
832 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
833 .dma = &r200_copy_dma,
834 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
835 .copy = &r100_copy_blit,
836 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
837 },
9e6f3d02
AD		 838 .surface = {
839 .set_reg = r100_set_surface_reg,
840 .clear_reg = r100_clear_surface_reg,
841 },
901ea57d
AD		 842 .hpd = {
843 .init = &rs600_hpd_init,
844 .fini = &rs600_hpd_fini,
845 .sense = &rs600_hpd_sense,
846 .set_polarity = &rs600_hpd_set_polarity,
847 },
a02fa397
AD		 848 .pm = {
849 .misc = &rs600_pm_misc,
850 .prepare = &rs600_pm_prepare,
851 .finish = &rs600_pm_finish,
852 .init_profile = &r420_pm_init_profile,
853 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 854 .get_engine_clock = &radeon_atom_get_engine_clock,
855 .set_engine_clock = &radeon_atom_set_engine_clock,
856 .get_memory_clock = &radeon_atom_get_memory_clock,
857 .set_memory_clock = &radeon_atom_set_memory_clock,
858 .get_pcie_lanes = &rv370_get_pcie_lanes,
859 .set_pcie_lanes = &rv370_set_pcie_lanes,
860 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 861 },
0f9e006c 862 .pflip = {
0f9e006c 863 .page_flip = &rs600_page_flip,
157fa14d 864 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 865 },
48e7a5f1
DV		 866};
867
76a0df85
CK		 868static struct radeon_asic_ring r600_gfx_ring = {
869 .ib_execute = &r600_ring_ib_execute,
870 .emit_fence = &r600_fence_ring_emit,
871 .emit_semaphore = &r600_semaphore_ring_emit,
872 .cs_parse = &r600_cs_parse,
873 .ring_test = &r600_ring_test,
874 .ib_test = &r600_ib_test,
875 .is_lockup = &r600_gfx_is_lockup,
ea31bf69
AD		 876 .get_rptr = &r600_gfx_get_rptr,
877 .get_wptr = &r600_gfx_get_wptr,
878 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 879};
880
881static struct radeon_asic_ring r600_dma_ring = {
882 .ib_execute = &r600_dma_ring_ib_execute,
883 .emit_fence = &r600_dma_fence_ring_emit,
884 .emit_semaphore = &r600_dma_semaphore_ring_emit,
885 .cs_parse = &r600_dma_cs_parse,
886 .ring_test = &r600_dma_ring_test,
887 .ib_test = &r600_dma_ib_test,
888 .is_lockup = &r600_dma_is_lockup,
2e1e6dad
CK		 889 .get_rptr = &r600_dma_get_rptr,
890 .get_wptr = &r600_dma_get_wptr,
891 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 892};
893
48e7a5f1
DV		 894static struct radeon_asic r600_asic = {
895 .init = &r600_init,
896 .fini = &r600_fini,
897 .suspend = &r600_suspend,
898 .resume = &r600_resume,
48e7a5f1 899 .vga_set_state = &r600_vga_set_state,
a2d07b74 900 .asic_reset = &r600_asic_reset,
54e88e06
AD		 901 .ioctl_wait_idle = r600_ioctl_wait_idle,
902 .gui_idle = &r600_gui_idle,
903 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 904 .get_xclk = &r600_get_xclk,
d0418894 905 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 906 .gart = {
907 .tlb_flush = &r600_pcie_gart_tlb_flush,
908 .set_page = &rs600_gart_set_page,
909 },
4c87bc26 910 .ring = {
76a0df85
CK		 911 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
912 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
4c87bc26 913 },
b35ea4ab
AD		 914 .irq = {
915 .set = &r600_irq_set,
916 .process = &r600_irq_process,
917 },
c79a49ca
AD		 918 .display = {
919 .bandwidth_update = &rv515_bandwidth_update,
920 .get_vblank_counter = &rs600_get_vblank_counter,
921 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 922 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 923 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 924 .hdmi_enable = &r600_hdmi_enable,
925 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 926 },
27cd7769 927 .copy = {
8dddb993 928 .blit = &r600_copy_cpdma,
27cd7769 929 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 930 .dma = &r600_copy_dma,
931 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 932 .copy = &r600_copy_cpdma,
aeea40cb 933 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 934 },
9e6f3d02
AD		 935 .surface = {
936 .set_reg = r600_set_surface_reg,
937 .clear_reg = r600_clear_surface_reg,
938 },
901ea57d
AD		 939 .hpd = {
940 .init = &r600_hpd_init,
941 .fini = &r600_hpd_fini,
942 .sense = &r600_hpd_sense,
943 .set_polarity = &r600_hpd_set_polarity,
944 },
a02fa397
AD		 945 .pm = {
946 .misc = &r600_pm_misc,
947 .prepare = &rs600_pm_prepare,
948 .finish = &rs600_pm_finish,
949 .init_profile = &r600_pm_init_profile,
950 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 951 .get_engine_clock = &radeon_atom_get_engine_clock,
952 .set_engine_clock = &radeon_atom_set_engine_clock,
953 .get_memory_clock = &radeon_atom_get_memory_clock,
954 .set_memory_clock = &radeon_atom_set_memory_clock,
955 .get_pcie_lanes = &r600_get_pcie_lanes,
956 .set_pcie_lanes = &r600_set_pcie_lanes,
957 .set_clock_gating = NULL,
6bd1c385 958 .get_temperature = &rv6xx_get_temp,
a02fa397 959 },
0f9e006c 960 .pflip = {
0f9e006c 961 .page_flip = &rs600_page_flip,
157fa14d 962 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 963 },
48e7a5f1
DV		 964};
965
ca361b65
AD		 966static struct radeon_asic rv6xx_asic = {
967 .init = &r600_init,
968 .fini = &r600_fini,
969 .suspend = &r600_suspend,
970 .resume = &r600_resume,
971 .vga_set_state = &r600_vga_set_state,
972 .asic_reset = &r600_asic_reset,
973 .ioctl_wait_idle = r600_ioctl_wait_idle,
974 .gui_idle = &r600_gui_idle,
975 .mc_wait_for_idle = &r600_mc_wait_for_idle,
976 .get_xclk = &r600_get_xclk,
977 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
978 .gart = {
979 .tlb_flush = &r600_pcie_gart_tlb_flush,
980 .set_page = &rs600_gart_set_page,
981 },
982 .ring = {
76a0df85
CK		 983 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
984 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
ca361b65
AD		 985 },
986 .irq = {
987 .set = &r600_irq_set,
988 .process = &r600_irq_process,
989 },
990 .display = {
991 .bandwidth_update = &rv515_bandwidth_update,
992 .get_vblank_counter = &rs600_get_vblank_counter,
993 .wait_for_vblank = &avivo_wait_for_vblank,
994 .set_backlight_level = &atombios_set_backlight_level,
995 .get_backlight_level = &atombios_get_backlight_level,
99d79aa2
AD		 996 .hdmi_enable = &r600_hdmi_enable,
997 .hdmi_setmode = &r600_hdmi_setmode,
ca361b65
AD		 998 },
999 .copy = {
8dddb993 1000 .blit = &r600_copy_cpdma,
ca361b65
AD		 1001 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1002 .dma = &r600_copy_dma,
1003 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1004 .copy = &r600_copy_cpdma,
aeea40cb 1005 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
ca361b65
AD		 1006 },
1007 .surface = {
1008 .set_reg = r600_set_surface_reg,
1009 .clear_reg = r600_clear_surface_reg,
1010 },
1011 .hpd = {
1012 .init = &r600_hpd_init,
1013 .fini = &r600_hpd_fini,
1014 .sense = &r600_hpd_sense,
1015 .set_polarity = &r600_hpd_set_polarity,
1016 },
1017 .pm = {
1018 .misc = &r600_pm_misc,
1019 .prepare = &rs600_pm_prepare,
1020 .finish = &rs600_pm_finish,
1021 .init_profile = &r600_pm_init_profile,
1022 .get_dynpm_state = &r600_pm_get_dynpm_state,
1023 .get_engine_clock = &radeon_atom_get_engine_clock,
1024 .set_engine_clock = &radeon_atom_set_engine_clock,
1025 .get_memory_clock = &radeon_atom_get_memory_clock,
1026 .set_memory_clock = &radeon_atom_set_memory_clock,
1027 .get_pcie_lanes = &r600_get_pcie_lanes,
1028 .set_pcie_lanes = &r600_set_pcie_lanes,
1029 .set_clock_gating = NULL,
1030 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1031 .set_uvd_clocks = &r600_set_uvd_clocks,
ca361b65 1032 },
4a6369e9
AD		 1033 .dpm = {
1034 .init = &rv6xx_dpm_init,
1035 .setup_asic = &rv6xx_setup_asic,
1036 .enable = &rv6xx_dpm_enable,
a4643ba3 1037 .late_enable = &r600_dpm_late_enable,
4a6369e9 1038 .disable = &rv6xx_dpm_disable,
98243917 1039 .pre_set_power_state = &r600_dpm_pre_set_power_state,
4a6369e9 1040 .set_power_state = &rv6xx_dpm_set_power_state,
98243917 1041 .post_set_power_state = &r600_dpm_post_set_power_state,
4a6369e9
AD		 1042 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1043 .fini = &rv6xx_dpm_fini,
1044 .get_sclk = &rv6xx_dpm_get_sclk,
1045 .get_mclk = &rv6xx_dpm_get_mclk,
1046 .print_power_state = &rv6xx_dpm_print_power_state,
242916a5 1047 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
f4f85a8c 1048 .force_performance_level = &rv6xx_dpm_force_performance_level,
4a6369e9 1049 },
ca361b65 1050 .pflip = {
ca361b65 1051 .page_flip = &rs600_page_flip,
157fa14d 1052 .page_flip_pending = &rs600_page_flip_pending,
ca361b65
AD		 1053 },
1054};
1055
f47299c5
AD		 1056static struct radeon_asic rs780_asic = {
1057 .init = &r600_init,
1058 .fini = &r600_fini,
1059 .suspend = &r600_suspend,
1060 .resume = &r600_resume,
f47299c5 1061 .vga_set_state = &r600_vga_set_state,
a2d07b74 1062 .asic_reset = &r600_asic_reset,
54e88e06
AD		 1063 .ioctl_wait_idle = r600_ioctl_wait_idle,
1064 .gui_idle = &r600_gui_idle,
1065 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1066 .get_xclk = &r600_get_xclk,
d0418894 1067 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1068 .gart = {
1069 .tlb_flush = &r600_pcie_gart_tlb_flush,
1070 .set_page = &rs600_gart_set_page,
1071 },
4c87bc26 1072 .ring = {
76a0df85
CK		 1073 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1074 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
4c87bc26 1075 },
b35ea4ab
AD		 1076 .irq = {
1077 .set = &r600_irq_set,
1078 .process = &r600_irq_process,
1079 },
c79a49ca
AD		 1080 .display = {
1081 .bandwidth_update = &rs690_bandwidth_update,
1082 .get_vblank_counter = &rs600_get_vblank_counter,
1083 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1084 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1085 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1086 .hdmi_enable = &r600_hdmi_enable,
1087 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1088 },
27cd7769 1089 .copy = {
8dddb993 1090 .blit = &r600_copy_cpdma,
27cd7769 1091 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1092 .dma = &r600_copy_dma,
1093 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1094 .copy = &r600_copy_cpdma,
aeea40cb 1095 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 1096 },
9e6f3d02
AD		 1097 .surface = {
1098 .set_reg = r600_set_surface_reg,
1099 .clear_reg = r600_clear_surface_reg,
1100 },
901ea57d
AD		 1101 .hpd = {
1102 .init = &r600_hpd_init,
1103 .fini = &r600_hpd_fini,
1104 .sense = &r600_hpd_sense,
1105 .set_polarity = &r600_hpd_set_polarity,
1106 },
a02fa397
AD		 1107 .pm = {
1108 .misc = &r600_pm_misc,
1109 .prepare = &rs600_pm_prepare,
1110 .finish = &rs600_pm_finish,
1111 .init_profile = &rs780_pm_init_profile,
1112 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1113 .get_engine_clock = &radeon_atom_get_engine_clock,
1114 .set_engine_clock = &radeon_atom_set_engine_clock,
1115 .get_memory_clock = NULL,
1116 .set_memory_clock = NULL,
1117 .get_pcie_lanes = NULL,
1118 .set_pcie_lanes = NULL,
1119 .set_clock_gating = NULL,
6bd1c385 1120 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1121 .set_uvd_clocks = &r600_set_uvd_clocks,
a02fa397 1122 },
9d67006e
AD		 1123 .dpm = {
1124 .init = &rs780_dpm_init,
1125 .setup_asic = &rs780_dpm_setup_asic,
1126 .enable = &rs780_dpm_enable,
a4643ba3 1127 .late_enable = &r600_dpm_late_enable,
9d67006e 1128 .disable = &rs780_dpm_disable,
98243917 1129 .pre_set_power_state = &r600_dpm_pre_set_power_state,
9d67006e 1130 .set_power_state = &rs780_dpm_set_power_state,
98243917 1131 .post_set_power_state = &r600_dpm_post_set_power_state,
9d67006e
AD		 1132 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1133 .fini = &rs780_dpm_fini,
1134 .get_sclk = &rs780_dpm_get_sclk,
1135 .get_mclk = &rs780_dpm_get_mclk,
1136 .print_power_state = &rs780_dpm_print_power_state,
444bddc4 1137 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
63580c3e 1138 .force_performance_level = &rs780_dpm_force_performance_level,
9d67006e 1139 },
0f9e006c 1140 .pflip = {
0f9e006c 1141 .page_flip = &rs600_page_flip,
157fa14d 1142 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 1143 },
f47299c5
AD		 1144};
1145
76a0df85 1146static struct radeon_asic_ring rv770_uvd_ring = {
e409b128
CK		 1147 .ib_execute = &uvd_v1_0_ib_execute,
1148 .emit_fence = &uvd_v2_2_fence_emit,
1149 .emit_semaphore = &uvd_v1_0_semaphore_emit,
76a0df85 1150 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1151 .ring_test = &uvd_v1_0_ring_test,
1152 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1153 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1154 .get_rptr = &uvd_v1_0_get_rptr,
1155 .get_wptr = &uvd_v1_0_get_wptr,
1156 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1157};
1158
48e7a5f1
DV		 1159static struct radeon_asic rv770_asic = {
1160 .init = &rv770_init,
1161 .fini = &rv770_fini,
1162 .suspend = &rv770_suspend,
1163 .resume = &rv770_resume,
a2d07b74 1164 .asic_reset = &r600_asic_reset,
48e7a5f1 1165 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1166 .ioctl_wait_idle = r600_ioctl_wait_idle,
1167 .gui_idle = &r600_gui_idle,
1168 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1169 .get_xclk = &rv770_get_xclk,
d0418894 1170 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1171 .gart = {
1172 .tlb_flush = &r600_pcie_gart_tlb_flush,
1173 .set_page = &rs600_gart_set_page,
1174 },
4c87bc26 1175 .ring = {
76a0df85
CK		 1176 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1177 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1178 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1179 },
b35ea4ab
AD		 1180 .irq = {
1181 .set = &r600_irq_set,
1182 .process = &r600_irq_process,
1183 },
c79a49ca
AD		 1184 .display = {
1185 .bandwidth_update = &rv515_bandwidth_update,
1186 .get_vblank_counter = &rs600_get_vblank_counter,
1187 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1188 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1189 .get_backlight_level = &atombios_get_backlight_level,
a973bea1 1190 .hdmi_enable = &r600_hdmi_enable,
8f33a156 1191 .hdmi_setmode = &dce3_1_hdmi_setmode,
c79a49ca 1192 },
27cd7769 1193 .copy = {
8dddb993 1194 .blit = &r600_copy_cpdma,
27cd7769 1195 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
43fb7787 1196 .dma = &rv770_copy_dma,
4d75658b 1197 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
43fb7787 1198 .copy = &rv770_copy_dma,
2d6cc729 1199 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1200 },
9e6f3d02
AD		 1201 .surface = {
1202 .set_reg = r600_set_surface_reg,
1203 .clear_reg = r600_clear_surface_reg,
1204 },
901ea57d
AD		 1205 .hpd = {
1206 .init = &r600_hpd_init,
1207 .fini = &r600_hpd_fini,
1208 .sense = &r600_hpd_sense,
1209 .set_polarity = &r600_hpd_set_polarity,
1210 },
a02fa397
AD		 1211 .pm = {
1212 .misc = &rv770_pm_misc,
1213 .prepare = &rs600_pm_prepare,
1214 .finish = &rs600_pm_finish,
1215 .init_profile = &r600_pm_init_profile,
1216 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1217 .get_engine_clock = &radeon_atom_get_engine_clock,
1218 .set_engine_clock = &radeon_atom_set_engine_clock,
1219 .get_memory_clock = &radeon_atom_get_memory_clock,
1220 .set_memory_clock = &radeon_atom_set_memory_clock,
1221 .get_pcie_lanes = &r600_get_pcie_lanes,
1222 .set_pcie_lanes = &r600_set_pcie_lanes,
1223 .set_clock_gating = &radeon_atom_set_clock_gating,
ef0e6e65 1224 .set_uvd_clocks = &rv770_set_uvd_clocks,
6bd1c385 1225 .get_temperature = &rv770_get_temp,
a02fa397 1226 },
66229b20
AD		 1227 .dpm = {
1228 .init = &rv770_dpm_init,
1229 .setup_asic = &rv770_dpm_setup_asic,
1230 .enable = &rv770_dpm_enable,
a3f11245 1231 .late_enable = &rv770_dpm_late_enable,
66229b20 1232 .disable = &rv770_dpm_disable,
98243917 1233 .pre_set_power_state = &r600_dpm_pre_set_power_state,
66229b20 1234 .set_power_state = &rv770_dpm_set_power_state,
98243917 1235 .post_set_power_state = &r600_dpm_post_set_power_state,
66229b20
AD		 1236 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1237 .fini = &rv770_dpm_fini,
1238 .get_sclk = &rv770_dpm_get_sclk,
1239 .get_mclk = &rv770_dpm_get_mclk,
1240 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1241 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1242 .force_performance_level = &rv770_dpm_force_performance_level,
b06195d9 1243 .vblank_too_short = &rv770_dpm_vblank_too_short,
66229b20 1244 },
0f9e006c 1245 .pflip = {
0f9e006c 1246 .page_flip = &rv770_page_flip,
157fa14d 1247 .page_flip_pending = &rv770_page_flip_pending,
0f9e006c 1248 },
48e7a5f1
DV		 1249};
1250
76a0df85
CK		 1251static struct radeon_asic_ring evergreen_gfx_ring = {
1252 .ib_execute = &evergreen_ring_ib_execute,
1253 .emit_fence = &r600_fence_ring_emit,
1254 .emit_semaphore = &r600_semaphore_ring_emit,
1255 .cs_parse = &evergreen_cs_parse,
1256 .ring_test = &r600_ring_test,
1257 .ib_test = &r600_ib_test,
1258 .is_lockup = &evergreen_gfx_is_lockup,
ea31bf69
AD		 1259 .get_rptr = &r600_gfx_get_rptr,
1260 .get_wptr = &r600_gfx_get_wptr,
1261 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 1262};
1263
1264static struct radeon_asic_ring evergreen_dma_ring = {
1265 .ib_execute = &evergreen_dma_ring_ib_execute,
1266 .emit_fence = &evergreen_dma_fence_ring_emit,
1267 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1268 .cs_parse = &evergreen_dma_cs_parse,
1269 .ring_test = &r600_dma_ring_test,
1270 .ib_test = &r600_dma_ib_test,
1271 .is_lockup = &evergreen_dma_is_lockup,
2e1e6dad
CK		 1272 .get_rptr = &r600_dma_get_rptr,
1273 .get_wptr = &r600_dma_get_wptr,
1274 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 1275};
1276
48e7a5f1
DV		 1277static struct radeon_asic evergreen_asic = {
1278 .init = &evergreen_init,
1279 .fini = &evergreen_fini,
1280 .suspend = &evergreen_suspend,
1281 .resume = &evergreen_resume,
a2d07b74 1282 .asic_reset = &evergreen_asic_reset,
48e7a5f1 1283 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1284 .ioctl_wait_idle = r600_ioctl_wait_idle,
1285 .gui_idle = &r600_gui_idle,
1286 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1287 .get_xclk = &rv770_get_xclk,
d0418894 1288 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1289 .gart = {
1290 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1291 .set_page = &rs600_gart_set_page,
1292 },
4c87bc26 1293 .ring = {
76a0df85
CK		 1294 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1295 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1296 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1297 },
b35ea4ab
AD		 1298 .irq = {
1299 .set = &evergreen_irq_set,
1300 .process = &evergreen_irq_process,
1301 },
c79a49ca
AD		 1302 .display = {
1303 .bandwidth_update = &evergreen_bandwidth_update,
1304 .get_vblank_counter = &evergreen_get_vblank_counter,
1305 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1306 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1307 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1308 .hdmi_enable = &evergreen_hdmi_enable,
1309 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1310 },
27cd7769 1311 .copy = {
8dddb993 1312 .blit = &r600_copy_cpdma,
27cd7769 1313 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1314 .dma = &evergreen_copy_dma,
1315 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1316 .copy = &evergreen_copy_dma,
1317 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1318 },
9e6f3d02
AD		 1319 .surface = {
1320 .set_reg = r600_set_surface_reg,
1321 .clear_reg = r600_clear_surface_reg,
1322 },
901ea57d
AD		 1323 .hpd = {
1324 .init = &evergreen_hpd_init,
1325 .fini = &evergreen_hpd_fini,
1326 .sense = &evergreen_hpd_sense,
1327 .set_polarity = &evergreen_hpd_set_polarity,
1328 },
a02fa397
AD		 1329 .pm = {
1330 .misc = &evergreen_pm_misc,
1331 .prepare = &evergreen_pm_prepare,
1332 .finish = &evergreen_pm_finish,
1333 .init_profile = &r600_pm_init_profile,
1334 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1335 .get_engine_clock = &radeon_atom_get_engine_clock,
1336 .set_engine_clock = &radeon_atom_set_engine_clock,
1337 .get_memory_clock = &radeon_atom_get_memory_clock,
1338 .set_memory_clock = &radeon_atom_set_memory_clock,
1339 .get_pcie_lanes = &r600_get_pcie_lanes,
1340 .set_pcie_lanes = &r600_set_pcie_lanes,
1341 .set_clock_gating = NULL,
a8b4925c 1342 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1343 .get_temperature = &evergreen_get_temp,
a02fa397 1344 },
dc50ba7f
AD		 1345 .dpm = {
1346 .init = &cypress_dpm_init,
1347 .setup_asic = &cypress_dpm_setup_asic,
1348 .enable = &cypress_dpm_enable,
a3f11245 1349 .late_enable = &rv770_dpm_late_enable,
dc50ba7f 1350 .disable = &cypress_dpm_disable,
98243917 1351 .pre_set_power_state = &r600_dpm_pre_set_power_state,
dc50ba7f 1352 .set_power_state = &cypress_dpm_set_power_state,
98243917 1353 .post_set_power_state = &r600_dpm_post_set_power_state,
dc50ba7f
AD		 1354 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1355 .fini = &cypress_dpm_fini,
1356 .get_sclk = &rv770_dpm_get_sclk,
1357 .get_mclk = &rv770_dpm_get_mclk,
1358 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1359 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1360 .force_performance_level = &rv770_dpm_force_performance_level,
d0b54bdc 1361 .vblank_too_short = &cypress_dpm_vblank_too_short,
dc50ba7f 1362 },
0f9e006c 1363 .pflip = {
0f9e006c 1364 .page_flip = &evergreen_page_flip,
157fa14d 1365 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1366 },
48e7a5f1
DV		 1367};
1368
958261d1
AD		 1369static struct radeon_asic sumo_asic = {
1370 .init = &evergreen_init,
1371 .fini = &evergreen_fini,
1372 .suspend = &evergreen_suspend,
1373 .resume = &evergreen_resume,
958261d1
AD		 1374 .asic_reset = &evergreen_asic_reset,
1375 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1376 .ioctl_wait_idle = r600_ioctl_wait_idle,
1377 .gui_idle = &r600_gui_idle,
1378 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1379 .get_xclk = &r600_get_xclk,
d0418894 1380 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1381 .gart = {
1382 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1383 .set_page = &rs600_gart_set_page,
1384 },
4c87bc26 1385 .ring = {
76a0df85
CK		 1386 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1387 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1388 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1389 },
b35ea4ab
AD		 1390 .irq = {
1391 .set = &evergreen_irq_set,
1392 .process = &evergreen_irq_process,
1393 },
c79a49ca
AD		 1394 .display = {
1395 .bandwidth_update = &evergreen_bandwidth_update,
1396 .get_vblank_counter = &evergreen_get_vblank_counter,
1397 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1398 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1399 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1400 .hdmi_enable = &evergreen_hdmi_enable,
1401 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1402 },
27cd7769 1403 .copy = {
8dddb993 1404 .blit = &r600_copy_cpdma,
27cd7769 1405 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1406 .dma = &evergreen_copy_dma,
1407 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1408 .copy = &evergreen_copy_dma,
1409 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1410 },
9e6f3d02
AD		 1411 .surface = {
1412 .set_reg = r600_set_surface_reg,
1413 .clear_reg = r600_clear_surface_reg,
1414 },
901ea57d
AD		 1415 .hpd = {
1416 .init = &evergreen_hpd_init,
1417 .fini = &evergreen_hpd_fini,
1418 .sense = &evergreen_hpd_sense,
1419 .set_polarity = &evergreen_hpd_set_polarity,
1420 },
a02fa397
AD		 1421 .pm = {
1422 .misc = &evergreen_pm_misc,
1423 .prepare = &evergreen_pm_prepare,
1424 .finish = &evergreen_pm_finish,
1425 .init_profile = &sumo_pm_init_profile,
1426 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1427 .get_engine_clock = &radeon_atom_get_engine_clock,
1428 .set_engine_clock = &radeon_atom_set_engine_clock,
1429 .get_memory_clock = NULL,
1430 .set_memory_clock = NULL,
1431 .get_pcie_lanes = NULL,
1432 .set_pcie_lanes = NULL,
1433 .set_clock_gating = NULL,
23d33ba3 1434 .set_uvd_clocks = &sumo_set_uvd_clocks,
6bd1c385 1435 .get_temperature = &sumo_get_temp,
a02fa397 1436 },
80ea2c12
AD		 1437 .dpm = {
1438 .init = &sumo_dpm_init,
1439 .setup_asic = &sumo_dpm_setup_asic,
1440 .enable = &sumo_dpm_enable,
14ec9fab 1441 .late_enable = &sumo_dpm_late_enable,
80ea2c12 1442 .disable = &sumo_dpm_disable,
422a56bc 1443 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
80ea2c12 1444 .set_power_state = &sumo_dpm_set_power_state,
422a56bc 1445 .post_set_power_state = &sumo_dpm_post_set_power_state,
80ea2c12
AD		 1446 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1447 .fini = &sumo_dpm_fini,
1448 .get_sclk = &sumo_dpm_get_sclk,
1449 .get_mclk = &sumo_dpm_get_mclk,
1450 .print_power_state = &sumo_dpm_print_power_state,
fb70160c 1451 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
5d5e5591 1452 .force_performance_level = &sumo_dpm_force_performance_level,
80ea2c12 1453 },
0f9e006c 1454 .pflip = {
0f9e006c 1455 .page_flip = &evergreen_page_flip,
157fa14d 1456 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1457 },
958261d1
AD		 1458};
1459
a43b7665
AD		 1460static struct radeon_asic btc_asic = {
1461 .init = &evergreen_init,
1462 .fini = &evergreen_fini,
1463 .suspend = &evergreen_suspend,
1464 .resume = &evergreen_resume,
a43b7665
AD		 1465 .asic_reset = &evergreen_asic_reset,
1466 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1467 .ioctl_wait_idle = r600_ioctl_wait_idle,
1468 .gui_idle = &r600_gui_idle,
1469 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1470 .get_xclk = &rv770_get_xclk,
d0418894 1471 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1472 .gart = {
1473 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1474 .set_page = &rs600_gart_set_page,
1475 },
4c87bc26 1476 .ring = {
76a0df85
CK		 1477 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1478 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1479 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1480 },
b35ea4ab
AD		 1481 .irq = {
1482 .set = &evergreen_irq_set,
1483 .process = &evergreen_irq_process,
1484 },
c79a49ca
AD		 1485 .display = {
1486 .bandwidth_update = &evergreen_bandwidth_update,
1487 .get_vblank_counter = &evergreen_get_vblank_counter,
1488 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1489 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1490 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1491 .hdmi_enable = &evergreen_hdmi_enable,
1492 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1493 },
27cd7769 1494 .copy = {
8dddb993 1495 .blit = &r600_copy_cpdma,
27cd7769 1496 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1497 .dma = &evergreen_copy_dma,
1498 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1499 .copy = &evergreen_copy_dma,
1500 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1501 },
9e6f3d02
AD		 1502 .surface = {
1503 .set_reg = r600_set_surface_reg,
1504 .clear_reg = r600_clear_surface_reg,
1505 },
901ea57d
AD		 1506 .hpd = {
1507 .init = &evergreen_hpd_init,
1508 .fini = &evergreen_hpd_fini,
1509 .sense = &evergreen_hpd_sense,
1510 .set_polarity = &evergreen_hpd_set_polarity,
1511 },
a02fa397
AD		 1512 .pm = {
1513 .misc = &evergreen_pm_misc,
1514 .prepare = &evergreen_pm_prepare,
1515 .finish = &evergreen_pm_finish,
27810fb2 1516 .init_profile = &btc_pm_init_profile,
a02fa397 1517 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1518 .get_engine_clock = &radeon_atom_get_engine_clock,
1519 .set_engine_clock = &radeon_atom_set_engine_clock,
1520 .get_memory_clock = &radeon_atom_get_memory_clock,
1521 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1522 .get_pcie_lanes = &r600_get_pcie_lanes,
1523 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1524 .set_clock_gating = NULL,
a8b4925c 1525 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1526 .get_temperature = &evergreen_get_temp,
a02fa397 1527 },
6596afd4
AD		 1528 .dpm = {
1529 .init = &btc_dpm_init,
1530 .setup_asic = &btc_dpm_setup_asic,
1531 .enable = &btc_dpm_enable,
a3f11245 1532 .late_enable = &rv770_dpm_late_enable,
6596afd4 1533 .disable = &btc_dpm_disable,
e8a9539f 1534 .pre_set_power_state = &btc_dpm_pre_set_power_state,
6596afd4 1535 .set_power_state = &btc_dpm_set_power_state,
e8a9539f 1536 .post_set_power_state = &btc_dpm_post_set_power_state,
6596afd4
AD		 1537 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1538 .fini = &btc_dpm_fini,
e8a9539f
AD		 1539 .get_sclk = &btc_dpm_get_sclk,
1540 .get_mclk = &btc_dpm_get_mclk,
6596afd4 1541 .print_power_state = &rv770_dpm_print_power_state,
9f3f63f2 1542 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1543 .force_performance_level = &rv770_dpm_force_performance_level,
a84301c6 1544 .vblank_too_short = &btc_dpm_vblank_too_short,
6596afd4 1545 },
0f9e006c 1546 .pflip = {
0f9e006c 1547 .page_flip = &evergreen_page_flip,
157fa14d 1548 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1549 },
a43b7665
AD		 1550};
1551
76a0df85
CK		 1552static struct radeon_asic_ring cayman_gfx_ring = {
1553 .ib_execute = &cayman_ring_ib_execute,
1554 .ib_parse = &evergreen_ib_parse,
1555 .emit_fence = &cayman_fence_ring_emit,
1556 .emit_semaphore = &r600_semaphore_ring_emit,
1557 .cs_parse = &evergreen_cs_parse,
1558 .ring_test = &r600_ring_test,
1559 .ib_test = &r600_ib_test,
1560 .is_lockup = &cayman_gfx_is_lockup,
1561 .vm_flush = &cayman_vm_flush,
ea31bf69
AD		 1562 .get_rptr = &cayman_gfx_get_rptr,
1563 .get_wptr = &cayman_gfx_get_wptr,
1564 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1565};
1566
1567static struct radeon_asic_ring cayman_dma_ring = {
1568 .ib_execute = &cayman_dma_ring_ib_execute,
1569 .ib_parse = &evergreen_dma_ib_parse,
1570 .emit_fence = &evergreen_dma_fence_ring_emit,
1571 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1572 .cs_parse = &evergreen_dma_cs_parse,
1573 .ring_test = &r600_dma_ring_test,
1574 .ib_test = &r600_dma_ib_test,
1575 .is_lockup = &cayman_dma_is_lockup,
1576 .vm_flush = &cayman_dma_vm_flush,
ea31bf69
AD		 1577 .get_rptr = &cayman_dma_get_rptr,
1578 .get_wptr = &cayman_dma_get_wptr,
1579 .set_wptr = &cayman_dma_set_wptr
76a0df85
CK		 1580};
1581
1582static struct radeon_asic_ring cayman_uvd_ring = {
e409b128
CK		 1583 .ib_execute = &uvd_v1_0_ib_execute,
1584 .emit_fence = &uvd_v2_2_fence_emit,
1585 .emit_semaphore = &uvd_v3_1_semaphore_emit,
76a0df85 1586 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1587 .ring_test = &uvd_v1_0_ring_test,
1588 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1589 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1590 .get_rptr = &uvd_v1_0_get_rptr,
1591 .get_wptr = &uvd_v1_0_get_wptr,
1592 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1593};
1594
e3487629
AD		 1595static struct radeon_asic cayman_asic = {
1596 .init = &cayman_init,
1597 .fini = &cayman_fini,
1598 .suspend = &cayman_suspend,
1599 .resume = &cayman_resume,
e3487629
AD		 1600 .asic_reset = &cayman_asic_reset,
1601 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1602 .ioctl_wait_idle = r600_ioctl_wait_idle,
1603 .gui_idle = &r600_gui_idle,
1604 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1605 .get_xclk = &rv770_get_xclk,
d0418894 1606 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1607 .gart = {
1608 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1609 .set_page = &rs600_gart_set_page,
1610 },
05b07147
CK		 1611 .vm = {
1612 .init = &cayman_vm_init,
1613 .fini = &cayman_vm_fini,
24c16439 1614 .set_page = &cayman_dma_vm_set_page,
05b07147 1615 },
4c87bc26 1616 .ring = {
76a0df85
CK		 1617 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1618 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1619 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1620 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1621 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1622 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
4c87bc26 1623 },
b35ea4ab
AD		 1624 .irq = {
1625 .set = &evergreen_irq_set,
1626 .process = &evergreen_irq_process,
1627 },
c79a49ca
AD		 1628 .display = {
1629 .bandwidth_update = &evergreen_bandwidth_update,
1630 .get_vblank_counter = &evergreen_get_vblank_counter,
1631 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1632 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1633 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1634 .hdmi_enable = &evergreen_hdmi_enable,
1635 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1636 },
27cd7769 1637 .copy = {
8dddb993 1638 .blit = &r600_copy_cpdma,
27cd7769 1639 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1640 .dma = &evergreen_copy_dma,
1641 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1642 .copy = &evergreen_copy_dma,
1643 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1644 },
9e6f3d02
AD		 1645 .surface = {
1646 .set_reg = r600_set_surface_reg,
1647 .clear_reg = r600_clear_surface_reg,
1648 },
901ea57d
AD		 1649 .hpd = {
1650 .init = &evergreen_hpd_init,
1651 .fini = &evergreen_hpd_fini,
1652 .sense = &evergreen_hpd_sense,
1653 .set_polarity = &evergreen_hpd_set_polarity,
1654 },
a02fa397
AD		 1655 .pm = {
1656 .misc = &evergreen_pm_misc,
1657 .prepare = &evergreen_pm_prepare,
1658 .finish = &evergreen_pm_finish,
27810fb2 1659 .init_profile = &btc_pm_init_profile,
a02fa397 1660 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1661 .get_engine_clock = &radeon_atom_get_engine_clock,
1662 .set_engine_clock = &radeon_atom_set_engine_clock,
1663 .get_memory_clock = &radeon_atom_get_memory_clock,
1664 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1665 .get_pcie_lanes = &r600_get_pcie_lanes,
1666 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1667 .set_clock_gating = NULL,
a8b4925c 1668 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1669 .get_temperature = &evergreen_get_temp,
a02fa397 1670 },
69e0b57a
AD		 1671 .dpm = {
1672 .init = &ni_dpm_init,
1673 .setup_asic = &ni_dpm_setup_asic,
1674 .enable = &ni_dpm_enable,
a3f11245 1675 .late_enable = &rv770_dpm_late_enable,
69e0b57a 1676 .disable = &ni_dpm_disable,
fee3d744 1677 .pre_set_power_state = &ni_dpm_pre_set_power_state,
69e0b57a 1678 .set_power_state = &ni_dpm_set_power_state,
fee3d744 1679 .post_set_power_state = &ni_dpm_post_set_power_state,
69e0b57a
AD		 1680 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1681 .fini = &ni_dpm_fini,
1682 .get_sclk = &ni_dpm_get_sclk,
1683 .get_mclk = &ni_dpm_get_mclk,
1684 .print_power_state = &ni_dpm_print_power_state,
bdf0c4f0 1685 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
170a47f0 1686 .force_performance_level = &ni_dpm_force_performance_level,
76ad73e5 1687 .vblank_too_short = &ni_dpm_vblank_too_short,
69e0b57a 1688 },
0f9e006c 1689 .pflip = {
0f9e006c 1690 .page_flip = &evergreen_page_flip,
157fa14d 1691 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1692 },
e3487629
AD		 1693};
1694
be63fe8c
AD		 1695static struct radeon_asic trinity_asic = {
1696 .init = &cayman_init,
1697 .fini = &cayman_fini,
1698 .suspend = &cayman_suspend,
1699 .resume = &cayman_resume,
be63fe8c
AD		 1700 .asic_reset = &cayman_asic_reset,
1701 .vga_set_state = &r600_vga_set_state,
1702 .ioctl_wait_idle = r600_ioctl_wait_idle,
1703 .gui_idle = &r600_gui_idle,
1704 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1705 .get_xclk = &r600_get_xclk,
d0418894 1706 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
be63fe8c
AD		 1707 .gart = {
1708 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1709 .set_page = &rs600_gart_set_page,
1710 },
05b07147
CK		 1711 .vm = {
1712 .init = &cayman_vm_init,
1713 .fini = &cayman_vm_fini,
24c16439 1714 .set_page = &cayman_dma_vm_set_page,
05b07147 1715 },
be63fe8c 1716 .ring = {
76a0df85
CK		 1717 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1718 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1719 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1720 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1721 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1722 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
be63fe8c
AD		 1723 },
1724 .irq = {
1725 .set = &evergreen_irq_set,
1726 .process = &evergreen_irq_process,
1727 },
1728 .display = {
1729 .bandwidth_update = &dce6_bandwidth_update,
1730 .get_vblank_counter = &evergreen_get_vblank_counter,
1731 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1732 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1733 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 1734 .hdmi_enable = &evergreen_hdmi_enable,
1735 .hdmi_setmode = &evergreen_hdmi_setmode,
be63fe8c
AD		 1736 },
1737 .copy = {
8dddb993 1738 .blit = &r600_copy_cpdma,
be63fe8c 1739 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1740 .dma = &evergreen_copy_dma,
1741 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1742 .copy = &evergreen_copy_dma,
1743 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
be63fe8c
AD		 1744 },
1745 .surface = {
1746 .set_reg = r600_set_surface_reg,
1747 .clear_reg = r600_clear_surface_reg,
1748 },
1749 .hpd = {
1750 .init = &evergreen_hpd_init,
1751 .fini = &evergreen_hpd_fini,
1752 .sense = &evergreen_hpd_sense,
1753 .set_polarity = &evergreen_hpd_set_polarity,
1754 },
1755 .pm = {
1756 .misc = &evergreen_pm_misc,
1757 .prepare = &evergreen_pm_prepare,
1758 .finish = &evergreen_pm_finish,
1759 .init_profile = &sumo_pm_init_profile,
1760 .get_dynpm_state = &r600_pm_get_dynpm_state,
1761 .get_engine_clock = &radeon_atom_get_engine_clock,
1762 .set_engine_clock = &radeon_atom_set_engine_clock,
1763 .get_memory_clock = NULL,
1764 .set_memory_clock = NULL,
1765 .get_pcie_lanes = NULL,
1766 .set_pcie_lanes = NULL,
1767 .set_clock_gating = NULL,
23d33ba3 1768 .set_uvd_clocks = &sumo_set_uvd_clocks,
29a15221 1769 .get_temperature = &tn_get_temp,
be63fe8c 1770 },
d70229f7
AD		 1771 .dpm = {
1772 .init = &trinity_dpm_init,
1773 .setup_asic = &trinity_dpm_setup_asic,
1774 .enable = &trinity_dpm_enable,
bda44c1a 1775 .late_enable = &trinity_dpm_late_enable,
d70229f7 1776 .disable = &trinity_dpm_disable,
a284c48a 1777 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
d70229f7 1778 .set_power_state = &trinity_dpm_set_power_state,
a284c48a 1779 .post_set_power_state = &trinity_dpm_post_set_power_state,
d70229f7
AD		 1780 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1781 .fini = &trinity_dpm_fini,
1782 .get_sclk = &trinity_dpm_get_sclk,
1783 .get_mclk = &trinity_dpm_get_mclk,
1784 .print_power_state = &trinity_dpm_print_power_state,
490ab931 1785 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
9b5de596 1786 .force_performance_level = &trinity_dpm_force_performance_level,
11877060 1787 .enable_bapm = &trinity_dpm_enable_bapm,
d70229f7 1788 },
be63fe8c 1789 .pflip = {
be63fe8c 1790 .page_flip = &evergreen_page_flip,
157fa14d 1791 .page_flip_pending = &evergreen_page_flip_pending,
be63fe8c
AD		 1792 },
1793};
1794
76a0df85
CK		 1795static struct radeon_asic_ring si_gfx_ring = {
1796 .ib_execute = &si_ring_ib_execute,
1797 .ib_parse = &si_ib_parse,
1798 .emit_fence = &si_fence_ring_emit,
1799 .emit_semaphore = &r600_semaphore_ring_emit,
1800 .cs_parse = NULL,
1801 .ring_test = &r600_ring_test,
1802 .ib_test = &r600_ib_test,
1803 .is_lockup = &si_gfx_is_lockup,
1804 .vm_flush = &si_vm_flush,
ea31bf69
AD		 1805 .get_rptr = &cayman_gfx_get_rptr,
1806 .get_wptr = &cayman_gfx_get_wptr,
1807 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1808};
1809
1810static struct radeon_asic_ring si_dma_ring = {
1811 .ib_execute = &cayman_dma_ring_ib_execute,
1812 .ib_parse = &evergreen_dma_ib_parse,
1813 .emit_fence = &evergreen_dma_fence_ring_emit,
1814 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1815 .cs_parse = NULL,
1816 .ring_test = &r600_dma_ring_test,
1817 .ib_test = &r600_dma_ib_test,
1818 .is_lockup = &si_dma_is_lockup,
1819 .vm_flush = &si_dma_vm_flush,
ea31bf69
AD		 1820 .get_rptr = &cayman_dma_get_rptr,
1821 .get_wptr = &cayman_dma_get_wptr,
1822 .set_wptr = &cayman_dma_set_wptr,
76a0df85
CK		 1823};
1824
02779c08
AD		 1825static struct radeon_asic si_asic = {
1826 .init = &si_init,
1827 .fini = &si_fini,
1828 .suspend = &si_suspend,
1829 .resume = &si_resume,
02779c08
AD		 1830 .asic_reset = &si_asic_reset,
1831 .vga_set_state = &r600_vga_set_state,
1832 .ioctl_wait_idle = r600_ioctl_wait_idle,
1833 .gui_idle = &r600_gui_idle,
1834 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1835 .get_xclk = &si_get_xclk,
d0418894 1836 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
02779c08
AD		 1837 .gart = {
1838 .tlb_flush = &si_pcie_gart_tlb_flush,
1839 .set_page = &rs600_gart_set_page,
1840 },
05b07147
CK		 1841 .vm = {
1842 .init = &si_vm_init,
1843 .fini = &si_vm_fini,
24c16439 1844 .set_page = &si_dma_vm_set_page,
05b07147 1845 },
02779c08 1846 .ring = {
76a0df85
CK		 1847 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1848 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1849 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1850 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1851 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1852 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
02779c08
AD		 1853 },
1854 .irq = {
1855 .set = &si_irq_set,
1856 .process = &si_irq_process,
1857 },
1858 .display = {
1859 .bandwidth_update = &dce6_bandwidth_update,
1860 .get_vblank_counter = &evergreen_get_vblank_counter,
1861 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1862 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1863 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 1864 .hdmi_enable = &evergreen_hdmi_enable,
1865 .hdmi_setmode = &evergreen_hdmi_setmode,
02779c08
AD		 1866 },
1867 .copy = {
5c722739 1868 .blit = &r600_copy_cpdma,
02779c08 1869 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
8c5fd7ef
AD		 1870 .dma = &si_copy_dma,
1871 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1872 .copy = &si_copy_dma,
1873 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
02779c08
AD		 1874 },
1875 .surface = {
1876 .set_reg = r600_set_surface_reg,
1877 .clear_reg = r600_clear_surface_reg,
1878 },
1879 .hpd = {
1880 .init = &evergreen_hpd_init,
1881 .fini = &evergreen_hpd_fini,
1882 .sense = &evergreen_hpd_sense,
1883 .set_polarity = &evergreen_hpd_set_polarity,
1884 },
1885 .pm = {
1886 .misc = &evergreen_pm_misc,
1887 .prepare = &evergreen_pm_prepare,
1888 .finish = &evergreen_pm_finish,
1889 .init_profile = &sumo_pm_init_profile,
1890 .get_dynpm_state = &r600_pm_get_dynpm_state,
1891 .get_engine_clock = &radeon_atom_get_engine_clock,
1892 .set_engine_clock = &radeon_atom_set_engine_clock,
1893 .get_memory_clock = &radeon_atom_get_memory_clock,
1894 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1895 .get_pcie_lanes = &r600_get_pcie_lanes,
1896 .set_pcie_lanes = &r600_set_pcie_lanes,
02779c08 1897 .set_clock_gating = NULL,
2539eb02 1898 .set_uvd_clocks = &si_set_uvd_clocks,
6bd1c385 1899 .get_temperature = &si_get_temp,
02779c08 1900 },
a9e61410
AD		 1901 .dpm = {
1902 .init = &si_dpm_init,
1903 .setup_asic = &si_dpm_setup_asic,
1904 .enable = &si_dpm_enable,
963c115d 1905 .late_enable = &si_dpm_late_enable,
a9e61410
AD		 1906 .disable = &si_dpm_disable,
1907 .pre_set_power_state = &si_dpm_pre_set_power_state,
1908 .set_power_state = &si_dpm_set_power_state,
1909 .post_set_power_state = &si_dpm_post_set_power_state,
1910 .display_configuration_changed = &si_dpm_display_configuration_changed,
1911 .fini = &si_dpm_fini,
1912 .get_sclk = &ni_dpm_get_sclk,
1913 .get_mclk = &ni_dpm_get_mclk,
1914 .print_power_state = &ni_dpm_print_power_state,
7982128c 1915 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
a160a6a3 1916 .force_performance_level = &si_dpm_force_performance_level,
f4dec318 1917 .vblank_too_short = &ni_dpm_vblank_too_short,
a9e61410 1918 },
02779c08 1919 .pflip = {
02779c08 1920 .page_flip = &evergreen_page_flip,
157fa14d 1921 .page_flip_pending = &evergreen_page_flip_pending,
02779c08
AD		 1922 },
1923};
1924
76a0df85
CK		 1925static struct radeon_asic_ring ci_gfx_ring = {
1926 .ib_execute = &cik_ring_ib_execute,
1927 .ib_parse = &cik_ib_parse,
1928 .emit_fence = &cik_fence_gfx_ring_emit,
1929 .emit_semaphore = &cik_semaphore_ring_emit,
1930 .cs_parse = NULL,
1931 .ring_test = &cik_ring_test,
1932 .ib_test = &cik_ib_test,
1933 .is_lockup = &cik_gfx_is_lockup,
1934 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 1935 .get_rptr = &cik_gfx_get_rptr,
1936 .get_wptr = &cik_gfx_get_wptr,
1937 .set_wptr = &cik_gfx_set_wptr,
76a0df85
CK		 1938};
1939
1940static struct radeon_asic_ring ci_cp_ring = {
1941 .ib_execute = &cik_ring_ib_execute,
1942 .ib_parse = &cik_ib_parse,
1943 .emit_fence = &cik_fence_compute_ring_emit,
1944 .emit_semaphore = &cik_semaphore_ring_emit,
1945 .cs_parse = NULL,
1946 .ring_test = &cik_ring_test,
1947 .ib_test = &cik_ib_test,
1948 .is_lockup = &cik_gfx_is_lockup,
1949 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 1950 .get_rptr = &cik_compute_get_rptr,
1951 .get_wptr = &cik_compute_get_wptr,
1952 .set_wptr = &cik_compute_set_wptr,
76a0df85
CK		 1953};
1954
1955static struct radeon_asic_ring ci_dma_ring = {
1956 .ib_execute = &cik_sdma_ring_ib_execute,
1957 .ib_parse = &cik_ib_parse,
1958 .emit_fence = &cik_sdma_fence_ring_emit,
1959 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1960 .cs_parse = NULL,
1961 .ring_test = &cik_sdma_ring_test,
1962 .ib_test = &cik_sdma_ib_test,
1963 .is_lockup = &cik_sdma_is_lockup,
1964 .vm_flush = &cik_dma_vm_flush,
ea31bf69
AD		 1965 .get_rptr = &cik_sdma_get_rptr,
1966 .get_wptr = &cik_sdma_get_wptr,
1967 .set_wptr = &cik_sdma_set_wptr,
76a0df85
CK		 1968};
1969
d93f7937
CK		 1970static struct radeon_asic_ring ci_vce_ring = {
1971 .ib_execute = &radeon_vce_ib_execute,
1972 .emit_fence = &radeon_vce_fence_emit,
1973 .emit_semaphore = &radeon_vce_semaphore_emit,
1974 .cs_parse = &radeon_vce_cs_parse,
1975 .ring_test = &radeon_vce_ring_test,
1976 .ib_test = &radeon_vce_ib_test,
1977 .is_lockup = &radeon_ring_test_lockup,
1978 .get_rptr = &vce_v1_0_get_rptr,
1979 .get_wptr = &vce_v1_0_get_wptr,
1980 .set_wptr = &vce_v1_0_set_wptr,
1981};
1982
0672e27b
AD		 1983static struct radeon_asic ci_asic = {
1984 .init = &cik_init,
1985 .fini = &cik_fini,
1986 .suspend = &cik_suspend,
1987 .resume = &cik_resume,
1988 .asic_reset = &cik_asic_reset,
1989 .vga_set_state = &r600_vga_set_state,
1990 .ioctl_wait_idle = NULL,
1991 .gui_idle = &r600_gui_idle,
1992 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1993 .get_xclk = &cik_get_xclk,
1994 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
1995 .gart = {
1996 .tlb_flush = &cik_pcie_gart_tlb_flush,
1997 .set_page = &rs600_gart_set_page,
1998 },
1999 .vm = {
2000 .init = &cik_vm_init,
2001 .fini = &cik_vm_fini,
24c16439 2002 .set_page = &cik_sdma_vm_set_page,
0672e27b
AD		 2003 },
2004 .ring = {
76a0df85
CK		 2005 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2006 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2007 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2008 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2009 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2010 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2011 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2012 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2013 },
2014 .irq = {
2015 .set = &cik_irq_set,
2016 .process = &cik_irq_process,
2017 },
2018 .display = {
2019 .bandwidth_update = &dce8_bandwidth_update,
2020 .get_vblank_counter = &evergreen_get_vblank_counter,
2021 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2022 .set_backlight_level = &atombios_set_backlight_level,
2023 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 2024 .hdmi_enable = &evergreen_hdmi_enable,
2025 .hdmi_setmode = &evergreen_hdmi_setmode,
0672e27b
AD		 2026 },
2027 .copy = {
7819678f 2028 .blit = &cik_copy_cpdma,
0672e27b
AD		 2029 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2030 .dma = &cik_copy_dma,
2031 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
b5be1a83
CK		 2032 .copy = &cik_copy_dma,
2033 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
0672e27b
AD		 2034 },
2035 .surface = {
2036 .set_reg = r600_set_surface_reg,
2037 .clear_reg = r600_clear_surface_reg,
2038 },
2039 .hpd = {
2040 .init = &evergreen_hpd_init,
2041 .fini = &evergreen_hpd_fini,
2042 .sense = &evergreen_hpd_sense,
2043 .set_polarity = &evergreen_hpd_set_polarity,
2044 },
2045 .pm = {
2046 .misc = &evergreen_pm_misc,
2047 .prepare = &evergreen_pm_prepare,
2048 .finish = &evergreen_pm_finish,
2049 .init_profile = &sumo_pm_init_profile,
2050 .get_dynpm_state = &r600_pm_get_dynpm_state,
2051 .get_engine_clock = &radeon_atom_get_engine_clock,
2052 .set_engine_clock = &radeon_atom_set_engine_clock,
2053 .get_memory_clock = &radeon_atom_get_memory_clock,
2054 .set_memory_clock = &radeon_atom_set_memory_clock,
2055 .get_pcie_lanes = NULL,
2056 .set_pcie_lanes = NULL,
2057 .set_clock_gating = NULL,
2058 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2059 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2060 .get_temperature = &ci_get_temp,
0672e27b 2061 },
cc8dbbb4
AD		 2062 .dpm = {
2063 .init = &ci_dpm_init,
2064 .setup_asic = &ci_dpm_setup_asic,
2065 .enable = &ci_dpm_enable,
90208427 2066 .late_enable = &ci_dpm_late_enable,
cc8dbbb4
AD		 2067 .disable = &ci_dpm_disable,
2068 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2069 .set_power_state = &ci_dpm_set_power_state,
2070 .post_set_power_state = &ci_dpm_post_set_power_state,
2071 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2072 .fini = &ci_dpm_fini,
2073 .get_sclk = &ci_dpm_get_sclk,
2074 .get_mclk = &ci_dpm_get_mclk,
2075 .print_power_state = &ci_dpm_print_power_state,
94b4adc5 2076 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
89536fd6 2077 .force_performance_level = &ci_dpm_force_performance_level,
5496131e 2078 .vblank_too_short = &ci_dpm_vblank_too_short,
942bdf7f 2079 .powergate_uvd = &ci_dpm_powergate_uvd,
cc8dbbb4 2080 },
0672e27b 2081 .pflip = {
0672e27b 2082 .page_flip = &evergreen_page_flip,
157fa14d 2083 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2084 },
2085};
2086
2087static struct radeon_asic kv_asic = {
2088 .init = &cik_init,
2089 .fini = &cik_fini,
2090 .suspend = &cik_suspend,
2091 .resume = &cik_resume,
2092 .asic_reset = &cik_asic_reset,
2093 .vga_set_state = &r600_vga_set_state,
2094 .ioctl_wait_idle = NULL,
2095 .gui_idle = &r600_gui_idle,
2096 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2097 .get_xclk = &cik_get_xclk,
2098 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2099 .gart = {
2100 .tlb_flush = &cik_pcie_gart_tlb_flush,
2101 .set_page = &rs600_gart_set_page,
2102 },
2103 .vm = {
2104 .init = &cik_vm_init,
2105 .fini = &cik_vm_fini,
24c16439 2106 .set_page = &cik_sdma_vm_set_page,
0672e27b
AD		 2107 },
2108 .ring = {
76a0df85
CK		 2109 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2110 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2111 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2112 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2113 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2114 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2115 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2116 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2117 },
2118 .irq = {
2119 .set = &cik_irq_set,
2120 .process = &cik_irq_process,
2121 },
2122 .display = {
2123 .bandwidth_update = &dce8_bandwidth_update,
2124 .get_vblank_counter = &evergreen_get_vblank_counter,
2125 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2126 .set_backlight_level = &atombios_set_backlight_level,
2127 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 2128 .hdmi_enable = &evergreen_hdmi_enable,
2129 .hdmi_setmode = &evergreen_hdmi_setmode,
0672e27b
AD		 2130 },
2131 .copy = {
7819678f 2132 .blit = &cik_copy_cpdma,
0672e27b
AD		 2133 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2134 .dma = &cik_copy_dma,
2135 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2136 .copy = &cik_copy_dma,
2137 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2138 },
2139 .surface = {
2140 .set_reg = r600_set_surface_reg,
2141 .clear_reg = r600_clear_surface_reg,
2142 },
2143 .hpd = {
2144 .init = &evergreen_hpd_init,
2145 .fini = &evergreen_hpd_fini,
2146 .sense = &evergreen_hpd_sense,
2147 .set_polarity = &evergreen_hpd_set_polarity,
2148 },
2149 .pm = {
2150 .misc = &evergreen_pm_misc,
2151 .prepare = &evergreen_pm_prepare,
2152 .finish = &evergreen_pm_finish,
2153 .init_profile = &sumo_pm_init_profile,
2154 .get_dynpm_state = &r600_pm_get_dynpm_state,
2155 .get_engine_clock = &radeon_atom_get_engine_clock,
2156 .set_engine_clock = &radeon_atom_set_engine_clock,
2157 .get_memory_clock = &radeon_atom_get_memory_clock,
2158 .set_memory_clock = &radeon_atom_set_memory_clock,
2159 .get_pcie_lanes = NULL,
2160 .set_pcie_lanes = NULL,
2161 .set_clock_gating = NULL,
2162 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2163 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2164 .get_temperature = &kv_get_temp,
0672e27b 2165 },
41a524ab
AD		 2166 .dpm = {
2167 .init = &kv_dpm_init,
2168 .setup_asic = &kv_dpm_setup_asic,
2169 .enable = &kv_dpm_enable,
d8852c34 2170 .late_enable = &kv_dpm_late_enable,
41a524ab
AD		 2171 .disable = &kv_dpm_disable,
2172 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2173 .set_power_state = &kv_dpm_set_power_state,
2174 .post_set_power_state = &kv_dpm_post_set_power_state,
2175 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2176 .fini = &kv_dpm_fini,
2177 .get_sclk = &kv_dpm_get_sclk,
2178 .get_mclk = &kv_dpm_get_mclk,
2179 .print_power_state = &kv_dpm_print_power_state,
ae3e40e8 2180 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2b4c8022 2181 .force_performance_level = &kv_dpm_force_performance_level,
77df508a 2182 .powergate_uvd = &kv_dpm_powergate_uvd,
b7a5ae97 2183 .enable_bapm = &kv_dpm_enable_bapm,
41a524ab 2184 },
0672e27b 2185 .pflip = {
0672e27b 2186 .page_flip = &evergreen_page_flip,
157fa14d 2187 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2188 },
2189};
2190
abf1dc67
AD		 2191/**
2192 * radeon_asic_init - register asic specific callbacks
2193 *
2194 * @rdev: radeon device pointer
2195 *
2196 * Registers the appropriate asic specific callbacks for each
2197 * chip family. Also sets other asics specific info like the number
2198 * of crtcs and the register aperture accessors (all asics).
2199 * Returns 0 for success.
2200 */
0a10c851
DV		 2201int radeon_asic_init(struct radeon_device *rdev)
2202{
2203 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 2204
2205 /* set the number of crtcs */
2206 if (rdev->flags & RADEON_SINGLE_CRTC)
2207 rdev->num_crtc = 1;
2208 else
2209 rdev->num_crtc = 2;
2210
948bee3f
AD		 2211 rdev->has_uvd = false;
2212
0a10c851
DV		 2213 switch (rdev->family) {
2214 case CHIP_R100:
2215 case CHIP_RV100:
2216 case CHIP_RS100:
2217 case CHIP_RV200:
2218 case CHIP_RS200:
2219 rdev->asic = &r100_asic;
2220 break;
2221 case CHIP_R200:
2222 case CHIP_RV250:
2223 case CHIP_RS300:
2224 case CHIP_RV280:
2225 rdev->asic = &r200_asic;
2226 break;
2227 case CHIP_R300:
2228 case CHIP_R350:
2229 case CHIP_RV350:
2230 case CHIP_RV380:
2231 if (rdev->flags & RADEON_IS_PCIE)
2232 rdev->asic = &r300_asic_pcie;
2233 else
2234 rdev->asic = &r300_asic;
2235 break;
2236 case CHIP_R420:
2237 case CHIP_R423:
2238 case CHIP_RV410:
2239 rdev->asic = &r420_asic;
07bb084c
AD		 2240 /* handle macs */
2241 if (rdev->bios == NULL) {
798bcf73
AD		 2242 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2243 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2244 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2245 rdev->asic->pm.set_memory_clock = NULL;
37e9b6a6 2246 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
07bb084c 2247 }
0a10c851
DV		 2248 break;
2249 case CHIP_RS400:
2250 case CHIP_RS480:
2251 rdev->asic = &rs400_asic;
2252 break;
2253 case CHIP_RS600:
2254 rdev->asic = &rs600_asic;
2255 break;
2256 case CHIP_RS690:
2257 case CHIP_RS740:
2258 rdev->asic = &rs690_asic;
2259 break;
2260 case CHIP_RV515:
2261 rdev->asic = &rv515_asic;
2262 break;
2263 case CHIP_R520:
2264 case CHIP_RV530:
2265 case CHIP_RV560:
2266 case CHIP_RV570:
2267 case CHIP_R580:
2268 rdev->asic = &r520_asic;
2269 break;
2270 case CHIP_R600:
ca361b65
AD		 2271 rdev->asic = &r600_asic;
2272 break;
0a10c851
DV		 2273 case CHIP_RV610:
2274 case CHIP_RV630:
2275 case CHIP_RV620:
2276 case CHIP_RV635:
2277 case CHIP_RV670:
ca361b65
AD		 2278 rdev->asic = &rv6xx_asic;
2279 rdev->has_uvd = true;
f47299c5 2280 break;
0a10c851
DV		 2281 case CHIP_RS780:
2282 case CHIP_RS880:
f47299c5 2283 rdev->asic = &rs780_asic;
948bee3f 2284 rdev->has_uvd = true;
0a10c851
DV		 2285 break;
2286 case CHIP_RV770:
2287 case CHIP_RV730:
2288 case CHIP_RV710:
2289 case CHIP_RV740:
2290 rdev->asic = &rv770_asic;
948bee3f 2291 rdev->has_uvd = true;
0a10c851
DV		 2292 break;
2293 case CHIP_CEDAR:
2294 case CHIP_REDWOOD:
2295 case CHIP_JUNIPER:
2296 case CHIP_CYPRESS:
2297 case CHIP_HEMLOCK:
ba7e05e9
AD		 2298 /* set num crtcs */
2299 if (rdev->family == CHIP_CEDAR)
2300 rdev->num_crtc = 4;
2301 else
2302 rdev->num_crtc = 6;
0a10c851 2303 rdev->asic = &evergreen_asic;
948bee3f 2304 rdev->has_uvd = true;
0a10c851 2305 break;
958261d1 2306 case CHIP_PALM:
89da5a37
AD		 2307 case CHIP_SUMO:
2308 case CHIP_SUMO2:
958261d1 2309 rdev->asic = &sumo_asic;
948bee3f 2310 rdev->has_uvd = true;
958261d1 2311 break;
a43b7665
AD		 2312 case CHIP_BARTS:
2313 case CHIP_TURKS:
2314 case CHIP_CAICOS:
ba7e05e9
AD		 2315 /* set num crtcs */
2316 if (rdev->family == CHIP_CAICOS)
2317 rdev->num_crtc = 4;
2318 else
2319 rdev->num_crtc = 6;
a43b7665 2320 rdev->asic = &btc_asic;
948bee3f 2321 rdev->has_uvd = true;
a43b7665 2322 break;
e3487629
AD		 2323 case CHIP_CAYMAN:
2324 rdev->asic = &cayman_asic;
ba7e05e9
AD		 2325 /* set num crtcs */
2326 rdev->num_crtc = 6;
948bee3f 2327 rdev->has_uvd = true;
e3487629 2328 break;
be63fe8c
AD		 2329 case CHIP_ARUBA:
2330 rdev->asic = &trinity_asic;
2331 /* set num crtcs */
2332 rdev->num_crtc = 4;
948bee3f 2333 rdev->has_uvd = true;
be63fe8c 2334 break;
02779c08
AD		 2335 case CHIP_TAHITI:
2336 case CHIP_PITCAIRN:
2337 case CHIP_VERDE:
e737a14c 2338 case CHIP_OLAND:
86a45cac 2339 case CHIP_HAINAN:
02779c08
AD		 2340 rdev->asic = &si_asic;
2341 /* set num crtcs */
86a45cac
AD		 2342 if (rdev->family == CHIP_HAINAN)
2343 rdev->num_crtc = 0;
2344 else if (rdev->family == CHIP_OLAND)
e737a14c
AD		 2345 rdev->num_crtc = 2;
2346 else
2347 rdev->num_crtc = 6;
948bee3f
AD		 2348 if (rdev->family == CHIP_HAINAN)
2349 rdev->has_uvd = false;
2350 else
2351 rdev->has_uvd = true;
0116e1ef
AD		 2352 switch (rdev->family) {
2353 case CHIP_TAHITI:
2354 rdev->cg_flags =
090f4b6a 2355 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2356 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2357 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2358 RADEON_CG_SUPPORT_GFX_CGLS |
2359 RADEON_CG_SUPPORT_GFX_CGTS |
2360 RADEON_CG_SUPPORT_GFX_CP_LS |
2361 RADEON_CG_SUPPORT_MC_MGCG |
2362 RADEON_CG_SUPPORT_SDMA_MGCG |
2363 RADEON_CG_SUPPORT_BIF_LS |
2364 RADEON_CG_SUPPORT_VCE_MGCG |
2365 RADEON_CG_SUPPORT_UVD_MGCG |
2366 RADEON_CG_SUPPORT_HDP_LS |
2367 RADEON_CG_SUPPORT_HDP_MGCG;
2368 rdev->pg_flags = 0;
2369 break;
2370 case CHIP_PITCAIRN:
2371 rdev->cg_flags =
090f4b6a 2372 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2373 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2374 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2375 RADEON_CG_SUPPORT_GFX_CGLS |
2376 RADEON_CG_SUPPORT_GFX_CGTS |
2377 RADEON_CG_SUPPORT_GFX_CP_LS |
2378 RADEON_CG_SUPPORT_GFX_RLC_LS |
2379 RADEON_CG_SUPPORT_MC_LS |
2380 RADEON_CG_SUPPORT_MC_MGCG |
2381 RADEON_CG_SUPPORT_SDMA_MGCG |
2382 RADEON_CG_SUPPORT_BIF_LS |
2383 RADEON_CG_SUPPORT_VCE_MGCG |
2384 RADEON_CG_SUPPORT_UVD_MGCG |
2385 RADEON_CG_SUPPORT_HDP_LS |
2386 RADEON_CG_SUPPORT_HDP_MGCG;
2387 rdev->pg_flags = 0;
2388 break;
2389 case CHIP_VERDE:
2390 rdev->cg_flags =
090f4b6a 2391 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2392 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2393 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2394 RADEON_CG_SUPPORT_GFX_CGLS |
2395 RADEON_CG_SUPPORT_GFX_CGTS |
2396 RADEON_CG_SUPPORT_GFX_CP_LS |
2397 RADEON_CG_SUPPORT_GFX_RLC_LS |
2398 RADEON_CG_SUPPORT_MC_LS |
2399 RADEON_CG_SUPPORT_MC_MGCG |
2400 RADEON_CG_SUPPORT_SDMA_MGCG |
2401 RADEON_CG_SUPPORT_BIF_LS |
2402 RADEON_CG_SUPPORT_VCE_MGCG |
2403 RADEON_CG_SUPPORT_UVD_MGCG |
2404 RADEON_CG_SUPPORT_HDP_LS |
2405 RADEON_CG_SUPPORT_HDP_MGCG;
ca6ebb39 2406 rdev->pg_flags = 0 |
2b19d17f 2407 /*RADEON_PG_SUPPORT_GFX_PG | */
ca6ebb39 2408 RADEON_PG_SUPPORT_SDMA;
0116e1ef
AD		 2409 break;
2410 case CHIP_OLAND:
2411 rdev->cg_flags =
090f4b6a 2412 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2413 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2414 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2415 RADEON_CG_SUPPORT_GFX_CGLS |
2416 RADEON_CG_SUPPORT_GFX_CGTS |
2417 RADEON_CG_SUPPORT_GFX_CP_LS |
2418 RADEON_CG_SUPPORT_GFX_RLC_LS |
2419 RADEON_CG_SUPPORT_MC_LS |
2420 RADEON_CG_SUPPORT_MC_MGCG |
2421 RADEON_CG_SUPPORT_SDMA_MGCG |
2422 RADEON_CG_SUPPORT_BIF_LS |
2423 RADEON_CG_SUPPORT_UVD_MGCG |
2424 RADEON_CG_SUPPORT_HDP_LS |
2425 RADEON_CG_SUPPORT_HDP_MGCG;
2426 rdev->pg_flags = 0;
2427 break;
2428 case CHIP_HAINAN:
2429 rdev->cg_flags =
090f4b6a 2430 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2431 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2432 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2433 RADEON_CG_SUPPORT_GFX_CGLS |
2434 RADEON_CG_SUPPORT_GFX_CGTS |
2435 RADEON_CG_SUPPORT_GFX_CP_LS |
2436 RADEON_CG_SUPPORT_GFX_RLC_LS |
2437 RADEON_CG_SUPPORT_MC_LS |
2438 RADEON_CG_SUPPORT_MC_MGCG |
2439 RADEON_CG_SUPPORT_SDMA_MGCG |
2440 RADEON_CG_SUPPORT_BIF_LS |
2441 RADEON_CG_SUPPORT_HDP_LS |
2442 RADEON_CG_SUPPORT_HDP_MGCG;
2443 rdev->pg_flags = 0;
2444 break;
2445 default:
2446 rdev->cg_flags = 0;
2447 rdev->pg_flags = 0;
2448 break;
2449 }
02779c08 2450 break;
0672e27b 2451 case CHIP_BONAIRE:
41971b37 2452 case CHIP_HAWAII:
0672e27b
AD		 2453 rdev->asic = &ci_asic;
2454 rdev->num_crtc = 6;
22c775ce 2455 rdev->has_uvd = true;
41971b37
AD		 2456 if (rdev->family == CHIP_BONAIRE) {
2457 rdev->cg_flags =
2458 RADEON_CG_SUPPORT_GFX_MGCG |
2459 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2460 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2461 RADEON_CG_SUPPORT_GFX_CGLS |
2462 RADEON_CG_SUPPORT_GFX_CGTS |
2463 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2464 RADEON_CG_SUPPORT_GFX_CP_LS |
2465 RADEON_CG_SUPPORT_MC_LS |
2466 RADEON_CG_SUPPORT_MC_MGCG |
2467 RADEON_CG_SUPPORT_SDMA_MGCG |
2468 RADEON_CG_SUPPORT_SDMA_LS |
2469 RADEON_CG_SUPPORT_BIF_LS |
2470 RADEON_CG_SUPPORT_VCE_MGCG |
2471 RADEON_CG_SUPPORT_UVD_MGCG |
2472 RADEON_CG_SUPPORT_HDP_LS |
2473 RADEON_CG_SUPPORT_HDP_MGCG;
2474 rdev->pg_flags = 0;
2475 } else {
2476 rdev->cg_flags =
2477 RADEON_CG_SUPPORT_GFX_MGCG |
2478 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2479 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2480 RADEON_CG_SUPPORT_GFX_CGLS |
2481 RADEON_CG_SUPPORT_GFX_CGTS |
2482 RADEON_CG_SUPPORT_GFX_CP_LS |
2483 RADEON_CG_SUPPORT_MC_LS |
2484 RADEON_CG_SUPPORT_MC_MGCG |
2485 RADEON_CG_SUPPORT_SDMA_MGCG |
2486 RADEON_CG_SUPPORT_SDMA_LS |
2487 RADEON_CG_SUPPORT_BIF_LS |
2488 RADEON_CG_SUPPORT_VCE_MGCG |
2489 RADEON_CG_SUPPORT_UVD_MGCG |
2490 RADEON_CG_SUPPORT_HDP_LS |
2491 RADEON_CG_SUPPORT_HDP_MGCG;
2492 rdev->pg_flags = 0;
2493 }
0672e27b
AD		 2494 break;
2495 case CHIP_KAVERI:
2496 case CHIP_KABINI:
b0a9f22a 2497 case CHIP_MULLINS:
0672e27b
AD		 2498 rdev->asic = &kv_asic;
2499 /* set num crtcs */
473359bc 2500 if (rdev->family == CHIP_KAVERI) {
0672e27b 2501 rdev->num_crtc = 4;
473359bc 2502 rdev->cg_flags =
773dc10a 2503 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2504 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2505 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2506 RADEON_CG_SUPPORT_GFX_CGLS |
2507 RADEON_CG_SUPPORT_GFX_CGTS |
2508 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2509 RADEON_CG_SUPPORT_GFX_CP_LS |
2510 RADEON_CG_SUPPORT_SDMA_MGCG |
2511 RADEON_CG_SUPPORT_SDMA_LS |
2512 RADEON_CG_SUPPORT_BIF_LS |
2513 RADEON_CG_SUPPORT_VCE_MGCG |
2514 RADEON_CG_SUPPORT_UVD_MGCG |
2515 RADEON_CG_SUPPORT_HDP_LS |
2516 RADEON_CG_SUPPORT_HDP_MGCG;
2517 rdev->pg_flags = 0;
2b19d17f 2518 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2519 RADEON_PG_SUPPORT_GFX_SMG |
2520 RADEON_PG_SUPPORT_GFX_DMG |
2521 RADEON_PG_SUPPORT_UVD |
2522 RADEON_PG_SUPPORT_VCE |
2523 RADEON_PG_SUPPORT_CP |
2524 RADEON_PG_SUPPORT_GDS |
2525 RADEON_PG_SUPPORT_RLC_SMU_HS |
2526 RADEON_PG_SUPPORT_ACP |
2527 RADEON_PG_SUPPORT_SAMU;*/
2528 } else {
0672e27b 2529 rdev->num_crtc = 2;
473359bc 2530 rdev->cg_flags =
773dc10a 2531 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2532 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2533 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2534 RADEON_CG_SUPPORT_GFX_CGLS |
2535 RADEON_CG_SUPPORT_GFX_CGTS |
2536 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2537 RADEON_CG_SUPPORT_GFX_CP_LS |
2538 RADEON_CG_SUPPORT_SDMA_MGCG |
2539 RADEON_CG_SUPPORT_SDMA_LS |
2540 RADEON_CG_SUPPORT_BIF_LS |
2541 RADEON_CG_SUPPORT_VCE_MGCG |
2542 RADEON_CG_SUPPORT_UVD_MGCG |
2543 RADEON_CG_SUPPORT_HDP_LS |
2544 RADEON_CG_SUPPORT_HDP_MGCG;
2545 rdev->pg_flags = 0;
2b19d17f 2546 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2547 RADEON_PG_SUPPORT_GFX_SMG |
2548 RADEON_PG_SUPPORT_UVD |
2549 RADEON_PG_SUPPORT_VCE |
2550 RADEON_PG_SUPPORT_CP |
2551 RADEON_PG_SUPPORT_GDS |
2552 RADEON_PG_SUPPORT_RLC_SMU_HS |
2553 RADEON_PG_SUPPORT_SAMU;*/
2554 }
22c775ce 2555 rdev->has_uvd = true;
0672e27b 2556 break;
0a10c851
DV		 2557 default:
2558 /* FIXME: not supported yet */
2559 return -EINVAL;
2560 }
2561
2562 if (rdev->flags & RADEON_IS_IGP) {
798bcf73
AD		 2563 rdev->asic->pm.get_memory_clock = NULL;
2564 rdev->asic->pm.set_memory_clock = NULL;
0a10c851
DV		 2565 }
2566
2567 return 0;
2568}
2569
Linux 6.x block layer and io_uring tree(s)