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0a10c851 DV |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | ||
29 | #include <linux/console.h> | |
30 | #include <drm/drmP.h> | |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
33 | #include <linux/vgaarb.h> | |
34 | #include <linux/vga_switcheroo.h> | |
35 | #include "radeon_reg.h" | |
36 | #include "radeon.h" | |
37 | #include "radeon_asic.h" | |
38 | #include "atom.h" | |
39 | ||
40 | /* | |
41 | * Registers accessors functions. | |
42 | */ | |
abf1dc67 AD |
43 | /** |
44 | * radeon_invalid_rreg - dummy reg read function | |
45 | * | |
46 | * @rdev: radeon device pointer | |
47 | * @reg: offset of register | |
48 | * | |
49 | * Dummy register read function. Used for register blocks | |
50 | * that certain asics don't have (all asics). | |
51 | * Returns the value in the register. | |
52 | */ | |
0a10c851 DV |
53 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
54 | { | |
55 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
56 | BUG_ON(1); | |
57 | return 0; | |
58 | } | |
59 | ||
abf1dc67 AD |
60 | /** |
61 | * radeon_invalid_wreg - dummy reg write function | |
62 | * | |
63 | * @rdev: radeon device pointer | |
64 | * @reg: offset of register | |
65 | * @v: value to write to the register | |
66 | * | |
67 | * Dummy register read function. Used for register blocks | |
68 | * that certain asics don't have (all asics). | |
69 | */ | |
0a10c851 DV |
70 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
71 | { | |
72 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
73 | reg, v); | |
74 | BUG_ON(1); | |
75 | } | |
76 | ||
abf1dc67 AD |
77 | /** |
78 | * radeon_register_accessor_init - sets up the register accessor callbacks | |
79 | * | |
80 | * @rdev: radeon device pointer | |
81 | * | |
82 | * Sets up the register accessor callbacks for various register | |
83 | * apertures. Not all asics have all apertures (all asics). | |
84 | */ | |
0a10c851 DV |
85 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
86 | { | |
87 | rdev->mc_rreg = &radeon_invalid_rreg; | |
88 | rdev->mc_wreg = &radeon_invalid_wreg; | |
89 | rdev->pll_rreg = &radeon_invalid_rreg; | |
90 | rdev->pll_wreg = &radeon_invalid_wreg; | |
91 | rdev->pciep_rreg = &radeon_invalid_rreg; | |
92 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
93 | ||
94 | /* Don't change order as we are overridding accessor. */ | |
95 | if (rdev->family < CHIP_RV515) { | |
96 | rdev->pcie_reg_mask = 0xff; | |
97 | } else { | |
98 | rdev->pcie_reg_mask = 0x7ff; | |
99 | } | |
100 | /* FIXME: not sure here */ | |
101 | if (rdev->family <= CHIP_R580) { | |
102 | rdev->pll_rreg = &r100_pll_rreg; | |
103 | rdev->pll_wreg = &r100_pll_wreg; | |
104 | } | |
105 | if (rdev->family >= CHIP_R420) { | |
106 | rdev->mc_rreg = &r420_mc_rreg; | |
107 | rdev->mc_wreg = &r420_mc_wreg; | |
108 | } | |
109 | if (rdev->family >= CHIP_RV515) { | |
110 | rdev->mc_rreg = &rv515_mc_rreg; | |
111 | rdev->mc_wreg = &rv515_mc_wreg; | |
112 | } | |
113 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
114 | rdev->mc_rreg = &rs400_mc_rreg; | |
115 | rdev->mc_wreg = &rs400_mc_wreg; | |
116 | } | |
117 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
118 | rdev->mc_rreg = &rs690_mc_rreg; | |
119 | rdev->mc_wreg = &rs690_mc_wreg; | |
120 | } | |
121 | if (rdev->family == CHIP_RS600) { | |
122 | rdev->mc_rreg = &rs600_mc_rreg; | |
123 | rdev->mc_wreg = &rs600_mc_wreg; | |
124 | } | |
65337e60 SL |
125 | if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { |
126 | rdev->mc_rreg = &rs780_mc_rreg; | |
127 | rdev->mc_wreg = &rs780_mc_wreg; | |
128 | } | |
6e2c3c0a AD |
129 | |
130 | if (rdev->family >= CHIP_BONAIRE) { | |
131 | rdev->pciep_rreg = &cik_pciep_rreg; | |
132 | rdev->pciep_wreg = &cik_pciep_wreg; | |
133 | } else if (rdev->family >= CHIP_R600) { | |
0a10c851 DV |
134 | rdev->pciep_rreg = &r600_pciep_rreg; |
135 | rdev->pciep_wreg = &r600_pciep_wreg; | |
136 | } | |
137 | } | |
138 | ||
139 | ||
140 | /* helper to disable agp */ | |
abf1dc67 AD |
141 | /** |
142 | * radeon_agp_disable - AGP disable helper function | |
143 | * | |
144 | * @rdev: radeon device pointer | |
145 | * | |
146 | * Removes AGP flags and changes the gart callbacks on AGP | |
147 | * cards when using the internal gart rather than AGP (all asics). | |
148 | */ | |
0a10c851 DV |
149 | void radeon_agp_disable(struct radeon_device *rdev) |
150 | { | |
151 | rdev->flags &= ~RADEON_IS_AGP; | |
152 | if (rdev->family >= CHIP_R600) { | |
153 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
154 | rdev->flags |= RADEON_IS_PCIE; | |
155 | } else if (rdev->family >= CHIP_RV515 || | |
156 | rdev->family == CHIP_RV380 || | |
157 | rdev->family == CHIP_RV410 || | |
158 | rdev->family == CHIP_R423) { | |
159 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
160 | rdev->flags |= RADEON_IS_PCIE; | |
c5b3b850 | 161 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
cb658906 | 162 | rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; |
c5b3b850 | 163 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; |
0a10c851 DV |
164 | } else { |
165 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
166 | rdev->flags |= RADEON_IS_PCI; | |
c5b3b850 | 167 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
cb658906 | 168 | rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; |
c5b3b850 | 169 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; |
0a10c851 DV |
170 | } |
171 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
172 | } | |
173 | ||
174 | /* | |
175 | * ASIC | |
176 | */ | |
76a0df85 CK |
177 | |
178 | static struct radeon_asic_ring r100_gfx_ring = { | |
179 | .ib_execute = &r100_ring_ib_execute, | |
180 | .emit_fence = &r100_fence_ring_emit, | |
181 | .emit_semaphore = &r100_semaphore_ring_emit, | |
182 | .cs_parse = &r100_cs_parse, | |
183 | .ring_start = &r100_ring_start, | |
184 | .ring_test = &r100_ring_test, | |
185 | .ib_test = &r100_ib_test, | |
186 | .is_lockup = &r100_gpu_is_lockup, | |
ea31bf69 AD |
187 | .get_rptr = &r100_gfx_get_rptr, |
188 | .get_wptr = &r100_gfx_get_wptr, | |
189 | .set_wptr = &r100_gfx_set_wptr, | |
76a0df85 CK |
190 | }; |
191 | ||
48e7a5f1 DV |
192 | static struct radeon_asic r100_asic = { |
193 | .init = &r100_init, | |
194 | .fini = &r100_fini, | |
195 | .suspend = &r100_suspend, | |
196 | .resume = &r100_resume, | |
197 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 198 | .asic_reset = &r100_asic_reset, |
124764f1 | 199 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
200 | .gui_idle = &r100_gui_idle, |
201 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
202 | .gart = { |
203 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
cb658906 | 204 | .get_page_entry = &r100_pci_gart_get_page_entry, |
c5b3b850 AD |
205 | .set_page = &r100_pci_gart_set_page, |
206 | }, | |
4c87bc26 | 207 | .ring = { |
76a0df85 | 208 | [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring |
4c87bc26 | 209 | }, |
b35ea4ab AD |
210 | .irq = { |
211 | .set = &r100_irq_set, | |
212 | .process = &r100_irq_process, | |
213 | }, | |
c79a49ca AD |
214 | .display = { |
215 | .bandwidth_update = &r100_bandwidth_update, | |
216 | .get_vblank_counter = &r100_get_vblank_counter, | |
217 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 218 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 219 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 220 | }, |
27cd7769 AD |
221 | .copy = { |
222 | .blit = &r100_copy_blit, | |
223 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
224 | .dma = NULL, | |
225 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
226 | .copy = &r100_copy_blit, | |
227 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
228 | }, | |
9e6f3d02 AD |
229 | .surface = { |
230 | .set_reg = r100_set_surface_reg, | |
231 | .clear_reg = r100_clear_surface_reg, | |
232 | }, | |
901ea57d AD |
233 | .hpd = { |
234 | .init = &r100_hpd_init, | |
235 | .fini = &r100_hpd_fini, | |
236 | .sense = &r100_hpd_sense, | |
237 | .set_polarity = &r100_hpd_set_polarity, | |
238 | }, | |
a02fa397 AD |
239 | .pm = { |
240 | .misc = &r100_pm_misc, | |
241 | .prepare = &r100_pm_prepare, | |
242 | .finish = &r100_pm_finish, | |
243 | .init_profile = &r100_pm_init_profile, | |
244 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
245 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
246 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
247 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
248 | .set_memory_clock = NULL, | |
249 | .get_pcie_lanes = NULL, | |
250 | .set_pcie_lanes = NULL, | |
251 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 252 | }, |
0f9e006c | 253 | .pflip = { |
0f9e006c | 254 | .page_flip = &r100_page_flip, |
157fa14d | 255 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 256 | }, |
48e7a5f1 DV |
257 | }; |
258 | ||
259 | static struct radeon_asic r200_asic = { | |
260 | .init = &r100_init, | |
261 | .fini = &r100_fini, | |
262 | .suspend = &r100_suspend, | |
263 | .resume = &r100_resume, | |
264 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 265 | .asic_reset = &r100_asic_reset, |
124764f1 | 266 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
267 | .gui_idle = &r100_gui_idle, |
268 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
269 | .gart = { |
270 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
cb658906 | 271 | .get_page_entry = &r100_pci_gart_get_page_entry, |
c5b3b850 AD |
272 | .set_page = &r100_pci_gart_set_page, |
273 | }, | |
4c87bc26 | 274 | .ring = { |
76a0df85 | 275 | [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring |
4c87bc26 | 276 | }, |
b35ea4ab AD |
277 | .irq = { |
278 | .set = &r100_irq_set, | |
279 | .process = &r100_irq_process, | |
280 | }, | |
c79a49ca AD |
281 | .display = { |
282 | .bandwidth_update = &r100_bandwidth_update, | |
283 | .get_vblank_counter = &r100_get_vblank_counter, | |
284 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 285 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 286 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 287 | }, |
27cd7769 AD |
288 | .copy = { |
289 | .blit = &r100_copy_blit, | |
290 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
291 | .dma = &r200_copy_dma, | |
292 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
293 | .copy = &r100_copy_blit, | |
294 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
295 | }, | |
9e6f3d02 AD |
296 | .surface = { |
297 | .set_reg = r100_set_surface_reg, | |
298 | .clear_reg = r100_clear_surface_reg, | |
299 | }, | |
901ea57d AD |
300 | .hpd = { |
301 | .init = &r100_hpd_init, | |
302 | .fini = &r100_hpd_fini, | |
303 | .sense = &r100_hpd_sense, | |
304 | .set_polarity = &r100_hpd_set_polarity, | |
305 | }, | |
a02fa397 AD |
306 | .pm = { |
307 | .misc = &r100_pm_misc, | |
308 | .prepare = &r100_pm_prepare, | |
309 | .finish = &r100_pm_finish, | |
310 | .init_profile = &r100_pm_init_profile, | |
311 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
312 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
313 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
314 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
315 | .set_memory_clock = NULL, | |
316 | .get_pcie_lanes = NULL, | |
317 | .set_pcie_lanes = NULL, | |
318 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 319 | }, |
0f9e006c | 320 | .pflip = { |
0f9e006c | 321 | .page_flip = &r100_page_flip, |
157fa14d | 322 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 323 | }, |
48e7a5f1 DV |
324 | }; |
325 | ||
76a0df85 CK |
326 | static struct radeon_asic_ring r300_gfx_ring = { |
327 | .ib_execute = &r100_ring_ib_execute, | |
328 | .emit_fence = &r300_fence_ring_emit, | |
329 | .emit_semaphore = &r100_semaphore_ring_emit, | |
330 | .cs_parse = &r300_cs_parse, | |
331 | .ring_start = &r300_ring_start, | |
332 | .ring_test = &r100_ring_test, | |
333 | .ib_test = &r100_ib_test, | |
334 | .is_lockup = &r100_gpu_is_lockup, | |
ea31bf69 AD |
335 | .get_rptr = &r100_gfx_get_rptr, |
336 | .get_wptr = &r100_gfx_get_wptr, | |
337 | .set_wptr = &r100_gfx_set_wptr, | |
76a0df85 CK |
338 | }; |
339 | ||
d8a74e18 AD |
340 | static struct radeon_asic_ring rv515_gfx_ring = { |
341 | .ib_execute = &r100_ring_ib_execute, | |
342 | .emit_fence = &r300_fence_ring_emit, | |
343 | .emit_semaphore = &r100_semaphore_ring_emit, | |
344 | .cs_parse = &r300_cs_parse, | |
345 | .ring_start = &rv515_ring_start, | |
346 | .ring_test = &r100_ring_test, | |
347 | .ib_test = &r100_ib_test, | |
348 | .is_lockup = &r100_gpu_is_lockup, | |
349 | .get_rptr = &r100_gfx_get_rptr, | |
350 | .get_wptr = &r100_gfx_get_wptr, | |
351 | .set_wptr = &r100_gfx_set_wptr, | |
352 | }; | |
353 | ||
48e7a5f1 DV |
354 | static struct radeon_asic r300_asic = { |
355 | .init = &r300_init, | |
356 | .fini = &r300_fini, | |
357 | .suspend = &r300_suspend, | |
358 | .resume = &r300_resume, | |
359 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 360 | .asic_reset = &r300_asic_reset, |
124764f1 | 361 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
362 | .gui_idle = &r100_gui_idle, |
363 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
364 | .gart = { |
365 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
cb658906 | 366 | .get_page_entry = &r100_pci_gart_get_page_entry, |
c5b3b850 AD |
367 | .set_page = &r100_pci_gart_set_page, |
368 | }, | |
4c87bc26 | 369 | .ring = { |
76a0df85 | 370 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 371 | }, |
b35ea4ab AD |
372 | .irq = { |
373 | .set = &r100_irq_set, | |
374 | .process = &r100_irq_process, | |
375 | }, | |
c79a49ca AD |
376 | .display = { |
377 | .bandwidth_update = &r100_bandwidth_update, | |
378 | .get_vblank_counter = &r100_get_vblank_counter, | |
379 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 380 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 381 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 382 | }, |
27cd7769 AD |
383 | .copy = { |
384 | .blit = &r100_copy_blit, | |
385 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
386 | .dma = &r200_copy_dma, | |
387 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
388 | .copy = &r100_copy_blit, | |
389 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
390 | }, | |
9e6f3d02 AD |
391 | .surface = { |
392 | .set_reg = r100_set_surface_reg, | |
393 | .clear_reg = r100_clear_surface_reg, | |
394 | }, | |
901ea57d AD |
395 | .hpd = { |
396 | .init = &r100_hpd_init, | |
397 | .fini = &r100_hpd_fini, | |
398 | .sense = &r100_hpd_sense, | |
399 | .set_polarity = &r100_hpd_set_polarity, | |
400 | }, | |
a02fa397 AD |
401 | .pm = { |
402 | .misc = &r100_pm_misc, | |
403 | .prepare = &r100_pm_prepare, | |
404 | .finish = &r100_pm_finish, | |
405 | .init_profile = &r100_pm_init_profile, | |
406 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
407 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
408 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
409 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
410 | .set_memory_clock = NULL, | |
411 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
412 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
413 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 414 | }, |
0f9e006c | 415 | .pflip = { |
0f9e006c | 416 | .page_flip = &r100_page_flip, |
157fa14d | 417 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 418 | }, |
48e7a5f1 DV |
419 | }; |
420 | ||
421 | static struct radeon_asic r300_asic_pcie = { | |
422 | .init = &r300_init, | |
423 | .fini = &r300_fini, | |
424 | .suspend = &r300_suspend, | |
425 | .resume = &r300_resume, | |
426 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 427 | .asic_reset = &r300_asic_reset, |
124764f1 | 428 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
429 | .gui_idle = &r100_gui_idle, |
430 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
431 | .gart = { |
432 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
cb658906 | 433 | .get_page_entry = &rv370_pcie_gart_get_page_entry, |
c5b3b850 AD |
434 | .set_page = &rv370_pcie_gart_set_page, |
435 | }, | |
4c87bc26 | 436 | .ring = { |
76a0df85 | 437 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 438 | }, |
b35ea4ab AD |
439 | .irq = { |
440 | .set = &r100_irq_set, | |
441 | .process = &r100_irq_process, | |
442 | }, | |
c79a49ca AD |
443 | .display = { |
444 | .bandwidth_update = &r100_bandwidth_update, | |
445 | .get_vblank_counter = &r100_get_vblank_counter, | |
446 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 447 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 448 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 449 | }, |
27cd7769 AD |
450 | .copy = { |
451 | .blit = &r100_copy_blit, | |
452 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
453 | .dma = &r200_copy_dma, | |
454 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
455 | .copy = &r100_copy_blit, | |
456 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
457 | }, | |
9e6f3d02 AD |
458 | .surface = { |
459 | .set_reg = r100_set_surface_reg, | |
460 | .clear_reg = r100_clear_surface_reg, | |
461 | }, | |
901ea57d AD |
462 | .hpd = { |
463 | .init = &r100_hpd_init, | |
464 | .fini = &r100_hpd_fini, | |
465 | .sense = &r100_hpd_sense, | |
466 | .set_polarity = &r100_hpd_set_polarity, | |
467 | }, | |
a02fa397 AD |
468 | .pm = { |
469 | .misc = &r100_pm_misc, | |
470 | .prepare = &r100_pm_prepare, | |
471 | .finish = &r100_pm_finish, | |
472 | .init_profile = &r100_pm_init_profile, | |
473 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
474 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
475 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
476 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
477 | .set_memory_clock = NULL, | |
478 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
479 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
480 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 481 | }, |
0f9e006c | 482 | .pflip = { |
0f9e006c | 483 | .page_flip = &r100_page_flip, |
157fa14d | 484 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 485 | }, |
48e7a5f1 DV |
486 | }; |
487 | ||
488 | static struct radeon_asic r420_asic = { | |
489 | .init = &r420_init, | |
490 | .fini = &r420_fini, | |
491 | .suspend = &r420_suspend, | |
492 | .resume = &r420_resume, | |
493 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 494 | .asic_reset = &r300_asic_reset, |
124764f1 | 495 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
496 | .gui_idle = &r100_gui_idle, |
497 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
498 | .gart = { |
499 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
cb658906 | 500 | .get_page_entry = &rv370_pcie_gart_get_page_entry, |
c5b3b850 AD |
501 | .set_page = &rv370_pcie_gart_set_page, |
502 | }, | |
4c87bc26 | 503 | .ring = { |
76a0df85 | 504 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 505 | }, |
b35ea4ab AD |
506 | .irq = { |
507 | .set = &r100_irq_set, | |
508 | .process = &r100_irq_process, | |
509 | }, | |
c79a49ca AD |
510 | .display = { |
511 | .bandwidth_update = &r100_bandwidth_update, | |
512 | .get_vblank_counter = &r100_get_vblank_counter, | |
513 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 514 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 515 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 516 | }, |
27cd7769 AD |
517 | .copy = { |
518 | .blit = &r100_copy_blit, | |
519 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
520 | .dma = &r200_copy_dma, | |
521 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
522 | .copy = &r100_copy_blit, | |
523 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
524 | }, | |
9e6f3d02 AD |
525 | .surface = { |
526 | .set_reg = r100_set_surface_reg, | |
527 | .clear_reg = r100_clear_surface_reg, | |
528 | }, | |
901ea57d AD |
529 | .hpd = { |
530 | .init = &r100_hpd_init, | |
531 | .fini = &r100_hpd_fini, | |
532 | .sense = &r100_hpd_sense, | |
533 | .set_polarity = &r100_hpd_set_polarity, | |
534 | }, | |
a02fa397 AD |
535 | .pm = { |
536 | .misc = &r100_pm_misc, | |
537 | .prepare = &r100_pm_prepare, | |
538 | .finish = &r100_pm_finish, | |
539 | .init_profile = &r420_pm_init_profile, | |
540 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
541 | .get_engine_clock = &radeon_atom_get_engine_clock, |
542 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
543 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
544 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
545 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
546 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
547 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 548 | }, |
0f9e006c | 549 | .pflip = { |
0f9e006c | 550 | .page_flip = &r100_page_flip, |
157fa14d | 551 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 552 | }, |
48e7a5f1 DV |
553 | }; |
554 | ||
555 | static struct radeon_asic rs400_asic = { | |
556 | .init = &rs400_init, | |
557 | .fini = &rs400_fini, | |
558 | .suspend = &rs400_suspend, | |
559 | .resume = &rs400_resume, | |
560 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 561 | .asic_reset = &r300_asic_reset, |
124764f1 | 562 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
563 | .gui_idle = &r100_gui_idle, |
564 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, | |
c5b3b850 AD |
565 | .gart = { |
566 | .tlb_flush = &rs400_gart_tlb_flush, | |
cb658906 | 567 | .get_page_entry = &rs400_gart_get_page_entry, |
c5b3b850 AD |
568 | .set_page = &rs400_gart_set_page, |
569 | }, | |
4c87bc26 | 570 | .ring = { |
76a0df85 | 571 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 572 | }, |
b35ea4ab AD |
573 | .irq = { |
574 | .set = &r100_irq_set, | |
575 | .process = &r100_irq_process, | |
576 | }, | |
c79a49ca AD |
577 | .display = { |
578 | .bandwidth_update = &r100_bandwidth_update, | |
579 | .get_vblank_counter = &r100_get_vblank_counter, | |
580 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 581 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 582 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 583 | }, |
27cd7769 AD |
584 | .copy = { |
585 | .blit = &r100_copy_blit, | |
586 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
587 | .dma = &r200_copy_dma, | |
588 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
589 | .copy = &r100_copy_blit, | |
590 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
591 | }, | |
9e6f3d02 AD |
592 | .surface = { |
593 | .set_reg = r100_set_surface_reg, | |
594 | .clear_reg = r100_clear_surface_reg, | |
595 | }, | |
901ea57d AD |
596 | .hpd = { |
597 | .init = &r100_hpd_init, | |
598 | .fini = &r100_hpd_fini, | |
599 | .sense = &r100_hpd_sense, | |
600 | .set_polarity = &r100_hpd_set_polarity, | |
601 | }, | |
a02fa397 AD |
602 | .pm = { |
603 | .misc = &r100_pm_misc, | |
604 | .prepare = &r100_pm_prepare, | |
605 | .finish = &r100_pm_finish, | |
606 | .init_profile = &r100_pm_init_profile, | |
607 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
608 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
609 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
610 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
611 | .set_memory_clock = NULL, | |
612 | .get_pcie_lanes = NULL, | |
613 | .set_pcie_lanes = NULL, | |
614 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 615 | }, |
0f9e006c | 616 | .pflip = { |
0f9e006c | 617 | .page_flip = &r100_page_flip, |
157fa14d | 618 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 619 | }, |
48e7a5f1 DV |
620 | }; |
621 | ||
622 | static struct radeon_asic rs600_asic = { | |
623 | .init = &rs600_init, | |
624 | .fini = &rs600_fini, | |
625 | .suspend = &rs600_suspend, | |
626 | .resume = &rs600_resume, | |
627 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 628 | .asic_reset = &rs600_asic_reset, |
124764f1 | 629 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
630 | .gui_idle = &r100_gui_idle, |
631 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, | |
c5b3b850 AD |
632 | .gart = { |
633 | .tlb_flush = &rs600_gart_tlb_flush, | |
cb658906 | 634 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
635 | .set_page = &rs600_gart_set_page, |
636 | }, | |
4c87bc26 | 637 | .ring = { |
76a0df85 | 638 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 639 | }, |
b35ea4ab AD |
640 | .irq = { |
641 | .set = &rs600_irq_set, | |
642 | .process = &rs600_irq_process, | |
643 | }, | |
c79a49ca AD |
644 | .display = { |
645 | .bandwidth_update = &rs600_bandwidth_update, | |
646 | .get_vblank_counter = &rs600_get_vblank_counter, | |
647 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 648 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 649 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 650 | }, |
27cd7769 AD |
651 | .copy = { |
652 | .blit = &r100_copy_blit, | |
653 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
654 | .dma = &r200_copy_dma, | |
655 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
656 | .copy = &r100_copy_blit, | |
657 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
658 | }, | |
9e6f3d02 AD |
659 | .surface = { |
660 | .set_reg = r100_set_surface_reg, | |
661 | .clear_reg = r100_clear_surface_reg, | |
662 | }, | |
901ea57d AD |
663 | .hpd = { |
664 | .init = &rs600_hpd_init, | |
665 | .fini = &rs600_hpd_fini, | |
666 | .sense = &rs600_hpd_sense, | |
667 | .set_polarity = &rs600_hpd_set_polarity, | |
668 | }, | |
a02fa397 AD |
669 | .pm = { |
670 | .misc = &rs600_pm_misc, | |
671 | .prepare = &rs600_pm_prepare, | |
672 | .finish = &rs600_pm_finish, | |
673 | .init_profile = &r420_pm_init_profile, | |
674 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
675 | .get_engine_clock = &radeon_atom_get_engine_clock, |
676 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
677 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
678 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
679 | .get_pcie_lanes = NULL, | |
680 | .set_pcie_lanes = NULL, | |
681 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 682 | }, |
0f9e006c | 683 | .pflip = { |
0f9e006c | 684 | .page_flip = &rs600_page_flip, |
157fa14d | 685 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 686 | }, |
48e7a5f1 DV |
687 | }; |
688 | ||
689 | static struct radeon_asic rs690_asic = { | |
690 | .init = &rs690_init, | |
691 | .fini = &rs690_fini, | |
692 | .suspend = &rs690_suspend, | |
693 | .resume = &rs690_resume, | |
694 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 695 | .asic_reset = &rs600_asic_reset, |
124764f1 | 696 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
697 | .gui_idle = &r100_gui_idle, |
698 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, | |
c5b3b850 AD |
699 | .gart = { |
700 | .tlb_flush = &rs400_gart_tlb_flush, | |
cb658906 | 701 | .get_page_entry = &rs400_gart_get_page_entry, |
c5b3b850 AD |
702 | .set_page = &rs400_gart_set_page, |
703 | }, | |
4c87bc26 | 704 | .ring = { |
76a0df85 | 705 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 706 | }, |
b35ea4ab AD |
707 | .irq = { |
708 | .set = &rs600_irq_set, | |
709 | .process = &rs600_irq_process, | |
710 | }, | |
c79a49ca AD |
711 | .display = { |
712 | .get_vblank_counter = &rs600_get_vblank_counter, | |
713 | .bandwidth_update = &rs690_bandwidth_update, | |
714 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 715 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 716 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 717 | }, |
27cd7769 AD |
718 | .copy = { |
719 | .blit = &r100_copy_blit, | |
720 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
721 | .dma = &r200_copy_dma, | |
722 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
723 | .copy = &r200_copy_dma, | |
724 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
725 | }, | |
9e6f3d02 AD |
726 | .surface = { |
727 | .set_reg = r100_set_surface_reg, | |
728 | .clear_reg = r100_clear_surface_reg, | |
729 | }, | |
901ea57d AD |
730 | .hpd = { |
731 | .init = &rs600_hpd_init, | |
732 | .fini = &rs600_hpd_fini, | |
733 | .sense = &rs600_hpd_sense, | |
734 | .set_polarity = &rs600_hpd_set_polarity, | |
735 | }, | |
a02fa397 AD |
736 | .pm = { |
737 | .misc = &rs600_pm_misc, | |
738 | .prepare = &rs600_pm_prepare, | |
739 | .finish = &rs600_pm_finish, | |
740 | .init_profile = &r420_pm_init_profile, | |
741 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
742 | .get_engine_clock = &radeon_atom_get_engine_clock, |
743 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
744 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
745 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
746 | .get_pcie_lanes = NULL, | |
747 | .set_pcie_lanes = NULL, | |
748 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 749 | }, |
0f9e006c | 750 | .pflip = { |
0f9e006c | 751 | .page_flip = &rs600_page_flip, |
157fa14d | 752 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 753 | }, |
48e7a5f1 DV |
754 | }; |
755 | ||
756 | static struct radeon_asic rv515_asic = { | |
757 | .init = &rv515_init, | |
758 | .fini = &rv515_fini, | |
759 | .suspend = &rv515_suspend, | |
760 | .resume = &rv515_resume, | |
761 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 762 | .asic_reset = &rs600_asic_reset, |
124764f1 | 763 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
764 | .gui_idle = &r100_gui_idle, |
765 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, | |
c5b3b850 AD |
766 | .gart = { |
767 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
cb658906 | 768 | .get_page_entry = &rv370_pcie_gart_get_page_entry, |
c5b3b850 AD |
769 | .set_page = &rv370_pcie_gart_set_page, |
770 | }, | |
4c87bc26 | 771 | .ring = { |
d8a74e18 | 772 | [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring |
4c87bc26 | 773 | }, |
b35ea4ab AD |
774 | .irq = { |
775 | .set = &rs600_irq_set, | |
776 | .process = &rs600_irq_process, | |
777 | }, | |
c79a49ca AD |
778 | .display = { |
779 | .get_vblank_counter = &rs600_get_vblank_counter, | |
780 | .bandwidth_update = &rv515_bandwidth_update, | |
781 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 782 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 783 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 784 | }, |
27cd7769 AD |
785 | .copy = { |
786 | .blit = &r100_copy_blit, | |
787 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
788 | .dma = &r200_copy_dma, | |
789 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
790 | .copy = &r100_copy_blit, | |
791 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
792 | }, | |
9e6f3d02 AD |
793 | .surface = { |
794 | .set_reg = r100_set_surface_reg, | |
795 | .clear_reg = r100_clear_surface_reg, | |
796 | }, | |
901ea57d AD |
797 | .hpd = { |
798 | .init = &rs600_hpd_init, | |
799 | .fini = &rs600_hpd_fini, | |
800 | .sense = &rs600_hpd_sense, | |
801 | .set_polarity = &rs600_hpd_set_polarity, | |
802 | }, | |
a02fa397 AD |
803 | .pm = { |
804 | .misc = &rs600_pm_misc, | |
805 | .prepare = &rs600_pm_prepare, | |
806 | .finish = &rs600_pm_finish, | |
807 | .init_profile = &r420_pm_init_profile, | |
808 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
809 | .get_engine_clock = &radeon_atom_get_engine_clock, |
810 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
811 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
812 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
813 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
814 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
815 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 816 | }, |
0f9e006c | 817 | .pflip = { |
0f9e006c | 818 | .page_flip = &rs600_page_flip, |
157fa14d | 819 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 820 | }, |
48e7a5f1 DV |
821 | }; |
822 | ||
823 | static struct radeon_asic r520_asic = { | |
824 | .init = &r520_init, | |
825 | .fini = &rv515_fini, | |
826 | .suspend = &rv515_suspend, | |
827 | .resume = &r520_resume, | |
828 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 829 | .asic_reset = &rs600_asic_reset, |
124764f1 | 830 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
831 | .gui_idle = &r100_gui_idle, |
832 | .mc_wait_for_idle = &r520_mc_wait_for_idle, | |
c5b3b850 AD |
833 | .gart = { |
834 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
cb658906 | 835 | .get_page_entry = &rv370_pcie_gart_get_page_entry, |
c5b3b850 AD |
836 | .set_page = &rv370_pcie_gart_set_page, |
837 | }, | |
4c87bc26 | 838 | .ring = { |
d8a74e18 | 839 | [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring |
4c87bc26 | 840 | }, |
b35ea4ab AD |
841 | .irq = { |
842 | .set = &rs600_irq_set, | |
843 | .process = &rs600_irq_process, | |
844 | }, | |
c79a49ca AD |
845 | .display = { |
846 | .bandwidth_update = &rv515_bandwidth_update, | |
847 | .get_vblank_counter = &rs600_get_vblank_counter, | |
848 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 849 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 850 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 851 | }, |
27cd7769 AD |
852 | .copy = { |
853 | .blit = &r100_copy_blit, | |
854 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
855 | .dma = &r200_copy_dma, | |
856 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
857 | .copy = &r100_copy_blit, | |
858 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
859 | }, | |
9e6f3d02 AD |
860 | .surface = { |
861 | .set_reg = r100_set_surface_reg, | |
862 | .clear_reg = r100_clear_surface_reg, | |
863 | }, | |
901ea57d AD |
864 | .hpd = { |
865 | .init = &rs600_hpd_init, | |
866 | .fini = &rs600_hpd_fini, | |
867 | .sense = &rs600_hpd_sense, | |
868 | .set_polarity = &rs600_hpd_set_polarity, | |
869 | }, | |
a02fa397 AD |
870 | .pm = { |
871 | .misc = &rs600_pm_misc, | |
872 | .prepare = &rs600_pm_prepare, | |
873 | .finish = &rs600_pm_finish, | |
874 | .init_profile = &r420_pm_init_profile, | |
875 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
876 | .get_engine_clock = &radeon_atom_get_engine_clock, |
877 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
878 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
879 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
880 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
881 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
882 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 883 | }, |
0f9e006c | 884 | .pflip = { |
0f9e006c | 885 | .page_flip = &rs600_page_flip, |
157fa14d | 886 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 887 | }, |
48e7a5f1 DV |
888 | }; |
889 | ||
76a0df85 CK |
890 | static struct radeon_asic_ring r600_gfx_ring = { |
891 | .ib_execute = &r600_ring_ib_execute, | |
892 | .emit_fence = &r600_fence_ring_emit, | |
893 | .emit_semaphore = &r600_semaphore_ring_emit, | |
894 | .cs_parse = &r600_cs_parse, | |
895 | .ring_test = &r600_ring_test, | |
896 | .ib_test = &r600_ib_test, | |
897 | .is_lockup = &r600_gfx_is_lockup, | |
ea31bf69 AD |
898 | .get_rptr = &r600_gfx_get_rptr, |
899 | .get_wptr = &r600_gfx_get_wptr, | |
900 | .set_wptr = &r600_gfx_set_wptr, | |
76a0df85 CK |
901 | }; |
902 | ||
903 | static struct radeon_asic_ring r600_dma_ring = { | |
904 | .ib_execute = &r600_dma_ring_ib_execute, | |
905 | .emit_fence = &r600_dma_fence_ring_emit, | |
906 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
907 | .cs_parse = &r600_dma_cs_parse, | |
908 | .ring_test = &r600_dma_ring_test, | |
909 | .ib_test = &r600_dma_ib_test, | |
910 | .is_lockup = &r600_dma_is_lockup, | |
2e1e6dad CK |
911 | .get_rptr = &r600_dma_get_rptr, |
912 | .get_wptr = &r600_dma_get_wptr, | |
913 | .set_wptr = &r600_dma_set_wptr, | |
76a0df85 CK |
914 | }; |
915 | ||
48e7a5f1 DV |
916 | static struct radeon_asic r600_asic = { |
917 | .init = &r600_init, | |
918 | .fini = &r600_fini, | |
919 | .suspend = &r600_suspend, | |
920 | .resume = &r600_resume, | |
48e7a5f1 | 921 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 922 | .asic_reset = &r600_asic_reset, |
124764f1 | 923 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
924 | .gui_idle = &r600_gui_idle, |
925 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 926 | .get_xclk = &r600_get_xclk, |
d0418894 | 927 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
928 | .gart = { |
929 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
cb658906 | 930 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
931 | .set_page = &rs600_gart_set_page, |
932 | }, | |
4c87bc26 | 933 | .ring = { |
76a0df85 CK |
934 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
935 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
4c87bc26 | 936 | }, |
b35ea4ab AD |
937 | .irq = { |
938 | .set = &r600_irq_set, | |
939 | .process = &r600_irq_process, | |
940 | }, | |
c79a49ca AD |
941 | .display = { |
942 | .bandwidth_update = &rv515_bandwidth_update, | |
943 | .get_vblank_counter = &rs600_get_vblank_counter, | |
944 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 945 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 946 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 947 | }, |
27cd7769 | 948 | .copy = { |
8dddb993 | 949 | .blit = &r600_copy_cpdma, |
27cd7769 | 950 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
4d75658b AD |
951 | .dma = &r600_copy_dma, |
952 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 953 | .copy = &r600_copy_cpdma, |
aeea40cb | 954 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
27cd7769 | 955 | }, |
9e6f3d02 AD |
956 | .surface = { |
957 | .set_reg = r600_set_surface_reg, | |
958 | .clear_reg = r600_clear_surface_reg, | |
959 | }, | |
901ea57d AD |
960 | .hpd = { |
961 | .init = &r600_hpd_init, | |
962 | .fini = &r600_hpd_fini, | |
963 | .sense = &r600_hpd_sense, | |
964 | .set_polarity = &r600_hpd_set_polarity, | |
965 | }, | |
a02fa397 AD |
966 | .pm = { |
967 | .misc = &r600_pm_misc, | |
968 | .prepare = &rs600_pm_prepare, | |
969 | .finish = &rs600_pm_finish, | |
970 | .init_profile = &r600_pm_init_profile, | |
971 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
972 | .get_engine_clock = &radeon_atom_get_engine_clock, |
973 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
974 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
975 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
976 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
977 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
978 | .set_clock_gating = NULL, | |
6bd1c385 | 979 | .get_temperature = &rv6xx_get_temp, |
a02fa397 | 980 | }, |
0f9e006c | 981 | .pflip = { |
0f9e006c | 982 | .page_flip = &rs600_page_flip, |
157fa14d | 983 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 984 | }, |
48e7a5f1 DV |
985 | }; |
986 | ||
856754c3 CK |
987 | static struct radeon_asic_ring rv6xx_uvd_ring = { |
988 | .ib_execute = &uvd_v1_0_ib_execute, | |
989 | .emit_fence = &uvd_v1_0_fence_emit, | |
990 | .emit_semaphore = &uvd_v1_0_semaphore_emit, | |
991 | .cs_parse = &radeon_uvd_cs_parse, | |
992 | .ring_test = &uvd_v1_0_ring_test, | |
993 | .ib_test = &uvd_v1_0_ib_test, | |
994 | .is_lockup = &radeon_ring_test_lockup, | |
995 | .get_rptr = &uvd_v1_0_get_rptr, | |
996 | .get_wptr = &uvd_v1_0_get_wptr, | |
997 | .set_wptr = &uvd_v1_0_set_wptr, | |
998 | }; | |
999 | ||
ca361b65 AD |
1000 | static struct radeon_asic rv6xx_asic = { |
1001 | .init = &r600_init, | |
1002 | .fini = &r600_fini, | |
1003 | .suspend = &r600_suspend, | |
1004 | .resume = &r600_resume, | |
1005 | .vga_set_state = &r600_vga_set_state, | |
1006 | .asic_reset = &r600_asic_reset, | |
124764f1 | 1007 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
ca361b65 AD |
1008 | .gui_idle = &r600_gui_idle, |
1009 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
1010 | .get_xclk = &r600_get_xclk, | |
1011 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | |
1012 | .gart = { | |
1013 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
cb658906 | 1014 | .get_page_entry = &rs600_gart_get_page_entry, |
ca361b65 AD |
1015 | .set_page = &rs600_gart_set_page, |
1016 | }, | |
1017 | .ring = { | |
76a0df85 CK |
1018 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1019 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
856754c3 | 1020 | [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, |
ca361b65 AD |
1021 | }, |
1022 | .irq = { | |
1023 | .set = &r600_irq_set, | |
1024 | .process = &r600_irq_process, | |
1025 | }, | |
1026 | .display = { | |
1027 | .bandwidth_update = &rv515_bandwidth_update, | |
1028 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1029 | .wait_for_vblank = &avivo_wait_for_vblank, | |
1030 | .set_backlight_level = &atombios_set_backlight_level, | |
1031 | .get_backlight_level = &atombios_get_backlight_level, | |
1032 | }, | |
1033 | .copy = { | |
8dddb993 | 1034 | .blit = &r600_copy_cpdma, |
ca361b65 AD |
1035 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1036 | .dma = &r600_copy_dma, | |
1037 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 1038 | .copy = &r600_copy_cpdma, |
aeea40cb | 1039 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
ca361b65 AD |
1040 | }, |
1041 | .surface = { | |
1042 | .set_reg = r600_set_surface_reg, | |
1043 | .clear_reg = r600_clear_surface_reg, | |
1044 | }, | |
1045 | .hpd = { | |
1046 | .init = &r600_hpd_init, | |
1047 | .fini = &r600_hpd_fini, | |
1048 | .sense = &r600_hpd_sense, | |
1049 | .set_polarity = &r600_hpd_set_polarity, | |
1050 | }, | |
1051 | .pm = { | |
1052 | .misc = &r600_pm_misc, | |
1053 | .prepare = &rs600_pm_prepare, | |
1054 | .finish = &rs600_pm_finish, | |
1055 | .init_profile = &r600_pm_init_profile, | |
1056 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1057 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1058 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1059 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1060 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1061 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1062 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1063 | .set_clock_gating = NULL, | |
1064 | .get_temperature = &rv6xx_get_temp, | |
1b9ba70a | 1065 | .set_uvd_clocks = &r600_set_uvd_clocks, |
ca361b65 | 1066 | }, |
4a6369e9 AD |
1067 | .dpm = { |
1068 | .init = &rv6xx_dpm_init, | |
1069 | .setup_asic = &rv6xx_setup_asic, | |
1070 | .enable = &rv6xx_dpm_enable, | |
a4643ba3 | 1071 | .late_enable = &r600_dpm_late_enable, |
4a6369e9 | 1072 | .disable = &rv6xx_dpm_disable, |
98243917 | 1073 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
4a6369e9 | 1074 | .set_power_state = &rv6xx_dpm_set_power_state, |
98243917 | 1075 | .post_set_power_state = &r600_dpm_post_set_power_state, |
4a6369e9 AD |
1076 | .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, |
1077 | .fini = &rv6xx_dpm_fini, | |
1078 | .get_sclk = &rv6xx_dpm_get_sclk, | |
1079 | .get_mclk = &rv6xx_dpm_get_mclk, | |
1080 | .print_power_state = &rv6xx_dpm_print_power_state, | |
242916a5 | 1081 | .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, |
f4f85a8c | 1082 | .force_performance_level = &rv6xx_dpm_force_performance_level, |
d0a04d3b AD |
1083 | .get_current_sclk = &rv6xx_dpm_get_current_sclk, |
1084 | .get_current_mclk = &rv6xx_dpm_get_current_mclk, | |
4a6369e9 | 1085 | }, |
ca361b65 | 1086 | .pflip = { |
ca361b65 | 1087 | .page_flip = &rs600_page_flip, |
157fa14d | 1088 | .page_flip_pending = &rs600_page_flip_pending, |
ca361b65 AD |
1089 | }, |
1090 | }; | |
1091 | ||
f47299c5 AD |
1092 | static struct radeon_asic rs780_asic = { |
1093 | .init = &r600_init, | |
1094 | .fini = &r600_fini, | |
1095 | .suspend = &r600_suspend, | |
1096 | .resume = &r600_resume, | |
f47299c5 | 1097 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 1098 | .asic_reset = &r600_asic_reset, |
124764f1 | 1099 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1100 | .gui_idle = &r600_gui_idle, |
1101 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 1102 | .get_xclk = &r600_get_xclk, |
d0418894 | 1103 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1104 | .gart = { |
1105 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
cb658906 | 1106 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1107 | .set_page = &rs600_gart_set_page, |
1108 | }, | |
4c87bc26 | 1109 | .ring = { |
76a0df85 CK |
1110 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1111 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
856754c3 | 1112 | [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, |
4c87bc26 | 1113 | }, |
b35ea4ab AD |
1114 | .irq = { |
1115 | .set = &r600_irq_set, | |
1116 | .process = &r600_irq_process, | |
1117 | }, | |
c79a49ca AD |
1118 | .display = { |
1119 | .bandwidth_update = &rs690_bandwidth_update, | |
1120 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1121 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1122 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1123 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1124 | }, |
27cd7769 | 1125 | .copy = { |
8dddb993 | 1126 | .blit = &r600_copy_cpdma, |
27cd7769 | 1127 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
4d75658b AD |
1128 | .dma = &r600_copy_dma, |
1129 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 1130 | .copy = &r600_copy_cpdma, |
aeea40cb | 1131 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
27cd7769 | 1132 | }, |
9e6f3d02 AD |
1133 | .surface = { |
1134 | .set_reg = r600_set_surface_reg, | |
1135 | .clear_reg = r600_clear_surface_reg, | |
1136 | }, | |
901ea57d AD |
1137 | .hpd = { |
1138 | .init = &r600_hpd_init, | |
1139 | .fini = &r600_hpd_fini, | |
1140 | .sense = &r600_hpd_sense, | |
1141 | .set_polarity = &r600_hpd_set_polarity, | |
1142 | }, | |
a02fa397 AD |
1143 | .pm = { |
1144 | .misc = &r600_pm_misc, | |
1145 | .prepare = &rs600_pm_prepare, | |
1146 | .finish = &rs600_pm_finish, | |
1147 | .init_profile = &rs780_pm_init_profile, | |
1148 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1149 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1150 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1151 | .get_memory_clock = NULL, | |
1152 | .set_memory_clock = NULL, | |
1153 | .get_pcie_lanes = NULL, | |
1154 | .set_pcie_lanes = NULL, | |
1155 | .set_clock_gating = NULL, | |
6bd1c385 | 1156 | .get_temperature = &rv6xx_get_temp, |
1b9ba70a | 1157 | .set_uvd_clocks = &r600_set_uvd_clocks, |
a02fa397 | 1158 | }, |
9d67006e AD |
1159 | .dpm = { |
1160 | .init = &rs780_dpm_init, | |
1161 | .setup_asic = &rs780_dpm_setup_asic, | |
1162 | .enable = &rs780_dpm_enable, | |
a4643ba3 | 1163 | .late_enable = &r600_dpm_late_enable, |
9d67006e | 1164 | .disable = &rs780_dpm_disable, |
98243917 | 1165 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
9d67006e | 1166 | .set_power_state = &rs780_dpm_set_power_state, |
98243917 | 1167 | .post_set_power_state = &r600_dpm_post_set_power_state, |
9d67006e AD |
1168 | .display_configuration_changed = &rs780_dpm_display_configuration_changed, |
1169 | .fini = &rs780_dpm_fini, | |
1170 | .get_sclk = &rs780_dpm_get_sclk, | |
1171 | .get_mclk = &rs780_dpm_get_mclk, | |
1172 | .print_power_state = &rs780_dpm_print_power_state, | |
444bddc4 | 1173 | .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, |
63580c3e | 1174 | .force_performance_level = &rs780_dpm_force_performance_level, |
3c94566c AD |
1175 | .get_current_sclk = &rs780_dpm_get_current_sclk, |
1176 | .get_current_mclk = &rs780_dpm_get_current_mclk, | |
9d67006e | 1177 | }, |
0f9e006c | 1178 | .pflip = { |
0f9e006c | 1179 | .page_flip = &rs600_page_flip, |
157fa14d | 1180 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 1181 | }, |
f47299c5 AD |
1182 | }; |
1183 | ||
76a0df85 | 1184 | static struct radeon_asic_ring rv770_uvd_ring = { |
e409b128 CK |
1185 | .ib_execute = &uvd_v1_0_ib_execute, |
1186 | .emit_fence = &uvd_v2_2_fence_emit, | |
1187 | .emit_semaphore = &uvd_v1_0_semaphore_emit, | |
76a0df85 | 1188 | .cs_parse = &radeon_uvd_cs_parse, |
e409b128 CK |
1189 | .ring_test = &uvd_v1_0_ring_test, |
1190 | .ib_test = &uvd_v1_0_ib_test, | |
76a0df85 | 1191 | .is_lockup = &radeon_ring_test_lockup, |
e409b128 CK |
1192 | .get_rptr = &uvd_v1_0_get_rptr, |
1193 | .get_wptr = &uvd_v1_0_get_wptr, | |
1194 | .set_wptr = &uvd_v1_0_set_wptr, | |
76a0df85 CK |
1195 | }; |
1196 | ||
48e7a5f1 DV |
1197 | static struct radeon_asic rv770_asic = { |
1198 | .init = &rv770_init, | |
1199 | .fini = &rv770_fini, | |
1200 | .suspend = &rv770_suspend, | |
1201 | .resume = &rv770_resume, | |
a2d07b74 | 1202 | .asic_reset = &r600_asic_reset, |
48e7a5f1 | 1203 | .vga_set_state = &r600_vga_set_state, |
124764f1 | 1204 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1205 | .gui_idle = &r600_gui_idle, |
1206 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 1207 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1208 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1209 | .gart = { |
1210 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
cb658906 | 1211 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1212 | .set_page = &rs600_gart_set_page, |
1213 | }, | |
4c87bc26 | 1214 | .ring = { |
76a0df85 CK |
1215 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1216 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
1217 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1218 | }, |
b35ea4ab AD |
1219 | .irq = { |
1220 | .set = &r600_irq_set, | |
1221 | .process = &r600_irq_process, | |
1222 | }, | |
c79a49ca AD |
1223 | .display = { |
1224 | .bandwidth_update = &rv515_bandwidth_update, | |
1225 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1226 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1227 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1228 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1229 | }, |
27cd7769 | 1230 | .copy = { |
8dddb993 | 1231 | .blit = &r600_copy_cpdma, |
27cd7769 | 1232 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
43fb7787 | 1233 | .dma = &rv770_copy_dma, |
4d75658b | 1234 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
43fb7787 | 1235 | .copy = &rv770_copy_dma, |
2d6cc729 | 1236 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
27cd7769 | 1237 | }, |
9e6f3d02 AD |
1238 | .surface = { |
1239 | .set_reg = r600_set_surface_reg, | |
1240 | .clear_reg = r600_clear_surface_reg, | |
1241 | }, | |
901ea57d AD |
1242 | .hpd = { |
1243 | .init = &r600_hpd_init, | |
1244 | .fini = &r600_hpd_fini, | |
1245 | .sense = &r600_hpd_sense, | |
1246 | .set_polarity = &r600_hpd_set_polarity, | |
1247 | }, | |
a02fa397 AD |
1248 | .pm = { |
1249 | .misc = &rv770_pm_misc, | |
1250 | .prepare = &rs600_pm_prepare, | |
1251 | .finish = &rs600_pm_finish, | |
1252 | .init_profile = &r600_pm_init_profile, | |
1253 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1254 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1255 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1256 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1257 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1258 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1259 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1260 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
ef0e6e65 | 1261 | .set_uvd_clocks = &rv770_set_uvd_clocks, |
6bd1c385 | 1262 | .get_temperature = &rv770_get_temp, |
a02fa397 | 1263 | }, |
66229b20 AD |
1264 | .dpm = { |
1265 | .init = &rv770_dpm_init, | |
1266 | .setup_asic = &rv770_dpm_setup_asic, | |
1267 | .enable = &rv770_dpm_enable, | |
a3f11245 | 1268 | .late_enable = &rv770_dpm_late_enable, |
66229b20 | 1269 | .disable = &rv770_dpm_disable, |
98243917 | 1270 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
66229b20 | 1271 | .set_power_state = &rv770_dpm_set_power_state, |
98243917 | 1272 | .post_set_power_state = &r600_dpm_post_set_power_state, |
66229b20 AD |
1273 | .display_configuration_changed = &rv770_dpm_display_configuration_changed, |
1274 | .fini = &rv770_dpm_fini, | |
1275 | .get_sclk = &rv770_dpm_get_sclk, | |
1276 | .get_mclk = &rv770_dpm_get_mclk, | |
1277 | .print_power_state = &rv770_dpm_print_power_state, | |
bd210d11 | 1278 | .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1279 | .force_performance_level = &rv770_dpm_force_performance_level, |
b06195d9 | 1280 | .vblank_too_short = &rv770_dpm_vblank_too_short, |
296deb71 AD |
1281 | .get_current_sclk = &rv770_dpm_get_current_sclk, |
1282 | .get_current_mclk = &rv770_dpm_get_current_mclk, | |
66229b20 | 1283 | }, |
0f9e006c | 1284 | .pflip = { |
0f9e006c | 1285 | .page_flip = &rv770_page_flip, |
157fa14d | 1286 | .page_flip_pending = &rv770_page_flip_pending, |
0f9e006c | 1287 | }, |
48e7a5f1 DV |
1288 | }; |
1289 | ||
76a0df85 CK |
1290 | static struct radeon_asic_ring evergreen_gfx_ring = { |
1291 | .ib_execute = &evergreen_ring_ib_execute, | |
1292 | .emit_fence = &r600_fence_ring_emit, | |
1293 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1294 | .cs_parse = &evergreen_cs_parse, | |
1295 | .ring_test = &r600_ring_test, | |
1296 | .ib_test = &r600_ib_test, | |
1297 | .is_lockup = &evergreen_gfx_is_lockup, | |
ea31bf69 AD |
1298 | .get_rptr = &r600_gfx_get_rptr, |
1299 | .get_wptr = &r600_gfx_get_wptr, | |
1300 | .set_wptr = &r600_gfx_set_wptr, | |
76a0df85 CK |
1301 | }; |
1302 | ||
1303 | static struct radeon_asic_ring evergreen_dma_ring = { | |
1304 | .ib_execute = &evergreen_dma_ring_ib_execute, | |
1305 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1306 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1307 | .cs_parse = &evergreen_dma_cs_parse, | |
1308 | .ring_test = &r600_dma_ring_test, | |
1309 | .ib_test = &r600_dma_ib_test, | |
1310 | .is_lockup = &evergreen_dma_is_lockup, | |
2e1e6dad CK |
1311 | .get_rptr = &r600_dma_get_rptr, |
1312 | .get_wptr = &r600_dma_get_wptr, | |
1313 | .set_wptr = &r600_dma_set_wptr, | |
76a0df85 CK |
1314 | }; |
1315 | ||
48e7a5f1 DV |
1316 | static struct radeon_asic evergreen_asic = { |
1317 | .init = &evergreen_init, | |
1318 | .fini = &evergreen_fini, | |
1319 | .suspend = &evergreen_suspend, | |
1320 | .resume = &evergreen_resume, | |
a2d07b74 | 1321 | .asic_reset = &evergreen_asic_reset, |
48e7a5f1 | 1322 | .vga_set_state = &r600_vga_set_state, |
124764f1 | 1323 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1324 | .gui_idle = &r600_gui_idle, |
1325 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1326 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1327 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1328 | .gart = { |
1329 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
cb658906 | 1330 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1331 | .set_page = &rs600_gart_set_page, |
1332 | }, | |
4c87bc26 | 1333 | .ring = { |
76a0df85 CK |
1334 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1335 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1336 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1337 | }, |
b35ea4ab AD |
1338 | .irq = { |
1339 | .set = &evergreen_irq_set, | |
1340 | .process = &evergreen_irq_process, | |
1341 | }, | |
c79a49ca AD |
1342 | .display = { |
1343 | .bandwidth_update = &evergreen_bandwidth_update, | |
1344 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1345 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1346 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1347 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1348 | }, |
27cd7769 | 1349 | .copy = { |
8dddb993 | 1350 | .blit = &r600_copy_cpdma, |
27cd7769 | 1351 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1352 | .dma = &evergreen_copy_dma, |
1353 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1354 | .copy = &evergreen_copy_dma, |
1355 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1356 | }, |
9e6f3d02 AD |
1357 | .surface = { |
1358 | .set_reg = r600_set_surface_reg, | |
1359 | .clear_reg = r600_clear_surface_reg, | |
1360 | }, | |
901ea57d AD |
1361 | .hpd = { |
1362 | .init = &evergreen_hpd_init, | |
1363 | .fini = &evergreen_hpd_fini, | |
1364 | .sense = &evergreen_hpd_sense, | |
1365 | .set_polarity = &evergreen_hpd_set_polarity, | |
1366 | }, | |
a02fa397 AD |
1367 | .pm = { |
1368 | .misc = &evergreen_pm_misc, | |
1369 | .prepare = &evergreen_pm_prepare, | |
1370 | .finish = &evergreen_pm_finish, | |
1371 | .init_profile = &r600_pm_init_profile, | |
1372 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1373 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1374 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1375 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1376 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1377 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1378 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1379 | .set_clock_gating = NULL, | |
a8b4925c | 1380 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1381 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1382 | }, |
dc50ba7f AD |
1383 | .dpm = { |
1384 | .init = &cypress_dpm_init, | |
1385 | .setup_asic = &cypress_dpm_setup_asic, | |
1386 | .enable = &cypress_dpm_enable, | |
a3f11245 | 1387 | .late_enable = &rv770_dpm_late_enable, |
dc50ba7f | 1388 | .disable = &cypress_dpm_disable, |
98243917 | 1389 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
dc50ba7f | 1390 | .set_power_state = &cypress_dpm_set_power_state, |
98243917 | 1391 | .post_set_power_state = &r600_dpm_post_set_power_state, |
dc50ba7f AD |
1392 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1393 | .fini = &cypress_dpm_fini, | |
1394 | .get_sclk = &rv770_dpm_get_sclk, | |
1395 | .get_mclk = &rv770_dpm_get_mclk, | |
1396 | .print_power_state = &rv770_dpm_print_power_state, | |
bd210d11 | 1397 | .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1398 | .force_performance_level = &rv770_dpm_force_performance_level, |
d0b54bdc | 1399 | .vblank_too_short = &cypress_dpm_vblank_too_short, |
296deb71 AD |
1400 | .get_current_sclk = &rv770_dpm_get_current_sclk, |
1401 | .get_current_mclk = &rv770_dpm_get_current_mclk, | |
dc50ba7f | 1402 | }, |
0f9e006c | 1403 | .pflip = { |
0f9e006c | 1404 | .page_flip = &evergreen_page_flip, |
157fa14d | 1405 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1406 | }, |
48e7a5f1 DV |
1407 | }; |
1408 | ||
958261d1 AD |
1409 | static struct radeon_asic sumo_asic = { |
1410 | .init = &evergreen_init, | |
1411 | .fini = &evergreen_fini, | |
1412 | .suspend = &evergreen_suspend, | |
1413 | .resume = &evergreen_resume, | |
958261d1 AD |
1414 | .asic_reset = &evergreen_asic_reset, |
1415 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1416 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1417 | .gui_idle = &r600_gui_idle, |
1418 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1419 | .get_xclk = &r600_get_xclk, |
d0418894 | 1420 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1421 | .gart = { |
1422 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
cb658906 | 1423 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1424 | .set_page = &rs600_gart_set_page, |
1425 | }, | |
4c87bc26 | 1426 | .ring = { |
76a0df85 CK |
1427 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1428 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1429 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1430 | }, |
b35ea4ab AD |
1431 | .irq = { |
1432 | .set = &evergreen_irq_set, | |
1433 | .process = &evergreen_irq_process, | |
1434 | }, | |
c79a49ca AD |
1435 | .display = { |
1436 | .bandwidth_update = &evergreen_bandwidth_update, | |
1437 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1438 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1439 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1440 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1441 | }, |
27cd7769 | 1442 | .copy = { |
8dddb993 | 1443 | .blit = &r600_copy_cpdma, |
27cd7769 | 1444 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1445 | .dma = &evergreen_copy_dma, |
1446 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1447 | .copy = &evergreen_copy_dma, |
1448 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1449 | }, |
9e6f3d02 AD |
1450 | .surface = { |
1451 | .set_reg = r600_set_surface_reg, | |
1452 | .clear_reg = r600_clear_surface_reg, | |
1453 | }, | |
901ea57d AD |
1454 | .hpd = { |
1455 | .init = &evergreen_hpd_init, | |
1456 | .fini = &evergreen_hpd_fini, | |
1457 | .sense = &evergreen_hpd_sense, | |
1458 | .set_polarity = &evergreen_hpd_set_polarity, | |
1459 | }, | |
a02fa397 AD |
1460 | .pm = { |
1461 | .misc = &evergreen_pm_misc, | |
1462 | .prepare = &evergreen_pm_prepare, | |
1463 | .finish = &evergreen_pm_finish, | |
1464 | .init_profile = &sumo_pm_init_profile, | |
1465 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1466 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1467 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1468 | .get_memory_clock = NULL, | |
1469 | .set_memory_clock = NULL, | |
1470 | .get_pcie_lanes = NULL, | |
1471 | .set_pcie_lanes = NULL, | |
1472 | .set_clock_gating = NULL, | |
23d33ba3 | 1473 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
6bd1c385 | 1474 | .get_temperature = &sumo_get_temp, |
a02fa397 | 1475 | }, |
80ea2c12 AD |
1476 | .dpm = { |
1477 | .init = &sumo_dpm_init, | |
1478 | .setup_asic = &sumo_dpm_setup_asic, | |
1479 | .enable = &sumo_dpm_enable, | |
14ec9fab | 1480 | .late_enable = &sumo_dpm_late_enable, |
80ea2c12 | 1481 | .disable = &sumo_dpm_disable, |
422a56bc | 1482 | .pre_set_power_state = &sumo_dpm_pre_set_power_state, |
80ea2c12 | 1483 | .set_power_state = &sumo_dpm_set_power_state, |
422a56bc | 1484 | .post_set_power_state = &sumo_dpm_post_set_power_state, |
80ea2c12 AD |
1485 | .display_configuration_changed = &sumo_dpm_display_configuration_changed, |
1486 | .fini = &sumo_dpm_fini, | |
1487 | .get_sclk = &sumo_dpm_get_sclk, | |
1488 | .get_mclk = &sumo_dpm_get_mclk, | |
1489 | .print_power_state = &sumo_dpm_print_power_state, | |
fb70160c | 1490 | .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, |
5d5e5591 | 1491 | .force_performance_level = &sumo_dpm_force_performance_level, |
80ea2c12 | 1492 | }, |
0f9e006c | 1493 | .pflip = { |
0f9e006c | 1494 | .page_flip = &evergreen_page_flip, |
157fa14d | 1495 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1496 | }, |
958261d1 AD |
1497 | }; |
1498 | ||
a43b7665 AD |
1499 | static struct radeon_asic btc_asic = { |
1500 | .init = &evergreen_init, | |
1501 | .fini = &evergreen_fini, | |
1502 | .suspend = &evergreen_suspend, | |
1503 | .resume = &evergreen_resume, | |
a43b7665 AD |
1504 | .asic_reset = &evergreen_asic_reset, |
1505 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1506 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1507 | .gui_idle = &r600_gui_idle, |
1508 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1509 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1510 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1511 | .gart = { |
1512 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
cb658906 | 1513 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1514 | .set_page = &rs600_gart_set_page, |
1515 | }, | |
4c87bc26 | 1516 | .ring = { |
76a0df85 CK |
1517 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1518 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1519 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1520 | }, |
b35ea4ab AD |
1521 | .irq = { |
1522 | .set = &evergreen_irq_set, | |
1523 | .process = &evergreen_irq_process, | |
1524 | }, | |
c79a49ca AD |
1525 | .display = { |
1526 | .bandwidth_update = &evergreen_bandwidth_update, | |
1527 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1528 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1529 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1530 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1531 | }, |
27cd7769 | 1532 | .copy = { |
8dddb993 | 1533 | .blit = &r600_copy_cpdma, |
27cd7769 | 1534 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1535 | .dma = &evergreen_copy_dma, |
1536 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1537 | .copy = &evergreen_copy_dma, |
1538 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1539 | }, |
9e6f3d02 AD |
1540 | .surface = { |
1541 | .set_reg = r600_set_surface_reg, | |
1542 | .clear_reg = r600_clear_surface_reg, | |
1543 | }, | |
901ea57d AD |
1544 | .hpd = { |
1545 | .init = &evergreen_hpd_init, | |
1546 | .fini = &evergreen_hpd_fini, | |
1547 | .sense = &evergreen_hpd_sense, | |
1548 | .set_polarity = &evergreen_hpd_set_polarity, | |
1549 | }, | |
a02fa397 AD |
1550 | .pm = { |
1551 | .misc = &evergreen_pm_misc, | |
1552 | .prepare = &evergreen_pm_prepare, | |
1553 | .finish = &evergreen_pm_finish, | |
27810fb2 | 1554 | .init_profile = &btc_pm_init_profile, |
a02fa397 | 1555 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
798bcf73 AD |
1556 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1557 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1558 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1559 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1560 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1561 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
798bcf73 | 1562 | .set_clock_gating = NULL, |
a8b4925c | 1563 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1564 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1565 | }, |
6596afd4 AD |
1566 | .dpm = { |
1567 | .init = &btc_dpm_init, | |
1568 | .setup_asic = &btc_dpm_setup_asic, | |
1569 | .enable = &btc_dpm_enable, | |
a3f11245 | 1570 | .late_enable = &rv770_dpm_late_enable, |
6596afd4 | 1571 | .disable = &btc_dpm_disable, |
e8a9539f | 1572 | .pre_set_power_state = &btc_dpm_pre_set_power_state, |
6596afd4 | 1573 | .set_power_state = &btc_dpm_set_power_state, |
e8a9539f | 1574 | .post_set_power_state = &btc_dpm_post_set_power_state, |
6596afd4 AD |
1575 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1576 | .fini = &btc_dpm_fini, | |
e8a9539f AD |
1577 | .get_sclk = &btc_dpm_get_sclk, |
1578 | .get_mclk = &btc_dpm_get_mclk, | |
6596afd4 | 1579 | .print_power_state = &rv770_dpm_print_power_state, |
9f3f63f2 | 1580 | .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1581 | .force_performance_level = &rv770_dpm_force_performance_level, |
a84301c6 | 1582 | .vblank_too_short = &btc_dpm_vblank_too_short, |
99550ee9 AD |
1583 | .get_current_sclk = &btc_dpm_get_current_sclk, |
1584 | .get_current_mclk = &btc_dpm_get_current_mclk, | |
6596afd4 | 1585 | }, |
0f9e006c | 1586 | .pflip = { |
0f9e006c | 1587 | .page_flip = &evergreen_page_flip, |
157fa14d | 1588 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1589 | }, |
a43b7665 AD |
1590 | }; |
1591 | ||
76a0df85 CK |
1592 | static struct radeon_asic_ring cayman_gfx_ring = { |
1593 | .ib_execute = &cayman_ring_ib_execute, | |
1594 | .ib_parse = &evergreen_ib_parse, | |
1595 | .emit_fence = &cayman_fence_ring_emit, | |
1596 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1597 | .cs_parse = &evergreen_cs_parse, | |
1598 | .ring_test = &r600_ring_test, | |
1599 | .ib_test = &r600_ib_test, | |
1600 | .is_lockup = &cayman_gfx_is_lockup, | |
1601 | .vm_flush = &cayman_vm_flush, | |
ea31bf69 AD |
1602 | .get_rptr = &cayman_gfx_get_rptr, |
1603 | .get_wptr = &cayman_gfx_get_wptr, | |
1604 | .set_wptr = &cayman_gfx_set_wptr, | |
76a0df85 CK |
1605 | }; |
1606 | ||
1607 | static struct radeon_asic_ring cayman_dma_ring = { | |
1608 | .ib_execute = &cayman_dma_ring_ib_execute, | |
1609 | .ib_parse = &evergreen_dma_ib_parse, | |
1610 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1611 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1612 | .cs_parse = &evergreen_dma_cs_parse, | |
1613 | .ring_test = &r600_dma_ring_test, | |
1614 | .ib_test = &r600_dma_ib_test, | |
1615 | .is_lockup = &cayman_dma_is_lockup, | |
1616 | .vm_flush = &cayman_dma_vm_flush, | |
ea31bf69 AD |
1617 | .get_rptr = &cayman_dma_get_rptr, |
1618 | .get_wptr = &cayman_dma_get_wptr, | |
1619 | .set_wptr = &cayman_dma_set_wptr | |
76a0df85 CK |
1620 | }; |
1621 | ||
1622 | static struct radeon_asic_ring cayman_uvd_ring = { | |
e409b128 CK |
1623 | .ib_execute = &uvd_v1_0_ib_execute, |
1624 | .emit_fence = &uvd_v2_2_fence_emit, | |
1625 | .emit_semaphore = &uvd_v3_1_semaphore_emit, | |
76a0df85 | 1626 | .cs_parse = &radeon_uvd_cs_parse, |
e409b128 CK |
1627 | .ring_test = &uvd_v1_0_ring_test, |
1628 | .ib_test = &uvd_v1_0_ib_test, | |
76a0df85 | 1629 | .is_lockup = &radeon_ring_test_lockup, |
e409b128 CK |
1630 | .get_rptr = &uvd_v1_0_get_rptr, |
1631 | .get_wptr = &uvd_v1_0_get_wptr, | |
1632 | .set_wptr = &uvd_v1_0_set_wptr, | |
76a0df85 CK |
1633 | }; |
1634 | ||
e3487629 AD |
1635 | static struct radeon_asic cayman_asic = { |
1636 | .init = &cayman_init, | |
1637 | .fini = &cayman_fini, | |
1638 | .suspend = &cayman_suspend, | |
1639 | .resume = &cayman_resume, | |
e3487629 AD |
1640 | .asic_reset = &cayman_asic_reset, |
1641 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1642 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1643 | .gui_idle = &r600_gui_idle, |
1644 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1645 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1646 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1647 | .gart = { |
1648 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
cb658906 | 1649 | .get_page_entry = &rs600_gart_get_page_entry, |
c5b3b850 AD |
1650 | .set_page = &rs600_gart_set_page, |
1651 | }, | |
05b07147 CK |
1652 | .vm = { |
1653 | .init = &cayman_vm_init, | |
1654 | .fini = &cayman_vm_fini, | |
03f62abd CK |
1655 | .copy_pages = &cayman_dma_vm_copy_pages, |
1656 | .write_pages = &cayman_dma_vm_write_pages, | |
1657 | .set_pages = &cayman_dma_vm_set_pages, | |
1658 | .pad_ib = &cayman_dma_vm_pad_ib, | |
05b07147 | 1659 | }, |
4c87bc26 | 1660 | .ring = { |
76a0df85 CK |
1661 | [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, |
1662 | [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, | |
1663 | [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, | |
1664 | [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, | |
1665 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, | |
1666 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
4c87bc26 | 1667 | }, |
b35ea4ab AD |
1668 | .irq = { |
1669 | .set = &evergreen_irq_set, | |
1670 | .process = &evergreen_irq_process, | |
1671 | }, | |
c79a49ca AD |
1672 | .display = { |
1673 | .bandwidth_update = &evergreen_bandwidth_update, | |
1674 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1675 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1676 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1677 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 1678 | }, |
27cd7769 | 1679 | .copy = { |
8dddb993 | 1680 | .blit = &r600_copy_cpdma, |
27cd7769 | 1681 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
f60cbd11 AD |
1682 | .dma = &evergreen_copy_dma, |
1683 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1684 | .copy = &evergreen_copy_dma, |
1685 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1686 | }, |
9e6f3d02 AD |
1687 | .surface = { |
1688 | .set_reg = r600_set_surface_reg, | |
1689 | .clear_reg = r600_clear_surface_reg, | |
1690 | }, | |
901ea57d AD |
1691 | .hpd = { |
1692 | .init = &evergreen_hpd_init, | |
1693 | .fini = &evergreen_hpd_fini, | |
1694 | .sense = &evergreen_hpd_sense, | |
1695 | .set_polarity = &evergreen_hpd_set_polarity, | |
1696 | }, | |
a02fa397 AD |
1697 | .pm = { |
1698 | .misc = &evergreen_pm_misc, | |
1699 | .prepare = &evergreen_pm_prepare, | |
1700 | .finish = &evergreen_pm_finish, | |
27810fb2 | 1701 | .init_profile = &btc_pm_init_profile, |
a02fa397 | 1702 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
798bcf73 AD |
1703 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1704 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1705 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1706 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1707 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1708 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
798bcf73 | 1709 | .set_clock_gating = NULL, |
a8b4925c | 1710 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1711 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1712 | }, |
69e0b57a AD |
1713 | .dpm = { |
1714 | .init = &ni_dpm_init, | |
1715 | .setup_asic = &ni_dpm_setup_asic, | |
1716 | .enable = &ni_dpm_enable, | |
a3f11245 | 1717 | .late_enable = &rv770_dpm_late_enable, |
69e0b57a | 1718 | .disable = &ni_dpm_disable, |
fee3d744 | 1719 | .pre_set_power_state = &ni_dpm_pre_set_power_state, |
69e0b57a | 1720 | .set_power_state = &ni_dpm_set_power_state, |
fee3d744 | 1721 | .post_set_power_state = &ni_dpm_post_set_power_state, |
69e0b57a AD |
1722 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1723 | .fini = &ni_dpm_fini, | |
1724 | .get_sclk = &ni_dpm_get_sclk, | |
1725 | .get_mclk = &ni_dpm_get_mclk, | |
1726 | .print_power_state = &ni_dpm_print_power_state, | |
bdf0c4f0 | 1727 | .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, |
170a47f0 | 1728 | .force_performance_level = &ni_dpm_force_performance_level, |
76ad73e5 | 1729 | .vblank_too_short = &ni_dpm_vblank_too_short, |
69e0b57a | 1730 | }, |
0f9e006c | 1731 | .pflip = { |
0f9e006c | 1732 | .page_flip = &evergreen_page_flip, |
157fa14d | 1733 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1734 | }, |
e3487629 AD |
1735 | }; |
1736 | ||
be63fe8c AD |
1737 | static struct radeon_asic trinity_asic = { |
1738 | .init = &cayman_init, | |
1739 | .fini = &cayman_fini, | |
1740 | .suspend = &cayman_suspend, | |
1741 | .resume = &cayman_resume, | |
be63fe8c AD |
1742 | .asic_reset = &cayman_asic_reset, |
1743 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1744 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
be63fe8c AD |
1745 | .gui_idle = &r600_gui_idle, |
1746 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1747 | .get_xclk = &r600_get_xclk, |
d0418894 | 1748 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
be63fe8c AD |
1749 | .gart = { |
1750 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
cb658906 | 1751 | .get_page_entry = &rs600_gart_get_page_entry, |
be63fe8c AD |
1752 | .set_page = &rs600_gart_set_page, |
1753 | }, | |
05b07147 CK |
1754 | .vm = { |
1755 | .init = &cayman_vm_init, | |
1756 | .fini = &cayman_vm_fini, | |
03f62abd CK |
1757 | .copy_pages = &cayman_dma_vm_copy_pages, |
1758 | .write_pages = &cayman_dma_vm_write_pages, | |
1759 | .set_pages = &cayman_dma_vm_set_pages, | |
1760 | .pad_ib = &cayman_dma_vm_pad_ib, | |
05b07147 | 1761 | }, |
be63fe8c | 1762 | .ring = { |
76a0df85 CK |
1763 | [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, |
1764 | [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, | |
1765 | [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, | |
1766 | [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, | |
1767 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, | |
1768 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
be63fe8c AD |
1769 | }, |
1770 | .irq = { | |
1771 | .set = &evergreen_irq_set, | |
1772 | .process = &evergreen_irq_process, | |
1773 | }, | |
1774 | .display = { | |
1775 | .bandwidth_update = &dce6_bandwidth_update, | |
1776 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1777 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1778 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1779 | .get_backlight_level = &atombios_get_backlight_level, |
be63fe8c AD |
1780 | }, |
1781 | .copy = { | |
8dddb993 | 1782 | .blit = &r600_copy_cpdma, |
be63fe8c | 1783 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
f60cbd11 AD |
1784 | .dma = &evergreen_copy_dma, |
1785 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1786 | .copy = &evergreen_copy_dma, |
1787 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
be63fe8c AD |
1788 | }, |
1789 | .surface = { | |
1790 | .set_reg = r600_set_surface_reg, | |
1791 | .clear_reg = r600_clear_surface_reg, | |
1792 | }, | |
1793 | .hpd = { | |
1794 | .init = &evergreen_hpd_init, | |
1795 | .fini = &evergreen_hpd_fini, | |
1796 | .sense = &evergreen_hpd_sense, | |
1797 | .set_polarity = &evergreen_hpd_set_polarity, | |
1798 | }, | |
1799 | .pm = { | |
1800 | .misc = &evergreen_pm_misc, | |
1801 | .prepare = &evergreen_pm_prepare, | |
1802 | .finish = &evergreen_pm_finish, | |
1803 | .init_profile = &sumo_pm_init_profile, | |
1804 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1805 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1806 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1807 | .get_memory_clock = NULL, | |
1808 | .set_memory_clock = NULL, | |
1809 | .get_pcie_lanes = NULL, | |
1810 | .set_pcie_lanes = NULL, | |
1811 | .set_clock_gating = NULL, | |
23d33ba3 | 1812 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
29a15221 | 1813 | .get_temperature = &tn_get_temp, |
be63fe8c | 1814 | }, |
d70229f7 AD |
1815 | .dpm = { |
1816 | .init = &trinity_dpm_init, | |
1817 | .setup_asic = &trinity_dpm_setup_asic, | |
1818 | .enable = &trinity_dpm_enable, | |
bda44c1a | 1819 | .late_enable = &trinity_dpm_late_enable, |
d70229f7 | 1820 | .disable = &trinity_dpm_disable, |
a284c48a | 1821 | .pre_set_power_state = &trinity_dpm_pre_set_power_state, |
d70229f7 | 1822 | .set_power_state = &trinity_dpm_set_power_state, |
a284c48a | 1823 | .post_set_power_state = &trinity_dpm_post_set_power_state, |
d70229f7 AD |
1824 | .display_configuration_changed = &trinity_dpm_display_configuration_changed, |
1825 | .fini = &trinity_dpm_fini, | |
1826 | .get_sclk = &trinity_dpm_get_sclk, | |
1827 | .get_mclk = &trinity_dpm_get_mclk, | |
1828 | .print_power_state = &trinity_dpm_print_power_state, | |
490ab931 | 1829 | .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, |
9b5de596 | 1830 | .force_performance_level = &trinity_dpm_force_performance_level, |
11877060 | 1831 | .enable_bapm = &trinity_dpm_enable_bapm, |
d70229f7 | 1832 | }, |
be63fe8c | 1833 | .pflip = { |
be63fe8c | 1834 | .page_flip = &evergreen_page_flip, |
157fa14d | 1835 | .page_flip_pending = &evergreen_page_flip_pending, |
be63fe8c AD |
1836 | }, |
1837 | }; | |
1838 | ||
76a0df85 CK |
1839 | static struct radeon_asic_ring si_gfx_ring = { |
1840 | .ib_execute = &si_ring_ib_execute, | |
1841 | .ib_parse = &si_ib_parse, | |
1842 | .emit_fence = &si_fence_ring_emit, | |
1843 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1844 | .cs_parse = NULL, | |
1845 | .ring_test = &r600_ring_test, | |
1846 | .ib_test = &r600_ib_test, | |
1847 | .is_lockup = &si_gfx_is_lockup, | |
1848 | .vm_flush = &si_vm_flush, | |
ea31bf69 AD |
1849 | .get_rptr = &cayman_gfx_get_rptr, |
1850 | .get_wptr = &cayman_gfx_get_wptr, | |
1851 | .set_wptr = &cayman_gfx_set_wptr, | |
76a0df85 CK |
1852 | }; |
1853 | ||
1854 | static struct radeon_asic_ring si_dma_ring = { | |
1855 | .ib_execute = &cayman_dma_ring_ib_execute, | |
1856 | .ib_parse = &evergreen_dma_ib_parse, | |
1857 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1858 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1859 | .cs_parse = NULL, | |
1860 | .ring_test = &r600_dma_ring_test, | |
1861 | .ib_test = &r600_dma_ib_test, | |
1862 | .is_lockup = &si_dma_is_lockup, | |
1863 | .vm_flush = &si_dma_vm_flush, | |
ea31bf69 AD |
1864 | .get_rptr = &cayman_dma_get_rptr, |
1865 | .get_wptr = &cayman_dma_get_wptr, | |
1866 | .set_wptr = &cayman_dma_set_wptr, | |
76a0df85 CK |
1867 | }; |
1868 | ||
02779c08 AD |
1869 | static struct radeon_asic si_asic = { |
1870 | .init = &si_init, | |
1871 | .fini = &si_fini, | |
1872 | .suspend = &si_suspend, | |
1873 | .resume = &si_resume, | |
02779c08 AD |
1874 | .asic_reset = &si_asic_reset, |
1875 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1876 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
02779c08 AD |
1877 | .gui_idle = &r600_gui_idle, |
1878 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1879 | .get_xclk = &si_get_xclk, |
d0418894 | 1880 | .get_gpu_clock_counter = &si_get_gpu_clock_counter, |
02779c08 AD |
1881 | .gart = { |
1882 | .tlb_flush = &si_pcie_gart_tlb_flush, | |
cb658906 | 1883 | .get_page_entry = &rs600_gart_get_page_entry, |
02779c08 AD |
1884 | .set_page = &rs600_gart_set_page, |
1885 | }, | |
05b07147 CK |
1886 | .vm = { |
1887 | .init = &si_vm_init, | |
1888 | .fini = &si_vm_fini, | |
03f62abd CK |
1889 | .copy_pages = &si_dma_vm_copy_pages, |
1890 | .write_pages = &si_dma_vm_write_pages, | |
1891 | .set_pages = &si_dma_vm_set_pages, | |
1892 | .pad_ib = &cayman_dma_vm_pad_ib, | |
05b07147 | 1893 | }, |
02779c08 | 1894 | .ring = { |
76a0df85 CK |
1895 | [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, |
1896 | [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, | |
1897 | [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, | |
1898 | [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, | |
1899 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, | |
1900 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
02779c08 AD |
1901 | }, |
1902 | .irq = { | |
1903 | .set = &si_irq_set, | |
1904 | .process = &si_irq_process, | |
1905 | }, | |
1906 | .display = { | |
1907 | .bandwidth_update = &dce6_bandwidth_update, | |
1908 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1909 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1910 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1911 | .get_backlight_level = &atombios_get_backlight_level, |
02779c08 AD |
1912 | }, |
1913 | .copy = { | |
5c722739 | 1914 | .blit = &r600_copy_cpdma, |
02779c08 | 1915 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
8c5fd7ef AD |
1916 | .dma = &si_copy_dma, |
1917 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1918 | .copy = &si_copy_dma, |
1919 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
02779c08 AD |
1920 | }, |
1921 | .surface = { | |
1922 | .set_reg = r600_set_surface_reg, | |
1923 | .clear_reg = r600_clear_surface_reg, | |
1924 | }, | |
1925 | .hpd = { | |
1926 | .init = &evergreen_hpd_init, | |
1927 | .fini = &evergreen_hpd_fini, | |
1928 | .sense = &evergreen_hpd_sense, | |
1929 | .set_polarity = &evergreen_hpd_set_polarity, | |
1930 | }, | |
1931 | .pm = { | |
1932 | .misc = &evergreen_pm_misc, | |
1933 | .prepare = &evergreen_pm_prepare, | |
1934 | .finish = &evergreen_pm_finish, | |
1935 | .init_profile = &sumo_pm_init_profile, | |
1936 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1937 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1938 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1939 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1940 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1941 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1942 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
02779c08 | 1943 | .set_clock_gating = NULL, |
2539eb02 | 1944 | .set_uvd_clocks = &si_set_uvd_clocks, |
6bd1c385 | 1945 | .get_temperature = &si_get_temp, |
02779c08 | 1946 | }, |
a9e61410 AD |
1947 | .dpm = { |
1948 | .init = &si_dpm_init, | |
1949 | .setup_asic = &si_dpm_setup_asic, | |
1950 | .enable = &si_dpm_enable, | |
963c115d | 1951 | .late_enable = &si_dpm_late_enable, |
a9e61410 AD |
1952 | .disable = &si_dpm_disable, |
1953 | .pre_set_power_state = &si_dpm_pre_set_power_state, | |
1954 | .set_power_state = &si_dpm_set_power_state, | |
1955 | .post_set_power_state = &si_dpm_post_set_power_state, | |
1956 | .display_configuration_changed = &si_dpm_display_configuration_changed, | |
1957 | .fini = &si_dpm_fini, | |
1958 | .get_sclk = &ni_dpm_get_sclk, | |
1959 | .get_mclk = &ni_dpm_get_mclk, | |
1960 | .print_power_state = &ni_dpm_print_power_state, | |
7982128c | 1961 | .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, |
a160a6a3 | 1962 | .force_performance_level = &si_dpm_force_performance_level, |
f4dec318 | 1963 | .vblank_too_short = &ni_dpm_vblank_too_short, |
5e8150a6 AD |
1964 | .fan_ctrl_set_mode = &si_fan_ctrl_set_mode, |
1965 | .fan_ctrl_get_mode = &si_fan_ctrl_get_mode, | |
1966 | .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent, | |
1967 | .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent, | |
a9e61410 | 1968 | }, |
02779c08 | 1969 | .pflip = { |
02779c08 | 1970 | .page_flip = &evergreen_page_flip, |
157fa14d | 1971 | .page_flip_pending = &evergreen_page_flip_pending, |
02779c08 AD |
1972 | }, |
1973 | }; | |
1974 | ||
76a0df85 CK |
1975 | static struct radeon_asic_ring ci_gfx_ring = { |
1976 | .ib_execute = &cik_ring_ib_execute, | |
1977 | .ib_parse = &cik_ib_parse, | |
1978 | .emit_fence = &cik_fence_gfx_ring_emit, | |
1979 | .emit_semaphore = &cik_semaphore_ring_emit, | |
1980 | .cs_parse = NULL, | |
1981 | .ring_test = &cik_ring_test, | |
1982 | .ib_test = &cik_ib_test, | |
1983 | .is_lockup = &cik_gfx_is_lockup, | |
1984 | .vm_flush = &cik_vm_flush, | |
ea31bf69 AD |
1985 | .get_rptr = &cik_gfx_get_rptr, |
1986 | .get_wptr = &cik_gfx_get_wptr, | |
1987 | .set_wptr = &cik_gfx_set_wptr, | |
76a0df85 CK |
1988 | }; |
1989 | ||
1990 | static struct radeon_asic_ring ci_cp_ring = { | |
1991 | .ib_execute = &cik_ring_ib_execute, | |
1992 | .ib_parse = &cik_ib_parse, | |
1993 | .emit_fence = &cik_fence_compute_ring_emit, | |
1994 | .emit_semaphore = &cik_semaphore_ring_emit, | |
1995 | .cs_parse = NULL, | |
1996 | .ring_test = &cik_ring_test, | |
1997 | .ib_test = &cik_ib_test, | |
1998 | .is_lockup = &cik_gfx_is_lockup, | |
1999 | .vm_flush = &cik_vm_flush, | |
ea31bf69 AD |
2000 | .get_rptr = &cik_compute_get_rptr, |
2001 | .get_wptr = &cik_compute_get_wptr, | |
2002 | .set_wptr = &cik_compute_set_wptr, | |
76a0df85 CK |
2003 | }; |
2004 | ||
2005 | static struct radeon_asic_ring ci_dma_ring = { | |
2006 | .ib_execute = &cik_sdma_ring_ib_execute, | |
2007 | .ib_parse = &cik_ib_parse, | |
2008 | .emit_fence = &cik_sdma_fence_ring_emit, | |
2009 | .emit_semaphore = &cik_sdma_semaphore_ring_emit, | |
2010 | .cs_parse = NULL, | |
2011 | .ring_test = &cik_sdma_ring_test, | |
2012 | .ib_test = &cik_sdma_ib_test, | |
2013 | .is_lockup = &cik_sdma_is_lockup, | |
2014 | .vm_flush = &cik_dma_vm_flush, | |
ea31bf69 AD |
2015 | .get_rptr = &cik_sdma_get_rptr, |
2016 | .get_wptr = &cik_sdma_get_wptr, | |
2017 | .set_wptr = &cik_sdma_set_wptr, | |
76a0df85 CK |
2018 | }; |
2019 | ||
d93f7937 CK |
2020 | static struct radeon_asic_ring ci_vce_ring = { |
2021 | .ib_execute = &radeon_vce_ib_execute, | |
2022 | .emit_fence = &radeon_vce_fence_emit, | |
2023 | .emit_semaphore = &radeon_vce_semaphore_emit, | |
2024 | .cs_parse = &radeon_vce_cs_parse, | |
2025 | .ring_test = &radeon_vce_ring_test, | |
2026 | .ib_test = &radeon_vce_ib_test, | |
2027 | .is_lockup = &radeon_ring_test_lockup, | |
2028 | .get_rptr = &vce_v1_0_get_rptr, | |
2029 | .get_wptr = &vce_v1_0_get_wptr, | |
2030 | .set_wptr = &vce_v1_0_set_wptr, | |
2031 | }; | |
2032 | ||
0672e27b AD |
2033 | static struct radeon_asic ci_asic = { |
2034 | .init = &cik_init, | |
2035 | .fini = &cik_fini, | |
2036 | .suspend = &cik_suspend, | |
2037 | .resume = &cik_resume, | |
2038 | .asic_reset = &cik_asic_reset, | |
2039 | .vga_set_state = &r600_vga_set_state, | |
72a9987e | 2040 | .mmio_hdp_flush = &r600_mmio_hdp_flush, |
0672e27b AD |
2041 | .gui_idle = &r600_gui_idle, |
2042 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
2043 | .get_xclk = &cik_get_xclk, | |
2044 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | |
2045 | .gart = { | |
2046 | .tlb_flush = &cik_pcie_gart_tlb_flush, | |
cb658906 | 2047 | .get_page_entry = &rs600_gart_get_page_entry, |
0672e27b AD |
2048 | .set_page = &rs600_gart_set_page, |
2049 | }, | |
2050 | .vm = { | |
2051 | .init = &cik_vm_init, | |
2052 | .fini = &cik_vm_fini, | |
03f62abd CK |
2053 | .copy_pages = &cik_sdma_vm_copy_pages, |
2054 | .write_pages = &cik_sdma_vm_write_pages, | |
2055 | .set_pages = &cik_sdma_vm_set_pages, | |
2056 | .pad_ib = &cik_sdma_vm_pad_ib, | |
0672e27b AD |
2057 | }, |
2058 | .ring = { | |
76a0df85 CK |
2059 | [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, |
2060 | [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, | |
2061 | [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, | |
2062 | [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, | |
2063 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, | |
2064 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
d93f7937 CK |
2065 | [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, |
2066 | [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, | |
0672e27b AD |
2067 | }, |
2068 | .irq = { | |
2069 | .set = &cik_irq_set, | |
2070 | .process = &cik_irq_process, | |
2071 | }, | |
2072 | .display = { | |
2073 | .bandwidth_update = &dce8_bandwidth_update, | |
2074 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2075 | .wait_for_vblank = &dce4_wait_for_vblank, | |
7272c9d2 SL |
2076 | .set_backlight_level = &atombios_set_backlight_level, |
2077 | .get_backlight_level = &atombios_get_backlight_level, | |
0672e27b AD |
2078 | }, |
2079 | .copy = { | |
7819678f | 2080 | .blit = &cik_copy_cpdma, |
0672e27b AD |
2081 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
2082 | .dma = &cik_copy_dma, | |
2083 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
b5be1a83 CK |
2084 | .copy = &cik_copy_dma, |
2085 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
0672e27b AD |
2086 | }, |
2087 | .surface = { | |
2088 | .set_reg = r600_set_surface_reg, | |
2089 | .clear_reg = r600_clear_surface_reg, | |
2090 | }, | |
2091 | .hpd = { | |
2092 | .init = &evergreen_hpd_init, | |
2093 | .fini = &evergreen_hpd_fini, | |
2094 | .sense = &evergreen_hpd_sense, | |
2095 | .set_polarity = &evergreen_hpd_set_polarity, | |
2096 | }, | |
2097 | .pm = { | |
2098 | .misc = &evergreen_pm_misc, | |
2099 | .prepare = &evergreen_pm_prepare, | |
2100 | .finish = &evergreen_pm_finish, | |
2101 | .init_profile = &sumo_pm_init_profile, | |
2102 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2103 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2104 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2105 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
2106 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
2107 | .get_pcie_lanes = NULL, | |
2108 | .set_pcie_lanes = NULL, | |
2109 | .set_clock_gating = NULL, | |
2110 | .set_uvd_clocks = &cik_set_uvd_clocks, | |
5ad6bf91 | 2111 | .set_vce_clocks = &cik_set_vce_clocks, |
286d9cc6 | 2112 | .get_temperature = &ci_get_temp, |
0672e27b | 2113 | }, |
cc8dbbb4 AD |
2114 | .dpm = { |
2115 | .init = &ci_dpm_init, | |
2116 | .setup_asic = &ci_dpm_setup_asic, | |
2117 | .enable = &ci_dpm_enable, | |
90208427 | 2118 | .late_enable = &ci_dpm_late_enable, |
cc8dbbb4 AD |
2119 | .disable = &ci_dpm_disable, |
2120 | .pre_set_power_state = &ci_dpm_pre_set_power_state, | |
2121 | .set_power_state = &ci_dpm_set_power_state, | |
2122 | .post_set_power_state = &ci_dpm_post_set_power_state, | |
2123 | .display_configuration_changed = &ci_dpm_display_configuration_changed, | |
2124 | .fini = &ci_dpm_fini, | |
2125 | .get_sclk = &ci_dpm_get_sclk, | |
2126 | .get_mclk = &ci_dpm_get_mclk, | |
2127 | .print_power_state = &ci_dpm_print_power_state, | |
94b4adc5 | 2128 | .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, |
89536fd6 | 2129 | .force_performance_level = &ci_dpm_force_performance_level, |
5496131e | 2130 | .vblank_too_short = &ci_dpm_vblank_too_short, |
942bdf7f | 2131 | .powergate_uvd = &ci_dpm_powergate_uvd, |
36689e57 OC |
2132 | .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode, |
2133 | .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode, | |
2134 | .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent, | |
2135 | .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent, | |
cc8dbbb4 | 2136 | }, |
0672e27b | 2137 | .pflip = { |
0672e27b | 2138 | .page_flip = &evergreen_page_flip, |
157fa14d | 2139 | .page_flip_pending = &evergreen_page_flip_pending, |
0672e27b AD |
2140 | }, |
2141 | }; | |
2142 | ||
2143 | static struct radeon_asic kv_asic = { | |
2144 | .init = &cik_init, | |
2145 | .fini = &cik_fini, | |
2146 | .suspend = &cik_suspend, | |
2147 | .resume = &cik_resume, | |
2148 | .asic_reset = &cik_asic_reset, | |
2149 | .vga_set_state = &r600_vga_set_state, | |
72a9987e | 2150 | .mmio_hdp_flush = &r600_mmio_hdp_flush, |
0672e27b AD |
2151 | .gui_idle = &r600_gui_idle, |
2152 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
2153 | .get_xclk = &cik_get_xclk, | |
2154 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | |
2155 | .gart = { | |
2156 | .tlb_flush = &cik_pcie_gart_tlb_flush, | |
cb658906 | 2157 | .get_page_entry = &rs600_gart_get_page_entry, |
0672e27b AD |
2158 | .set_page = &rs600_gart_set_page, |
2159 | }, | |
2160 | .vm = { | |
2161 | .init = &cik_vm_init, | |
2162 | .fini = &cik_vm_fini, | |
03f62abd CK |
2163 | .copy_pages = &cik_sdma_vm_copy_pages, |
2164 | .write_pages = &cik_sdma_vm_write_pages, | |
2165 | .set_pages = &cik_sdma_vm_set_pages, | |
2166 | .pad_ib = &cik_sdma_vm_pad_ib, | |
0672e27b AD |
2167 | }, |
2168 | .ring = { | |
76a0df85 CK |
2169 | [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, |
2170 | [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, | |
2171 | [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, | |
2172 | [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, | |
2173 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, | |
2174 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
d93f7937 CK |
2175 | [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, |
2176 | [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, | |
0672e27b AD |
2177 | }, |
2178 | .irq = { | |
2179 | .set = &cik_irq_set, | |
2180 | .process = &cik_irq_process, | |
2181 | }, | |
2182 | .display = { | |
2183 | .bandwidth_update = &dce8_bandwidth_update, | |
2184 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2185 | .wait_for_vblank = &dce4_wait_for_vblank, | |
7272c9d2 SL |
2186 | .set_backlight_level = &atombios_set_backlight_level, |
2187 | .get_backlight_level = &atombios_get_backlight_level, | |
0672e27b AD |
2188 | }, |
2189 | .copy = { | |
7819678f | 2190 | .blit = &cik_copy_cpdma, |
0672e27b AD |
2191 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
2192 | .dma = &cik_copy_dma, | |
2193 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2194 | .copy = &cik_copy_dma, | |
2195 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2196 | }, | |
2197 | .surface = { | |
2198 | .set_reg = r600_set_surface_reg, | |
2199 | .clear_reg = r600_clear_surface_reg, | |
2200 | }, | |
2201 | .hpd = { | |
2202 | .init = &evergreen_hpd_init, | |
2203 | .fini = &evergreen_hpd_fini, | |
2204 | .sense = &evergreen_hpd_sense, | |
2205 | .set_polarity = &evergreen_hpd_set_polarity, | |
2206 | }, | |
2207 | .pm = { | |
2208 | .misc = &evergreen_pm_misc, | |
2209 | .prepare = &evergreen_pm_prepare, | |
2210 | .finish = &evergreen_pm_finish, | |
2211 | .init_profile = &sumo_pm_init_profile, | |
2212 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2213 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2214 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2215 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
2216 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
2217 | .get_pcie_lanes = NULL, | |
2218 | .set_pcie_lanes = NULL, | |
2219 | .set_clock_gating = NULL, | |
2220 | .set_uvd_clocks = &cik_set_uvd_clocks, | |
5ad6bf91 | 2221 | .set_vce_clocks = &cik_set_vce_clocks, |
286d9cc6 | 2222 | .get_temperature = &kv_get_temp, |
0672e27b | 2223 | }, |
41a524ab AD |
2224 | .dpm = { |
2225 | .init = &kv_dpm_init, | |
2226 | .setup_asic = &kv_dpm_setup_asic, | |
2227 | .enable = &kv_dpm_enable, | |
d8852c34 | 2228 | .late_enable = &kv_dpm_late_enable, |
41a524ab AD |
2229 | .disable = &kv_dpm_disable, |
2230 | .pre_set_power_state = &kv_dpm_pre_set_power_state, | |
2231 | .set_power_state = &kv_dpm_set_power_state, | |
2232 | .post_set_power_state = &kv_dpm_post_set_power_state, | |
2233 | .display_configuration_changed = &kv_dpm_display_configuration_changed, | |
2234 | .fini = &kv_dpm_fini, | |
2235 | .get_sclk = &kv_dpm_get_sclk, | |
2236 | .get_mclk = &kv_dpm_get_mclk, | |
2237 | .print_power_state = &kv_dpm_print_power_state, | |
ae3e40e8 | 2238 | .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, |
2b4c8022 | 2239 | .force_performance_level = &kv_dpm_force_performance_level, |
77df508a | 2240 | .powergate_uvd = &kv_dpm_powergate_uvd, |
b7a5ae97 | 2241 | .enable_bapm = &kv_dpm_enable_bapm, |
41a524ab | 2242 | }, |
0672e27b | 2243 | .pflip = { |
0672e27b | 2244 | .page_flip = &evergreen_page_flip, |
157fa14d | 2245 | .page_flip_pending = &evergreen_page_flip_pending, |
0672e27b AD |
2246 | }, |
2247 | }; | |
2248 | ||
abf1dc67 AD |
2249 | /** |
2250 | * radeon_asic_init - register asic specific callbacks | |
2251 | * | |
2252 | * @rdev: radeon device pointer | |
2253 | * | |
2254 | * Registers the appropriate asic specific callbacks for each | |
2255 | * chip family. Also sets other asics specific info like the number | |
2256 | * of crtcs and the register aperture accessors (all asics). | |
2257 | * Returns 0 for success. | |
2258 | */ | |
0a10c851 DV |
2259 | int radeon_asic_init(struct radeon_device *rdev) |
2260 | { | |
2261 | radeon_register_accessor_init(rdev); | |
ba7e05e9 AD |
2262 | |
2263 | /* set the number of crtcs */ | |
2264 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
2265 | rdev->num_crtc = 1; | |
2266 | else | |
2267 | rdev->num_crtc = 2; | |
2268 | ||
948bee3f AD |
2269 | rdev->has_uvd = false; |
2270 | ||
0a10c851 DV |
2271 | switch (rdev->family) { |
2272 | case CHIP_R100: | |
2273 | case CHIP_RV100: | |
2274 | case CHIP_RS100: | |
2275 | case CHIP_RV200: | |
2276 | case CHIP_RS200: | |
2277 | rdev->asic = &r100_asic; | |
2278 | break; | |
2279 | case CHIP_R200: | |
2280 | case CHIP_RV250: | |
2281 | case CHIP_RS300: | |
2282 | case CHIP_RV280: | |
2283 | rdev->asic = &r200_asic; | |
2284 | break; | |
2285 | case CHIP_R300: | |
2286 | case CHIP_R350: | |
2287 | case CHIP_RV350: | |
2288 | case CHIP_RV380: | |
2289 | if (rdev->flags & RADEON_IS_PCIE) | |
2290 | rdev->asic = &r300_asic_pcie; | |
2291 | else | |
2292 | rdev->asic = &r300_asic; | |
2293 | break; | |
2294 | case CHIP_R420: | |
2295 | case CHIP_R423: | |
2296 | case CHIP_RV410: | |
2297 | rdev->asic = &r420_asic; | |
07bb084c AD |
2298 | /* handle macs */ |
2299 | if (rdev->bios == NULL) { | |
798bcf73 AD |
2300 | rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; |
2301 | rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; | |
2302 | rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; | |
2303 | rdev->asic->pm.set_memory_clock = NULL; | |
37e9b6a6 | 2304 | rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; |
07bb084c | 2305 | } |
0a10c851 DV |
2306 | break; |
2307 | case CHIP_RS400: | |
2308 | case CHIP_RS480: | |
2309 | rdev->asic = &rs400_asic; | |
2310 | break; | |
2311 | case CHIP_RS600: | |
2312 | rdev->asic = &rs600_asic; | |
2313 | break; | |
2314 | case CHIP_RS690: | |
2315 | case CHIP_RS740: | |
2316 | rdev->asic = &rs690_asic; | |
2317 | break; | |
2318 | case CHIP_RV515: | |
2319 | rdev->asic = &rv515_asic; | |
2320 | break; | |
2321 | case CHIP_R520: | |
2322 | case CHIP_RV530: | |
2323 | case CHIP_RV560: | |
2324 | case CHIP_RV570: | |
2325 | case CHIP_R580: | |
2326 | rdev->asic = &r520_asic; | |
2327 | break; | |
2328 | case CHIP_R600: | |
ca361b65 AD |
2329 | rdev->asic = &r600_asic; |
2330 | break; | |
0a10c851 DV |
2331 | case CHIP_RV610: |
2332 | case CHIP_RV630: | |
2333 | case CHIP_RV620: | |
2334 | case CHIP_RV635: | |
2335 | case CHIP_RV670: | |
ca361b65 AD |
2336 | rdev->asic = &rv6xx_asic; |
2337 | rdev->has_uvd = true; | |
f47299c5 | 2338 | break; |
0a10c851 DV |
2339 | case CHIP_RS780: |
2340 | case CHIP_RS880: | |
f47299c5 | 2341 | rdev->asic = &rs780_asic; |
bdc99722 AD |
2342 | /* 760G/780V/880V don't have UVD */ |
2343 | if ((rdev->pdev->device == 0x9616)|| | |
2344 | (rdev->pdev->device == 0x9611)|| | |
2345 | (rdev->pdev->device == 0x9613)|| | |
2346 | (rdev->pdev->device == 0x9711)|| | |
2347 | (rdev->pdev->device == 0x9713)) | |
2348 | rdev->has_uvd = false; | |
2349 | else | |
2350 | rdev->has_uvd = true; | |
0a10c851 DV |
2351 | break; |
2352 | case CHIP_RV770: | |
2353 | case CHIP_RV730: | |
2354 | case CHIP_RV710: | |
2355 | case CHIP_RV740: | |
2356 | rdev->asic = &rv770_asic; | |
948bee3f | 2357 | rdev->has_uvd = true; |
0a10c851 DV |
2358 | break; |
2359 | case CHIP_CEDAR: | |
2360 | case CHIP_REDWOOD: | |
2361 | case CHIP_JUNIPER: | |
2362 | case CHIP_CYPRESS: | |
2363 | case CHIP_HEMLOCK: | |
ba7e05e9 AD |
2364 | /* set num crtcs */ |
2365 | if (rdev->family == CHIP_CEDAR) | |
2366 | rdev->num_crtc = 4; | |
2367 | else | |
2368 | rdev->num_crtc = 6; | |
0a10c851 | 2369 | rdev->asic = &evergreen_asic; |
948bee3f | 2370 | rdev->has_uvd = true; |
0a10c851 | 2371 | break; |
958261d1 | 2372 | case CHIP_PALM: |
89da5a37 AD |
2373 | case CHIP_SUMO: |
2374 | case CHIP_SUMO2: | |
958261d1 | 2375 | rdev->asic = &sumo_asic; |
948bee3f | 2376 | rdev->has_uvd = true; |
958261d1 | 2377 | break; |
a43b7665 AD |
2378 | case CHIP_BARTS: |
2379 | case CHIP_TURKS: | |
2380 | case CHIP_CAICOS: | |
ba7e05e9 AD |
2381 | /* set num crtcs */ |
2382 | if (rdev->family == CHIP_CAICOS) | |
2383 | rdev->num_crtc = 4; | |
2384 | else | |
2385 | rdev->num_crtc = 6; | |
a43b7665 | 2386 | rdev->asic = &btc_asic; |
948bee3f | 2387 | rdev->has_uvd = true; |
a43b7665 | 2388 | break; |
e3487629 AD |
2389 | case CHIP_CAYMAN: |
2390 | rdev->asic = &cayman_asic; | |
ba7e05e9 AD |
2391 | /* set num crtcs */ |
2392 | rdev->num_crtc = 6; | |
948bee3f | 2393 | rdev->has_uvd = true; |
e3487629 | 2394 | break; |
be63fe8c AD |
2395 | case CHIP_ARUBA: |
2396 | rdev->asic = &trinity_asic; | |
2397 | /* set num crtcs */ | |
2398 | rdev->num_crtc = 4; | |
948bee3f | 2399 | rdev->has_uvd = true; |
be63fe8c | 2400 | break; |
02779c08 AD |
2401 | case CHIP_TAHITI: |
2402 | case CHIP_PITCAIRN: | |
2403 | case CHIP_VERDE: | |
e737a14c | 2404 | case CHIP_OLAND: |
86a45cac | 2405 | case CHIP_HAINAN: |
02779c08 AD |
2406 | rdev->asic = &si_asic; |
2407 | /* set num crtcs */ | |
86a45cac AD |
2408 | if (rdev->family == CHIP_HAINAN) |
2409 | rdev->num_crtc = 0; | |
2410 | else if (rdev->family == CHIP_OLAND) | |
e737a14c AD |
2411 | rdev->num_crtc = 2; |
2412 | else | |
2413 | rdev->num_crtc = 6; | |
948bee3f AD |
2414 | if (rdev->family == CHIP_HAINAN) |
2415 | rdev->has_uvd = false; | |
2416 | else | |
2417 | rdev->has_uvd = true; | |
0116e1ef AD |
2418 | switch (rdev->family) { |
2419 | case CHIP_TAHITI: | |
2420 | rdev->cg_flags = | |
090f4b6a | 2421 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2422 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2423 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2424 | RADEON_CG_SUPPORT_GFX_CGLS | |
2425 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2426 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2427 | RADEON_CG_SUPPORT_MC_MGCG | | |
2428 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2429 | RADEON_CG_SUPPORT_BIF_LS | | |
2430 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2431 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2432 | RADEON_CG_SUPPORT_HDP_LS | | |
2433 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2434 | rdev->pg_flags = 0; | |
2435 | break; | |
2436 | case CHIP_PITCAIRN: | |
2437 | rdev->cg_flags = | |
090f4b6a | 2438 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2439 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2440 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2441 | RADEON_CG_SUPPORT_GFX_CGLS | |
2442 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2443 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2444 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2445 | RADEON_CG_SUPPORT_MC_LS | | |
2446 | RADEON_CG_SUPPORT_MC_MGCG | | |
2447 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2448 | RADEON_CG_SUPPORT_BIF_LS | | |
2449 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2450 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2451 | RADEON_CG_SUPPORT_HDP_LS | | |
2452 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2453 | rdev->pg_flags = 0; | |
2454 | break; | |
2455 | case CHIP_VERDE: | |
2456 | rdev->cg_flags = | |
090f4b6a | 2457 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2458 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2459 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2460 | RADEON_CG_SUPPORT_GFX_CGLS | |
2461 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2462 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2463 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2464 | RADEON_CG_SUPPORT_MC_LS | | |
2465 | RADEON_CG_SUPPORT_MC_MGCG | | |
2466 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2467 | RADEON_CG_SUPPORT_BIF_LS | | |
2468 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2469 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2470 | RADEON_CG_SUPPORT_HDP_LS | | |
2471 | RADEON_CG_SUPPORT_HDP_MGCG; | |
ca6ebb39 | 2472 | rdev->pg_flags = 0 | |
2b19d17f | 2473 | /*RADEON_PG_SUPPORT_GFX_PG | */ |
ca6ebb39 | 2474 | RADEON_PG_SUPPORT_SDMA; |
0116e1ef AD |
2475 | break; |
2476 | case CHIP_OLAND: | |
2477 | rdev->cg_flags = | |
090f4b6a | 2478 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2479 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2480 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2481 | RADEON_CG_SUPPORT_GFX_CGLS | |
2482 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2483 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2484 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2485 | RADEON_CG_SUPPORT_MC_LS | | |
2486 | RADEON_CG_SUPPORT_MC_MGCG | | |
2487 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2488 | RADEON_CG_SUPPORT_BIF_LS | | |
2489 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2490 | RADEON_CG_SUPPORT_HDP_LS | | |
2491 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2492 | rdev->pg_flags = 0; | |
2493 | break; | |
2494 | case CHIP_HAINAN: | |
2495 | rdev->cg_flags = | |
090f4b6a | 2496 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2497 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2498 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2499 | RADEON_CG_SUPPORT_GFX_CGLS | |
2500 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2501 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2502 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2503 | RADEON_CG_SUPPORT_MC_LS | | |
2504 | RADEON_CG_SUPPORT_MC_MGCG | | |
2505 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2506 | RADEON_CG_SUPPORT_BIF_LS | | |
2507 | RADEON_CG_SUPPORT_HDP_LS | | |
2508 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2509 | rdev->pg_flags = 0; | |
2510 | break; | |
2511 | default: | |
2512 | rdev->cg_flags = 0; | |
2513 | rdev->pg_flags = 0; | |
2514 | break; | |
2515 | } | |
02779c08 | 2516 | break; |
0672e27b | 2517 | case CHIP_BONAIRE: |
41971b37 | 2518 | case CHIP_HAWAII: |
0672e27b AD |
2519 | rdev->asic = &ci_asic; |
2520 | rdev->num_crtc = 6; | |
22c775ce | 2521 | rdev->has_uvd = true; |
41971b37 AD |
2522 | if (rdev->family == CHIP_BONAIRE) { |
2523 | rdev->cg_flags = | |
2524 | RADEON_CG_SUPPORT_GFX_MGCG | | |
2525 | RADEON_CG_SUPPORT_GFX_MGLS | | |
6960948d | 2526 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
41971b37 AD |
2527 | RADEON_CG_SUPPORT_GFX_CGLS | |
2528 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2529 | RADEON_CG_SUPPORT_GFX_CGTS_LS | | |
2530 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2531 | RADEON_CG_SUPPORT_MC_LS | | |
2532 | RADEON_CG_SUPPORT_MC_MGCG | | |
2533 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2534 | RADEON_CG_SUPPORT_SDMA_LS | | |
2535 | RADEON_CG_SUPPORT_BIF_LS | | |
2536 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2537 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2538 | RADEON_CG_SUPPORT_HDP_LS | | |
2539 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2540 | rdev->pg_flags = 0; | |
2541 | } else { | |
2542 | rdev->cg_flags = | |
2543 | RADEON_CG_SUPPORT_GFX_MGCG | | |
2544 | RADEON_CG_SUPPORT_GFX_MGLS | | |
6960948d | 2545 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
41971b37 AD |
2546 | RADEON_CG_SUPPORT_GFX_CGLS | |
2547 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2548 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2549 | RADEON_CG_SUPPORT_MC_LS | | |
2550 | RADEON_CG_SUPPORT_MC_MGCG | | |
2551 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2552 | RADEON_CG_SUPPORT_SDMA_LS | | |
2553 | RADEON_CG_SUPPORT_BIF_LS | | |
2554 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2555 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2556 | RADEON_CG_SUPPORT_HDP_LS | | |
2557 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2558 | rdev->pg_flags = 0; | |
2559 | } | |
0672e27b AD |
2560 | break; |
2561 | case CHIP_KAVERI: | |
2562 | case CHIP_KABINI: | |
b0a9f22a | 2563 | case CHIP_MULLINS: |
0672e27b AD |
2564 | rdev->asic = &kv_asic; |
2565 | /* set num crtcs */ | |
473359bc | 2566 | if (rdev->family == CHIP_KAVERI) { |
0672e27b | 2567 | rdev->num_crtc = 4; |
473359bc | 2568 | rdev->cg_flags = |
773dc10a | 2569 | RADEON_CG_SUPPORT_GFX_MGCG | |
473359bc | 2570 | RADEON_CG_SUPPORT_GFX_MGLS | |
6960948d | 2571 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
473359bc AD |
2572 | RADEON_CG_SUPPORT_GFX_CGLS | |
2573 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2574 | RADEON_CG_SUPPORT_GFX_CGTS_LS | | |
2575 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2576 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2577 | RADEON_CG_SUPPORT_SDMA_LS | | |
2578 | RADEON_CG_SUPPORT_BIF_LS | | |
2579 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2580 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2581 | RADEON_CG_SUPPORT_HDP_LS | | |
2582 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2583 | rdev->pg_flags = 0; | |
2b19d17f | 2584 | /*RADEON_PG_SUPPORT_GFX_PG | |
473359bc AD |
2585 | RADEON_PG_SUPPORT_GFX_SMG | |
2586 | RADEON_PG_SUPPORT_GFX_DMG | | |
2587 | RADEON_PG_SUPPORT_UVD | | |
2588 | RADEON_PG_SUPPORT_VCE | | |
2589 | RADEON_PG_SUPPORT_CP | | |
2590 | RADEON_PG_SUPPORT_GDS | | |
2591 | RADEON_PG_SUPPORT_RLC_SMU_HS | | |
2592 | RADEON_PG_SUPPORT_ACP | | |
2593 | RADEON_PG_SUPPORT_SAMU;*/ | |
2594 | } else { | |
0672e27b | 2595 | rdev->num_crtc = 2; |
473359bc | 2596 | rdev->cg_flags = |
773dc10a | 2597 | RADEON_CG_SUPPORT_GFX_MGCG | |
473359bc | 2598 | RADEON_CG_SUPPORT_GFX_MGLS | |
6960948d | 2599 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
473359bc AD |
2600 | RADEON_CG_SUPPORT_GFX_CGLS | |
2601 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2602 | RADEON_CG_SUPPORT_GFX_CGTS_LS | | |
2603 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2604 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2605 | RADEON_CG_SUPPORT_SDMA_LS | | |
2606 | RADEON_CG_SUPPORT_BIF_LS | | |
2607 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2608 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2609 | RADEON_CG_SUPPORT_HDP_LS | | |
2610 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2611 | rdev->pg_flags = 0; | |
2b19d17f | 2612 | /*RADEON_PG_SUPPORT_GFX_PG | |
473359bc AD |
2613 | RADEON_PG_SUPPORT_GFX_SMG | |
2614 | RADEON_PG_SUPPORT_UVD | | |
2615 | RADEON_PG_SUPPORT_VCE | | |
2616 | RADEON_PG_SUPPORT_CP | | |
2617 | RADEON_PG_SUPPORT_GDS | | |
2618 | RADEON_PG_SUPPORT_RLC_SMU_HS | | |
2619 | RADEON_PG_SUPPORT_SAMU;*/ | |
2620 | } | |
22c775ce | 2621 | rdev->has_uvd = true; |
0672e27b | 2622 | break; |
0a10c851 DV |
2623 | default: |
2624 | /* FIXME: not supported yet */ | |
2625 | return -EINVAL; | |
2626 | } | |
2627 | ||
2628 | if (rdev->flags & RADEON_IS_IGP) { | |
798bcf73 AD |
2629 | rdev->asic->pm.get_memory_clock = NULL; |
2630 | rdev->asic->pm.set_memory_clock = NULL; | |
0a10c851 DV |
2631 | } |
2632 | ||
2633 | return 0; | |
2634 | } | |
2635 |