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0a10c851 DV |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | ||
29 | #include <linux/console.h> | |
30 | #include <drm/drmP.h> | |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
33 | #include <linux/vgaarb.h> | |
34 | #include <linux/vga_switcheroo.h> | |
35 | #include "radeon_reg.h" | |
36 | #include "radeon.h" | |
37 | #include "radeon_asic.h" | |
38 | #include "atom.h" | |
39 | ||
40 | /* | |
41 | * Registers accessors functions. | |
42 | */ | |
43 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) | |
44 | { | |
45 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
46 | BUG_ON(1); | |
47 | return 0; | |
48 | } | |
49 | ||
50 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
51 | { | |
52 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
53 | reg, v); | |
54 | BUG_ON(1); | |
55 | } | |
56 | ||
57 | static void radeon_register_accessor_init(struct radeon_device *rdev) | |
58 | { | |
59 | rdev->mc_rreg = &radeon_invalid_rreg; | |
60 | rdev->mc_wreg = &radeon_invalid_wreg; | |
61 | rdev->pll_rreg = &radeon_invalid_rreg; | |
62 | rdev->pll_wreg = &radeon_invalid_wreg; | |
63 | rdev->pciep_rreg = &radeon_invalid_rreg; | |
64 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
65 | ||
66 | /* Don't change order as we are overridding accessor. */ | |
67 | if (rdev->family < CHIP_RV515) { | |
68 | rdev->pcie_reg_mask = 0xff; | |
69 | } else { | |
70 | rdev->pcie_reg_mask = 0x7ff; | |
71 | } | |
72 | /* FIXME: not sure here */ | |
73 | if (rdev->family <= CHIP_R580) { | |
74 | rdev->pll_rreg = &r100_pll_rreg; | |
75 | rdev->pll_wreg = &r100_pll_wreg; | |
76 | } | |
77 | if (rdev->family >= CHIP_R420) { | |
78 | rdev->mc_rreg = &r420_mc_rreg; | |
79 | rdev->mc_wreg = &r420_mc_wreg; | |
80 | } | |
81 | if (rdev->family >= CHIP_RV515) { | |
82 | rdev->mc_rreg = &rv515_mc_rreg; | |
83 | rdev->mc_wreg = &rv515_mc_wreg; | |
84 | } | |
85 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
86 | rdev->mc_rreg = &rs400_mc_rreg; | |
87 | rdev->mc_wreg = &rs400_mc_wreg; | |
88 | } | |
89 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
90 | rdev->mc_rreg = &rs690_mc_rreg; | |
91 | rdev->mc_wreg = &rs690_mc_wreg; | |
92 | } | |
93 | if (rdev->family == CHIP_RS600) { | |
94 | rdev->mc_rreg = &rs600_mc_rreg; | |
95 | rdev->mc_wreg = &rs600_mc_wreg; | |
96 | } | |
b4df8be1 | 97 | if (rdev->family >= CHIP_R600) { |
0a10c851 DV |
98 | rdev->pciep_rreg = &r600_pciep_rreg; |
99 | rdev->pciep_wreg = &r600_pciep_wreg; | |
100 | } | |
101 | } | |
102 | ||
103 | ||
104 | /* helper to disable agp */ | |
105 | void radeon_agp_disable(struct radeon_device *rdev) | |
106 | { | |
107 | rdev->flags &= ~RADEON_IS_AGP; | |
108 | if (rdev->family >= CHIP_R600) { | |
109 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
110 | rdev->flags |= RADEON_IS_PCIE; | |
111 | } else if (rdev->family >= CHIP_RV515 || | |
112 | rdev->family == CHIP_RV380 || | |
113 | rdev->family == CHIP_RV410 || | |
114 | rdev->family == CHIP_R423) { | |
115 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
116 | rdev->flags |= RADEON_IS_PCIE; | |
117 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; | |
118 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; | |
119 | } else { | |
120 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
121 | rdev->flags |= RADEON_IS_PCI; | |
122 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; | |
123 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; | |
124 | } | |
125 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
126 | } | |
127 | ||
128 | /* | |
129 | * ASIC | |
130 | */ | |
48e7a5f1 DV |
131 | static struct radeon_asic r100_asic = { |
132 | .init = &r100_init, | |
133 | .fini = &r100_fini, | |
134 | .suspend = &r100_suspend, | |
135 | .resume = &r100_resume, | |
136 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 137 | .gpu_is_lockup = &r100_gpu_is_lockup, |
a2d07b74 | 138 | .asic_reset = &r100_asic_reset, |
48e7a5f1 DV |
139 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
140 | .gart_set_page = &r100_pci_gart_set_page, | |
48e7a5f1 DV |
141 | .ring_start = &r100_ring_start, |
142 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
143 | .ring = { |
144 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
145 | .ib_execute = &r100_ring_ib_execute, | |
146 | .emit_fence = &r100_fence_ring_emit, | |
147 | .emit_semaphore = &r100_semaphore_ring_emit, | |
148 | } | |
149 | }, | |
48e7a5f1 DV |
150 | .irq_set = &r100_irq_set, |
151 | .irq_process = &r100_irq_process, | |
152 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
153 | .cs_parse = &r100_cs_parse, |
154 | .copy_blit = &r100_copy_blit, | |
155 | .copy_dma = NULL, | |
156 | .copy = &r100_copy_blit, | |
157 | .get_engine_clock = &radeon_legacy_get_engine_clock, | |
158 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
159 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
160 | .set_memory_clock = NULL, | |
161 | .get_pcie_lanes = NULL, | |
162 | .set_pcie_lanes = NULL, | |
163 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
164 | .set_surface_reg = r100_set_surface_reg, | |
165 | .clear_surface_reg = r100_clear_surface_reg, | |
166 | .bandwidth_update = &r100_bandwidth_update, | |
901ea57d AD |
167 | .hpd = { |
168 | .init = &r100_hpd_init, | |
169 | .fini = &r100_hpd_fini, | |
170 | .sense = &r100_hpd_sense, | |
171 | .set_polarity = &r100_hpd_set_polarity, | |
172 | }, | |
48e7a5f1 | 173 | .ioctl_wait_idle = NULL, |
def9ba9c | 174 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
175 | .pm_misc = &r100_pm_misc, |
176 | .pm_prepare = &r100_pm_prepare, | |
177 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
178 | .pm_init_profile = &r100_pm_init_profile, |
179 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
180 | .pre_page_flip = &r100_pre_page_flip, |
181 | .page_flip = &r100_page_flip, | |
182 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 183 | .wait_for_vblank = &r100_wait_for_vblank, |
89e5181f | 184 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
48e7a5f1 DV |
185 | }; |
186 | ||
187 | static struct radeon_asic r200_asic = { | |
188 | .init = &r100_init, | |
189 | .fini = &r100_fini, | |
190 | .suspend = &r100_suspend, | |
191 | .resume = &r100_resume, | |
192 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 193 | .gpu_is_lockup = &r100_gpu_is_lockup, |
a2d07b74 | 194 | .asic_reset = &r100_asic_reset, |
48e7a5f1 DV |
195 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
196 | .gart_set_page = &r100_pci_gart_set_page, | |
48e7a5f1 DV |
197 | .ring_start = &r100_ring_start, |
198 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
199 | .ring = { |
200 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
201 | .ib_execute = &r100_ring_ib_execute, | |
202 | .emit_fence = &r100_fence_ring_emit, | |
203 | .emit_semaphore = &r100_semaphore_ring_emit, | |
204 | } | |
205 | }, | |
48e7a5f1 DV |
206 | .irq_set = &r100_irq_set, |
207 | .irq_process = &r100_irq_process, | |
208 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
209 | .cs_parse = &r100_cs_parse, |
210 | .copy_blit = &r100_copy_blit, | |
211 | .copy_dma = &r200_copy_dma, | |
212 | .copy = &r100_copy_blit, | |
213 | .get_engine_clock = &radeon_legacy_get_engine_clock, | |
214 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
215 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
216 | .set_memory_clock = NULL, | |
217 | .set_pcie_lanes = NULL, | |
218 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
219 | .set_surface_reg = r100_set_surface_reg, | |
220 | .clear_surface_reg = r100_clear_surface_reg, | |
221 | .bandwidth_update = &r100_bandwidth_update, | |
901ea57d AD |
222 | .hpd = { |
223 | .init = &r100_hpd_init, | |
224 | .fini = &r100_hpd_fini, | |
225 | .sense = &r100_hpd_sense, | |
226 | .set_polarity = &r100_hpd_set_polarity, | |
227 | }, | |
48e7a5f1 | 228 | .ioctl_wait_idle = NULL, |
def9ba9c | 229 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
230 | .pm_misc = &r100_pm_misc, |
231 | .pm_prepare = &r100_pm_prepare, | |
232 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
233 | .pm_init_profile = &r100_pm_init_profile, |
234 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
235 | .pre_page_flip = &r100_pre_page_flip, |
236 | .page_flip = &r100_page_flip, | |
237 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 238 | .wait_for_vblank = &r100_wait_for_vblank, |
89e5181f | 239 | .mc_wait_for_idle = &r100_mc_wait_for_idle, |
48e7a5f1 DV |
240 | }; |
241 | ||
242 | static struct radeon_asic r300_asic = { | |
243 | .init = &r300_init, | |
244 | .fini = &r300_fini, | |
245 | .suspend = &r300_suspend, | |
246 | .resume = &r300_resume, | |
247 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 248 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 249 | .asic_reset = &r300_asic_reset, |
48e7a5f1 DV |
250 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
251 | .gart_set_page = &r100_pci_gart_set_page, | |
48e7a5f1 DV |
252 | .ring_start = &r300_ring_start, |
253 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
254 | .ring = { |
255 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
256 | .ib_execute = &r100_ring_ib_execute, | |
257 | .emit_fence = &r300_fence_ring_emit, | |
258 | .emit_semaphore = &r100_semaphore_ring_emit, | |
259 | } | |
260 | }, | |
48e7a5f1 DV |
261 | .irq_set = &r100_irq_set, |
262 | .irq_process = &r100_irq_process, | |
263 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
264 | .cs_parse = &r300_cs_parse, |
265 | .copy_blit = &r100_copy_blit, | |
266 | .copy_dma = &r200_copy_dma, | |
267 | .copy = &r100_copy_blit, | |
268 | .get_engine_clock = &radeon_legacy_get_engine_clock, | |
269 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
270 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
271 | .set_memory_clock = NULL, | |
272 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
273 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
274 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
275 | .set_surface_reg = r100_set_surface_reg, | |
276 | .clear_surface_reg = r100_clear_surface_reg, | |
277 | .bandwidth_update = &r100_bandwidth_update, | |
901ea57d AD |
278 | .hpd = { |
279 | .init = &r100_hpd_init, | |
280 | .fini = &r100_hpd_fini, | |
281 | .sense = &r100_hpd_sense, | |
282 | .set_polarity = &r100_hpd_set_polarity, | |
283 | }, | |
48e7a5f1 | 284 | .ioctl_wait_idle = NULL, |
def9ba9c | 285 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
286 | .pm_misc = &r100_pm_misc, |
287 | .pm_prepare = &r100_pm_prepare, | |
288 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
289 | .pm_init_profile = &r100_pm_init_profile, |
290 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
291 | .pre_page_flip = &r100_pre_page_flip, |
292 | .page_flip = &r100_page_flip, | |
293 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 294 | .wait_for_vblank = &r100_wait_for_vblank, |
89e5181f | 295 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
48e7a5f1 DV |
296 | }; |
297 | ||
298 | static struct radeon_asic r300_asic_pcie = { | |
299 | .init = &r300_init, | |
300 | .fini = &r300_fini, | |
301 | .suspend = &r300_suspend, | |
302 | .resume = &r300_resume, | |
303 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 304 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 305 | .asic_reset = &r300_asic_reset, |
48e7a5f1 DV |
306 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
307 | .gart_set_page = &rv370_pcie_gart_set_page, | |
48e7a5f1 DV |
308 | .ring_start = &r300_ring_start, |
309 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
310 | .ring = { |
311 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
312 | .ib_execute = &r100_ring_ib_execute, | |
313 | .emit_fence = &r300_fence_ring_emit, | |
314 | .emit_semaphore = &r100_semaphore_ring_emit, | |
315 | } | |
316 | }, | |
48e7a5f1 DV |
317 | .irq_set = &r100_irq_set, |
318 | .irq_process = &r100_irq_process, | |
319 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
320 | .cs_parse = &r300_cs_parse, |
321 | .copy_blit = &r100_copy_blit, | |
322 | .copy_dma = &r200_copy_dma, | |
323 | .copy = &r100_copy_blit, | |
324 | .get_engine_clock = &radeon_legacy_get_engine_clock, | |
325 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
326 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
327 | .set_memory_clock = NULL, | |
328 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
329 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
330 | .set_surface_reg = r100_set_surface_reg, | |
331 | .clear_surface_reg = r100_clear_surface_reg, | |
332 | .bandwidth_update = &r100_bandwidth_update, | |
901ea57d AD |
333 | .hpd = { |
334 | .init = &r100_hpd_init, | |
335 | .fini = &r100_hpd_fini, | |
336 | .sense = &r100_hpd_sense, | |
337 | .set_polarity = &r100_hpd_set_polarity, | |
338 | }, | |
48e7a5f1 | 339 | .ioctl_wait_idle = NULL, |
def9ba9c | 340 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
341 | .pm_misc = &r100_pm_misc, |
342 | .pm_prepare = &r100_pm_prepare, | |
343 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
344 | .pm_init_profile = &r100_pm_init_profile, |
345 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
346 | .pre_page_flip = &r100_pre_page_flip, |
347 | .page_flip = &r100_page_flip, | |
348 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 349 | .wait_for_vblank = &r100_wait_for_vblank, |
89e5181f | 350 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
48e7a5f1 DV |
351 | }; |
352 | ||
353 | static struct radeon_asic r420_asic = { | |
354 | .init = &r420_init, | |
355 | .fini = &r420_fini, | |
356 | .suspend = &r420_suspend, | |
357 | .resume = &r420_resume, | |
358 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 359 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 360 | .asic_reset = &r300_asic_reset, |
48e7a5f1 DV |
361 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
362 | .gart_set_page = &rv370_pcie_gart_set_page, | |
48e7a5f1 DV |
363 | .ring_start = &r300_ring_start, |
364 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
365 | .ring = { |
366 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
367 | .ib_execute = &r100_ring_ib_execute, | |
368 | .emit_fence = &r300_fence_ring_emit, | |
369 | .emit_semaphore = &r100_semaphore_ring_emit, | |
370 | } | |
371 | }, | |
48e7a5f1 DV |
372 | .irq_set = &r100_irq_set, |
373 | .irq_process = &r100_irq_process, | |
374 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
375 | .cs_parse = &r300_cs_parse, |
376 | .copy_blit = &r100_copy_blit, | |
377 | .copy_dma = &r200_copy_dma, | |
378 | .copy = &r100_copy_blit, | |
379 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
380 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
381 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
382 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
383 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
384 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
385 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
386 | .set_surface_reg = r100_set_surface_reg, | |
387 | .clear_surface_reg = r100_clear_surface_reg, | |
388 | .bandwidth_update = &r100_bandwidth_update, | |
901ea57d AD |
389 | .hpd = { |
390 | .init = &r100_hpd_init, | |
391 | .fini = &r100_hpd_fini, | |
392 | .sense = &r100_hpd_sense, | |
393 | .set_polarity = &r100_hpd_set_polarity, | |
394 | }, | |
48e7a5f1 | 395 | .ioctl_wait_idle = NULL, |
def9ba9c | 396 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
397 | .pm_misc = &r100_pm_misc, |
398 | .pm_prepare = &r100_pm_prepare, | |
399 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
400 | .pm_init_profile = &r420_pm_init_profile, |
401 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
402 | .pre_page_flip = &r100_pre_page_flip, |
403 | .page_flip = &r100_page_flip, | |
404 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 405 | .wait_for_vblank = &r100_wait_for_vblank, |
89e5181f | 406 | .mc_wait_for_idle = &r300_mc_wait_for_idle, |
48e7a5f1 DV |
407 | }; |
408 | ||
409 | static struct radeon_asic rs400_asic = { | |
410 | .init = &rs400_init, | |
411 | .fini = &rs400_fini, | |
412 | .suspend = &rs400_suspend, | |
413 | .resume = &rs400_resume, | |
414 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 415 | .gpu_is_lockup = &r300_gpu_is_lockup, |
a2d07b74 | 416 | .asic_reset = &r300_asic_reset, |
48e7a5f1 DV |
417 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
418 | .gart_set_page = &rs400_gart_set_page, | |
48e7a5f1 DV |
419 | .ring_start = &r300_ring_start, |
420 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
421 | .ring = { |
422 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
423 | .ib_execute = &r100_ring_ib_execute, | |
424 | .emit_fence = &r300_fence_ring_emit, | |
425 | .emit_semaphore = &r100_semaphore_ring_emit, | |
426 | } | |
427 | }, | |
48e7a5f1 DV |
428 | .irq_set = &r100_irq_set, |
429 | .irq_process = &r100_irq_process, | |
430 | .get_vblank_counter = &r100_get_vblank_counter, | |
48e7a5f1 DV |
431 | .cs_parse = &r300_cs_parse, |
432 | .copy_blit = &r100_copy_blit, | |
433 | .copy_dma = &r200_copy_dma, | |
434 | .copy = &r100_copy_blit, | |
435 | .get_engine_clock = &radeon_legacy_get_engine_clock, | |
436 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
437 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
438 | .set_memory_clock = NULL, | |
439 | .get_pcie_lanes = NULL, | |
440 | .set_pcie_lanes = NULL, | |
441 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
442 | .set_surface_reg = r100_set_surface_reg, | |
443 | .clear_surface_reg = r100_clear_surface_reg, | |
444 | .bandwidth_update = &r100_bandwidth_update, | |
901ea57d AD |
445 | .hpd = { |
446 | .init = &r100_hpd_init, | |
447 | .fini = &r100_hpd_fini, | |
448 | .sense = &r100_hpd_sense, | |
449 | .set_polarity = &r100_hpd_set_polarity, | |
450 | }, | |
48e7a5f1 | 451 | .ioctl_wait_idle = NULL, |
def9ba9c | 452 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
453 | .pm_misc = &r100_pm_misc, |
454 | .pm_prepare = &r100_pm_prepare, | |
455 | .pm_finish = &r100_pm_finish, | |
ce8f5370 AD |
456 | .pm_init_profile = &r100_pm_init_profile, |
457 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
458 | .pre_page_flip = &r100_pre_page_flip, |
459 | .page_flip = &r100_page_flip, | |
460 | .post_page_flip = &r100_post_page_flip, | |
3ae19b75 | 461 | .wait_for_vblank = &r100_wait_for_vblank, |
89e5181f | 462 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, |
48e7a5f1 DV |
463 | }; |
464 | ||
465 | static struct radeon_asic rs600_asic = { | |
466 | .init = &rs600_init, | |
467 | .fini = &rs600_fini, | |
468 | .suspend = &rs600_suspend, | |
469 | .resume = &rs600_resume, | |
470 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 471 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 472 | .asic_reset = &rs600_asic_reset, |
48e7a5f1 DV |
473 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
474 | .gart_set_page = &rs600_gart_set_page, | |
48e7a5f1 DV |
475 | .ring_start = &r300_ring_start, |
476 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
477 | .ring = { |
478 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
479 | .ib_execute = &r100_ring_ib_execute, | |
480 | .emit_fence = &r300_fence_ring_emit, | |
481 | .emit_semaphore = &r100_semaphore_ring_emit, | |
482 | } | |
483 | }, | |
48e7a5f1 DV |
484 | .irq_set = &rs600_irq_set, |
485 | .irq_process = &rs600_irq_process, | |
486 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
487 | .cs_parse = &r300_cs_parse, |
488 | .copy_blit = &r100_copy_blit, | |
489 | .copy_dma = &r200_copy_dma, | |
490 | .copy = &r100_copy_blit, | |
491 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
492 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
493 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
494 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
495 | .get_pcie_lanes = NULL, | |
496 | .set_pcie_lanes = NULL, | |
497 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
498 | .set_surface_reg = r100_set_surface_reg, | |
499 | .clear_surface_reg = r100_clear_surface_reg, | |
500 | .bandwidth_update = &rs600_bandwidth_update, | |
901ea57d AD |
501 | .hpd = { |
502 | .init = &rs600_hpd_init, | |
503 | .fini = &rs600_hpd_fini, | |
504 | .sense = &rs600_hpd_sense, | |
505 | .set_polarity = &rs600_hpd_set_polarity, | |
506 | }, | |
48e7a5f1 | 507 | .ioctl_wait_idle = NULL, |
def9ba9c | 508 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
509 | .pm_misc = &rs600_pm_misc, |
510 | .pm_prepare = &rs600_pm_prepare, | |
511 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
512 | .pm_init_profile = &r420_pm_init_profile, |
513 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
514 | .pre_page_flip = &rs600_pre_page_flip, |
515 | .page_flip = &rs600_page_flip, | |
516 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 517 | .wait_for_vblank = &avivo_wait_for_vblank, |
89e5181f | 518 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, |
48e7a5f1 DV |
519 | }; |
520 | ||
521 | static struct radeon_asic rs690_asic = { | |
522 | .init = &rs690_init, | |
523 | .fini = &rs690_fini, | |
524 | .suspend = &rs690_suspend, | |
525 | .resume = &rs690_resume, | |
526 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 527 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 528 | .asic_reset = &rs600_asic_reset, |
48e7a5f1 DV |
529 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
530 | .gart_set_page = &rs400_gart_set_page, | |
48e7a5f1 DV |
531 | .ring_start = &r300_ring_start, |
532 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
533 | .ring = { |
534 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
535 | .ib_execute = &r100_ring_ib_execute, | |
536 | .emit_fence = &r300_fence_ring_emit, | |
537 | .emit_semaphore = &r100_semaphore_ring_emit, | |
538 | } | |
539 | }, | |
48e7a5f1 DV |
540 | .irq_set = &rs600_irq_set, |
541 | .irq_process = &rs600_irq_process, | |
542 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
543 | .cs_parse = &r300_cs_parse, |
544 | .copy_blit = &r100_copy_blit, | |
545 | .copy_dma = &r200_copy_dma, | |
546 | .copy = &r200_copy_dma, | |
547 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
548 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
549 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
550 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
551 | .get_pcie_lanes = NULL, | |
552 | .set_pcie_lanes = NULL, | |
553 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
554 | .set_surface_reg = r100_set_surface_reg, | |
555 | .clear_surface_reg = r100_clear_surface_reg, | |
556 | .bandwidth_update = &rs690_bandwidth_update, | |
901ea57d AD |
557 | .hpd = { |
558 | .init = &rs600_hpd_init, | |
559 | .fini = &rs600_hpd_fini, | |
560 | .sense = &rs600_hpd_sense, | |
561 | .set_polarity = &rs600_hpd_set_polarity, | |
562 | }, | |
48e7a5f1 | 563 | .ioctl_wait_idle = NULL, |
def9ba9c | 564 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
565 | .pm_misc = &rs600_pm_misc, |
566 | .pm_prepare = &rs600_pm_prepare, | |
567 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
568 | .pm_init_profile = &r420_pm_init_profile, |
569 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
570 | .pre_page_flip = &rs600_pre_page_flip, |
571 | .page_flip = &rs600_page_flip, | |
572 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 573 | .wait_for_vblank = &avivo_wait_for_vblank, |
89e5181f | 574 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, |
48e7a5f1 DV |
575 | }; |
576 | ||
577 | static struct radeon_asic rv515_asic = { | |
578 | .init = &rv515_init, | |
579 | .fini = &rv515_fini, | |
580 | .suspend = &rv515_suspend, | |
581 | .resume = &rv515_resume, | |
582 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 583 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 584 | .asic_reset = &rs600_asic_reset, |
48e7a5f1 DV |
585 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
586 | .gart_set_page = &rv370_pcie_gart_set_page, | |
48e7a5f1 DV |
587 | .ring_start = &rv515_ring_start, |
588 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
589 | .ring = { |
590 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
591 | .ib_execute = &r100_ring_ib_execute, | |
592 | .emit_fence = &r300_fence_ring_emit, | |
593 | .emit_semaphore = &r100_semaphore_ring_emit, | |
594 | } | |
595 | }, | |
48e7a5f1 DV |
596 | .irq_set = &rs600_irq_set, |
597 | .irq_process = &rs600_irq_process, | |
598 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
599 | .cs_parse = &r300_cs_parse, |
600 | .copy_blit = &r100_copy_blit, | |
601 | .copy_dma = &r200_copy_dma, | |
602 | .copy = &r100_copy_blit, | |
603 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
604 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
605 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
606 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
607 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
608 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
609 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
610 | .set_surface_reg = r100_set_surface_reg, | |
611 | .clear_surface_reg = r100_clear_surface_reg, | |
612 | .bandwidth_update = &rv515_bandwidth_update, | |
901ea57d AD |
613 | .hpd = { |
614 | .init = &rs600_hpd_init, | |
615 | .fini = &rs600_hpd_fini, | |
616 | .sense = &rs600_hpd_sense, | |
617 | .set_polarity = &rs600_hpd_set_polarity, | |
618 | }, | |
48e7a5f1 | 619 | .ioctl_wait_idle = NULL, |
def9ba9c | 620 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
621 | .pm_misc = &rs600_pm_misc, |
622 | .pm_prepare = &rs600_pm_prepare, | |
623 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
624 | .pm_init_profile = &r420_pm_init_profile, |
625 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
626 | .pre_page_flip = &rs600_pre_page_flip, |
627 | .page_flip = &rs600_page_flip, | |
628 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 629 | .wait_for_vblank = &avivo_wait_for_vblank, |
89e5181f | 630 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, |
48e7a5f1 DV |
631 | }; |
632 | ||
633 | static struct radeon_asic r520_asic = { | |
634 | .init = &r520_init, | |
635 | .fini = &rv515_fini, | |
636 | .suspend = &rv515_suspend, | |
637 | .resume = &r520_resume, | |
638 | .vga_set_state = &r100_vga_set_state, | |
225758d8 | 639 | .gpu_is_lockup = &r300_gpu_is_lockup, |
90aca4d2 | 640 | .asic_reset = &rs600_asic_reset, |
48e7a5f1 DV |
641 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
642 | .gart_set_page = &rv370_pcie_gart_set_page, | |
48e7a5f1 DV |
643 | .ring_start = &rv515_ring_start, |
644 | .ring_test = &r100_ring_test, | |
4c87bc26 CK |
645 | .ring = { |
646 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
647 | .ib_execute = &r100_ring_ib_execute, | |
648 | .emit_fence = &r300_fence_ring_emit, | |
649 | .emit_semaphore = &r100_semaphore_ring_emit, | |
650 | } | |
651 | }, | |
48e7a5f1 DV |
652 | .irq_set = &rs600_irq_set, |
653 | .irq_process = &rs600_irq_process, | |
654 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
655 | .cs_parse = &r300_cs_parse, |
656 | .copy_blit = &r100_copy_blit, | |
657 | .copy_dma = &r200_copy_dma, | |
658 | .copy = &r100_copy_blit, | |
659 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
660 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
661 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
662 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
663 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
664 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
665 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
666 | .set_surface_reg = r100_set_surface_reg, | |
667 | .clear_surface_reg = r100_clear_surface_reg, | |
668 | .bandwidth_update = &rv515_bandwidth_update, | |
901ea57d AD |
669 | .hpd = { |
670 | .init = &rs600_hpd_init, | |
671 | .fini = &rs600_hpd_fini, | |
672 | .sense = &rs600_hpd_sense, | |
673 | .set_polarity = &rs600_hpd_set_polarity, | |
674 | }, | |
48e7a5f1 | 675 | .ioctl_wait_idle = NULL, |
def9ba9c | 676 | .gui_idle = &r100_gui_idle, |
49e02b73 AD |
677 | .pm_misc = &rs600_pm_misc, |
678 | .pm_prepare = &rs600_pm_prepare, | |
679 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
680 | .pm_init_profile = &r420_pm_init_profile, |
681 | .pm_get_dynpm_state = &r100_pm_get_dynpm_state, | |
6f34be50 AD |
682 | .pre_page_flip = &rs600_pre_page_flip, |
683 | .page_flip = &rs600_page_flip, | |
684 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 685 | .wait_for_vblank = &avivo_wait_for_vblank, |
89e5181f | 686 | .mc_wait_for_idle = &r520_mc_wait_for_idle, |
48e7a5f1 DV |
687 | }; |
688 | ||
689 | static struct radeon_asic r600_asic = { | |
690 | .init = &r600_init, | |
691 | .fini = &r600_fini, | |
692 | .suspend = &r600_suspend, | |
693 | .resume = &r600_resume, | |
48e7a5f1 | 694 | .vga_set_state = &r600_vga_set_state, |
225758d8 | 695 | .gpu_is_lockup = &r600_gpu_is_lockup, |
a2d07b74 | 696 | .asic_reset = &r600_asic_reset, |
48e7a5f1 DV |
697 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
698 | .gart_set_page = &rs600_gart_set_page, | |
699 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
700 | .ring = { |
701 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
702 | .ib_execute = &r600_ring_ib_execute, | |
703 | .emit_fence = &r600_fence_ring_emit, | |
704 | .emit_semaphore = &r600_semaphore_ring_emit, | |
705 | } | |
706 | }, | |
48e7a5f1 DV |
707 | .irq_set = &r600_irq_set, |
708 | .irq_process = &r600_irq_process, | |
709 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
710 | .cs_parse = &r600_cs_parse, |
711 | .copy_blit = &r600_copy_blit, | |
20633442 | 712 | .copy_dma = NULL, |
48e7a5f1 DV |
713 | .copy = &r600_copy_blit, |
714 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
715 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
716 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
717 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
3313e3d4 AD |
718 | .get_pcie_lanes = &r600_get_pcie_lanes, |
719 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
48e7a5f1 DV |
720 | .set_clock_gating = NULL, |
721 | .set_surface_reg = r600_set_surface_reg, | |
722 | .clear_surface_reg = r600_clear_surface_reg, | |
723 | .bandwidth_update = &rv515_bandwidth_update, | |
901ea57d AD |
724 | .hpd = { |
725 | .init = &r600_hpd_init, | |
726 | .fini = &r600_hpd_fini, | |
727 | .sense = &r600_hpd_sense, | |
728 | .set_polarity = &r600_hpd_set_polarity, | |
729 | }, | |
48e7a5f1 | 730 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
def9ba9c | 731 | .gui_idle = &r600_gui_idle, |
49e02b73 AD |
732 | .pm_misc = &r600_pm_misc, |
733 | .pm_prepare = &rs600_pm_prepare, | |
734 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
735 | .pm_init_profile = &r600_pm_init_profile, |
736 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
6f34be50 AD |
737 | .pre_page_flip = &rs600_pre_page_flip, |
738 | .page_flip = &rs600_page_flip, | |
739 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 740 | .wait_for_vblank = &avivo_wait_for_vblank, |
89e5181f | 741 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
48e7a5f1 DV |
742 | }; |
743 | ||
f47299c5 AD |
744 | static struct radeon_asic rs780_asic = { |
745 | .init = &r600_init, | |
746 | .fini = &r600_fini, | |
747 | .suspend = &r600_suspend, | |
748 | .resume = &r600_resume, | |
90aca4d2 | 749 | .gpu_is_lockup = &r600_gpu_is_lockup, |
f47299c5 | 750 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 751 | .asic_reset = &r600_asic_reset, |
f47299c5 AD |
752 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
753 | .gart_set_page = &rs600_gart_set_page, | |
754 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
755 | .ring = { |
756 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
757 | .ib_execute = &r600_ring_ib_execute, | |
758 | .emit_fence = &r600_fence_ring_emit, | |
759 | .emit_semaphore = &r600_semaphore_ring_emit, | |
760 | } | |
761 | }, | |
f47299c5 AD |
762 | .irq_set = &r600_irq_set, |
763 | .irq_process = &r600_irq_process, | |
764 | .get_vblank_counter = &rs600_get_vblank_counter, | |
f47299c5 AD |
765 | .cs_parse = &r600_cs_parse, |
766 | .copy_blit = &r600_copy_blit, | |
20633442 | 767 | .copy_dma = NULL, |
f47299c5 AD |
768 | .copy = &r600_copy_blit, |
769 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
770 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
771 | .get_memory_clock = NULL, | |
772 | .set_memory_clock = NULL, | |
773 | .get_pcie_lanes = NULL, | |
774 | .set_pcie_lanes = NULL, | |
775 | .set_clock_gating = NULL, | |
776 | .set_surface_reg = r600_set_surface_reg, | |
777 | .clear_surface_reg = r600_clear_surface_reg, | |
778 | .bandwidth_update = &rs690_bandwidth_update, | |
901ea57d AD |
779 | .hpd = { |
780 | .init = &r600_hpd_init, | |
781 | .fini = &r600_hpd_fini, | |
782 | .sense = &r600_hpd_sense, | |
783 | .set_polarity = &r600_hpd_set_polarity, | |
784 | }, | |
f47299c5 | 785 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
def9ba9c | 786 | .gui_idle = &r600_gui_idle, |
49e02b73 AD |
787 | .pm_misc = &r600_pm_misc, |
788 | .pm_prepare = &rs600_pm_prepare, | |
789 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
790 | .pm_init_profile = &rs780_pm_init_profile, |
791 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
6f34be50 AD |
792 | .pre_page_flip = &rs600_pre_page_flip, |
793 | .page_flip = &rs600_page_flip, | |
794 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 795 | .wait_for_vblank = &avivo_wait_for_vblank, |
89e5181f | 796 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
f47299c5 AD |
797 | }; |
798 | ||
48e7a5f1 DV |
799 | static struct radeon_asic rv770_asic = { |
800 | .init = &rv770_init, | |
801 | .fini = &rv770_fini, | |
802 | .suspend = &rv770_suspend, | |
803 | .resume = &rv770_resume, | |
a2d07b74 | 804 | .asic_reset = &r600_asic_reset, |
225758d8 | 805 | .gpu_is_lockup = &r600_gpu_is_lockup, |
48e7a5f1 DV |
806 | .vga_set_state = &r600_vga_set_state, |
807 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, | |
808 | .gart_set_page = &rs600_gart_set_page, | |
809 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
810 | .ring = { |
811 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
812 | .ib_execute = &r600_ring_ib_execute, | |
813 | .emit_fence = &r600_fence_ring_emit, | |
814 | .emit_semaphore = &r600_semaphore_ring_emit, | |
815 | } | |
816 | }, | |
48e7a5f1 DV |
817 | .irq_set = &r600_irq_set, |
818 | .irq_process = &r600_irq_process, | |
819 | .get_vblank_counter = &rs600_get_vblank_counter, | |
48e7a5f1 DV |
820 | .cs_parse = &r600_cs_parse, |
821 | .copy_blit = &r600_copy_blit, | |
20633442 | 822 | .copy_dma = NULL, |
48e7a5f1 DV |
823 | .copy = &r600_copy_blit, |
824 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
825 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
826 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
827 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
3313e3d4 AD |
828 | .get_pcie_lanes = &r600_get_pcie_lanes, |
829 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
48e7a5f1 DV |
830 | .set_clock_gating = &radeon_atom_set_clock_gating, |
831 | .set_surface_reg = r600_set_surface_reg, | |
832 | .clear_surface_reg = r600_clear_surface_reg, | |
833 | .bandwidth_update = &rv515_bandwidth_update, | |
901ea57d AD |
834 | .hpd = { |
835 | .init = &r600_hpd_init, | |
836 | .fini = &r600_hpd_fini, | |
837 | .sense = &r600_hpd_sense, | |
838 | .set_polarity = &r600_hpd_set_polarity, | |
839 | }, | |
48e7a5f1 | 840 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
def9ba9c | 841 | .gui_idle = &r600_gui_idle, |
49e02b73 AD |
842 | .pm_misc = &rv770_pm_misc, |
843 | .pm_prepare = &rs600_pm_prepare, | |
844 | .pm_finish = &rs600_pm_finish, | |
ce8f5370 AD |
845 | .pm_init_profile = &r600_pm_init_profile, |
846 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
6f34be50 AD |
847 | .pre_page_flip = &rs600_pre_page_flip, |
848 | .page_flip = &rv770_page_flip, | |
849 | .post_page_flip = &rs600_post_page_flip, | |
3ae19b75 | 850 | .wait_for_vblank = &avivo_wait_for_vblank, |
89e5181f | 851 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
48e7a5f1 DV |
852 | }; |
853 | ||
854 | static struct radeon_asic evergreen_asic = { | |
855 | .init = &evergreen_init, | |
856 | .fini = &evergreen_fini, | |
857 | .suspend = &evergreen_suspend, | |
858 | .resume = &evergreen_resume, | |
225758d8 | 859 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
a2d07b74 | 860 | .asic_reset = &evergreen_asic_reset, |
48e7a5f1 | 861 | .vga_set_state = &r600_vga_set_state, |
0fcdb61e | 862 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
48e7a5f1 | 863 | .gart_set_page = &rs600_gart_set_page, |
fe251e2f | 864 | .ring_test = &r600_ring_test, |
4c87bc26 CK |
865 | .ring = { |
866 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
867 | .ib_execute = &evergreen_ring_ib_execute, | |
868 | .emit_fence = &r600_fence_ring_emit, | |
869 | .emit_semaphore = &r600_semaphore_ring_emit, | |
870 | } | |
871 | }, | |
45f9a39b AD |
872 | .irq_set = &evergreen_irq_set, |
873 | .irq_process = &evergreen_irq_process, | |
874 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
cb5fcbd5 | 875 | .cs_parse = &evergreen_cs_parse, |
fb3d9e97 | 876 | .copy_blit = &r600_copy_blit, |
20633442 | 877 | .copy_dma = NULL, |
fb3d9e97 | 878 | .copy = &r600_copy_blit, |
48e7a5f1 DV |
879 | .get_engine_clock = &radeon_atom_get_engine_clock, |
880 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
881 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
882 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
3313e3d4 AD |
883 | .get_pcie_lanes = &r600_get_pcie_lanes, |
884 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
48e7a5f1 DV |
885 | .set_clock_gating = NULL, |
886 | .set_surface_reg = r600_set_surface_reg, | |
887 | .clear_surface_reg = r600_clear_surface_reg, | |
888 | .bandwidth_update = &evergreen_bandwidth_update, | |
901ea57d AD |
889 | .hpd = { |
890 | .init = &evergreen_hpd_init, | |
891 | .fini = &evergreen_hpd_fini, | |
892 | .sense = &evergreen_hpd_sense, | |
893 | .set_polarity = &evergreen_hpd_set_polarity, | |
894 | }, | |
97bfd0ac | 895 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
def9ba9c | 896 | .gui_idle = &r600_gui_idle, |
49e02b73 AD |
897 | .pm_misc = &evergreen_pm_misc, |
898 | .pm_prepare = &evergreen_pm_prepare, | |
899 | .pm_finish = &evergreen_pm_finish, | |
ce8f5370 AD |
900 | .pm_init_profile = &r600_pm_init_profile, |
901 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
6f34be50 AD |
902 | .pre_page_flip = &evergreen_pre_page_flip, |
903 | .page_flip = &evergreen_page_flip, | |
904 | .post_page_flip = &evergreen_post_page_flip, | |
3ae19b75 | 905 | .wait_for_vblank = &dce4_wait_for_vblank, |
89e5181f | 906 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
48e7a5f1 DV |
907 | }; |
908 | ||
958261d1 AD |
909 | static struct radeon_asic sumo_asic = { |
910 | .init = &evergreen_init, | |
911 | .fini = &evergreen_fini, | |
912 | .suspend = &evergreen_suspend, | |
913 | .resume = &evergreen_resume, | |
958261d1 AD |
914 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
915 | .asic_reset = &evergreen_asic_reset, | |
916 | .vga_set_state = &r600_vga_set_state, | |
917 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
918 | .gart_set_page = &rs600_gart_set_page, | |
919 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
920 | .ring = { |
921 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
922 | .ib_execute = &evergreen_ring_ib_execute, | |
923 | .emit_fence = &r600_fence_ring_emit, | |
924 | .emit_semaphore = &r600_semaphore_ring_emit, | |
925 | } | |
926 | }, | |
958261d1 AD |
927 | .irq_set = &evergreen_irq_set, |
928 | .irq_process = &evergreen_irq_process, | |
929 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
958261d1 | 930 | .cs_parse = &evergreen_cs_parse, |
fb3d9e97 | 931 | .copy_blit = &r600_copy_blit, |
20633442 | 932 | .copy_dma = NULL, |
fb3d9e97 | 933 | .copy = &r600_copy_blit, |
958261d1 AD |
934 | .get_engine_clock = &radeon_atom_get_engine_clock, |
935 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
936 | .get_memory_clock = NULL, | |
937 | .set_memory_clock = NULL, | |
938 | .get_pcie_lanes = NULL, | |
939 | .set_pcie_lanes = NULL, | |
940 | .set_clock_gating = NULL, | |
941 | .set_surface_reg = r600_set_surface_reg, | |
942 | .clear_surface_reg = r600_clear_surface_reg, | |
943 | .bandwidth_update = &evergreen_bandwidth_update, | |
901ea57d AD |
944 | .hpd = { |
945 | .init = &evergreen_hpd_init, | |
946 | .fini = &evergreen_hpd_fini, | |
947 | .sense = &evergreen_hpd_sense, | |
948 | .set_polarity = &evergreen_hpd_set_polarity, | |
949 | }, | |
97bfd0ac | 950 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
958261d1 AD |
951 | .gui_idle = &r600_gui_idle, |
952 | .pm_misc = &evergreen_pm_misc, | |
953 | .pm_prepare = &evergreen_pm_prepare, | |
954 | .pm_finish = &evergreen_pm_finish, | |
a4c9e2ee | 955 | .pm_init_profile = &sumo_pm_init_profile, |
958261d1 | 956 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
fdc315a1 DA |
957 | .pre_page_flip = &evergreen_pre_page_flip, |
958 | .page_flip = &evergreen_page_flip, | |
959 | .post_page_flip = &evergreen_post_page_flip, | |
3ae19b75 | 960 | .wait_for_vblank = &dce4_wait_for_vblank, |
89e5181f | 961 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
958261d1 AD |
962 | }; |
963 | ||
a43b7665 AD |
964 | static struct radeon_asic btc_asic = { |
965 | .init = &evergreen_init, | |
966 | .fini = &evergreen_fini, | |
967 | .suspend = &evergreen_suspend, | |
968 | .resume = &evergreen_resume, | |
a43b7665 AD |
969 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
970 | .asic_reset = &evergreen_asic_reset, | |
971 | .vga_set_state = &r600_vga_set_state, | |
972 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
973 | .gart_set_page = &rs600_gart_set_page, | |
974 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
975 | .ring = { |
976 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
977 | .ib_execute = &evergreen_ring_ib_execute, | |
978 | .emit_fence = &r600_fence_ring_emit, | |
979 | .emit_semaphore = &r600_semaphore_ring_emit, | |
980 | } | |
981 | }, | |
a43b7665 AD |
982 | .irq_set = &evergreen_irq_set, |
983 | .irq_process = &evergreen_irq_process, | |
984 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
a43b7665 | 985 | .cs_parse = &evergreen_cs_parse, |
fb3d9e97 | 986 | .copy_blit = &r600_copy_blit, |
20633442 | 987 | .copy_dma = NULL, |
fb3d9e97 | 988 | .copy = &r600_copy_blit, |
a43b7665 AD |
989 | .get_engine_clock = &radeon_atom_get_engine_clock, |
990 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
991 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
992 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
993 | .get_pcie_lanes = NULL, | |
994 | .set_pcie_lanes = NULL, | |
995 | .set_clock_gating = NULL, | |
996 | .set_surface_reg = r600_set_surface_reg, | |
997 | .clear_surface_reg = r600_clear_surface_reg, | |
998 | .bandwidth_update = &evergreen_bandwidth_update, | |
901ea57d AD |
999 | .hpd = { |
1000 | .init = &evergreen_hpd_init, | |
1001 | .fini = &evergreen_hpd_fini, | |
1002 | .sense = &evergreen_hpd_sense, | |
1003 | .set_polarity = &evergreen_hpd_set_polarity, | |
1004 | }, | |
97bfd0ac | 1005 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
a43b7665 AD |
1006 | .gui_idle = &r600_gui_idle, |
1007 | .pm_misc = &evergreen_pm_misc, | |
1008 | .pm_prepare = &evergreen_pm_prepare, | |
1009 | .pm_finish = &evergreen_pm_finish, | |
1010 | .pm_init_profile = &r600_pm_init_profile, | |
1011 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
1012 | .pre_page_flip = &evergreen_pre_page_flip, | |
1013 | .page_flip = &evergreen_page_flip, | |
1014 | .post_page_flip = &evergreen_post_page_flip, | |
3ae19b75 | 1015 | .wait_for_vblank = &dce4_wait_for_vblank, |
89e5181f | 1016 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
a43b7665 AD |
1017 | }; |
1018 | ||
721604a1 JG |
1019 | static const struct radeon_vm_funcs cayman_vm_funcs = { |
1020 | .init = &cayman_vm_init, | |
1021 | .fini = &cayman_vm_fini, | |
1022 | .bind = &cayman_vm_bind, | |
1023 | .unbind = &cayman_vm_unbind, | |
1024 | .tlb_flush = &cayman_vm_tlb_flush, | |
1025 | .page_flags = &cayman_vm_page_flags, | |
1026 | .set_page = &cayman_vm_set_page, | |
1027 | }; | |
1028 | ||
e3487629 AD |
1029 | static struct radeon_asic cayman_asic = { |
1030 | .init = &cayman_init, | |
1031 | .fini = &cayman_fini, | |
1032 | .suspend = &cayman_suspend, | |
1033 | .resume = &cayman_resume, | |
e3487629 AD |
1034 | .gpu_is_lockup = &cayman_gpu_is_lockup, |
1035 | .asic_reset = &cayman_asic_reset, | |
1036 | .vga_set_state = &r600_vga_set_state, | |
1037 | .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1038 | .gart_set_page = &rs600_gart_set_page, | |
1039 | .ring_test = &r600_ring_test, | |
4c87bc26 CK |
1040 | .ring = { |
1041 | [RADEON_RING_TYPE_GFX_INDEX] = { | |
721604a1 JG |
1042 | .ib_execute = &cayman_ring_ib_execute, |
1043 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1044 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 CK |
1045 | .emit_semaphore = &r600_semaphore_ring_emit, |
1046 | }, | |
1047 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | |
721604a1 JG |
1048 | .ib_execute = &cayman_ring_ib_execute, |
1049 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1050 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 CK |
1051 | .emit_semaphore = &r600_semaphore_ring_emit, |
1052 | }, | |
1053 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | |
721604a1 JG |
1054 | .ib_execute = &cayman_ring_ib_execute, |
1055 | .ib_parse = &evergreen_ib_parse, | |
b40e7e16 | 1056 | .emit_fence = &cayman_fence_ring_emit, |
4c87bc26 CK |
1057 | .emit_semaphore = &r600_semaphore_ring_emit, |
1058 | } | |
1059 | }, | |
e3487629 AD |
1060 | .irq_set = &evergreen_irq_set, |
1061 | .irq_process = &evergreen_irq_process, | |
1062 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
e3487629 | 1063 | .cs_parse = &evergreen_cs_parse, |
fb3d9e97 | 1064 | .copy_blit = &r600_copy_blit, |
20633442 | 1065 | .copy_dma = NULL, |
fb3d9e97 | 1066 | .copy = &r600_copy_blit, |
e3487629 AD |
1067 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1068 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1069 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1070 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1071 | .get_pcie_lanes = NULL, | |
1072 | .set_pcie_lanes = NULL, | |
1073 | .set_clock_gating = NULL, | |
1074 | .set_surface_reg = r600_set_surface_reg, | |
1075 | .clear_surface_reg = r600_clear_surface_reg, | |
1076 | .bandwidth_update = &evergreen_bandwidth_update, | |
901ea57d AD |
1077 | .hpd = { |
1078 | .init = &evergreen_hpd_init, | |
1079 | .fini = &evergreen_hpd_fini, | |
1080 | .sense = &evergreen_hpd_sense, | |
1081 | .set_polarity = &evergreen_hpd_set_polarity, | |
1082 | }, | |
97bfd0ac | 1083 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
e3487629 AD |
1084 | .gui_idle = &r600_gui_idle, |
1085 | .pm_misc = &evergreen_pm_misc, | |
1086 | .pm_prepare = &evergreen_pm_prepare, | |
1087 | .pm_finish = &evergreen_pm_finish, | |
1088 | .pm_init_profile = &r600_pm_init_profile, | |
1089 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | |
1090 | .pre_page_flip = &evergreen_pre_page_flip, | |
1091 | .page_flip = &evergreen_page_flip, | |
1092 | .post_page_flip = &evergreen_post_page_flip, | |
3ae19b75 | 1093 | .wait_for_vblank = &dce4_wait_for_vblank, |
89e5181f | 1094 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
e3487629 AD |
1095 | }; |
1096 | ||
0a10c851 DV |
1097 | int radeon_asic_init(struct radeon_device *rdev) |
1098 | { | |
1099 | radeon_register_accessor_init(rdev); | |
ba7e05e9 AD |
1100 | |
1101 | /* set the number of crtcs */ | |
1102 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
1103 | rdev->num_crtc = 1; | |
1104 | else | |
1105 | rdev->num_crtc = 2; | |
1106 | ||
3000bf39 AD |
1107 | /* set the ring used for bo copies */ |
1108 | rdev->copy_ring = RADEON_RING_TYPE_GFX_INDEX; | |
1109 | ||
0a10c851 DV |
1110 | switch (rdev->family) { |
1111 | case CHIP_R100: | |
1112 | case CHIP_RV100: | |
1113 | case CHIP_RS100: | |
1114 | case CHIP_RV200: | |
1115 | case CHIP_RS200: | |
1116 | rdev->asic = &r100_asic; | |
1117 | break; | |
1118 | case CHIP_R200: | |
1119 | case CHIP_RV250: | |
1120 | case CHIP_RS300: | |
1121 | case CHIP_RV280: | |
1122 | rdev->asic = &r200_asic; | |
1123 | break; | |
1124 | case CHIP_R300: | |
1125 | case CHIP_R350: | |
1126 | case CHIP_RV350: | |
1127 | case CHIP_RV380: | |
1128 | if (rdev->flags & RADEON_IS_PCIE) | |
1129 | rdev->asic = &r300_asic_pcie; | |
1130 | else | |
1131 | rdev->asic = &r300_asic; | |
1132 | break; | |
1133 | case CHIP_R420: | |
1134 | case CHIP_R423: | |
1135 | case CHIP_RV410: | |
1136 | rdev->asic = &r420_asic; | |
07bb084c AD |
1137 | /* handle macs */ |
1138 | if (rdev->bios == NULL) { | |
1139 | rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock; | |
1140 | rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock; | |
1141 | rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock; | |
1142 | rdev->asic->set_memory_clock = NULL; | |
1143 | } | |
0a10c851 DV |
1144 | break; |
1145 | case CHIP_RS400: | |
1146 | case CHIP_RS480: | |
1147 | rdev->asic = &rs400_asic; | |
1148 | break; | |
1149 | case CHIP_RS600: | |
1150 | rdev->asic = &rs600_asic; | |
1151 | break; | |
1152 | case CHIP_RS690: | |
1153 | case CHIP_RS740: | |
1154 | rdev->asic = &rs690_asic; | |
1155 | break; | |
1156 | case CHIP_RV515: | |
1157 | rdev->asic = &rv515_asic; | |
1158 | break; | |
1159 | case CHIP_R520: | |
1160 | case CHIP_RV530: | |
1161 | case CHIP_RV560: | |
1162 | case CHIP_RV570: | |
1163 | case CHIP_R580: | |
1164 | rdev->asic = &r520_asic; | |
1165 | break; | |
1166 | case CHIP_R600: | |
1167 | case CHIP_RV610: | |
1168 | case CHIP_RV630: | |
1169 | case CHIP_RV620: | |
1170 | case CHIP_RV635: | |
1171 | case CHIP_RV670: | |
f47299c5 AD |
1172 | rdev->asic = &r600_asic; |
1173 | break; | |
0a10c851 DV |
1174 | case CHIP_RS780: |
1175 | case CHIP_RS880: | |
f47299c5 | 1176 | rdev->asic = &rs780_asic; |
0a10c851 DV |
1177 | break; |
1178 | case CHIP_RV770: | |
1179 | case CHIP_RV730: | |
1180 | case CHIP_RV710: | |
1181 | case CHIP_RV740: | |
1182 | rdev->asic = &rv770_asic; | |
1183 | break; | |
1184 | case CHIP_CEDAR: | |
1185 | case CHIP_REDWOOD: | |
1186 | case CHIP_JUNIPER: | |
1187 | case CHIP_CYPRESS: | |
1188 | case CHIP_HEMLOCK: | |
ba7e05e9 AD |
1189 | /* set num crtcs */ |
1190 | if (rdev->family == CHIP_CEDAR) | |
1191 | rdev->num_crtc = 4; | |
1192 | else | |
1193 | rdev->num_crtc = 6; | |
0a10c851 DV |
1194 | rdev->asic = &evergreen_asic; |
1195 | break; | |
958261d1 | 1196 | case CHIP_PALM: |
89da5a37 AD |
1197 | case CHIP_SUMO: |
1198 | case CHIP_SUMO2: | |
958261d1 AD |
1199 | rdev->asic = &sumo_asic; |
1200 | break; | |
a43b7665 AD |
1201 | case CHIP_BARTS: |
1202 | case CHIP_TURKS: | |
1203 | case CHIP_CAICOS: | |
ba7e05e9 AD |
1204 | /* set num crtcs */ |
1205 | if (rdev->family == CHIP_CAICOS) | |
1206 | rdev->num_crtc = 4; | |
1207 | else | |
1208 | rdev->num_crtc = 6; | |
a43b7665 AD |
1209 | rdev->asic = &btc_asic; |
1210 | break; | |
e3487629 AD |
1211 | case CHIP_CAYMAN: |
1212 | rdev->asic = &cayman_asic; | |
ba7e05e9 AD |
1213 | /* set num crtcs */ |
1214 | rdev->num_crtc = 6; | |
721604a1 | 1215 | rdev->vm_manager.funcs = &cayman_vm_funcs; |
e3487629 | 1216 | break; |
0a10c851 DV |
1217 | default: |
1218 | /* FIXME: not supported yet */ | |
1219 | return -EINVAL; | |
1220 | } | |
1221 | ||
1222 | if (rdev->flags & RADEON_IS_IGP) { | |
1223 | rdev->asic->get_memory_clock = NULL; | |
1224 | rdev->asic->set_memory_clock = NULL; | |
1225 | } | |
1226 | ||
1227 | return 0; | |
1228 | } | |
1229 |