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0a10c851 DV |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | ||
29 | #include <linux/console.h> | |
30 | #include <drm/drmP.h> | |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
33 | #include <linux/vgaarb.h> | |
34 | #include <linux/vga_switcheroo.h> | |
35 | #include "radeon_reg.h" | |
36 | #include "radeon.h" | |
37 | #include "radeon_asic.h" | |
38 | #include "atom.h" | |
39 | ||
40 | /* | |
41 | * Registers accessors functions. | |
42 | */ | |
abf1dc67 AD |
43 | /** |
44 | * radeon_invalid_rreg - dummy reg read function | |
45 | * | |
46 | * @rdev: radeon device pointer | |
47 | * @reg: offset of register | |
48 | * | |
49 | * Dummy register read function. Used for register blocks | |
50 | * that certain asics don't have (all asics). | |
51 | * Returns the value in the register. | |
52 | */ | |
0a10c851 DV |
53 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
54 | { | |
55 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
56 | BUG_ON(1); | |
57 | return 0; | |
58 | } | |
59 | ||
abf1dc67 AD |
60 | /** |
61 | * radeon_invalid_wreg - dummy reg write function | |
62 | * | |
63 | * @rdev: radeon device pointer | |
64 | * @reg: offset of register | |
65 | * @v: value to write to the register | |
66 | * | |
67 | * Dummy register read function. Used for register blocks | |
68 | * that certain asics don't have (all asics). | |
69 | */ | |
0a10c851 DV |
70 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
71 | { | |
72 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
73 | reg, v); | |
74 | BUG_ON(1); | |
75 | } | |
76 | ||
abf1dc67 AD |
77 | /** |
78 | * radeon_register_accessor_init - sets up the register accessor callbacks | |
79 | * | |
80 | * @rdev: radeon device pointer | |
81 | * | |
82 | * Sets up the register accessor callbacks for various register | |
83 | * apertures. Not all asics have all apertures (all asics). | |
84 | */ | |
0a10c851 DV |
85 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
86 | { | |
87 | rdev->mc_rreg = &radeon_invalid_rreg; | |
88 | rdev->mc_wreg = &radeon_invalid_wreg; | |
89 | rdev->pll_rreg = &radeon_invalid_rreg; | |
90 | rdev->pll_wreg = &radeon_invalid_wreg; | |
91 | rdev->pciep_rreg = &radeon_invalid_rreg; | |
92 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
93 | ||
94 | /* Don't change order as we are overridding accessor. */ | |
95 | if (rdev->family < CHIP_RV515) { | |
96 | rdev->pcie_reg_mask = 0xff; | |
97 | } else { | |
98 | rdev->pcie_reg_mask = 0x7ff; | |
99 | } | |
100 | /* FIXME: not sure here */ | |
101 | if (rdev->family <= CHIP_R580) { | |
102 | rdev->pll_rreg = &r100_pll_rreg; | |
103 | rdev->pll_wreg = &r100_pll_wreg; | |
104 | } | |
105 | if (rdev->family >= CHIP_R420) { | |
106 | rdev->mc_rreg = &r420_mc_rreg; | |
107 | rdev->mc_wreg = &r420_mc_wreg; | |
108 | } | |
109 | if (rdev->family >= CHIP_RV515) { | |
110 | rdev->mc_rreg = &rv515_mc_rreg; | |
111 | rdev->mc_wreg = &rv515_mc_wreg; | |
112 | } | |
113 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
114 | rdev->mc_rreg = &rs400_mc_rreg; | |
115 | rdev->mc_wreg = &rs400_mc_wreg; | |
116 | } | |
117 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
118 | rdev->mc_rreg = &rs690_mc_rreg; | |
119 | rdev->mc_wreg = &rs690_mc_wreg; | |
120 | } | |
121 | if (rdev->family == CHIP_RS600) { | |
122 | rdev->mc_rreg = &rs600_mc_rreg; | |
123 | rdev->mc_wreg = &rs600_mc_wreg; | |
124 | } | |
65337e60 SL |
125 | if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { |
126 | rdev->mc_rreg = &rs780_mc_rreg; | |
127 | rdev->mc_wreg = &rs780_mc_wreg; | |
128 | } | |
6e2c3c0a AD |
129 | |
130 | if (rdev->family >= CHIP_BONAIRE) { | |
131 | rdev->pciep_rreg = &cik_pciep_rreg; | |
132 | rdev->pciep_wreg = &cik_pciep_wreg; | |
133 | } else if (rdev->family >= CHIP_R600) { | |
0a10c851 DV |
134 | rdev->pciep_rreg = &r600_pciep_rreg; |
135 | rdev->pciep_wreg = &r600_pciep_wreg; | |
136 | } | |
137 | } | |
138 | ||
139 | ||
140 | /* helper to disable agp */ | |
abf1dc67 AD |
141 | /** |
142 | * radeon_agp_disable - AGP disable helper function | |
143 | * | |
144 | * @rdev: radeon device pointer | |
145 | * | |
146 | * Removes AGP flags and changes the gart callbacks on AGP | |
147 | * cards when using the internal gart rather than AGP (all asics). | |
148 | */ | |
0a10c851 DV |
149 | void radeon_agp_disable(struct radeon_device *rdev) |
150 | { | |
151 | rdev->flags &= ~RADEON_IS_AGP; | |
152 | if (rdev->family >= CHIP_R600) { | |
153 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
154 | rdev->flags |= RADEON_IS_PCIE; | |
155 | } else if (rdev->family >= CHIP_RV515 || | |
156 | rdev->family == CHIP_RV380 || | |
157 | rdev->family == CHIP_RV410 || | |
158 | rdev->family == CHIP_R423) { | |
159 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
160 | rdev->flags |= RADEON_IS_PCIE; | |
c5b3b850 AD |
161 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
162 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; | |
0a10c851 DV |
163 | } else { |
164 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
165 | rdev->flags |= RADEON_IS_PCI; | |
c5b3b850 AD |
166 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
167 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; | |
0a10c851 DV |
168 | } |
169 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
170 | } | |
171 | ||
172 | /* | |
173 | * ASIC | |
174 | */ | |
76a0df85 CK |
175 | |
176 | static struct radeon_asic_ring r100_gfx_ring = { | |
177 | .ib_execute = &r100_ring_ib_execute, | |
178 | .emit_fence = &r100_fence_ring_emit, | |
179 | .emit_semaphore = &r100_semaphore_ring_emit, | |
180 | .cs_parse = &r100_cs_parse, | |
181 | .ring_start = &r100_ring_start, | |
182 | .ring_test = &r100_ring_test, | |
183 | .ib_test = &r100_ib_test, | |
184 | .is_lockup = &r100_gpu_is_lockup, | |
185 | .get_rptr = &radeon_ring_generic_get_rptr, | |
186 | .get_wptr = &radeon_ring_generic_get_wptr, | |
187 | .set_wptr = &radeon_ring_generic_set_wptr, | |
188 | }; | |
189 | ||
48e7a5f1 DV |
190 | static struct radeon_asic r100_asic = { |
191 | .init = &r100_init, | |
192 | .fini = &r100_fini, | |
193 | .suspend = &r100_suspend, | |
194 | .resume = &r100_resume, | |
195 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 196 | .asic_reset = &r100_asic_reset, |
54e88e06 AD |
197 | .ioctl_wait_idle = NULL, |
198 | .gui_idle = &r100_gui_idle, | |
199 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
200 | .gart = { |
201 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
202 | .set_page = &r100_pci_gart_set_page, | |
203 | }, | |
4c87bc26 | 204 | .ring = { |
76a0df85 | 205 | [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring |
4c87bc26 | 206 | }, |
b35ea4ab AD |
207 | .irq = { |
208 | .set = &r100_irq_set, | |
209 | .process = &r100_irq_process, | |
210 | }, | |
c79a49ca AD |
211 | .display = { |
212 | .bandwidth_update = &r100_bandwidth_update, | |
213 | .get_vblank_counter = &r100_get_vblank_counter, | |
214 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 215 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 216 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 217 | }, |
27cd7769 AD |
218 | .copy = { |
219 | .blit = &r100_copy_blit, | |
220 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
221 | .dma = NULL, | |
222 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
223 | .copy = &r100_copy_blit, | |
224 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
225 | }, | |
9e6f3d02 AD |
226 | .surface = { |
227 | .set_reg = r100_set_surface_reg, | |
228 | .clear_reg = r100_clear_surface_reg, | |
229 | }, | |
901ea57d AD |
230 | .hpd = { |
231 | .init = &r100_hpd_init, | |
232 | .fini = &r100_hpd_fini, | |
233 | .sense = &r100_hpd_sense, | |
234 | .set_polarity = &r100_hpd_set_polarity, | |
235 | }, | |
a02fa397 AD |
236 | .pm = { |
237 | .misc = &r100_pm_misc, | |
238 | .prepare = &r100_pm_prepare, | |
239 | .finish = &r100_pm_finish, | |
240 | .init_profile = &r100_pm_init_profile, | |
241 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
242 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
243 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
244 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
245 | .set_memory_clock = NULL, | |
246 | .get_pcie_lanes = NULL, | |
247 | .set_pcie_lanes = NULL, | |
248 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 249 | }, |
0f9e006c AD |
250 | .pflip = { |
251 | .pre_page_flip = &r100_pre_page_flip, | |
252 | .page_flip = &r100_page_flip, | |
253 | .post_page_flip = &r100_post_page_flip, | |
254 | }, | |
48e7a5f1 DV |
255 | }; |
256 | ||
257 | static struct radeon_asic r200_asic = { | |
258 | .init = &r100_init, | |
259 | .fini = &r100_fini, | |
260 | .suspend = &r100_suspend, | |
261 | .resume = &r100_resume, | |
262 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 263 | .asic_reset = &r100_asic_reset, |
54e88e06 AD |
264 | .ioctl_wait_idle = NULL, |
265 | .gui_idle = &r100_gui_idle, | |
266 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
267 | .gart = { |
268 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
269 | .set_page = &r100_pci_gart_set_page, | |
270 | }, | |
4c87bc26 | 271 | .ring = { |
76a0df85 | 272 | [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring |
4c87bc26 | 273 | }, |
b35ea4ab AD |
274 | .irq = { |
275 | .set = &r100_irq_set, | |
276 | .process = &r100_irq_process, | |
277 | }, | |
c79a49ca AD |
278 | .display = { |
279 | .bandwidth_update = &r100_bandwidth_update, | |
280 | .get_vblank_counter = &r100_get_vblank_counter, | |
281 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 282 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 283 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 284 | }, |
27cd7769 AD |
285 | .copy = { |
286 | .blit = &r100_copy_blit, | |
287 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
288 | .dma = &r200_copy_dma, | |
289 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
290 | .copy = &r100_copy_blit, | |
291 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
292 | }, | |
9e6f3d02 AD |
293 | .surface = { |
294 | .set_reg = r100_set_surface_reg, | |
295 | .clear_reg = r100_clear_surface_reg, | |
296 | }, | |
901ea57d AD |
297 | .hpd = { |
298 | .init = &r100_hpd_init, | |
299 | .fini = &r100_hpd_fini, | |
300 | .sense = &r100_hpd_sense, | |
301 | .set_polarity = &r100_hpd_set_polarity, | |
302 | }, | |
a02fa397 AD |
303 | .pm = { |
304 | .misc = &r100_pm_misc, | |
305 | .prepare = &r100_pm_prepare, | |
306 | .finish = &r100_pm_finish, | |
307 | .init_profile = &r100_pm_init_profile, | |
308 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
309 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
310 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
311 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
312 | .set_memory_clock = NULL, | |
313 | .get_pcie_lanes = NULL, | |
314 | .set_pcie_lanes = NULL, | |
315 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 316 | }, |
0f9e006c AD |
317 | .pflip = { |
318 | .pre_page_flip = &r100_pre_page_flip, | |
319 | .page_flip = &r100_page_flip, | |
320 | .post_page_flip = &r100_post_page_flip, | |
321 | }, | |
48e7a5f1 DV |
322 | }; |
323 | ||
76a0df85 CK |
324 | static struct radeon_asic_ring r300_gfx_ring = { |
325 | .ib_execute = &r100_ring_ib_execute, | |
326 | .emit_fence = &r300_fence_ring_emit, | |
327 | .emit_semaphore = &r100_semaphore_ring_emit, | |
328 | .cs_parse = &r300_cs_parse, | |
329 | .ring_start = &r300_ring_start, | |
330 | .ring_test = &r100_ring_test, | |
331 | .ib_test = &r100_ib_test, | |
332 | .is_lockup = &r100_gpu_is_lockup, | |
333 | .get_rptr = &radeon_ring_generic_get_rptr, | |
334 | .get_wptr = &radeon_ring_generic_get_wptr, | |
335 | .set_wptr = &radeon_ring_generic_set_wptr, | |
336 | }; | |
337 | ||
48e7a5f1 DV |
338 | static struct radeon_asic r300_asic = { |
339 | .init = &r300_init, | |
340 | .fini = &r300_fini, | |
341 | .suspend = &r300_suspend, | |
342 | .resume = &r300_resume, | |
343 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 344 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
345 | .ioctl_wait_idle = NULL, |
346 | .gui_idle = &r100_gui_idle, | |
347 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
348 | .gart = { |
349 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
350 | .set_page = &r100_pci_gart_set_page, | |
351 | }, | |
4c87bc26 | 352 | .ring = { |
76a0df85 | 353 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 354 | }, |
b35ea4ab AD |
355 | .irq = { |
356 | .set = &r100_irq_set, | |
357 | .process = &r100_irq_process, | |
358 | }, | |
c79a49ca AD |
359 | .display = { |
360 | .bandwidth_update = &r100_bandwidth_update, | |
361 | .get_vblank_counter = &r100_get_vblank_counter, | |
362 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 363 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 364 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 365 | }, |
27cd7769 AD |
366 | .copy = { |
367 | .blit = &r100_copy_blit, | |
368 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
369 | .dma = &r200_copy_dma, | |
370 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
371 | .copy = &r100_copy_blit, | |
372 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
373 | }, | |
9e6f3d02 AD |
374 | .surface = { |
375 | .set_reg = r100_set_surface_reg, | |
376 | .clear_reg = r100_clear_surface_reg, | |
377 | }, | |
901ea57d AD |
378 | .hpd = { |
379 | .init = &r100_hpd_init, | |
380 | .fini = &r100_hpd_fini, | |
381 | .sense = &r100_hpd_sense, | |
382 | .set_polarity = &r100_hpd_set_polarity, | |
383 | }, | |
a02fa397 AD |
384 | .pm = { |
385 | .misc = &r100_pm_misc, | |
386 | .prepare = &r100_pm_prepare, | |
387 | .finish = &r100_pm_finish, | |
388 | .init_profile = &r100_pm_init_profile, | |
389 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
390 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
391 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
392 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
393 | .set_memory_clock = NULL, | |
394 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
395 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
396 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 397 | }, |
0f9e006c AD |
398 | .pflip = { |
399 | .pre_page_flip = &r100_pre_page_flip, | |
400 | .page_flip = &r100_page_flip, | |
401 | .post_page_flip = &r100_post_page_flip, | |
402 | }, | |
48e7a5f1 DV |
403 | }; |
404 | ||
405 | static struct radeon_asic r300_asic_pcie = { | |
406 | .init = &r300_init, | |
407 | .fini = &r300_fini, | |
408 | .suspend = &r300_suspend, | |
409 | .resume = &r300_resume, | |
410 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 411 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
412 | .ioctl_wait_idle = NULL, |
413 | .gui_idle = &r100_gui_idle, | |
414 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
415 | .gart = { |
416 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
417 | .set_page = &rv370_pcie_gart_set_page, | |
418 | }, | |
4c87bc26 | 419 | .ring = { |
76a0df85 | 420 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 421 | }, |
b35ea4ab AD |
422 | .irq = { |
423 | .set = &r100_irq_set, | |
424 | .process = &r100_irq_process, | |
425 | }, | |
c79a49ca AD |
426 | .display = { |
427 | .bandwidth_update = &r100_bandwidth_update, | |
428 | .get_vblank_counter = &r100_get_vblank_counter, | |
429 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 430 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 431 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 432 | }, |
27cd7769 AD |
433 | .copy = { |
434 | .blit = &r100_copy_blit, | |
435 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
436 | .dma = &r200_copy_dma, | |
437 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
438 | .copy = &r100_copy_blit, | |
439 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
440 | }, | |
9e6f3d02 AD |
441 | .surface = { |
442 | .set_reg = r100_set_surface_reg, | |
443 | .clear_reg = r100_clear_surface_reg, | |
444 | }, | |
901ea57d AD |
445 | .hpd = { |
446 | .init = &r100_hpd_init, | |
447 | .fini = &r100_hpd_fini, | |
448 | .sense = &r100_hpd_sense, | |
449 | .set_polarity = &r100_hpd_set_polarity, | |
450 | }, | |
a02fa397 AD |
451 | .pm = { |
452 | .misc = &r100_pm_misc, | |
453 | .prepare = &r100_pm_prepare, | |
454 | .finish = &r100_pm_finish, | |
455 | .init_profile = &r100_pm_init_profile, | |
456 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
457 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
458 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
459 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
460 | .set_memory_clock = NULL, | |
461 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
462 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
463 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 464 | }, |
0f9e006c AD |
465 | .pflip = { |
466 | .pre_page_flip = &r100_pre_page_flip, | |
467 | .page_flip = &r100_page_flip, | |
468 | .post_page_flip = &r100_post_page_flip, | |
469 | }, | |
48e7a5f1 DV |
470 | }; |
471 | ||
472 | static struct radeon_asic r420_asic = { | |
473 | .init = &r420_init, | |
474 | .fini = &r420_fini, | |
475 | .suspend = &r420_suspend, | |
476 | .resume = &r420_resume, | |
477 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 478 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
479 | .ioctl_wait_idle = NULL, |
480 | .gui_idle = &r100_gui_idle, | |
481 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
482 | .gart = { |
483 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
484 | .set_page = &rv370_pcie_gart_set_page, | |
485 | }, | |
4c87bc26 | 486 | .ring = { |
76a0df85 | 487 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 488 | }, |
b35ea4ab AD |
489 | .irq = { |
490 | .set = &r100_irq_set, | |
491 | .process = &r100_irq_process, | |
492 | }, | |
c79a49ca AD |
493 | .display = { |
494 | .bandwidth_update = &r100_bandwidth_update, | |
495 | .get_vblank_counter = &r100_get_vblank_counter, | |
496 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 497 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 498 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 499 | }, |
27cd7769 AD |
500 | .copy = { |
501 | .blit = &r100_copy_blit, | |
502 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
503 | .dma = &r200_copy_dma, | |
504 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
505 | .copy = &r100_copy_blit, | |
506 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
507 | }, | |
9e6f3d02 AD |
508 | .surface = { |
509 | .set_reg = r100_set_surface_reg, | |
510 | .clear_reg = r100_clear_surface_reg, | |
511 | }, | |
901ea57d AD |
512 | .hpd = { |
513 | .init = &r100_hpd_init, | |
514 | .fini = &r100_hpd_fini, | |
515 | .sense = &r100_hpd_sense, | |
516 | .set_polarity = &r100_hpd_set_polarity, | |
517 | }, | |
a02fa397 AD |
518 | .pm = { |
519 | .misc = &r100_pm_misc, | |
520 | .prepare = &r100_pm_prepare, | |
521 | .finish = &r100_pm_finish, | |
522 | .init_profile = &r420_pm_init_profile, | |
523 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
524 | .get_engine_clock = &radeon_atom_get_engine_clock, |
525 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
526 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
527 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
528 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
529 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
530 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 531 | }, |
0f9e006c AD |
532 | .pflip = { |
533 | .pre_page_flip = &r100_pre_page_flip, | |
534 | .page_flip = &r100_page_flip, | |
535 | .post_page_flip = &r100_post_page_flip, | |
536 | }, | |
48e7a5f1 DV |
537 | }; |
538 | ||
539 | static struct radeon_asic rs400_asic = { | |
540 | .init = &rs400_init, | |
541 | .fini = &rs400_fini, | |
542 | .suspend = &rs400_suspend, | |
543 | .resume = &rs400_resume, | |
544 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 545 | .asic_reset = &r300_asic_reset, |
54e88e06 AD |
546 | .ioctl_wait_idle = NULL, |
547 | .gui_idle = &r100_gui_idle, | |
548 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, | |
c5b3b850 AD |
549 | .gart = { |
550 | .tlb_flush = &rs400_gart_tlb_flush, | |
551 | .set_page = &rs400_gart_set_page, | |
552 | }, | |
4c87bc26 | 553 | .ring = { |
76a0df85 | 554 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 555 | }, |
b35ea4ab AD |
556 | .irq = { |
557 | .set = &r100_irq_set, | |
558 | .process = &r100_irq_process, | |
559 | }, | |
c79a49ca AD |
560 | .display = { |
561 | .bandwidth_update = &r100_bandwidth_update, | |
562 | .get_vblank_counter = &r100_get_vblank_counter, | |
563 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 564 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 565 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 566 | }, |
27cd7769 AD |
567 | .copy = { |
568 | .blit = &r100_copy_blit, | |
569 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
570 | .dma = &r200_copy_dma, | |
571 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
572 | .copy = &r100_copy_blit, | |
573 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
574 | }, | |
9e6f3d02 AD |
575 | .surface = { |
576 | .set_reg = r100_set_surface_reg, | |
577 | .clear_reg = r100_clear_surface_reg, | |
578 | }, | |
901ea57d AD |
579 | .hpd = { |
580 | .init = &r100_hpd_init, | |
581 | .fini = &r100_hpd_fini, | |
582 | .sense = &r100_hpd_sense, | |
583 | .set_polarity = &r100_hpd_set_polarity, | |
584 | }, | |
a02fa397 AD |
585 | .pm = { |
586 | .misc = &r100_pm_misc, | |
587 | .prepare = &r100_pm_prepare, | |
588 | .finish = &r100_pm_finish, | |
589 | .init_profile = &r100_pm_init_profile, | |
590 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
591 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
592 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
593 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
594 | .set_memory_clock = NULL, | |
595 | .get_pcie_lanes = NULL, | |
596 | .set_pcie_lanes = NULL, | |
597 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 598 | }, |
0f9e006c AD |
599 | .pflip = { |
600 | .pre_page_flip = &r100_pre_page_flip, | |
601 | .page_flip = &r100_page_flip, | |
602 | .post_page_flip = &r100_post_page_flip, | |
603 | }, | |
48e7a5f1 DV |
604 | }; |
605 | ||
606 | static struct radeon_asic rs600_asic = { | |
607 | .init = &rs600_init, | |
608 | .fini = &rs600_fini, | |
609 | .suspend = &rs600_suspend, | |
610 | .resume = &rs600_resume, | |
611 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 612 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
613 | .ioctl_wait_idle = NULL, |
614 | .gui_idle = &r100_gui_idle, | |
615 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, | |
c5b3b850 AD |
616 | .gart = { |
617 | .tlb_flush = &rs600_gart_tlb_flush, | |
618 | .set_page = &rs600_gart_set_page, | |
619 | }, | |
4c87bc26 | 620 | .ring = { |
76a0df85 | 621 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 622 | }, |
b35ea4ab AD |
623 | .irq = { |
624 | .set = &rs600_irq_set, | |
625 | .process = &rs600_irq_process, | |
626 | }, | |
c79a49ca AD |
627 | .display = { |
628 | .bandwidth_update = &rs600_bandwidth_update, | |
629 | .get_vblank_counter = &rs600_get_vblank_counter, | |
630 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 631 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 632 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
633 | .hdmi_enable = &r600_hdmi_enable, |
634 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 635 | }, |
27cd7769 AD |
636 | .copy = { |
637 | .blit = &r100_copy_blit, | |
638 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
639 | .dma = &r200_copy_dma, | |
640 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
641 | .copy = &r100_copy_blit, | |
642 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
643 | }, | |
9e6f3d02 AD |
644 | .surface = { |
645 | .set_reg = r100_set_surface_reg, | |
646 | .clear_reg = r100_clear_surface_reg, | |
647 | }, | |
901ea57d AD |
648 | .hpd = { |
649 | .init = &rs600_hpd_init, | |
650 | .fini = &rs600_hpd_fini, | |
651 | .sense = &rs600_hpd_sense, | |
652 | .set_polarity = &rs600_hpd_set_polarity, | |
653 | }, | |
a02fa397 AD |
654 | .pm = { |
655 | .misc = &rs600_pm_misc, | |
656 | .prepare = &rs600_pm_prepare, | |
657 | .finish = &rs600_pm_finish, | |
658 | .init_profile = &r420_pm_init_profile, | |
659 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
660 | .get_engine_clock = &radeon_atom_get_engine_clock, |
661 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
662 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
663 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
664 | .get_pcie_lanes = NULL, | |
665 | .set_pcie_lanes = NULL, | |
666 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 667 | }, |
0f9e006c AD |
668 | .pflip = { |
669 | .pre_page_flip = &rs600_pre_page_flip, | |
670 | .page_flip = &rs600_page_flip, | |
671 | .post_page_flip = &rs600_post_page_flip, | |
672 | }, | |
48e7a5f1 DV |
673 | }; |
674 | ||
675 | static struct radeon_asic rs690_asic = { | |
676 | .init = &rs690_init, | |
677 | .fini = &rs690_fini, | |
678 | .suspend = &rs690_suspend, | |
679 | .resume = &rs690_resume, | |
680 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 681 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
682 | .ioctl_wait_idle = NULL, |
683 | .gui_idle = &r100_gui_idle, | |
684 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, | |
c5b3b850 AD |
685 | .gart = { |
686 | .tlb_flush = &rs400_gart_tlb_flush, | |
687 | .set_page = &rs400_gart_set_page, | |
688 | }, | |
4c87bc26 | 689 | .ring = { |
76a0df85 | 690 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 691 | }, |
b35ea4ab AD |
692 | .irq = { |
693 | .set = &rs600_irq_set, | |
694 | .process = &rs600_irq_process, | |
695 | }, | |
c79a49ca AD |
696 | .display = { |
697 | .get_vblank_counter = &rs600_get_vblank_counter, | |
698 | .bandwidth_update = &rs690_bandwidth_update, | |
699 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 700 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 701 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
702 | .hdmi_enable = &r600_hdmi_enable, |
703 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 704 | }, |
27cd7769 AD |
705 | .copy = { |
706 | .blit = &r100_copy_blit, | |
707 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
708 | .dma = &r200_copy_dma, | |
709 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
710 | .copy = &r200_copy_dma, | |
711 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
712 | }, | |
9e6f3d02 AD |
713 | .surface = { |
714 | .set_reg = r100_set_surface_reg, | |
715 | .clear_reg = r100_clear_surface_reg, | |
716 | }, | |
901ea57d AD |
717 | .hpd = { |
718 | .init = &rs600_hpd_init, | |
719 | .fini = &rs600_hpd_fini, | |
720 | .sense = &rs600_hpd_sense, | |
721 | .set_polarity = &rs600_hpd_set_polarity, | |
722 | }, | |
a02fa397 AD |
723 | .pm = { |
724 | .misc = &rs600_pm_misc, | |
725 | .prepare = &rs600_pm_prepare, | |
726 | .finish = &rs600_pm_finish, | |
727 | .init_profile = &r420_pm_init_profile, | |
728 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
729 | .get_engine_clock = &radeon_atom_get_engine_clock, |
730 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
731 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
732 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
733 | .get_pcie_lanes = NULL, | |
734 | .set_pcie_lanes = NULL, | |
735 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 736 | }, |
0f9e006c AD |
737 | .pflip = { |
738 | .pre_page_flip = &rs600_pre_page_flip, | |
739 | .page_flip = &rs600_page_flip, | |
740 | .post_page_flip = &rs600_post_page_flip, | |
741 | }, | |
48e7a5f1 DV |
742 | }; |
743 | ||
744 | static struct radeon_asic rv515_asic = { | |
745 | .init = &rv515_init, | |
746 | .fini = &rv515_fini, | |
747 | .suspend = &rv515_suspend, | |
748 | .resume = &rv515_resume, | |
749 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 750 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
751 | .ioctl_wait_idle = NULL, |
752 | .gui_idle = &r100_gui_idle, | |
753 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, | |
c5b3b850 AD |
754 | .gart = { |
755 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
756 | .set_page = &rv370_pcie_gart_set_page, | |
757 | }, | |
4c87bc26 | 758 | .ring = { |
76a0df85 | 759 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 760 | }, |
b35ea4ab AD |
761 | .irq = { |
762 | .set = &rs600_irq_set, | |
763 | .process = &rs600_irq_process, | |
764 | }, | |
c79a49ca AD |
765 | .display = { |
766 | .get_vblank_counter = &rs600_get_vblank_counter, | |
767 | .bandwidth_update = &rv515_bandwidth_update, | |
768 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 769 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 770 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 771 | }, |
27cd7769 AD |
772 | .copy = { |
773 | .blit = &r100_copy_blit, | |
774 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
775 | .dma = &r200_copy_dma, | |
776 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
777 | .copy = &r100_copy_blit, | |
778 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
779 | }, | |
9e6f3d02 AD |
780 | .surface = { |
781 | .set_reg = r100_set_surface_reg, | |
782 | .clear_reg = r100_clear_surface_reg, | |
783 | }, | |
901ea57d AD |
784 | .hpd = { |
785 | .init = &rs600_hpd_init, | |
786 | .fini = &rs600_hpd_fini, | |
787 | .sense = &rs600_hpd_sense, | |
788 | .set_polarity = &rs600_hpd_set_polarity, | |
789 | }, | |
a02fa397 AD |
790 | .pm = { |
791 | .misc = &rs600_pm_misc, | |
792 | .prepare = &rs600_pm_prepare, | |
793 | .finish = &rs600_pm_finish, | |
794 | .init_profile = &r420_pm_init_profile, | |
795 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
796 | .get_engine_clock = &radeon_atom_get_engine_clock, |
797 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
798 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
799 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
800 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
801 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
802 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 803 | }, |
0f9e006c AD |
804 | .pflip = { |
805 | .pre_page_flip = &rs600_pre_page_flip, | |
806 | .page_flip = &rs600_page_flip, | |
807 | .post_page_flip = &rs600_post_page_flip, | |
808 | }, | |
48e7a5f1 DV |
809 | }; |
810 | ||
811 | static struct radeon_asic r520_asic = { | |
812 | .init = &r520_init, | |
813 | .fini = &rv515_fini, | |
814 | .suspend = &rv515_suspend, | |
815 | .resume = &r520_resume, | |
816 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 817 | .asic_reset = &rs600_asic_reset, |
54e88e06 AD |
818 | .ioctl_wait_idle = NULL, |
819 | .gui_idle = &r100_gui_idle, | |
820 | .mc_wait_for_idle = &r520_mc_wait_for_idle, | |
c5b3b850 AD |
821 | .gart = { |
822 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
823 | .set_page = &rv370_pcie_gart_set_page, | |
824 | }, | |
4c87bc26 | 825 | .ring = { |
76a0df85 | 826 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 827 | }, |
b35ea4ab AD |
828 | .irq = { |
829 | .set = &rs600_irq_set, | |
830 | .process = &rs600_irq_process, | |
831 | }, | |
c79a49ca AD |
832 | .display = { |
833 | .bandwidth_update = &rv515_bandwidth_update, | |
834 | .get_vblank_counter = &rs600_get_vblank_counter, | |
835 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 836 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 837 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 838 | }, |
27cd7769 AD |
839 | .copy = { |
840 | .blit = &r100_copy_blit, | |
841 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
842 | .dma = &r200_copy_dma, | |
843 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
844 | .copy = &r100_copy_blit, | |
845 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
846 | }, | |
9e6f3d02 AD |
847 | .surface = { |
848 | .set_reg = r100_set_surface_reg, | |
849 | .clear_reg = r100_clear_surface_reg, | |
850 | }, | |
901ea57d AD |
851 | .hpd = { |
852 | .init = &rs600_hpd_init, | |
853 | .fini = &rs600_hpd_fini, | |
854 | .sense = &rs600_hpd_sense, | |
855 | .set_polarity = &rs600_hpd_set_polarity, | |
856 | }, | |
a02fa397 AD |
857 | .pm = { |
858 | .misc = &rs600_pm_misc, | |
859 | .prepare = &rs600_pm_prepare, | |
860 | .finish = &rs600_pm_finish, | |
861 | .init_profile = &r420_pm_init_profile, | |
862 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
863 | .get_engine_clock = &radeon_atom_get_engine_clock, |
864 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
865 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
866 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
867 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
868 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
869 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 870 | }, |
0f9e006c AD |
871 | .pflip = { |
872 | .pre_page_flip = &rs600_pre_page_flip, | |
873 | .page_flip = &rs600_page_flip, | |
874 | .post_page_flip = &rs600_post_page_flip, | |
875 | }, | |
48e7a5f1 DV |
876 | }; |
877 | ||
76a0df85 CK |
878 | static struct radeon_asic_ring r600_gfx_ring = { |
879 | .ib_execute = &r600_ring_ib_execute, | |
880 | .emit_fence = &r600_fence_ring_emit, | |
881 | .emit_semaphore = &r600_semaphore_ring_emit, | |
882 | .cs_parse = &r600_cs_parse, | |
883 | .ring_test = &r600_ring_test, | |
884 | .ib_test = &r600_ib_test, | |
885 | .is_lockup = &r600_gfx_is_lockup, | |
886 | .get_rptr = &radeon_ring_generic_get_rptr, | |
887 | .get_wptr = &radeon_ring_generic_get_wptr, | |
888 | .set_wptr = &radeon_ring_generic_set_wptr, | |
889 | }; | |
890 | ||
891 | static struct radeon_asic_ring r600_dma_ring = { | |
892 | .ib_execute = &r600_dma_ring_ib_execute, | |
893 | .emit_fence = &r600_dma_fence_ring_emit, | |
894 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
895 | .cs_parse = &r600_dma_cs_parse, | |
896 | .ring_test = &r600_dma_ring_test, | |
897 | .ib_test = &r600_dma_ib_test, | |
898 | .is_lockup = &r600_dma_is_lockup, | |
2e1e6dad CK |
899 | .get_rptr = &r600_dma_get_rptr, |
900 | .get_wptr = &r600_dma_get_wptr, | |
901 | .set_wptr = &r600_dma_set_wptr, | |
76a0df85 CK |
902 | }; |
903 | ||
48e7a5f1 DV |
904 | static struct radeon_asic r600_asic = { |
905 | .init = &r600_init, | |
906 | .fini = &r600_fini, | |
907 | .suspend = &r600_suspend, | |
908 | .resume = &r600_resume, | |
48e7a5f1 | 909 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 910 | .asic_reset = &r600_asic_reset, |
54e88e06 AD |
911 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
912 | .gui_idle = &r600_gui_idle, | |
913 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 914 | .get_xclk = &r600_get_xclk, |
d0418894 | 915 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
916 | .gart = { |
917 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
918 | .set_page = &rs600_gart_set_page, | |
919 | }, | |
4c87bc26 | 920 | .ring = { |
76a0df85 CK |
921 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
922 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
4c87bc26 | 923 | }, |
b35ea4ab AD |
924 | .irq = { |
925 | .set = &r600_irq_set, | |
926 | .process = &r600_irq_process, | |
927 | }, | |
c79a49ca AD |
928 | .display = { |
929 | .bandwidth_update = &rv515_bandwidth_update, | |
930 | .get_vblank_counter = &rs600_get_vblank_counter, | |
931 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 932 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 933 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
934 | .hdmi_enable = &r600_hdmi_enable, |
935 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 936 | }, |
27cd7769 | 937 | .copy = { |
8dddb993 | 938 | .blit = &r600_copy_cpdma, |
27cd7769 | 939 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
4d75658b AD |
940 | .dma = &r600_copy_dma, |
941 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 942 | .copy = &r600_copy_cpdma, |
aeea40cb | 943 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
27cd7769 | 944 | }, |
9e6f3d02 AD |
945 | .surface = { |
946 | .set_reg = r600_set_surface_reg, | |
947 | .clear_reg = r600_clear_surface_reg, | |
948 | }, | |
901ea57d AD |
949 | .hpd = { |
950 | .init = &r600_hpd_init, | |
951 | .fini = &r600_hpd_fini, | |
952 | .sense = &r600_hpd_sense, | |
953 | .set_polarity = &r600_hpd_set_polarity, | |
954 | }, | |
a02fa397 AD |
955 | .pm = { |
956 | .misc = &r600_pm_misc, | |
957 | .prepare = &rs600_pm_prepare, | |
958 | .finish = &rs600_pm_finish, | |
959 | .init_profile = &r600_pm_init_profile, | |
960 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
961 | .get_engine_clock = &radeon_atom_get_engine_clock, |
962 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
963 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
964 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
965 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
966 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
967 | .set_clock_gating = NULL, | |
6bd1c385 | 968 | .get_temperature = &rv6xx_get_temp, |
a02fa397 | 969 | }, |
0f9e006c AD |
970 | .pflip = { |
971 | .pre_page_flip = &rs600_pre_page_flip, | |
972 | .page_flip = &rs600_page_flip, | |
973 | .post_page_flip = &rs600_post_page_flip, | |
974 | }, | |
48e7a5f1 DV |
975 | }; |
976 | ||
ca361b65 AD |
977 | static struct radeon_asic rv6xx_asic = { |
978 | .init = &r600_init, | |
979 | .fini = &r600_fini, | |
980 | .suspend = &r600_suspend, | |
981 | .resume = &r600_resume, | |
982 | .vga_set_state = &r600_vga_set_state, | |
983 | .asic_reset = &r600_asic_reset, | |
984 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
985 | .gui_idle = &r600_gui_idle, | |
986 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
987 | .get_xclk = &r600_get_xclk, | |
988 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | |
989 | .gart = { | |
990 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
991 | .set_page = &rs600_gart_set_page, | |
992 | }, | |
993 | .ring = { | |
76a0df85 CK |
994 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
995 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
ca361b65 AD |
996 | }, |
997 | .irq = { | |
998 | .set = &r600_irq_set, | |
999 | .process = &r600_irq_process, | |
1000 | }, | |
1001 | .display = { | |
1002 | .bandwidth_update = &rv515_bandwidth_update, | |
1003 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1004 | .wait_for_vblank = &avivo_wait_for_vblank, | |
1005 | .set_backlight_level = &atombios_set_backlight_level, | |
1006 | .get_backlight_level = &atombios_get_backlight_level, | |
1007 | }, | |
1008 | .copy = { | |
8dddb993 | 1009 | .blit = &r600_copy_cpdma, |
ca361b65 AD |
1010 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1011 | .dma = &r600_copy_dma, | |
1012 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 1013 | .copy = &r600_copy_cpdma, |
aeea40cb | 1014 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
ca361b65 AD |
1015 | }, |
1016 | .surface = { | |
1017 | .set_reg = r600_set_surface_reg, | |
1018 | .clear_reg = r600_clear_surface_reg, | |
1019 | }, | |
1020 | .hpd = { | |
1021 | .init = &r600_hpd_init, | |
1022 | .fini = &r600_hpd_fini, | |
1023 | .sense = &r600_hpd_sense, | |
1024 | .set_polarity = &r600_hpd_set_polarity, | |
1025 | }, | |
1026 | .pm = { | |
1027 | .misc = &r600_pm_misc, | |
1028 | .prepare = &rs600_pm_prepare, | |
1029 | .finish = &rs600_pm_finish, | |
1030 | .init_profile = &r600_pm_init_profile, | |
1031 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1032 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1033 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1034 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1035 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1036 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1037 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1038 | .set_clock_gating = NULL, | |
1039 | .get_temperature = &rv6xx_get_temp, | |
1040 | }, | |
4a6369e9 AD |
1041 | .dpm = { |
1042 | .init = &rv6xx_dpm_init, | |
1043 | .setup_asic = &rv6xx_setup_asic, | |
1044 | .enable = &rv6xx_dpm_enable, | |
1045 | .disable = &rv6xx_dpm_disable, | |
98243917 | 1046 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
4a6369e9 | 1047 | .set_power_state = &rv6xx_dpm_set_power_state, |
98243917 | 1048 | .post_set_power_state = &r600_dpm_post_set_power_state, |
4a6369e9 AD |
1049 | .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, |
1050 | .fini = &rv6xx_dpm_fini, | |
1051 | .get_sclk = &rv6xx_dpm_get_sclk, | |
1052 | .get_mclk = &rv6xx_dpm_get_mclk, | |
1053 | .print_power_state = &rv6xx_dpm_print_power_state, | |
242916a5 | 1054 | .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, |
f4f85a8c | 1055 | .force_performance_level = &rv6xx_dpm_force_performance_level, |
4a6369e9 | 1056 | }, |
ca361b65 AD |
1057 | .pflip = { |
1058 | .pre_page_flip = &rs600_pre_page_flip, | |
1059 | .page_flip = &rs600_page_flip, | |
1060 | .post_page_flip = &rs600_post_page_flip, | |
1061 | }, | |
1062 | }; | |
1063 | ||
f47299c5 AD |
1064 | static struct radeon_asic rs780_asic = { |
1065 | .init = &r600_init, | |
1066 | .fini = &r600_fini, | |
1067 | .suspend = &r600_suspend, | |
1068 | .resume = &r600_resume, | |
f47299c5 | 1069 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 1070 | .asic_reset = &r600_asic_reset, |
54e88e06 AD |
1071 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1072 | .gui_idle = &r600_gui_idle, | |
1073 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 1074 | .get_xclk = &r600_get_xclk, |
d0418894 | 1075 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1076 | .gart = { |
1077 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
1078 | .set_page = &rs600_gart_set_page, | |
1079 | }, | |
4c87bc26 | 1080 | .ring = { |
76a0df85 CK |
1081 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1082 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
4c87bc26 | 1083 | }, |
b35ea4ab AD |
1084 | .irq = { |
1085 | .set = &r600_irq_set, | |
1086 | .process = &r600_irq_process, | |
1087 | }, | |
c79a49ca AD |
1088 | .display = { |
1089 | .bandwidth_update = &rs690_bandwidth_update, | |
1090 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1091 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1092 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1093 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1094 | .hdmi_enable = &r600_hdmi_enable, |
1095 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 1096 | }, |
27cd7769 | 1097 | .copy = { |
8dddb993 | 1098 | .blit = &r600_copy_cpdma, |
27cd7769 | 1099 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
4d75658b AD |
1100 | .dma = &r600_copy_dma, |
1101 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 1102 | .copy = &r600_copy_cpdma, |
aeea40cb | 1103 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
27cd7769 | 1104 | }, |
9e6f3d02 AD |
1105 | .surface = { |
1106 | .set_reg = r600_set_surface_reg, | |
1107 | .clear_reg = r600_clear_surface_reg, | |
1108 | }, | |
901ea57d AD |
1109 | .hpd = { |
1110 | .init = &r600_hpd_init, | |
1111 | .fini = &r600_hpd_fini, | |
1112 | .sense = &r600_hpd_sense, | |
1113 | .set_polarity = &r600_hpd_set_polarity, | |
1114 | }, | |
a02fa397 AD |
1115 | .pm = { |
1116 | .misc = &r600_pm_misc, | |
1117 | .prepare = &rs600_pm_prepare, | |
1118 | .finish = &rs600_pm_finish, | |
1119 | .init_profile = &rs780_pm_init_profile, | |
1120 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1121 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1122 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1123 | .get_memory_clock = NULL, | |
1124 | .set_memory_clock = NULL, | |
1125 | .get_pcie_lanes = NULL, | |
1126 | .set_pcie_lanes = NULL, | |
1127 | .set_clock_gating = NULL, | |
6bd1c385 | 1128 | .get_temperature = &rv6xx_get_temp, |
a02fa397 | 1129 | }, |
9d67006e AD |
1130 | .dpm = { |
1131 | .init = &rs780_dpm_init, | |
1132 | .setup_asic = &rs780_dpm_setup_asic, | |
1133 | .enable = &rs780_dpm_enable, | |
1134 | .disable = &rs780_dpm_disable, | |
98243917 | 1135 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
9d67006e | 1136 | .set_power_state = &rs780_dpm_set_power_state, |
98243917 | 1137 | .post_set_power_state = &r600_dpm_post_set_power_state, |
9d67006e AD |
1138 | .display_configuration_changed = &rs780_dpm_display_configuration_changed, |
1139 | .fini = &rs780_dpm_fini, | |
1140 | .get_sclk = &rs780_dpm_get_sclk, | |
1141 | .get_mclk = &rs780_dpm_get_mclk, | |
1142 | .print_power_state = &rs780_dpm_print_power_state, | |
444bddc4 | 1143 | .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, |
9d67006e | 1144 | }, |
0f9e006c AD |
1145 | .pflip = { |
1146 | .pre_page_flip = &rs600_pre_page_flip, | |
1147 | .page_flip = &rs600_page_flip, | |
1148 | .post_page_flip = &rs600_post_page_flip, | |
1149 | }, | |
f47299c5 AD |
1150 | }; |
1151 | ||
76a0df85 CK |
1152 | static struct radeon_asic_ring rv770_uvd_ring = { |
1153 | .ib_execute = &r600_uvd_ib_execute, | |
1154 | .emit_fence = &r600_uvd_fence_emit, | |
1155 | .emit_semaphore = &r600_uvd_semaphore_emit, | |
1156 | .cs_parse = &radeon_uvd_cs_parse, | |
1157 | .ring_test = &r600_uvd_ring_test, | |
1158 | .ib_test = &r600_uvd_ib_test, | |
1159 | .is_lockup = &radeon_ring_test_lockup, | |
02c9f7fa CK |
1160 | .get_rptr = &r600_uvd_get_rptr, |
1161 | .get_wptr = &r600_uvd_get_wptr, | |
1162 | .set_wptr = &r600_uvd_set_wptr, | |
76a0df85 CK |
1163 | }; |
1164 | ||
48e7a5f1 DV |
1165 | static struct radeon_asic rv770_asic = { |
1166 | .init = &rv770_init, | |
1167 | .fini = &rv770_fini, | |
1168 | .suspend = &rv770_suspend, | |
1169 | .resume = &rv770_resume, | |
a2d07b74 | 1170 | .asic_reset = &r600_asic_reset, |
48e7a5f1 | 1171 | .vga_set_state = &r600_vga_set_state, |
54e88e06 AD |
1172 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1173 | .gui_idle = &r600_gui_idle, | |
1174 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 1175 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1176 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1177 | .gart = { |
1178 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
1179 | .set_page = &rs600_gart_set_page, | |
1180 | }, | |
4c87bc26 | 1181 | .ring = { |
76a0df85 CK |
1182 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1183 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
1184 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1185 | }, |
b35ea4ab AD |
1186 | .irq = { |
1187 | .set = &r600_irq_set, | |
1188 | .process = &r600_irq_process, | |
1189 | }, | |
c79a49ca AD |
1190 | .display = { |
1191 | .bandwidth_update = &rv515_bandwidth_update, | |
1192 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1193 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1194 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1195 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1196 | .hdmi_enable = &r600_hdmi_enable, |
1197 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 1198 | }, |
27cd7769 | 1199 | .copy = { |
8dddb993 | 1200 | .blit = &r600_copy_cpdma, |
27cd7769 | 1201 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
43fb7787 | 1202 | .dma = &rv770_copy_dma, |
4d75658b | 1203 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
43fb7787 | 1204 | .copy = &rv770_copy_dma, |
2d6cc729 | 1205 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
27cd7769 | 1206 | }, |
9e6f3d02 AD |
1207 | .surface = { |
1208 | .set_reg = r600_set_surface_reg, | |
1209 | .clear_reg = r600_clear_surface_reg, | |
1210 | }, | |
901ea57d AD |
1211 | .hpd = { |
1212 | .init = &r600_hpd_init, | |
1213 | .fini = &r600_hpd_fini, | |
1214 | .sense = &r600_hpd_sense, | |
1215 | .set_polarity = &r600_hpd_set_polarity, | |
1216 | }, | |
a02fa397 AD |
1217 | .pm = { |
1218 | .misc = &rv770_pm_misc, | |
1219 | .prepare = &rs600_pm_prepare, | |
1220 | .finish = &rs600_pm_finish, | |
1221 | .init_profile = &r600_pm_init_profile, | |
1222 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1223 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1224 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1225 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1226 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1227 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1228 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1229 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
ef0e6e65 | 1230 | .set_uvd_clocks = &rv770_set_uvd_clocks, |
6bd1c385 | 1231 | .get_temperature = &rv770_get_temp, |
a02fa397 | 1232 | }, |
66229b20 AD |
1233 | .dpm = { |
1234 | .init = &rv770_dpm_init, | |
1235 | .setup_asic = &rv770_dpm_setup_asic, | |
1236 | .enable = &rv770_dpm_enable, | |
1237 | .disable = &rv770_dpm_disable, | |
98243917 | 1238 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
66229b20 | 1239 | .set_power_state = &rv770_dpm_set_power_state, |
98243917 | 1240 | .post_set_power_state = &r600_dpm_post_set_power_state, |
66229b20 AD |
1241 | .display_configuration_changed = &rv770_dpm_display_configuration_changed, |
1242 | .fini = &rv770_dpm_fini, | |
1243 | .get_sclk = &rv770_dpm_get_sclk, | |
1244 | .get_mclk = &rv770_dpm_get_mclk, | |
1245 | .print_power_state = &rv770_dpm_print_power_state, | |
bd210d11 | 1246 | .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1247 | .force_performance_level = &rv770_dpm_force_performance_level, |
b06195d9 | 1248 | .vblank_too_short = &rv770_dpm_vblank_too_short, |
66229b20 | 1249 | }, |
0f9e006c AD |
1250 | .pflip = { |
1251 | .pre_page_flip = &rs600_pre_page_flip, | |
1252 | .page_flip = &rv770_page_flip, | |
1253 | .post_page_flip = &rs600_post_page_flip, | |
1254 | }, | |
48e7a5f1 DV |
1255 | }; |
1256 | ||
76a0df85 CK |
1257 | static struct radeon_asic_ring evergreen_gfx_ring = { |
1258 | .ib_execute = &evergreen_ring_ib_execute, | |
1259 | .emit_fence = &r600_fence_ring_emit, | |
1260 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1261 | .cs_parse = &evergreen_cs_parse, | |
1262 | .ring_test = &r600_ring_test, | |
1263 | .ib_test = &r600_ib_test, | |
1264 | .is_lockup = &evergreen_gfx_is_lockup, | |
1265 | .get_rptr = &radeon_ring_generic_get_rptr, | |
1266 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1267 | .set_wptr = &radeon_ring_generic_set_wptr, | |
1268 | }; | |
1269 | ||
1270 | static struct radeon_asic_ring evergreen_dma_ring = { | |
1271 | .ib_execute = &evergreen_dma_ring_ib_execute, | |
1272 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1273 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1274 | .cs_parse = &evergreen_dma_cs_parse, | |
1275 | .ring_test = &r600_dma_ring_test, | |
1276 | .ib_test = &r600_dma_ib_test, | |
1277 | .is_lockup = &evergreen_dma_is_lockup, | |
2e1e6dad CK |
1278 | .get_rptr = &r600_dma_get_rptr, |
1279 | .get_wptr = &r600_dma_get_wptr, | |
1280 | .set_wptr = &r600_dma_set_wptr, | |
76a0df85 CK |
1281 | }; |
1282 | ||
48e7a5f1 DV |
1283 | static struct radeon_asic evergreen_asic = { |
1284 | .init = &evergreen_init, | |
1285 | .fini = &evergreen_fini, | |
1286 | .suspend = &evergreen_suspend, | |
1287 | .resume = &evergreen_resume, | |
a2d07b74 | 1288 | .asic_reset = &evergreen_asic_reset, |
48e7a5f1 | 1289 | .vga_set_state = &r600_vga_set_state, |
54e88e06 AD |
1290 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1291 | .gui_idle = &r600_gui_idle, | |
1292 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1293 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1294 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1295 | .gart = { |
1296 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1297 | .set_page = &rs600_gart_set_page, | |
1298 | }, | |
4c87bc26 | 1299 | .ring = { |
76a0df85 CK |
1300 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1301 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1302 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1303 | }, |
b35ea4ab AD |
1304 | .irq = { |
1305 | .set = &evergreen_irq_set, | |
1306 | .process = &evergreen_irq_process, | |
1307 | }, | |
c79a49ca AD |
1308 | .display = { |
1309 | .bandwidth_update = &evergreen_bandwidth_update, | |
1310 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1311 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1312 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1313 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1314 | .hdmi_enable = &evergreen_hdmi_enable, |
1315 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1316 | }, |
27cd7769 | 1317 | .copy = { |
8dddb993 | 1318 | .blit = &r600_copy_cpdma, |
27cd7769 | 1319 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1320 | .dma = &evergreen_copy_dma, |
1321 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1322 | .copy = &evergreen_copy_dma, |
1323 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1324 | }, |
9e6f3d02 AD |
1325 | .surface = { |
1326 | .set_reg = r600_set_surface_reg, | |
1327 | .clear_reg = r600_clear_surface_reg, | |
1328 | }, | |
901ea57d AD |
1329 | .hpd = { |
1330 | .init = &evergreen_hpd_init, | |
1331 | .fini = &evergreen_hpd_fini, | |
1332 | .sense = &evergreen_hpd_sense, | |
1333 | .set_polarity = &evergreen_hpd_set_polarity, | |
1334 | }, | |
a02fa397 AD |
1335 | .pm = { |
1336 | .misc = &evergreen_pm_misc, | |
1337 | .prepare = &evergreen_pm_prepare, | |
1338 | .finish = &evergreen_pm_finish, | |
1339 | .init_profile = &r600_pm_init_profile, | |
1340 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1341 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1342 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1343 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1344 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1345 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1346 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1347 | .set_clock_gating = NULL, | |
a8b4925c | 1348 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1349 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1350 | }, |
dc50ba7f AD |
1351 | .dpm = { |
1352 | .init = &cypress_dpm_init, | |
1353 | .setup_asic = &cypress_dpm_setup_asic, | |
1354 | .enable = &cypress_dpm_enable, | |
1355 | .disable = &cypress_dpm_disable, | |
98243917 | 1356 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
dc50ba7f | 1357 | .set_power_state = &cypress_dpm_set_power_state, |
98243917 | 1358 | .post_set_power_state = &r600_dpm_post_set_power_state, |
dc50ba7f AD |
1359 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1360 | .fini = &cypress_dpm_fini, | |
1361 | .get_sclk = &rv770_dpm_get_sclk, | |
1362 | .get_mclk = &rv770_dpm_get_mclk, | |
1363 | .print_power_state = &rv770_dpm_print_power_state, | |
bd210d11 | 1364 | .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1365 | .force_performance_level = &rv770_dpm_force_performance_level, |
d0b54bdc | 1366 | .vblank_too_short = &cypress_dpm_vblank_too_short, |
dc50ba7f | 1367 | }, |
0f9e006c AD |
1368 | .pflip = { |
1369 | .pre_page_flip = &evergreen_pre_page_flip, | |
1370 | .page_flip = &evergreen_page_flip, | |
1371 | .post_page_flip = &evergreen_post_page_flip, | |
1372 | }, | |
48e7a5f1 DV |
1373 | }; |
1374 | ||
958261d1 AD |
1375 | static struct radeon_asic sumo_asic = { |
1376 | .init = &evergreen_init, | |
1377 | .fini = &evergreen_fini, | |
1378 | .suspend = &evergreen_suspend, | |
1379 | .resume = &evergreen_resume, | |
958261d1 AD |
1380 | .asic_reset = &evergreen_asic_reset, |
1381 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1382 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1383 | .gui_idle = &r600_gui_idle, | |
1384 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1385 | .get_xclk = &r600_get_xclk, |
d0418894 | 1386 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1387 | .gart = { |
1388 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1389 | .set_page = &rs600_gart_set_page, | |
1390 | }, | |
4c87bc26 | 1391 | .ring = { |
76a0df85 CK |
1392 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1393 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1394 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1395 | }, |
b35ea4ab AD |
1396 | .irq = { |
1397 | .set = &evergreen_irq_set, | |
1398 | .process = &evergreen_irq_process, | |
1399 | }, | |
c79a49ca AD |
1400 | .display = { |
1401 | .bandwidth_update = &evergreen_bandwidth_update, | |
1402 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1403 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1404 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1405 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1406 | .hdmi_enable = &evergreen_hdmi_enable, |
1407 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1408 | }, |
27cd7769 | 1409 | .copy = { |
8dddb993 | 1410 | .blit = &r600_copy_cpdma, |
27cd7769 | 1411 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1412 | .dma = &evergreen_copy_dma, |
1413 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1414 | .copy = &evergreen_copy_dma, |
1415 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1416 | }, |
9e6f3d02 AD |
1417 | .surface = { |
1418 | .set_reg = r600_set_surface_reg, | |
1419 | .clear_reg = r600_clear_surface_reg, | |
1420 | }, | |
901ea57d AD |
1421 | .hpd = { |
1422 | .init = &evergreen_hpd_init, | |
1423 | .fini = &evergreen_hpd_fini, | |
1424 | .sense = &evergreen_hpd_sense, | |
1425 | .set_polarity = &evergreen_hpd_set_polarity, | |
1426 | }, | |
a02fa397 AD |
1427 | .pm = { |
1428 | .misc = &evergreen_pm_misc, | |
1429 | .prepare = &evergreen_pm_prepare, | |
1430 | .finish = &evergreen_pm_finish, | |
1431 | .init_profile = &sumo_pm_init_profile, | |
1432 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1433 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1434 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1435 | .get_memory_clock = NULL, | |
1436 | .set_memory_clock = NULL, | |
1437 | .get_pcie_lanes = NULL, | |
1438 | .set_pcie_lanes = NULL, | |
1439 | .set_clock_gating = NULL, | |
23d33ba3 | 1440 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
6bd1c385 | 1441 | .get_temperature = &sumo_get_temp, |
a02fa397 | 1442 | }, |
80ea2c12 AD |
1443 | .dpm = { |
1444 | .init = &sumo_dpm_init, | |
1445 | .setup_asic = &sumo_dpm_setup_asic, | |
1446 | .enable = &sumo_dpm_enable, | |
1447 | .disable = &sumo_dpm_disable, | |
422a56bc | 1448 | .pre_set_power_state = &sumo_dpm_pre_set_power_state, |
80ea2c12 | 1449 | .set_power_state = &sumo_dpm_set_power_state, |
422a56bc | 1450 | .post_set_power_state = &sumo_dpm_post_set_power_state, |
80ea2c12 AD |
1451 | .display_configuration_changed = &sumo_dpm_display_configuration_changed, |
1452 | .fini = &sumo_dpm_fini, | |
1453 | .get_sclk = &sumo_dpm_get_sclk, | |
1454 | .get_mclk = &sumo_dpm_get_mclk, | |
1455 | .print_power_state = &sumo_dpm_print_power_state, | |
fb70160c | 1456 | .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, |
5d5e5591 | 1457 | .force_performance_level = &sumo_dpm_force_performance_level, |
80ea2c12 | 1458 | }, |
0f9e006c AD |
1459 | .pflip = { |
1460 | .pre_page_flip = &evergreen_pre_page_flip, | |
1461 | .page_flip = &evergreen_page_flip, | |
1462 | .post_page_flip = &evergreen_post_page_flip, | |
1463 | }, | |
958261d1 AD |
1464 | }; |
1465 | ||
a43b7665 AD |
1466 | static struct radeon_asic btc_asic = { |
1467 | .init = &evergreen_init, | |
1468 | .fini = &evergreen_fini, | |
1469 | .suspend = &evergreen_suspend, | |
1470 | .resume = &evergreen_resume, | |
a43b7665 AD |
1471 | .asic_reset = &evergreen_asic_reset, |
1472 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1473 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1474 | .gui_idle = &r600_gui_idle, | |
1475 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1476 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1477 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1478 | .gart = { |
1479 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1480 | .set_page = &rs600_gart_set_page, | |
1481 | }, | |
4c87bc26 | 1482 | .ring = { |
76a0df85 CK |
1483 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1484 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1485 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1486 | }, |
b35ea4ab AD |
1487 | .irq = { |
1488 | .set = &evergreen_irq_set, | |
1489 | .process = &evergreen_irq_process, | |
1490 | }, | |
c79a49ca AD |
1491 | .display = { |
1492 | .bandwidth_update = &evergreen_bandwidth_update, | |
1493 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1494 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1495 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1496 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1497 | .hdmi_enable = &evergreen_hdmi_enable, |
1498 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1499 | }, |
27cd7769 | 1500 | .copy = { |
8dddb993 | 1501 | .blit = &r600_copy_cpdma, |
27cd7769 | 1502 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1503 | .dma = &evergreen_copy_dma, |
1504 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1505 | .copy = &evergreen_copy_dma, |
1506 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1507 | }, |
9e6f3d02 AD |
1508 | .surface = { |
1509 | .set_reg = r600_set_surface_reg, | |
1510 | .clear_reg = r600_clear_surface_reg, | |
1511 | }, | |
901ea57d AD |
1512 | .hpd = { |
1513 | .init = &evergreen_hpd_init, | |
1514 | .fini = &evergreen_hpd_fini, | |
1515 | .sense = &evergreen_hpd_sense, | |
1516 | .set_polarity = &evergreen_hpd_set_polarity, | |
1517 | }, | |
a02fa397 AD |
1518 | .pm = { |
1519 | .misc = &evergreen_pm_misc, | |
1520 | .prepare = &evergreen_pm_prepare, | |
1521 | .finish = &evergreen_pm_finish, | |
27810fb2 | 1522 | .init_profile = &btc_pm_init_profile, |
a02fa397 | 1523 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
798bcf73 AD |
1524 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1525 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1526 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1527 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1528 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1529 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
798bcf73 | 1530 | .set_clock_gating = NULL, |
a8b4925c | 1531 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1532 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1533 | }, |
6596afd4 AD |
1534 | .dpm = { |
1535 | .init = &btc_dpm_init, | |
1536 | .setup_asic = &btc_dpm_setup_asic, | |
1537 | .enable = &btc_dpm_enable, | |
1538 | .disable = &btc_dpm_disable, | |
e8a9539f | 1539 | .pre_set_power_state = &btc_dpm_pre_set_power_state, |
6596afd4 | 1540 | .set_power_state = &btc_dpm_set_power_state, |
e8a9539f | 1541 | .post_set_power_state = &btc_dpm_post_set_power_state, |
6596afd4 AD |
1542 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1543 | .fini = &btc_dpm_fini, | |
e8a9539f AD |
1544 | .get_sclk = &btc_dpm_get_sclk, |
1545 | .get_mclk = &btc_dpm_get_mclk, | |
6596afd4 | 1546 | .print_power_state = &rv770_dpm_print_power_state, |
bd210d11 | 1547 | .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1548 | .force_performance_level = &rv770_dpm_force_performance_level, |
a84301c6 | 1549 | .vblank_too_short = &btc_dpm_vblank_too_short, |
6596afd4 | 1550 | }, |
0f9e006c AD |
1551 | .pflip = { |
1552 | .pre_page_flip = &evergreen_pre_page_flip, | |
1553 | .page_flip = &evergreen_page_flip, | |
1554 | .post_page_flip = &evergreen_post_page_flip, | |
1555 | }, | |
a43b7665 AD |
1556 | }; |
1557 | ||
76a0df85 CK |
1558 | static struct radeon_asic_ring cayman_gfx_ring = { |
1559 | .ib_execute = &cayman_ring_ib_execute, | |
1560 | .ib_parse = &evergreen_ib_parse, | |
1561 | .emit_fence = &cayman_fence_ring_emit, | |
1562 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1563 | .cs_parse = &evergreen_cs_parse, | |
1564 | .ring_test = &r600_ring_test, | |
1565 | .ib_test = &r600_ib_test, | |
1566 | .is_lockup = &cayman_gfx_is_lockup, | |
1567 | .vm_flush = &cayman_vm_flush, | |
1568 | .get_rptr = &radeon_ring_generic_get_rptr, | |
1569 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1570 | .set_wptr = &radeon_ring_generic_set_wptr, | |
1571 | }; | |
1572 | ||
1573 | static struct radeon_asic_ring cayman_dma_ring = { | |
1574 | .ib_execute = &cayman_dma_ring_ib_execute, | |
1575 | .ib_parse = &evergreen_dma_ib_parse, | |
1576 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1577 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1578 | .cs_parse = &evergreen_dma_cs_parse, | |
1579 | .ring_test = &r600_dma_ring_test, | |
1580 | .ib_test = &r600_dma_ib_test, | |
1581 | .is_lockup = &cayman_dma_is_lockup, | |
1582 | .vm_flush = &cayman_dma_vm_flush, | |
2e1e6dad CK |
1583 | .get_rptr = &r600_dma_get_rptr, |
1584 | .get_wptr = &r600_dma_get_wptr, | |
1585 | .set_wptr = &r600_dma_set_wptr | |
76a0df85 CK |
1586 | }; |
1587 | ||
1588 | static struct radeon_asic_ring cayman_uvd_ring = { | |
1589 | .ib_execute = &r600_uvd_ib_execute, | |
1590 | .emit_fence = &r600_uvd_fence_emit, | |
1591 | .emit_semaphore = &cayman_uvd_semaphore_emit, | |
1592 | .cs_parse = &radeon_uvd_cs_parse, | |
1593 | .ring_test = &r600_uvd_ring_test, | |
1594 | .ib_test = &r600_uvd_ib_test, | |
1595 | .is_lockup = &radeon_ring_test_lockup, | |
02c9f7fa CK |
1596 | .get_rptr = &r600_uvd_get_rptr, |
1597 | .get_wptr = &r600_uvd_get_wptr, | |
1598 | .set_wptr = &r600_uvd_set_wptr, | |
76a0df85 CK |
1599 | }; |
1600 | ||
e3487629 AD |
1601 | static struct radeon_asic cayman_asic = { |
1602 | .init = &cayman_init, | |
1603 | .fini = &cayman_fini, | |
1604 | .suspend = &cayman_suspend, | |
1605 | .resume = &cayman_resume, | |
e3487629 AD |
1606 | .asic_reset = &cayman_asic_reset, |
1607 | .vga_set_state = &r600_vga_set_state, | |
54e88e06 AD |
1608 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1609 | .gui_idle = &r600_gui_idle, | |
1610 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1611 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1612 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1613 | .gart = { |
1614 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1615 | .set_page = &rs600_gart_set_page, | |
1616 | }, | |
05b07147 CK |
1617 | .vm = { |
1618 | .init = &cayman_vm_init, | |
1619 | .fini = &cayman_vm_fini, | |
df160044 | 1620 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
05b07147 CK |
1621 | .set_page = &cayman_vm_set_page, |
1622 | }, | |
4c87bc26 | 1623 | .ring = { |
76a0df85 CK |
1624 | [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, |
1625 | [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, | |
1626 | [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, | |
1627 | [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, | |
1628 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, | |
1629 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
4c87bc26 | 1630 | }, |
b35ea4ab AD |
1631 | .irq = { |
1632 | .set = &evergreen_irq_set, | |
1633 | .process = &evergreen_irq_process, | |
1634 | }, | |
c79a49ca AD |
1635 | .display = { |
1636 | .bandwidth_update = &evergreen_bandwidth_update, | |
1637 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1638 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1639 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1640 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1641 | .hdmi_enable = &evergreen_hdmi_enable, |
1642 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1643 | }, |
27cd7769 | 1644 | .copy = { |
8dddb993 | 1645 | .blit = &r600_copy_cpdma, |
27cd7769 | 1646 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
f60cbd11 AD |
1647 | .dma = &evergreen_copy_dma, |
1648 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1649 | .copy = &evergreen_copy_dma, |
1650 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1651 | }, |
9e6f3d02 AD |
1652 | .surface = { |
1653 | .set_reg = r600_set_surface_reg, | |
1654 | .clear_reg = r600_clear_surface_reg, | |
1655 | }, | |
901ea57d AD |
1656 | .hpd = { |
1657 | .init = &evergreen_hpd_init, | |
1658 | .fini = &evergreen_hpd_fini, | |
1659 | .sense = &evergreen_hpd_sense, | |
1660 | .set_polarity = &evergreen_hpd_set_polarity, | |
1661 | }, | |
a02fa397 AD |
1662 | .pm = { |
1663 | .misc = &evergreen_pm_misc, | |
1664 | .prepare = &evergreen_pm_prepare, | |
1665 | .finish = &evergreen_pm_finish, | |
27810fb2 | 1666 | .init_profile = &btc_pm_init_profile, |
a02fa397 | 1667 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
798bcf73 AD |
1668 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1669 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1670 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1671 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1672 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1673 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
798bcf73 | 1674 | .set_clock_gating = NULL, |
a8b4925c | 1675 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1676 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1677 | }, |
69e0b57a AD |
1678 | .dpm = { |
1679 | .init = &ni_dpm_init, | |
1680 | .setup_asic = &ni_dpm_setup_asic, | |
1681 | .enable = &ni_dpm_enable, | |
1682 | .disable = &ni_dpm_disable, | |
fee3d744 | 1683 | .pre_set_power_state = &ni_dpm_pre_set_power_state, |
69e0b57a | 1684 | .set_power_state = &ni_dpm_set_power_state, |
fee3d744 | 1685 | .post_set_power_state = &ni_dpm_post_set_power_state, |
69e0b57a AD |
1686 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1687 | .fini = &ni_dpm_fini, | |
1688 | .get_sclk = &ni_dpm_get_sclk, | |
1689 | .get_mclk = &ni_dpm_get_mclk, | |
1690 | .print_power_state = &ni_dpm_print_power_state, | |
bdf0c4f0 | 1691 | .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, |
170a47f0 | 1692 | .force_performance_level = &ni_dpm_force_performance_level, |
76ad73e5 | 1693 | .vblank_too_short = &ni_dpm_vblank_too_short, |
69e0b57a | 1694 | }, |
0f9e006c AD |
1695 | .pflip = { |
1696 | .pre_page_flip = &evergreen_pre_page_flip, | |
1697 | .page_flip = &evergreen_page_flip, | |
1698 | .post_page_flip = &evergreen_post_page_flip, | |
1699 | }, | |
e3487629 AD |
1700 | }; |
1701 | ||
be63fe8c AD |
1702 | static struct radeon_asic trinity_asic = { |
1703 | .init = &cayman_init, | |
1704 | .fini = &cayman_fini, | |
1705 | .suspend = &cayman_suspend, | |
1706 | .resume = &cayman_resume, | |
be63fe8c AD |
1707 | .asic_reset = &cayman_asic_reset, |
1708 | .vga_set_state = &r600_vga_set_state, | |
1709 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
1710 | .gui_idle = &r600_gui_idle, | |
1711 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1712 | .get_xclk = &r600_get_xclk, |
d0418894 | 1713 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
be63fe8c AD |
1714 | .gart = { |
1715 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1716 | .set_page = &rs600_gart_set_page, | |
1717 | }, | |
05b07147 CK |
1718 | .vm = { |
1719 | .init = &cayman_vm_init, | |
1720 | .fini = &cayman_vm_fini, | |
df160044 | 1721 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
05b07147 CK |
1722 | .set_page = &cayman_vm_set_page, |
1723 | }, | |
be63fe8c | 1724 | .ring = { |
76a0df85 CK |
1725 | [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, |
1726 | [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, | |
1727 | [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, | |
1728 | [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, | |
1729 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, | |
1730 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
be63fe8c AD |
1731 | }, |
1732 | .irq = { | |
1733 | .set = &evergreen_irq_set, | |
1734 | .process = &evergreen_irq_process, | |
1735 | }, | |
1736 | .display = { | |
1737 | .bandwidth_update = &dce6_bandwidth_update, | |
1738 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1739 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1740 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1741 | .get_backlight_level = &atombios_get_backlight_level, |
be63fe8c AD |
1742 | }, |
1743 | .copy = { | |
8dddb993 | 1744 | .blit = &r600_copy_cpdma, |
be63fe8c | 1745 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
f60cbd11 AD |
1746 | .dma = &evergreen_copy_dma, |
1747 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1748 | .copy = &evergreen_copy_dma, |
1749 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
be63fe8c AD |
1750 | }, |
1751 | .surface = { | |
1752 | .set_reg = r600_set_surface_reg, | |
1753 | .clear_reg = r600_clear_surface_reg, | |
1754 | }, | |
1755 | .hpd = { | |
1756 | .init = &evergreen_hpd_init, | |
1757 | .fini = &evergreen_hpd_fini, | |
1758 | .sense = &evergreen_hpd_sense, | |
1759 | .set_polarity = &evergreen_hpd_set_polarity, | |
1760 | }, | |
1761 | .pm = { | |
1762 | .misc = &evergreen_pm_misc, | |
1763 | .prepare = &evergreen_pm_prepare, | |
1764 | .finish = &evergreen_pm_finish, | |
1765 | .init_profile = &sumo_pm_init_profile, | |
1766 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1767 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1768 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1769 | .get_memory_clock = NULL, | |
1770 | .set_memory_clock = NULL, | |
1771 | .get_pcie_lanes = NULL, | |
1772 | .set_pcie_lanes = NULL, | |
1773 | .set_clock_gating = NULL, | |
23d33ba3 | 1774 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
29a15221 | 1775 | .get_temperature = &tn_get_temp, |
be63fe8c | 1776 | }, |
d70229f7 AD |
1777 | .dpm = { |
1778 | .init = &trinity_dpm_init, | |
1779 | .setup_asic = &trinity_dpm_setup_asic, | |
1780 | .enable = &trinity_dpm_enable, | |
1781 | .disable = &trinity_dpm_disable, | |
a284c48a | 1782 | .pre_set_power_state = &trinity_dpm_pre_set_power_state, |
d70229f7 | 1783 | .set_power_state = &trinity_dpm_set_power_state, |
a284c48a | 1784 | .post_set_power_state = &trinity_dpm_post_set_power_state, |
d70229f7 AD |
1785 | .display_configuration_changed = &trinity_dpm_display_configuration_changed, |
1786 | .fini = &trinity_dpm_fini, | |
1787 | .get_sclk = &trinity_dpm_get_sclk, | |
1788 | .get_mclk = &trinity_dpm_get_mclk, | |
1789 | .print_power_state = &trinity_dpm_print_power_state, | |
490ab931 | 1790 | .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, |
9b5de596 | 1791 | .force_performance_level = &trinity_dpm_force_performance_level, |
d70229f7 | 1792 | }, |
be63fe8c AD |
1793 | .pflip = { |
1794 | .pre_page_flip = &evergreen_pre_page_flip, | |
1795 | .page_flip = &evergreen_page_flip, | |
1796 | .post_page_flip = &evergreen_post_page_flip, | |
1797 | }, | |
1798 | }; | |
1799 | ||
76a0df85 CK |
1800 | static struct radeon_asic_ring si_gfx_ring = { |
1801 | .ib_execute = &si_ring_ib_execute, | |
1802 | .ib_parse = &si_ib_parse, | |
1803 | .emit_fence = &si_fence_ring_emit, | |
1804 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1805 | .cs_parse = NULL, | |
1806 | .ring_test = &r600_ring_test, | |
1807 | .ib_test = &r600_ib_test, | |
1808 | .is_lockup = &si_gfx_is_lockup, | |
1809 | .vm_flush = &si_vm_flush, | |
1810 | .get_rptr = &radeon_ring_generic_get_rptr, | |
1811 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1812 | .set_wptr = &radeon_ring_generic_set_wptr, | |
1813 | }; | |
1814 | ||
1815 | static struct radeon_asic_ring si_dma_ring = { | |
1816 | .ib_execute = &cayman_dma_ring_ib_execute, | |
1817 | .ib_parse = &evergreen_dma_ib_parse, | |
1818 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1819 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1820 | .cs_parse = NULL, | |
1821 | .ring_test = &r600_dma_ring_test, | |
1822 | .ib_test = &r600_dma_ib_test, | |
1823 | .is_lockup = &si_dma_is_lockup, | |
1824 | .vm_flush = &si_dma_vm_flush, | |
2e1e6dad CK |
1825 | .get_rptr = &r600_dma_get_rptr, |
1826 | .get_wptr = &r600_dma_get_wptr, | |
1827 | .set_wptr = &r600_dma_set_wptr, | |
76a0df85 CK |
1828 | }; |
1829 | ||
02779c08 AD |
1830 | static struct radeon_asic si_asic = { |
1831 | .init = &si_init, | |
1832 | .fini = &si_fini, | |
1833 | .suspend = &si_suspend, | |
1834 | .resume = &si_resume, | |
02779c08 AD |
1835 | .asic_reset = &si_asic_reset, |
1836 | .vga_set_state = &r600_vga_set_state, | |
1837 | .ioctl_wait_idle = r600_ioctl_wait_idle, | |
1838 | .gui_idle = &r600_gui_idle, | |
1839 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1840 | .get_xclk = &si_get_xclk, |
d0418894 | 1841 | .get_gpu_clock_counter = &si_get_gpu_clock_counter, |
02779c08 AD |
1842 | .gart = { |
1843 | .tlb_flush = &si_pcie_gart_tlb_flush, | |
1844 | .set_page = &rs600_gart_set_page, | |
1845 | }, | |
05b07147 CK |
1846 | .vm = { |
1847 | .init = &si_vm_init, | |
1848 | .fini = &si_vm_fini, | |
df160044 | 1849 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, |
82ffd92b | 1850 | .set_page = &si_vm_set_page, |
05b07147 | 1851 | }, |
02779c08 | 1852 | .ring = { |
76a0df85 CK |
1853 | [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, |
1854 | [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, | |
1855 | [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, | |
1856 | [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, | |
1857 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, | |
1858 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
02779c08 AD |
1859 | }, |
1860 | .irq = { | |
1861 | .set = &si_irq_set, | |
1862 | .process = &si_irq_process, | |
1863 | }, | |
1864 | .display = { | |
1865 | .bandwidth_update = &dce6_bandwidth_update, | |
1866 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1867 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1868 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1869 | .get_backlight_level = &atombios_get_backlight_level, |
02779c08 AD |
1870 | }, |
1871 | .copy = { | |
1872 | .blit = NULL, | |
1873 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
8c5fd7ef AD |
1874 | .dma = &si_copy_dma, |
1875 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1876 | .copy = &si_copy_dma, |
1877 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
02779c08 AD |
1878 | }, |
1879 | .surface = { | |
1880 | .set_reg = r600_set_surface_reg, | |
1881 | .clear_reg = r600_clear_surface_reg, | |
1882 | }, | |
1883 | .hpd = { | |
1884 | .init = &evergreen_hpd_init, | |
1885 | .fini = &evergreen_hpd_fini, | |
1886 | .sense = &evergreen_hpd_sense, | |
1887 | .set_polarity = &evergreen_hpd_set_polarity, | |
1888 | }, | |
1889 | .pm = { | |
1890 | .misc = &evergreen_pm_misc, | |
1891 | .prepare = &evergreen_pm_prepare, | |
1892 | .finish = &evergreen_pm_finish, | |
1893 | .init_profile = &sumo_pm_init_profile, | |
1894 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1895 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1896 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1897 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1898 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1899 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1900 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
02779c08 | 1901 | .set_clock_gating = NULL, |
2539eb02 | 1902 | .set_uvd_clocks = &si_set_uvd_clocks, |
6bd1c385 | 1903 | .get_temperature = &si_get_temp, |
02779c08 | 1904 | }, |
a9e61410 AD |
1905 | .dpm = { |
1906 | .init = &si_dpm_init, | |
1907 | .setup_asic = &si_dpm_setup_asic, | |
1908 | .enable = &si_dpm_enable, | |
1909 | .disable = &si_dpm_disable, | |
1910 | .pre_set_power_state = &si_dpm_pre_set_power_state, | |
1911 | .set_power_state = &si_dpm_set_power_state, | |
1912 | .post_set_power_state = &si_dpm_post_set_power_state, | |
1913 | .display_configuration_changed = &si_dpm_display_configuration_changed, | |
1914 | .fini = &si_dpm_fini, | |
1915 | .get_sclk = &ni_dpm_get_sclk, | |
1916 | .get_mclk = &ni_dpm_get_mclk, | |
1917 | .print_power_state = &ni_dpm_print_power_state, | |
7982128c | 1918 | .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, |
a160a6a3 | 1919 | .force_performance_level = &si_dpm_force_performance_level, |
f4dec318 | 1920 | .vblank_too_short = &ni_dpm_vblank_too_short, |
a9e61410 | 1921 | }, |
02779c08 AD |
1922 | .pflip = { |
1923 | .pre_page_flip = &evergreen_pre_page_flip, | |
1924 | .page_flip = &evergreen_page_flip, | |
1925 | .post_page_flip = &evergreen_post_page_flip, | |
1926 | }, | |
1927 | }; | |
1928 | ||
76a0df85 CK |
1929 | static struct radeon_asic_ring ci_gfx_ring = { |
1930 | .ib_execute = &cik_ring_ib_execute, | |
1931 | .ib_parse = &cik_ib_parse, | |
1932 | .emit_fence = &cik_fence_gfx_ring_emit, | |
1933 | .emit_semaphore = &cik_semaphore_ring_emit, | |
1934 | .cs_parse = NULL, | |
1935 | .ring_test = &cik_ring_test, | |
1936 | .ib_test = &cik_ib_test, | |
1937 | .is_lockup = &cik_gfx_is_lockup, | |
1938 | .vm_flush = &cik_vm_flush, | |
1939 | .get_rptr = &radeon_ring_generic_get_rptr, | |
1940 | .get_wptr = &radeon_ring_generic_get_wptr, | |
1941 | .set_wptr = &radeon_ring_generic_set_wptr, | |
1942 | }; | |
1943 | ||
1944 | static struct radeon_asic_ring ci_cp_ring = { | |
1945 | .ib_execute = &cik_ring_ib_execute, | |
1946 | .ib_parse = &cik_ib_parse, | |
1947 | .emit_fence = &cik_fence_compute_ring_emit, | |
1948 | .emit_semaphore = &cik_semaphore_ring_emit, | |
1949 | .cs_parse = NULL, | |
1950 | .ring_test = &cik_ring_test, | |
1951 | .ib_test = &cik_ib_test, | |
1952 | .is_lockup = &cik_gfx_is_lockup, | |
1953 | .vm_flush = &cik_vm_flush, | |
1954 | .get_rptr = &cik_compute_ring_get_rptr, | |
1955 | .get_wptr = &cik_compute_ring_get_wptr, | |
1956 | .set_wptr = &cik_compute_ring_set_wptr, | |
1957 | }; | |
1958 | ||
1959 | static struct radeon_asic_ring ci_dma_ring = { | |
1960 | .ib_execute = &cik_sdma_ring_ib_execute, | |
1961 | .ib_parse = &cik_ib_parse, | |
1962 | .emit_fence = &cik_sdma_fence_ring_emit, | |
1963 | .emit_semaphore = &cik_sdma_semaphore_ring_emit, | |
1964 | .cs_parse = NULL, | |
1965 | .ring_test = &cik_sdma_ring_test, | |
1966 | .ib_test = &cik_sdma_ib_test, | |
1967 | .is_lockup = &cik_sdma_is_lockup, | |
1968 | .vm_flush = &cik_dma_vm_flush, | |
2e1e6dad CK |
1969 | .get_rptr = &r600_dma_get_rptr, |
1970 | .get_wptr = &r600_dma_get_wptr, | |
1971 | .set_wptr = &r600_dma_set_wptr, | |
76a0df85 CK |
1972 | }; |
1973 | ||
0672e27b AD |
1974 | static struct radeon_asic ci_asic = { |
1975 | .init = &cik_init, | |
1976 | .fini = &cik_fini, | |
1977 | .suspend = &cik_suspend, | |
1978 | .resume = &cik_resume, | |
1979 | .asic_reset = &cik_asic_reset, | |
1980 | .vga_set_state = &r600_vga_set_state, | |
1981 | .ioctl_wait_idle = NULL, | |
1982 | .gui_idle = &r600_gui_idle, | |
1983 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
1984 | .get_xclk = &cik_get_xclk, | |
1985 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | |
1986 | .gart = { | |
1987 | .tlb_flush = &cik_pcie_gart_tlb_flush, | |
1988 | .set_page = &rs600_gart_set_page, | |
1989 | }, | |
1990 | .vm = { | |
1991 | .init = &cik_vm_init, | |
1992 | .fini = &cik_vm_fini, | |
1993 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, | |
1994 | .set_page = &cik_vm_set_page, | |
1995 | }, | |
1996 | .ring = { | |
76a0df85 CK |
1997 | [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, |
1998 | [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, | |
1999 | [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, | |
2000 | [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, | |
2001 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, | |
2002 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
0672e27b AD |
2003 | }, |
2004 | .irq = { | |
2005 | .set = &cik_irq_set, | |
2006 | .process = &cik_irq_process, | |
2007 | }, | |
2008 | .display = { | |
2009 | .bandwidth_update = &dce8_bandwidth_update, | |
2010 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2011 | .wait_for_vblank = &dce4_wait_for_vblank, | |
2012 | }, | |
2013 | .copy = { | |
2014 | .blit = NULL, | |
2015 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
2016 | .dma = &cik_copy_dma, | |
2017 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2018 | .copy = &cik_copy_dma, | |
2019 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2020 | }, | |
2021 | .surface = { | |
2022 | .set_reg = r600_set_surface_reg, | |
2023 | .clear_reg = r600_clear_surface_reg, | |
2024 | }, | |
2025 | .hpd = { | |
2026 | .init = &evergreen_hpd_init, | |
2027 | .fini = &evergreen_hpd_fini, | |
2028 | .sense = &evergreen_hpd_sense, | |
2029 | .set_polarity = &evergreen_hpd_set_polarity, | |
2030 | }, | |
2031 | .pm = { | |
2032 | .misc = &evergreen_pm_misc, | |
2033 | .prepare = &evergreen_pm_prepare, | |
2034 | .finish = &evergreen_pm_finish, | |
2035 | .init_profile = &sumo_pm_init_profile, | |
2036 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2037 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2038 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2039 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
2040 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
2041 | .get_pcie_lanes = NULL, | |
2042 | .set_pcie_lanes = NULL, | |
2043 | .set_clock_gating = NULL, | |
2044 | .set_uvd_clocks = &cik_set_uvd_clocks, | |
286d9cc6 | 2045 | .get_temperature = &ci_get_temp, |
0672e27b | 2046 | }, |
cc8dbbb4 AD |
2047 | .dpm = { |
2048 | .init = &ci_dpm_init, | |
2049 | .setup_asic = &ci_dpm_setup_asic, | |
2050 | .enable = &ci_dpm_enable, | |
2051 | .disable = &ci_dpm_disable, | |
2052 | .pre_set_power_state = &ci_dpm_pre_set_power_state, | |
2053 | .set_power_state = &ci_dpm_set_power_state, | |
2054 | .post_set_power_state = &ci_dpm_post_set_power_state, | |
2055 | .display_configuration_changed = &ci_dpm_display_configuration_changed, | |
2056 | .fini = &ci_dpm_fini, | |
2057 | .get_sclk = &ci_dpm_get_sclk, | |
2058 | .get_mclk = &ci_dpm_get_mclk, | |
2059 | .print_power_state = &ci_dpm_print_power_state, | |
94b4adc5 | 2060 | .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, |
89536fd6 | 2061 | .force_performance_level = &ci_dpm_force_performance_level, |
5496131e | 2062 | .vblank_too_short = &ci_dpm_vblank_too_short, |
942bdf7f | 2063 | .powergate_uvd = &ci_dpm_powergate_uvd, |
cc8dbbb4 | 2064 | }, |
0672e27b AD |
2065 | .pflip = { |
2066 | .pre_page_flip = &evergreen_pre_page_flip, | |
2067 | .page_flip = &evergreen_page_flip, | |
2068 | .post_page_flip = &evergreen_post_page_flip, | |
2069 | }, | |
2070 | }; | |
2071 | ||
2072 | static struct radeon_asic kv_asic = { | |
2073 | .init = &cik_init, | |
2074 | .fini = &cik_fini, | |
2075 | .suspend = &cik_suspend, | |
2076 | .resume = &cik_resume, | |
2077 | .asic_reset = &cik_asic_reset, | |
2078 | .vga_set_state = &r600_vga_set_state, | |
2079 | .ioctl_wait_idle = NULL, | |
2080 | .gui_idle = &r600_gui_idle, | |
2081 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
2082 | .get_xclk = &cik_get_xclk, | |
2083 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | |
2084 | .gart = { | |
2085 | .tlb_flush = &cik_pcie_gart_tlb_flush, | |
2086 | .set_page = &rs600_gart_set_page, | |
2087 | }, | |
2088 | .vm = { | |
2089 | .init = &cik_vm_init, | |
2090 | .fini = &cik_vm_fini, | |
2091 | .pt_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2092 | .set_page = &cik_vm_set_page, | |
2093 | }, | |
2094 | .ring = { | |
76a0df85 CK |
2095 | [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, |
2096 | [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, | |
2097 | [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, | |
2098 | [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, | |
2099 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, | |
2100 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
0672e27b AD |
2101 | }, |
2102 | .irq = { | |
2103 | .set = &cik_irq_set, | |
2104 | .process = &cik_irq_process, | |
2105 | }, | |
2106 | .display = { | |
2107 | .bandwidth_update = &dce8_bandwidth_update, | |
2108 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2109 | .wait_for_vblank = &dce4_wait_for_vblank, | |
2110 | }, | |
2111 | .copy = { | |
2112 | .blit = NULL, | |
2113 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
2114 | .dma = &cik_copy_dma, | |
2115 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2116 | .copy = &cik_copy_dma, | |
2117 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2118 | }, | |
2119 | .surface = { | |
2120 | .set_reg = r600_set_surface_reg, | |
2121 | .clear_reg = r600_clear_surface_reg, | |
2122 | }, | |
2123 | .hpd = { | |
2124 | .init = &evergreen_hpd_init, | |
2125 | .fini = &evergreen_hpd_fini, | |
2126 | .sense = &evergreen_hpd_sense, | |
2127 | .set_polarity = &evergreen_hpd_set_polarity, | |
2128 | }, | |
2129 | .pm = { | |
2130 | .misc = &evergreen_pm_misc, | |
2131 | .prepare = &evergreen_pm_prepare, | |
2132 | .finish = &evergreen_pm_finish, | |
2133 | .init_profile = &sumo_pm_init_profile, | |
2134 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2135 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2136 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2137 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
2138 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
2139 | .get_pcie_lanes = NULL, | |
2140 | .set_pcie_lanes = NULL, | |
2141 | .set_clock_gating = NULL, | |
2142 | .set_uvd_clocks = &cik_set_uvd_clocks, | |
286d9cc6 | 2143 | .get_temperature = &kv_get_temp, |
0672e27b | 2144 | }, |
41a524ab AD |
2145 | .dpm = { |
2146 | .init = &kv_dpm_init, | |
2147 | .setup_asic = &kv_dpm_setup_asic, | |
2148 | .enable = &kv_dpm_enable, | |
2149 | .disable = &kv_dpm_disable, | |
2150 | .pre_set_power_state = &kv_dpm_pre_set_power_state, | |
2151 | .set_power_state = &kv_dpm_set_power_state, | |
2152 | .post_set_power_state = &kv_dpm_post_set_power_state, | |
2153 | .display_configuration_changed = &kv_dpm_display_configuration_changed, | |
2154 | .fini = &kv_dpm_fini, | |
2155 | .get_sclk = &kv_dpm_get_sclk, | |
2156 | .get_mclk = &kv_dpm_get_mclk, | |
2157 | .print_power_state = &kv_dpm_print_power_state, | |
ae3e40e8 | 2158 | .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, |
2b4c8022 | 2159 | .force_performance_level = &kv_dpm_force_performance_level, |
77df508a | 2160 | .powergate_uvd = &kv_dpm_powergate_uvd, |
41a524ab | 2161 | }, |
0672e27b AD |
2162 | .pflip = { |
2163 | .pre_page_flip = &evergreen_pre_page_flip, | |
2164 | .page_flip = &evergreen_page_flip, | |
2165 | .post_page_flip = &evergreen_post_page_flip, | |
2166 | }, | |
2167 | }; | |
2168 | ||
abf1dc67 AD |
2169 | /** |
2170 | * radeon_asic_init - register asic specific callbacks | |
2171 | * | |
2172 | * @rdev: radeon device pointer | |
2173 | * | |
2174 | * Registers the appropriate asic specific callbacks for each | |
2175 | * chip family. Also sets other asics specific info like the number | |
2176 | * of crtcs and the register aperture accessors (all asics). | |
2177 | * Returns 0 for success. | |
2178 | */ | |
0a10c851 DV |
2179 | int radeon_asic_init(struct radeon_device *rdev) |
2180 | { | |
2181 | radeon_register_accessor_init(rdev); | |
ba7e05e9 AD |
2182 | |
2183 | /* set the number of crtcs */ | |
2184 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
2185 | rdev->num_crtc = 1; | |
2186 | else | |
2187 | rdev->num_crtc = 2; | |
2188 | ||
948bee3f AD |
2189 | rdev->has_uvd = false; |
2190 | ||
0a10c851 DV |
2191 | switch (rdev->family) { |
2192 | case CHIP_R100: | |
2193 | case CHIP_RV100: | |
2194 | case CHIP_RS100: | |
2195 | case CHIP_RV200: | |
2196 | case CHIP_RS200: | |
2197 | rdev->asic = &r100_asic; | |
2198 | break; | |
2199 | case CHIP_R200: | |
2200 | case CHIP_RV250: | |
2201 | case CHIP_RS300: | |
2202 | case CHIP_RV280: | |
2203 | rdev->asic = &r200_asic; | |
2204 | break; | |
2205 | case CHIP_R300: | |
2206 | case CHIP_R350: | |
2207 | case CHIP_RV350: | |
2208 | case CHIP_RV380: | |
2209 | if (rdev->flags & RADEON_IS_PCIE) | |
2210 | rdev->asic = &r300_asic_pcie; | |
2211 | else | |
2212 | rdev->asic = &r300_asic; | |
2213 | break; | |
2214 | case CHIP_R420: | |
2215 | case CHIP_R423: | |
2216 | case CHIP_RV410: | |
2217 | rdev->asic = &r420_asic; | |
07bb084c AD |
2218 | /* handle macs */ |
2219 | if (rdev->bios == NULL) { | |
798bcf73 AD |
2220 | rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; |
2221 | rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; | |
2222 | rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; | |
2223 | rdev->asic->pm.set_memory_clock = NULL; | |
37e9b6a6 | 2224 | rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; |
07bb084c | 2225 | } |
0a10c851 DV |
2226 | break; |
2227 | case CHIP_RS400: | |
2228 | case CHIP_RS480: | |
2229 | rdev->asic = &rs400_asic; | |
2230 | break; | |
2231 | case CHIP_RS600: | |
2232 | rdev->asic = &rs600_asic; | |
2233 | break; | |
2234 | case CHIP_RS690: | |
2235 | case CHIP_RS740: | |
2236 | rdev->asic = &rs690_asic; | |
2237 | break; | |
2238 | case CHIP_RV515: | |
2239 | rdev->asic = &rv515_asic; | |
2240 | break; | |
2241 | case CHIP_R520: | |
2242 | case CHIP_RV530: | |
2243 | case CHIP_RV560: | |
2244 | case CHIP_RV570: | |
2245 | case CHIP_R580: | |
2246 | rdev->asic = &r520_asic; | |
2247 | break; | |
2248 | case CHIP_R600: | |
ca361b65 AD |
2249 | rdev->asic = &r600_asic; |
2250 | break; | |
0a10c851 DV |
2251 | case CHIP_RV610: |
2252 | case CHIP_RV630: | |
2253 | case CHIP_RV620: | |
2254 | case CHIP_RV635: | |
2255 | case CHIP_RV670: | |
ca361b65 AD |
2256 | rdev->asic = &rv6xx_asic; |
2257 | rdev->has_uvd = true; | |
f47299c5 | 2258 | break; |
0a10c851 DV |
2259 | case CHIP_RS780: |
2260 | case CHIP_RS880: | |
f47299c5 | 2261 | rdev->asic = &rs780_asic; |
948bee3f | 2262 | rdev->has_uvd = true; |
0a10c851 DV |
2263 | break; |
2264 | case CHIP_RV770: | |
2265 | case CHIP_RV730: | |
2266 | case CHIP_RV710: | |
2267 | case CHIP_RV740: | |
2268 | rdev->asic = &rv770_asic; | |
948bee3f | 2269 | rdev->has_uvd = true; |
0a10c851 DV |
2270 | break; |
2271 | case CHIP_CEDAR: | |
2272 | case CHIP_REDWOOD: | |
2273 | case CHIP_JUNIPER: | |
2274 | case CHIP_CYPRESS: | |
2275 | case CHIP_HEMLOCK: | |
ba7e05e9 AD |
2276 | /* set num crtcs */ |
2277 | if (rdev->family == CHIP_CEDAR) | |
2278 | rdev->num_crtc = 4; | |
2279 | else | |
2280 | rdev->num_crtc = 6; | |
0a10c851 | 2281 | rdev->asic = &evergreen_asic; |
948bee3f | 2282 | rdev->has_uvd = true; |
0a10c851 | 2283 | break; |
958261d1 | 2284 | case CHIP_PALM: |
89da5a37 AD |
2285 | case CHIP_SUMO: |
2286 | case CHIP_SUMO2: | |
958261d1 | 2287 | rdev->asic = &sumo_asic; |
948bee3f | 2288 | rdev->has_uvd = true; |
958261d1 | 2289 | break; |
a43b7665 AD |
2290 | case CHIP_BARTS: |
2291 | case CHIP_TURKS: | |
2292 | case CHIP_CAICOS: | |
ba7e05e9 AD |
2293 | /* set num crtcs */ |
2294 | if (rdev->family == CHIP_CAICOS) | |
2295 | rdev->num_crtc = 4; | |
2296 | else | |
2297 | rdev->num_crtc = 6; | |
a43b7665 | 2298 | rdev->asic = &btc_asic; |
948bee3f | 2299 | rdev->has_uvd = true; |
a43b7665 | 2300 | break; |
e3487629 AD |
2301 | case CHIP_CAYMAN: |
2302 | rdev->asic = &cayman_asic; | |
ba7e05e9 AD |
2303 | /* set num crtcs */ |
2304 | rdev->num_crtc = 6; | |
948bee3f | 2305 | rdev->has_uvd = true; |
e3487629 | 2306 | break; |
be63fe8c AD |
2307 | case CHIP_ARUBA: |
2308 | rdev->asic = &trinity_asic; | |
2309 | /* set num crtcs */ | |
2310 | rdev->num_crtc = 4; | |
948bee3f | 2311 | rdev->has_uvd = true; |
be63fe8c | 2312 | break; |
02779c08 AD |
2313 | case CHIP_TAHITI: |
2314 | case CHIP_PITCAIRN: | |
2315 | case CHIP_VERDE: | |
e737a14c | 2316 | case CHIP_OLAND: |
86a45cac | 2317 | case CHIP_HAINAN: |
02779c08 AD |
2318 | rdev->asic = &si_asic; |
2319 | /* set num crtcs */ | |
86a45cac AD |
2320 | if (rdev->family == CHIP_HAINAN) |
2321 | rdev->num_crtc = 0; | |
2322 | else if (rdev->family == CHIP_OLAND) | |
e737a14c AD |
2323 | rdev->num_crtc = 2; |
2324 | else | |
2325 | rdev->num_crtc = 6; | |
948bee3f AD |
2326 | if (rdev->family == CHIP_HAINAN) |
2327 | rdev->has_uvd = false; | |
2328 | else | |
2329 | rdev->has_uvd = true; | |
02779c08 | 2330 | break; |
0672e27b AD |
2331 | case CHIP_BONAIRE: |
2332 | rdev->asic = &ci_asic; | |
2333 | rdev->num_crtc = 6; | |
22c775ce | 2334 | rdev->has_uvd = true; |
0672e27b AD |
2335 | break; |
2336 | case CHIP_KAVERI: | |
2337 | case CHIP_KABINI: | |
2338 | rdev->asic = &kv_asic; | |
2339 | /* set num crtcs */ | |
2340 | if (rdev->family == CHIP_KAVERI) | |
2341 | rdev->num_crtc = 4; | |
2342 | else | |
2343 | rdev->num_crtc = 2; | |
22c775ce | 2344 | rdev->has_uvd = true; |
0672e27b | 2345 | break; |
0a10c851 DV |
2346 | default: |
2347 | /* FIXME: not supported yet */ | |
2348 | return -EINVAL; | |
2349 | } | |
2350 | ||
2351 | if (rdev->flags & RADEON_IS_IGP) { | |
798bcf73 AD |
2352 | rdev->asic->pm.get_memory_clock = NULL; |
2353 | rdev->asic->pm.set_memory_clock = NULL; | |
0a10c851 DV |
2354 | } |
2355 | ||
2356 | return 0; | |
2357 | } | |
2358 |