projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon/dpm: add vce support for SI
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
abf1dc67
AD		 43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
0a10c851
DV		 53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
abf1dc67
AD		 60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
0a10c851
DV		 70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
abf1dc67
AD		 77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
0a10c851
DV		 85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
65337e60
SL		 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
6e2c3c0a
AD		 129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
0a10c851
DV		 134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
18b53e90
AD		 139static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
140 u32 reg, u32 *val)
141{
142 return -EINVAL;
143}
0a10c851
DV		 144
145/* helper to disable agp */
abf1dc67
AD		 146/**
147 * radeon_agp_disable - AGP disable helper function
148 *
149 * @rdev: radeon device pointer
150 *
151 * Removes AGP flags and changes the gart callbacks on AGP
152 * cards when using the internal gart rather than AGP (all asics).
153 */
0a10c851
DV		 154void radeon_agp_disable(struct radeon_device *rdev)
155{
156 rdev->flags &= ~RADEON_IS_AGP;
157 if (rdev->family >= CHIP_R600) {
158 DRM_INFO("Forcing AGP to PCIE mode\n");
159 rdev->flags |= RADEON_IS_PCIE;
160 } else if (rdev->family >= CHIP_RV515 ||
161 rdev->family == CHIP_RV380 ||
162 rdev->family == CHIP_RV410 ||
163 rdev->family == CHIP_R423) {
164 DRM_INFO("Forcing AGP to PCIE mode\n");
165 rdev->flags |= RADEON_IS_PCIE;
c5b3b850 166 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
cb658906 167 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
c5b3b850 168 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0a10c851
DV		 169 } else {
170 DRM_INFO("Forcing AGP to PCI mode\n");
171 rdev->flags |= RADEON_IS_PCI;
c5b3b850 172 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
cb658906 173 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
c5b3b850 174 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0a10c851
DV		 175 }
176 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
177}
178
179/*
180 * ASIC
181 */
76a0df85
CK		 182
183static struct radeon_asic_ring r100_gfx_ring = {
184 .ib_execute = &r100_ring_ib_execute,
185 .emit_fence = &r100_fence_ring_emit,
186 .emit_semaphore = &r100_semaphore_ring_emit,
187 .cs_parse = &r100_cs_parse,
188 .ring_start = &r100_ring_start,
189 .ring_test = &r100_ring_test,
190 .ib_test = &r100_ib_test,
191 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 192 .get_rptr = &r100_gfx_get_rptr,
193 .get_wptr = &r100_gfx_get_wptr,
194 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 195};
196
48e7a5f1
DV		 197static struct radeon_asic r100_asic = {
198 .init = &r100_init,
199 .fini = &r100_fini,
200 .suspend = &r100_suspend,
201 .resume = &r100_resume,
202 .vga_set_state = &r100_vga_set_state,
a2d07b74 203 .asic_reset = &r100_asic_reset,
124764f1 204 .mmio_hdp_flush = NULL,
54e88e06
AD		 205 .gui_idle = &r100_gui_idle,
206 .mc_wait_for_idle = &r100_mc_wait_for_idle,
18b53e90 207 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 208 .gart = {
209 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 210 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 211 .set_page = &r100_pci_gart_set_page,
212 },
4c87bc26 213 .ring = {
76a0df85 214 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 215 },
b35ea4ab
AD		 216 .irq = {
217 .set = &r100_irq_set,
218 .process = &r100_irq_process,
219 },
c79a49ca
AD		 220 .display = {
221 .bandwidth_update = &r100_bandwidth_update,
222 .get_vblank_counter = &r100_get_vblank_counter,
223 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 224 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 225 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 226 },
27cd7769
AD		 227 .copy = {
228 .blit = &r100_copy_blit,
229 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
230 .dma = NULL,
231 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
232 .copy = &r100_copy_blit,
233 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
234 },
9e6f3d02
AD		 235 .surface = {
236 .set_reg = r100_set_surface_reg,
237 .clear_reg = r100_clear_surface_reg,
238 },
901ea57d
AD		 239 .hpd = {
240 .init = &r100_hpd_init,
241 .fini = &r100_hpd_fini,
242 .sense = &r100_hpd_sense,
243 .set_polarity = &r100_hpd_set_polarity,
244 },
a02fa397
AD		 245 .pm = {
246 .misc = &r100_pm_misc,
247 .prepare = &r100_pm_prepare,
248 .finish = &r100_pm_finish,
249 .init_profile = &r100_pm_init_profile,
250 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 251 .get_engine_clock = &radeon_legacy_get_engine_clock,
252 .set_engine_clock = &radeon_legacy_set_engine_clock,
253 .get_memory_clock = &radeon_legacy_get_memory_clock,
254 .set_memory_clock = NULL,
255 .get_pcie_lanes = NULL,
256 .set_pcie_lanes = NULL,
257 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 258 },
0f9e006c 259 .pflip = {
0f9e006c 260 .page_flip = &r100_page_flip,
157fa14d 261 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 262 },
48e7a5f1
DV		 263};
264
265static struct radeon_asic r200_asic = {
266 .init = &r100_init,
267 .fini = &r100_fini,
268 .suspend = &r100_suspend,
269 .resume = &r100_resume,
270 .vga_set_state = &r100_vga_set_state,
a2d07b74 271 .asic_reset = &r100_asic_reset,
124764f1 272 .mmio_hdp_flush = NULL,
54e88e06
AD		 273 .gui_idle = &r100_gui_idle,
274 .mc_wait_for_idle = &r100_mc_wait_for_idle,
18b53e90 275 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 276 .gart = {
277 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 278 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 279 .set_page = &r100_pci_gart_set_page,
280 },
4c87bc26 281 .ring = {
76a0df85 282 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 283 },
b35ea4ab
AD		 284 .irq = {
285 .set = &r100_irq_set,
286 .process = &r100_irq_process,
287 },
c79a49ca
AD		 288 .display = {
289 .bandwidth_update = &r100_bandwidth_update,
290 .get_vblank_counter = &r100_get_vblank_counter,
291 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 292 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 293 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 294 },
27cd7769
AD		 295 .copy = {
296 .blit = &r100_copy_blit,
297 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
298 .dma = &r200_copy_dma,
299 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
300 .copy = &r100_copy_blit,
301 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
302 },
9e6f3d02
AD		 303 .surface = {
304 .set_reg = r100_set_surface_reg,
305 .clear_reg = r100_clear_surface_reg,
306 },
901ea57d
AD		 307 .hpd = {
308 .init = &r100_hpd_init,
309 .fini = &r100_hpd_fini,
310 .sense = &r100_hpd_sense,
311 .set_polarity = &r100_hpd_set_polarity,
312 },
a02fa397
AD		 313 .pm = {
314 .misc = &r100_pm_misc,
315 .prepare = &r100_pm_prepare,
316 .finish = &r100_pm_finish,
317 .init_profile = &r100_pm_init_profile,
318 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 319 .get_engine_clock = &radeon_legacy_get_engine_clock,
320 .set_engine_clock = &radeon_legacy_set_engine_clock,
321 .get_memory_clock = &radeon_legacy_get_memory_clock,
322 .set_memory_clock = NULL,
323 .get_pcie_lanes = NULL,
324 .set_pcie_lanes = NULL,
325 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 326 },
0f9e006c 327 .pflip = {
0f9e006c 328 .page_flip = &r100_page_flip,
157fa14d 329 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 330 },
48e7a5f1
DV		 331};
332
76a0df85
CK		 333static struct radeon_asic_ring r300_gfx_ring = {
334 .ib_execute = &r100_ring_ib_execute,
335 .emit_fence = &r300_fence_ring_emit,
336 .emit_semaphore = &r100_semaphore_ring_emit,
337 .cs_parse = &r300_cs_parse,
338 .ring_start = &r300_ring_start,
339 .ring_test = &r100_ring_test,
340 .ib_test = &r100_ib_test,
341 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 342 .get_rptr = &r100_gfx_get_rptr,
343 .get_wptr = &r100_gfx_get_wptr,
344 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 345};
346
d8a74e18
AD		 347static struct radeon_asic_ring rv515_gfx_ring = {
348 .ib_execute = &r100_ring_ib_execute,
349 .emit_fence = &r300_fence_ring_emit,
350 .emit_semaphore = &r100_semaphore_ring_emit,
351 .cs_parse = &r300_cs_parse,
352 .ring_start = &rv515_ring_start,
353 .ring_test = &r100_ring_test,
354 .ib_test = &r100_ib_test,
355 .is_lockup = &r100_gpu_is_lockup,
356 .get_rptr = &r100_gfx_get_rptr,
357 .get_wptr = &r100_gfx_get_wptr,
358 .set_wptr = &r100_gfx_set_wptr,
359};
360
48e7a5f1
DV		 361static struct radeon_asic r300_asic = {
362 .init = &r300_init,
363 .fini = &r300_fini,
364 .suspend = &r300_suspend,
365 .resume = &r300_resume,
366 .vga_set_state = &r100_vga_set_state,
a2d07b74 367 .asic_reset = &r300_asic_reset,
124764f1 368 .mmio_hdp_flush = NULL,
54e88e06
AD		 369 .gui_idle = &r100_gui_idle,
370 .mc_wait_for_idle = &r300_mc_wait_for_idle,
18b53e90 371 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 372 .gart = {
373 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 374 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 375 .set_page = &r100_pci_gart_set_page,
376 },
4c87bc26 377 .ring = {
76a0df85 378 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 379 },
b35ea4ab
AD		 380 .irq = {
381 .set = &r100_irq_set,
382 .process = &r100_irq_process,
383 },
c79a49ca
AD		 384 .display = {
385 .bandwidth_update = &r100_bandwidth_update,
386 .get_vblank_counter = &r100_get_vblank_counter,
387 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 388 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 389 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 390 },
27cd7769
AD		 391 .copy = {
392 .blit = &r100_copy_blit,
393 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
394 .dma = &r200_copy_dma,
395 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
396 .copy = &r100_copy_blit,
397 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
398 },
9e6f3d02
AD		 399 .surface = {
400 .set_reg = r100_set_surface_reg,
401 .clear_reg = r100_clear_surface_reg,
402 },
901ea57d
AD		 403 .hpd = {
404 .init = &r100_hpd_init,
405 .fini = &r100_hpd_fini,
406 .sense = &r100_hpd_sense,
407 .set_polarity = &r100_hpd_set_polarity,
408 },
a02fa397
AD		 409 .pm = {
410 .misc = &r100_pm_misc,
411 .prepare = &r100_pm_prepare,
412 .finish = &r100_pm_finish,
413 .init_profile = &r100_pm_init_profile,
414 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 415 .get_engine_clock = &radeon_legacy_get_engine_clock,
416 .set_engine_clock = &radeon_legacy_set_engine_clock,
417 .get_memory_clock = &radeon_legacy_get_memory_clock,
418 .set_memory_clock = NULL,
419 .get_pcie_lanes = &rv370_get_pcie_lanes,
420 .set_pcie_lanes = &rv370_set_pcie_lanes,
421 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 422 },
0f9e006c 423 .pflip = {
0f9e006c 424 .page_flip = &r100_page_flip,
157fa14d 425 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 426 },
48e7a5f1
DV		 427};
428
429static struct radeon_asic r300_asic_pcie = {
430 .init = &r300_init,
431 .fini = &r300_fini,
432 .suspend = &r300_suspend,
433 .resume = &r300_resume,
434 .vga_set_state = &r100_vga_set_state,
a2d07b74 435 .asic_reset = &r300_asic_reset,
124764f1 436 .mmio_hdp_flush = NULL,
54e88e06
AD		 437 .gui_idle = &r100_gui_idle,
438 .mc_wait_for_idle = &r300_mc_wait_for_idle,
18b53e90 439 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 440 .gart = {
441 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 442 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 443 .set_page = &rv370_pcie_gart_set_page,
444 },
4c87bc26 445 .ring = {
76a0df85 446 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 447 },
b35ea4ab
AD		 448 .irq = {
449 .set = &r100_irq_set,
450 .process = &r100_irq_process,
451 },
c79a49ca
AD		 452 .display = {
453 .bandwidth_update = &r100_bandwidth_update,
454 .get_vblank_counter = &r100_get_vblank_counter,
455 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 456 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 457 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 458 },
27cd7769
AD		 459 .copy = {
460 .blit = &r100_copy_blit,
461 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
462 .dma = &r200_copy_dma,
463 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
464 .copy = &r100_copy_blit,
465 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
466 },
9e6f3d02
AD		 467 .surface = {
468 .set_reg = r100_set_surface_reg,
469 .clear_reg = r100_clear_surface_reg,
470 },
901ea57d
AD		 471 .hpd = {
472 .init = &r100_hpd_init,
473 .fini = &r100_hpd_fini,
474 .sense = &r100_hpd_sense,
475 .set_polarity = &r100_hpd_set_polarity,
476 },
a02fa397
AD		 477 .pm = {
478 .misc = &r100_pm_misc,
479 .prepare = &r100_pm_prepare,
480 .finish = &r100_pm_finish,
481 .init_profile = &r100_pm_init_profile,
482 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 483 .get_engine_clock = &radeon_legacy_get_engine_clock,
484 .set_engine_clock = &radeon_legacy_set_engine_clock,
485 .get_memory_clock = &radeon_legacy_get_memory_clock,
486 .set_memory_clock = NULL,
487 .get_pcie_lanes = &rv370_get_pcie_lanes,
488 .set_pcie_lanes = &rv370_set_pcie_lanes,
489 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 490 },
0f9e006c 491 .pflip = {
0f9e006c 492 .page_flip = &r100_page_flip,
157fa14d 493 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 494 },
48e7a5f1
DV		 495};
496
497static struct radeon_asic r420_asic = {
498 .init = &r420_init,
499 .fini = &r420_fini,
500 .suspend = &r420_suspend,
501 .resume = &r420_resume,
502 .vga_set_state = &r100_vga_set_state,
a2d07b74 503 .asic_reset = &r300_asic_reset,
124764f1 504 .mmio_hdp_flush = NULL,
54e88e06
AD		 505 .gui_idle = &r100_gui_idle,
506 .mc_wait_for_idle = &r300_mc_wait_for_idle,
18b53e90 507 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 508 .gart = {
509 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 510 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 511 .set_page = &rv370_pcie_gart_set_page,
512 },
4c87bc26 513 .ring = {
76a0df85 514 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 515 },
b35ea4ab
AD		 516 .irq = {
517 .set = &r100_irq_set,
518 .process = &r100_irq_process,
519 },
c79a49ca
AD		 520 .display = {
521 .bandwidth_update = &r100_bandwidth_update,
522 .get_vblank_counter = &r100_get_vblank_counter,
523 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 524 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 525 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 526 },
27cd7769
AD		 527 .copy = {
528 .blit = &r100_copy_blit,
529 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
530 .dma = &r200_copy_dma,
531 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
532 .copy = &r100_copy_blit,
533 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
534 },
9e6f3d02
AD		 535 .surface = {
536 .set_reg = r100_set_surface_reg,
537 .clear_reg = r100_clear_surface_reg,
538 },
901ea57d
AD		 539 .hpd = {
540 .init = &r100_hpd_init,
541 .fini = &r100_hpd_fini,
542 .sense = &r100_hpd_sense,
543 .set_polarity = &r100_hpd_set_polarity,
544 },
a02fa397
AD		 545 .pm = {
546 .misc = &r100_pm_misc,
547 .prepare = &r100_pm_prepare,
548 .finish = &r100_pm_finish,
549 .init_profile = &r420_pm_init_profile,
550 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 551 .get_engine_clock = &radeon_atom_get_engine_clock,
552 .set_engine_clock = &radeon_atom_set_engine_clock,
553 .get_memory_clock = &radeon_atom_get_memory_clock,
554 .set_memory_clock = &radeon_atom_set_memory_clock,
555 .get_pcie_lanes = &rv370_get_pcie_lanes,
556 .set_pcie_lanes = &rv370_set_pcie_lanes,
557 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 558 },
0f9e006c 559 .pflip = {
0f9e006c 560 .page_flip = &r100_page_flip,
157fa14d 561 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 562 },
48e7a5f1
DV		 563};
564
565static struct radeon_asic rs400_asic = {
566 .init = &rs400_init,
567 .fini = &rs400_fini,
568 .suspend = &rs400_suspend,
569 .resume = &rs400_resume,
570 .vga_set_state = &r100_vga_set_state,
a2d07b74 571 .asic_reset = &r300_asic_reset,
124764f1 572 .mmio_hdp_flush = NULL,
54e88e06
AD		 573 .gui_idle = &r100_gui_idle,
574 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
18b53e90 575 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 576 .gart = {
577 .tlb_flush = &rs400_gart_tlb_flush,
cb658906 578 .get_page_entry = &rs400_gart_get_page_entry,
c5b3b850
AD		 579 .set_page = &rs400_gart_set_page,
580 },
4c87bc26 581 .ring = {
76a0df85 582 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 583 },
b35ea4ab
AD		 584 .irq = {
585 .set = &r100_irq_set,
586 .process = &r100_irq_process,
587 },
c79a49ca
AD		 588 .display = {
589 .bandwidth_update = &r100_bandwidth_update,
590 .get_vblank_counter = &r100_get_vblank_counter,
591 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 592 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 593 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 594 },
27cd7769
AD		 595 .copy = {
596 .blit = &r100_copy_blit,
597 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
598 .dma = &r200_copy_dma,
599 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
600 .copy = &r100_copy_blit,
601 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
602 },
9e6f3d02
AD		 603 .surface = {
604 .set_reg = r100_set_surface_reg,
605 .clear_reg = r100_clear_surface_reg,
606 },
901ea57d
AD		 607 .hpd = {
608 .init = &r100_hpd_init,
609 .fini = &r100_hpd_fini,
610 .sense = &r100_hpd_sense,
611 .set_polarity = &r100_hpd_set_polarity,
612 },
a02fa397
AD		 613 .pm = {
614 .misc = &r100_pm_misc,
615 .prepare = &r100_pm_prepare,
616 .finish = &r100_pm_finish,
617 .init_profile = &r100_pm_init_profile,
618 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 619 .get_engine_clock = &radeon_legacy_get_engine_clock,
620 .set_engine_clock = &radeon_legacy_set_engine_clock,
621 .get_memory_clock = &radeon_legacy_get_memory_clock,
622 .set_memory_clock = NULL,
623 .get_pcie_lanes = NULL,
624 .set_pcie_lanes = NULL,
625 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 626 },
0f9e006c 627 .pflip = {
0f9e006c 628 .page_flip = &r100_page_flip,
157fa14d 629 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 630 },
48e7a5f1
DV		 631};
632
633static struct radeon_asic rs600_asic = {
634 .init = &rs600_init,
635 .fini = &rs600_fini,
636 .suspend = &rs600_suspend,
637 .resume = &rs600_resume,
638 .vga_set_state = &r100_vga_set_state,
90aca4d2 639 .asic_reset = &rs600_asic_reset,
124764f1 640 .mmio_hdp_flush = NULL,
54e88e06
AD		 641 .gui_idle = &r100_gui_idle,
642 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
18b53e90 643 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 644 .gart = {
645 .tlb_flush = &rs600_gart_tlb_flush,
cb658906 646 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 647 .set_page = &rs600_gart_set_page,
648 },
4c87bc26 649 .ring = {
76a0df85 650 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 651 },
b35ea4ab
AD		 652 .irq = {
653 .set = &rs600_irq_set,
654 .process = &rs600_irq_process,
655 },
c79a49ca
AD		 656 .display = {
657 .bandwidth_update = &rs600_bandwidth_update,
658 .get_vblank_counter = &rs600_get_vblank_counter,
659 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 660 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 661 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 662 },
27cd7769
AD		 663 .copy = {
664 .blit = &r100_copy_blit,
665 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
666 .dma = &r200_copy_dma,
667 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
668 .copy = &r100_copy_blit,
669 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
670 },
9e6f3d02
AD		 671 .surface = {
672 .set_reg = r100_set_surface_reg,
673 .clear_reg = r100_clear_surface_reg,
674 },
901ea57d
AD		 675 .hpd = {
676 .init = &rs600_hpd_init,
677 .fini = &rs600_hpd_fini,
678 .sense = &rs600_hpd_sense,
679 .set_polarity = &rs600_hpd_set_polarity,
680 },
a02fa397
AD		 681 .pm = {
682 .misc = &rs600_pm_misc,
683 .prepare = &rs600_pm_prepare,
684 .finish = &rs600_pm_finish,
685 .init_profile = &r420_pm_init_profile,
686 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 687 .get_engine_clock = &radeon_atom_get_engine_clock,
688 .set_engine_clock = &radeon_atom_set_engine_clock,
689 .get_memory_clock = &radeon_atom_get_memory_clock,
690 .set_memory_clock = &radeon_atom_set_memory_clock,
691 .get_pcie_lanes = NULL,
692 .set_pcie_lanes = NULL,
693 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 694 },
0f9e006c 695 .pflip = {
0f9e006c 696 .page_flip = &rs600_page_flip,
157fa14d 697 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 698 },
48e7a5f1
DV		 699};
700
701static struct radeon_asic rs690_asic = {
702 .init = &rs690_init,
703 .fini = &rs690_fini,
704 .suspend = &rs690_suspend,
705 .resume = &rs690_resume,
706 .vga_set_state = &r100_vga_set_state,
90aca4d2 707 .asic_reset = &rs600_asic_reset,
124764f1 708 .mmio_hdp_flush = NULL,
54e88e06
AD		 709 .gui_idle = &r100_gui_idle,
710 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
18b53e90 711 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 712 .gart = {
713 .tlb_flush = &rs400_gart_tlb_flush,
cb658906 714 .get_page_entry = &rs400_gart_get_page_entry,
c5b3b850
AD		 715 .set_page = &rs400_gart_set_page,
716 },
4c87bc26 717 .ring = {
76a0df85 718 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 719 },
b35ea4ab
AD		 720 .irq = {
721 .set = &rs600_irq_set,
722 .process = &rs600_irq_process,
723 },
c79a49ca
AD		 724 .display = {
725 .get_vblank_counter = &rs600_get_vblank_counter,
726 .bandwidth_update = &rs690_bandwidth_update,
727 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 728 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 729 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 730 },
27cd7769
AD		 731 .copy = {
732 .blit = &r100_copy_blit,
733 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
734 .dma = &r200_copy_dma,
735 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
736 .copy = &r200_copy_dma,
737 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
738 },
9e6f3d02
AD		 739 .surface = {
740 .set_reg = r100_set_surface_reg,
741 .clear_reg = r100_clear_surface_reg,
742 },
901ea57d
AD		 743 .hpd = {
744 .init = &rs600_hpd_init,
745 .fini = &rs600_hpd_fini,
746 .sense = &rs600_hpd_sense,
747 .set_polarity = &rs600_hpd_set_polarity,
748 },
a02fa397
AD		 749 .pm = {
750 .misc = &rs600_pm_misc,
751 .prepare = &rs600_pm_prepare,
752 .finish = &rs600_pm_finish,
753 .init_profile = &r420_pm_init_profile,
754 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 755 .get_engine_clock = &radeon_atom_get_engine_clock,
756 .set_engine_clock = &radeon_atom_set_engine_clock,
757 .get_memory_clock = &radeon_atom_get_memory_clock,
758 .set_memory_clock = &radeon_atom_set_memory_clock,
759 .get_pcie_lanes = NULL,
760 .set_pcie_lanes = NULL,
761 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 762 },
0f9e006c 763 .pflip = {
0f9e006c 764 .page_flip = &rs600_page_flip,
157fa14d 765 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 766 },
48e7a5f1
DV		 767};
768
769static struct radeon_asic rv515_asic = {
770 .init = &rv515_init,
771 .fini = &rv515_fini,
772 .suspend = &rv515_suspend,
773 .resume = &rv515_resume,
774 .vga_set_state = &r100_vga_set_state,
90aca4d2 775 .asic_reset = &rs600_asic_reset,
124764f1 776 .mmio_hdp_flush = NULL,
54e88e06
AD		 777 .gui_idle = &r100_gui_idle,
778 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
18b53e90 779 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 780 .gart = {
781 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 782 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 783 .set_page = &rv370_pcie_gart_set_page,
784 },
4c87bc26 785 .ring = {
d8a74e18 786 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
4c87bc26 787 },
b35ea4ab
AD		 788 .irq = {
789 .set = &rs600_irq_set,
790 .process = &rs600_irq_process,
791 },
c79a49ca
AD		 792 .display = {
793 .get_vblank_counter = &rs600_get_vblank_counter,
794 .bandwidth_update = &rv515_bandwidth_update,
795 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 796 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 797 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 798 },
27cd7769
AD		 799 .copy = {
800 .blit = &r100_copy_blit,
801 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
802 .dma = &r200_copy_dma,
803 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
804 .copy = &r100_copy_blit,
805 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
806 },
9e6f3d02
AD		 807 .surface = {
808 .set_reg = r100_set_surface_reg,
809 .clear_reg = r100_clear_surface_reg,
810 },
901ea57d
AD		 811 .hpd = {
812 .init = &rs600_hpd_init,
813 .fini = &rs600_hpd_fini,
814 .sense = &rs600_hpd_sense,
815 .set_polarity = &rs600_hpd_set_polarity,
816 },
a02fa397
AD		 817 .pm = {
818 .misc = &rs600_pm_misc,
819 .prepare = &rs600_pm_prepare,
820 .finish = &rs600_pm_finish,
821 .init_profile = &r420_pm_init_profile,
822 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 823 .get_engine_clock = &radeon_atom_get_engine_clock,
824 .set_engine_clock = &radeon_atom_set_engine_clock,
825 .get_memory_clock = &radeon_atom_get_memory_clock,
826 .set_memory_clock = &radeon_atom_set_memory_clock,
827 .get_pcie_lanes = &rv370_get_pcie_lanes,
828 .set_pcie_lanes = &rv370_set_pcie_lanes,
829 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 830 },
0f9e006c 831 .pflip = {
0f9e006c 832 .page_flip = &rs600_page_flip,
157fa14d 833 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 834 },
48e7a5f1
DV		 835};
836
837static struct radeon_asic r520_asic = {
838 .init = &r520_init,
839 .fini = &rv515_fini,
840 .suspend = &rv515_suspend,
841 .resume = &r520_resume,
842 .vga_set_state = &r100_vga_set_state,
90aca4d2 843 .asic_reset = &rs600_asic_reset,
124764f1 844 .mmio_hdp_flush = NULL,
54e88e06
AD		 845 .gui_idle = &r100_gui_idle,
846 .mc_wait_for_idle = &r520_mc_wait_for_idle,
18b53e90 847 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 848 .gart = {
849 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 850 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 851 .set_page = &rv370_pcie_gart_set_page,
852 },
4c87bc26 853 .ring = {
d8a74e18 854 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
4c87bc26 855 },
b35ea4ab
AD		 856 .irq = {
857 .set = &rs600_irq_set,
858 .process = &rs600_irq_process,
859 },
c79a49ca
AD		 860 .display = {
861 .bandwidth_update = &rv515_bandwidth_update,
862 .get_vblank_counter = &rs600_get_vblank_counter,
863 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 864 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 865 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 866 },
27cd7769
AD		 867 .copy = {
868 .blit = &r100_copy_blit,
869 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
870 .dma = &r200_copy_dma,
871 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
872 .copy = &r100_copy_blit,
873 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
874 },
9e6f3d02
AD		 875 .surface = {
876 .set_reg = r100_set_surface_reg,
877 .clear_reg = r100_clear_surface_reg,
878 },
901ea57d
AD		 879 .hpd = {
880 .init = &rs600_hpd_init,
881 .fini = &rs600_hpd_fini,
882 .sense = &rs600_hpd_sense,
883 .set_polarity = &rs600_hpd_set_polarity,
884 },
a02fa397
AD		 885 .pm = {
886 .misc = &rs600_pm_misc,
887 .prepare = &rs600_pm_prepare,
888 .finish = &rs600_pm_finish,
889 .init_profile = &r420_pm_init_profile,
890 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 891 .get_engine_clock = &radeon_atom_get_engine_clock,
892 .set_engine_clock = &radeon_atom_set_engine_clock,
893 .get_memory_clock = &radeon_atom_get_memory_clock,
894 .set_memory_clock = &radeon_atom_set_memory_clock,
895 .get_pcie_lanes = &rv370_get_pcie_lanes,
896 .set_pcie_lanes = &rv370_set_pcie_lanes,
897 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 898 },
0f9e006c 899 .pflip = {
0f9e006c 900 .page_flip = &rs600_page_flip,
157fa14d 901 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 902 },
48e7a5f1
DV		 903};
904
76a0df85
CK		 905static struct radeon_asic_ring r600_gfx_ring = {
906 .ib_execute = &r600_ring_ib_execute,
907 .emit_fence = &r600_fence_ring_emit,
908 .emit_semaphore = &r600_semaphore_ring_emit,
909 .cs_parse = &r600_cs_parse,
910 .ring_test = &r600_ring_test,
911 .ib_test = &r600_ib_test,
912 .is_lockup = &r600_gfx_is_lockup,
ea31bf69
AD		 913 .get_rptr = &r600_gfx_get_rptr,
914 .get_wptr = &r600_gfx_get_wptr,
915 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 916};
917
918static struct radeon_asic_ring r600_dma_ring = {
919 .ib_execute = &r600_dma_ring_ib_execute,
920 .emit_fence = &r600_dma_fence_ring_emit,
921 .emit_semaphore = &r600_dma_semaphore_ring_emit,
922 .cs_parse = &r600_dma_cs_parse,
923 .ring_test = &r600_dma_ring_test,
924 .ib_test = &r600_dma_ib_test,
925 .is_lockup = &r600_dma_is_lockup,
2e1e6dad
CK		 926 .get_rptr = &r600_dma_get_rptr,
927 .get_wptr = &r600_dma_get_wptr,
928 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 929};
930
48e7a5f1
DV		 931static struct radeon_asic r600_asic = {
932 .init = &r600_init,
933 .fini = &r600_fini,
934 .suspend = &r600_suspend,
935 .resume = &r600_resume,
48e7a5f1 936 .vga_set_state = &r600_vga_set_state,
a2d07b74 937 .asic_reset = &r600_asic_reset,
124764f1 938 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 939 .gui_idle = &r600_gui_idle,
940 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 941 .get_xclk = &r600_get_xclk,
d0418894 942 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c6d2ac2c 943 .get_allowed_info_register = r600_get_allowed_info_register,
c5b3b850
AD		 944 .gart = {
945 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 946 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 947 .set_page = &rs600_gart_set_page,
948 },
4c87bc26 949 .ring = {
76a0df85
CK		 950 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
951 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
4c87bc26 952 },
b35ea4ab
AD		 953 .irq = {
954 .set = &r600_irq_set,
955 .process = &r600_irq_process,
956 },
c79a49ca
AD		 957 .display = {
958 .bandwidth_update = &rv515_bandwidth_update,
959 .get_vblank_counter = &rs600_get_vblank_counter,
960 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 961 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 962 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 963 },
27cd7769 964 .copy = {
8dddb993 965 .blit = &r600_copy_cpdma,
27cd7769 966 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 967 .dma = &r600_copy_dma,
968 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 969 .copy = &r600_copy_cpdma,
aeea40cb 970 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 971 },
9e6f3d02
AD		 972 .surface = {
973 .set_reg = r600_set_surface_reg,
974 .clear_reg = r600_clear_surface_reg,
975 },
901ea57d
AD		 976 .hpd = {
977 .init = &r600_hpd_init,
978 .fini = &r600_hpd_fini,
979 .sense = &r600_hpd_sense,
980 .set_polarity = &r600_hpd_set_polarity,
981 },
a02fa397
AD		 982 .pm = {
983 .misc = &r600_pm_misc,
984 .prepare = &rs600_pm_prepare,
985 .finish = &rs600_pm_finish,
986 .init_profile = &r600_pm_init_profile,
987 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 988 .get_engine_clock = &radeon_atom_get_engine_clock,
989 .set_engine_clock = &radeon_atom_set_engine_clock,
990 .get_memory_clock = &radeon_atom_get_memory_clock,
991 .set_memory_clock = &radeon_atom_set_memory_clock,
992 .get_pcie_lanes = &r600_get_pcie_lanes,
993 .set_pcie_lanes = &r600_set_pcie_lanes,
994 .set_clock_gating = NULL,
6bd1c385 995 .get_temperature = &rv6xx_get_temp,
a02fa397 996 },
0f9e006c 997 .pflip = {
0f9e006c 998 .page_flip = &rs600_page_flip,
157fa14d 999 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 1000 },
48e7a5f1
DV		 1001};
1002
856754c3
CK		 1003static struct radeon_asic_ring rv6xx_uvd_ring = {
1004 .ib_execute = &uvd_v1_0_ib_execute,
1005 .emit_fence = &uvd_v1_0_fence_emit,
1006 .emit_semaphore = &uvd_v1_0_semaphore_emit,
1007 .cs_parse = &radeon_uvd_cs_parse,
1008 .ring_test = &uvd_v1_0_ring_test,
1009 .ib_test = &uvd_v1_0_ib_test,
1010 .is_lockup = &radeon_ring_test_lockup,
1011 .get_rptr = &uvd_v1_0_get_rptr,
1012 .get_wptr = &uvd_v1_0_get_wptr,
1013 .set_wptr = &uvd_v1_0_set_wptr,
1014};
1015
ca361b65
AD		 1016static struct radeon_asic rv6xx_asic = {
1017 .init = &r600_init,
1018 .fini = &r600_fini,
1019 .suspend = &r600_suspend,
1020 .resume = &r600_resume,
1021 .vga_set_state = &r600_vga_set_state,
1022 .asic_reset = &r600_asic_reset,
124764f1 1023 .mmio_hdp_flush = r600_mmio_hdp_flush,
ca361b65
AD		 1024 .gui_idle = &r600_gui_idle,
1025 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1026 .get_xclk = &r600_get_xclk,
1027 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c6d2ac2c 1028 .get_allowed_info_register = r600_get_allowed_info_register,
ca361b65
AD		 1029 .gart = {
1030 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1031 .get_page_entry = &rs600_gart_get_page_entry,
ca361b65
AD		 1032 .set_page = &rs600_gart_set_page,
1033 },
1034 .ring = {
76a0df85
CK		 1035 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1036 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
856754c3 1037 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
ca361b65
AD		 1038 },
1039 .irq = {
1040 .set = &r600_irq_set,
1041 .process = &r600_irq_process,
1042 },
1043 .display = {
1044 .bandwidth_update = &rv515_bandwidth_update,
1045 .get_vblank_counter = &rs600_get_vblank_counter,
1046 .wait_for_vblank = &avivo_wait_for_vblank,
1047 .set_backlight_level = &atombios_set_backlight_level,
1048 .get_backlight_level = &atombios_get_backlight_level,
1049 },
1050 .copy = {
8dddb993 1051 .blit = &r600_copy_cpdma,
ca361b65
AD		 1052 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1053 .dma = &r600_copy_dma,
1054 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1055 .copy = &r600_copy_cpdma,
aeea40cb 1056 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
ca361b65
AD		 1057 },
1058 .surface = {
1059 .set_reg = r600_set_surface_reg,
1060 .clear_reg = r600_clear_surface_reg,
1061 },
1062 .hpd = {
1063 .init = &r600_hpd_init,
1064 .fini = &r600_hpd_fini,
1065 .sense = &r600_hpd_sense,
1066 .set_polarity = &r600_hpd_set_polarity,
1067 },
1068 .pm = {
1069 .misc = &r600_pm_misc,
1070 .prepare = &rs600_pm_prepare,
1071 .finish = &rs600_pm_finish,
1072 .init_profile = &r600_pm_init_profile,
1073 .get_dynpm_state = &r600_pm_get_dynpm_state,
1074 .get_engine_clock = &radeon_atom_get_engine_clock,
1075 .set_engine_clock = &radeon_atom_set_engine_clock,
1076 .get_memory_clock = &radeon_atom_get_memory_clock,
1077 .set_memory_clock = &radeon_atom_set_memory_clock,
1078 .get_pcie_lanes = &r600_get_pcie_lanes,
1079 .set_pcie_lanes = &r600_set_pcie_lanes,
1080 .set_clock_gating = NULL,
1081 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1082 .set_uvd_clocks = &r600_set_uvd_clocks,
ca361b65 1083 },
4a6369e9
AD		 1084 .dpm = {
1085 .init = &rv6xx_dpm_init,
1086 .setup_asic = &rv6xx_setup_asic,
1087 .enable = &rv6xx_dpm_enable,
a4643ba3 1088 .late_enable = &r600_dpm_late_enable,
4a6369e9 1089 .disable = &rv6xx_dpm_disable,
98243917 1090 .pre_set_power_state = &r600_dpm_pre_set_power_state,
4a6369e9 1091 .set_power_state = &rv6xx_dpm_set_power_state,
98243917 1092 .post_set_power_state = &r600_dpm_post_set_power_state,
4a6369e9
AD		 1093 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1094 .fini = &rv6xx_dpm_fini,
1095 .get_sclk = &rv6xx_dpm_get_sclk,
1096 .get_mclk = &rv6xx_dpm_get_mclk,
1097 .print_power_state = &rv6xx_dpm_print_power_state,
242916a5 1098 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
f4f85a8c 1099 .force_performance_level = &rv6xx_dpm_force_performance_level,
d0a04d3b
AD		 1100 .get_current_sclk = &rv6xx_dpm_get_current_sclk,
1101 .get_current_mclk = &rv6xx_dpm_get_current_mclk,
4a6369e9 1102 },
ca361b65 1103 .pflip = {
ca361b65 1104 .page_flip = &rs600_page_flip,
157fa14d 1105 .page_flip_pending = &rs600_page_flip_pending,
ca361b65
AD		 1106 },
1107};
1108
f47299c5
AD		 1109static struct radeon_asic rs780_asic = {
1110 .init = &r600_init,
1111 .fini = &r600_fini,
1112 .suspend = &r600_suspend,
1113 .resume = &r600_resume,
f47299c5 1114 .vga_set_state = &r600_vga_set_state,
a2d07b74 1115 .asic_reset = &r600_asic_reset,
124764f1 1116 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1117 .gui_idle = &r600_gui_idle,
1118 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1119 .get_xclk = &r600_get_xclk,
d0418894 1120 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c6d2ac2c 1121 .get_allowed_info_register = r600_get_allowed_info_register,
c5b3b850
AD		 1122 .gart = {
1123 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1124 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1125 .set_page = &rs600_gart_set_page,
1126 },
4c87bc26 1127 .ring = {
76a0df85
CK		 1128 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1129 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
856754c3 1130 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
4c87bc26 1131 },
b35ea4ab
AD		 1132 .irq = {
1133 .set = &r600_irq_set,
1134 .process = &r600_irq_process,
1135 },
c79a49ca
AD		 1136 .display = {
1137 .bandwidth_update = &rs690_bandwidth_update,
1138 .get_vblank_counter = &rs600_get_vblank_counter,
1139 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1140 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1141 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1142 },
27cd7769 1143 .copy = {
8dddb993 1144 .blit = &r600_copy_cpdma,
27cd7769 1145 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1146 .dma = &r600_copy_dma,
1147 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1148 .copy = &r600_copy_cpdma,
aeea40cb 1149 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 1150 },
9e6f3d02
AD		 1151 .surface = {
1152 .set_reg = r600_set_surface_reg,
1153 .clear_reg = r600_clear_surface_reg,
1154 },
901ea57d
AD		 1155 .hpd = {
1156 .init = &r600_hpd_init,
1157 .fini = &r600_hpd_fini,
1158 .sense = &r600_hpd_sense,
1159 .set_polarity = &r600_hpd_set_polarity,
1160 },
a02fa397
AD		 1161 .pm = {
1162 .misc = &r600_pm_misc,
1163 .prepare = &rs600_pm_prepare,
1164 .finish = &rs600_pm_finish,
1165 .init_profile = &rs780_pm_init_profile,
1166 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1167 .get_engine_clock = &radeon_atom_get_engine_clock,
1168 .set_engine_clock = &radeon_atom_set_engine_clock,
1169 .get_memory_clock = NULL,
1170 .set_memory_clock = NULL,
1171 .get_pcie_lanes = NULL,
1172 .set_pcie_lanes = NULL,
1173 .set_clock_gating = NULL,
6bd1c385 1174 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1175 .set_uvd_clocks = &r600_set_uvd_clocks,
a02fa397 1176 },
9d67006e
AD		 1177 .dpm = {
1178 .init = &rs780_dpm_init,
1179 .setup_asic = &rs780_dpm_setup_asic,
1180 .enable = &rs780_dpm_enable,
a4643ba3 1181 .late_enable = &r600_dpm_late_enable,
9d67006e 1182 .disable = &rs780_dpm_disable,
98243917 1183 .pre_set_power_state = &r600_dpm_pre_set_power_state,
9d67006e 1184 .set_power_state = &rs780_dpm_set_power_state,
98243917 1185 .post_set_power_state = &r600_dpm_post_set_power_state,
9d67006e
AD		 1186 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1187 .fini = &rs780_dpm_fini,
1188 .get_sclk = &rs780_dpm_get_sclk,
1189 .get_mclk = &rs780_dpm_get_mclk,
1190 .print_power_state = &rs780_dpm_print_power_state,
444bddc4 1191 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
63580c3e 1192 .force_performance_level = &rs780_dpm_force_performance_level,
3c94566c
AD		 1193 .get_current_sclk = &rs780_dpm_get_current_sclk,
1194 .get_current_mclk = &rs780_dpm_get_current_mclk,
9d67006e 1195 },
0f9e006c 1196 .pflip = {
0f9e006c 1197 .page_flip = &rs600_page_flip,
157fa14d 1198 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 1199 },
f47299c5
AD		 1200};
1201
76a0df85 1202static struct radeon_asic_ring rv770_uvd_ring = {
e409b128
CK		 1203 .ib_execute = &uvd_v1_0_ib_execute,
1204 .emit_fence = &uvd_v2_2_fence_emit,
013ead48 1205 .emit_semaphore = &uvd_v2_2_semaphore_emit,
76a0df85 1206 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1207 .ring_test = &uvd_v1_0_ring_test,
1208 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1209 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1210 .get_rptr = &uvd_v1_0_get_rptr,
1211 .get_wptr = &uvd_v1_0_get_wptr,
1212 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1213};
1214
48e7a5f1
DV		 1215static struct radeon_asic rv770_asic = {
1216 .init = &rv770_init,
1217 .fini = &rv770_fini,
1218 .suspend = &rv770_suspend,
1219 .resume = &rv770_resume,
a2d07b74 1220 .asic_reset = &r600_asic_reset,
48e7a5f1 1221 .vga_set_state = &r600_vga_set_state,
124764f1 1222 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1223 .gui_idle = &r600_gui_idle,
1224 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1225 .get_xclk = &rv770_get_xclk,
d0418894 1226 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c6d2ac2c 1227 .get_allowed_info_register = r600_get_allowed_info_register,
c5b3b850
AD		 1228 .gart = {
1229 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1230 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1231 .set_page = &rs600_gart_set_page,
1232 },
4c87bc26 1233 .ring = {
76a0df85
CK		 1234 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1235 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1236 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1237 },
b35ea4ab
AD		 1238 .irq = {
1239 .set = &r600_irq_set,
1240 .process = &r600_irq_process,
1241 },
c79a49ca
AD		 1242 .display = {
1243 .bandwidth_update = &rv515_bandwidth_update,
1244 .get_vblank_counter = &rs600_get_vblank_counter,
1245 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1246 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1247 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1248 },
27cd7769 1249 .copy = {
8dddb993 1250 .blit = &r600_copy_cpdma,
27cd7769 1251 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
43fb7787 1252 .dma = &rv770_copy_dma,
4d75658b 1253 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
43fb7787 1254 .copy = &rv770_copy_dma,
2d6cc729 1255 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1256 },
9e6f3d02
AD		 1257 .surface = {
1258 .set_reg = r600_set_surface_reg,
1259 .clear_reg = r600_clear_surface_reg,
1260 },
901ea57d
AD		 1261 .hpd = {
1262 .init = &r600_hpd_init,
1263 .fini = &r600_hpd_fini,
1264 .sense = &r600_hpd_sense,
1265 .set_polarity = &r600_hpd_set_polarity,
1266 },
a02fa397
AD		 1267 .pm = {
1268 .misc = &rv770_pm_misc,
1269 .prepare = &rs600_pm_prepare,
1270 .finish = &rs600_pm_finish,
1271 .init_profile = &r600_pm_init_profile,
1272 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1273 .get_engine_clock = &radeon_atom_get_engine_clock,
1274 .set_engine_clock = &radeon_atom_set_engine_clock,
1275 .get_memory_clock = &radeon_atom_get_memory_clock,
1276 .set_memory_clock = &radeon_atom_set_memory_clock,
1277 .get_pcie_lanes = &r600_get_pcie_lanes,
1278 .set_pcie_lanes = &r600_set_pcie_lanes,
1279 .set_clock_gating = &radeon_atom_set_clock_gating,
ef0e6e65 1280 .set_uvd_clocks = &rv770_set_uvd_clocks,
6bd1c385 1281 .get_temperature = &rv770_get_temp,
a02fa397 1282 },
66229b20
AD		 1283 .dpm = {
1284 .init = &rv770_dpm_init,
1285 .setup_asic = &rv770_dpm_setup_asic,
1286 .enable = &rv770_dpm_enable,
a3f11245 1287 .late_enable = &rv770_dpm_late_enable,
66229b20 1288 .disable = &rv770_dpm_disable,
98243917 1289 .pre_set_power_state = &r600_dpm_pre_set_power_state,
66229b20 1290 .set_power_state = &rv770_dpm_set_power_state,
98243917 1291 .post_set_power_state = &r600_dpm_post_set_power_state,
66229b20
AD		 1292 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1293 .fini = &rv770_dpm_fini,
1294 .get_sclk = &rv770_dpm_get_sclk,
1295 .get_mclk = &rv770_dpm_get_mclk,
1296 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1297 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1298 .force_performance_level = &rv770_dpm_force_performance_level,
b06195d9 1299 .vblank_too_short = &rv770_dpm_vblank_too_short,
296deb71
AD		 1300 .get_current_sclk = &rv770_dpm_get_current_sclk,
1301 .get_current_mclk = &rv770_dpm_get_current_mclk,
66229b20 1302 },
0f9e006c 1303 .pflip = {
0f9e006c 1304 .page_flip = &rv770_page_flip,
157fa14d 1305 .page_flip_pending = &rv770_page_flip_pending,
0f9e006c 1306 },
48e7a5f1
DV		 1307};
1308
76a0df85
CK		 1309static struct radeon_asic_ring evergreen_gfx_ring = {
1310 .ib_execute = &evergreen_ring_ib_execute,
1311 .emit_fence = &r600_fence_ring_emit,
1312 .emit_semaphore = &r600_semaphore_ring_emit,
1313 .cs_parse = &evergreen_cs_parse,
1314 .ring_test = &r600_ring_test,
1315 .ib_test = &r600_ib_test,
1316 .is_lockup = &evergreen_gfx_is_lockup,
ea31bf69
AD		 1317 .get_rptr = &r600_gfx_get_rptr,
1318 .get_wptr = &r600_gfx_get_wptr,
1319 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 1320};
1321
1322static struct radeon_asic_ring evergreen_dma_ring = {
1323 .ib_execute = &evergreen_dma_ring_ib_execute,
1324 .emit_fence = &evergreen_dma_fence_ring_emit,
1325 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1326 .cs_parse = &evergreen_dma_cs_parse,
1327 .ring_test = &r600_dma_ring_test,
1328 .ib_test = &r600_dma_ib_test,
1329 .is_lockup = &evergreen_dma_is_lockup,
2e1e6dad
CK		 1330 .get_rptr = &r600_dma_get_rptr,
1331 .get_wptr = &r600_dma_get_wptr,
1332 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 1333};
1334
48e7a5f1
DV		 1335static struct radeon_asic evergreen_asic = {
1336 .init = &evergreen_init,
1337 .fini = &evergreen_fini,
1338 .suspend = &evergreen_suspend,
1339 .resume = &evergreen_resume,
a2d07b74 1340 .asic_reset = &evergreen_asic_reset,
48e7a5f1 1341 .vga_set_state = &r600_vga_set_state,
124764f1 1342 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1343 .gui_idle = &r600_gui_idle,
1344 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1345 .get_xclk = &rv770_get_xclk,
d0418894 1346 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
ff609975 1347 .get_allowed_info_register = evergreen_get_allowed_info_register,
c5b3b850
AD		 1348 .gart = {
1349 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1350 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1351 .set_page = &rs600_gart_set_page,
1352 },
4c87bc26 1353 .ring = {
76a0df85
CK		 1354 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1355 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1356 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1357 },
b35ea4ab
AD		 1358 .irq = {
1359 .set = &evergreen_irq_set,
1360 .process = &evergreen_irq_process,
1361 },
c79a49ca
AD		 1362 .display = {
1363 .bandwidth_update = &evergreen_bandwidth_update,
1364 .get_vblank_counter = &evergreen_get_vblank_counter,
1365 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1366 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1367 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1368 },
27cd7769 1369 .copy = {
8dddb993 1370 .blit = &r600_copy_cpdma,
27cd7769 1371 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1372 .dma = &evergreen_copy_dma,
1373 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1374 .copy = &evergreen_copy_dma,
1375 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1376 },
9e6f3d02
AD		 1377 .surface = {
1378 .set_reg = r600_set_surface_reg,
1379 .clear_reg = r600_clear_surface_reg,
1380 },
901ea57d
AD		 1381 .hpd = {
1382 .init = &evergreen_hpd_init,
1383 .fini = &evergreen_hpd_fini,
1384 .sense = &evergreen_hpd_sense,
1385 .set_polarity = &evergreen_hpd_set_polarity,
1386 },
a02fa397
AD		 1387 .pm = {
1388 .misc = &evergreen_pm_misc,
1389 .prepare = &evergreen_pm_prepare,
1390 .finish = &evergreen_pm_finish,
1391 .init_profile = &r600_pm_init_profile,
1392 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1393 .get_engine_clock = &radeon_atom_get_engine_clock,
1394 .set_engine_clock = &radeon_atom_set_engine_clock,
1395 .get_memory_clock = &radeon_atom_get_memory_clock,
1396 .set_memory_clock = &radeon_atom_set_memory_clock,
1397 .get_pcie_lanes = &r600_get_pcie_lanes,
1398 .set_pcie_lanes = &r600_set_pcie_lanes,
1399 .set_clock_gating = NULL,
a8b4925c 1400 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1401 .get_temperature = &evergreen_get_temp,
a02fa397 1402 },
dc50ba7f
AD		 1403 .dpm = {
1404 .init = &cypress_dpm_init,
1405 .setup_asic = &cypress_dpm_setup_asic,
1406 .enable = &cypress_dpm_enable,
a3f11245 1407 .late_enable = &rv770_dpm_late_enable,
dc50ba7f 1408 .disable = &cypress_dpm_disable,
98243917 1409 .pre_set_power_state = &r600_dpm_pre_set_power_state,
dc50ba7f 1410 .set_power_state = &cypress_dpm_set_power_state,
98243917 1411 .post_set_power_state = &r600_dpm_post_set_power_state,
dc50ba7f
AD		 1412 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1413 .fini = &cypress_dpm_fini,
1414 .get_sclk = &rv770_dpm_get_sclk,
1415 .get_mclk = &rv770_dpm_get_mclk,
1416 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1417 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1418 .force_performance_level = &rv770_dpm_force_performance_level,
d0b54bdc 1419 .vblank_too_short = &cypress_dpm_vblank_too_short,
296deb71
AD		 1420 .get_current_sclk = &rv770_dpm_get_current_sclk,
1421 .get_current_mclk = &rv770_dpm_get_current_mclk,
dc50ba7f 1422 },
0f9e006c 1423 .pflip = {
0f9e006c 1424 .page_flip = &evergreen_page_flip,
157fa14d 1425 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1426 },
48e7a5f1
DV		 1427};
1428
958261d1
AD		 1429static struct radeon_asic sumo_asic = {
1430 .init = &evergreen_init,
1431 .fini = &evergreen_fini,
1432 .suspend = &evergreen_suspend,
1433 .resume = &evergreen_resume,
958261d1
AD		 1434 .asic_reset = &evergreen_asic_reset,
1435 .vga_set_state = &r600_vga_set_state,
124764f1 1436 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1437 .gui_idle = &r600_gui_idle,
1438 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1439 .get_xclk = &r600_get_xclk,
d0418894 1440 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
ff609975 1441 .get_allowed_info_register = evergreen_get_allowed_info_register,
c5b3b850
AD		 1442 .gart = {
1443 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1444 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1445 .set_page = &rs600_gart_set_page,
1446 },
4c87bc26 1447 .ring = {
76a0df85
CK		 1448 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1449 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1450 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1451 },
b35ea4ab
AD		 1452 .irq = {
1453 .set = &evergreen_irq_set,
1454 .process = &evergreen_irq_process,
1455 },
c79a49ca
AD		 1456 .display = {
1457 .bandwidth_update = &evergreen_bandwidth_update,
1458 .get_vblank_counter = &evergreen_get_vblank_counter,
1459 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1460 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1461 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1462 },
27cd7769 1463 .copy = {
8dddb993 1464 .blit = &r600_copy_cpdma,
27cd7769 1465 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1466 .dma = &evergreen_copy_dma,
1467 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1468 .copy = &evergreen_copy_dma,
1469 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1470 },
9e6f3d02
AD		 1471 .surface = {
1472 .set_reg = r600_set_surface_reg,
1473 .clear_reg = r600_clear_surface_reg,
1474 },
901ea57d
AD		 1475 .hpd = {
1476 .init = &evergreen_hpd_init,
1477 .fini = &evergreen_hpd_fini,
1478 .sense = &evergreen_hpd_sense,
1479 .set_polarity = &evergreen_hpd_set_polarity,
1480 },
a02fa397
AD		 1481 .pm = {
1482 .misc = &evergreen_pm_misc,
1483 .prepare = &evergreen_pm_prepare,
1484 .finish = &evergreen_pm_finish,
1485 .init_profile = &sumo_pm_init_profile,
1486 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1487 .get_engine_clock = &radeon_atom_get_engine_clock,
1488 .set_engine_clock = &radeon_atom_set_engine_clock,
1489 .get_memory_clock = NULL,
1490 .set_memory_clock = NULL,
1491 .get_pcie_lanes = NULL,
1492 .set_pcie_lanes = NULL,
1493 .set_clock_gating = NULL,
23d33ba3 1494 .set_uvd_clocks = &sumo_set_uvd_clocks,
6bd1c385 1495 .get_temperature = &sumo_get_temp,
a02fa397 1496 },
80ea2c12
AD		 1497 .dpm = {
1498 .init = &sumo_dpm_init,
1499 .setup_asic = &sumo_dpm_setup_asic,
1500 .enable = &sumo_dpm_enable,
14ec9fab 1501 .late_enable = &sumo_dpm_late_enable,
80ea2c12 1502 .disable = &sumo_dpm_disable,
422a56bc 1503 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
80ea2c12 1504 .set_power_state = &sumo_dpm_set_power_state,
422a56bc 1505 .post_set_power_state = &sumo_dpm_post_set_power_state,
80ea2c12
AD		 1506 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1507 .fini = &sumo_dpm_fini,
1508 .get_sclk = &sumo_dpm_get_sclk,
1509 .get_mclk = &sumo_dpm_get_mclk,
1510 .print_power_state = &sumo_dpm_print_power_state,
fb70160c 1511 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
5d5e5591 1512 .force_performance_level = &sumo_dpm_force_performance_level,
2f8e1eb7
AD		 1513 .get_current_sclk = &sumo_dpm_get_current_sclk,
1514 .get_current_mclk = &sumo_dpm_get_current_mclk,
80ea2c12 1515 },
0f9e006c 1516 .pflip = {
0f9e006c 1517 .page_flip = &evergreen_page_flip,
157fa14d 1518 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1519 },
958261d1
AD		 1520};
1521
a43b7665
AD		 1522static struct radeon_asic btc_asic = {
1523 .init = &evergreen_init,
1524 .fini = &evergreen_fini,
1525 .suspend = &evergreen_suspend,
1526 .resume = &evergreen_resume,
a43b7665
AD		 1527 .asic_reset = &evergreen_asic_reset,
1528 .vga_set_state = &r600_vga_set_state,
124764f1 1529 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1530 .gui_idle = &r600_gui_idle,
1531 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1532 .get_xclk = &rv770_get_xclk,
d0418894 1533 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
ff609975 1534 .get_allowed_info_register = evergreen_get_allowed_info_register,
c5b3b850
AD		 1535 .gart = {
1536 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1537 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1538 .set_page = &rs600_gart_set_page,
1539 },
4c87bc26 1540 .ring = {
76a0df85
CK		 1541 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1542 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1543 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1544 },
b35ea4ab
AD		 1545 .irq = {
1546 .set = &evergreen_irq_set,
1547 .process = &evergreen_irq_process,
1548 },
c79a49ca
AD		 1549 .display = {
1550 .bandwidth_update = &evergreen_bandwidth_update,
1551 .get_vblank_counter = &evergreen_get_vblank_counter,
1552 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1553 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1554 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1555 },
27cd7769 1556 .copy = {
8dddb993 1557 .blit = &r600_copy_cpdma,
27cd7769 1558 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1559 .dma = &evergreen_copy_dma,
1560 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1561 .copy = &evergreen_copy_dma,
1562 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1563 },
9e6f3d02
AD		 1564 .surface = {
1565 .set_reg = r600_set_surface_reg,
1566 .clear_reg = r600_clear_surface_reg,
1567 },
901ea57d
AD		 1568 .hpd = {
1569 .init = &evergreen_hpd_init,
1570 .fini = &evergreen_hpd_fini,
1571 .sense = &evergreen_hpd_sense,
1572 .set_polarity = &evergreen_hpd_set_polarity,
1573 },
a02fa397
AD		 1574 .pm = {
1575 .misc = &evergreen_pm_misc,
1576 .prepare = &evergreen_pm_prepare,
1577 .finish = &evergreen_pm_finish,
27810fb2 1578 .init_profile = &btc_pm_init_profile,
a02fa397 1579 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1580 .get_engine_clock = &radeon_atom_get_engine_clock,
1581 .set_engine_clock = &radeon_atom_set_engine_clock,
1582 .get_memory_clock = &radeon_atom_get_memory_clock,
1583 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1584 .get_pcie_lanes = &r600_get_pcie_lanes,
1585 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1586 .set_clock_gating = NULL,
a8b4925c 1587 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1588 .get_temperature = &evergreen_get_temp,
a02fa397 1589 },
6596afd4
AD		 1590 .dpm = {
1591 .init = &btc_dpm_init,
1592 .setup_asic = &btc_dpm_setup_asic,
1593 .enable = &btc_dpm_enable,
a3f11245 1594 .late_enable = &rv770_dpm_late_enable,
6596afd4 1595 .disable = &btc_dpm_disable,
e8a9539f 1596 .pre_set_power_state = &btc_dpm_pre_set_power_state,
6596afd4 1597 .set_power_state = &btc_dpm_set_power_state,
e8a9539f 1598 .post_set_power_state = &btc_dpm_post_set_power_state,
6596afd4
AD		 1599 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1600 .fini = &btc_dpm_fini,
e8a9539f
AD		 1601 .get_sclk = &btc_dpm_get_sclk,
1602 .get_mclk = &btc_dpm_get_mclk,
6596afd4 1603 .print_power_state = &rv770_dpm_print_power_state,
9f3f63f2 1604 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1605 .force_performance_level = &rv770_dpm_force_performance_level,
a84301c6 1606 .vblank_too_short = &btc_dpm_vblank_too_short,
99550ee9
AD		 1607 .get_current_sclk = &btc_dpm_get_current_sclk,
1608 .get_current_mclk = &btc_dpm_get_current_mclk,
6596afd4 1609 },
0f9e006c 1610 .pflip = {
0f9e006c 1611 .page_flip = &evergreen_page_flip,
157fa14d 1612 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1613 },
a43b7665
AD		 1614};
1615
76a0df85
CK		 1616static struct radeon_asic_ring cayman_gfx_ring = {
1617 .ib_execute = &cayman_ring_ib_execute,
1618 .ib_parse = &evergreen_ib_parse,
1619 .emit_fence = &cayman_fence_ring_emit,
1620 .emit_semaphore = &r600_semaphore_ring_emit,
1621 .cs_parse = &evergreen_cs_parse,
1622 .ring_test = &r600_ring_test,
1623 .ib_test = &r600_ib_test,
1624 .is_lockup = &cayman_gfx_is_lockup,
1625 .vm_flush = &cayman_vm_flush,
ea31bf69
AD		 1626 .get_rptr = &cayman_gfx_get_rptr,
1627 .get_wptr = &cayman_gfx_get_wptr,
1628 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1629};
1630
1631static struct radeon_asic_ring cayman_dma_ring = {
1632 .ib_execute = &cayman_dma_ring_ib_execute,
1633 .ib_parse = &evergreen_dma_ib_parse,
1634 .emit_fence = &evergreen_dma_fence_ring_emit,
1635 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1636 .cs_parse = &evergreen_dma_cs_parse,
1637 .ring_test = &r600_dma_ring_test,
1638 .ib_test = &r600_dma_ib_test,
1639 .is_lockup = &cayman_dma_is_lockup,
1640 .vm_flush = &cayman_dma_vm_flush,
ea31bf69
AD		 1641 .get_rptr = &cayman_dma_get_rptr,
1642 .get_wptr = &cayman_dma_get_wptr,
1643 .set_wptr = &cayman_dma_set_wptr
76a0df85
CK		 1644};
1645
1646static struct radeon_asic_ring cayman_uvd_ring = {
e409b128
CK		 1647 .ib_execute = &uvd_v1_0_ib_execute,
1648 .emit_fence = &uvd_v2_2_fence_emit,
1649 .emit_semaphore = &uvd_v3_1_semaphore_emit,
76a0df85 1650 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1651 .ring_test = &uvd_v1_0_ring_test,
1652 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1653 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1654 .get_rptr = &uvd_v1_0_get_rptr,
1655 .get_wptr = &uvd_v1_0_get_wptr,
1656 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1657};
1658
e3487629
AD		 1659static struct radeon_asic cayman_asic = {
1660 .init = &cayman_init,
1661 .fini = &cayman_fini,
1662 .suspend = &cayman_suspend,
1663 .resume = &cayman_resume,
e3487629
AD		 1664 .asic_reset = &cayman_asic_reset,
1665 .vga_set_state = &r600_vga_set_state,
124764f1 1666 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1667 .gui_idle = &r600_gui_idle,
1668 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1669 .get_xclk = &rv770_get_xclk,
d0418894 1670 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
e66582f9 1671 .get_allowed_info_register = cayman_get_allowed_info_register,
c5b3b850
AD		 1672 .gart = {
1673 .tlb_flush = &cayman_pcie_gart_tlb_flush,
cb658906 1674 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1675 .set_page = &rs600_gart_set_page,
1676 },
05b07147
CK		 1677 .vm = {
1678 .init = &cayman_vm_init,
1679 .fini = &cayman_vm_fini,
03f62abd
CK		 1680 .copy_pages = &cayman_dma_vm_copy_pages,
1681 .write_pages = &cayman_dma_vm_write_pages,
1682 .set_pages = &cayman_dma_vm_set_pages,
1683 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1684 },
4c87bc26 1685 .ring = {
76a0df85
CK		 1686 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1687 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1688 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1689 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1690 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1691 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
4c87bc26 1692 },
b35ea4ab
AD		 1693 .irq = {
1694 .set = &evergreen_irq_set,
1695 .process = &evergreen_irq_process,
1696 },
c79a49ca
AD		 1697 .display = {
1698 .bandwidth_update = &evergreen_bandwidth_update,
1699 .get_vblank_counter = &evergreen_get_vblank_counter,
1700 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1701 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1702 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1703 },
27cd7769 1704 .copy = {
8dddb993 1705 .blit = &r600_copy_cpdma,
27cd7769 1706 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1707 .dma = &evergreen_copy_dma,
1708 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1709 .copy = &evergreen_copy_dma,
1710 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1711 },
9e6f3d02
AD		 1712 .surface = {
1713 .set_reg = r600_set_surface_reg,
1714 .clear_reg = r600_clear_surface_reg,
1715 },
901ea57d
AD		 1716 .hpd = {
1717 .init = &evergreen_hpd_init,
1718 .fini = &evergreen_hpd_fini,
1719 .sense = &evergreen_hpd_sense,
1720 .set_polarity = &evergreen_hpd_set_polarity,
1721 },
a02fa397
AD		 1722 .pm = {
1723 .misc = &evergreen_pm_misc,
1724 .prepare = &evergreen_pm_prepare,
1725 .finish = &evergreen_pm_finish,
27810fb2 1726 .init_profile = &btc_pm_init_profile,
a02fa397 1727 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1728 .get_engine_clock = &radeon_atom_get_engine_clock,
1729 .set_engine_clock = &radeon_atom_set_engine_clock,
1730 .get_memory_clock = &radeon_atom_get_memory_clock,
1731 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1732 .get_pcie_lanes = &r600_get_pcie_lanes,
1733 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1734 .set_clock_gating = NULL,
a8b4925c 1735 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1736 .get_temperature = &evergreen_get_temp,
a02fa397 1737 },
69e0b57a
AD		 1738 .dpm = {
1739 .init = &ni_dpm_init,
1740 .setup_asic = &ni_dpm_setup_asic,
1741 .enable = &ni_dpm_enable,
a3f11245 1742 .late_enable = &rv770_dpm_late_enable,
69e0b57a 1743 .disable = &ni_dpm_disable,
fee3d744 1744 .pre_set_power_state = &ni_dpm_pre_set_power_state,
69e0b57a 1745 .set_power_state = &ni_dpm_set_power_state,
fee3d744 1746 .post_set_power_state = &ni_dpm_post_set_power_state,
69e0b57a
AD		 1747 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1748 .fini = &ni_dpm_fini,
1749 .get_sclk = &ni_dpm_get_sclk,
1750 .get_mclk = &ni_dpm_get_mclk,
1751 .print_power_state = &ni_dpm_print_power_state,
bdf0c4f0 1752 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
170a47f0 1753 .force_performance_level = &ni_dpm_force_performance_level,
76ad73e5 1754 .vblank_too_short = &ni_dpm_vblank_too_short,
1d633e3a
AD		 1755 .get_current_sclk = &ni_dpm_get_current_sclk,
1756 .get_current_mclk = &ni_dpm_get_current_mclk,
69e0b57a 1757 },
0f9e006c 1758 .pflip = {
0f9e006c 1759 .page_flip = &evergreen_page_flip,
157fa14d 1760 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1761 },
e3487629
AD		 1762};
1763
be63fe8c
AD		 1764static struct radeon_asic trinity_asic = {
1765 .init = &cayman_init,
1766 .fini = &cayman_fini,
1767 .suspend = &cayman_suspend,
1768 .resume = &cayman_resume,
be63fe8c
AD		 1769 .asic_reset = &cayman_asic_reset,
1770 .vga_set_state = &r600_vga_set_state,
124764f1 1771 .mmio_hdp_flush = r600_mmio_hdp_flush,
be63fe8c
AD		 1772 .gui_idle = &r600_gui_idle,
1773 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1774 .get_xclk = &r600_get_xclk,
d0418894 1775 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
e66582f9 1776 .get_allowed_info_register = cayman_get_allowed_info_register,
be63fe8c
AD		 1777 .gart = {
1778 .tlb_flush = &cayman_pcie_gart_tlb_flush,
cb658906 1779 .get_page_entry = &rs600_gart_get_page_entry,
be63fe8c
AD		 1780 .set_page = &rs600_gart_set_page,
1781 },
05b07147
CK		 1782 .vm = {
1783 .init = &cayman_vm_init,
1784 .fini = &cayman_vm_fini,
03f62abd
CK		 1785 .copy_pages = &cayman_dma_vm_copy_pages,
1786 .write_pages = &cayman_dma_vm_write_pages,
1787 .set_pages = &cayman_dma_vm_set_pages,
1788 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1789 },
be63fe8c 1790 .ring = {
76a0df85
CK		 1791 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1792 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1793 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1794 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1795 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1796 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
be63fe8c
AD		 1797 },
1798 .irq = {
1799 .set = &evergreen_irq_set,
1800 .process = &evergreen_irq_process,
1801 },
1802 .display = {
1803 .bandwidth_update = &dce6_bandwidth_update,
1804 .get_vblank_counter = &evergreen_get_vblank_counter,
1805 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1806 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1807 .get_backlight_level = &atombios_get_backlight_level,
be63fe8c
AD		 1808 },
1809 .copy = {
8dddb993 1810 .blit = &r600_copy_cpdma,
be63fe8c 1811 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1812 .dma = &evergreen_copy_dma,
1813 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1814 .copy = &evergreen_copy_dma,
1815 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
be63fe8c
AD		 1816 },
1817 .surface = {
1818 .set_reg = r600_set_surface_reg,
1819 .clear_reg = r600_clear_surface_reg,
1820 },
1821 .hpd = {
1822 .init = &evergreen_hpd_init,
1823 .fini = &evergreen_hpd_fini,
1824 .sense = &evergreen_hpd_sense,
1825 .set_polarity = &evergreen_hpd_set_polarity,
1826 },
1827 .pm = {
1828 .misc = &evergreen_pm_misc,
1829 .prepare = &evergreen_pm_prepare,
1830 .finish = &evergreen_pm_finish,
1831 .init_profile = &sumo_pm_init_profile,
1832 .get_dynpm_state = &r600_pm_get_dynpm_state,
1833 .get_engine_clock = &radeon_atom_get_engine_clock,
1834 .set_engine_clock = &radeon_atom_set_engine_clock,
1835 .get_memory_clock = NULL,
1836 .set_memory_clock = NULL,
1837 .get_pcie_lanes = NULL,
1838 .set_pcie_lanes = NULL,
1839 .set_clock_gating = NULL,
23d33ba3 1840 .set_uvd_clocks = &sumo_set_uvd_clocks,
0fda42ac 1841 .set_vce_clocks = &tn_set_vce_clocks,
29a15221 1842 .get_temperature = &tn_get_temp,
be63fe8c 1843 },
d70229f7
AD		 1844 .dpm = {
1845 .init = &trinity_dpm_init,
1846 .setup_asic = &trinity_dpm_setup_asic,
1847 .enable = &trinity_dpm_enable,
bda44c1a 1848 .late_enable = &trinity_dpm_late_enable,
d70229f7 1849 .disable = &trinity_dpm_disable,
a284c48a 1850 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
d70229f7 1851 .set_power_state = &trinity_dpm_set_power_state,
a284c48a 1852 .post_set_power_state = &trinity_dpm_post_set_power_state,
d70229f7
AD		 1853 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1854 .fini = &trinity_dpm_fini,
1855 .get_sclk = &trinity_dpm_get_sclk,
1856 .get_mclk = &trinity_dpm_get_mclk,
1857 .print_power_state = &trinity_dpm_print_power_state,
490ab931 1858 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
9b5de596 1859 .force_performance_level = &trinity_dpm_force_performance_level,
11877060 1860 .enable_bapm = &trinity_dpm_enable_bapm,
7ce9cdae
AD		 1861 .get_current_sclk = &trinity_dpm_get_current_sclk,
1862 .get_current_mclk = &trinity_dpm_get_current_mclk,
d70229f7 1863 },
be63fe8c 1864 .pflip = {
be63fe8c 1865 .page_flip = &evergreen_page_flip,
157fa14d 1866 .page_flip_pending = &evergreen_page_flip_pending,
be63fe8c
AD		 1867 },
1868};
1869
76a0df85
CK		 1870static struct radeon_asic_ring si_gfx_ring = {
1871 .ib_execute = &si_ring_ib_execute,
1872 .ib_parse = &si_ib_parse,
1873 .emit_fence = &si_fence_ring_emit,
1874 .emit_semaphore = &r600_semaphore_ring_emit,
1875 .cs_parse = NULL,
1876 .ring_test = &r600_ring_test,
1877 .ib_test = &r600_ib_test,
1878 .is_lockup = &si_gfx_is_lockup,
1879 .vm_flush = &si_vm_flush,
ea31bf69
AD		 1880 .get_rptr = &cayman_gfx_get_rptr,
1881 .get_wptr = &cayman_gfx_get_wptr,
1882 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1883};
1884
1885static struct radeon_asic_ring si_dma_ring = {
1886 .ib_execute = &cayman_dma_ring_ib_execute,
1887 .ib_parse = &evergreen_dma_ib_parse,
1888 .emit_fence = &evergreen_dma_fence_ring_emit,
1889 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1890 .cs_parse = NULL,
1891 .ring_test = &r600_dma_ring_test,
1892 .ib_test = &r600_dma_ib_test,
1893 .is_lockup = &si_dma_is_lockup,
1894 .vm_flush = &si_dma_vm_flush,
ea31bf69
AD		 1895 .get_rptr = &cayman_dma_get_rptr,
1896 .get_wptr = &cayman_dma_get_wptr,
1897 .set_wptr = &cayman_dma_set_wptr,
76a0df85
CK		 1898};
1899
02779c08
AD		 1900static struct radeon_asic si_asic = {
1901 .init = &si_init,
1902 .fini = &si_fini,
1903 .suspend = &si_suspend,
1904 .resume = &si_resume,
02779c08
AD		 1905 .asic_reset = &si_asic_reset,
1906 .vga_set_state = &r600_vga_set_state,
124764f1 1907 .mmio_hdp_flush = r600_mmio_hdp_flush,
02779c08
AD		 1908 .gui_idle = &r600_gui_idle,
1909 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1910 .get_xclk = &si_get_xclk,
d0418894 1911 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
4af692f6 1912 .get_allowed_info_register = si_get_allowed_info_register,
02779c08
AD		 1913 .gart = {
1914 .tlb_flush = &si_pcie_gart_tlb_flush,
cb658906 1915 .get_page_entry = &rs600_gart_get_page_entry,
02779c08
AD		 1916 .set_page = &rs600_gart_set_page,
1917 },
05b07147
CK		 1918 .vm = {
1919 .init = &si_vm_init,
1920 .fini = &si_vm_fini,
03f62abd
CK		 1921 .copy_pages = &si_dma_vm_copy_pages,
1922 .write_pages = &si_dma_vm_write_pages,
1923 .set_pages = &si_dma_vm_set_pages,
1924 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1925 },
02779c08 1926 .ring = {
76a0df85
CK		 1927 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1928 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1929 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1930 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1931 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1932 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
02779c08
AD		 1933 },
1934 .irq = {
1935 .set = &si_irq_set,
1936 .process = &si_irq_process,
1937 },
1938 .display = {
1939 .bandwidth_update = &dce6_bandwidth_update,
1940 .get_vblank_counter = &evergreen_get_vblank_counter,
1941 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1942 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1943 .get_backlight_level = &atombios_get_backlight_level,
02779c08
AD		 1944 },
1945 .copy = {
5c722739 1946 .blit = &r600_copy_cpdma,
02779c08 1947 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
8c5fd7ef
AD		 1948 .dma = &si_copy_dma,
1949 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1950 .copy = &si_copy_dma,
1951 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
02779c08
AD		 1952 },
1953 .surface = {
1954 .set_reg = r600_set_surface_reg,
1955 .clear_reg = r600_clear_surface_reg,
1956 },
1957 .hpd = {
1958 .init = &evergreen_hpd_init,
1959 .fini = &evergreen_hpd_fini,
1960 .sense = &evergreen_hpd_sense,
1961 .set_polarity = &evergreen_hpd_set_polarity,
1962 },
1963 .pm = {
1964 .misc = &evergreen_pm_misc,
1965 .prepare = &evergreen_pm_prepare,
1966 .finish = &evergreen_pm_finish,
1967 .init_profile = &sumo_pm_init_profile,
1968 .get_dynpm_state = &r600_pm_get_dynpm_state,
1969 .get_engine_clock = &radeon_atom_get_engine_clock,
1970 .set_engine_clock = &radeon_atom_set_engine_clock,
1971 .get_memory_clock = &radeon_atom_get_memory_clock,
1972 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1973 .get_pcie_lanes = &r600_get_pcie_lanes,
1974 .set_pcie_lanes = &r600_set_pcie_lanes,
02779c08 1975 .set_clock_gating = NULL,
2539eb02 1976 .set_uvd_clocks = &si_set_uvd_clocks,
b7af630c 1977 .set_vce_clocks = &si_set_vce_clocks,
6bd1c385 1978 .get_temperature = &si_get_temp,
02779c08 1979 },
a9e61410
AD		 1980 .dpm = {
1981 .init = &si_dpm_init,
1982 .setup_asic = &si_dpm_setup_asic,
1983 .enable = &si_dpm_enable,
963c115d 1984 .late_enable = &si_dpm_late_enable,
a9e61410
AD		 1985 .disable = &si_dpm_disable,
1986 .pre_set_power_state = &si_dpm_pre_set_power_state,
1987 .set_power_state = &si_dpm_set_power_state,
1988 .post_set_power_state = &si_dpm_post_set_power_state,
1989 .display_configuration_changed = &si_dpm_display_configuration_changed,
1990 .fini = &si_dpm_fini,
1991 .get_sclk = &ni_dpm_get_sclk,
1992 .get_mclk = &ni_dpm_get_mclk,
1993 .print_power_state = &ni_dpm_print_power_state,
7982128c 1994 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
a160a6a3 1995 .force_performance_level = &si_dpm_force_performance_level,
f4dec318 1996 .vblank_too_short = &ni_dpm_vblank_too_short,
5e8150a6
AD		 1997 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
1998 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
1999 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
2000 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
ca1110bc
AD		 2001 .get_current_sclk = &si_dpm_get_current_sclk,
2002 .get_current_mclk = &si_dpm_get_current_mclk,
a9e61410 2003 },
02779c08 2004 .pflip = {
02779c08 2005 .page_flip = &evergreen_page_flip,
157fa14d 2006 .page_flip_pending = &evergreen_page_flip_pending,
02779c08
AD		 2007 },
2008};
2009
76a0df85
CK		 2010static struct radeon_asic_ring ci_gfx_ring = {
2011 .ib_execute = &cik_ring_ib_execute,
2012 .ib_parse = &cik_ib_parse,
2013 .emit_fence = &cik_fence_gfx_ring_emit,
2014 .emit_semaphore = &cik_semaphore_ring_emit,
2015 .cs_parse = NULL,
2016 .ring_test = &cik_ring_test,
2017 .ib_test = &cik_ib_test,
2018 .is_lockup = &cik_gfx_is_lockup,
2019 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 2020 .get_rptr = &cik_gfx_get_rptr,
2021 .get_wptr = &cik_gfx_get_wptr,
2022 .set_wptr = &cik_gfx_set_wptr,
76a0df85
CK		 2023};
2024
2025static struct radeon_asic_ring ci_cp_ring = {
2026 .ib_execute = &cik_ring_ib_execute,
2027 .ib_parse = &cik_ib_parse,
2028 .emit_fence = &cik_fence_compute_ring_emit,
2029 .emit_semaphore = &cik_semaphore_ring_emit,
2030 .cs_parse = NULL,
2031 .ring_test = &cik_ring_test,
2032 .ib_test = &cik_ib_test,
2033 .is_lockup = &cik_gfx_is_lockup,
2034 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 2035 .get_rptr = &cik_compute_get_rptr,
2036 .get_wptr = &cik_compute_get_wptr,
2037 .set_wptr = &cik_compute_set_wptr,
76a0df85
CK		 2038};
2039
2040static struct radeon_asic_ring ci_dma_ring = {
2041 .ib_execute = &cik_sdma_ring_ib_execute,
2042 .ib_parse = &cik_ib_parse,
2043 .emit_fence = &cik_sdma_fence_ring_emit,
2044 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2045 .cs_parse = NULL,
2046 .ring_test = &cik_sdma_ring_test,
2047 .ib_test = &cik_sdma_ib_test,
2048 .is_lockup = &cik_sdma_is_lockup,
2049 .vm_flush = &cik_dma_vm_flush,
ea31bf69
AD		 2050 .get_rptr = &cik_sdma_get_rptr,
2051 .get_wptr = &cik_sdma_get_wptr,
2052 .set_wptr = &cik_sdma_set_wptr,
76a0df85
CK		 2053};
2054
d93f7937
CK		 2055static struct radeon_asic_ring ci_vce_ring = {
2056 .ib_execute = &radeon_vce_ib_execute,
2057 .emit_fence = &radeon_vce_fence_emit,
2058 .emit_semaphore = &radeon_vce_semaphore_emit,
2059 .cs_parse = &radeon_vce_cs_parse,
2060 .ring_test = &radeon_vce_ring_test,
2061 .ib_test = &radeon_vce_ib_test,
2062 .is_lockup = &radeon_ring_test_lockup,
2063 .get_rptr = &vce_v1_0_get_rptr,
2064 .get_wptr = &vce_v1_0_get_wptr,
2065 .set_wptr = &vce_v1_0_set_wptr,
2066};
2067
0672e27b
AD		 2068static struct radeon_asic ci_asic = {
2069 .init = &cik_init,
2070 .fini = &cik_fini,
2071 .suspend = &cik_suspend,
2072 .resume = &cik_resume,
2073 .asic_reset = &cik_asic_reset,
2074 .vga_set_state = &r600_vga_set_state,
72a9987e 2075 .mmio_hdp_flush = &r600_mmio_hdp_flush,
0672e27b
AD		 2076 .gui_idle = &r600_gui_idle,
2077 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2078 .get_xclk = &cik_get_xclk,
2079 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
353eec2a 2080 .get_allowed_info_register = cik_get_allowed_info_register,
0672e27b
AD		 2081 .gart = {
2082 .tlb_flush = &cik_pcie_gart_tlb_flush,
cb658906 2083 .get_page_entry = &rs600_gart_get_page_entry,
0672e27b
AD		 2084 .set_page = &rs600_gart_set_page,
2085 },
2086 .vm = {
2087 .init = &cik_vm_init,
2088 .fini = &cik_vm_fini,
03f62abd
CK		 2089 .copy_pages = &cik_sdma_vm_copy_pages,
2090 .write_pages = &cik_sdma_vm_write_pages,
2091 .set_pages = &cik_sdma_vm_set_pages,
2092 .pad_ib = &cik_sdma_vm_pad_ib,
0672e27b
AD		 2093 },
2094 .ring = {
76a0df85
CK		 2095 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2096 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2097 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2098 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2099 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2100 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2101 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2102 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2103 },
2104 .irq = {
2105 .set = &cik_irq_set,
2106 .process = &cik_irq_process,
2107 },
2108 .display = {
2109 .bandwidth_update = &dce8_bandwidth_update,
2110 .get_vblank_counter = &evergreen_get_vblank_counter,
2111 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2112 .set_backlight_level = &atombios_set_backlight_level,
2113 .get_backlight_level = &atombios_get_backlight_level,
0672e27b
AD		 2114 },
2115 .copy = {
7819678f 2116 .blit = &cik_copy_cpdma,
0672e27b
AD		 2117 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2118 .dma = &cik_copy_dma,
2119 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
b5be1a83
CK		 2120 .copy = &cik_copy_dma,
2121 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
0672e27b
AD		 2122 },
2123 .surface = {
2124 .set_reg = r600_set_surface_reg,
2125 .clear_reg = r600_clear_surface_reg,
2126 },
2127 .hpd = {
2128 .init = &evergreen_hpd_init,
2129 .fini = &evergreen_hpd_fini,
2130 .sense = &evergreen_hpd_sense,
2131 .set_polarity = &evergreen_hpd_set_polarity,
2132 },
2133 .pm = {
2134 .misc = &evergreen_pm_misc,
2135 .prepare = &evergreen_pm_prepare,
2136 .finish = &evergreen_pm_finish,
2137 .init_profile = &sumo_pm_init_profile,
2138 .get_dynpm_state = &r600_pm_get_dynpm_state,
2139 .get_engine_clock = &radeon_atom_get_engine_clock,
2140 .set_engine_clock = &radeon_atom_set_engine_clock,
2141 .get_memory_clock = &radeon_atom_get_memory_clock,
2142 .set_memory_clock = &radeon_atom_set_memory_clock,
2143 .get_pcie_lanes = NULL,
2144 .set_pcie_lanes = NULL,
2145 .set_clock_gating = NULL,
2146 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2147 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2148 .get_temperature = &ci_get_temp,
0672e27b 2149 },
cc8dbbb4
AD		 2150 .dpm = {
2151 .init = &ci_dpm_init,
2152 .setup_asic = &ci_dpm_setup_asic,
2153 .enable = &ci_dpm_enable,
90208427 2154 .late_enable = &ci_dpm_late_enable,
cc8dbbb4
AD		 2155 .disable = &ci_dpm_disable,
2156 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2157 .set_power_state = &ci_dpm_set_power_state,
2158 .post_set_power_state = &ci_dpm_post_set_power_state,
2159 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2160 .fini = &ci_dpm_fini,
2161 .get_sclk = &ci_dpm_get_sclk,
2162 .get_mclk = &ci_dpm_get_mclk,
2163 .print_power_state = &ci_dpm_print_power_state,
94b4adc5 2164 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
89536fd6 2165 .force_performance_level = &ci_dpm_force_performance_level,
5496131e 2166 .vblank_too_short = &ci_dpm_vblank_too_short,
942bdf7f 2167 .powergate_uvd = &ci_dpm_powergate_uvd,
36689e57
OC		 2168 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
2169 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
2170 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
2171 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
dbbd3c81
AD		 2172 .get_current_sclk = &ci_dpm_get_current_sclk,
2173 .get_current_mclk = &ci_dpm_get_current_mclk,
cc8dbbb4 2174 },
0672e27b 2175 .pflip = {
0672e27b 2176 .page_flip = &evergreen_page_flip,
157fa14d 2177 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2178 },
2179};
2180
2181static struct radeon_asic kv_asic = {
2182 .init = &cik_init,
2183 .fini = &cik_fini,
2184 .suspend = &cik_suspend,
2185 .resume = &cik_resume,
2186 .asic_reset = &cik_asic_reset,
2187 .vga_set_state = &r600_vga_set_state,
72a9987e 2188 .mmio_hdp_flush = &r600_mmio_hdp_flush,
0672e27b
AD		 2189 .gui_idle = &r600_gui_idle,
2190 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2191 .get_xclk = &cik_get_xclk,
2192 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
353eec2a 2193 .get_allowed_info_register = cik_get_allowed_info_register,
0672e27b
AD		 2194 .gart = {
2195 .tlb_flush = &cik_pcie_gart_tlb_flush,
cb658906 2196 .get_page_entry = &rs600_gart_get_page_entry,
0672e27b
AD		 2197 .set_page = &rs600_gart_set_page,
2198 },
2199 .vm = {
2200 .init = &cik_vm_init,
2201 .fini = &cik_vm_fini,
03f62abd
CK		 2202 .copy_pages = &cik_sdma_vm_copy_pages,
2203 .write_pages = &cik_sdma_vm_write_pages,
2204 .set_pages = &cik_sdma_vm_set_pages,
2205 .pad_ib = &cik_sdma_vm_pad_ib,
0672e27b
AD		 2206 },
2207 .ring = {
76a0df85
CK		 2208 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2209 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2210 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2211 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2212 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2213 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2214 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2215 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2216 },
2217 .irq = {
2218 .set = &cik_irq_set,
2219 .process = &cik_irq_process,
2220 },
2221 .display = {
2222 .bandwidth_update = &dce8_bandwidth_update,
2223 .get_vblank_counter = &evergreen_get_vblank_counter,
2224 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2225 .set_backlight_level = &atombios_set_backlight_level,
2226 .get_backlight_level = &atombios_get_backlight_level,
0672e27b
AD		 2227 },
2228 .copy = {
7819678f 2229 .blit = &cik_copy_cpdma,
0672e27b
AD		 2230 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2231 .dma = &cik_copy_dma,
2232 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2233 .copy = &cik_copy_dma,
2234 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2235 },
2236 .surface = {
2237 .set_reg = r600_set_surface_reg,
2238 .clear_reg = r600_clear_surface_reg,
2239 },
2240 .hpd = {
2241 .init = &evergreen_hpd_init,
2242 .fini = &evergreen_hpd_fini,
2243 .sense = &evergreen_hpd_sense,
2244 .set_polarity = &evergreen_hpd_set_polarity,
2245 },
2246 .pm = {
2247 .misc = &evergreen_pm_misc,
2248 .prepare = &evergreen_pm_prepare,
2249 .finish = &evergreen_pm_finish,
2250 .init_profile = &sumo_pm_init_profile,
2251 .get_dynpm_state = &r600_pm_get_dynpm_state,
2252 .get_engine_clock = &radeon_atom_get_engine_clock,
2253 .set_engine_clock = &radeon_atom_set_engine_clock,
2254 .get_memory_clock = &radeon_atom_get_memory_clock,
2255 .set_memory_clock = &radeon_atom_set_memory_clock,
2256 .get_pcie_lanes = NULL,
2257 .set_pcie_lanes = NULL,
2258 .set_clock_gating = NULL,
2259 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2260 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2261 .get_temperature = &kv_get_temp,
0672e27b 2262 },
41a524ab
AD		 2263 .dpm = {
2264 .init = &kv_dpm_init,
2265 .setup_asic = &kv_dpm_setup_asic,
2266 .enable = &kv_dpm_enable,
d8852c34 2267 .late_enable = &kv_dpm_late_enable,
41a524ab
AD		 2268 .disable = &kv_dpm_disable,
2269 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2270 .set_power_state = &kv_dpm_set_power_state,
2271 .post_set_power_state = &kv_dpm_post_set_power_state,
2272 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2273 .fini = &kv_dpm_fini,
2274 .get_sclk = &kv_dpm_get_sclk,
2275 .get_mclk = &kv_dpm_get_mclk,
2276 .print_power_state = &kv_dpm_print_power_state,
ae3e40e8 2277 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2b4c8022 2278 .force_performance_level = &kv_dpm_force_performance_level,
77df508a 2279 .powergate_uvd = &kv_dpm_powergate_uvd,
b7a5ae97 2280 .enable_bapm = &kv_dpm_enable_bapm,
9b23bad0
AD		 2281 .get_current_sclk = &kv_dpm_get_current_sclk,
2282 .get_current_mclk = &kv_dpm_get_current_mclk,
41a524ab 2283 },
0672e27b 2284 .pflip = {
0672e27b 2285 .page_flip = &evergreen_page_flip,
157fa14d 2286 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2287 },
2288};
2289
abf1dc67
AD		 2290/**
2291 * radeon_asic_init - register asic specific callbacks
2292 *
2293 * @rdev: radeon device pointer
2294 *
2295 * Registers the appropriate asic specific callbacks for each
2296 * chip family. Also sets other asics specific info like the number
2297 * of crtcs and the register aperture accessors (all asics).
2298 * Returns 0 for success.
2299 */
0a10c851
DV		 2300int radeon_asic_init(struct radeon_device *rdev)
2301{
2302 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 2303
2304 /* set the number of crtcs */
2305 if (rdev->flags & RADEON_SINGLE_CRTC)
2306 rdev->num_crtc = 1;
2307 else
2308 rdev->num_crtc = 2;
2309
948bee3f
AD		 2310 rdev->has_uvd = false;
2311
0a10c851
DV		 2312 switch (rdev->family) {
2313 case CHIP_R100:
2314 case CHIP_RV100:
2315 case CHIP_RS100:
2316 case CHIP_RV200:
2317 case CHIP_RS200:
2318 rdev->asic = &r100_asic;
2319 break;
2320 case CHIP_R200:
2321 case CHIP_RV250:
2322 case CHIP_RS300:
2323 case CHIP_RV280:
2324 rdev->asic = &r200_asic;
2325 break;
2326 case CHIP_R300:
2327 case CHIP_R350:
2328 case CHIP_RV350:
2329 case CHIP_RV380:
2330 if (rdev->flags & RADEON_IS_PCIE)
2331 rdev->asic = &r300_asic_pcie;
2332 else
2333 rdev->asic = &r300_asic;
2334 break;
2335 case CHIP_R420:
2336 case CHIP_R423:
2337 case CHIP_RV410:
2338 rdev->asic = &r420_asic;
07bb084c
AD		 2339 /* handle macs */
2340 if (rdev->bios == NULL) {
798bcf73
AD		 2341 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2342 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2343 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2344 rdev->asic->pm.set_memory_clock = NULL;
37e9b6a6 2345 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
07bb084c 2346 }
0a10c851
DV		 2347 break;
2348 case CHIP_RS400:
2349 case CHIP_RS480:
2350 rdev->asic = &rs400_asic;
2351 break;
2352 case CHIP_RS600:
2353 rdev->asic = &rs600_asic;
2354 break;
2355 case CHIP_RS690:
2356 case CHIP_RS740:
2357 rdev->asic = &rs690_asic;
2358 break;
2359 case CHIP_RV515:
2360 rdev->asic = &rv515_asic;
2361 break;
2362 case CHIP_R520:
2363 case CHIP_RV530:
2364 case CHIP_RV560:
2365 case CHIP_RV570:
2366 case CHIP_R580:
2367 rdev->asic = &r520_asic;
2368 break;
2369 case CHIP_R600:
ca361b65
AD		 2370 rdev->asic = &r600_asic;
2371 break;
0a10c851
DV		 2372 case CHIP_RV610:
2373 case CHIP_RV630:
2374 case CHIP_RV620:
2375 case CHIP_RV635:
2376 case CHIP_RV670:
ca361b65
AD		 2377 rdev->asic = &rv6xx_asic;
2378 rdev->has_uvd = true;
f47299c5 2379 break;
0a10c851
DV		 2380 case CHIP_RS780:
2381 case CHIP_RS880:
f47299c5 2382 rdev->asic = &rs780_asic;
bdc99722
AD		 2383 /* 760G/780V/880V don't have UVD */
2384 if ((rdev->pdev->device == 0x9616)||
2385 (rdev->pdev->device == 0x9611)||
2386 (rdev->pdev->device == 0x9613)||
2387 (rdev->pdev->device == 0x9711)||
2388 (rdev->pdev->device == 0x9713))
2389 rdev->has_uvd = false;
2390 else
2391 rdev->has_uvd = true;
0a10c851
DV		 2392 break;
2393 case CHIP_RV770:
2394 case CHIP_RV730:
2395 case CHIP_RV710:
2396 case CHIP_RV740:
2397 rdev->asic = &rv770_asic;
948bee3f 2398 rdev->has_uvd = true;
0a10c851
DV		 2399 break;
2400 case CHIP_CEDAR:
2401 case CHIP_REDWOOD:
2402 case CHIP_JUNIPER:
2403 case CHIP_CYPRESS:
2404 case CHIP_HEMLOCK:
ba7e05e9
AD		 2405 /* set num crtcs */
2406 if (rdev->family == CHIP_CEDAR)
2407 rdev->num_crtc = 4;
2408 else
2409 rdev->num_crtc = 6;
0a10c851 2410 rdev->asic = &evergreen_asic;
948bee3f 2411 rdev->has_uvd = true;
0a10c851 2412 break;
958261d1 2413 case CHIP_PALM:
89da5a37
AD		 2414 case CHIP_SUMO:
2415 case CHIP_SUMO2:
958261d1 2416 rdev->asic = &sumo_asic;
948bee3f 2417 rdev->has_uvd = true;
958261d1 2418 break;
a43b7665
AD		 2419 case CHIP_BARTS:
2420 case CHIP_TURKS:
2421 case CHIP_CAICOS:
ba7e05e9
AD		 2422 /* set num crtcs */
2423 if (rdev->family == CHIP_CAICOS)
2424 rdev->num_crtc = 4;
2425 else
2426 rdev->num_crtc = 6;
a43b7665 2427 rdev->asic = &btc_asic;
948bee3f 2428 rdev->has_uvd = true;
a43b7665 2429 break;
e3487629
AD		 2430 case CHIP_CAYMAN:
2431 rdev->asic = &cayman_asic;
ba7e05e9
AD		 2432 /* set num crtcs */
2433 rdev->num_crtc = 6;
948bee3f 2434 rdev->has_uvd = true;
e3487629 2435 break;
be63fe8c
AD		 2436 case CHIP_ARUBA:
2437 rdev->asic = &trinity_asic;
2438 /* set num crtcs */
2439 rdev->num_crtc = 4;
948bee3f 2440 rdev->has_uvd = true;
be63fe8c 2441 break;
02779c08
AD		 2442 case CHIP_TAHITI:
2443 case CHIP_PITCAIRN:
2444 case CHIP_VERDE:
e737a14c 2445 case CHIP_OLAND:
86a45cac 2446 case CHIP_HAINAN:
02779c08
AD		 2447 rdev->asic = &si_asic;
2448 /* set num crtcs */
86a45cac
AD		 2449 if (rdev->family == CHIP_HAINAN)
2450 rdev->num_crtc = 0;
2451 else if (rdev->family == CHIP_OLAND)
e737a14c
AD		 2452 rdev->num_crtc = 2;
2453 else
2454 rdev->num_crtc = 6;
948bee3f
AD		 2455 if (rdev->family == CHIP_HAINAN)
2456 rdev->has_uvd = false;
2457 else
2458 rdev->has_uvd = true;
0116e1ef
AD		 2459 switch (rdev->family) {
2460 case CHIP_TAHITI:
2461 rdev->cg_flags =
090f4b6a 2462 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2463 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2464 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2465 RADEON_CG_SUPPORT_GFX_CGLS |
2466 RADEON_CG_SUPPORT_GFX_CGTS |
2467 RADEON_CG_SUPPORT_GFX_CP_LS |
2468 RADEON_CG_SUPPORT_MC_MGCG |
2469 RADEON_CG_SUPPORT_SDMA_MGCG |
2470 RADEON_CG_SUPPORT_BIF_LS |
2471 RADEON_CG_SUPPORT_VCE_MGCG |
2472 RADEON_CG_SUPPORT_UVD_MGCG |
2473 RADEON_CG_SUPPORT_HDP_LS |
2474 RADEON_CG_SUPPORT_HDP_MGCG;
2475 rdev->pg_flags = 0;
2476 break;
2477 case CHIP_PITCAIRN:
2478 rdev->cg_flags =
090f4b6a 2479 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2480 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2481 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2482 RADEON_CG_SUPPORT_GFX_CGLS |
2483 RADEON_CG_SUPPORT_GFX_CGTS |
2484 RADEON_CG_SUPPORT_GFX_CP_LS |
2485 RADEON_CG_SUPPORT_GFX_RLC_LS |
2486 RADEON_CG_SUPPORT_MC_LS |
2487 RADEON_CG_SUPPORT_MC_MGCG |
2488 RADEON_CG_SUPPORT_SDMA_MGCG |
2489 RADEON_CG_SUPPORT_BIF_LS |
2490 RADEON_CG_SUPPORT_VCE_MGCG |
2491 RADEON_CG_SUPPORT_UVD_MGCG |
2492 RADEON_CG_SUPPORT_HDP_LS |
2493 RADEON_CG_SUPPORT_HDP_MGCG;
2494 rdev->pg_flags = 0;
2495 break;
2496 case CHIP_VERDE:
2497 rdev->cg_flags =
090f4b6a 2498 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2499 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2500 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2501 RADEON_CG_SUPPORT_GFX_CGLS |
2502 RADEON_CG_SUPPORT_GFX_CGTS |
2503 RADEON_CG_SUPPORT_GFX_CP_LS |
2504 RADEON_CG_SUPPORT_GFX_RLC_LS |
2505 RADEON_CG_SUPPORT_MC_LS |
2506 RADEON_CG_SUPPORT_MC_MGCG |
2507 RADEON_CG_SUPPORT_SDMA_MGCG |
2508 RADEON_CG_SUPPORT_BIF_LS |
2509 RADEON_CG_SUPPORT_VCE_MGCG |
2510 RADEON_CG_SUPPORT_UVD_MGCG |
2511 RADEON_CG_SUPPORT_HDP_LS |
2512 RADEON_CG_SUPPORT_HDP_MGCG;
ca6ebb39 2513 rdev->pg_flags = 0 |
2b19d17f 2514 /*RADEON_PG_SUPPORT_GFX_PG | */
ca6ebb39 2515 RADEON_PG_SUPPORT_SDMA;
0116e1ef
AD		 2516 break;
2517 case CHIP_OLAND:
2518 rdev->cg_flags =
090f4b6a 2519 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2520 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2521 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2522 RADEON_CG_SUPPORT_GFX_CGLS |
2523 RADEON_CG_SUPPORT_GFX_CGTS |
2524 RADEON_CG_SUPPORT_GFX_CP_LS |
2525 RADEON_CG_SUPPORT_GFX_RLC_LS |
2526 RADEON_CG_SUPPORT_MC_LS |
2527 RADEON_CG_SUPPORT_MC_MGCG |
2528 RADEON_CG_SUPPORT_SDMA_MGCG |
2529 RADEON_CG_SUPPORT_BIF_LS |
2530 RADEON_CG_SUPPORT_UVD_MGCG |
2531 RADEON_CG_SUPPORT_HDP_LS |
2532 RADEON_CG_SUPPORT_HDP_MGCG;
2533 rdev->pg_flags = 0;
2534 break;
2535 case CHIP_HAINAN:
2536 rdev->cg_flags =
090f4b6a 2537 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2538 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2539 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2540 RADEON_CG_SUPPORT_GFX_CGLS |
2541 RADEON_CG_SUPPORT_GFX_CGTS |
2542 RADEON_CG_SUPPORT_GFX_CP_LS |
2543 RADEON_CG_SUPPORT_GFX_RLC_LS |
2544 RADEON_CG_SUPPORT_MC_LS |
2545 RADEON_CG_SUPPORT_MC_MGCG |
2546 RADEON_CG_SUPPORT_SDMA_MGCG |
2547 RADEON_CG_SUPPORT_BIF_LS |
2548 RADEON_CG_SUPPORT_HDP_LS |
2549 RADEON_CG_SUPPORT_HDP_MGCG;
2550 rdev->pg_flags = 0;
2551 break;
2552 default:
2553 rdev->cg_flags = 0;
2554 rdev->pg_flags = 0;
2555 break;
2556 }
02779c08 2557 break;
0672e27b 2558 case CHIP_BONAIRE:
41971b37 2559 case CHIP_HAWAII:
0672e27b
AD		 2560 rdev->asic = &ci_asic;
2561 rdev->num_crtc = 6;
22c775ce 2562 rdev->has_uvd = true;
41971b37
AD		 2563 if (rdev->family == CHIP_BONAIRE) {
2564 rdev->cg_flags =
2565 RADEON_CG_SUPPORT_GFX_MGCG |
2566 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2567 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2568 RADEON_CG_SUPPORT_GFX_CGLS |
2569 RADEON_CG_SUPPORT_GFX_CGTS |
2570 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2571 RADEON_CG_SUPPORT_GFX_CP_LS |
2572 RADEON_CG_SUPPORT_MC_LS |
2573 RADEON_CG_SUPPORT_MC_MGCG |
2574 RADEON_CG_SUPPORT_SDMA_MGCG |
2575 RADEON_CG_SUPPORT_SDMA_LS |
2576 RADEON_CG_SUPPORT_BIF_LS |
2577 RADEON_CG_SUPPORT_VCE_MGCG |
2578 RADEON_CG_SUPPORT_UVD_MGCG |
2579 RADEON_CG_SUPPORT_HDP_LS |
2580 RADEON_CG_SUPPORT_HDP_MGCG;
2581 rdev->pg_flags = 0;
2582 } else {
2583 rdev->cg_flags =
2584 RADEON_CG_SUPPORT_GFX_MGCG |
2585 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2586 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2587 RADEON_CG_SUPPORT_GFX_CGLS |
2588 RADEON_CG_SUPPORT_GFX_CGTS |
2589 RADEON_CG_SUPPORT_GFX_CP_LS |
2590 RADEON_CG_SUPPORT_MC_LS |
2591 RADEON_CG_SUPPORT_MC_MGCG |
2592 RADEON_CG_SUPPORT_SDMA_MGCG |
2593 RADEON_CG_SUPPORT_SDMA_LS |
2594 RADEON_CG_SUPPORT_BIF_LS |
2595 RADEON_CG_SUPPORT_VCE_MGCG |
2596 RADEON_CG_SUPPORT_UVD_MGCG |
2597 RADEON_CG_SUPPORT_HDP_LS |
2598 RADEON_CG_SUPPORT_HDP_MGCG;
2599 rdev->pg_flags = 0;
2600 }
0672e27b
AD		 2601 break;
2602 case CHIP_KAVERI:
2603 case CHIP_KABINI:
b0a9f22a 2604 case CHIP_MULLINS:
0672e27b
AD		 2605 rdev->asic = &kv_asic;
2606 /* set num crtcs */
473359bc 2607 if (rdev->family == CHIP_KAVERI) {
0672e27b 2608 rdev->num_crtc = 4;
473359bc 2609 rdev->cg_flags =
773dc10a 2610 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2611 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2612 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2613 RADEON_CG_SUPPORT_GFX_CGLS |
2614 RADEON_CG_SUPPORT_GFX_CGTS |
2615 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2616 RADEON_CG_SUPPORT_GFX_CP_LS |
2617 RADEON_CG_SUPPORT_SDMA_MGCG |
2618 RADEON_CG_SUPPORT_SDMA_LS |
2619 RADEON_CG_SUPPORT_BIF_LS |
2620 RADEON_CG_SUPPORT_VCE_MGCG |
2621 RADEON_CG_SUPPORT_UVD_MGCG |
2622 RADEON_CG_SUPPORT_HDP_LS |
2623 RADEON_CG_SUPPORT_HDP_MGCG;
2624 rdev->pg_flags = 0;
2b19d17f 2625 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2626 RADEON_PG_SUPPORT_GFX_SMG |
2627 RADEON_PG_SUPPORT_GFX_DMG |
2628 RADEON_PG_SUPPORT_UVD |
2629 RADEON_PG_SUPPORT_VCE |
2630 RADEON_PG_SUPPORT_CP |
2631 RADEON_PG_SUPPORT_GDS |
2632 RADEON_PG_SUPPORT_RLC_SMU_HS |
2633 RADEON_PG_SUPPORT_ACP |
2634 RADEON_PG_SUPPORT_SAMU;*/
2635 } else {
0672e27b 2636 rdev->num_crtc = 2;
473359bc 2637 rdev->cg_flags =
773dc10a 2638 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2639 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2640 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2641 RADEON_CG_SUPPORT_GFX_CGLS |
2642 RADEON_CG_SUPPORT_GFX_CGTS |
2643 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2644 RADEON_CG_SUPPORT_GFX_CP_LS |
2645 RADEON_CG_SUPPORT_SDMA_MGCG |
2646 RADEON_CG_SUPPORT_SDMA_LS |
2647 RADEON_CG_SUPPORT_BIF_LS |
2648 RADEON_CG_SUPPORT_VCE_MGCG |
2649 RADEON_CG_SUPPORT_UVD_MGCG |
2650 RADEON_CG_SUPPORT_HDP_LS |
2651 RADEON_CG_SUPPORT_HDP_MGCG;
2652 rdev->pg_flags = 0;
2b19d17f 2653 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2654 RADEON_PG_SUPPORT_GFX_SMG |
2655 RADEON_PG_SUPPORT_UVD |
2656 RADEON_PG_SUPPORT_VCE |
2657 RADEON_PG_SUPPORT_CP |
2658 RADEON_PG_SUPPORT_GDS |
2659 RADEON_PG_SUPPORT_RLC_SMU_HS |
2660 RADEON_PG_SUPPORT_SAMU;*/
2661 }
22c775ce 2662 rdev->has_uvd = true;
0672e27b 2663 break;
0a10c851
DV		 2664 default:
2665 /* FIXME: not supported yet */
2666 return -EINVAL;
2667 }
2668
2669 if (rdev->flags & RADEON_IS_IGP) {
798bcf73
AD		 2670 rdev->asic->pm.get_memory_clock = NULL;
2671 rdev->asic->pm.set_memory_clock = NULL;
0a10c851
DV		 2672 }
2673
2674 return 0;
2675}
2676
Linux 6.x block layer and io_uring tree(s)