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drm/radeon/kms: add accessors for RCU indirect space
[linux-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
771fe6b9
JG		 99
100/*
101 * Copy from radeon_drv.h so we don't have to include both and have conflicting
102 * symbol;
103 */
bb635567
JG		 104#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
105#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 106/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 107#define RADEON_IB_POOL_SIZE 16
108#define RADEON_DEBUGFS_MAX_COMPONENTS 32
109#define RADEONFB_CONN_LIMIT 4
110#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 111
1b37078b 112/* max number of rings */
f2ba57b5 113#define RADEON_NUM_RINGS 6
bb635567
JG		 114
115/* fence seq are set to this number when signaled */
116#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 117
118/* internal ring indices */
119/* r1xx+ has gfx CP ring */
f2ba57b5 120#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 121
122/* cayman has 2 compute CP rings */
f2ba57b5
CK		 123#define CAYMAN_RING_TYPE_CP1_INDEX 1
124#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 125
4d75658b
AD		 126/* R600+ has an async dma ring */
127#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 128/* cayman add a second async dma ring */
129#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 130
f2ba57b5
CK		 131/* R600+ */
132#define R600_RING_TYPE_UVD_INDEX 5
133
721604a1 134/* hardcode those limit for now */
ca19f21e 135#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 136#define RADEON_VA_RESERVED_SIZE (8 << 20)
137#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 138
ec46c76d
AD		 139/* reset flags */
140#define RADEON_RESET_GFX (1 << 0)
141#define RADEON_RESET_COMPUTE (1 << 1)
142#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 143#define RADEON_RESET_CP (1 << 3)
144#define RADEON_RESET_GRBM (1 << 4)
145#define RADEON_RESET_DMA1 (1 << 5)
146#define RADEON_RESET_RLC (1 << 6)
147#define RADEON_RESET_SEM (1 << 7)
148#define RADEON_RESET_IH (1 << 8)
149#define RADEON_RESET_VMC (1 << 9)
150#define RADEON_RESET_MC (1 << 10)
151#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 152
9e05fa1d
AD		 153/* max cursor sizes (in pixels) */
154#define CURSOR_WIDTH 64
155#define CURSOR_HEIGHT 64
156
157#define CIK_CURSOR_WIDTH 128
158#define CIK_CURSOR_HEIGHT 128
159
771fe6b9
JG		 160/*
161 * Errata workarounds.
162 */
163enum radeon_pll_errata {
164 CHIP_ERRATA_R300_CG = 0x00000001,
165 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
166 CHIP_ERRATA_PLL_DELAY = 0x00000004
167};
168
169
170struct radeon_device;
171
172
173/*
174 * BIOS.
175 */
176bool radeon_get_bios(struct radeon_device *rdev);
177
178/*
3ce0a23d 179 * Dummy page
771fe6b9 180 */
3ce0a23d
JG		 181struct radeon_dummy_page {
182 struct page *page;
183 dma_addr_t addr;
184};
185int radeon_dummy_page_init(struct radeon_device *rdev);
186void radeon_dummy_page_fini(struct radeon_device *rdev);
187
771fe6b9 188
3ce0a23d
JG		 189/*
190 * Clocks
191 */
771fe6b9
JG		 192struct radeon_clock {
193 struct radeon_pll p1pll;
194 struct radeon_pll p2pll;
bcc1c2a1 195 struct radeon_pll dcpll;
771fe6b9
JG		 196 struct radeon_pll spll;
197 struct radeon_pll mpll;
198 /* 10 Khz units */
199 uint32_t default_mclk;
200 uint32_t default_sclk;
bcc1c2a1
AD		 201 uint32_t default_dispclk;
202 uint32_t dp_extclk;
b20f9bef 203 uint32_t max_pixel_clock;
771fe6b9
JG		 204};
205
7433874e
RM		 206/*
207 * Power management
208 */
209int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 210void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 211void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 212void radeon_pm_suspend(struct radeon_device *rdev);
213void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 214void radeon_combios_get_power_modes(struct radeon_device *rdev);
215void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 216int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
217 u8 clock_type,
218 u32 clock,
219 bool strobe_mode,
220 struct atom_clock_dividers *dividers);
8a83ec5e 221void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
f892034a 222void rs690_pm_info(struct radeon_device *rdev);
20d391d7
AD		 223extern int rv6xx_get_temp(struct radeon_device *rdev);
224extern int rv770_get_temp(struct radeon_device *rdev);
225extern int evergreen_get_temp(struct radeon_device *rdev);
226extern int sumo_get_temp(struct radeon_device *rdev);
1bd47d2e 227extern int si_get_temp(struct radeon_device *rdev);
285484e2
JG		 228extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
229 unsigned *bankh, unsigned *mtaspect,
230 unsigned *tile_split);
3ce0a23d 231
771fe6b9
JG		 232/*
233 * Fences.
234 */
235struct radeon_fence_driver {
236 uint32_t scratch_reg;
30eb77f4
JG		 237 uint64_t gpu_addr;
238 volatile uint32_t *cpu_addr;
68e250b7
CK		 239 /* sync_seq is protected by ring emission lock */
240 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 241 atomic64_t last_seq;
36abacae 242 unsigned long last_activity;
0a0c7596 243 bool initialized;
771fe6b9
JG		 244};
245
246struct radeon_fence {
247 struct radeon_device *rdev;
248 struct kref kref;
771fe6b9 249 /* protected by radeon_fence.lock */
bb635567 250 uint64_t seq;
7465280c 251 /* RB, DMA, etc. */
bb635567 252 unsigned ring;
771fe6b9
JG		 253};
254
30eb77f4
JG		 255int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
256int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 257void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 258void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 259int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 260void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 261bool radeon_fence_signaled(struct radeon_fence *fence);
262int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
8a47cc9e 263int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 264int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 265int radeon_fence_wait_any(struct radeon_device *rdev,
266 struct radeon_fence **fences,
267 bool intr);
771fe6b9
JG		 268struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
269void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 270unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 271bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
272void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
273static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
274 struct radeon_fence *b)
275{
276 if (!a) {
277 return b;
278 }
279
280 if (!b) {
281 return a;
282 }
283
284 BUG_ON(a->ring != b->ring);
285
286 if (a->seq > b->seq) {
287 return a;
288 } else {
289 return b;
290 }
291}
771fe6b9 292
ee60e29f
CK		 293static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
294 struct radeon_fence *b)
295{
296 if (!a) {
297 return false;
298 }
299
300 if (!b) {
301 return true;
302 }
303
304 BUG_ON(a->ring != b->ring);
305
306 return a->seq < b->seq;
307}
308
e024e110
DA		 309/*
310 * Tiling registers
311 */
312struct radeon_surface_reg {
4c788679 313 struct radeon_bo *bo;
e024e110
DA		 314};
315
316#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 317
318/*
4c788679 319 * TTM.
771fe6b9 320 */
4c788679
JG		 321struct radeon_mman {
322 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 323 struct drm_global_reference mem_global_ref;
4c788679 324 struct ttm_bo_device bdev;
0a0c7596
JG		 325 bool mem_global_referenced;
326 bool initialized;
4c788679
JG		 327};
328
721604a1
JG		 329/* bo virtual address in a specific vm */
330struct radeon_bo_va {
e971bd5e 331 /* protected by bo being reserved */
721604a1 332 struct list_head bo_list;
721604a1
JG		 333 uint64_t soffset;
334 uint64_t eoffset;
335 uint32_t flags;
336 bool valid;
e971bd5e
CK		 337 unsigned ref_count;
338
339 /* protected by vm mutex */
340 struct list_head vm_list;
341
342 /* constant after initialization */
343 struct radeon_vm *vm;
344 struct radeon_bo *bo;
721604a1
JG		 345};
346
4c788679
JG		 347struct radeon_bo {
348 /* Protected by gem.mutex */
349 struct list_head list;
350 /* Protected by tbo.reserved */
312ea8da
JG		 351 u32 placements[3];
352 struct ttm_placement placement;
4c788679
JG		 353 struct ttm_buffer_object tbo;
354 struct ttm_bo_kmap_obj kmap;
355 unsigned pin_count;
356 void *kptr;
357 u32 tiling_flags;
358 u32 pitch;
359 int surface_reg;
721604a1
JG		 360 /* list of all virtual address to which this bo
361 * is associated to
362 */
363 struct list_head va;
4c788679
JG		 364 /* Constant after initialization */
365 struct radeon_device *rdev;
441921d5 366 struct drm_gem_object gem_base;
63bc620b 367
409851f4
JG		 368 struct ttm_bo_kmap_obj dma_buf_vmap;
369 pid_t pid;
4c788679 370};
7e4d15d9 371#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 372
4c788679 373struct radeon_bo_list {
147666fb 374 struct ttm_validate_buffer tv;
4c788679 375 struct radeon_bo *bo;
771fe6b9 376 uint64_t gpu_offset;
4474f3a9
CK		 377 bool written;
378 unsigned domain;
379 unsigned alt_domain;
4c788679 380 u32 tiling_flags;
771fe6b9
JG		 381};
382
409851f4
JG		 383int radeon_gem_debugfs_init(struct radeon_device *rdev);
384
b15ba512
JG		 385/* sub-allocation manager, it has to be protected by another lock.
386 * By conception this is an helper for other part of the driver
387 * like the indirect buffer or semaphore, which both have their
388 * locking.
389 *
390 * Principe is simple, we keep a list of sub allocation in offset
391 * order (first entry has offset == 0, last entry has the highest
392 * offset).
393 *
394 * When allocating new object we first check if there is room at
395 * the end total_size - (last_object_offset + last_object_size) >=
396 * alloc_size. If so we allocate new object there.
397 *
398 * When there is not enough room at the end, we start waiting for
399 * each sub object until we reach object_offset+object_size >=
400 * alloc_size, this object then become the sub object we return.
401 *
402 * Alignment can't be bigger than page size.
403 *
404 * Hole are not considered for allocation to keep things simple.
405 * Assumption is that there won't be hole (all object on same
406 * alignment).
407 */
408struct radeon_sa_manager {
bfb38d35 409 wait_queue_head_t wq;
b15ba512 410 struct radeon_bo *bo;
c3b7fe8b
CK		 411 struct list_head *hole;
412 struct list_head flist[RADEON_NUM_RINGS];
413 struct list_head olist;
b15ba512
JG		 414 unsigned size;
415 uint64_t gpu_addr;
416 void *cpu_ptr;
417 uint32_t domain;
418};
419
420struct radeon_sa_bo;
421
422/* sub-allocation buffer */
423struct radeon_sa_bo {
c3b7fe8b
CK		 424 struct list_head olist;
425 struct list_head flist;
b15ba512 426 struct radeon_sa_manager *manager;
e6661a96
CK		 427 unsigned soffset;
428 unsigned eoffset;
557017a0 429 struct radeon_fence *fence;
b15ba512
JG		 430};
431
771fe6b9
JG		 432/*
433 * GEM objects.
434 */
435struct radeon_gem {
4c788679 436 struct mutex mutex;
771fe6b9
JG		 437 struct list_head objects;
438};
439
440int radeon_gem_init(struct radeon_device *rdev);
441void radeon_gem_fini(struct radeon_device *rdev);
442int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 443 int alignment, int initial_domain,
444 bool discardable, bool kernel,
445 struct drm_gem_object **obj);
771fe6b9 446
ff72145b
DA		 447int radeon_mode_dumb_create(struct drm_file *file_priv,
448 struct drm_device *dev,
449 struct drm_mode_create_dumb *args);
450int radeon_mode_dumb_mmap(struct drm_file *filp,
451 struct drm_device *dev,
452 uint32_t handle, uint64_t *offset_p);
453int radeon_mode_dumb_destroy(struct drm_file *file_priv,
454 struct drm_device *dev,
455 uint32_t handle);
771fe6b9 456
c1341e52
JG		 457/*
458 * Semaphores.
459 */
c1341e52
JG		 460/* everything here is constant */
461struct radeon_semaphore {
a8c05940
JG		 462 struct radeon_sa_bo *sa_bo;
463 signed waiters;
c1341e52 464 uint64_t gpu_addr;
c1341e52
JG		 465};
466
c1341e52
JG		 467int radeon_semaphore_create(struct radeon_device *rdev,
468 struct radeon_semaphore **semaphore);
469void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
470 struct radeon_semaphore *semaphore);
471void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
472 struct radeon_semaphore *semaphore);
8f676c4c
CK		 473int radeon_semaphore_sync_rings(struct radeon_device *rdev,
474 struct radeon_semaphore *semaphore,
220907d9 475 int signaler, int waiter);
c1341e52 476void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 477 struct radeon_semaphore **semaphore,
a8c05940 478 struct radeon_fence *fence);
c1341e52 479
771fe6b9
JG		 480/*
481 * GART structures, functions & helpers
482 */
483struct radeon_mc;
484
a77f1718 485#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 486#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 487#define RADEON_GPU_PAGE_SHIFT 12
721604a1 488#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 489
771fe6b9
JG		 490struct radeon_gart {
491 dma_addr_t table_addr;
c9a1be96
JG		 492 struct radeon_bo *robj;
493 void *ptr;
771fe6b9
JG		 494 unsigned num_gpu_pages;
495 unsigned num_cpu_pages;
496 unsigned table_size;
771fe6b9
JG		 497 struct page **pages;
498 dma_addr_t *pages_addr;
499 bool ready;
500};
501
502int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
503void radeon_gart_table_ram_free(struct radeon_device *rdev);
504int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
505void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 506int radeon_gart_table_vram_pin(struct radeon_device *rdev);
507void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 508int radeon_gart_init(struct radeon_device *rdev);
509void radeon_gart_fini(struct radeon_device *rdev);
510void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
511 int pages);
512int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 513 int pages, struct page **pagelist,
514 dma_addr_t *dma_addr);
c9a1be96 515void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 516
517
518/*
519 * GPU MC structures, functions & helpers
520 */
521struct radeon_mc {
522 resource_size_t aper_size;
523 resource_size_t aper_base;
524 resource_size_t agp_base;
7a50f01a
DA		 525 /* for some chips with <= 32MB we need to lie
526 * about vram size near mc fb location */
3ce0a23d 527 u64 mc_vram_size;
d594e46a 528 u64 visible_vram_size;
3ce0a23d
JG		 529 u64 gtt_size;
530 u64 gtt_start;
531 u64 gtt_end;
3ce0a23d
JG		 532 u64 vram_start;
533 u64 vram_end;
771fe6b9 534 unsigned vram_width;
3ce0a23d 535 u64 real_vram_size;
771fe6b9
JG		 536 int vram_mtrr;
537 bool vram_is_ddr;
d594e46a 538 bool igp_sideport_enabled;
8d369bb1 539 u64 gtt_base_align;
9ed8b1f9 540 u64 mc_mask;
771fe6b9
JG		 541};
542
06b6476d
AD		 543bool radeon_combios_sideport_present(struct radeon_device *rdev);
544bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 545
546/*
547 * GPU scratch registers structures, functions & helpers
548 */
549struct radeon_scratch {
550 unsigned num_reg;
724c80e1 551 uint32_t reg_base;
771fe6b9
JG		 552 bool free[32];
553 uint32_t reg[32];
554};
555
556int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
557void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
558
75efdee1
AD		 559/*
560 * GPU doorbell structures, functions & helpers
561 */
562struct radeon_doorbell {
563 u32 num_pages;
564 bool free[1024];
565 /* doorbell mmio */
566 resource_size_t base;
567 resource_size_t size;
568 void __iomem *ptr;
569};
570
571int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
572void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 573
574/*
575 * IRQS.
576 */
6f34be50
AD		 577
578struct radeon_unpin_work {
579 struct work_struct work;
580 struct radeon_device *rdev;
581 int crtc_id;
582 struct radeon_fence *fence;
583 struct drm_pending_vblank_event *event;
584 struct radeon_bo *old_rbo;
585 u64 new_crtc_base;
586};
587
588struct r500_irq_stat_regs {
589 u32 disp_int;
f122c610 590 u32 hdmi0_status;
6f34be50
AD		 591};
592
593struct r600_irq_stat_regs {
594 u32 disp_int;
595 u32 disp_int_cont;
596 u32 disp_int_cont2;
597 u32 d1grph_int;
598 u32 d2grph_int;
f122c610
AD		 599 u32 hdmi0_status;
600 u32 hdmi1_status;
6f34be50
AD		 601};
602
603struct evergreen_irq_stat_regs {
604 u32 disp_int;
605 u32 disp_int_cont;
606 u32 disp_int_cont2;
607 u32 disp_int_cont3;
608 u32 disp_int_cont4;
609 u32 disp_int_cont5;
610 u32 d1grph_int;
611 u32 d2grph_int;
612 u32 d3grph_int;
613 u32 d4grph_int;
614 u32 d5grph_int;
615 u32 d6grph_int;
f122c610
AD		 616 u32 afmt_status1;
617 u32 afmt_status2;
618 u32 afmt_status3;
619 u32 afmt_status4;
620 u32 afmt_status5;
621 u32 afmt_status6;
6f34be50
AD		 622};
623
a59781bb
AD		 624struct cik_irq_stat_regs {
625 u32 disp_int;
626 u32 disp_int_cont;
627 u32 disp_int_cont2;
628 u32 disp_int_cont3;
629 u32 disp_int_cont4;
630 u32 disp_int_cont5;
631 u32 disp_int_cont6;
632};
633
6f34be50
AD		 634union radeon_irq_stat_regs {
635 struct r500_irq_stat_regs r500;
636 struct r600_irq_stat_regs r600;
637 struct evergreen_irq_stat_regs evergreen;
a59781bb 638 struct cik_irq_stat_regs cik;
6f34be50
AD		 639};
640
54bd5206
IH		 641#define RADEON_MAX_HPD_PINS 6
642#define RADEON_MAX_CRTCS 6
f122c610 643#define RADEON_MAX_AFMT_BLOCKS 6
54bd5206 644
771fe6b9 645struct radeon_irq {
fb98257a
CK		 646 bool installed;
647 spinlock_t lock;
736fc37f 648 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 649 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 650 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 651 wait_queue_head_t vblank_queue;
652 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 653 bool afmt[RADEON_MAX_AFMT_BLOCKS];
654 union radeon_irq_stat_regs stat_regs;
771fe6b9
JG		 655};
656
657int radeon_irq_kms_init(struct radeon_device *rdev);
658void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 659void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
660void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 661void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
662void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 663void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
664void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
665void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
666void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 667
668/*
e32eb50d 669 * CP & rings.
771fe6b9 670 */
7465280c 671
771fe6b9 672struct radeon_ib {
68470ae7
JG		 673 struct radeon_sa_bo *sa_bo;
674 uint32_t length_dw;
675 uint64_t gpu_addr;
676 uint32_t *ptr;
876dc9f3 677 int ring;
68470ae7 678 struct radeon_fence *fence;
4bf3dd92 679 struct radeon_vm *vm;
68470ae7 680 bool is_const_ib;
220907d9 681 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
68470ae7 682 struct radeon_semaphore *semaphore;
771fe6b9
JG		 683};
684
e32eb50d 685struct radeon_ring {
4c788679 686 struct radeon_bo *ring_obj;
771fe6b9
JG		 687 volatile uint32_t *ring;
688 unsigned rptr;
5596a9db
CK		 689 unsigned rptr_offs;
690 unsigned rptr_reg;
45df6803 691 unsigned rptr_save_reg;
89d35807
AD		 692 u64 next_rptr_gpu_addr;
693 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 694 unsigned wptr;
695 unsigned wptr_old;
5596a9db 696 unsigned wptr_reg;
771fe6b9
JG		 697 unsigned ring_size;
698 unsigned ring_free_dw;
699 int count_dw;
069211e5
CK		 700 unsigned long last_activity;
701 unsigned last_rptr;
771fe6b9
JG		 702 uint64_t gpu_addr;
703 uint32_t align_mask;
704 uint32_t ptr_mask;
771fe6b9 705 bool ready;
78c5560a
AD		 706 u32 ptr_reg_shift;
707 u32 ptr_reg_mask;
708 u32 nop;
8b25ed34 709 u32 idx;
5f0839c1
JG		 710 u64 last_semaphore_signal_addr;
711 u64 last_semaphore_wait_addr;
963e81f9
AD		 712 /* for CIK queues */
713 u32 me;
714 u32 pipe;
715 u32 queue;
716 struct radeon_bo *mqd_obj;
717 u32 doorbell_page_num;
718 u32 doorbell_offset;
719 unsigned wptr_offs;
720};
721
722struct radeon_mec {
723 struct radeon_bo *hpd_eop_obj;
724 u64 hpd_eop_gpu_addr;
725 u32 num_pipe;
726 u32 num_mec;
727 u32 num_queue;
771fe6b9
JG		 728};
729
721604a1
JG		 730/*
731 * VM
732 */
ee60e29f 733
fa87e62d 734/* maximum number of VMIDs */
ee60e29f
CK		 735#define RADEON_NUM_VM 16
736
fa87e62d
DC		 737/* defines number of bits in page table versus page directory,
738 * a page is 4KB so we have 12 bits offset, 9 bits in the page
739 * table and the remaining 19 bits are in the page directory */
740#define RADEON_VM_BLOCK_SIZE 9
741
742/* number of entries in page table */
743#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
744
721604a1
JG		 745struct radeon_vm {
746 struct list_head list;
747 struct list_head va;
ee60e29f 748 unsigned id;
90a51a32
CK		 749
750 /* contains the page directory */
751 struct radeon_sa_bo *page_directory;
752 uint64_t pd_gpu_addr;
753
754 /* array of page tables, one for each page directory entry */
755 struct radeon_sa_bo **page_tables;
756
721604a1
JG		 757 struct mutex mutex;
758 /* last fence for cs using this vm */
759 struct radeon_fence *fence;
9b40e5d8
CK		 760 /* last flush or NULL if we still need to flush */
761 struct radeon_fence *last_flush;
721604a1
JG		 762};
763
721604a1 764struct radeon_vm_manager {
36ff39c4 765 struct mutex lock;
721604a1 766 struct list_head lru_vm;
ee60e29f 767 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 768 struct radeon_sa_manager sa_manager;
769 uint32_t max_pfn;
721604a1
JG		 770 /* number of VMIDs */
771 unsigned nvm;
772 /* vram base address for page table entry */
773 u64 vram_base_offset;
67e915e4
AD		 774 /* is vm enabled? */
775 bool enabled;
721604a1
JG		 776};
777
778/*
779 * file private structure
780 */
781struct radeon_fpriv {
782 struct radeon_vm vm;
783};
784
d8f60cfc
AD		 785/*
786 * R6xx+ IH ring
787 */
788struct r600_ih {
4c788679 789 struct radeon_bo *ring_obj;
d8f60cfc
AD		 790 volatile uint32_t *ring;
791 unsigned rptr;
d8f60cfc
AD		 792 unsigned ring_size;
793 uint64_t gpu_addr;
d8f60cfc 794 uint32_t ptr_mask;
c20dc369 795 atomic_t lock;
d8f60cfc
AD		 796 bool enabled;
797};
798
8eec9d6f
IH		 799struct r600_blit_cp_primitives {
800 void (*set_render_target)(struct radeon_device *rdev, int format,
801 int w, int h, u64 gpu_addr);
802 void (*cp_set_surface_sync)(struct radeon_device *rdev,
803 u32 sync_type, u32 size,
804 u64 mc_addr);
805 void (*set_shaders)(struct radeon_device *rdev);
806 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
807 void (*set_tex_resource)(struct radeon_device *rdev,
808 int format, int w, int h, int pitch,
9bb7703c 809 u64 gpu_addr, u32 size);
8eec9d6f
IH		 810 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
811 int x2, int y2);
812 void (*draw_auto)(struct radeon_device *rdev);
813 void (*set_default_state)(struct radeon_device *rdev);
814};
815
3ce0a23d 816struct r600_blit {
4c788679 817 struct radeon_bo *shader_obj;
8eec9d6f
IH		 818 struct r600_blit_cp_primitives primitives;
819 int max_dim;
820 int ring_size_common;
821 int ring_size_per_loop;
3ce0a23d
JG		 822 u64 shader_gpu_addr;
823 u32 vs_offset, ps_offset;
824 u32 state_offset;
825 u32 state_len;
3ce0a23d
JG		 826};
827
347e7592
AD		 828/*
829 * SI RLC stuff
830 */
831struct si_rlc {
832 /* for power gating */
833 struct radeon_bo *save_restore_obj;
834 uint64_t save_restore_gpu_addr;
835 /* for clear state */
836 struct radeon_bo *clear_state_obj;
837 uint64_t clear_state_gpu_addr;
838};
839
69e130a6 840int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 841 struct radeon_ib *ib, struct radeon_vm *vm,
842 unsigned size);
f2e39221 843void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
43f1214a 844void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
4ef72566
CK		 845int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
846 struct radeon_ib *const_ib);
771fe6b9
JG		 847int radeon_ib_pool_init(struct radeon_device *rdev);
848void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 849int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 850/* Ring access between begin & end cannot sleep */
89d35807
AD		 851bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
852 struct radeon_ring *ring);
e32eb50d
CK		 853void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
854int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
855int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
856void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
857void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 858void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 859void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
860int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 861void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 862void radeon_ring_lockup_update(struct radeon_ring *ring);
863bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 864unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
865 uint32_t **data);
866int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
867 unsigned size, uint32_t *data);
e32eb50d 868int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
78c5560a
AD		 869 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
870 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
e32eb50d 871void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 872
873
4d75658b
AD		 874/* r600 async dma */
875void r600_dma_stop(struct radeon_device *rdev);
876int r600_dma_resume(struct radeon_device *rdev);
877void r600_dma_fini(struct radeon_device *rdev);
878
8c5fd7ef
AD		 879void cayman_dma_stop(struct radeon_device *rdev);
880int cayman_dma_resume(struct radeon_device *rdev);
881void cayman_dma_fini(struct radeon_device *rdev);
882
771fe6b9
JG		 883/*
884 * CS.
885 */
886struct radeon_cs_reloc {
887 struct drm_gem_object *gobj;
4c788679
JG		 888 struct radeon_bo *robj;
889 struct radeon_bo_list lobj;
771fe6b9
JG		 890 uint32_t handle;
891 uint32_t flags;
892};
893
894struct radeon_cs_chunk {
895 uint32_t chunk_id;
896 uint32_t length_dw;
721604a1
JG		 897 int kpage_idx[2];
898 uint32_t *kpage[2];
771fe6b9 899 uint32_t *kdata;
721604a1
JG		 900 void __user *user_ptr;
901 int last_copied_page;
902 int last_page_index;
771fe6b9
JG		 903};
904
905struct radeon_cs_parser {
c8c15ff1 906 struct device *dev;
771fe6b9
JG		 907 struct radeon_device *rdev;
908 struct drm_file *filp;
909 /* chunks */
910 unsigned nchunks;
911 struct radeon_cs_chunk *chunks;
912 uint64_t *chunks_array;
913 /* IB */
914 unsigned idx;
915 /* relocations */
916 unsigned nrelocs;
917 struct radeon_cs_reloc *relocs;
918 struct radeon_cs_reloc **relocs_ptr;
919 struct list_head validated;
cf4ccd01 920 unsigned dma_reloc_idx;
771fe6b9
JG		 921 /* indices of various chunks */
922 int chunk_ib_idx;
923 int chunk_relocs_idx;
721604a1 924 int chunk_flags_idx;
dfcf5f36 925 int chunk_const_ib_idx;
f2e39221
JG		 926 struct radeon_ib ib;
927 struct radeon_ib const_ib;
771fe6b9 928 void *track;
3ce0a23d 929 unsigned family;
e70f224c 930 int parser_error;
721604a1
JG		 931 u32 cs_flags;
932 u32 ring;
933 s32 priority;
771fe6b9
JG		 934};
935
513bcb46 936extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
ce580fab 937extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
513bcb46 938
771fe6b9
JG		 939struct radeon_cs_packet {
940 unsigned idx;
941 unsigned type;
942 unsigned reg;
943 unsigned opcode;
944 int count;
945 unsigned one_reg_wr;
946};
947
948typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
949 struct radeon_cs_packet *pkt,
950 unsigned idx, unsigned reg);
951typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
952 struct radeon_cs_packet *pkt);
953
954
955/*
956 * AGP
957 */
958int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 959void radeon_agp_resume(struct radeon_device *rdev);
10b06122 960void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 961void radeon_agp_fini(struct radeon_device *rdev);
962
963
964/*
965 * Writeback
966 */
967struct radeon_wb {
4c788679 968 struct radeon_bo *wb_obj;
771fe6b9
JG		 969 volatile uint32_t *wb;
970 uint64_t gpu_addr;
724c80e1 971 bool enabled;
d0f8a854 972 bool use_event;
771fe6b9
JG		 973};
974
724c80e1 975#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 976#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 977#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 978#define RADEON_WB_CP1_RPTR_OFFSET 1280
979#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 980#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 981#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 982#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
f2ba57b5 983#define R600_WB_UVD_RPTR_OFFSET 2560
d0f8a854 984#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 985#define CIK_WB_CP1_WPTR_OFFSET 3328
986#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 987
c93bb85b
JG		 988/**
989 * struct radeon_pm - power management datas
990 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
991 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
992 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
993 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
994 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
995 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
996 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
997 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
998 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 999 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1000 * @needed_bandwidth: current bandwidth needs
1001 *
1002 * It keeps track of various data needed to take powermanagement decision.
25985edc 1003 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1004 * Equation between gpu/memory clock and available bandwidth is hw dependent
1005 * (type of memory, bus size, efficiency, ...)
1006 */
ce8f5370
AD		 1007
1008enum radeon_pm_method {
1009 PM_METHOD_PROFILE,
1010 PM_METHOD_DYNPM,
1011};
1012
1013enum radeon_dynpm_state {
1014 DYNPM_STATE_DISABLED,
1015 DYNPM_STATE_MINIMUM,
1016 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1017 DYNPM_STATE_ACTIVE,
1018 DYNPM_STATE_SUSPENDED,
c913e23a 1019};
ce8f5370
AD		 1020enum radeon_dynpm_action {
1021 DYNPM_ACTION_NONE,
1022 DYNPM_ACTION_MINIMUM,
1023 DYNPM_ACTION_DOWNCLOCK,
1024 DYNPM_ACTION_UPCLOCK,
1025 DYNPM_ACTION_DEFAULT
c913e23a 1026};
56278a8e
AD		 1027
1028enum radeon_voltage_type {
1029 VOLTAGE_NONE = 0,
1030 VOLTAGE_GPIO,
1031 VOLTAGE_VDDC,
1032 VOLTAGE_SW
1033};
1034
0ec0e74f
AD		 1035enum radeon_pm_state_type {
1036 POWER_STATE_TYPE_DEFAULT,
1037 POWER_STATE_TYPE_POWERSAVE,
1038 POWER_STATE_TYPE_BATTERY,
1039 POWER_STATE_TYPE_BALANCED,
1040 POWER_STATE_TYPE_PERFORMANCE,
1041};
1042
ce8f5370
AD		 1043enum radeon_pm_profile_type {
1044 PM_PROFILE_DEFAULT,
1045 PM_PROFILE_AUTO,
1046 PM_PROFILE_LOW,
c9e75b21 1047 PM_PROFILE_MID,
ce8f5370
AD		 1048 PM_PROFILE_HIGH,
1049};
1050
1051#define PM_PROFILE_DEFAULT_IDX 0
1052#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1053#define PM_PROFILE_MID_SH_IDX 2
1054#define PM_PROFILE_HIGH_SH_IDX 3
1055#define PM_PROFILE_LOW_MH_IDX 4
1056#define PM_PROFILE_MID_MH_IDX 5
1057#define PM_PROFILE_HIGH_MH_IDX 6
1058#define PM_PROFILE_MAX 7
ce8f5370
AD		 1059
1060struct radeon_pm_profile {
1061 int dpms_off_ps_idx;
1062 int dpms_on_ps_idx;
1063 int dpms_off_cm_idx;
1064 int dpms_on_cm_idx;
516d0e46
AD		 1065};
1066
21a8122a
AD		 1067enum radeon_int_thermal_type {
1068 THERMAL_TYPE_NONE,
1069 THERMAL_TYPE_RV6XX,
1070 THERMAL_TYPE_RV770,
1071 THERMAL_TYPE_EVERGREEN,
e33df25f 1072 THERMAL_TYPE_SUMO,
4fddba1f 1073 THERMAL_TYPE_NI,
14607d08 1074 THERMAL_TYPE_SI,
51150207 1075 THERMAL_TYPE_CI,
21a8122a
AD		 1076};
1077
56278a8e
AD		 1078struct radeon_voltage {
1079 enum radeon_voltage_type type;
1080 /* gpio voltage */
1081 struct radeon_gpio_rec gpio;
1082 u32 delay; /* delay in usec from voltage drop to sclk change */
1083 bool active_high; /* voltage drop is active when bit is high */
1084 /* VDDC voltage */
1085 u8 vddc_id; /* index into vddc voltage table */
1086 u8 vddci_id; /* index into vddci voltage table */
1087 bool vddci_enabled;
1088 /* r6xx+ sw */
2feea49a
AD		 1089 u16 voltage;
1090 /* evergreen+ vddci */
1091 u16 vddci;
56278a8e
AD		 1092};
1093
d7311171
AD		 1094/* clock mode flags */
1095#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1096
56278a8e
AD		 1097struct radeon_pm_clock_info {
1098 /* memory clock */
1099 u32 mclk;
1100 /* engine clock */
1101 u32 sclk;
1102 /* voltage info */
1103 struct radeon_voltage voltage;
d7311171 1104 /* standardized clock flags */
56278a8e
AD		 1105 u32 flags;
1106};
1107
a48b9b4e 1108/* state flags */
d7311171 1109#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1110
56278a8e 1111struct radeon_power_state {
0ec0e74f 1112 enum radeon_pm_state_type type;
8f3f1c9a 1113 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1114 /* number of valid clock modes in this power state */
1115 int num_clock_modes;
56278a8e 1116 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1117 /* standardized state flags */
1118 u32 flags;
79daedc9
AD		 1119 u32 misc; /* vbios specific flags */
1120 u32 misc2; /* vbios specific flags */
1121 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1122};
1123
27459324
RM		 1124/*
1125 * Some modes are overclocked by very low value, accept them
1126 */
1127#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1128
c93bb85b 1129struct radeon_pm {
c913e23a 1130 struct mutex mutex;
db7fce39
CK		 1131 /* write locked while reprogramming mclk */
1132 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1133 u32 active_crtcs;
1134 int active_crtc_count;
c913e23a 1135 int req_vblank;
839461d3 1136 bool vblank_sync;
c93bb85b
JG		 1137 fixed20_12 max_bandwidth;
1138 fixed20_12 igp_sideport_mclk;
1139 fixed20_12 igp_system_mclk;
1140 fixed20_12 igp_ht_link_clk;
1141 fixed20_12 igp_ht_link_width;
1142 fixed20_12 k8_bandwidth;
1143 fixed20_12 sideport_bandwidth;
1144 fixed20_12 ht_bandwidth;
1145 fixed20_12 core_bandwidth;
1146 fixed20_12 sclk;
f47299c5 1147 fixed20_12 mclk;
c93bb85b 1148 fixed20_12 needed_bandwidth;
0975b162 1149 struct radeon_power_state *power_state;
56278a8e
AD		 1150 /* number of valid power states */
1151 int num_power_states;
a48b9b4e
AD		 1152 int current_power_state_index;
1153 int current_clock_mode_index;
1154 int requested_power_state_index;
1155 int requested_clock_mode_index;
1156 int default_power_state_index;
1157 u32 current_sclk;
1158 u32 current_mclk;
2feea49a
AD		 1159 u16 current_vddc;
1160 u16 current_vddci;
9ace9f7b
AD		 1161 u32 default_sclk;
1162 u32 default_mclk;
2feea49a
AD		 1163 u16 default_vddc;
1164 u16 default_vddci;
29fb52ca 1165 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1166 /* selected pm method */
1167 enum radeon_pm_method pm_method;
1168 /* dynpm power management */
1169 struct delayed_work dynpm_idle_work;
1170 enum radeon_dynpm_state dynpm_state;
1171 enum radeon_dynpm_action dynpm_planned_action;
1172 unsigned long dynpm_action_timeout;
1173 bool dynpm_can_upclock;
1174 bool dynpm_can_downclock;
1175 /* profile-based power management */
1176 enum radeon_pm_profile_type profile;
1177 int profile_index;
1178 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1179 /* internal thermal controller on rv6xx+ */
1180 enum radeon_int_thermal_type int_thermal_type;
1181 struct device *int_hwmon_dev;
c93bb85b
JG		 1182};
1183
a4c9e2ee
AD		 1184int radeon_pm_get_type_index(struct radeon_device *rdev,
1185 enum radeon_pm_state_type ps_type,
1186 int instance);
f2ba57b5
CK		 1187/*
1188 * UVD
1189 */
1190#define RADEON_MAX_UVD_HANDLES 10
1191#define RADEON_UVD_STACK_SIZE (1024*1024)
1192#define RADEON_UVD_HEAP_SIZE (1024*1024)
1193
1194struct radeon_uvd {
1195 struct radeon_bo *vcpu_bo;
1196 void *cpu_addr;
1197 uint64_t gpu_addr;
1198 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1199 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
55b51c88 1200 struct delayed_work idle_work;
f2ba57b5
CK		 1201};
1202
1203int radeon_uvd_init(struct radeon_device *rdev);
1204void radeon_uvd_fini(struct radeon_device *rdev);
1205int radeon_uvd_suspend(struct radeon_device *rdev);
1206int radeon_uvd_resume(struct radeon_device *rdev);
1207int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1208 uint32_t handle, struct radeon_fence **fence);
1209int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1210 uint32_t handle, struct radeon_fence **fence);
1211void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1212void radeon_uvd_free_handles(struct radeon_device *rdev,
1213 struct drm_file *filp);
1214int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1215void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1216int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1217 unsigned vclk, unsigned dclk,
1218 unsigned vco_min, unsigned vco_max,
1219 unsigned fb_factor, unsigned fb_mask,
1220 unsigned pd_min, unsigned pd_max,
1221 unsigned pd_even,
1222 unsigned *optimal_fb_div,
1223 unsigned *optimal_vclk_div,
1224 unsigned *optimal_dclk_div);
1225int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1226 unsigned cg_upll_func_cntl);
771fe6b9 1227
a92553ab 1228struct r600_audio {
a92553ab
RM		 1229 int channels;
1230 int rate;
1231 int bits_per_sample;
1232 u8 status_bits;
1233 u8 category_code;
1234};
1235
771fe6b9
JG		 1236/*
1237 * Benchmarking
1238 */
638dd7db 1239void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1240
1241
ecc0b326
MD		 1242/*
1243 * Testing
1244 */
1245void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1246void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1247 struct radeon_ring *cpA,
1248 struct radeon_ring *cpB);
60a7e396 1249void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1250
1251
771fe6b9
JG		 1252/*
1253 * Debugfs
1254 */
4d8bf9ae
CK		 1255struct radeon_debugfs {
1256 struct drm_info_list *files;
1257 unsigned num_files;
1258};
1259
771fe6b9
JG		 1260int radeon_debugfs_add_files(struct radeon_device *rdev,
1261 struct drm_info_list *files,
1262 unsigned nfiles);
1263int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9
JG		 1264
1265
1266/*
1267 * ASIC specific functions.
1268 */
1269struct radeon_asic {
068a117c 1270 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1271 void (*fini)(struct radeon_device *rdev);
1272 int (*resume)(struct radeon_device *rdev);
1273 int (*suspend)(struct radeon_device *rdev);
28d52043 1274 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1275 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1276 /* ioctl hw specific callback. Some hw might want to perform special
1277 * operation on specific ioctl. For instance on wait idle some hw
1278 * might want to perform and HDP flush through MMIO as it seems that
1279 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1280 * through ring.
1281 */
1282 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1283 /* check if 3D engine is idle */
1284 bool (*gui_idle)(struct radeon_device *rdev);
1285 /* wait for mc_idle */
1286 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1287 /* get the reference clock */
1288 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1289 /* get the gpu clock counter */
1290 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1291 /* gart */
c5b3b850
AD		 1292 struct {
1293 void (*tlb_flush)(struct radeon_device *rdev);
1294 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1295 } gart;
05b07147
CK		 1296 struct {
1297 int (*init)(struct radeon_device *rdev);
1298 void (*fini)(struct radeon_device *rdev);
2a6f1abb
CK		 1299
1300 u32 pt_ring_index;
43f1214a
AD		 1301 void (*set_page)(struct radeon_device *rdev,
1302 struct radeon_ib *ib,
1303 uint64_t pe,
dce34bfd
CK		 1304 uint64_t addr, unsigned count,
1305 uint32_t incr, uint32_t flags);
05b07147 1306 } vm;
54e88e06 1307 /* ring specific callbacks */
4c87bc26
CK		 1308 struct {
1309 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
721604a1 1310 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
4c87bc26 1311 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
e32eb50d 1312 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
4c87bc26 1313 struct radeon_semaphore *semaphore, bool emit_wait);
eb0c19c5 1314 int (*cs_parse)(struct radeon_cs_parser *p);
f712812e
AD		 1315 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1316 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1317 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
312c4a8c 1318 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
498522b4 1319 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
f93bdefe
AD		 1320
1321 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1322 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1323 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
4c87bc26 1324 } ring[RADEON_NUM_RINGS];
54e88e06 1325 /* irqs */
b35ea4ab
AD		 1326 struct {
1327 int (*set)(struct radeon_device *rdev);
1328 int (*process)(struct radeon_device *rdev);
1329 } irq;
54e88e06 1330 /* displays */
c79a49ca
AD		 1331 struct {
1332 /* display watermarks */
1333 void (*bandwidth_update)(struct radeon_device *rdev);
1334 /* get frame count */
1335 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1336 /* wait for vblank */
1337 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1338 /* set backlight level */
1339 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1340 /* get backlight level */
1341 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1342 /* audio callbacks */
1343 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1344 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1345 } display;
54e88e06 1346 /* copy functions for bo handling */
27cd7769
AD		 1347 struct {
1348 int (*blit)(struct radeon_device *rdev,
1349 uint64_t src_offset,
1350 uint64_t dst_offset,
1351 unsigned num_gpu_pages,
876dc9f3 1352 struct radeon_fence **fence);
27cd7769
AD		 1353 u32 blit_ring_index;
1354 int (*dma)(struct radeon_device *rdev,
1355 uint64_t src_offset,
1356 uint64_t dst_offset,
1357 unsigned num_gpu_pages,
876dc9f3 1358 struct radeon_fence **fence);
27cd7769
AD		 1359 u32 dma_ring_index;
1360 /* method used for bo copy */
1361 int (*copy)(struct radeon_device *rdev,
1362 uint64_t src_offset,
1363 uint64_t dst_offset,
1364 unsigned num_gpu_pages,
876dc9f3 1365 struct radeon_fence **fence);
27cd7769
AD		 1366 /* ring used for bo copies */
1367 u32 copy_ring_index;
1368 } copy;
54e88e06 1369 /* surfaces */
9e6f3d02
AD		 1370 struct {
1371 int (*set_reg)(struct radeon_device *rdev, int reg,
1372 uint32_t tiling_flags, uint32_t pitch,
1373 uint32_t offset, uint32_t obj_size);
1374 void (*clear_reg)(struct radeon_device *rdev, int reg);
1375 } surface;
54e88e06 1376 /* hotplug detect */
901ea57d
AD		 1377 struct {
1378 void (*init)(struct radeon_device *rdev);
1379 void (*fini)(struct radeon_device *rdev);
1380 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1381 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1382 } hpd;
ce8f5370 1383 /* power management */
a02fa397
AD		 1384 struct {
1385 void (*misc)(struct radeon_device *rdev);
1386 void (*prepare)(struct radeon_device *rdev);
1387 void (*finish)(struct radeon_device *rdev);
1388 void (*init_profile)(struct radeon_device *rdev);
1389 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1390 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1391 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1392 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1393 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1394 int (*get_pcie_lanes)(struct radeon_device *rdev);
1395 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1396 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1397 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
a02fa397 1398 } pm;
6f34be50 1399 /* pageflipping */
0f9e006c
AD		 1400 struct {
1401 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1402 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1403 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1404 } pflip;
771fe6b9
JG		 1405};
1406
21f9a437
JG		 1407/*
1408 * Asic structures
1409 */
551ebd83 1410struct r100_asic {
225758d8
JG		 1411 const unsigned *reg_safe_bm;
1412 unsigned reg_safe_bm_size;
1413 u32 hdp_cntl;
551ebd83
DA		 1414};
1415
21f9a437 1416struct r300_asic {
225758d8
JG		 1417 const unsigned *reg_safe_bm;
1418 unsigned reg_safe_bm_size;
1419 u32 resync_scratch;
1420 u32 hdp_cntl;
21f9a437
JG		 1421};
1422
1423struct r600_asic {
225758d8
JG		 1424 unsigned max_pipes;
1425 unsigned max_tile_pipes;
1426 unsigned max_simds;
1427 unsigned max_backends;
1428 unsigned max_gprs;
1429 unsigned max_threads;
1430 unsigned max_stack_entries;
1431 unsigned max_hw_contexts;
1432 unsigned max_gs_threads;
1433 unsigned sx_max_export_size;
1434 unsigned sx_max_export_pos_size;
1435 unsigned sx_max_export_smx_size;
1436 unsigned sq_num_cf_insts;
1437 unsigned tiling_nbanks;
1438 unsigned tiling_npipes;
1439 unsigned tiling_group_size;
e7aeeba6 1440 unsigned tile_config;
e55b9422 1441 unsigned backend_map;
21f9a437
JG		 1442};
1443
1444struct rv770_asic {
225758d8
JG		 1445 unsigned max_pipes;
1446 unsigned max_tile_pipes;
1447 unsigned max_simds;
1448 unsigned max_backends;
1449 unsigned max_gprs;
1450 unsigned max_threads;
1451 unsigned max_stack_entries;
1452 unsigned max_hw_contexts;
1453 unsigned max_gs_threads;
1454 unsigned sx_max_export_size;
1455 unsigned sx_max_export_pos_size;
1456 unsigned sx_max_export_smx_size;
1457 unsigned sq_num_cf_insts;
1458 unsigned sx_num_of_sets;
1459 unsigned sc_prim_fifo_size;
1460 unsigned sc_hiz_tile_fifo_size;
1461 unsigned sc_earlyz_tile_fifo_fize;
1462 unsigned tiling_nbanks;
1463 unsigned tiling_npipes;
1464 unsigned tiling_group_size;
e7aeeba6 1465 unsigned tile_config;
e55b9422 1466 unsigned backend_map;
21f9a437
JG		 1467};
1468
32fcdbf4
AD		 1469struct evergreen_asic {
1470 unsigned num_ses;
1471 unsigned max_pipes;
1472 unsigned max_tile_pipes;
1473 unsigned max_simds;
1474 unsigned max_backends;
1475 unsigned max_gprs;
1476 unsigned max_threads;
1477 unsigned max_stack_entries;
1478 unsigned max_hw_contexts;
1479 unsigned max_gs_threads;
1480 unsigned sx_max_export_size;
1481 unsigned sx_max_export_pos_size;
1482 unsigned sx_max_export_smx_size;
1483 unsigned sq_num_cf_insts;
1484 unsigned sx_num_of_sets;
1485 unsigned sc_prim_fifo_size;
1486 unsigned sc_hiz_tile_fifo_size;
1487 unsigned sc_earlyz_tile_fifo_size;
1488 unsigned tiling_nbanks;
1489 unsigned tiling_npipes;
1490 unsigned tiling_group_size;
e7aeeba6 1491 unsigned tile_config;
e55b9422 1492 unsigned backend_map;
32fcdbf4
AD		 1493};
1494
fecf1d07
AD		 1495struct cayman_asic {
1496 unsigned max_shader_engines;
1497 unsigned max_pipes_per_simd;
1498 unsigned max_tile_pipes;
1499 unsigned max_simds_per_se;
1500 unsigned max_backends_per_se;
1501 unsigned max_texture_channel_caches;
1502 unsigned max_gprs;
1503 unsigned max_threads;
1504 unsigned max_gs_threads;
1505 unsigned max_stack_entries;
1506 unsigned sx_num_of_sets;
1507 unsigned sx_max_export_size;
1508 unsigned sx_max_export_pos_size;
1509 unsigned sx_max_export_smx_size;
1510 unsigned max_hw_contexts;
1511 unsigned sq_num_cf_insts;
1512 unsigned sc_prim_fifo_size;
1513 unsigned sc_hiz_tile_fifo_size;
1514 unsigned sc_earlyz_tile_fifo_size;
1515
1516 unsigned num_shader_engines;
1517 unsigned num_shader_pipes_per_simd;
1518 unsigned num_tile_pipes;
1519 unsigned num_simds_per_se;
1520 unsigned num_backends_per_se;
1521 unsigned backend_disable_mask_per_asic;
1522 unsigned backend_map;
1523 unsigned num_texture_channel_caches;
1524 unsigned mem_max_burst_length_bytes;
1525 unsigned mem_row_size_in_kb;
1526 unsigned shader_engine_tile_size;
1527 unsigned num_gpus;
1528 unsigned multi_gpu_tile_size;
1529
1530 unsigned tile_config;
fecf1d07
AD		 1531};
1532
0a96d72b
AD		 1533struct si_asic {
1534 unsigned max_shader_engines;
0a96d72b 1535 unsigned max_tile_pipes;
1a8ca750
AD		 1536 unsigned max_cu_per_sh;
1537 unsigned max_sh_per_se;
0a96d72b
AD		 1538 unsigned max_backends_per_se;
1539 unsigned max_texture_channel_caches;
1540 unsigned max_gprs;
1541 unsigned max_gs_threads;
1542 unsigned max_hw_contexts;
1543 unsigned sc_prim_fifo_size_frontend;
1544 unsigned sc_prim_fifo_size_backend;
1545 unsigned sc_hiz_tile_fifo_size;
1546 unsigned sc_earlyz_tile_fifo_size;
1547
0a96d72b
AD		 1548 unsigned num_tile_pipes;
1549 unsigned num_backends_per_se;
1550 unsigned backend_disable_mask_per_asic;
1551 unsigned backend_map;
1552 unsigned num_texture_channel_caches;
1553 unsigned mem_max_burst_length_bytes;
1554 unsigned mem_row_size_in_kb;
1555 unsigned shader_engine_tile_size;
1556 unsigned num_gpus;
1557 unsigned multi_gpu_tile_size;
1558
1559 unsigned tile_config;
64d7b8be 1560 uint32_t tile_mode_array[32];
0a96d72b
AD		 1561};
1562
8cc1a532
AD		 1563struct cik_asic {
1564 unsigned max_shader_engines;
1565 unsigned max_tile_pipes;
1566 unsigned max_cu_per_sh;
1567 unsigned max_sh_per_se;
1568 unsigned max_backends_per_se;
1569 unsigned max_texture_channel_caches;
1570 unsigned max_gprs;
1571 unsigned max_gs_threads;
1572 unsigned max_hw_contexts;
1573 unsigned sc_prim_fifo_size_frontend;
1574 unsigned sc_prim_fifo_size_backend;
1575 unsigned sc_hiz_tile_fifo_size;
1576 unsigned sc_earlyz_tile_fifo_size;
1577
1578 unsigned num_tile_pipes;
1579 unsigned num_backends_per_se;
1580 unsigned backend_disable_mask_per_asic;
1581 unsigned backend_map;
1582 unsigned num_texture_channel_caches;
1583 unsigned mem_max_burst_length_bytes;
1584 unsigned mem_row_size_in_kb;
1585 unsigned shader_engine_tile_size;
1586 unsigned num_gpus;
1587 unsigned multi_gpu_tile_size;
1588
1589 unsigned tile_config;
39aee490 1590 uint32_t tile_mode_array[32];
8cc1a532
AD		 1591};
1592
068a117c
JG		 1593union radeon_asic_config {
1594 struct r300_asic r300;
551ebd83 1595 struct r100_asic r100;
3ce0a23d
JG		 1596 struct r600_asic r600;
1597 struct rv770_asic rv770;
32fcdbf4 1598 struct evergreen_asic evergreen;
fecf1d07 1599 struct cayman_asic cayman;
0a96d72b 1600 struct si_asic si;
8cc1a532 1601 struct cik_asic cik;
068a117c
JG		 1602};
1603
0a10c851
DV		 1604/*
1605 * asic initizalization from radeon_asic.c
1606 */
1607void radeon_agp_disable(struct radeon_device *rdev);
1608int radeon_asic_init(struct radeon_device *rdev);
1609
771fe6b9
JG		 1610
1611/*
1612 * IOCTL.
1613 */
1614int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1615 struct drm_file *filp);
1616int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1617 struct drm_file *filp);
1618int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1619 struct drm_file *file_priv);
1620int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1621 struct drm_file *file_priv);
1622int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1623 struct drm_file *file_priv);
1624int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1625 struct drm_file *file_priv);
1626int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1627 struct drm_file *filp);
1628int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1629 struct drm_file *filp);
1630int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1631 struct drm_file *filp);
1632int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1633 struct drm_file *filp);
721604a1
JG		 1634int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1635 struct drm_file *filp);
771fe6b9 1636int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1637int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1638 struct drm_file *filp);
1639int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1640 struct drm_file *filp);
771fe6b9 1641
16cdf04d
AD		 1642/* VRAM scratch page for HDP bug, default vram page */
1643struct r600_vram_scratch {
87cbf8f2
AD		 1644 struct radeon_bo *robj;
1645 volatile uint32_t *ptr;
16cdf04d 1646 u64 gpu_addr;
87cbf8f2 1647};
771fe6b9 1648
fd64ca8a
LT		 1649/*
1650 * ACPI
1651 */
1652struct radeon_atif_notification_cfg {
1653 bool enabled;
1654 int command_code;
1655};
1656
1657struct radeon_atif_notifications {
1658 bool display_switch;
1659 bool expansion_mode_change;
1660 bool thermal_state;
1661 bool forced_power_state;
1662 bool system_power_state;
1663 bool display_conf_change;
1664 bool px_gfx_switch;
1665 bool brightness_change;
1666 bool dgpu_display_event;
1667};
1668
1669struct radeon_atif_functions {
1670 bool system_params;
1671 bool sbios_requests;
1672 bool select_active_disp;
1673 bool lid_state;
1674 bool get_tv_standard;
1675 bool set_tv_standard;
1676 bool get_panel_expansion_mode;
1677 bool set_panel_expansion_mode;
1678 bool temperature_change;
1679 bool graphics_device_types;
1680};
1681
1682struct radeon_atif {
1683 struct radeon_atif_notifications notifications;
1684 struct radeon_atif_functions functions;
1685 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 1686 struct radeon_encoder *encoder_for_bl;
fd64ca8a 1687};
7a1619b9 1688
e3a15920
AD		 1689struct radeon_atcs_functions {
1690 bool get_ext_state;
1691 bool pcie_perf_req;
1692 bool pcie_dev_rdy;
1693 bool pcie_bus_width;
1694};
1695
1696struct radeon_atcs {
1697 struct radeon_atcs_functions functions;
1698};
1699
771fe6b9
JG		 1700/*
1701 * Core structure, functions and helpers.
1702 */
1703typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1704typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1705
1706struct radeon_device {
9f022ddf 1707 struct device *dev;
771fe6b9
JG		 1708 struct drm_device *ddev;
1709 struct pci_dev *pdev;
dee53e7f 1710 struct rw_semaphore exclusive_lock;
771fe6b9 1711 /* ASIC */
068a117c 1712 union radeon_asic_config config;
771fe6b9
JG		 1713 enum radeon_family family;
1714 unsigned long flags;
1715 int usec_timeout;
1716 enum radeon_pll_errata pll_errata;
1717 int num_gb_pipes;
f779b3e5 1718 int num_z_pipes;
771fe6b9
JG		 1719 int disp_priority;
1720 /* BIOS */
1721 uint8_t *bios;
1722 bool is_atom_bios;
1723 uint16_t bios_header_start;
4c788679 1724 struct radeon_bo *stollen_vga_memory;
771fe6b9 1725 /* Register mmio */
4c9bc75c
DA		 1726 resource_size_t rmmio_base;
1727 resource_size_t rmmio_size;
2c385151
DV		 1728 /* protects concurrent MM_INDEX/DATA based register access */
1729 spinlock_t mmio_idx_lock;
a0533fbf 1730 void __iomem *rmmio;
771fe6b9
JG		 1731 radeon_rreg_t mc_rreg;
1732 radeon_wreg_t mc_wreg;
1733 radeon_rreg_t pll_rreg;
1734 radeon_wreg_t pll_wreg;
de1b2898 1735 uint32_t pcie_reg_mask;
771fe6b9
JG		 1736 radeon_rreg_t pciep_rreg;
1737 radeon_wreg_t pciep_wreg;
351a52a2
AD		 1738 /* io port */
1739 void __iomem *rio_mem;
1740 resource_size_t rio_mem_size;
771fe6b9
JG		 1741 struct radeon_clock clock;
1742 struct radeon_mc mc;
1743 struct radeon_gart gart;
1744 struct radeon_mode_info mode_info;
1745 struct radeon_scratch scratch;
75efdee1 1746 struct radeon_doorbell doorbell;
771fe6b9 1747 struct radeon_mman mman;
7465280c 1748 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 1749 wait_queue_head_t fence_queue;
d6999bc7 1750 struct mutex ring_lock;
e32eb50d 1751 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 1752 bool ib_pool_ready;
1753 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 1754 struct radeon_irq irq;
1755 struct radeon_asic *asic;
1756 struct radeon_gem gem;
c93bb85b 1757 struct radeon_pm pm;
f2ba57b5 1758 struct radeon_uvd uvd;
f657c2a7 1759 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 1760 struct radeon_wb wb;
3ce0a23d 1761 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 1762 bool shutdown;
1763 bool suspend;
ad49f501 1764 bool need_dma32;
733289c2 1765 bool accel_working;
a0a53aa8 1766 bool fastfb_working; /* IGP feature*/
e024e110 1767 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 1768 const struct firmware *me_fw; /* all family ME firmware */
1769 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 1770 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 1771 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 1772 const struct firmware *ce_fw; /* SI CE firmware */
f2ba57b5 1773 const struct firmware *uvd_fw; /* UVD firmware */
02c81327 1774 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 1775 const struct firmware *sdma_fw; /* CIK SDMA firmware */
3ce0a23d 1776 struct r600_blit r600_blit;
16cdf04d 1777 struct r600_vram_scratch vram_scratch;
3e5cb98d 1778 int msi_enabled; /* msi enabled */
d8f60cfc 1779 struct r600_ih ih; /* r6/700 interrupt ring */
347e7592 1780 struct si_rlc rlc;
963e81f9 1781 struct radeon_mec mec;
d4877cf2 1782 struct work_struct hotplug_work;
f122c610 1783 struct work_struct audio_work;
8f61b34c 1784 struct work_struct reset_work;
18917b60 1785 int num_crtc; /* number of crtcs */
40bacf16 1786 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
3299de95 1787 bool audio_enabled;
948bee3f 1788 bool has_uvd;
3299de95 1789 struct r600_audio audio_status; /* audio stuff */
ce8f5370 1790 struct notifier_block acpi_nb;
9eba4a93 1791 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 1792 struct drm_file *hyperz_filp;
9eba4a93 1793 struct drm_file *cmask_filp;
f376b94f
AD		 1794 /* i2c buses */
1795 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 1796 /* debugfs */
1797 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1798 unsigned debugfs_count;
721604a1
JG		 1799 /* virtual memory */
1800 struct radeon_vm_manager vm_manager;
6759a0a7 1801 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 1802 /* ACPI interface */
1803 struct radeon_atif atif;
e3a15920 1804 struct radeon_atcs atcs;
771fe6b9
JG		 1805};
1806
1807int radeon_device_init(struct radeon_device *rdev,
1808 struct drm_device *ddev,
1809 struct pci_dev *pdev,
1810 uint32_t flags);
1811void radeon_device_fini(struct radeon_device *rdev);
1812int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1813
2ef9bdfe
DV		 1814uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
1815 bool always_indirect);
1816void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
1817 bool always_indirect);
6fcbef7a
AK		 1818u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1819void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 1820
75efdee1
AD		 1821u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
1822void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
1823
4c788679
JG		 1824/*
1825 * Cast helper
1826 */
1827#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 1828
1829/*
1830 * Registers read & write functions.
1831 */
a0533fbf
BH		 1832#define RREG8(reg) readb((rdev->rmmio) + (reg))
1833#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1834#define RREG16(reg) readw((rdev->rmmio) + (reg))
1835#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 1836#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
1837#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
1838#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
1839#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
1840#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 1841#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1842#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1843#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1844#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1845#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1846#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 1847#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1848#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 1849#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
1850#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 1851#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
1852#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 1853#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
1854#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
771fe6b9
JG		 1855#define WREG32_P(reg, val, mask) \
1856 do { \
1857 uint32_t tmp_ = RREG32(reg); \
1858 tmp_ &= (mask); \
1859 tmp_ |= ((val) & ~(mask)); \
1860 WREG32(reg, tmp_); \
1861 } while (0)
d5169fc4
RM		 1862#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1863#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
771fe6b9
JG		 1864#define WREG32_PLL_P(reg, val, mask) \
1865 do { \
1866 uint32_t tmp_ = RREG32_PLL(reg); \
1867 tmp_ &= (mask); \
1868 tmp_ |= ((val) & ~(mask)); \
1869 WREG32_PLL(reg, tmp_); \
1870 } while (0)
2ef9bdfe 1871#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 1872#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1873#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 1874
75efdee1
AD		 1875#define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
1876#define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
1877
de1b2898
DA		 1878/*
1879 * Indirect registers accessor
1880 */
1881static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1882{
1883 uint32_t r;
1884
1885 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1886 r = RREG32(RADEON_PCIE_DATA);
1887 return r;
1888}
1889
1890static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1891{
1892 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1893 WREG32(RADEON_PCIE_DATA, (v));
1894}
1895
1d5d0c34
AD		 1896static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
1897{
1898 u32 r;
1899
1900 WREG32(TN_SMC_IND_INDEX_0, (reg));
1901 r = RREG32(TN_SMC_IND_DATA_0);
1902 return r;
1903}
1904
1905static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1906{
1907 WREG32(TN_SMC_IND_INDEX_0, (reg));
1908 WREG32(TN_SMC_IND_DATA_0, (v));
1909}
1910
ff82bbc4
AD		 1911static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
1912{
1913 u32 r;
1914
1915 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
1916 r = RREG32(R600_RCU_DATA);
1917 return r;
1918}
1919
1920static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1921{
1922 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
1923 WREG32(R600_RCU_DATA, (v));
1924}
1925
771fe6b9
JG		 1926void r100_pll_errata_after_index(struct radeon_device *rdev);
1927
1928
1929/*
1930 * ASICs helpers.
1931 */
b995e433
DA		 1932#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1933 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 1934#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1935 (rdev->family == CHIP_RV200) || \
1936 (rdev->family == CHIP_RS100) || \
1937 (rdev->family == CHIP_RS200) || \
1938 (rdev->family == CHIP_RV250) || \
1939 (rdev->family == CHIP_RV280) || \
1940 (rdev->family == CHIP_RS300))
1941#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1942 (rdev->family == CHIP_RV350) || \
1943 (rdev->family == CHIP_R350) || \
1944 (rdev->family == CHIP_RV380) || \
1945 (rdev->family == CHIP_R420) || \
1946 (rdev->family == CHIP_R423) || \
1947 (rdev->family == CHIP_RV410) || \
1948 (rdev->family == CHIP_RS400) || \
1949 (rdev->family == CHIP_RS480))
3313e3d4
AD		 1950#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1951 (rdev->ddev->pdev->device == 0x9443) || \
1952 (rdev->ddev->pdev->device == 0x944B) || \
1953 (rdev->ddev->pdev->device == 0x9506) || \
1954 (rdev->ddev->pdev->device == 0x9509) || \
1955 (rdev->ddev->pdev->device == 0x950F) || \
1956 (rdev->ddev->pdev->device == 0x689C) || \
1957 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 1958#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 1959#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1960 (rdev->family == CHIP_RS690) || \
1961 (rdev->family == CHIP_RS740) || \
1962 (rdev->family >= CHIP_R600))
771fe6b9
JG		 1963#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1964#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 1965#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 1966#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1967 (rdev->flags & RADEON_IS_IGP))
1fe18305 1968#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 1969#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1970#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1971 (rdev->flags & RADEON_IS_IGP))
624d3524 1972#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 1973#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 1974#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9
JG		 1975
1976/*
1977 * BIOS helpers.
1978 */
1979#define RBIOS8(i) (rdev->bios[i])
1980#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1981#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1982
1983int radeon_combios_init(struct radeon_device *rdev);
1984void radeon_combios_fini(struct radeon_device *rdev);
1985int radeon_atombios_init(struct radeon_device *rdev);
1986void radeon_atombios_fini(struct radeon_device *rdev);
1987
1988
1989/*
1990 * RING helpers.
1991 */
ce580fab 1992#if DRM_DEBUG_CODE == 0
e32eb50d 1993static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 1994{
e32eb50d
CK		 1995 ring->ring[ring->wptr++] = v;
1996 ring->wptr &= ring->ptr_mask;
1997 ring->count_dw--;
1998 ring->ring_free_dw--;
771fe6b9 1999}
ce580fab
AK		 2000#else
2001/* With debugging this is just too big to inline */
e32eb50d 2002void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2003#endif
771fe6b9
JG		 2004
2005/*
2006 * ASICs macro.
2007 */
068a117c 2008#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2009#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2010#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2011#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
eb0c19c5 2012#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
28d52043 2013#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2014#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2015#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2016#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2017#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2018#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2019#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
f712812e
AD		 2020#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2021#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2022#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
4c87bc26 2023#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
721604a1 2024#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
312c4a8c 2025#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
498522b4 2026#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
f93bdefe
AD		 2027#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2028#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2029#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
b35ea4ab
AD		 2030#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2031#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2032#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2033#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2034#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2035#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2036#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
4c87bc26
CK		 2037#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2038#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2039#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2040#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2041#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2042#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2043#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2044#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2045#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2046#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2047#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2048#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2049#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2050#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2051#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2052#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
9e6f3d02
AD		 2053#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2054#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2055#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2056#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2057#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2058#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2059#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2060#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2061#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2062#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2063#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2064#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2065#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2066#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2067#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2068#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2069#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2070#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2071#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2072#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
771fe6b9 2073
6cf8a3f5 2074/* Common functions */
700a0cc0 2075/* AGP */
90aca4d2 2076extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2077extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2078extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2079extern int radeon_modeset_init(struct radeon_device *rdev);
2080extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2081extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2082extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2083extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2084extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2085extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2086extern void radeon_wb_fini(struct radeon_device *rdev);
2087extern int radeon_wb_init(struct radeon_device *rdev);
2088extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2089extern void radeon_surface_init(struct radeon_device *rdev);
2090extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2091extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2092extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2093extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2094extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2095extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2096extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 2097extern int radeon_resume_kms(struct drm_device *dev);
2098extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
53595338 2099extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2100extern void radeon_program_register_sequence(struct radeon_device *rdev,
2101 const u32 *registers,
2102 const u32 array_size);
6cf8a3f5 2103
721604a1
JG		 2104/*
2105 * vm
2106 */
2107int radeon_vm_manager_init(struct radeon_device *rdev);
2108void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2109void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2110void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2111int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2112void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2113struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2114 struct radeon_vm *vm, int ring);
2115void radeon_vm_fence(struct radeon_device *rdev,
2116 struct radeon_vm *vm,
2117 struct radeon_fence *fence);
dce34bfd 2118uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
721604a1
JG		 2119int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2120 struct radeon_vm *vm,
2121 struct radeon_bo *bo,
2122 struct ttm_mem_reg *mem);
2123void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2124 struct radeon_bo *bo);
421ca7ab
CK		 2125struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2126 struct radeon_bo *bo);
e971bd5e
CK		 2127struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2128 struct radeon_vm *vm,
2129 struct radeon_bo *bo);
2130int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2131 struct radeon_bo_va *bo_va,
2132 uint64_t offset,
2133 uint32_t flags);
721604a1 2134int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2135 struct radeon_bo_va *bo_va);
721604a1 2136
f122c610
AD		 2137/* audio */
2138void r600_audio_update_hdmi(struct work_struct *work);
721604a1 2139
16cdf04d
AD		 2140/*
2141 * R600 vram scratch functions
2142 */
2143int r600_vram_scratch_init(struct radeon_device *rdev);
2144void r600_vram_scratch_fini(struct radeon_device *rdev);
2145
285484e2
JG		 2146/*
2147 * r600 cs checking helper
2148 */
2149unsigned r600_mip_minify(unsigned size, unsigned level);
2150bool r600_fmt_is_valid_color(u32 format);
2151bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2152int r600_fmt_get_blocksize(u32 format);
2153int r600_fmt_get_nblocksx(u32 format, u32 w);
2154int r600_fmt_get_nblocksy(u32 format, u32 h);
2155
3574dda4
DV		 2156/*
2157 * r600 functions used by radeon_encoder.c
2158 */
1b688d08
RM		 2159struct radeon_hdmi_acr {
2160 u32 clock;
2161
2162 int n_32khz;
2163 int cts_32khz;
2164
2165 int n_44_1khz;
2166 int cts_44_1khz;
2167
2168 int n_48khz;
2169 int cts_48khz;
2170
2171};
2172
e55d3e6c
RM		 2173extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2174
416a2bd2
AD		 2175extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2176 u32 tiling_pipe_num,
2177 u32 max_rb_num,
2178 u32 total_max_rb_num,
2179 u32 enabled_rb_mask);
fe251e2f 2180
e55d3e6c
RM		 2181/*
2182 * evergreen functions used by radeon_encoder.c
2183 */
2184
0af62b01 2185extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2186extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2187
c4917074
AD		 2188/* radeon_acpi.c */
2189#if defined(CONFIG_ACPI)
2190extern int radeon_acpi_init(struct radeon_device *rdev);
2191extern void radeon_acpi_fini(struct radeon_device *rdev);
2192#else
2193static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2194static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2195#endif
d7a2952f 2196
c38f34b5
IH		 2197int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2198 struct radeon_cs_packet *pkt,
2199 unsigned idx);
9ffb7a6d 2200bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2201void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2202 struct radeon_cs_packet *pkt);
e9716993
IH		 2203int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2204 struct radeon_cs_reloc **cs_reloc,
2205 int nomm);
40592a17
IH		 2206int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2207 uint32_t *vline_start_end,
2208 uint32_t *vline_status);
c38f34b5 2209
4c788679
JG		 2210#include "radeon_object.h"
2211
771fe6b9 2212#endif
Linux 6.x block layer and io_uring tree(s)