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drm/radeon: drop drivers copy of the rptr
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
363eb0b4 102extern int radeon_hard_reset;
771fe6b9
JG		 103
104/*
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 * symbol;
107 */
bb635567
JG		 108#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 110/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 111#define RADEON_IB_POOL_SIZE 16
112#define RADEON_DEBUGFS_MAX_COMPONENTS 32
113#define RADEONFB_CONN_LIMIT 4
114#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 115
bb635567
JG		 116/* fence seq are set to this number when signaled */
117#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 118
119/* internal ring indices */
120/* r1xx+ has gfx CP ring */
d93f7937 121#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 122
123/* cayman has 2 compute CP rings */
d93f7937
CK		 124#define CAYMAN_RING_TYPE_CP1_INDEX 1
125#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 126
4d75658b
AD		 127/* R600+ has an async dma ring */
128#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 129/* cayman add a second async dma ring */
130#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 131
f2ba57b5 132/* R600+ */
d93f7937
CK		 133#define R600_RING_TYPE_UVD_INDEX 5
134
135/* TN+ */
136#define TN_RING_TYPE_VCE1_INDEX 6
137#define TN_RING_TYPE_VCE2_INDEX 7
138
139/* max number of rings */
140#define RADEON_NUM_RINGS 8
f2ba57b5 141
1c61eae4
CK		 142/* number of hw syncs before falling back on blocking */
143#define RADEON_NUM_SYNCS 4
144
721604a1 145/* hardcode those limit for now */
ca19f21e 146#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 147#define RADEON_VA_RESERVED_SIZE (8 << 20)
148#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 149
1a0041b8
AD		 150/* hard reset data */
151#define RADEON_ASIC_RESET_DATA 0x39d5e86b
152
ec46c76d
AD		 153/* reset flags */
154#define RADEON_RESET_GFX (1 << 0)
155#define RADEON_RESET_COMPUTE (1 << 1)
156#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 157#define RADEON_RESET_CP (1 << 3)
158#define RADEON_RESET_GRBM (1 << 4)
159#define RADEON_RESET_DMA1 (1 << 5)
160#define RADEON_RESET_RLC (1 << 6)
161#define RADEON_RESET_SEM (1 << 7)
162#define RADEON_RESET_IH (1 << 8)
163#define RADEON_RESET_VMC (1 << 9)
164#define RADEON_RESET_MC (1 << 10)
165#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 166
22c775ce
AD		 167/* CG block flags */
168#define RADEON_CG_BLOCK_GFX (1 << 0)
169#define RADEON_CG_BLOCK_MC (1 << 1)
170#define RADEON_CG_BLOCK_SDMA (1 << 2)
171#define RADEON_CG_BLOCK_UVD (1 << 3)
172#define RADEON_CG_BLOCK_VCE (1 << 4)
173#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 174#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 175
64d8a728
AD		 176/* CG flags */
177#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
178#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
179#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
180#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
181#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
182#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
183#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
184#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
185#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
186#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
187#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
188#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
189#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
190#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
191#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
192#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
193#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
194
195/* PG flags */
2b19d17f 196#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 197#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
198#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
199#define RADEON_PG_SUPPORT_UVD (1 << 3)
200#define RADEON_PG_SUPPORT_VCE (1 << 4)
201#define RADEON_PG_SUPPORT_CP (1 << 5)
202#define RADEON_PG_SUPPORT_GDS (1 << 6)
203#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
204#define RADEON_PG_SUPPORT_SDMA (1 << 8)
205#define RADEON_PG_SUPPORT_ACP (1 << 9)
206#define RADEON_PG_SUPPORT_SAMU (1 << 10)
207
9e05fa1d
AD		 208/* max cursor sizes (in pixels) */
209#define CURSOR_WIDTH 64
210#define CURSOR_HEIGHT 64
211
212#define CIK_CURSOR_WIDTH 128
213#define CIK_CURSOR_HEIGHT 128
214
771fe6b9
JG		 215/*
216 * Errata workarounds.
217 */
218enum radeon_pll_errata {
219 CHIP_ERRATA_R300_CG = 0x00000001,
220 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
221 CHIP_ERRATA_PLL_DELAY = 0x00000004
222};
223
224
225struct radeon_device;
226
227
228/*
229 * BIOS.
230 */
231bool radeon_get_bios(struct radeon_device *rdev);
232
233/*
3ce0a23d 234 * Dummy page
771fe6b9 235 */
3ce0a23d
JG		 236struct radeon_dummy_page {
237 struct page *page;
238 dma_addr_t addr;
239};
240int radeon_dummy_page_init(struct radeon_device *rdev);
241void radeon_dummy_page_fini(struct radeon_device *rdev);
242
771fe6b9 243
3ce0a23d
JG		 244/*
245 * Clocks
246 */
771fe6b9
JG		 247struct radeon_clock {
248 struct radeon_pll p1pll;
249 struct radeon_pll p2pll;
bcc1c2a1 250 struct radeon_pll dcpll;
771fe6b9
JG		 251 struct radeon_pll spll;
252 struct radeon_pll mpll;
253 /* 10 Khz units */
254 uint32_t default_mclk;
255 uint32_t default_sclk;
bcc1c2a1 256 uint32_t default_dispclk;
4489cd62 257 uint32_t current_dispclk;
bcc1c2a1 258 uint32_t dp_extclk;
b20f9bef 259 uint32_t max_pixel_clock;
771fe6b9
JG		 260};
261
7433874e
RM		 262/*
263 * Power management
264 */
265int radeon_pm_init(struct radeon_device *rdev);
914a8987 266int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 267void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 268void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 269void radeon_pm_suspend(struct radeon_device *rdev);
270void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 271void radeon_combios_get_power_modes(struct radeon_device *rdev);
272void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 273int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
274 u8 clock_type,
275 u32 clock,
276 bool strobe_mode,
277 struct atom_clock_dividers *dividers);
eaa778af
AD		 278int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
279 u32 clock,
280 bool strobe_mode,
281 struct atom_mpll_param *mpll_param);
8a83ec5e 282void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 283int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
284 u16 voltage_level, u8 voltage_type,
285 u32 *gpio_value, u32 *gpio_mask);
286void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
287 u32 eng_clock, u32 mem_clock);
288int radeon_atom_get_voltage_step(struct radeon_device *rdev,
289 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 290int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
291 u16 voltage_id, u16 *voltage);
beb79f40
AD		 292int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
293 u16 *voltage,
294 u16 leakage_idx);
cc8dbbb4
AD		 295int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
296 u16 *leakage_id);
297int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
298 u16 *vddc, u16 *vddci,
299 u16 virtual_voltage_id,
300 u16 vbios_voltage_id);
ae5b0abb
AD		 301int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
302 u8 voltage_type,
303 u16 nominal_voltage,
304 u16 *true_voltage);
305int radeon_atom_get_min_voltage(struct radeon_device *rdev,
306 u8 voltage_type, u16 *min_voltage);
307int radeon_atom_get_max_voltage(struct radeon_device *rdev,
308 u8 voltage_type, u16 *max_voltage);
309int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 310 u8 voltage_type, u8 voltage_mode,
ae5b0abb 311 struct atom_voltage_table *voltage_table);
58653abd
AD		 312bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
313 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 314void radeon_atom_update_memory_dll(struct radeon_device *rdev,
315 u32 mem_clock);
316void radeon_atom_set_ac_timing(struct radeon_device *rdev,
317 u32 mem_clock);
318int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
319 u8 module_index,
320 struct atom_mc_reg_table *reg_table);
321int radeon_atom_get_memory_info(struct radeon_device *rdev,
322 u8 module_index, struct atom_memory_info *mem_info);
323int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
324 bool gddr5, u8 module_index,
325 struct atom_memory_clock_range_table *mclk_range_table);
326int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
327 u16 voltage_id, u16 *voltage);
f892034a 328void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 329extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
330 unsigned *bankh, unsigned *mtaspect,
331 unsigned *tile_split);
3ce0a23d 332
771fe6b9
JG		 333/*
334 * Fences.
335 */
336struct radeon_fence_driver {
337 uint32_t scratch_reg;
30eb77f4
JG		 338 uint64_t gpu_addr;
339 volatile uint32_t *cpu_addr;
68e250b7
CK		 340 /* sync_seq is protected by ring emission lock */
341 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 342 atomic64_t last_seq;
0a0c7596 343 bool initialized;
771fe6b9
JG		 344};
345
346struct radeon_fence {
347 struct radeon_device *rdev;
348 struct kref kref;
771fe6b9 349 /* protected by radeon_fence.lock */
bb635567 350 uint64_t seq;
7465280c 351 /* RB, DMA, etc. */
bb635567 352 unsigned ring;
771fe6b9
JG		 353};
354
30eb77f4
JG		 355int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
356int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 357void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 358void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 359int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 360void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 361bool radeon_fence_signaled(struct radeon_fence *fence);
362int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
1654b817 363int radeon_fence_wait_locked(struct radeon_fence *fence);
8a47cc9e 364int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 365int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 366int radeon_fence_wait_any(struct radeon_device *rdev,
367 struct radeon_fence **fences,
368 bool intr);
771fe6b9
JG		 369struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
370void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 371unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 372bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
373void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
374static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
375 struct radeon_fence *b)
376{
377 if (!a) {
378 return b;
379 }
380
381 if (!b) {
382 return a;
383 }
384
385 BUG_ON(a->ring != b->ring);
386
387 if (a->seq > b->seq) {
388 return a;
389 } else {
390 return b;
391 }
392}
771fe6b9 393
ee60e29f
CK		 394static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
395 struct radeon_fence *b)
396{
397 if (!a) {
398 return false;
399 }
400
401 if (!b) {
402 return true;
403 }
404
405 BUG_ON(a->ring != b->ring);
406
407 return a->seq < b->seq;
408}
409
e024e110
DA		 410/*
411 * Tiling registers
412 */
413struct radeon_surface_reg {
4c788679 414 struct radeon_bo *bo;
e024e110
DA		 415};
416
417#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 418
419/*
4c788679 420 * TTM.
771fe6b9 421 */
4c788679
JG		 422struct radeon_mman {
423 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 424 struct drm_global_reference mem_global_ref;
4c788679 425 struct ttm_bo_device bdev;
0a0c7596
JG		 426 bool mem_global_referenced;
427 bool initialized;
2014b569
CK		 428
429#if defined(CONFIG_DEBUG_FS)
430 struct dentry *vram;
dd66d20e 431 struct dentry *gtt;
2014b569 432#endif
4c788679
JG		 433};
434
721604a1
JG		 435/* bo virtual address in a specific vm */
436struct radeon_bo_va {
e971bd5e 437 /* protected by bo being reserved */
721604a1 438 struct list_head bo_list;
721604a1
JG		 439 uint64_t soffset;
440 uint64_t eoffset;
441 uint32_t flags;
442 bool valid;
e971bd5e
CK		 443 unsigned ref_count;
444
445 /* protected by vm mutex */
446 struct list_head vm_list;
447
448 /* constant after initialization */
449 struct radeon_vm *vm;
450 struct radeon_bo *bo;
721604a1
JG		 451};
452
4c788679
JG		 453struct radeon_bo {
454 /* Protected by gem.mutex */
455 struct list_head list;
456 /* Protected by tbo.reserved */
312ea8da
JG		 457 u32 placements[3];
458 struct ttm_placement placement;
4c788679
JG		 459 struct ttm_buffer_object tbo;
460 struct ttm_bo_kmap_obj kmap;
461 unsigned pin_count;
462 void *kptr;
463 u32 tiling_flags;
464 u32 pitch;
465 int surface_reg;
721604a1
JG		 466 /* list of all virtual address to which this bo
467 * is associated to
468 */
469 struct list_head va;
4c788679
JG		 470 /* Constant after initialization */
471 struct radeon_device *rdev;
441921d5 472 struct drm_gem_object gem_base;
63bc620b 473
409851f4
JG		 474 struct ttm_bo_kmap_obj dma_buf_vmap;
475 pid_t pid;
4c788679 476};
7e4d15d9 477#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 478
4c788679 479struct radeon_bo_list {
147666fb 480 struct ttm_validate_buffer tv;
4c788679 481 struct radeon_bo *bo;
771fe6b9 482 uint64_t gpu_offset;
4474f3a9
CK		 483 bool written;
484 unsigned domain;
485 unsigned alt_domain;
4c788679 486 u32 tiling_flags;
771fe6b9
JG		 487};
488
409851f4
JG		 489int radeon_gem_debugfs_init(struct radeon_device *rdev);
490
b15ba512
JG		 491/* sub-allocation manager, it has to be protected by another lock.
492 * By conception this is an helper for other part of the driver
493 * like the indirect buffer or semaphore, which both have their
494 * locking.
495 *
496 * Principe is simple, we keep a list of sub allocation in offset
497 * order (first entry has offset == 0, last entry has the highest
498 * offset).
499 *
500 * When allocating new object we first check if there is room at
501 * the end total_size - (last_object_offset + last_object_size) >=
502 * alloc_size. If so we allocate new object there.
503 *
504 * When there is not enough room at the end, we start waiting for
505 * each sub object until we reach object_offset+object_size >=
506 * alloc_size, this object then become the sub object we return.
507 *
508 * Alignment can't be bigger than page size.
509 *
510 * Hole are not considered for allocation to keep things simple.
511 * Assumption is that there won't be hole (all object on same
512 * alignment).
513 */
514struct radeon_sa_manager {
bfb38d35 515 wait_queue_head_t wq;
b15ba512 516 struct radeon_bo *bo;
c3b7fe8b
CK		 517 struct list_head *hole;
518 struct list_head flist[RADEON_NUM_RINGS];
519 struct list_head olist;
b15ba512
JG		 520 unsigned size;
521 uint64_t gpu_addr;
522 void *cpu_ptr;
523 uint32_t domain;
6c4f978b 524 uint32_t align;
b15ba512
JG		 525};
526
527struct radeon_sa_bo;
528
529/* sub-allocation buffer */
530struct radeon_sa_bo {
c3b7fe8b
CK		 531 struct list_head olist;
532 struct list_head flist;
b15ba512 533 struct radeon_sa_manager *manager;
e6661a96
CK		 534 unsigned soffset;
535 unsigned eoffset;
557017a0 536 struct radeon_fence *fence;
b15ba512
JG		 537};
538
771fe6b9
JG		 539/*
540 * GEM objects.
541 */
542struct radeon_gem {
4c788679 543 struct mutex mutex;
771fe6b9
JG		 544 struct list_head objects;
545};
546
547int radeon_gem_init(struct radeon_device *rdev);
548void radeon_gem_fini(struct radeon_device *rdev);
549int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 550 int alignment, int initial_domain,
551 bool discardable, bool kernel,
552 struct drm_gem_object **obj);
771fe6b9 553
ff72145b
DA		 554int radeon_mode_dumb_create(struct drm_file *file_priv,
555 struct drm_device *dev,
556 struct drm_mode_create_dumb *args);
557int radeon_mode_dumb_mmap(struct drm_file *filp,
558 struct drm_device *dev,
559 uint32_t handle, uint64_t *offset_p);
771fe6b9 560
c1341e52
JG		 561/*
562 * Semaphores.
563 */
c1341e52 564struct radeon_semaphore {
a8c05940
JG		 565 struct radeon_sa_bo *sa_bo;
566 signed waiters;
c1341e52 567 uint64_t gpu_addr;
1654b817 568 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 569};
570
c1341e52
JG		 571int radeon_semaphore_create(struct radeon_device *rdev,
572 struct radeon_semaphore **semaphore);
1654b817 573bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 574 struct radeon_semaphore *semaphore);
1654b817 575bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 576 struct radeon_semaphore *semaphore);
1654b817
CK		 577void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
578 struct radeon_fence *fence);
8f676c4c
CK		 579int radeon_semaphore_sync_rings(struct radeon_device *rdev,
580 struct radeon_semaphore *semaphore,
1654b817 581 int waiting_ring);
c1341e52 582void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 583 struct radeon_semaphore **semaphore,
a8c05940 584 struct radeon_fence *fence);
c1341e52 585
771fe6b9
JG		 586/*
587 * GART structures, functions & helpers
588 */
589struct radeon_mc;
590
a77f1718 591#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 592#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 593#define RADEON_GPU_PAGE_SHIFT 12
721604a1 594#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 595
771fe6b9
JG		 596struct radeon_gart {
597 dma_addr_t table_addr;
c9a1be96
JG		 598 struct radeon_bo *robj;
599 void *ptr;
771fe6b9
JG		 600 unsigned num_gpu_pages;
601 unsigned num_cpu_pages;
602 unsigned table_size;
771fe6b9
JG		 603 struct page **pages;
604 dma_addr_t *pages_addr;
605 bool ready;
606};
607
608int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
609void radeon_gart_table_ram_free(struct radeon_device *rdev);
610int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
611void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 612int radeon_gart_table_vram_pin(struct radeon_device *rdev);
613void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 614int radeon_gart_init(struct radeon_device *rdev);
615void radeon_gart_fini(struct radeon_device *rdev);
616void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
617 int pages);
618int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 619 int pages, struct page **pagelist,
620 dma_addr_t *dma_addr);
c9a1be96 621void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 622
623
624/*
625 * GPU MC structures, functions & helpers
626 */
627struct radeon_mc {
628 resource_size_t aper_size;
629 resource_size_t aper_base;
630 resource_size_t agp_base;
7a50f01a
DA		 631 /* for some chips with <= 32MB we need to lie
632 * about vram size near mc fb location */
3ce0a23d 633 u64 mc_vram_size;
d594e46a 634 u64 visible_vram_size;
3ce0a23d
JG		 635 u64 gtt_size;
636 u64 gtt_start;
637 u64 gtt_end;
3ce0a23d
JG		 638 u64 vram_start;
639 u64 vram_end;
771fe6b9 640 unsigned vram_width;
3ce0a23d 641 u64 real_vram_size;
771fe6b9
JG		 642 int vram_mtrr;
643 bool vram_is_ddr;
d594e46a 644 bool igp_sideport_enabled;
8d369bb1 645 u64 gtt_base_align;
9ed8b1f9 646 u64 mc_mask;
771fe6b9
JG		 647};
648
06b6476d
AD		 649bool radeon_combios_sideport_present(struct radeon_device *rdev);
650bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 651
652/*
653 * GPU scratch registers structures, functions & helpers
654 */
655struct radeon_scratch {
656 unsigned num_reg;
724c80e1 657 uint32_t reg_base;
771fe6b9
JG		 658 bool free[32];
659 uint32_t reg[32];
660};
661
662int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
663void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
664
75efdee1
AD		 665/*
666 * GPU doorbell structures, functions & helpers
667 */
d5754ab8
AL		 668#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
669
75efdee1 670struct radeon_doorbell {
75efdee1 671 /* doorbell mmio */
d5754ab8
AL		 672 resource_size_t base;
673 resource_size_t size;
674 u32 __iomem *ptr;
675 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
676 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 677};
678
679int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
680void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 681
682/*
683 * IRQS.
684 */
6f34be50
AD		 685
686struct radeon_unpin_work {
687 struct work_struct work;
688 struct radeon_device *rdev;
689 int crtc_id;
690 struct radeon_fence *fence;
691 struct drm_pending_vblank_event *event;
692 struct radeon_bo *old_rbo;
693 u64 new_crtc_base;
694};
695
696struct r500_irq_stat_regs {
697 u32 disp_int;
f122c610 698 u32 hdmi0_status;
6f34be50
AD		 699};
700
701struct r600_irq_stat_regs {
702 u32 disp_int;
703 u32 disp_int_cont;
704 u32 disp_int_cont2;
705 u32 d1grph_int;
706 u32 d2grph_int;
f122c610
AD		 707 u32 hdmi0_status;
708 u32 hdmi1_status;
6f34be50
AD		 709};
710
711struct evergreen_irq_stat_regs {
712 u32 disp_int;
713 u32 disp_int_cont;
714 u32 disp_int_cont2;
715 u32 disp_int_cont3;
716 u32 disp_int_cont4;
717 u32 disp_int_cont5;
718 u32 d1grph_int;
719 u32 d2grph_int;
720 u32 d3grph_int;
721 u32 d4grph_int;
722 u32 d5grph_int;
723 u32 d6grph_int;
f122c610
AD		 724 u32 afmt_status1;
725 u32 afmt_status2;
726 u32 afmt_status3;
727 u32 afmt_status4;
728 u32 afmt_status5;
729 u32 afmt_status6;
6f34be50
AD		 730};
731
a59781bb
AD		 732struct cik_irq_stat_regs {
733 u32 disp_int;
734 u32 disp_int_cont;
735 u32 disp_int_cont2;
736 u32 disp_int_cont3;
737 u32 disp_int_cont4;
738 u32 disp_int_cont5;
739 u32 disp_int_cont6;
740};
741
6f34be50
AD		 742union radeon_irq_stat_regs {
743 struct r500_irq_stat_regs r500;
744 struct r600_irq_stat_regs r600;
745 struct evergreen_irq_stat_regs evergreen;
a59781bb 746 struct cik_irq_stat_regs cik;
6f34be50
AD		 747};
748
54bd5206
IH		 749#define RADEON_MAX_HPD_PINS 6
750#define RADEON_MAX_CRTCS 6
b530602f 751#define RADEON_MAX_AFMT_BLOCKS 7
54bd5206 752
771fe6b9 753struct radeon_irq {
fb98257a
CK		 754 bool installed;
755 spinlock_t lock;
736fc37f 756 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 757 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 758 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 759 wait_queue_head_t vblank_queue;
760 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 761 bool afmt[RADEON_MAX_AFMT_BLOCKS];
762 union radeon_irq_stat_regs stat_regs;
4a6369e9 763 bool dpm_thermal;
771fe6b9
JG		 764};
765
766int radeon_irq_kms_init(struct radeon_device *rdev);
767void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 768void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
769void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 770void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
771void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 772void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
773void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
774void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
775void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 776
777/*
e32eb50d 778 * CP & rings.
771fe6b9 779 */
7465280c 780
771fe6b9 781struct radeon_ib {
68470ae7
JG		 782 struct radeon_sa_bo *sa_bo;
783 uint32_t length_dw;
784 uint64_t gpu_addr;
785 uint32_t *ptr;
876dc9f3 786 int ring;
68470ae7 787 struct radeon_fence *fence;
4bf3dd92 788 struct radeon_vm *vm;
68470ae7
JG		 789 bool is_const_ib;
790 struct radeon_semaphore *semaphore;
771fe6b9
JG		 791};
792
e32eb50d 793struct radeon_ring {
4c788679 794 struct radeon_bo *ring_obj;
771fe6b9 795 volatile uint32_t *ring;
5596a9db 796 unsigned rptr_offs;
45df6803 797 unsigned rptr_save_reg;
89d35807
AD		 798 u64 next_rptr_gpu_addr;
799 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 800 unsigned wptr;
801 unsigned wptr_old;
802 unsigned ring_size;
803 unsigned ring_free_dw;
804 int count_dw;
069211e5
CK		 805 unsigned long last_activity;
806 unsigned last_rptr;
771fe6b9
JG		 807 uint64_t gpu_addr;
808 uint32_t align_mask;
809 uint32_t ptr_mask;
771fe6b9 810 bool ready;
78c5560a 811 u32 nop;
8b25ed34 812 u32 idx;
5f0839c1
JG		 813 u64 last_semaphore_signal_addr;
814 u64 last_semaphore_wait_addr;
963e81f9
AD		 815 /* for CIK queues */
816 u32 me;
817 u32 pipe;
818 u32 queue;
819 struct radeon_bo *mqd_obj;
d5754ab8 820 u32 doorbell_index;
963e81f9
AD		 821 unsigned wptr_offs;
822};
823
824struct radeon_mec {
825 struct radeon_bo *hpd_eop_obj;
826 u64 hpd_eop_gpu_addr;
827 u32 num_pipe;
828 u32 num_mec;
829 u32 num_queue;
771fe6b9
JG		 830};
831
721604a1
JG		 832/*
833 * VM
834 */
ee60e29f 835
fa87e62d 836/* maximum number of VMIDs */
ee60e29f
CK		 837#define RADEON_NUM_VM 16
838
fa87e62d
DC		 839/* defines number of bits in page table versus page directory,
840 * a page is 4KB so we have 12 bits offset, 9 bits in the page
841 * table and the remaining 19 bits are in the page directory */
842#define RADEON_VM_BLOCK_SIZE 9
843
844/* number of entries in page table */
845#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
846
1c01103c
AD		 847/* PTBs (Page Table Blocks) need to be aligned to 32K */
848#define RADEON_VM_PTB_ALIGN_SIZE 32768
849#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
850#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
851
24c16439
CK		 852#define R600_PTE_VALID (1 << 0)
853#define R600_PTE_SYSTEM (1 << 1)
854#define R600_PTE_SNOOPED (1 << 2)
855#define R600_PTE_READABLE (1 << 5)
856#define R600_PTE_WRITEABLE (1 << 6)
857
721604a1
JG		 858struct radeon_vm {
859 struct list_head list;
860 struct list_head va;
ee60e29f 861 unsigned id;
90a51a32
CK		 862
863 /* contains the page directory */
864 struct radeon_sa_bo *page_directory;
865 uint64_t pd_gpu_addr;
866
867 /* array of page tables, one for each page directory entry */
868 struct radeon_sa_bo **page_tables;
869
721604a1
JG		 870 struct mutex mutex;
871 /* last fence for cs using this vm */
872 struct radeon_fence *fence;
9b40e5d8
CK		 873 /* last flush or NULL if we still need to flush */
874 struct radeon_fence *last_flush;
593b2635
CK		 875 /* last use of vmid */
876 struct radeon_fence *last_id_use;
721604a1
JG		 877};
878
721604a1 879struct radeon_vm_manager {
36ff39c4 880 struct mutex lock;
721604a1 881 struct list_head lru_vm;
ee60e29f 882 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 883 struct radeon_sa_manager sa_manager;
884 uint32_t max_pfn;
721604a1
JG		 885 /* number of VMIDs */
886 unsigned nvm;
887 /* vram base address for page table entry */
888 u64 vram_base_offset;
67e915e4
AD		 889 /* is vm enabled? */
890 bool enabled;
721604a1
JG		 891};
892
893/*
894 * file private structure
895 */
896struct radeon_fpriv {
897 struct radeon_vm vm;
898};
899
d8f60cfc
AD		 900/*
901 * R6xx+ IH ring
902 */
903struct r600_ih {
4c788679 904 struct radeon_bo *ring_obj;
d8f60cfc
AD		 905 volatile uint32_t *ring;
906 unsigned rptr;
d8f60cfc
AD		 907 unsigned ring_size;
908 uint64_t gpu_addr;
d8f60cfc 909 uint32_t ptr_mask;
c20dc369 910 atomic_t lock;
d8f60cfc
AD		 911 bool enabled;
912};
913
347e7592 914/*
2948f5e6 915 * RLC stuff
347e7592 916 */
2948f5e6
AD		 917#include "clearstate_defs.h"
918
919struct radeon_rlc {
347e7592
AD		 920 /* for power gating */
921 struct radeon_bo *save_restore_obj;
922 uint64_t save_restore_gpu_addr;
2948f5e6 923 volatile uint32_t *sr_ptr;
1fd11777 924 const u32 *reg_list;
2948f5e6 925 u32 reg_list_size;
347e7592
AD		 926 /* for clear state */
927 struct radeon_bo *clear_state_obj;
928 uint64_t clear_state_gpu_addr;
2948f5e6 929 volatile uint32_t *cs_ptr;
1fd11777 930 const struct cs_section_def *cs_data;
22c775ce
AD		 931 u32 clear_state_size;
932 /* for cp tables */
933 struct radeon_bo *cp_table_obj;
934 uint64_t cp_table_gpu_addr;
935 volatile uint32_t *cp_table_ptr;
936 u32 cp_table_size;
347e7592
AD		 937};
938
69e130a6 939int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 940 struct radeon_ib *ib, struct radeon_vm *vm,
941 unsigned size);
f2e39221 942void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 943int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
944 struct radeon_ib *const_ib);
771fe6b9
JG		 945int radeon_ib_pool_init(struct radeon_device *rdev);
946void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 947int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 948/* Ring access between begin & end cannot sleep */
89d35807
AD		 949bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
950 struct radeon_ring *ring);
e32eb50d
CK		 951void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
952int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
953int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
954void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
955void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 956void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 957void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
958int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 959void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
ff212f25
CK		 960void radeon_ring_lockup_update(struct radeon_device *rdev,
961 struct radeon_ring *ring);
069211e5 962bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 963unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
964 uint32_t **data);
965int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
966 unsigned size, uint32_t *data);
e32eb50d 967int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 968 unsigned rptr_offs, u32 nop);
e32eb50d 969void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 970
971
4d75658b
AD		 972/* r600 async dma */
973void r600_dma_stop(struct radeon_device *rdev);
974int r600_dma_resume(struct radeon_device *rdev);
975void r600_dma_fini(struct radeon_device *rdev);
976
8c5fd7ef
AD		 977void cayman_dma_stop(struct radeon_device *rdev);
978int cayman_dma_resume(struct radeon_device *rdev);
979void cayman_dma_fini(struct radeon_device *rdev);
980
771fe6b9
JG		 981/*
982 * CS.
983 */
984struct radeon_cs_reloc {
985 struct drm_gem_object *gobj;
4c788679
JG		 986 struct radeon_bo *robj;
987 struct radeon_bo_list lobj;
771fe6b9
JG		 988 uint32_t handle;
989 uint32_t flags;
990};
991
992struct radeon_cs_chunk {
993 uint32_t chunk_id;
994 uint32_t length_dw;
995 uint32_t *kdata;
721604a1 996 void __user *user_ptr;
771fe6b9
JG		 997};
998
999struct radeon_cs_parser {
c8c15ff1 1000 struct device *dev;
771fe6b9
JG		 1001 struct radeon_device *rdev;
1002 struct drm_file *filp;
1003 /* chunks */
1004 unsigned nchunks;
1005 struct radeon_cs_chunk *chunks;
1006 uint64_t *chunks_array;
1007 /* IB */
1008 unsigned idx;
1009 /* relocations */
1010 unsigned nrelocs;
1011 struct radeon_cs_reloc *relocs;
1012 struct radeon_cs_reloc **relocs_ptr;
1013 struct list_head validated;
cf4ccd01 1014 unsigned dma_reloc_idx;
771fe6b9
JG		 1015 /* indices of various chunks */
1016 int chunk_ib_idx;
1017 int chunk_relocs_idx;
721604a1 1018 int chunk_flags_idx;
dfcf5f36 1019 int chunk_const_ib_idx;
f2e39221
JG		 1020 struct radeon_ib ib;
1021 struct radeon_ib const_ib;
771fe6b9 1022 void *track;
3ce0a23d 1023 unsigned family;
e70f224c 1024 int parser_error;
721604a1
JG		 1025 u32 cs_flags;
1026 u32 ring;
1027 s32 priority;
ecff665f 1028 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1029};
1030
28a326c5
ML		 1031static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1032{
1033 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1034
1035 if (ibc->kdata)
1036 return ibc->kdata[idx];
1037 return p->ib.ptr[idx];
1038}
1039
513bcb46 1040
771fe6b9
JG		 1041struct radeon_cs_packet {
1042 unsigned idx;
1043 unsigned type;
1044 unsigned reg;
1045 unsigned opcode;
1046 int count;
1047 unsigned one_reg_wr;
1048};
1049
1050typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1051 struct radeon_cs_packet *pkt,
1052 unsigned idx, unsigned reg);
1053typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1054 struct radeon_cs_packet *pkt);
1055
1056
1057/*
1058 * AGP
1059 */
1060int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1061void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1062void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1063void radeon_agp_fini(struct radeon_device *rdev);
1064
1065
1066/*
1067 * Writeback
1068 */
1069struct radeon_wb {
4c788679 1070 struct radeon_bo *wb_obj;
771fe6b9
JG		 1071 volatile uint32_t *wb;
1072 uint64_t gpu_addr;
724c80e1 1073 bool enabled;
d0f8a854 1074 bool use_event;
771fe6b9
JG		 1075};
1076
724c80e1 1077#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1078#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1079#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1080#define RADEON_WB_CP1_RPTR_OFFSET 1280
1081#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1082#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1083#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1084#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1085#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1086#define CIK_WB_CP1_WPTR_OFFSET 3328
1087#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1088
c93bb85b
JG		 1089/**
1090 * struct radeon_pm - power management datas
1091 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1092 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1093 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1094 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1095 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1096 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1097 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1098 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1099 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1100 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1101 * @needed_bandwidth: current bandwidth needs
1102 *
1103 * It keeps track of various data needed to take powermanagement decision.
25985edc 1104 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1105 * Equation between gpu/memory clock and available bandwidth is hw dependent
1106 * (type of memory, bus size, efficiency, ...)
1107 */
ce8f5370
AD		 1108
1109enum radeon_pm_method {
1110 PM_METHOD_PROFILE,
1111 PM_METHOD_DYNPM,
da321c8a 1112 PM_METHOD_DPM,
ce8f5370
AD		 1113};
1114
1115enum radeon_dynpm_state {
1116 DYNPM_STATE_DISABLED,
1117 DYNPM_STATE_MINIMUM,
1118 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1119 DYNPM_STATE_ACTIVE,
1120 DYNPM_STATE_SUSPENDED,
c913e23a 1121};
ce8f5370
AD		 1122enum radeon_dynpm_action {
1123 DYNPM_ACTION_NONE,
1124 DYNPM_ACTION_MINIMUM,
1125 DYNPM_ACTION_DOWNCLOCK,
1126 DYNPM_ACTION_UPCLOCK,
1127 DYNPM_ACTION_DEFAULT
c913e23a 1128};
56278a8e
AD		 1129
1130enum radeon_voltage_type {
1131 VOLTAGE_NONE = 0,
1132 VOLTAGE_GPIO,
1133 VOLTAGE_VDDC,
1134 VOLTAGE_SW
1135};
1136
0ec0e74f 1137enum radeon_pm_state_type {
da321c8a 1138 /* not used for dpm */
0ec0e74f
AD		 1139 POWER_STATE_TYPE_DEFAULT,
1140 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1141 /* user selectable states */
0ec0e74f
AD		 1142 POWER_STATE_TYPE_BATTERY,
1143 POWER_STATE_TYPE_BALANCED,
1144 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1145 /* internal states */
1146 POWER_STATE_TYPE_INTERNAL_UVD,
1147 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1148 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1149 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1150 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1151 POWER_STATE_TYPE_INTERNAL_BOOT,
1152 POWER_STATE_TYPE_INTERNAL_THERMAL,
1153 POWER_STATE_TYPE_INTERNAL_ACPI,
1154 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1155 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1156};
1157
ce8f5370
AD		 1158enum radeon_pm_profile_type {
1159 PM_PROFILE_DEFAULT,
1160 PM_PROFILE_AUTO,
1161 PM_PROFILE_LOW,
c9e75b21 1162 PM_PROFILE_MID,
ce8f5370
AD		 1163 PM_PROFILE_HIGH,
1164};
1165
1166#define PM_PROFILE_DEFAULT_IDX 0
1167#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1168#define PM_PROFILE_MID_SH_IDX 2
1169#define PM_PROFILE_HIGH_SH_IDX 3
1170#define PM_PROFILE_LOW_MH_IDX 4
1171#define PM_PROFILE_MID_MH_IDX 5
1172#define PM_PROFILE_HIGH_MH_IDX 6
1173#define PM_PROFILE_MAX 7
ce8f5370
AD		 1174
1175struct radeon_pm_profile {
1176 int dpms_off_ps_idx;
1177 int dpms_on_ps_idx;
1178 int dpms_off_cm_idx;
1179 int dpms_on_cm_idx;
516d0e46
AD		 1180};
1181
21a8122a
AD		 1182enum radeon_int_thermal_type {
1183 THERMAL_TYPE_NONE,
da321c8a
AD		 1184 THERMAL_TYPE_EXTERNAL,
1185 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1186 THERMAL_TYPE_RV6XX,
1187 THERMAL_TYPE_RV770,
da321c8a 1188 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1189 THERMAL_TYPE_EVERGREEN,
e33df25f 1190 THERMAL_TYPE_SUMO,
4fddba1f 1191 THERMAL_TYPE_NI,
14607d08 1192 THERMAL_TYPE_SI,
da321c8a 1193 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1194 THERMAL_TYPE_CI,
16fbe00d 1195 THERMAL_TYPE_KV,
21a8122a
AD		 1196};
1197
56278a8e
AD		 1198struct radeon_voltage {
1199 enum radeon_voltage_type type;
1200 /* gpio voltage */
1201 struct radeon_gpio_rec gpio;
1202 u32 delay; /* delay in usec from voltage drop to sclk change */
1203 bool active_high; /* voltage drop is active when bit is high */
1204 /* VDDC voltage */
1205 u8 vddc_id; /* index into vddc voltage table */
1206 u8 vddci_id; /* index into vddci voltage table */
1207 bool vddci_enabled;
1208 /* r6xx+ sw */
2feea49a
AD		 1209 u16 voltage;
1210 /* evergreen+ vddci */
1211 u16 vddci;
56278a8e
AD		 1212};
1213
d7311171
AD		 1214/* clock mode flags */
1215#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1216
56278a8e
AD		 1217struct radeon_pm_clock_info {
1218 /* memory clock */
1219 u32 mclk;
1220 /* engine clock */
1221 u32 sclk;
1222 /* voltage info */
1223 struct radeon_voltage voltage;
d7311171 1224 /* standardized clock flags */
56278a8e
AD		 1225 u32 flags;
1226};
1227
a48b9b4e 1228/* state flags */
d7311171 1229#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1230
56278a8e 1231struct radeon_power_state {
0ec0e74f 1232 enum radeon_pm_state_type type;
8f3f1c9a 1233 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1234 /* number of valid clock modes in this power state */
1235 int num_clock_modes;
56278a8e 1236 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1237 /* standardized state flags */
1238 u32 flags;
79daedc9
AD		 1239 u32 misc; /* vbios specific flags */
1240 u32 misc2; /* vbios specific flags */
1241 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1242};
1243
27459324
RM		 1244/*
1245 * Some modes are overclocked by very low value, accept them
1246 */
1247#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1248
2e9d4c05
AD		 1249enum radeon_dpm_auto_throttle_src {
1250 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1251 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1252};
1253
1254enum radeon_dpm_event_src {
1255 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1256 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1257 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1258 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1259 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1260};
1261
58bd2a88
AD		 1262#define RADEON_MAX_VCE_LEVELS 6
1263
b62d628b
AD		 1264enum radeon_vce_level {
1265 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1266 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1267 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1268 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1269 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1270 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1271};
1272
da321c8a
AD		 1273struct radeon_ps {
1274 u32 caps; /* vbios flags */
1275 u32 class; /* vbios flags */
1276 u32 class2; /* vbios flags */
1277 /* UVD clocks */
1278 u32 vclk;
1279 u32 dclk;
c4453e66
AD		 1280 /* VCE clocks */
1281 u32 evclk;
1282 u32 ecclk;
b62d628b
AD		 1283 bool vce_active;
1284 enum radeon_vce_level vce_level;
da321c8a
AD		 1285 /* asic priv */
1286 void *ps_priv;
1287};
1288
1289struct radeon_dpm_thermal {
1290 /* thermal interrupt work */
1291 struct work_struct work;
1292 /* low temperature threshold */
1293 int min_temp;
1294 /* high temperature threshold */
1295 int max_temp;
1296 /* was interrupt low to high or high to low */
1297 bool high_to_low;
1298};
1299
d22b7e40
AD		 1300enum radeon_clk_action
1301{
1302 RADEON_SCLK_UP = 1,
1303 RADEON_SCLK_DOWN
1304};
1305
1306struct radeon_blacklist_clocks
1307{
1308 u32 sclk;
1309 u32 mclk;
1310 enum radeon_clk_action action;
1311};
1312
61b7d601
AD		 1313struct radeon_clock_and_voltage_limits {
1314 u32 sclk;
1315 u32 mclk;
cdf6e805
AD		 1316 u16 vddc;
1317 u16 vddci;
61b7d601
AD		 1318};
1319
1320struct radeon_clock_array {
1321 u32 count;
1322 u32 *values;
1323};
1324
1325struct radeon_clock_voltage_dependency_entry {
1326 u32 clk;
1327 u16 v;
1328};
1329
1330struct radeon_clock_voltage_dependency_table {
1331 u32 count;
1332 struct radeon_clock_voltage_dependency_entry *entries;
1333};
1334
ef976ec4
AD		 1335union radeon_cac_leakage_entry {
1336 struct {
1337 u16 vddc;
1338 u32 leakage;
1339 };
1340 struct {
1341 u16 vddc1;
1342 u16 vddc2;
1343 u16 vddc3;
1344 };
61b7d601
AD		 1345};
1346
1347struct radeon_cac_leakage_table {
1348 u32 count;
ef976ec4 1349 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1350};
1351
929ee7a8
AD		 1352struct radeon_phase_shedding_limits_entry {
1353 u16 voltage;
1354 u32 sclk;
1355 u32 mclk;
1356};
1357
1358struct radeon_phase_shedding_limits_table {
1359 u32 count;
1360 struct radeon_phase_shedding_limits_entry *entries;
1361};
1362
84a9d9ee
AD		 1363struct radeon_uvd_clock_voltage_dependency_entry {
1364 u32 vclk;
1365 u32 dclk;
1366 u16 v;
1367};
1368
1369struct radeon_uvd_clock_voltage_dependency_table {
1370 u8 count;
1371 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1372};
1373
d29f013b
AD		 1374struct radeon_vce_clock_voltage_dependency_entry {
1375 u32 ecclk;
1376 u32 evclk;
1377 u16 v;
1378};
1379
1380struct radeon_vce_clock_voltage_dependency_table {
1381 u8 count;
1382 struct radeon_vce_clock_voltage_dependency_entry *entries;
1383};
1384
a5cb318e
AD		 1385struct radeon_ppm_table {
1386 u8 ppm_design;
1387 u16 cpu_core_number;
1388 u32 platform_tdp;
1389 u32 small_ac_platform_tdp;
1390 u32 platform_tdc;
1391 u32 small_ac_platform_tdc;
1392 u32 apu_tdp;
1393 u32 dgpu_tdp;
1394 u32 dgpu_ulv_power;
1395 u32 tj_max;
1396};
1397
58cb7632
AD		 1398struct radeon_cac_tdp_table {
1399 u16 tdp;
1400 u16 configurable_tdp;
1401 u16 tdc;
1402 u16 battery_power_limit;
1403 u16 small_power_limit;
1404 u16 low_cac_leakage;
1405 u16 high_cac_leakage;
1406 u16 maximum_power_delivery_limit;
1407};
1408
61b7d601
AD		 1409struct radeon_dpm_dynamic_state {
1410 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1411 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1412 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1413 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1414 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1415 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1416 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1417 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1418 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1419 struct radeon_clock_array valid_sclk_values;
1420 struct radeon_clock_array valid_mclk_values;
1421 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1422 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1423 u32 mclk_sclk_ratio;
1424 u32 sclk_mclk_delta;
1425 u16 vddc_vddci_delta;
1426 u16 min_vddc_for_pcie_gen2;
1427 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1428 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1429 struct radeon_ppm_table *ppm_table;
58cb7632 1430 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1431};
1432
1433struct radeon_dpm_fan {
1434 u16 t_min;
1435 u16 t_med;
1436 u16 t_high;
1437 u16 pwm_min;
1438 u16 pwm_med;
1439 u16 pwm_high;
1440 u8 t_hyst;
1441 u32 cycle_delay;
1442 u16 t_max;
1443 bool ucode_fan_control;
1444};
1445
32ce4652
AD		 1446enum radeon_pcie_gen {
1447 RADEON_PCIE_GEN1 = 0,
1448 RADEON_PCIE_GEN2 = 1,
1449 RADEON_PCIE_GEN3 = 2,
1450 RADEON_PCIE_GEN_INVALID = 0xffff
1451};
1452
70d01a5e
AD		 1453enum radeon_dpm_forced_level {
1454 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1455 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1456 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1457};
1458
58bd2a88
AD		 1459struct radeon_vce_state {
1460 /* vce clocks */
1461 u32 evclk;
1462 u32 ecclk;
1463 /* gpu clocks */
1464 u32 sclk;
1465 u32 mclk;
1466 u8 clk_idx;
1467 u8 pstate;
1468};
1469
da321c8a
AD		 1470struct radeon_dpm {
1471 struct radeon_ps *ps;
1472 /* number of valid power states */
1473 int num_ps;
1474 /* current power state that is active */
1475 struct radeon_ps *current_ps;
1476 /* requested power state */
1477 struct radeon_ps *requested_ps;
1478 /* boot up power state */
1479 struct radeon_ps *boot_ps;
1480 /* default uvd power state */
1481 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1482 /* vce requirements */
1483 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1484 enum radeon_vce_level vce_level;
da321c8a
AD		 1485 enum radeon_pm_state_type state;
1486 enum radeon_pm_state_type user_state;
1487 u32 platform_caps;
1488 u32 voltage_response_time;
1489 u32 backbias_response_time;
1490 void *priv;
1491 u32 new_active_crtcs;
1492 int new_active_crtc_count;
1493 u32 current_active_crtcs;
1494 int current_active_crtc_count;
61b7d601
AD		 1495 struct radeon_dpm_dynamic_state dyn_state;
1496 struct radeon_dpm_fan fan;
1497 u32 tdp_limit;
1498 u32 near_tdp_limit;
a9e61410 1499 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1500 u32 sq_ramping_threshold;
1501 u32 cac_leakage;
1502 u16 tdp_od_limit;
1503 u32 tdp_adjustment;
1504 u16 load_line_slope;
1505 bool power_control;
5ca302f7 1506 bool ac_power;
da321c8a
AD		 1507 /* special states active */
1508 bool thermal_active;
8a227555 1509 bool uvd_active;
b62d628b 1510 bool vce_active;
da321c8a
AD		 1511 /* thermal handling */
1512 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1513 /* forced levels */
1514 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1515 /* track UVD streams */
1516 unsigned sd;
1517 unsigned hd;
da321c8a
AD		 1518};
1519
ce3537d5 1520void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1521void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1522
c93bb85b 1523struct radeon_pm {
c913e23a 1524 struct mutex mutex;
db7fce39
CK		 1525 /* write locked while reprogramming mclk */
1526 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1527 u32 active_crtcs;
1528 int active_crtc_count;
c913e23a 1529 int req_vblank;
839461d3 1530 bool vblank_sync;
c93bb85b
JG		 1531 fixed20_12 max_bandwidth;
1532 fixed20_12 igp_sideport_mclk;
1533 fixed20_12 igp_system_mclk;
1534 fixed20_12 igp_ht_link_clk;
1535 fixed20_12 igp_ht_link_width;
1536 fixed20_12 k8_bandwidth;
1537 fixed20_12 sideport_bandwidth;
1538 fixed20_12 ht_bandwidth;
1539 fixed20_12 core_bandwidth;
1540 fixed20_12 sclk;
f47299c5 1541 fixed20_12 mclk;
c93bb85b 1542 fixed20_12 needed_bandwidth;
0975b162 1543 struct radeon_power_state *power_state;
56278a8e
AD		 1544 /* number of valid power states */
1545 int num_power_states;
a48b9b4e
AD		 1546 int current_power_state_index;
1547 int current_clock_mode_index;
1548 int requested_power_state_index;
1549 int requested_clock_mode_index;
1550 int default_power_state_index;
1551 u32 current_sclk;
1552 u32 current_mclk;
2feea49a
AD		 1553 u16 current_vddc;
1554 u16 current_vddci;
9ace9f7b
AD		 1555 u32 default_sclk;
1556 u32 default_mclk;
2feea49a
AD		 1557 u16 default_vddc;
1558 u16 default_vddci;
29fb52ca 1559 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1560 /* selected pm method */
1561 enum radeon_pm_method pm_method;
1562 /* dynpm power management */
1563 struct delayed_work dynpm_idle_work;
1564 enum radeon_dynpm_state dynpm_state;
1565 enum radeon_dynpm_action dynpm_planned_action;
1566 unsigned long dynpm_action_timeout;
1567 bool dynpm_can_upclock;
1568 bool dynpm_can_downclock;
1569 /* profile-based power management */
1570 enum radeon_pm_profile_type profile;
1571 int profile_index;
1572 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1573 /* internal thermal controller on rv6xx+ */
1574 enum radeon_int_thermal_type int_thermal_type;
1575 struct device *int_hwmon_dev;
da321c8a
AD		 1576 /* dpm */
1577 bool dpm_enabled;
1578 struct radeon_dpm dpm;
c93bb85b
JG		 1579};
1580
a4c9e2ee
AD		 1581int radeon_pm_get_type_index(struct radeon_device *rdev,
1582 enum radeon_pm_state_type ps_type,
1583 int instance);
f2ba57b5
CK		 1584/*
1585 * UVD
1586 */
1587#define RADEON_MAX_UVD_HANDLES 10
1588#define RADEON_UVD_STACK_SIZE (1024*1024)
1589#define RADEON_UVD_HEAP_SIZE (1024*1024)
1590
1591struct radeon_uvd {
1592 struct radeon_bo *vcpu_bo;
1593 void *cpu_addr;
1594 uint64_t gpu_addr;
9cc2e0e9 1595 void *saved_bo;
f2ba57b5
CK		 1596 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1597 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1598 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1599 struct delayed_work idle_work;
f2ba57b5
CK		 1600};
1601
1602int radeon_uvd_init(struct radeon_device *rdev);
1603void radeon_uvd_fini(struct radeon_device *rdev);
1604int radeon_uvd_suspend(struct radeon_device *rdev);
1605int radeon_uvd_resume(struct radeon_device *rdev);
1606int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1607 uint32_t handle, struct radeon_fence **fence);
1608int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1609 uint32_t handle, struct radeon_fence **fence);
1610void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1611void radeon_uvd_free_handles(struct radeon_device *rdev,
1612 struct drm_file *filp);
1613int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1614void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1615int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1616 unsigned vclk, unsigned dclk,
1617 unsigned vco_min, unsigned vco_max,
1618 unsigned fb_factor, unsigned fb_mask,
1619 unsigned pd_min, unsigned pd_max,
1620 unsigned pd_even,
1621 unsigned *optimal_fb_div,
1622 unsigned *optimal_vclk_div,
1623 unsigned *optimal_dclk_div);
1624int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1625 unsigned cg_upll_func_cntl);
771fe6b9 1626
d93f7937
CK		 1627/*
1628 * VCE
1629 */
1630#define RADEON_MAX_VCE_HANDLES 16
1631#define RADEON_VCE_STACK_SIZE (1024*1024)
1632#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1633
1634struct radeon_vce {
1635 struct radeon_bo *vcpu_bo;
1636 void *cpu_addr;
1637 uint64_t gpu_addr;
98ccc291
CK		 1638 unsigned fw_version;
1639 unsigned fb_version;
d93f7937
CK		 1640 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1641 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
03afe6f6 1642 struct delayed_work idle_work;
d93f7937
CK		 1643};
1644
1645int radeon_vce_init(struct radeon_device *rdev);
1646void radeon_vce_fini(struct radeon_device *rdev);
1647int radeon_vce_suspend(struct radeon_device *rdev);
1648int radeon_vce_resume(struct radeon_device *rdev);
1649int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1650 uint32_t handle, struct radeon_fence **fence);
1651int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1652 uint32_t handle, struct radeon_fence **fence);
1653void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1654void radeon_vce_note_usage(struct radeon_device *rdev);
d93f7937
CK		 1655int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi);
1656int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1657bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1658 struct radeon_ring *ring,
1659 struct radeon_semaphore *semaphore,
1660 bool emit_wait);
1661void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1662void radeon_vce_fence_emit(struct radeon_device *rdev,
1663 struct radeon_fence *fence);
1664int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1665int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1666
b530602f 1667struct r600_audio_pin {
a92553ab
RM		 1668 int channels;
1669 int rate;
1670 int bits_per_sample;
1671 u8 status_bits;
1672 u8 category_code;
b530602f
AD		 1673 u32 offset;
1674 bool connected;
1675 u32 id;
1676};
1677
1678struct r600_audio {
1679 bool enabled;
1680 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1681 int num_pins;
a92553ab
RM		 1682};
1683
771fe6b9
JG		 1684/*
1685 * Benchmarking
1686 */
638dd7db 1687void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1688
1689
ecc0b326
MD		 1690/*
1691 * Testing
1692 */
1693void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1694void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1695 struct radeon_ring *cpA,
1696 struct radeon_ring *cpB);
60a7e396 1697void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1698
1699
771fe6b9
JG		 1700/*
1701 * Debugfs
1702 */
4d8bf9ae
CK		 1703struct radeon_debugfs {
1704 struct drm_info_list *files;
1705 unsigned num_files;
1706};
1707
771fe6b9
JG		 1708int radeon_debugfs_add_files(struct radeon_device *rdev,
1709 struct drm_info_list *files,
1710 unsigned nfiles);
1711int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1712
76a0df85
CK		 1713/*
1714 * ASIC ring specific functions.
1715 */
1716struct radeon_asic_ring {
1717 /* ring read/write ptr handling */
1718 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1719 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1720 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1721
1722 /* validating and patching of IBs */
1723 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1724 int (*cs_parse)(struct radeon_cs_parser *p);
1725
1726 /* command emmit functions */
1727 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1728 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1654b817 1729 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1730 struct radeon_semaphore *semaphore, bool emit_wait);
1731 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1732
1733 /* testing functions */
1734 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1735 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1736 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1737
1738 /* deprecated */
1739 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1740};
771fe6b9
JG		 1741
1742/*
1743 * ASIC specific functions.
1744 */
1745struct radeon_asic {
068a117c 1746 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1747 void (*fini)(struct radeon_device *rdev);
1748 int (*resume)(struct radeon_device *rdev);
1749 int (*suspend)(struct radeon_device *rdev);
28d52043 1750 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1751 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1752 /* ioctl hw specific callback. Some hw might want to perform special
1753 * operation on specific ioctl. For instance on wait idle some hw
1754 * might want to perform and HDP flush through MMIO as it seems that
1755 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1756 * through ring.
1757 */
1758 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1759 /* check if 3D engine is idle */
1760 bool (*gui_idle)(struct radeon_device *rdev);
1761 /* wait for mc_idle */
1762 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1763 /* get the reference clock */
1764 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1765 /* get the gpu clock counter */
1766 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1767 /* gart */
c5b3b850
AD		 1768 struct {
1769 void (*tlb_flush)(struct radeon_device *rdev);
1770 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1771 } gart;
05b07147
CK		 1772 struct {
1773 int (*init)(struct radeon_device *rdev);
1774 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1775 void (*set_page)(struct radeon_device *rdev,
1776 struct radeon_ib *ib,
1777 uint64_t pe,
dce34bfd
CK		 1778 uint64_t addr, unsigned count,
1779 uint32_t incr, uint32_t flags);
05b07147 1780 } vm;
54e88e06 1781 /* ring specific callbacks */
76a0df85 1782 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1783 /* irqs */
b35ea4ab
AD		 1784 struct {
1785 int (*set)(struct radeon_device *rdev);
1786 int (*process)(struct radeon_device *rdev);
1787 } irq;
54e88e06 1788 /* displays */
c79a49ca
AD		 1789 struct {
1790 /* display watermarks */
1791 void (*bandwidth_update)(struct radeon_device *rdev);
1792 /* get frame count */
1793 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1794 /* wait for vblank */
1795 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1796 /* set backlight level */
1797 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1798 /* get backlight level */
1799 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1800 /* audio callbacks */
1801 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1802 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1803 } display;
54e88e06 1804 /* copy functions for bo handling */
27cd7769
AD		 1805 struct {
1806 int (*blit)(struct radeon_device *rdev,
1807 uint64_t src_offset,
1808 uint64_t dst_offset,
1809 unsigned num_gpu_pages,
876dc9f3 1810 struct radeon_fence **fence);
27cd7769
AD		 1811 u32 blit_ring_index;
1812 int (*dma)(struct radeon_device *rdev,
1813 uint64_t src_offset,
1814 uint64_t dst_offset,
1815 unsigned num_gpu_pages,
876dc9f3 1816 struct radeon_fence **fence);
27cd7769
AD		 1817 u32 dma_ring_index;
1818 /* method used for bo copy */
1819 int (*copy)(struct radeon_device *rdev,
1820 uint64_t src_offset,
1821 uint64_t dst_offset,
1822 unsigned num_gpu_pages,
876dc9f3 1823 struct radeon_fence **fence);
27cd7769
AD		 1824 /* ring used for bo copies */
1825 u32 copy_ring_index;
1826 } copy;
54e88e06 1827 /* surfaces */
9e6f3d02
AD		 1828 struct {
1829 int (*set_reg)(struct radeon_device *rdev, int reg,
1830 uint32_t tiling_flags, uint32_t pitch,
1831 uint32_t offset, uint32_t obj_size);
1832 void (*clear_reg)(struct radeon_device *rdev, int reg);
1833 } surface;
54e88e06 1834 /* hotplug detect */
901ea57d
AD		 1835 struct {
1836 void (*init)(struct radeon_device *rdev);
1837 void (*fini)(struct radeon_device *rdev);
1838 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1839 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1840 } hpd;
da321c8a 1841 /* static power management */
a02fa397
AD		 1842 struct {
1843 void (*misc)(struct radeon_device *rdev);
1844 void (*prepare)(struct radeon_device *rdev);
1845 void (*finish)(struct radeon_device *rdev);
1846 void (*init_profile)(struct radeon_device *rdev);
1847 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1848 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1849 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1850 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1851 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1852 int (*get_pcie_lanes)(struct radeon_device *rdev);
1853 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1854 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1855 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1856 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1857 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1858 } pm;
da321c8a
AD		 1859 /* dynamic power management */
1860 struct {
1861 int (*init)(struct radeon_device *rdev);
1862 void (*setup_asic)(struct radeon_device *rdev);
1863 int (*enable)(struct radeon_device *rdev);
914a8987 1864 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1865 void (*disable)(struct radeon_device *rdev);
84dd1928 1866 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1867 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1868 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1869 void (*display_configuration_changed)(struct radeon_device *rdev);
1870 void (*fini)(struct radeon_device *rdev);
1871 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1872 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1873 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1874 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1875 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1876 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1877 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1878 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1879 } dpm;
6f34be50 1880 /* pageflipping */
0f9e006c
AD		 1881 struct {
1882 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1883 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1884 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1885 } pflip;
771fe6b9
JG		 1886};
1887
21f9a437
JG		 1888/*
1889 * Asic structures
1890 */
551ebd83 1891struct r100_asic {
225758d8
JG		 1892 const unsigned *reg_safe_bm;
1893 unsigned reg_safe_bm_size;
1894 u32 hdp_cntl;
551ebd83
DA		 1895};
1896
21f9a437 1897struct r300_asic {
225758d8
JG		 1898 const unsigned *reg_safe_bm;
1899 unsigned reg_safe_bm_size;
1900 u32 resync_scratch;
1901 u32 hdp_cntl;
21f9a437
JG		 1902};
1903
1904struct r600_asic {
225758d8
JG		 1905 unsigned max_pipes;
1906 unsigned max_tile_pipes;
1907 unsigned max_simds;
1908 unsigned max_backends;
1909 unsigned max_gprs;
1910 unsigned max_threads;
1911 unsigned max_stack_entries;
1912 unsigned max_hw_contexts;
1913 unsigned max_gs_threads;
1914 unsigned sx_max_export_size;
1915 unsigned sx_max_export_pos_size;
1916 unsigned sx_max_export_smx_size;
1917 unsigned sq_num_cf_insts;
1918 unsigned tiling_nbanks;
1919 unsigned tiling_npipes;
1920 unsigned tiling_group_size;
e7aeeba6 1921 unsigned tile_config;
e55b9422 1922 unsigned backend_map;
21f9a437
JG		 1923};
1924
1925struct rv770_asic {
225758d8
JG		 1926 unsigned max_pipes;
1927 unsigned max_tile_pipes;
1928 unsigned max_simds;
1929 unsigned max_backends;
1930 unsigned max_gprs;
1931 unsigned max_threads;
1932 unsigned max_stack_entries;
1933 unsigned max_hw_contexts;
1934 unsigned max_gs_threads;
1935 unsigned sx_max_export_size;
1936 unsigned sx_max_export_pos_size;
1937 unsigned sx_max_export_smx_size;
1938 unsigned sq_num_cf_insts;
1939 unsigned sx_num_of_sets;
1940 unsigned sc_prim_fifo_size;
1941 unsigned sc_hiz_tile_fifo_size;
1942 unsigned sc_earlyz_tile_fifo_fize;
1943 unsigned tiling_nbanks;
1944 unsigned tiling_npipes;
1945 unsigned tiling_group_size;
e7aeeba6 1946 unsigned tile_config;
e55b9422 1947 unsigned backend_map;
21f9a437
JG		 1948};
1949
32fcdbf4
AD		 1950struct evergreen_asic {
1951 unsigned num_ses;
1952 unsigned max_pipes;
1953 unsigned max_tile_pipes;
1954 unsigned max_simds;
1955 unsigned max_backends;
1956 unsigned max_gprs;
1957 unsigned max_threads;
1958 unsigned max_stack_entries;
1959 unsigned max_hw_contexts;
1960 unsigned max_gs_threads;
1961 unsigned sx_max_export_size;
1962 unsigned sx_max_export_pos_size;
1963 unsigned sx_max_export_smx_size;
1964 unsigned sq_num_cf_insts;
1965 unsigned sx_num_of_sets;
1966 unsigned sc_prim_fifo_size;
1967 unsigned sc_hiz_tile_fifo_size;
1968 unsigned sc_earlyz_tile_fifo_size;
1969 unsigned tiling_nbanks;
1970 unsigned tiling_npipes;
1971 unsigned tiling_group_size;
e7aeeba6 1972 unsigned tile_config;
e55b9422 1973 unsigned backend_map;
32fcdbf4
AD		 1974};
1975
fecf1d07
AD		 1976struct cayman_asic {
1977 unsigned max_shader_engines;
1978 unsigned max_pipes_per_simd;
1979 unsigned max_tile_pipes;
1980 unsigned max_simds_per_se;
1981 unsigned max_backends_per_se;
1982 unsigned max_texture_channel_caches;
1983 unsigned max_gprs;
1984 unsigned max_threads;
1985 unsigned max_gs_threads;
1986 unsigned max_stack_entries;
1987 unsigned sx_num_of_sets;
1988 unsigned sx_max_export_size;
1989 unsigned sx_max_export_pos_size;
1990 unsigned sx_max_export_smx_size;
1991 unsigned max_hw_contexts;
1992 unsigned sq_num_cf_insts;
1993 unsigned sc_prim_fifo_size;
1994 unsigned sc_hiz_tile_fifo_size;
1995 unsigned sc_earlyz_tile_fifo_size;
1996
1997 unsigned num_shader_engines;
1998 unsigned num_shader_pipes_per_simd;
1999 unsigned num_tile_pipes;
2000 unsigned num_simds_per_se;
2001 unsigned num_backends_per_se;
2002 unsigned backend_disable_mask_per_asic;
2003 unsigned backend_map;
2004 unsigned num_texture_channel_caches;
2005 unsigned mem_max_burst_length_bytes;
2006 unsigned mem_row_size_in_kb;
2007 unsigned shader_engine_tile_size;
2008 unsigned num_gpus;
2009 unsigned multi_gpu_tile_size;
2010
2011 unsigned tile_config;
fecf1d07
AD		 2012};
2013
0a96d72b
AD		 2014struct si_asic {
2015 unsigned max_shader_engines;
0a96d72b 2016 unsigned max_tile_pipes;
1a8ca750
AD		 2017 unsigned max_cu_per_sh;
2018 unsigned max_sh_per_se;
0a96d72b
AD		 2019 unsigned max_backends_per_se;
2020 unsigned max_texture_channel_caches;
2021 unsigned max_gprs;
2022 unsigned max_gs_threads;
2023 unsigned max_hw_contexts;
2024 unsigned sc_prim_fifo_size_frontend;
2025 unsigned sc_prim_fifo_size_backend;
2026 unsigned sc_hiz_tile_fifo_size;
2027 unsigned sc_earlyz_tile_fifo_size;
2028
0a96d72b 2029 unsigned num_tile_pipes;
439a1cff 2030 unsigned backend_enable_mask;
0a96d72b
AD		 2031 unsigned backend_disable_mask_per_asic;
2032 unsigned backend_map;
2033 unsigned num_texture_channel_caches;
2034 unsigned mem_max_burst_length_bytes;
2035 unsigned mem_row_size_in_kb;
2036 unsigned shader_engine_tile_size;
2037 unsigned num_gpus;
2038 unsigned multi_gpu_tile_size;
2039
2040 unsigned tile_config;
64d7b8be 2041 uint32_t tile_mode_array[32];
0a96d72b
AD		 2042};
2043
8cc1a532
AD		 2044struct cik_asic {
2045 unsigned max_shader_engines;
2046 unsigned max_tile_pipes;
2047 unsigned max_cu_per_sh;
2048 unsigned max_sh_per_se;
2049 unsigned max_backends_per_se;
2050 unsigned max_texture_channel_caches;
2051 unsigned max_gprs;
2052 unsigned max_gs_threads;
2053 unsigned max_hw_contexts;
2054 unsigned sc_prim_fifo_size_frontend;
2055 unsigned sc_prim_fifo_size_backend;
2056 unsigned sc_hiz_tile_fifo_size;
2057 unsigned sc_earlyz_tile_fifo_size;
2058
2059 unsigned num_tile_pipes;
439a1cff 2060 unsigned backend_enable_mask;
8cc1a532
AD		 2061 unsigned backend_disable_mask_per_asic;
2062 unsigned backend_map;
2063 unsigned num_texture_channel_caches;
2064 unsigned mem_max_burst_length_bytes;
2065 unsigned mem_row_size_in_kb;
2066 unsigned shader_engine_tile_size;
2067 unsigned num_gpus;
2068 unsigned multi_gpu_tile_size;
2069
2070 unsigned tile_config;
39aee490 2071 uint32_t tile_mode_array[32];
32f79a8a 2072 uint32_t macrotile_mode_array[16];
8cc1a532
AD		 2073};
2074
068a117c
JG		 2075union radeon_asic_config {
2076 struct r300_asic r300;
551ebd83 2077 struct r100_asic r100;
3ce0a23d
JG		 2078 struct r600_asic r600;
2079 struct rv770_asic rv770;
32fcdbf4 2080 struct evergreen_asic evergreen;
fecf1d07 2081 struct cayman_asic cayman;
0a96d72b 2082 struct si_asic si;
8cc1a532 2083 struct cik_asic cik;
068a117c
JG		 2084};
2085
0a10c851
DV		 2086/*
2087 * asic initizalization from radeon_asic.c
2088 */
2089void radeon_agp_disable(struct radeon_device *rdev);
2090int radeon_asic_init(struct radeon_device *rdev);
2091
771fe6b9
JG		 2092
2093/*
2094 * IOCTL.
2095 */
2096int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2097 struct drm_file *filp);
2098int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2099 struct drm_file *filp);
2100int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2101 struct drm_file *file_priv);
2102int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2103 struct drm_file *file_priv);
2104int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2105 struct drm_file *file_priv);
2106int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2107 struct drm_file *file_priv);
2108int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2109 struct drm_file *filp);
2110int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2111 struct drm_file *filp);
2112int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2113 struct drm_file *filp);
2114int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2115 struct drm_file *filp);
721604a1
JG		 2116int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2117 struct drm_file *filp);
771fe6b9 2118int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2119int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2120 struct drm_file *filp);
2121int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2122 struct drm_file *filp);
771fe6b9 2123
16cdf04d
AD		 2124/* VRAM scratch page for HDP bug, default vram page */
2125struct r600_vram_scratch {
87cbf8f2
AD		 2126 struct radeon_bo *robj;
2127 volatile uint32_t *ptr;
16cdf04d 2128 u64 gpu_addr;
87cbf8f2 2129};
771fe6b9 2130
fd64ca8a
LT		 2131/*
2132 * ACPI
2133 */
2134struct radeon_atif_notification_cfg {
2135 bool enabled;
2136 int command_code;
2137};
2138
2139struct radeon_atif_notifications {
2140 bool display_switch;
2141 bool expansion_mode_change;
2142 bool thermal_state;
2143 bool forced_power_state;
2144 bool system_power_state;
2145 bool display_conf_change;
2146 bool px_gfx_switch;
2147 bool brightness_change;
2148 bool dgpu_display_event;
2149};
2150
2151struct radeon_atif_functions {
2152 bool system_params;
2153 bool sbios_requests;
2154 bool select_active_disp;
2155 bool lid_state;
2156 bool get_tv_standard;
2157 bool set_tv_standard;
2158 bool get_panel_expansion_mode;
2159 bool set_panel_expansion_mode;
2160 bool temperature_change;
2161 bool graphics_device_types;
2162};
2163
2164struct radeon_atif {
2165 struct radeon_atif_notifications notifications;
2166 struct radeon_atif_functions functions;
2167 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2168 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2169};
7a1619b9 2170
e3a15920
AD		 2171struct radeon_atcs_functions {
2172 bool get_ext_state;
2173 bool pcie_perf_req;
2174 bool pcie_dev_rdy;
2175 bool pcie_bus_width;
2176};
2177
2178struct radeon_atcs {
2179 struct radeon_atcs_functions functions;
2180};
2181
771fe6b9
JG		 2182/*
2183 * Core structure, functions and helpers.
2184 */
2185typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2186typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2187
2188struct radeon_device {
9f022ddf 2189 struct device *dev;
771fe6b9
JG		 2190 struct drm_device *ddev;
2191 struct pci_dev *pdev;
dee53e7f 2192 struct rw_semaphore exclusive_lock;
771fe6b9 2193 /* ASIC */
068a117c 2194 union radeon_asic_config config;
771fe6b9
JG		 2195 enum radeon_family family;
2196 unsigned long flags;
2197 int usec_timeout;
2198 enum radeon_pll_errata pll_errata;
2199 int num_gb_pipes;
f779b3e5 2200 int num_z_pipes;
771fe6b9
JG		 2201 int disp_priority;
2202 /* BIOS */
2203 uint8_t *bios;
2204 bool is_atom_bios;
2205 uint16_t bios_header_start;
4c788679 2206 struct radeon_bo *stollen_vga_memory;
771fe6b9 2207 /* Register mmio */
4c9bc75c
DA		 2208 resource_size_t rmmio_base;
2209 resource_size_t rmmio_size;
2c385151
DV		 2210 /* protects concurrent MM_INDEX/DATA based register access */
2211 spinlock_t mmio_idx_lock;
fe78118c
AD		 2212 /* protects concurrent SMC based register access */
2213 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2214 /* protects concurrent PLL register access */
2215 spinlock_t pll_idx_lock;
2216 /* protects concurrent MC register access */
2217 spinlock_t mc_idx_lock;
2218 /* protects concurrent PCIE register access */
2219 spinlock_t pcie_idx_lock;
2220 /* protects concurrent PCIE_PORT register access */
2221 spinlock_t pciep_idx_lock;
2222 /* protects concurrent PIF register access */
2223 spinlock_t pif_idx_lock;
2224 /* protects concurrent CG register access */
2225 spinlock_t cg_idx_lock;
2226 /* protects concurrent UVD register access */
2227 spinlock_t uvd_idx_lock;
2228 /* protects concurrent RCU register access */
2229 spinlock_t rcu_idx_lock;
2230 /* protects concurrent DIDT register access */
2231 spinlock_t didt_idx_lock;
2232 /* protects concurrent ENDPOINT (audio) register access */
2233 spinlock_t end_idx_lock;
a0533fbf 2234 void __iomem *rmmio;
771fe6b9
JG		 2235 radeon_rreg_t mc_rreg;
2236 radeon_wreg_t mc_wreg;
2237 radeon_rreg_t pll_rreg;
2238 radeon_wreg_t pll_wreg;
de1b2898 2239 uint32_t pcie_reg_mask;
771fe6b9
JG		 2240 radeon_rreg_t pciep_rreg;
2241 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2242 /* io port */
2243 void __iomem *rio_mem;
2244 resource_size_t rio_mem_size;
771fe6b9
JG		 2245 struct radeon_clock clock;
2246 struct radeon_mc mc;
2247 struct radeon_gart gart;
2248 struct radeon_mode_info mode_info;
2249 struct radeon_scratch scratch;
75efdee1 2250 struct radeon_doorbell doorbell;
771fe6b9 2251 struct radeon_mman mman;
7465280c 2252 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2253 wait_queue_head_t fence_queue;
d6999bc7 2254 struct mutex ring_lock;
e32eb50d 2255 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2256 bool ib_pool_ready;
2257 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2258 struct radeon_irq irq;
2259 struct radeon_asic *asic;
2260 struct radeon_gem gem;
c93bb85b 2261 struct radeon_pm pm;
f2ba57b5 2262 struct radeon_uvd uvd;
d93f7937 2263 struct radeon_vce vce;
f657c2a7 2264 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2265 struct radeon_wb wb;
3ce0a23d 2266 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2267 bool shutdown;
2268 bool suspend;
ad49f501 2269 bool need_dma32;
733289c2 2270 bool accel_working;
a0a53aa8 2271 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2272 bool needs_reset;
e024e110 2273 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2274 const struct firmware *me_fw; /* all family ME firmware */
2275 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2276 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2277 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2278 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2279 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2280 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2281 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2282 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2283 const struct firmware *vce_fw; /* VCE firmware */
16cdf04d 2284 struct r600_vram_scratch vram_scratch;
3e5cb98d 2285 int msi_enabled; /* msi enabled */
d8f60cfc 2286 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2287 struct radeon_rlc rlc;
963e81f9 2288 struct radeon_mec mec;
d4877cf2 2289 struct work_struct hotplug_work;
f122c610 2290 struct work_struct audio_work;
8f61b34c 2291 struct work_struct reset_work;
18917b60 2292 int num_crtc; /* number of crtcs */
40bacf16 2293 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2294 bool has_uvd;
b530602f 2295 struct r600_audio audio; /* audio stuff */
ce8f5370 2296 struct notifier_block acpi_nb;
9eba4a93 2297 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2298 struct drm_file *hyperz_filp;
9eba4a93 2299 struct drm_file *cmask_filp;
f376b94f
AD		 2300 /* i2c buses */
2301 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2302 /* debugfs */
2303 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2304 unsigned debugfs_count;
721604a1
JG		 2305 /* virtual memory */
2306 struct radeon_vm_manager vm_manager;
6759a0a7 2307 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2308 /* ACPI interface */
2309 struct radeon_atif atif;
e3a15920 2310 struct radeon_atcs atcs;
f61d5b46
AD		 2311 /* srbm instance registers */
2312 struct mutex srbm_mutex;
64d8a728
AD		 2313 /* clock, powergating flags */
2314 u32 cg_flags;
2315 u32 pg_flags;
10ebc0bc
DA		 2316
2317 struct dev_pm_domain vga_pm_domain;
2318 bool have_disp_power_ref;
771fe6b9
JG		 2319};
2320
2321int radeon_device_init(struct radeon_device *rdev,
2322 struct drm_device *ddev,
2323 struct pci_dev *pdev,
2324 uint32_t flags);
2325void radeon_device_fini(struct radeon_device *rdev);
2326int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2327
2ef9bdfe
DV		 2328uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2329 bool always_indirect);
2330void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2331 bool always_indirect);
6fcbef7a
AK		 2332u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2333void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2334
d5754ab8
AL		 2335u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2336void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2337
4c788679
JG		 2338/*
2339 * Cast helper
2340 */
2341#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2342
2343/*
2344 * Registers read & write functions.
2345 */
a0533fbf
BH		 2346#define RREG8(reg) readb((rdev->rmmio) + (reg))
2347#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2348#define RREG16(reg) readw((rdev->rmmio) + (reg))
2349#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2350#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2351#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2352#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2353#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2354#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2355#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2356#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2357#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2358#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2359#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2360#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2361#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2362#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2363#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2364#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2365#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2366#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2367#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2368#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2369#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2370#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2371#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2372#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2373#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2374#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2375#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2376#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2377#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2378#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2379#define WREG32_P(reg, val, mask) \
2380 do { \
2381 uint32_t tmp_ = RREG32(reg); \
2382 tmp_ &= (mask); \
2383 tmp_ |= ((val) & ~(mask)); \
2384 WREG32(reg, tmp_); \
2385 } while (0)
d5169fc4 2386#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2387#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2388#define WREG32_PLL_P(reg, val, mask) \
2389 do { \
2390 uint32_t tmp_ = RREG32_PLL(reg); \
2391 tmp_ &= (mask); \
2392 tmp_ |= ((val) & ~(mask)); \
2393 WREG32_PLL(reg, tmp_); \
2394 } while (0)
2ef9bdfe 2395#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2396#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2397#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2398
d5754ab8
AL		 2399#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2400#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2401
de1b2898
DA		 2402/*
2403 * Indirect registers accessor
2404 */
2405static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2406{
0a5b7b0b 2407 unsigned long flags;
de1b2898
DA		 2408 uint32_t r;
2409
0a5b7b0b 2410 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2411 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2412 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2413 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2414 return r;
2415}
2416
2417static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2418{
0a5b7b0b
AD		 2419 unsigned long flags;
2420
2421 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2422 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2423 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2424 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2425}
2426
1d5d0c34
AD		 2427static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2428{
fe78118c 2429 unsigned long flags;
1d5d0c34
AD		 2430 u32 r;
2431
fe78118c 2432 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2433 WREG32(TN_SMC_IND_INDEX_0, (reg));
2434 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2435 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2436 return r;
2437}
2438
2439static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2440{
fe78118c
AD		 2441 unsigned long flags;
2442
2443 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2444 WREG32(TN_SMC_IND_INDEX_0, (reg));
2445 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2446 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2447}
2448
ff82bbc4
AD		 2449static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2450{
0a5b7b0b 2451 unsigned long flags;
ff82bbc4
AD		 2452 u32 r;
2453
0a5b7b0b 2454 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2455 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2456 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2457 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2458 return r;
2459}
2460
2461static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2462{
0a5b7b0b
AD		 2463 unsigned long flags;
2464
2465 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2466 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2467 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2468 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2469}
2470
46f9564a
AD		 2471static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2472{
0a5b7b0b 2473 unsigned long flags;
46f9564a
AD		 2474 u32 r;
2475
0a5b7b0b 2476 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2477 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2478 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2479 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2480 return r;
2481}
2482
2483static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2484{
0a5b7b0b
AD		 2485 unsigned long flags;
2486
2487 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2488 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2489 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2490 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2491}
2492
792edd69
AD		 2493static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2494{
0a5b7b0b 2495 unsigned long flags;
792edd69
AD		 2496 u32 r;
2497
0a5b7b0b 2498 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2499 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2500 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2501 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2502 return r;
2503}
2504
2505static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2506{
0a5b7b0b
AD		 2507 unsigned long flags;
2508
2509 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2510 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2511 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2512 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2513}
2514
2515static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2516{
0a5b7b0b 2517 unsigned long flags;
792edd69
AD		 2518 u32 r;
2519
0a5b7b0b 2520 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2521 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2522 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2523 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2524 return r;
2525}
2526
2527static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2528{
0a5b7b0b
AD		 2529 unsigned long flags;
2530
2531 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2532 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2533 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2534 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2535}
2536
93656cdd
AD		 2537static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2538{
0a5b7b0b 2539 unsigned long flags;
93656cdd
AD		 2540 u32 r;
2541
0a5b7b0b 2542 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2543 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2544 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2545 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2546 return r;
2547}
2548
2549static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2550{
0a5b7b0b
AD		 2551 unsigned long flags;
2552
2553 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2554 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2555 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2556 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2557}
2558
1d58234d
AD		 2559
2560static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2561{
0a5b7b0b 2562 unsigned long flags;
1d58234d
AD		 2563 u32 r;
2564
0a5b7b0b 2565 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2566 WREG32(CIK_DIDT_IND_INDEX, (reg));
2567 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2568 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2569 return r;
2570}
2571
2572static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2573{
0a5b7b0b
AD		 2574 unsigned long flags;
2575
2576 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2577 WREG32(CIK_DIDT_IND_INDEX, (reg));
2578 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2579 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2580}
2581
771fe6b9
JG		 2582void r100_pll_errata_after_index(struct radeon_device *rdev);
2583
2584
2585/*
2586 * ASICs helpers.
2587 */
b995e433
DA		 2588#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2589 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2590#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2591 (rdev->family == CHIP_RV200) || \
2592 (rdev->family == CHIP_RS100) || \
2593 (rdev->family == CHIP_RS200) || \
2594 (rdev->family == CHIP_RV250) || \
2595 (rdev->family == CHIP_RV280) || \
2596 (rdev->family == CHIP_RS300))
2597#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2598 (rdev->family == CHIP_RV350) || \
2599 (rdev->family == CHIP_R350) || \
2600 (rdev->family == CHIP_RV380) || \
2601 (rdev->family == CHIP_R420) || \
2602 (rdev->family == CHIP_R423) || \
2603 (rdev->family == CHIP_RV410) || \
2604 (rdev->family == CHIP_RS400) || \
2605 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2606#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2607 (rdev->ddev->pdev->device == 0x9443) || \
2608 (rdev->ddev->pdev->device == 0x944B) || \
2609 (rdev->ddev->pdev->device == 0x9506) || \
2610 (rdev->ddev->pdev->device == 0x9509) || \
2611 (rdev->ddev->pdev->device == 0x950F) || \
2612 (rdev->ddev->pdev->device == 0x689C) || \
2613 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2614#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2615#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2616 (rdev->family == CHIP_RS690) || \
2617 (rdev->family == CHIP_RS740) || \
2618 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2619#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2620#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2621#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2622#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2623 (rdev->flags & RADEON_IS_IGP))
1fe18305 2624#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2625#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2626#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2627 (rdev->flags & RADEON_IS_IGP))
624d3524 2628#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2629#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2630#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2631
dc50ba7f
AD		 2632#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2633 (rdev->ddev->pdev->device == 0x6850) || \
2634 (rdev->ddev->pdev->device == 0x6858) || \
2635 (rdev->ddev->pdev->device == 0x6859) || \
2636 (rdev->ddev->pdev->device == 0x6840) || \
2637 (rdev->ddev->pdev->device == 0x6841) || \
2638 (rdev->ddev->pdev->device == 0x6842) || \
2639 (rdev->ddev->pdev->device == 0x6843))
2640
771fe6b9
JG		 2641/*
2642 * BIOS helpers.
2643 */
2644#define RBIOS8(i) (rdev->bios[i])
2645#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2646#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2647
2648int radeon_combios_init(struct radeon_device *rdev);
2649void radeon_combios_fini(struct radeon_device *rdev);
2650int radeon_atombios_init(struct radeon_device *rdev);
2651void radeon_atombios_fini(struct radeon_device *rdev);
2652
2653
2654/*
2655 * RING helpers.
2656 */
ce580fab 2657#if DRM_DEBUG_CODE == 0
e32eb50d 2658static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2659{
e32eb50d
CK		 2660 ring->ring[ring->wptr++] = v;
2661 ring->wptr &= ring->ptr_mask;
2662 ring->count_dw--;
2663 ring->ring_free_dw--;
771fe6b9 2664}
ce580fab
AK		 2665#else
2666/* With debugging this is just too big to inline */
e32eb50d 2667void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2668#endif
771fe6b9
JG		 2669
2670/*
2671 * ASICs macro.
2672 */
068a117c 2673#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2674#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2675#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2676#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2677#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2678#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2679#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2680#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2681#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2682#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2683#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2684#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2685#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2686#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2687#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2688#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2689#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2690#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2691#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2692#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2693#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2694#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2695#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2696#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2697#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2698#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2699#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2700#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2701#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2702#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2703#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2704#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2705#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2706#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2707#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2708#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2709#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2710#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2711#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2712#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2713#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2714#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2715#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2716#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2717#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2718#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2719#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2720#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2721#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2722#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2723#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2724#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2725#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2726#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2727#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2728#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2729#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2730#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2731#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2732#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2733#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2734#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2735#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2736#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2737#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2738#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2739#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2740#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2741#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2742#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2743#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2744#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2745#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2746#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2747#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2748#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2749#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2750#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2751#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2752#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2753#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2754#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2755#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2756#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2757#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2758
6cf8a3f5 2759/* Common functions */
700a0cc0 2760/* AGP */
90aca4d2 2761extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2762extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2763extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2764extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2765extern int radeon_modeset_init(struct radeon_device *rdev);
2766extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2767extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2768extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2769extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2770extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2771extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2772extern void radeon_wb_fini(struct radeon_device *rdev);
2773extern int radeon_wb_init(struct radeon_device *rdev);
2774extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2775extern void radeon_surface_init(struct radeon_device *rdev);
2776extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2777extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2778extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2779extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2780extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2781extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2782extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2783extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2784extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2785extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2786extern void radeon_program_register_sequence(struct radeon_device *rdev,
2787 const u32 *registers,
2788 const u32 array_size);
6cf8a3f5 2789
721604a1
JG		 2790/*
2791 * vm
2792 */
2793int radeon_vm_manager_init(struct radeon_device *rdev);
2794void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2795void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2796void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2797int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2798void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2799struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2800 struct radeon_vm *vm, int ring);
2801void radeon_vm_fence(struct radeon_device *rdev,
2802 struct radeon_vm *vm,
2803 struct radeon_fence *fence);
dce34bfd 2804uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
9c57a6bd
CK		 2805int radeon_vm_bo_update(struct radeon_device *rdev,
2806 struct radeon_vm *vm,
2807 struct radeon_bo *bo,
2808 struct ttm_mem_reg *mem);
721604a1
JG		 2809void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2810 struct radeon_bo *bo);
421ca7ab
CK		 2811struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2812 struct radeon_bo *bo);
e971bd5e
CK		 2813struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2814 struct radeon_vm *vm,
2815 struct radeon_bo *bo);
2816int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2817 struct radeon_bo_va *bo_va,
2818 uint64_t offset,
2819 uint32_t flags);
721604a1 2820int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2821 struct radeon_bo_va *bo_va);
721604a1 2822
f122c610
AD		 2823/* audio */
2824void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2825struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2826struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
721604a1 2827
16cdf04d
AD		 2828/*
2829 * R600 vram scratch functions
2830 */
2831int r600_vram_scratch_init(struct radeon_device *rdev);
2832void r600_vram_scratch_fini(struct radeon_device *rdev);
2833
285484e2
JG		 2834/*
2835 * r600 cs checking helper
2836 */
2837unsigned r600_mip_minify(unsigned size, unsigned level);
2838bool r600_fmt_is_valid_color(u32 format);
2839bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2840int r600_fmt_get_blocksize(u32 format);
2841int r600_fmt_get_nblocksx(u32 format, u32 w);
2842int r600_fmt_get_nblocksy(u32 format, u32 h);
2843
3574dda4
DV		 2844/*
2845 * r600 functions used by radeon_encoder.c
2846 */
1b688d08
RM		 2847struct radeon_hdmi_acr {
2848 u32 clock;
2849
2850 int n_32khz;
2851 int cts_32khz;
2852
2853 int n_44_1khz;
2854 int cts_44_1khz;
2855
2856 int n_48khz;
2857 int cts_48khz;
2858
2859};
2860
e55d3e6c
RM		 2861extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2862
416a2bd2
AD		 2863extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2864 u32 tiling_pipe_num,
2865 u32 max_rb_num,
2866 u32 total_max_rb_num,
2867 u32 enabled_rb_mask);
fe251e2f 2868
e55d3e6c
RM		 2869/*
2870 * evergreen functions used by radeon_encoder.c
2871 */
2872
0af62b01 2873extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2874extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2875
c4917074
AD		 2876/* radeon_acpi.c */
2877#if defined(CONFIG_ACPI)
2878extern int radeon_acpi_init(struct radeon_device *rdev);
2879extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2880extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2881extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2882 u8 perf_req, bool advertise);
dc50ba7f 2883extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2884#else
2885static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2886static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2887#endif
d7a2952f 2888
c38f34b5
IH		 2889int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2890 struct radeon_cs_packet *pkt,
2891 unsigned idx);
9ffb7a6d 2892bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2893void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2894 struct radeon_cs_packet *pkt);
e9716993
IH		 2895int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2896 struct radeon_cs_reloc **cs_reloc,
2897 int nomm);
40592a17
IH		 2898int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2899 uint32_t *vline_start_end,
2900 uint32_t *vline_status);
c38f34b5 2901
4c788679
JG		 2902#include "radeon_object.h"
2903
771fe6b9 2904#endif
Linux 6.x block layer and io_uring tree(s)