Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
60063497 | 63 | #include <linux/atomic.h> |
771fe6b9 JG |
64 | #include <linux/wait.h> |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
147666fb | 72 | #include <ttm/ttm_execbuf_util.h> |
4c788679 | 73 | |
c2142715 | 74 | #include "radeon_family.h" |
771fe6b9 JG |
75 | #include "radeon_mode.h" |
76 | #include "radeon_reg.h" | |
771fe6b9 JG |
77 | |
78 | /* | |
79 | * Modules parameters. | |
80 | */ | |
81 | extern int radeon_no_wb; | |
82 | extern int radeon_modeset; | |
83 | extern int radeon_dynclks; | |
84 | extern int radeon_r4xx_atom; | |
85 | extern int radeon_agpmode; | |
86 | extern int radeon_vram_limit; | |
87 | extern int radeon_gart_size; | |
88 | extern int radeon_benchmarking; | |
ecc0b326 | 89 | extern int radeon_testing; |
771fe6b9 | 90 | extern int radeon_connector_table; |
4ce001ab | 91 | extern int radeon_tv; |
dafc3bd5 | 92 | extern int radeon_audio; |
f46c0120 | 93 | extern int radeon_disp_priority; |
e2b0a8e1 | 94 | extern int radeon_hw_i2c; |
d42dd579 | 95 | extern int radeon_pcie_gen2; |
a18cee15 | 96 | extern int radeon_msi; |
3368ff0c | 97 | extern int radeon_lockup_timeout; |
771fe6b9 JG |
98 | |
99 | /* | |
100 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
101 | * symbol; | |
102 | */ | |
bb635567 JG |
103 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
104 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
e821767b | 105 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
bb635567 JG |
106 | #define RADEON_IB_POOL_SIZE 16 |
107 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 | |
108 | #define RADEONFB_CONN_LIMIT 4 | |
109 | #define RADEON_BIOS_NUM_SCRATCH 8 | |
771fe6b9 | 110 | |
1b37078b | 111 | /* max number of rings */ |
bb635567 JG |
112 | #define RADEON_NUM_RINGS 3 |
113 | ||
114 | /* fence seq are set to this number when signaled */ | |
115 | #define RADEON_FENCE_SIGNALED_SEQ 0LL | |
1b37078b AD |
116 | |
117 | /* internal ring indices */ | |
118 | /* r1xx+ has gfx CP ring */ | |
bb635567 | 119 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
1b37078b AD |
120 | |
121 | /* cayman has 2 compute CP rings */ | |
bb635567 JG |
122 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
123 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 | |
1b37078b | 124 | |
721604a1 | 125 | /* hardcode those limit for now */ |
ca19f21e | 126 | #define RADEON_VA_IB_OFFSET (1 << 20) |
bb635567 JG |
127 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
128 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) | |
721604a1 | 129 | |
771fe6b9 JG |
130 | /* |
131 | * Errata workarounds. | |
132 | */ | |
133 | enum radeon_pll_errata { | |
134 | CHIP_ERRATA_R300_CG = 0x00000001, | |
135 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
136 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
137 | }; | |
138 | ||
139 | ||
140 | struct radeon_device; | |
141 | ||
142 | ||
143 | /* | |
144 | * BIOS. | |
145 | */ | |
146 | bool radeon_get_bios(struct radeon_device *rdev); | |
147 | ||
148 | /* | |
3ce0a23d | 149 | * Dummy page |
771fe6b9 | 150 | */ |
3ce0a23d JG |
151 | struct radeon_dummy_page { |
152 | struct page *page; | |
153 | dma_addr_t addr; | |
154 | }; | |
155 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
156 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
157 | ||
771fe6b9 | 158 | |
3ce0a23d JG |
159 | /* |
160 | * Clocks | |
161 | */ | |
771fe6b9 JG |
162 | struct radeon_clock { |
163 | struct radeon_pll p1pll; | |
164 | struct radeon_pll p2pll; | |
bcc1c2a1 | 165 | struct radeon_pll dcpll; |
771fe6b9 JG |
166 | struct radeon_pll spll; |
167 | struct radeon_pll mpll; | |
168 | /* 10 Khz units */ | |
169 | uint32_t default_mclk; | |
170 | uint32_t default_sclk; | |
bcc1c2a1 AD |
171 | uint32_t default_dispclk; |
172 | uint32_t dp_extclk; | |
b20f9bef | 173 | uint32_t max_pixel_clock; |
771fe6b9 JG |
174 | }; |
175 | ||
7433874e RM |
176 | /* |
177 | * Power management | |
178 | */ | |
179 | int radeon_pm_init(struct radeon_device *rdev); | |
29fb52ca | 180 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 181 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
ce8f5370 AD |
182 | void radeon_pm_suspend(struct radeon_device *rdev); |
183 | void radeon_pm_resume(struct radeon_device *rdev); | |
56278a8e AD |
184 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
185 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
8a83ec5e | 186 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
f892034a | 187 | void rs690_pm_info(struct radeon_device *rdev); |
20d391d7 AD |
188 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
189 | extern int rv770_get_temp(struct radeon_device *rdev); | |
190 | extern int evergreen_get_temp(struct radeon_device *rdev); | |
191 | extern int sumo_get_temp(struct radeon_device *rdev); | |
1bd47d2e | 192 | extern int si_get_temp(struct radeon_device *rdev); |
285484e2 JG |
193 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
194 | unsigned *bankh, unsigned *mtaspect, | |
195 | unsigned *tile_split); | |
3ce0a23d | 196 | |
771fe6b9 JG |
197 | /* |
198 | * Fences. | |
199 | */ | |
200 | struct radeon_fence_driver { | |
201 | uint32_t scratch_reg; | |
30eb77f4 JG |
202 | uint64_t gpu_addr; |
203 | volatile uint32_t *cpu_addr; | |
68e250b7 CK |
204 | /* sync_seq is protected by ring emission lock */ |
205 | uint64_t sync_seq[RADEON_NUM_RINGS]; | |
bb635567 | 206 | atomic64_t last_seq; |
36abacae | 207 | unsigned long last_activity; |
0a0c7596 | 208 | bool initialized; |
771fe6b9 JG |
209 | }; |
210 | ||
211 | struct radeon_fence { | |
212 | struct radeon_device *rdev; | |
213 | struct kref kref; | |
771fe6b9 | 214 | /* protected by radeon_fence.lock */ |
bb635567 | 215 | uint64_t seq; |
7465280c | 216 | /* RB, DMA, etc. */ |
bb635567 | 217 | unsigned ring; |
771fe6b9 JG |
218 | }; |
219 | ||
30eb77f4 JG |
220 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
221 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
771fe6b9 | 222 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
876dc9f3 | 223 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
7465280c | 224 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
771fe6b9 JG |
225 | bool radeon_fence_signaled(struct radeon_fence *fence); |
226 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
8a47cc9e | 227 | int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); |
7ecc45e3 | 228 | void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); |
0085c950 JG |
229 | int radeon_fence_wait_any(struct radeon_device *rdev, |
230 | struct radeon_fence **fences, | |
231 | bool intr); | |
771fe6b9 JG |
232 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
233 | void radeon_fence_unref(struct radeon_fence **fence); | |
3b7a2b24 | 234 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
68e250b7 CK |
235 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
236 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); | |
237 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, | |
238 | struct radeon_fence *b) | |
239 | { | |
240 | if (!a) { | |
241 | return b; | |
242 | } | |
243 | ||
244 | if (!b) { | |
245 | return a; | |
246 | } | |
247 | ||
248 | BUG_ON(a->ring != b->ring); | |
249 | ||
250 | if (a->seq > b->seq) { | |
251 | return a; | |
252 | } else { | |
253 | return b; | |
254 | } | |
255 | } | |
771fe6b9 | 256 | |
ee60e29f CK |
257 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
258 | struct radeon_fence *b) | |
259 | { | |
260 | if (!a) { | |
261 | return false; | |
262 | } | |
263 | ||
264 | if (!b) { | |
265 | return true; | |
266 | } | |
267 | ||
268 | BUG_ON(a->ring != b->ring); | |
269 | ||
270 | return a->seq < b->seq; | |
271 | } | |
272 | ||
e024e110 DA |
273 | /* |
274 | * Tiling registers | |
275 | */ | |
276 | struct radeon_surface_reg { | |
4c788679 | 277 | struct radeon_bo *bo; |
e024e110 DA |
278 | }; |
279 | ||
280 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
281 | |
282 | /* | |
4c788679 | 283 | * TTM. |
771fe6b9 | 284 | */ |
4c788679 JG |
285 | struct radeon_mman { |
286 | struct ttm_bo_global_ref bo_global_ref; | |
ba4420c2 | 287 | struct drm_global_reference mem_global_ref; |
4c788679 | 288 | struct ttm_bo_device bdev; |
0a0c7596 JG |
289 | bool mem_global_referenced; |
290 | bool initialized; | |
4c788679 JG |
291 | }; |
292 | ||
721604a1 JG |
293 | /* bo virtual address in a specific vm */ |
294 | struct radeon_bo_va { | |
e971bd5e | 295 | /* protected by bo being reserved */ |
721604a1 | 296 | struct list_head bo_list; |
721604a1 JG |
297 | uint64_t soffset; |
298 | uint64_t eoffset; | |
299 | uint32_t flags; | |
300 | bool valid; | |
e971bd5e CK |
301 | unsigned ref_count; |
302 | ||
303 | /* protected by vm mutex */ | |
304 | struct list_head vm_list; | |
305 | ||
306 | /* constant after initialization */ | |
307 | struct radeon_vm *vm; | |
308 | struct radeon_bo *bo; | |
721604a1 JG |
309 | }; |
310 | ||
4c788679 JG |
311 | struct radeon_bo { |
312 | /* Protected by gem.mutex */ | |
313 | struct list_head list; | |
314 | /* Protected by tbo.reserved */ | |
312ea8da JG |
315 | u32 placements[3]; |
316 | struct ttm_placement placement; | |
4c788679 JG |
317 | struct ttm_buffer_object tbo; |
318 | struct ttm_bo_kmap_obj kmap; | |
319 | unsigned pin_count; | |
320 | void *kptr; | |
321 | u32 tiling_flags; | |
322 | u32 pitch; | |
323 | int surface_reg; | |
721604a1 JG |
324 | /* list of all virtual address to which this bo |
325 | * is associated to | |
326 | */ | |
327 | struct list_head va; | |
4c788679 JG |
328 | /* Constant after initialization */ |
329 | struct radeon_device *rdev; | |
441921d5 | 330 | struct drm_gem_object gem_base; |
63bc620b DA |
331 | |
332 | struct ttm_bo_kmap_obj dma_buf_vmap; | |
333 | int vmapping_count; | |
4c788679 | 334 | }; |
7e4d15d9 | 335 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
771fe6b9 | 336 | |
4c788679 | 337 | struct radeon_bo_list { |
147666fb | 338 | struct ttm_validate_buffer tv; |
4c788679 | 339 | struct radeon_bo *bo; |
771fe6b9 JG |
340 | uint64_t gpu_offset; |
341 | unsigned rdomain; | |
342 | unsigned wdomain; | |
4c788679 | 343 | u32 tiling_flags; |
771fe6b9 JG |
344 | }; |
345 | ||
b15ba512 JG |
346 | /* sub-allocation manager, it has to be protected by another lock. |
347 | * By conception this is an helper for other part of the driver | |
348 | * like the indirect buffer or semaphore, which both have their | |
349 | * locking. | |
350 | * | |
351 | * Principe is simple, we keep a list of sub allocation in offset | |
352 | * order (first entry has offset == 0, last entry has the highest | |
353 | * offset). | |
354 | * | |
355 | * When allocating new object we first check if there is room at | |
356 | * the end total_size - (last_object_offset + last_object_size) >= | |
357 | * alloc_size. If so we allocate new object there. | |
358 | * | |
359 | * When there is not enough room at the end, we start waiting for | |
360 | * each sub object until we reach object_offset+object_size >= | |
361 | * alloc_size, this object then become the sub object we return. | |
362 | * | |
363 | * Alignment can't be bigger than page size. | |
364 | * | |
365 | * Hole are not considered for allocation to keep things simple. | |
366 | * Assumption is that there won't be hole (all object on same | |
367 | * alignment). | |
368 | */ | |
369 | struct radeon_sa_manager { | |
bfb38d35 | 370 | wait_queue_head_t wq; |
b15ba512 | 371 | struct radeon_bo *bo; |
c3b7fe8b CK |
372 | struct list_head *hole; |
373 | struct list_head flist[RADEON_NUM_RINGS]; | |
374 | struct list_head olist; | |
b15ba512 JG |
375 | unsigned size; |
376 | uint64_t gpu_addr; | |
377 | void *cpu_ptr; | |
378 | uint32_t domain; | |
379 | }; | |
380 | ||
381 | struct radeon_sa_bo; | |
382 | ||
383 | /* sub-allocation buffer */ | |
384 | struct radeon_sa_bo { | |
c3b7fe8b CK |
385 | struct list_head olist; |
386 | struct list_head flist; | |
b15ba512 | 387 | struct radeon_sa_manager *manager; |
e6661a96 CK |
388 | unsigned soffset; |
389 | unsigned eoffset; | |
557017a0 | 390 | struct radeon_fence *fence; |
b15ba512 JG |
391 | }; |
392 | ||
771fe6b9 JG |
393 | /* |
394 | * GEM objects. | |
395 | */ | |
396 | struct radeon_gem { | |
4c788679 | 397 | struct mutex mutex; |
771fe6b9 JG |
398 | struct list_head objects; |
399 | }; | |
400 | ||
401 | int radeon_gem_init(struct radeon_device *rdev); | |
402 | void radeon_gem_fini(struct radeon_device *rdev); | |
403 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
404 | int alignment, int initial_domain, |
405 | bool discardable, bool kernel, | |
406 | struct drm_gem_object **obj); | |
771fe6b9 | 407 | |
ff72145b DA |
408 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
409 | struct drm_device *dev, | |
410 | struct drm_mode_create_dumb *args); | |
411 | int radeon_mode_dumb_mmap(struct drm_file *filp, | |
412 | struct drm_device *dev, | |
413 | uint32_t handle, uint64_t *offset_p); | |
414 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, | |
415 | struct drm_device *dev, | |
416 | uint32_t handle); | |
771fe6b9 | 417 | |
c1341e52 JG |
418 | /* |
419 | * Semaphores. | |
420 | */ | |
c1341e52 JG |
421 | /* everything here is constant */ |
422 | struct radeon_semaphore { | |
a8c05940 JG |
423 | struct radeon_sa_bo *sa_bo; |
424 | signed waiters; | |
c1341e52 | 425 | uint64_t gpu_addr; |
c1341e52 JG |
426 | }; |
427 | ||
c1341e52 JG |
428 | int radeon_semaphore_create(struct radeon_device *rdev, |
429 | struct radeon_semaphore **semaphore); | |
430 | void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, | |
431 | struct radeon_semaphore *semaphore); | |
432 | void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, | |
433 | struct radeon_semaphore *semaphore); | |
8f676c4c CK |
434 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
435 | struct radeon_semaphore *semaphore, | |
220907d9 | 436 | int signaler, int waiter); |
c1341e52 | 437 | void radeon_semaphore_free(struct radeon_device *rdev, |
220907d9 | 438 | struct radeon_semaphore **semaphore, |
a8c05940 | 439 | struct radeon_fence *fence); |
c1341e52 | 440 | |
771fe6b9 JG |
441 | /* |
442 | * GART structures, functions & helpers | |
443 | */ | |
444 | struct radeon_mc; | |
445 | ||
a77f1718 | 446 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 447 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
003cefe0 | 448 | #define RADEON_GPU_PAGE_SHIFT 12 |
721604a1 | 449 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
a77f1718 | 450 | |
771fe6b9 JG |
451 | struct radeon_gart { |
452 | dma_addr_t table_addr; | |
c9a1be96 JG |
453 | struct radeon_bo *robj; |
454 | void *ptr; | |
771fe6b9 JG |
455 | unsigned num_gpu_pages; |
456 | unsigned num_cpu_pages; | |
457 | unsigned table_size; | |
771fe6b9 JG |
458 | struct page **pages; |
459 | dma_addr_t *pages_addr; | |
460 | bool ready; | |
461 | }; | |
462 | ||
463 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
464 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
465 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
466 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
c9a1be96 JG |
467 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
468 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); | |
771fe6b9 JG |
469 | int radeon_gart_init(struct radeon_device *rdev); |
470 | void radeon_gart_fini(struct radeon_device *rdev); | |
471 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
472 | int pages); | |
473 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
c39d3516 KRW |
474 | int pages, struct page **pagelist, |
475 | dma_addr_t *dma_addr); | |
c9a1be96 | 476 | void radeon_gart_restore(struct radeon_device *rdev); |
771fe6b9 JG |
477 | |
478 | ||
479 | /* | |
480 | * GPU MC structures, functions & helpers | |
481 | */ | |
482 | struct radeon_mc { | |
483 | resource_size_t aper_size; | |
484 | resource_size_t aper_base; | |
485 | resource_size_t agp_base; | |
7a50f01a DA |
486 | /* for some chips with <= 32MB we need to lie |
487 | * about vram size near mc fb location */ | |
3ce0a23d | 488 | u64 mc_vram_size; |
d594e46a | 489 | u64 visible_vram_size; |
3ce0a23d JG |
490 | u64 gtt_size; |
491 | u64 gtt_start; | |
492 | u64 gtt_end; | |
3ce0a23d JG |
493 | u64 vram_start; |
494 | u64 vram_end; | |
771fe6b9 | 495 | unsigned vram_width; |
3ce0a23d | 496 | u64 real_vram_size; |
771fe6b9 JG |
497 | int vram_mtrr; |
498 | bool vram_is_ddr; | |
d594e46a | 499 | bool igp_sideport_enabled; |
8d369bb1 | 500 | u64 gtt_base_align; |
771fe6b9 JG |
501 | }; |
502 | ||
06b6476d AD |
503 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
504 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
505 | |
506 | /* | |
507 | * GPU scratch registers structures, functions & helpers | |
508 | */ | |
509 | struct radeon_scratch { | |
510 | unsigned num_reg; | |
724c80e1 | 511 | uint32_t reg_base; |
771fe6b9 JG |
512 | bool free[32]; |
513 | uint32_t reg[32]; | |
514 | }; | |
515 | ||
516 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
517 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
518 | ||
519 | ||
520 | /* | |
521 | * IRQS. | |
522 | */ | |
6f34be50 AD |
523 | |
524 | struct radeon_unpin_work { | |
525 | struct work_struct work; | |
526 | struct radeon_device *rdev; | |
527 | int crtc_id; | |
528 | struct radeon_fence *fence; | |
529 | struct drm_pending_vblank_event *event; | |
530 | struct radeon_bo *old_rbo; | |
531 | u64 new_crtc_base; | |
532 | }; | |
533 | ||
534 | struct r500_irq_stat_regs { | |
535 | u32 disp_int; | |
f122c610 | 536 | u32 hdmi0_status; |
6f34be50 AD |
537 | }; |
538 | ||
539 | struct r600_irq_stat_regs { | |
540 | u32 disp_int; | |
541 | u32 disp_int_cont; | |
542 | u32 disp_int_cont2; | |
543 | u32 d1grph_int; | |
544 | u32 d2grph_int; | |
f122c610 AD |
545 | u32 hdmi0_status; |
546 | u32 hdmi1_status; | |
6f34be50 AD |
547 | }; |
548 | ||
549 | struct evergreen_irq_stat_regs { | |
550 | u32 disp_int; | |
551 | u32 disp_int_cont; | |
552 | u32 disp_int_cont2; | |
553 | u32 disp_int_cont3; | |
554 | u32 disp_int_cont4; | |
555 | u32 disp_int_cont5; | |
556 | u32 d1grph_int; | |
557 | u32 d2grph_int; | |
558 | u32 d3grph_int; | |
559 | u32 d4grph_int; | |
560 | u32 d5grph_int; | |
561 | u32 d6grph_int; | |
f122c610 AD |
562 | u32 afmt_status1; |
563 | u32 afmt_status2; | |
564 | u32 afmt_status3; | |
565 | u32 afmt_status4; | |
566 | u32 afmt_status5; | |
567 | u32 afmt_status6; | |
6f34be50 AD |
568 | }; |
569 | ||
570 | union radeon_irq_stat_regs { | |
571 | struct r500_irq_stat_regs r500; | |
572 | struct r600_irq_stat_regs r600; | |
573 | struct evergreen_irq_stat_regs evergreen; | |
574 | }; | |
575 | ||
54bd5206 IH |
576 | #define RADEON_MAX_HPD_PINS 6 |
577 | #define RADEON_MAX_CRTCS 6 | |
f122c610 | 578 | #define RADEON_MAX_AFMT_BLOCKS 6 |
54bd5206 | 579 | |
771fe6b9 | 580 | struct radeon_irq { |
fb98257a CK |
581 | bool installed; |
582 | spinlock_t lock; | |
736fc37f | 583 | atomic_t ring_int[RADEON_NUM_RINGS]; |
fb98257a | 584 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
736fc37f | 585 | atomic_t pflip[RADEON_MAX_CRTCS]; |
fb98257a CK |
586 | wait_queue_head_t vblank_queue; |
587 | bool hpd[RADEON_MAX_HPD_PINS]; | |
fb98257a CK |
588 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
589 | union radeon_irq_stat_regs stat_regs; | |
771fe6b9 JG |
590 | }; |
591 | ||
592 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
593 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1b37078b AD |
594 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
595 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); | |
6f34be50 AD |
596 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
597 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); | |
fb98257a CK |
598 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
599 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); | |
600 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
601 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
771fe6b9 JG |
602 | |
603 | /* | |
e32eb50d | 604 | * CP & rings. |
771fe6b9 | 605 | */ |
7465280c | 606 | |
771fe6b9 | 607 | struct radeon_ib { |
68470ae7 JG |
608 | struct radeon_sa_bo *sa_bo; |
609 | uint32_t length_dw; | |
610 | uint64_t gpu_addr; | |
611 | uint32_t *ptr; | |
876dc9f3 | 612 | int ring; |
68470ae7 | 613 | struct radeon_fence *fence; |
4bf3dd92 | 614 | struct radeon_vm *vm; |
68470ae7 | 615 | bool is_const_ib; |
220907d9 | 616 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
68470ae7 | 617 | struct radeon_semaphore *semaphore; |
771fe6b9 JG |
618 | }; |
619 | ||
e32eb50d | 620 | struct radeon_ring { |
4c788679 | 621 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
622 | volatile uint32_t *ring; |
623 | unsigned rptr; | |
5596a9db CK |
624 | unsigned rptr_offs; |
625 | unsigned rptr_reg; | |
45df6803 | 626 | unsigned rptr_save_reg; |
89d35807 AD |
627 | u64 next_rptr_gpu_addr; |
628 | volatile u32 *next_rptr_cpu_addr; | |
771fe6b9 JG |
629 | unsigned wptr; |
630 | unsigned wptr_old; | |
5596a9db | 631 | unsigned wptr_reg; |
771fe6b9 JG |
632 | unsigned ring_size; |
633 | unsigned ring_free_dw; | |
634 | int count_dw; | |
069211e5 CK |
635 | unsigned long last_activity; |
636 | unsigned last_rptr; | |
771fe6b9 JG |
637 | uint64_t gpu_addr; |
638 | uint32_t align_mask; | |
639 | uint32_t ptr_mask; | |
771fe6b9 | 640 | bool ready; |
78c5560a AD |
641 | u32 ptr_reg_shift; |
642 | u32 ptr_reg_mask; | |
643 | u32 nop; | |
8b25ed34 | 644 | u32 idx; |
771fe6b9 JG |
645 | }; |
646 | ||
721604a1 JG |
647 | /* |
648 | * VM | |
649 | */ | |
ee60e29f | 650 | |
fa87e62d | 651 | /* maximum number of VMIDs */ |
ee60e29f CK |
652 | #define RADEON_NUM_VM 16 |
653 | ||
fa87e62d DC |
654 | /* defines number of bits in page table versus page directory, |
655 | * a page is 4KB so we have 12 bits offset, 9 bits in the page | |
656 | * table and the remaining 19 bits are in the page directory */ | |
657 | #define RADEON_VM_BLOCK_SIZE 9 | |
658 | ||
659 | /* number of entries in page table */ | |
660 | #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) | |
661 | ||
721604a1 JG |
662 | struct radeon_vm { |
663 | struct list_head list; | |
664 | struct list_head va; | |
ee60e29f | 665 | unsigned id; |
721604a1 | 666 | unsigned last_pfn; |
fa87e62d | 667 | u64 pd_gpu_addr; |
2e0d9910 | 668 | struct radeon_sa_bo *sa_bo; |
721604a1 JG |
669 | struct mutex mutex; |
670 | /* last fence for cs using this vm */ | |
671 | struct radeon_fence *fence; | |
9b40e5d8 CK |
672 | /* last flush or NULL if we still need to flush */ |
673 | struct radeon_fence *last_flush; | |
721604a1 JG |
674 | }; |
675 | ||
721604a1 | 676 | struct radeon_vm_manager { |
36ff39c4 | 677 | struct mutex lock; |
721604a1 | 678 | struct list_head lru_vm; |
ee60e29f | 679 | struct radeon_fence *active[RADEON_NUM_VM]; |
721604a1 JG |
680 | struct radeon_sa_manager sa_manager; |
681 | uint32_t max_pfn; | |
721604a1 JG |
682 | /* number of VMIDs */ |
683 | unsigned nvm; | |
684 | /* vram base address for page table entry */ | |
685 | u64 vram_base_offset; | |
67e915e4 AD |
686 | /* is vm enabled? */ |
687 | bool enabled; | |
721604a1 JG |
688 | }; |
689 | ||
690 | /* | |
691 | * file private structure | |
692 | */ | |
693 | struct radeon_fpriv { | |
694 | struct radeon_vm vm; | |
695 | }; | |
696 | ||
d8f60cfc AD |
697 | /* |
698 | * R6xx+ IH ring | |
699 | */ | |
700 | struct r600_ih { | |
4c788679 | 701 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
702 | volatile uint32_t *ring; |
703 | unsigned rptr; | |
d8f60cfc AD |
704 | unsigned ring_size; |
705 | uint64_t gpu_addr; | |
d8f60cfc | 706 | uint32_t ptr_mask; |
c20dc369 | 707 | atomic_t lock; |
d8f60cfc AD |
708 | bool enabled; |
709 | }; | |
710 | ||
8eec9d6f IH |
711 | struct r600_blit_cp_primitives { |
712 | void (*set_render_target)(struct radeon_device *rdev, int format, | |
713 | int w, int h, u64 gpu_addr); | |
714 | void (*cp_set_surface_sync)(struct radeon_device *rdev, | |
715 | u32 sync_type, u32 size, | |
716 | u64 mc_addr); | |
717 | void (*set_shaders)(struct radeon_device *rdev); | |
718 | void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); | |
719 | void (*set_tex_resource)(struct radeon_device *rdev, | |
720 | int format, int w, int h, int pitch, | |
9bb7703c | 721 | u64 gpu_addr, u32 size); |
8eec9d6f IH |
722 | void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, |
723 | int x2, int y2); | |
724 | void (*draw_auto)(struct radeon_device *rdev); | |
725 | void (*set_default_state)(struct radeon_device *rdev); | |
726 | }; | |
727 | ||
3ce0a23d | 728 | struct r600_blit { |
4c788679 | 729 | struct radeon_bo *shader_obj; |
8eec9d6f IH |
730 | struct r600_blit_cp_primitives primitives; |
731 | int max_dim; | |
732 | int ring_size_common; | |
733 | int ring_size_per_loop; | |
3ce0a23d JG |
734 | u64 shader_gpu_addr; |
735 | u32 vs_offset, ps_offset; | |
736 | u32 state_offset; | |
737 | u32 state_len; | |
3ce0a23d JG |
738 | }; |
739 | ||
347e7592 AD |
740 | /* |
741 | * SI RLC stuff | |
742 | */ | |
743 | struct si_rlc { | |
744 | /* for power gating */ | |
745 | struct radeon_bo *save_restore_obj; | |
746 | uint64_t save_restore_gpu_addr; | |
747 | /* for clear state */ | |
748 | struct radeon_bo *clear_state_obj; | |
749 | uint64_t clear_state_gpu_addr; | |
750 | }; | |
751 | ||
69e130a6 | 752 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
753 | struct radeon_ib *ib, struct radeon_vm *vm, |
754 | unsigned size); | |
f2e39221 | 755 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
4ef72566 CK |
756 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
757 | struct radeon_ib *const_ib); | |
771fe6b9 JG |
758 | int radeon_ib_pool_init(struct radeon_device *rdev); |
759 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
7bd560e8 | 760 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
771fe6b9 | 761 | /* Ring access between begin & end cannot sleep */ |
89d35807 AD |
762 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
763 | struct radeon_ring *ring); | |
e32eb50d CK |
764 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
765 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
766 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
767 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
768 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
d6999bc7 | 769 | void radeon_ring_undo(struct radeon_ring *ring); |
e32eb50d CK |
770 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
771 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); | |
7b9ef16b | 772 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); |
069211e5 CK |
773 | void radeon_ring_lockup_update(struct radeon_ring *ring); |
774 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
55d7c221 CK |
775 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
776 | uint32_t **data); | |
777 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
778 | unsigned size, uint32_t *data); | |
e32eb50d | 779 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
78c5560a AD |
780 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
781 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); | |
e32eb50d | 782 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
771fe6b9 JG |
783 | |
784 | ||
785 | /* | |
786 | * CS. | |
787 | */ | |
788 | struct radeon_cs_reloc { | |
789 | struct drm_gem_object *gobj; | |
4c788679 JG |
790 | struct radeon_bo *robj; |
791 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
792 | uint32_t handle; |
793 | uint32_t flags; | |
794 | }; | |
795 | ||
796 | struct radeon_cs_chunk { | |
797 | uint32_t chunk_id; | |
798 | uint32_t length_dw; | |
721604a1 JG |
799 | int kpage_idx[2]; |
800 | uint32_t *kpage[2]; | |
771fe6b9 | 801 | uint32_t *kdata; |
721604a1 JG |
802 | void __user *user_ptr; |
803 | int last_copied_page; | |
804 | int last_page_index; | |
771fe6b9 JG |
805 | }; |
806 | ||
807 | struct radeon_cs_parser { | |
c8c15ff1 | 808 | struct device *dev; |
771fe6b9 JG |
809 | struct radeon_device *rdev; |
810 | struct drm_file *filp; | |
811 | /* chunks */ | |
812 | unsigned nchunks; | |
813 | struct radeon_cs_chunk *chunks; | |
814 | uint64_t *chunks_array; | |
815 | /* IB */ | |
816 | unsigned idx; | |
817 | /* relocations */ | |
818 | unsigned nrelocs; | |
819 | struct radeon_cs_reloc *relocs; | |
820 | struct radeon_cs_reloc **relocs_ptr; | |
821 | struct list_head validated; | |
822 | /* indices of various chunks */ | |
823 | int chunk_ib_idx; | |
824 | int chunk_relocs_idx; | |
721604a1 | 825 | int chunk_flags_idx; |
dfcf5f36 | 826 | int chunk_const_ib_idx; |
f2e39221 JG |
827 | struct radeon_ib ib; |
828 | struct radeon_ib const_ib; | |
771fe6b9 | 829 | void *track; |
3ce0a23d | 830 | unsigned family; |
e70f224c | 831 | int parser_error; |
721604a1 JG |
832 | u32 cs_flags; |
833 | u32 ring; | |
834 | s32 priority; | |
771fe6b9 JG |
835 | }; |
836 | ||
513bcb46 | 837 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
ce580fab | 838 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
513bcb46 | 839 | |
771fe6b9 JG |
840 | struct radeon_cs_packet { |
841 | unsigned idx; | |
842 | unsigned type; | |
843 | unsigned reg; | |
844 | unsigned opcode; | |
845 | int count; | |
846 | unsigned one_reg_wr; | |
847 | }; | |
848 | ||
849 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
850 | struct radeon_cs_packet *pkt, | |
851 | unsigned idx, unsigned reg); | |
852 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
853 | struct radeon_cs_packet *pkt); | |
854 | ||
855 | ||
856 | /* | |
857 | * AGP | |
858 | */ | |
859 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 860 | void radeon_agp_resume(struct radeon_device *rdev); |
10b06122 | 861 | void radeon_agp_suspend(struct radeon_device *rdev); |
771fe6b9 JG |
862 | void radeon_agp_fini(struct radeon_device *rdev); |
863 | ||
864 | ||
865 | /* | |
866 | * Writeback | |
867 | */ | |
868 | struct radeon_wb { | |
4c788679 | 869 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
870 | volatile uint32_t *wb; |
871 | uint64_t gpu_addr; | |
724c80e1 | 872 | bool enabled; |
d0f8a854 | 873 | bool use_event; |
771fe6b9 JG |
874 | }; |
875 | ||
724c80e1 | 876 | #define RADEON_WB_SCRATCH_OFFSET 0 |
89d35807 | 877 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
724c80e1 | 878 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
0c88a02e AD |
879 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
880 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 | |
724c80e1 | 881 | #define R600_WB_IH_WPTR_OFFSET 2048 |
d0f8a854 | 882 | #define R600_WB_EVENT_OFFSET 3072 |
724c80e1 | 883 | |
c93bb85b JG |
884 | /** |
885 | * struct radeon_pm - power management datas | |
886 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
887 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
888 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
889 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
890 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
891 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
892 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
893 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
894 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
25985edc | 895 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
c93bb85b JG |
896 | * @needed_bandwidth: current bandwidth needs |
897 | * | |
898 | * It keeps track of various data needed to take powermanagement decision. | |
25985edc | 899 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
c93bb85b JG |
900 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
901 | * (type of memory, bus size, efficiency, ...) | |
902 | */ | |
ce8f5370 AD |
903 | |
904 | enum radeon_pm_method { | |
905 | PM_METHOD_PROFILE, | |
906 | PM_METHOD_DYNPM, | |
907 | }; | |
908 | ||
909 | enum radeon_dynpm_state { | |
910 | DYNPM_STATE_DISABLED, | |
911 | DYNPM_STATE_MINIMUM, | |
912 | DYNPM_STATE_PAUSED, | |
3f53eb6f RW |
913 | DYNPM_STATE_ACTIVE, |
914 | DYNPM_STATE_SUSPENDED, | |
c913e23a | 915 | }; |
ce8f5370 AD |
916 | enum radeon_dynpm_action { |
917 | DYNPM_ACTION_NONE, | |
918 | DYNPM_ACTION_MINIMUM, | |
919 | DYNPM_ACTION_DOWNCLOCK, | |
920 | DYNPM_ACTION_UPCLOCK, | |
921 | DYNPM_ACTION_DEFAULT | |
c913e23a | 922 | }; |
56278a8e AD |
923 | |
924 | enum radeon_voltage_type { | |
925 | VOLTAGE_NONE = 0, | |
926 | VOLTAGE_GPIO, | |
927 | VOLTAGE_VDDC, | |
928 | VOLTAGE_SW | |
929 | }; | |
930 | ||
0ec0e74f AD |
931 | enum radeon_pm_state_type { |
932 | POWER_STATE_TYPE_DEFAULT, | |
933 | POWER_STATE_TYPE_POWERSAVE, | |
934 | POWER_STATE_TYPE_BATTERY, | |
935 | POWER_STATE_TYPE_BALANCED, | |
936 | POWER_STATE_TYPE_PERFORMANCE, | |
937 | }; | |
938 | ||
ce8f5370 AD |
939 | enum radeon_pm_profile_type { |
940 | PM_PROFILE_DEFAULT, | |
941 | PM_PROFILE_AUTO, | |
942 | PM_PROFILE_LOW, | |
c9e75b21 | 943 | PM_PROFILE_MID, |
ce8f5370 AD |
944 | PM_PROFILE_HIGH, |
945 | }; | |
946 | ||
947 | #define PM_PROFILE_DEFAULT_IDX 0 | |
948 | #define PM_PROFILE_LOW_SH_IDX 1 | |
c9e75b21 AD |
949 | #define PM_PROFILE_MID_SH_IDX 2 |
950 | #define PM_PROFILE_HIGH_SH_IDX 3 | |
951 | #define PM_PROFILE_LOW_MH_IDX 4 | |
952 | #define PM_PROFILE_MID_MH_IDX 5 | |
953 | #define PM_PROFILE_HIGH_MH_IDX 6 | |
954 | #define PM_PROFILE_MAX 7 | |
ce8f5370 AD |
955 | |
956 | struct radeon_pm_profile { | |
957 | int dpms_off_ps_idx; | |
958 | int dpms_on_ps_idx; | |
959 | int dpms_off_cm_idx; | |
960 | int dpms_on_cm_idx; | |
516d0e46 AD |
961 | }; |
962 | ||
21a8122a AD |
963 | enum radeon_int_thermal_type { |
964 | THERMAL_TYPE_NONE, | |
965 | THERMAL_TYPE_RV6XX, | |
966 | THERMAL_TYPE_RV770, | |
967 | THERMAL_TYPE_EVERGREEN, | |
e33df25f | 968 | THERMAL_TYPE_SUMO, |
4fddba1f | 969 | THERMAL_TYPE_NI, |
14607d08 | 970 | THERMAL_TYPE_SI, |
21a8122a AD |
971 | }; |
972 | ||
56278a8e AD |
973 | struct radeon_voltage { |
974 | enum radeon_voltage_type type; | |
975 | /* gpio voltage */ | |
976 | struct radeon_gpio_rec gpio; | |
977 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
978 | bool active_high; /* voltage drop is active when bit is high */ | |
979 | /* VDDC voltage */ | |
980 | u8 vddc_id; /* index into vddc voltage table */ | |
981 | u8 vddci_id; /* index into vddci voltage table */ | |
982 | bool vddci_enabled; | |
983 | /* r6xx+ sw */ | |
2feea49a AD |
984 | u16 voltage; |
985 | /* evergreen+ vddci */ | |
986 | u16 vddci; | |
56278a8e AD |
987 | }; |
988 | ||
d7311171 AD |
989 | /* clock mode flags */ |
990 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) | |
991 | ||
56278a8e AD |
992 | struct radeon_pm_clock_info { |
993 | /* memory clock */ | |
994 | u32 mclk; | |
995 | /* engine clock */ | |
996 | u32 sclk; | |
997 | /* voltage info */ | |
998 | struct radeon_voltage voltage; | |
d7311171 | 999 | /* standardized clock flags */ |
56278a8e AD |
1000 | u32 flags; |
1001 | }; | |
1002 | ||
a48b9b4e | 1003 | /* state flags */ |
d7311171 | 1004 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
a48b9b4e | 1005 | |
56278a8e | 1006 | struct radeon_power_state { |
0ec0e74f | 1007 | enum radeon_pm_state_type type; |
8f3f1c9a | 1008 | struct radeon_pm_clock_info *clock_info; |
56278a8e AD |
1009 | /* number of valid clock modes in this power state */ |
1010 | int num_clock_modes; | |
56278a8e | 1011 | struct radeon_pm_clock_info *default_clock_mode; |
a48b9b4e AD |
1012 | /* standardized state flags */ |
1013 | u32 flags; | |
79daedc9 AD |
1014 | u32 misc; /* vbios specific flags */ |
1015 | u32 misc2; /* vbios specific flags */ | |
1016 | int pcie_lanes; /* pcie lanes */ | |
56278a8e AD |
1017 | }; |
1018 | ||
27459324 RM |
1019 | /* |
1020 | * Some modes are overclocked by very low value, accept them | |
1021 | */ | |
1022 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
1023 | ||
c93bb85b | 1024 | struct radeon_pm { |
c913e23a | 1025 | struct mutex mutex; |
db7fce39 CK |
1026 | /* write locked while reprogramming mclk */ |
1027 | struct rw_semaphore mclk_lock; | |
a48b9b4e AD |
1028 | u32 active_crtcs; |
1029 | int active_crtc_count; | |
c913e23a | 1030 | int req_vblank; |
839461d3 | 1031 | bool vblank_sync; |
c93bb85b JG |
1032 | fixed20_12 max_bandwidth; |
1033 | fixed20_12 igp_sideport_mclk; | |
1034 | fixed20_12 igp_system_mclk; | |
1035 | fixed20_12 igp_ht_link_clk; | |
1036 | fixed20_12 igp_ht_link_width; | |
1037 | fixed20_12 k8_bandwidth; | |
1038 | fixed20_12 sideport_bandwidth; | |
1039 | fixed20_12 ht_bandwidth; | |
1040 | fixed20_12 core_bandwidth; | |
1041 | fixed20_12 sclk; | |
f47299c5 | 1042 | fixed20_12 mclk; |
c93bb85b | 1043 | fixed20_12 needed_bandwidth; |
0975b162 | 1044 | struct radeon_power_state *power_state; |
56278a8e AD |
1045 | /* number of valid power states */ |
1046 | int num_power_states; | |
a48b9b4e AD |
1047 | int current_power_state_index; |
1048 | int current_clock_mode_index; | |
1049 | int requested_power_state_index; | |
1050 | int requested_clock_mode_index; | |
1051 | int default_power_state_index; | |
1052 | u32 current_sclk; | |
1053 | u32 current_mclk; | |
2feea49a AD |
1054 | u16 current_vddc; |
1055 | u16 current_vddci; | |
9ace9f7b AD |
1056 | u32 default_sclk; |
1057 | u32 default_mclk; | |
2feea49a AD |
1058 | u16 default_vddc; |
1059 | u16 default_vddci; | |
29fb52ca | 1060 | struct radeon_i2c_chan *i2c_bus; |
ce8f5370 AD |
1061 | /* selected pm method */ |
1062 | enum radeon_pm_method pm_method; | |
1063 | /* dynpm power management */ | |
1064 | struct delayed_work dynpm_idle_work; | |
1065 | enum radeon_dynpm_state dynpm_state; | |
1066 | enum radeon_dynpm_action dynpm_planned_action; | |
1067 | unsigned long dynpm_action_timeout; | |
1068 | bool dynpm_can_upclock; | |
1069 | bool dynpm_can_downclock; | |
1070 | /* profile-based power management */ | |
1071 | enum radeon_pm_profile_type profile; | |
1072 | int profile_index; | |
1073 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; | |
21a8122a AD |
1074 | /* internal thermal controller on rv6xx+ */ |
1075 | enum radeon_int_thermal_type int_thermal_type; | |
1076 | struct device *int_hwmon_dev; | |
c93bb85b JG |
1077 | }; |
1078 | ||
a4c9e2ee AD |
1079 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1080 | enum radeon_pm_state_type ps_type, | |
1081 | int instance); | |
771fe6b9 | 1082 | |
a92553ab | 1083 | struct r600_audio { |
a92553ab RM |
1084 | int channels; |
1085 | int rate; | |
1086 | int bits_per_sample; | |
1087 | u8 status_bits; | |
1088 | u8 category_code; | |
1089 | }; | |
1090 | ||
771fe6b9 JG |
1091 | /* |
1092 | * Benchmarking | |
1093 | */ | |
638dd7db | 1094 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
771fe6b9 JG |
1095 | |
1096 | ||
ecc0b326 MD |
1097 | /* |
1098 | * Testing | |
1099 | */ | |
1100 | void radeon_test_moves(struct radeon_device *rdev); | |
60a7e396 | 1101 | void radeon_test_ring_sync(struct radeon_device *rdev, |
e32eb50d CK |
1102 | struct radeon_ring *cpA, |
1103 | struct radeon_ring *cpB); | |
60a7e396 | 1104 | void radeon_test_syncing(struct radeon_device *rdev); |
ecc0b326 MD |
1105 | |
1106 | ||
771fe6b9 JG |
1107 | /* |
1108 | * Debugfs | |
1109 | */ | |
4d8bf9ae CK |
1110 | struct radeon_debugfs { |
1111 | struct drm_info_list *files; | |
1112 | unsigned num_files; | |
1113 | }; | |
1114 | ||
771fe6b9 JG |
1115 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1116 | struct drm_info_list *files, | |
1117 | unsigned nfiles); | |
1118 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 JG |
1119 | |
1120 | ||
1121 | /* | |
1122 | * ASIC specific functions. | |
1123 | */ | |
1124 | struct radeon_asic { | |
068a117c | 1125 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
1126 | void (*fini)(struct radeon_device *rdev); |
1127 | int (*resume)(struct radeon_device *rdev); | |
1128 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 1129 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
a2d07b74 | 1130 | int (*asic_reset)(struct radeon_device *rdev); |
54e88e06 AD |
1131 | /* ioctl hw specific callback. Some hw might want to perform special |
1132 | * operation on specific ioctl. For instance on wait idle some hw | |
1133 | * might want to perform and HDP flush through MMIO as it seems that | |
1134 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
1135 | * through ring. | |
1136 | */ | |
1137 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
1138 | /* check if 3D engine is idle */ | |
1139 | bool (*gui_idle)(struct radeon_device *rdev); | |
1140 | /* wait for mc_idle */ | |
1141 | int (*mc_wait_for_idle)(struct radeon_device *rdev); | |
1142 | /* gart */ | |
c5b3b850 AD |
1143 | struct { |
1144 | void (*tlb_flush)(struct radeon_device *rdev); | |
1145 | int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
1146 | } gart; | |
05b07147 CK |
1147 | struct { |
1148 | int (*init)(struct radeon_device *rdev); | |
1149 | void (*fini)(struct radeon_device *rdev); | |
2a6f1abb CK |
1150 | |
1151 | u32 pt_ring_index; | |
dce34bfd CK |
1152 | void (*set_page)(struct radeon_device *rdev, uint64_t pe, |
1153 | uint64_t addr, unsigned count, | |
1154 | uint32_t incr, uint32_t flags); | |
05b07147 | 1155 | } vm; |
54e88e06 | 1156 | /* ring specific callbacks */ |
4c87bc26 CK |
1157 | struct { |
1158 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
721604a1 | 1159 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
4c87bc26 | 1160 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
e32eb50d | 1161 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
4c87bc26 | 1162 | struct radeon_semaphore *semaphore, bool emit_wait); |
eb0c19c5 | 1163 | int (*cs_parse)(struct radeon_cs_parser *p); |
f712812e AD |
1164 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
1165 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1166 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
312c4a8c | 1167 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
9b40e5d8 | 1168 | void (*vm_flush)(struct radeon_device *rdev, struct radeon_ib *ib); |
4c87bc26 | 1169 | } ring[RADEON_NUM_RINGS]; |
54e88e06 | 1170 | /* irqs */ |
b35ea4ab AD |
1171 | struct { |
1172 | int (*set)(struct radeon_device *rdev); | |
1173 | int (*process)(struct radeon_device *rdev); | |
1174 | } irq; | |
54e88e06 | 1175 | /* displays */ |
c79a49ca AD |
1176 | struct { |
1177 | /* display watermarks */ | |
1178 | void (*bandwidth_update)(struct radeon_device *rdev); | |
1179 | /* get frame count */ | |
1180 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); | |
1181 | /* wait for vblank */ | |
1182 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); | |
37e9b6a6 AD |
1183 | /* set backlight level */ |
1184 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); | |
6d92f81d AD |
1185 | /* get backlight level */ |
1186 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); | |
c79a49ca | 1187 | } display; |
54e88e06 | 1188 | /* copy functions for bo handling */ |
27cd7769 AD |
1189 | struct { |
1190 | int (*blit)(struct radeon_device *rdev, | |
1191 | uint64_t src_offset, | |
1192 | uint64_t dst_offset, | |
1193 | unsigned num_gpu_pages, | |
876dc9f3 | 1194 | struct radeon_fence **fence); |
27cd7769 AD |
1195 | u32 blit_ring_index; |
1196 | int (*dma)(struct radeon_device *rdev, | |
1197 | uint64_t src_offset, | |
1198 | uint64_t dst_offset, | |
1199 | unsigned num_gpu_pages, | |
876dc9f3 | 1200 | struct radeon_fence **fence); |
27cd7769 AD |
1201 | u32 dma_ring_index; |
1202 | /* method used for bo copy */ | |
1203 | int (*copy)(struct radeon_device *rdev, | |
1204 | uint64_t src_offset, | |
1205 | uint64_t dst_offset, | |
1206 | unsigned num_gpu_pages, | |
876dc9f3 | 1207 | struct radeon_fence **fence); |
27cd7769 AD |
1208 | /* ring used for bo copies */ |
1209 | u32 copy_ring_index; | |
1210 | } copy; | |
54e88e06 | 1211 | /* surfaces */ |
9e6f3d02 AD |
1212 | struct { |
1213 | int (*set_reg)(struct radeon_device *rdev, int reg, | |
1214 | uint32_t tiling_flags, uint32_t pitch, | |
1215 | uint32_t offset, uint32_t obj_size); | |
1216 | void (*clear_reg)(struct radeon_device *rdev, int reg); | |
1217 | } surface; | |
54e88e06 | 1218 | /* hotplug detect */ |
901ea57d AD |
1219 | struct { |
1220 | void (*init)(struct radeon_device *rdev); | |
1221 | void (*fini)(struct radeon_device *rdev); | |
1222 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1223 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1224 | } hpd; | |
ce8f5370 | 1225 | /* power management */ |
a02fa397 AD |
1226 | struct { |
1227 | void (*misc)(struct radeon_device *rdev); | |
1228 | void (*prepare)(struct radeon_device *rdev); | |
1229 | void (*finish)(struct radeon_device *rdev); | |
1230 | void (*init_profile)(struct radeon_device *rdev); | |
1231 | void (*get_dynpm_state)(struct radeon_device *rdev); | |
798bcf73 AD |
1232 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1233 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); | |
1234 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); | |
1235 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); | |
1236 | int (*get_pcie_lanes)(struct radeon_device *rdev); | |
1237 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); | |
1238 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
a02fa397 | 1239 | } pm; |
6f34be50 | 1240 | /* pageflipping */ |
0f9e006c AD |
1241 | struct { |
1242 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); | |
1243 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
1244 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); | |
1245 | } pflip; | |
771fe6b9 JG |
1246 | }; |
1247 | ||
21f9a437 JG |
1248 | /* |
1249 | * Asic structures | |
1250 | */ | |
551ebd83 | 1251 | struct r100_asic { |
225758d8 JG |
1252 | const unsigned *reg_safe_bm; |
1253 | unsigned reg_safe_bm_size; | |
1254 | u32 hdp_cntl; | |
551ebd83 DA |
1255 | }; |
1256 | ||
21f9a437 | 1257 | struct r300_asic { |
225758d8 JG |
1258 | const unsigned *reg_safe_bm; |
1259 | unsigned reg_safe_bm_size; | |
1260 | u32 resync_scratch; | |
1261 | u32 hdp_cntl; | |
21f9a437 JG |
1262 | }; |
1263 | ||
1264 | struct r600_asic { | |
225758d8 JG |
1265 | unsigned max_pipes; |
1266 | unsigned max_tile_pipes; | |
1267 | unsigned max_simds; | |
1268 | unsigned max_backends; | |
1269 | unsigned max_gprs; | |
1270 | unsigned max_threads; | |
1271 | unsigned max_stack_entries; | |
1272 | unsigned max_hw_contexts; | |
1273 | unsigned max_gs_threads; | |
1274 | unsigned sx_max_export_size; | |
1275 | unsigned sx_max_export_pos_size; | |
1276 | unsigned sx_max_export_smx_size; | |
1277 | unsigned sq_num_cf_insts; | |
1278 | unsigned tiling_nbanks; | |
1279 | unsigned tiling_npipes; | |
1280 | unsigned tiling_group_size; | |
e7aeeba6 | 1281 | unsigned tile_config; |
e55b9422 | 1282 | unsigned backend_map; |
21f9a437 JG |
1283 | }; |
1284 | ||
1285 | struct rv770_asic { | |
225758d8 JG |
1286 | unsigned max_pipes; |
1287 | unsigned max_tile_pipes; | |
1288 | unsigned max_simds; | |
1289 | unsigned max_backends; | |
1290 | unsigned max_gprs; | |
1291 | unsigned max_threads; | |
1292 | unsigned max_stack_entries; | |
1293 | unsigned max_hw_contexts; | |
1294 | unsigned max_gs_threads; | |
1295 | unsigned sx_max_export_size; | |
1296 | unsigned sx_max_export_pos_size; | |
1297 | unsigned sx_max_export_smx_size; | |
1298 | unsigned sq_num_cf_insts; | |
1299 | unsigned sx_num_of_sets; | |
1300 | unsigned sc_prim_fifo_size; | |
1301 | unsigned sc_hiz_tile_fifo_size; | |
1302 | unsigned sc_earlyz_tile_fifo_fize; | |
1303 | unsigned tiling_nbanks; | |
1304 | unsigned tiling_npipes; | |
1305 | unsigned tiling_group_size; | |
e7aeeba6 | 1306 | unsigned tile_config; |
e55b9422 | 1307 | unsigned backend_map; |
21f9a437 JG |
1308 | }; |
1309 | ||
32fcdbf4 AD |
1310 | struct evergreen_asic { |
1311 | unsigned num_ses; | |
1312 | unsigned max_pipes; | |
1313 | unsigned max_tile_pipes; | |
1314 | unsigned max_simds; | |
1315 | unsigned max_backends; | |
1316 | unsigned max_gprs; | |
1317 | unsigned max_threads; | |
1318 | unsigned max_stack_entries; | |
1319 | unsigned max_hw_contexts; | |
1320 | unsigned max_gs_threads; | |
1321 | unsigned sx_max_export_size; | |
1322 | unsigned sx_max_export_pos_size; | |
1323 | unsigned sx_max_export_smx_size; | |
1324 | unsigned sq_num_cf_insts; | |
1325 | unsigned sx_num_of_sets; | |
1326 | unsigned sc_prim_fifo_size; | |
1327 | unsigned sc_hiz_tile_fifo_size; | |
1328 | unsigned sc_earlyz_tile_fifo_size; | |
1329 | unsigned tiling_nbanks; | |
1330 | unsigned tiling_npipes; | |
1331 | unsigned tiling_group_size; | |
e7aeeba6 | 1332 | unsigned tile_config; |
e55b9422 | 1333 | unsigned backend_map; |
32fcdbf4 AD |
1334 | }; |
1335 | ||
fecf1d07 AD |
1336 | struct cayman_asic { |
1337 | unsigned max_shader_engines; | |
1338 | unsigned max_pipes_per_simd; | |
1339 | unsigned max_tile_pipes; | |
1340 | unsigned max_simds_per_se; | |
1341 | unsigned max_backends_per_se; | |
1342 | unsigned max_texture_channel_caches; | |
1343 | unsigned max_gprs; | |
1344 | unsigned max_threads; | |
1345 | unsigned max_gs_threads; | |
1346 | unsigned max_stack_entries; | |
1347 | unsigned sx_num_of_sets; | |
1348 | unsigned sx_max_export_size; | |
1349 | unsigned sx_max_export_pos_size; | |
1350 | unsigned sx_max_export_smx_size; | |
1351 | unsigned max_hw_contexts; | |
1352 | unsigned sq_num_cf_insts; | |
1353 | unsigned sc_prim_fifo_size; | |
1354 | unsigned sc_hiz_tile_fifo_size; | |
1355 | unsigned sc_earlyz_tile_fifo_size; | |
1356 | ||
1357 | unsigned num_shader_engines; | |
1358 | unsigned num_shader_pipes_per_simd; | |
1359 | unsigned num_tile_pipes; | |
1360 | unsigned num_simds_per_se; | |
1361 | unsigned num_backends_per_se; | |
1362 | unsigned backend_disable_mask_per_asic; | |
1363 | unsigned backend_map; | |
1364 | unsigned num_texture_channel_caches; | |
1365 | unsigned mem_max_burst_length_bytes; | |
1366 | unsigned mem_row_size_in_kb; | |
1367 | unsigned shader_engine_tile_size; | |
1368 | unsigned num_gpus; | |
1369 | unsigned multi_gpu_tile_size; | |
1370 | ||
1371 | unsigned tile_config; | |
fecf1d07 AD |
1372 | }; |
1373 | ||
0a96d72b AD |
1374 | struct si_asic { |
1375 | unsigned max_shader_engines; | |
0a96d72b | 1376 | unsigned max_tile_pipes; |
1a8ca750 AD |
1377 | unsigned max_cu_per_sh; |
1378 | unsigned max_sh_per_se; | |
0a96d72b AD |
1379 | unsigned max_backends_per_se; |
1380 | unsigned max_texture_channel_caches; | |
1381 | unsigned max_gprs; | |
1382 | unsigned max_gs_threads; | |
1383 | unsigned max_hw_contexts; | |
1384 | unsigned sc_prim_fifo_size_frontend; | |
1385 | unsigned sc_prim_fifo_size_backend; | |
1386 | unsigned sc_hiz_tile_fifo_size; | |
1387 | unsigned sc_earlyz_tile_fifo_size; | |
1388 | ||
0a96d72b AD |
1389 | unsigned num_tile_pipes; |
1390 | unsigned num_backends_per_se; | |
1391 | unsigned backend_disable_mask_per_asic; | |
1392 | unsigned backend_map; | |
1393 | unsigned num_texture_channel_caches; | |
1394 | unsigned mem_max_burst_length_bytes; | |
1395 | unsigned mem_row_size_in_kb; | |
1396 | unsigned shader_engine_tile_size; | |
1397 | unsigned num_gpus; | |
1398 | unsigned multi_gpu_tile_size; | |
1399 | ||
1400 | unsigned tile_config; | |
0a96d72b AD |
1401 | }; |
1402 | ||
068a117c JG |
1403 | union radeon_asic_config { |
1404 | struct r300_asic r300; | |
551ebd83 | 1405 | struct r100_asic r100; |
3ce0a23d JG |
1406 | struct r600_asic r600; |
1407 | struct rv770_asic rv770; | |
32fcdbf4 | 1408 | struct evergreen_asic evergreen; |
fecf1d07 | 1409 | struct cayman_asic cayman; |
0a96d72b | 1410 | struct si_asic si; |
068a117c JG |
1411 | }; |
1412 | ||
0a10c851 DV |
1413 | /* |
1414 | * asic initizalization from radeon_asic.c | |
1415 | */ | |
1416 | void radeon_agp_disable(struct radeon_device *rdev); | |
1417 | int radeon_asic_init(struct radeon_device *rdev); | |
1418 | ||
771fe6b9 JG |
1419 | |
1420 | /* | |
1421 | * IOCTL. | |
1422 | */ | |
1423 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
1424 | struct drm_file *filp); | |
1425 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
1426 | struct drm_file *filp); | |
1427 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
1428 | struct drm_file *file_priv); | |
1429 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1430 | struct drm_file *file_priv); | |
1431 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1432 | struct drm_file *file_priv); | |
1433 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1434 | struct drm_file *file_priv); | |
1435 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1436 | struct drm_file *filp); | |
1437 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1438 | struct drm_file *filp); | |
1439 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1440 | struct drm_file *filp); | |
1441 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1442 | struct drm_file *filp); | |
721604a1 JG |
1443 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
1444 | struct drm_file *filp); | |
771fe6b9 | 1445 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
e024e110 DA |
1446 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
1447 | struct drm_file *filp); | |
1448 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
1449 | struct drm_file *filp); | |
771fe6b9 | 1450 | |
16cdf04d AD |
1451 | /* VRAM scratch page for HDP bug, default vram page */ |
1452 | struct r600_vram_scratch { | |
87cbf8f2 AD |
1453 | struct radeon_bo *robj; |
1454 | volatile uint32_t *ptr; | |
16cdf04d | 1455 | u64 gpu_addr; |
87cbf8f2 | 1456 | }; |
771fe6b9 | 1457 | |
fd64ca8a LT |
1458 | /* |
1459 | * ACPI | |
1460 | */ | |
1461 | struct radeon_atif_notification_cfg { | |
1462 | bool enabled; | |
1463 | int command_code; | |
1464 | }; | |
1465 | ||
1466 | struct radeon_atif_notifications { | |
1467 | bool display_switch; | |
1468 | bool expansion_mode_change; | |
1469 | bool thermal_state; | |
1470 | bool forced_power_state; | |
1471 | bool system_power_state; | |
1472 | bool display_conf_change; | |
1473 | bool px_gfx_switch; | |
1474 | bool brightness_change; | |
1475 | bool dgpu_display_event; | |
1476 | }; | |
1477 | ||
1478 | struct radeon_atif_functions { | |
1479 | bool system_params; | |
1480 | bool sbios_requests; | |
1481 | bool select_active_disp; | |
1482 | bool lid_state; | |
1483 | bool get_tv_standard; | |
1484 | bool set_tv_standard; | |
1485 | bool get_panel_expansion_mode; | |
1486 | bool set_panel_expansion_mode; | |
1487 | bool temperature_change; | |
1488 | bool graphics_device_types; | |
1489 | }; | |
1490 | ||
1491 | struct radeon_atif { | |
1492 | struct radeon_atif_notifications notifications; | |
1493 | struct radeon_atif_functions functions; | |
1494 | struct radeon_atif_notification_cfg notification_cfg; | |
37e9b6a6 | 1495 | struct radeon_encoder *encoder_for_bl; |
fd64ca8a | 1496 | }; |
7a1619b9 | 1497 | |
e3a15920 AD |
1498 | struct radeon_atcs_functions { |
1499 | bool get_ext_state; | |
1500 | bool pcie_perf_req; | |
1501 | bool pcie_dev_rdy; | |
1502 | bool pcie_bus_width; | |
1503 | }; | |
1504 | ||
1505 | struct radeon_atcs { | |
1506 | struct radeon_atcs_functions functions; | |
1507 | }; | |
1508 | ||
771fe6b9 JG |
1509 | /* |
1510 | * Core structure, functions and helpers. | |
1511 | */ | |
1512 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
1513 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
1514 | ||
1515 | struct radeon_device { | |
9f022ddf | 1516 | struct device *dev; |
771fe6b9 JG |
1517 | struct drm_device *ddev; |
1518 | struct pci_dev *pdev; | |
dee53e7f | 1519 | struct rw_semaphore exclusive_lock; |
771fe6b9 | 1520 | /* ASIC */ |
068a117c | 1521 | union radeon_asic_config config; |
771fe6b9 JG |
1522 | enum radeon_family family; |
1523 | unsigned long flags; | |
1524 | int usec_timeout; | |
1525 | enum radeon_pll_errata pll_errata; | |
1526 | int num_gb_pipes; | |
f779b3e5 | 1527 | int num_z_pipes; |
771fe6b9 JG |
1528 | int disp_priority; |
1529 | /* BIOS */ | |
1530 | uint8_t *bios; | |
1531 | bool is_atom_bios; | |
1532 | uint16_t bios_header_start; | |
4c788679 | 1533 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 1534 | /* Register mmio */ |
4c9bc75c DA |
1535 | resource_size_t rmmio_base; |
1536 | resource_size_t rmmio_size; | |
a0533fbf | 1537 | void __iomem *rmmio; |
771fe6b9 JG |
1538 | radeon_rreg_t mc_rreg; |
1539 | radeon_wreg_t mc_wreg; | |
1540 | radeon_rreg_t pll_rreg; | |
1541 | radeon_wreg_t pll_wreg; | |
de1b2898 | 1542 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
1543 | radeon_rreg_t pciep_rreg; |
1544 | radeon_wreg_t pciep_wreg; | |
351a52a2 AD |
1545 | /* io port */ |
1546 | void __iomem *rio_mem; | |
1547 | resource_size_t rio_mem_size; | |
771fe6b9 JG |
1548 | struct radeon_clock clock; |
1549 | struct radeon_mc mc; | |
1550 | struct radeon_gart gart; | |
1551 | struct radeon_mode_info mode_info; | |
1552 | struct radeon_scratch scratch; | |
1553 | struct radeon_mman mman; | |
7465280c | 1554 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
0085c950 | 1555 | wait_queue_head_t fence_queue; |
d6999bc7 | 1556 | struct mutex ring_lock; |
e32eb50d | 1557 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
c507f7ef JG |
1558 | bool ib_pool_ready; |
1559 | struct radeon_sa_manager ring_tmp_bo; | |
771fe6b9 JG |
1560 | struct radeon_irq irq; |
1561 | struct radeon_asic *asic; | |
1562 | struct radeon_gem gem; | |
c93bb85b | 1563 | struct radeon_pm pm; |
f657c2a7 | 1564 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 | 1565 | struct radeon_wb wb; |
3ce0a23d | 1566 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
1567 | bool shutdown; |
1568 | bool suspend; | |
ad49f501 | 1569 | bool need_dma32; |
733289c2 | 1570 | bool accel_working; |
e024e110 | 1571 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
1572 | const struct firmware *me_fw; /* all family ME firmware */ |
1573 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 1574 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
0af62b01 | 1575 | const struct firmware *mc_fw; /* NI MC firmware */ |
0f0de06c | 1576 | const struct firmware *ce_fw; /* SI CE firmware */ |
3ce0a23d | 1577 | struct r600_blit r600_blit; |
16cdf04d | 1578 | struct r600_vram_scratch vram_scratch; |
3e5cb98d | 1579 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 1580 | struct r600_ih ih; /* r6/700 interrupt ring */ |
347e7592 | 1581 | struct si_rlc rlc; |
d4877cf2 | 1582 | struct work_struct hotplug_work; |
f122c610 | 1583 | struct work_struct audio_work; |
18917b60 | 1584 | int num_crtc; /* number of crtcs */ |
40bacf16 | 1585 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
3299de95 RM |
1586 | bool audio_enabled; |
1587 | struct r600_audio audio_status; /* audio stuff */ | |
ce8f5370 | 1588 | struct notifier_block acpi_nb; |
9eba4a93 | 1589 | /* only one userspace can use Hyperz features or CMASK at a time */ |
ab9e1f59 | 1590 | struct drm_file *hyperz_filp; |
9eba4a93 | 1591 | struct drm_file *cmask_filp; |
f376b94f AD |
1592 | /* i2c buses */ |
1593 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; | |
4d8bf9ae CK |
1594 | /* debugfs */ |
1595 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; | |
1596 | unsigned debugfs_count; | |
721604a1 JG |
1597 | /* virtual memory */ |
1598 | struct radeon_vm_manager vm_manager; | |
6759a0a7 | 1599 | struct mutex gpu_clock_mutex; |
fd64ca8a LT |
1600 | /* ACPI interface */ |
1601 | struct radeon_atif atif; | |
e3a15920 | 1602 | struct radeon_atcs atcs; |
771fe6b9 JG |
1603 | }; |
1604 | ||
1605 | int radeon_device_init(struct radeon_device *rdev, | |
1606 | struct drm_device *ddev, | |
1607 | struct pci_dev *pdev, | |
1608 | uint32_t flags); | |
1609 | void radeon_device_fini(struct radeon_device *rdev); | |
1610 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
1611 | ||
6fcbef7a AK |
1612 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
1613 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | |
1614 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); | |
1615 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
351a52a2 | 1616 | |
4c788679 JG |
1617 | /* |
1618 | * Cast helper | |
1619 | */ | |
1620 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
1621 | |
1622 | /* | |
1623 | * Registers read & write functions. | |
1624 | */ | |
a0533fbf BH |
1625 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
1626 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) | |
1627 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) | |
1628 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) | |
de1b2898 | 1629 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
3ce0a23d | 1630 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
de1b2898 | 1631 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
771fe6b9 JG |
1632 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1633 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1634 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
1635 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
1636 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
1637 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
1638 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1639 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
aa5120d2 RM |
1640 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1641 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
1642 | #define WREG32_P(reg, val, mask) \ |
1643 | do { \ | |
1644 | uint32_t tmp_ = RREG32(reg); \ | |
1645 | tmp_ &= (mask); \ | |
1646 | tmp_ |= ((val) & ~(mask)); \ | |
1647 | WREG32(reg, tmp_); \ | |
1648 | } while (0) | |
1649 | #define WREG32_PLL_P(reg, val, mask) \ | |
1650 | do { \ | |
1651 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1652 | tmp_ &= (mask); \ | |
1653 | tmp_ |= ((val) & ~(mask)); \ | |
1654 | WREG32_PLL(reg, tmp_); \ | |
1655 | } while (0) | |
3ce0a23d | 1656 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
351a52a2 AD |
1657 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1658 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) | |
771fe6b9 | 1659 | |
de1b2898 DA |
1660 | /* |
1661 | * Indirect registers accessor | |
1662 | */ | |
1663 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
1664 | { | |
1665 | uint32_t r; | |
1666 | ||
1667 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1668 | r = RREG32(RADEON_PCIE_DATA); | |
1669 | return r; | |
1670 | } | |
1671 | ||
1672 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1673 | { | |
1674 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1675 | WREG32(RADEON_PCIE_DATA, (v)); | |
1676 | } | |
1677 | ||
771fe6b9 JG |
1678 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1679 | ||
1680 | ||
1681 | /* | |
1682 | * ASICs helpers. | |
1683 | */ | |
b995e433 DA |
1684 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1685 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
1686 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1687 | (rdev->family == CHIP_RV200) || \ | |
1688 | (rdev->family == CHIP_RS100) || \ | |
1689 | (rdev->family == CHIP_RS200) || \ | |
1690 | (rdev->family == CHIP_RV250) || \ | |
1691 | (rdev->family == CHIP_RV280) || \ | |
1692 | (rdev->family == CHIP_RS300)) | |
1693 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
1694 | (rdev->family == CHIP_RV350) || \ | |
1695 | (rdev->family == CHIP_R350) || \ | |
1696 | (rdev->family == CHIP_RV380) || \ | |
1697 | (rdev->family == CHIP_R420) || \ | |
1698 | (rdev->family == CHIP_R423) || \ | |
1699 | (rdev->family == CHIP_RV410) || \ | |
1700 | (rdev->family == CHIP_RS400) || \ | |
1701 | (rdev->family == CHIP_RS480)) | |
3313e3d4 AD |
1702 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
1703 | (rdev->ddev->pdev->device == 0x9443) || \ | |
1704 | (rdev->ddev->pdev->device == 0x944B) || \ | |
1705 | (rdev->ddev->pdev->device == 0x9506) || \ | |
1706 | (rdev->ddev->pdev->device == 0x9509) || \ | |
1707 | (rdev->ddev->pdev->device == 0x950F) || \ | |
1708 | (rdev->ddev->pdev->device == 0x689C) || \ | |
1709 | (rdev->ddev->pdev->device == 0x689D)) | |
771fe6b9 | 1710 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
99999aaa AD |
1711 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
1712 | (rdev->family == CHIP_RS690) || \ | |
1713 | (rdev->family == CHIP_RS740) || \ | |
1714 | (rdev->family >= CHIP_R600)) | |
771fe6b9 JG |
1715 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1716 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 1717 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
633b9164 AD |
1718 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
1719 | (rdev->flags & RADEON_IS_IGP)) | |
1fe18305 | 1720 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
8848f759 AD |
1721 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
1722 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ | |
1723 | (rdev->flags & RADEON_IS_IGP)) | |
771fe6b9 JG |
1724 | |
1725 | /* | |
1726 | * BIOS helpers. | |
1727 | */ | |
1728 | #define RBIOS8(i) (rdev->bios[i]) | |
1729 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1730 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1731 | ||
1732 | int radeon_combios_init(struct radeon_device *rdev); | |
1733 | void radeon_combios_fini(struct radeon_device *rdev); | |
1734 | int radeon_atombios_init(struct radeon_device *rdev); | |
1735 | void radeon_atombios_fini(struct radeon_device *rdev); | |
1736 | ||
1737 | ||
1738 | /* | |
1739 | * RING helpers. | |
1740 | */ | |
ce580fab | 1741 | #if DRM_DEBUG_CODE == 0 |
e32eb50d | 1742 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
771fe6b9 | 1743 | { |
e32eb50d CK |
1744 | ring->ring[ring->wptr++] = v; |
1745 | ring->wptr &= ring->ptr_mask; | |
1746 | ring->count_dw--; | |
1747 | ring->ring_free_dw--; | |
771fe6b9 | 1748 | } |
ce580fab AK |
1749 | #else |
1750 | /* With debugging this is just too big to inline */ | |
e32eb50d | 1751 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
ce580fab | 1752 | #endif |
771fe6b9 JG |
1753 | |
1754 | /* | |
1755 | * ASICs macro. | |
1756 | */ | |
068a117c | 1757 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
1758 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1759 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
1760 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
eb0c19c5 | 1761 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) |
28d52043 | 1762 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
a2d07b74 | 1763 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
c5b3b850 AD |
1764 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
1765 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) | |
05b07147 CK |
1766 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
1767 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) | |
dce34bfd | 1768 | #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) |
f712812e AD |
1769 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) |
1770 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) | |
1771 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) | |
4c87bc26 | 1772 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) |
721604a1 | 1773 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) |
312c4a8c | 1774 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) |
9b40e5d8 | 1775 | #define radeon_ring_vm_flush(rdev, r, ib) (rdev)->asic->ring[(r)].vm_flush((rdev), (ib)) |
b35ea4ab AD |
1776 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
1777 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) | |
c79a49ca | 1778 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
37e9b6a6 | 1779 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
6d92f81d | 1780 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
4c87bc26 CK |
1781 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) |
1782 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) | |
27cd7769 AD |
1783 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
1784 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) | |
1785 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) | |
1786 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index | |
1787 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index | |
1788 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index | |
798bcf73 AD |
1789 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
1790 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) | |
1791 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) | |
1792 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) | |
1793 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) | |
1794 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) | |
1795 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) | |
9e6f3d02 AD |
1796 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
1797 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) | |
c79a49ca | 1798 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
901ea57d AD |
1799 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
1800 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) | |
1801 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) | |
1802 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) | |
def9ba9c | 1803 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
a02fa397 AD |
1804 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
1805 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) | |
1806 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) | |
1807 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) | |
1808 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) | |
69b62ad8 AD |
1809 | #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) |
1810 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) | |
1811 | #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) | |
1812 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) | |
1813 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) | |
771fe6b9 | 1814 | |
6cf8a3f5 | 1815 | /* Common functions */ |
700a0cc0 | 1816 | /* AGP */ |
90aca4d2 | 1817 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
700a0cc0 | 1818 | extern void radeon_agp_disable(struct radeon_device *rdev); |
21f9a437 JG |
1819 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1820 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 1821 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 1822 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 1823 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 1824 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 | 1825 | extern void radeon_scratch_init(struct radeon_device *rdev); |
724c80e1 AD |
1826 | extern void radeon_wb_fini(struct radeon_device *rdev); |
1827 | extern int radeon_wb_init(struct radeon_device *rdev); | |
1828 | extern void radeon_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1829 | extern void radeon_surface_init(struct radeon_device *rdev); |
1830 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1831 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1832 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 1833 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 1834 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
d594e46a JG |
1835 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1836 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
6a9ee8af DA |
1837 | extern int radeon_resume_kms(struct drm_device *dev); |
1838 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
53595338 | 1839 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
6cf8a3f5 | 1840 | |
721604a1 JG |
1841 | /* |
1842 | * vm | |
1843 | */ | |
1844 | int radeon_vm_manager_init(struct radeon_device *rdev); | |
1845 | void radeon_vm_manager_fini(struct radeon_device *rdev); | |
721604a1 JG |
1846 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
1847 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); | |
ddf03f5c | 1848 | int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); |
ee60e29f CK |
1849 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
1850 | struct radeon_vm *vm, int ring); | |
1851 | void radeon_vm_fence(struct radeon_device *rdev, | |
1852 | struct radeon_vm *vm, | |
1853 | struct radeon_fence *fence); | |
dce34bfd | 1854 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
721604a1 JG |
1855 | int radeon_vm_bo_update_pte(struct radeon_device *rdev, |
1856 | struct radeon_vm *vm, | |
1857 | struct radeon_bo *bo, | |
1858 | struct ttm_mem_reg *mem); | |
1859 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, | |
1860 | struct radeon_bo *bo); | |
421ca7ab CK |
1861 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
1862 | struct radeon_bo *bo); | |
e971bd5e CK |
1863 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
1864 | struct radeon_vm *vm, | |
1865 | struct radeon_bo *bo); | |
1866 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, | |
1867 | struct radeon_bo_va *bo_va, | |
1868 | uint64_t offset, | |
1869 | uint32_t flags); | |
721604a1 | 1870 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
e971bd5e | 1871 | struct radeon_bo_va *bo_va); |
721604a1 | 1872 | |
f122c610 AD |
1873 | /* audio */ |
1874 | void r600_audio_update_hdmi(struct work_struct *work); | |
721604a1 | 1875 | |
16cdf04d AD |
1876 | /* |
1877 | * R600 vram scratch functions | |
1878 | */ | |
1879 | int r600_vram_scratch_init(struct radeon_device *rdev); | |
1880 | void r600_vram_scratch_fini(struct radeon_device *rdev); | |
1881 | ||
285484e2 JG |
1882 | /* |
1883 | * r600 cs checking helper | |
1884 | */ | |
1885 | unsigned r600_mip_minify(unsigned size, unsigned level); | |
1886 | bool r600_fmt_is_valid_color(u32 format); | |
1887 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); | |
1888 | int r600_fmt_get_blocksize(u32 format); | |
1889 | int r600_fmt_get_nblocksx(u32 format, u32 w); | |
1890 | int r600_fmt_get_nblocksy(u32 format, u32 h); | |
1891 | ||
3574dda4 DV |
1892 | /* |
1893 | * r600 functions used by radeon_encoder.c | |
1894 | */ | |
1b688d08 RM |
1895 | struct radeon_hdmi_acr { |
1896 | u32 clock; | |
1897 | ||
1898 | int n_32khz; | |
1899 | int cts_32khz; | |
1900 | ||
1901 | int n_44_1khz; | |
1902 | int cts_44_1khz; | |
1903 | ||
1904 | int n_48khz; | |
1905 | int cts_48khz; | |
1906 | ||
1907 | }; | |
1908 | ||
e55d3e6c RM |
1909 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
1910 | ||
2cd6218c RM |
1911 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
1912 | extern void r600_hdmi_disable(struct drm_encoder *encoder); | |
dafc3bd5 | 1913 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
416a2bd2 AD |
1914 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
1915 | u32 tiling_pipe_num, | |
1916 | u32 max_rb_num, | |
1917 | u32 total_max_rb_num, | |
1918 | u32 enabled_rb_mask); | |
fe251e2f | 1919 | |
e55d3e6c RM |
1920 | /* |
1921 | * evergreen functions used by radeon_encoder.c | |
1922 | */ | |
1923 | ||
1924 | extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
1925 | ||
0af62b01 | 1926 | extern int ni_init_microcode(struct radeon_device *rdev); |
755d819e | 1927 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
0af62b01 | 1928 | |
c4917074 AD |
1929 | /* radeon_acpi.c */ |
1930 | #if defined(CONFIG_ACPI) | |
1931 | extern int radeon_acpi_init(struct radeon_device *rdev); | |
1932 | extern void radeon_acpi_fini(struct radeon_device *rdev); | |
1933 | #else | |
1934 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } | |
1935 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } | |
1936 | #endif | |
d7a2952f | 1937 | |
4c788679 JG |
1938 | #include "radeon_object.h" |
1939 | ||
771fe6b9 | 1940 | #endif |