Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
60063497 | 63 | #include <linux/atomic.h> |
771fe6b9 JG |
64 | #include <linux/wait.h> |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
147666fb | 72 | #include <ttm/ttm_execbuf_util.h> |
4c788679 | 73 | |
c2142715 | 74 | #include "radeon_family.h" |
771fe6b9 JG |
75 | #include "radeon_mode.h" |
76 | #include "radeon_reg.h" | |
771fe6b9 JG |
77 | |
78 | /* | |
79 | * Modules parameters. | |
80 | */ | |
81 | extern int radeon_no_wb; | |
82 | extern int radeon_modeset; | |
83 | extern int radeon_dynclks; | |
84 | extern int radeon_r4xx_atom; | |
85 | extern int radeon_agpmode; | |
86 | extern int radeon_vram_limit; | |
87 | extern int radeon_gart_size; | |
88 | extern int radeon_benchmarking; | |
ecc0b326 | 89 | extern int radeon_testing; |
771fe6b9 | 90 | extern int radeon_connector_table; |
4ce001ab | 91 | extern int radeon_tv; |
dafc3bd5 | 92 | extern int radeon_audio; |
f46c0120 | 93 | extern int radeon_disp_priority; |
e2b0a8e1 | 94 | extern int radeon_hw_i2c; |
d42dd579 | 95 | extern int radeon_pcie_gen2; |
a18cee15 | 96 | extern int radeon_msi; |
3368ff0c | 97 | extern int radeon_lockup_timeout; |
a0a53aa8 | 98 | extern int radeon_fastfb; |
771fe6b9 JG |
99 | |
100 | /* | |
101 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
102 | * symbol; | |
103 | */ | |
bb635567 JG |
104 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
105 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
e821767b | 106 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
bb635567 JG |
107 | #define RADEON_IB_POOL_SIZE 16 |
108 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 | |
109 | #define RADEONFB_CONN_LIMIT 4 | |
110 | #define RADEON_BIOS_NUM_SCRATCH 8 | |
771fe6b9 | 111 | |
1b37078b | 112 | /* max number of rings */ |
f2ba57b5 | 113 | #define RADEON_NUM_RINGS 6 |
bb635567 JG |
114 | |
115 | /* fence seq are set to this number when signaled */ | |
116 | #define RADEON_FENCE_SIGNALED_SEQ 0LL | |
1b37078b AD |
117 | |
118 | /* internal ring indices */ | |
119 | /* r1xx+ has gfx CP ring */ | |
f2ba57b5 | 120 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
1b37078b AD |
121 | |
122 | /* cayman has 2 compute CP rings */ | |
f2ba57b5 CK |
123 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
124 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 | |
1b37078b | 125 | |
4d75658b AD |
126 | /* R600+ has an async dma ring */ |
127 | #define R600_RING_TYPE_DMA_INDEX 3 | |
f60cbd11 AD |
128 | /* cayman add a second async dma ring */ |
129 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 | |
4d75658b | 130 | |
f2ba57b5 CK |
131 | /* R600+ */ |
132 | #define R600_RING_TYPE_UVD_INDEX 5 | |
133 | ||
721604a1 | 134 | /* hardcode those limit for now */ |
ca19f21e | 135 | #define RADEON_VA_IB_OFFSET (1 << 20) |
bb635567 JG |
136 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
137 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) | |
721604a1 | 138 | |
ec46c76d AD |
139 | /* reset flags */ |
140 | #define RADEON_RESET_GFX (1 << 0) | |
141 | #define RADEON_RESET_COMPUTE (1 << 1) | |
142 | #define RADEON_RESET_DMA (1 << 2) | |
9ff0744c AD |
143 | #define RADEON_RESET_CP (1 << 3) |
144 | #define RADEON_RESET_GRBM (1 << 4) | |
145 | #define RADEON_RESET_DMA1 (1 << 5) | |
146 | #define RADEON_RESET_RLC (1 << 6) | |
147 | #define RADEON_RESET_SEM (1 << 7) | |
148 | #define RADEON_RESET_IH (1 << 8) | |
149 | #define RADEON_RESET_VMC (1 << 9) | |
150 | #define RADEON_RESET_MC (1 << 10) | |
151 | #define RADEON_RESET_DISPLAY (1 << 11) | |
ec46c76d | 152 | |
771fe6b9 JG |
153 | /* |
154 | * Errata workarounds. | |
155 | */ | |
156 | enum radeon_pll_errata { | |
157 | CHIP_ERRATA_R300_CG = 0x00000001, | |
158 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
159 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
160 | }; | |
161 | ||
162 | ||
163 | struct radeon_device; | |
164 | ||
165 | ||
166 | /* | |
167 | * BIOS. | |
168 | */ | |
169 | bool radeon_get_bios(struct radeon_device *rdev); | |
170 | ||
171 | /* | |
3ce0a23d | 172 | * Dummy page |
771fe6b9 | 173 | */ |
3ce0a23d JG |
174 | struct radeon_dummy_page { |
175 | struct page *page; | |
176 | dma_addr_t addr; | |
177 | }; | |
178 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
179 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
180 | ||
771fe6b9 | 181 | |
3ce0a23d JG |
182 | /* |
183 | * Clocks | |
184 | */ | |
771fe6b9 JG |
185 | struct radeon_clock { |
186 | struct radeon_pll p1pll; | |
187 | struct radeon_pll p2pll; | |
bcc1c2a1 | 188 | struct radeon_pll dcpll; |
771fe6b9 JG |
189 | struct radeon_pll spll; |
190 | struct radeon_pll mpll; | |
191 | /* 10 Khz units */ | |
192 | uint32_t default_mclk; | |
193 | uint32_t default_sclk; | |
bcc1c2a1 AD |
194 | uint32_t default_dispclk; |
195 | uint32_t dp_extclk; | |
b20f9bef | 196 | uint32_t max_pixel_clock; |
771fe6b9 JG |
197 | }; |
198 | ||
7433874e RM |
199 | /* |
200 | * Power management | |
201 | */ | |
202 | int radeon_pm_init(struct radeon_device *rdev); | |
29fb52ca | 203 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 204 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
ce8f5370 AD |
205 | void radeon_pm_suspend(struct radeon_device *rdev); |
206 | void radeon_pm_resume(struct radeon_device *rdev); | |
56278a8e AD |
207 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
208 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
8a83ec5e | 209 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
f892034a | 210 | void rs690_pm_info(struct radeon_device *rdev); |
20d391d7 AD |
211 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
212 | extern int rv770_get_temp(struct radeon_device *rdev); | |
213 | extern int evergreen_get_temp(struct radeon_device *rdev); | |
214 | extern int sumo_get_temp(struct radeon_device *rdev); | |
1bd47d2e | 215 | extern int si_get_temp(struct radeon_device *rdev); |
285484e2 JG |
216 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
217 | unsigned *bankh, unsigned *mtaspect, | |
218 | unsigned *tile_split); | |
3ce0a23d | 219 | |
771fe6b9 JG |
220 | /* |
221 | * Fences. | |
222 | */ | |
223 | struct radeon_fence_driver { | |
224 | uint32_t scratch_reg; | |
30eb77f4 JG |
225 | uint64_t gpu_addr; |
226 | volatile uint32_t *cpu_addr; | |
68e250b7 CK |
227 | /* sync_seq is protected by ring emission lock */ |
228 | uint64_t sync_seq[RADEON_NUM_RINGS]; | |
bb635567 | 229 | atomic64_t last_seq; |
36abacae | 230 | unsigned long last_activity; |
0a0c7596 | 231 | bool initialized; |
771fe6b9 JG |
232 | }; |
233 | ||
234 | struct radeon_fence { | |
235 | struct radeon_device *rdev; | |
236 | struct kref kref; | |
771fe6b9 | 237 | /* protected by radeon_fence.lock */ |
bb635567 | 238 | uint64_t seq; |
7465280c | 239 | /* RB, DMA, etc. */ |
bb635567 | 240 | unsigned ring; |
771fe6b9 JG |
241 | }; |
242 | ||
30eb77f4 JG |
243 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
244 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
771fe6b9 | 245 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
76903b96 | 246 | void radeon_fence_driver_force_completion(struct radeon_device *rdev); |
876dc9f3 | 247 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
7465280c | 248 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
771fe6b9 JG |
249 | bool radeon_fence_signaled(struct radeon_fence *fence); |
250 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
8a47cc9e | 251 | int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); |
5f8f635e | 252 | int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); |
0085c950 JG |
253 | int radeon_fence_wait_any(struct radeon_device *rdev, |
254 | struct radeon_fence **fences, | |
255 | bool intr); | |
771fe6b9 JG |
256 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
257 | void radeon_fence_unref(struct radeon_fence **fence); | |
3b7a2b24 | 258 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
68e250b7 CK |
259 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
260 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); | |
261 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, | |
262 | struct radeon_fence *b) | |
263 | { | |
264 | if (!a) { | |
265 | return b; | |
266 | } | |
267 | ||
268 | if (!b) { | |
269 | return a; | |
270 | } | |
271 | ||
272 | BUG_ON(a->ring != b->ring); | |
273 | ||
274 | if (a->seq > b->seq) { | |
275 | return a; | |
276 | } else { | |
277 | return b; | |
278 | } | |
279 | } | |
771fe6b9 | 280 | |
ee60e29f CK |
281 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
282 | struct radeon_fence *b) | |
283 | { | |
284 | if (!a) { | |
285 | return false; | |
286 | } | |
287 | ||
288 | if (!b) { | |
289 | return true; | |
290 | } | |
291 | ||
292 | BUG_ON(a->ring != b->ring); | |
293 | ||
294 | return a->seq < b->seq; | |
295 | } | |
296 | ||
e024e110 DA |
297 | /* |
298 | * Tiling registers | |
299 | */ | |
300 | struct radeon_surface_reg { | |
4c788679 | 301 | struct radeon_bo *bo; |
e024e110 DA |
302 | }; |
303 | ||
304 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
305 | |
306 | /* | |
4c788679 | 307 | * TTM. |
771fe6b9 | 308 | */ |
4c788679 JG |
309 | struct radeon_mman { |
310 | struct ttm_bo_global_ref bo_global_ref; | |
ba4420c2 | 311 | struct drm_global_reference mem_global_ref; |
4c788679 | 312 | struct ttm_bo_device bdev; |
0a0c7596 JG |
313 | bool mem_global_referenced; |
314 | bool initialized; | |
4c788679 JG |
315 | }; |
316 | ||
721604a1 JG |
317 | /* bo virtual address in a specific vm */ |
318 | struct radeon_bo_va { | |
e971bd5e | 319 | /* protected by bo being reserved */ |
721604a1 | 320 | struct list_head bo_list; |
721604a1 JG |
321 | uint64_t soffset; |
322 | uint64_t eoffset; | |
323 | uint32_t flags; | |
324 | bool valid; | |
e971bd5e CK |
325 | unsigned ref_count; |
326 | ||
327 | /* protected by vm mutex */ | |
328 | struct list_head vm_list; | |
329 | ||
330 | /* constant after initialization */ | |
331 | struct radeon_vm *vm; | |
332 | struct radeon_bo *bo; | |
721604a1 JG |
333 | }; |
334 | ||
4c788679 JG |
335 | struct radeon_bo { |
336 | /* Protected by gem.mutex */ | |
337 | struct list_head list; | |
338 | /* Protected by tbo.reserved */ | |
312ea8da JG |
339 | u32 placements[3]; |
340 | struct ttm_placement placement; | |
4c788679 JG |
341 | struct ttm_buffer_object tbo; |
342 | struct ttm_bo_kmap_obj kmap; | |
343 | unsigned pin_count; | |
344 | void *kptr; | |
345 | u32 tiling_flags; | |
346 | u32 pitch; | |
347 | int surface_reg; | |
721604a1 JG |
348 | /* list of all virtual address to which this bo |
349 | * is associated to | |
350 | */ | |
351 | struct list_head va; | |
4c788679 JG |
352 | /* Constant after initialization */ |
353 | struct radeon_device *rdev; | |
441921d5 | 354 | struct drm_gem_object gem_base; |
63bc620b DA |
355 | |
356 | struct ttm_bo_kmap_obj dma_buf_vmap; | |
4c788679 | 357 | }; |
7e4d15d9 | 358 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
771fe6b9 | 359 | |
4c788679 | 360 | struct radeon_bo_list { |
147666fb | 361 | struct ttm_validate_buffer tv; |
4c788679 | 362 | struct radeon_bo *bo; |
771fe6b9 | 363 | uint64_t gpu_offset; |
4474f3a9 CK |
364 | bool written; |
365 | unsigned domain; | |
366 | unsigned alt_domain; | |
4c788679 | 367 | u32 tiling_flags; |
771fe6b9 JG |
368 | }; |
369 | ||
b15ba512 JG |
370 | /* sub-allocation manager, it has to be protected by another lock. |
371 | * By conception this is an helper for other part of the driver | |
372 | * like the indirect buffer or semaphore, which both have their | |
373 | * locking. | |
374 | * | |
375 | * Principe is simple, we keep a list of sub allocation in offset | |
376 | * order (first entry has offset == 0, last entry has the highest | |
377 | * offset). | |
378 | * | |
379 | * When allocating new object we first check if there is room at | |
380 | * the end total_size - (last_object_offset + last_object_size) >= | |
381 | * alloc_size. If so we allocate new object there. | |
382 | * | |
383 | * When there is not enough room at the end, we start waiting for | |
384 | * each sub object until we reach object_offset+object_size >= | |
385 | * alloc_size, this object then become the sub object we return. | |
386 | * | |
387 | * Alignment can't be bigger than page size. | |
388 | * | |
389 | * Hole are not considered for allocation to keep things simple. | |
390 | * Assumption is that there won't be hole (all object on same | |
391 | * alignment). | |
392 | */ | |
393 | struct radeon_sa_manager { | |
bfb38d35 | 394 | wait_queue_head_t wq; |
b15ba512 | 395 | struct radeon_bo *bo; |
c3b7fe8b CK |
396 | struct list_head *hole; |
397 | struct list_head flist[RADEON_NUM_RINGS]; | |
398 | struct list_head olist; | |
b15ba512 JG |
399 | unsigned size; |
400 | uint64_t gpu_addr; | |
401 | void *cpu_ptr; | |
402 | uint32_t domain; | |
403 | }; | |
404 | ||
405 | struct radeon_sa_bo; | |
406 | ||
407 | /* sub-allocation buffer */ | |
408 | struct radeon_sa_bo { | |
c3b7fe8b CK |
409 | struct list_head olist; |
410 | struct list_head flist; | |
b15ba512 | 411 | struct radeon_sa_manager *manager; |
e6661a96 CK |
412 | unsigned soffset; |
413 | unsigned eoffset; | |
557017a0 | 414 | struct radeon_fence *fence; |
b15ba512 JG |
415 | }; |
416 | ||
771fe6b9 JG |
417 | /* |
418 | * GEM objects. | |
419 | */ | |
420 | struct radeon_gem { | |
4c788679 | 421 | struct mutex mutex; |
771fe6b9 JG |
422 | struct list_head objects; |
423 | }; | |
424 | ||
425 | int radeon_gem_init(struct radeon_device *rdev); | |
426 | void radeon_gem_fini(struct radeon_device *rdev); | |
427 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
428 | int alignment, int initial_domain, |
429 | bool discardable, bool kernel, | |
430 | struct drm_gem_object **obj); | |
771fe6b9 | 431 | |
ff72145b DA |
432 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
433 | struct drm_device *dev, | |
434 | struct drm_mode_create_dumb *args); | |
435 | int radeon_mode_dumb_mmap(struct drm_file *filp, | |
436 | struct drm_device *dev, | |
437 | uint32_t handle, uint64_t *offset_p); | |
438 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, | |
439 | struct drm_device *dev, | |
440 | uint32_t handle); | |
771fe6b9 | 441 | |
c1341e52 JG |
442 | /* |
443 | * Semaphores. | |
444 | */ | |
c1341e52 JG |
445 | /* everything here is constant */ |
446 | struct radeon_semaphore { | |
a8c05940 JG |
447 | struct radeon_sa_bo *sa_bo; |
448 | signed waiters; | |
c1341e52 | 449 | uint64_t gpu_addr; |
c1341e52 JG |
450 | }; |
451 | ||
c1341e52 JG |
452 | int radeon_semaphore_create(struct radeon_device *rdev, |
453 | struct radeon_semaphore **semaphore); | |
454 | void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, | |
455 | struct radeon_semaphore *semaphore); | |
456 | void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, | |
457 | struct radeon_semaphore *semaphore); | |
8f676c4c CK |
458 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
459 | struct radeon_semaphore *semaphore, | |
220907d9 | 460 | int signaler, int waiter); |
c1341e52 | 461 | void radeon_semaphore_free(struct radeon_device *rdev, |
220907d9 | 462 | struct radeon_semaphore **semaphore, |
a8c05940 | 463 | struct radeon_fence *fence); |
c1341e52 | 464 | |
771fe6b9 JG |
465 | /* |
466 | * GART structures, functions & helpers | |
467 | */ | |
468 | struct radeon_mc; | |
469 | ||
a77f1718 | 470 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 471 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
003cefe0 | 472 | #define RADEON_GPU_PAGE_SHIFT 12 |
721604a1 | 473 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
a77f1718 | 474 | |
771fe6b9 JG |
475 | struct radeon_gart { |
476 | dma_addr_t table_addr; | |
c9a1be96 JG |
477 | struct radeon_bo *robj; |
478 | void *ptr; | |
771fe6b9 JG |
479 | unsigned num_gpu_pages; |
480 | unsigned num_cpu_pages; | |
481 | unsigned table_size; | |
771fe6b9 JG |
482 | struct page **pages; |
483 | dma_addr_t *pages_addr; | |
484 | bool ready; | |
485 | }; | |
486 | ||
487 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
488 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
489 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
490 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
c9a1be96 JG |
491 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
492 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); | |
771fe6b9 JG |
493 | int radeon_gart_init(struct radeon_device *rdev); |
494 | void radeon_gart_fini(struct radeon_device *rdev); | |
495 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
496 | int pages); | |
497 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
c39d3516 KRW |
498 | int pages, struct page **pagelist, |
499 | dma_addr_t *dma_addr); | |
c9a1be96 | 500 | void radeon_gart_restore(struct radeon_device *rdev); |
771fe6b9 JG |
501 | |
502 | ||
503 | /* | |
504 | * GPU MC structures, functions & helpers | |
505 | */ | |
506 | struct radeon_mc { | |
507 | resource_size_t aper_size; | |
508 | resource_size_t aper_base; | |
509 | resource_size_t agp_base; | |
7a50f01a DA |
510 | /* for some chips with <= 32MB we need to lie |
511 | * about vram size near mc fb location */ | |
3ce0a23d | 512 | u64 mc_vram_size; |
d594e46a | 513 | u64 visible_vram_size; |
3ce0a23d JG |
514 | u64 gtt_size; |
515 | u64 gtt_start; | |
516 | u64 gtt_end; | |
3ce0a23d JG |
517 | u64 vram_start; |
518 | u64 vram_end; | |
771fe6b9 | 519 | unsigned vram_width; |
3ce0a23d | 520 | u64 real_vram_size; |
771fe6b9 JG |
521 | int vram_mtrr; |
522 | bool vram_is_ddr; | |
d594e46a | 523 | bool igp_sideport_enabled; |
8d369bb1 | 524 | u64 gtt_base_align; |
9ed8b1f9 | 525 | u64 mc_mask; |
771fe6b9 JG |
526 | }; |
527 | ||
06b6476d AD |
528 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
529 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
530 | |
531 | /* | |
532 | * GPU scratch registers structures, functions & helpers | |
533 | */ | |
534 | struct radeon_scratch { | |
535 | unsigned num_reg; | |
724c80e1 | 536 | uint32_t reg_base; |
771fe6b9 JG |
537 | bool free[32]; |
538 | uint32_t reg[32]; | |
539 | }; | |
540 | ||
541 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
542 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
543 | ||
544 | ||
545 | /* | |
546 | * IRQS. | |
547 | */ | |
6f34be50 AD |
548 | |
549 | struct radeon_unpin_work { | |
550 | struct work_struct work; | |
551 | struct radeon_device *rdev; | |
552 | int crtc_id; | |
553 | struct radeon_fence *fence; | |
554 | struct drm_pending_vblank_event *event; | |
555 | struct radeon_bo *old_rbo; | |
556 | u64 new_crtc_base; | |
557 | }; | |
558 | ||
559 | struct r500_irq_stat_regs { | |
560 | u32 disp_int; | |
f122c610 | 561 | u32 hdmi0_status; |
6f34be50 AD |
562 | }; |
563 | ||
564 | struct r600_irq_stat_regs { | |
565 | u32 disp_int; | |
566 | u32 disp_int_cont; | |
567 | u32 disp_int_cont2; | |
568 | u32 d1grph_int; | |
569 | u32 d2grph_int; | |
f122c610 AD |
570 | u32 hdmi0_status; |
571 | u32 hdmi1_status; | |
6f34be50 AD |
572 | }; |
573 | ||
574 | struct evergreen_irq_stat_regs { | |
575 | u32 disp_int; | |
576 | u32 disp_int_cont; | |
577 | u32 disp_int_cont2; | |
578 | u32 disp_int_cont3; | |
579 | u32 disp_int_cont4; | |
580 | u32 disp_int_cont5; | |
581 | u32 d1grph_int; | |
582 | u32 d2grph_int; | |
583 | u32 d3grph_int; | |
584 | u32 d4grph_int; | |
585 | u32 d5grph_int; | |
586 | u32 d6grph_int; | |
f122c610 AD |
587 | u32 afmt_status1; |
588 | u32 afmt_status2; | |
589 | u32 afmt_status3; | |
590 | u32 afmt_status4; | |
591 | u32 afmt_status5; | |
592 | u32 afmt_status6; | |
6f34be50 AD |
593 | }; |
594 | ||
595 | union radeon_irq_stat_regs { | |
596 | struct r500_irq_stat_regs r500; | |
597 | struct r600_irq_stat_regs r600; | |
598 | struct evergreen_irq_stat_regs evergreen; | |
599 | }; | |
600 | ||
54bd5206 IH |
601 | #define RADEON_MAX_HPD_PINS 6 |
602 | #define RADEON_MAX_CRTCS 6 | |
f122c610 | 603 | #define RADEON_MAX_AFMT_BLOCKS 6 |
54bd5206 | 604 | |
771fe6b9 | 605 | struct radeon_irq { |
fb98257a CK |
606 | bool installed; |
607 | spinlock_t lock; | |
736fc37f | 608 | atomic_t ring_int[RADEON_NUM_RINGS]; |
fb98257a | 609 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
736fc37f | 610 | atomic_t pflip[RADEON_MAX_CRTCS]; |
fb98257a CK |
611 | wait_queue_head_t vblank_queue; |
612 | bool hpd[RADEON_MAX_HPD_PINS]; | |
fb98257a CK |
613 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
614 | union radeon_irq_stat_regs stat_regs; | |
771fe6b9 JG |
615 | }; |
616 | ||
617 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
618 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1b37078b AD |
619 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
620 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); | |
6f34be50 AD |
621 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
622 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); | |
fb98257a CK |
623 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
624 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); | |
625 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
626 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
771fe6b9 JG |
627 | |
628 | /* | |
e32eb50d | 629 | * CP & rings. |
771fe6b9 | 630 | */ |
7465280c | 631 | |
771fe6b9 | 632 | struct radeon_ib { |
68470ae7 JG |
633 | struct radeon_sa_bo *sa_bo; |
634 | uint32_t length_dw; | |
635 | uint64_t gpu_addr; | |
636 | uint32_t *ptr; | |
876dc9f3 | 637 | int ring; |
68470ae7 | 638 | struct radeon_fence *fence; |
4bf3dd92 | 639 | struct radeon_vm *vm; |
68470ae7 | 640 | bool is_const_ib; |
220907d9 | 641 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
68470ae7 | 642 | struct radeon_semaphore *semaphore; |
771fe6b9 JG |
643 | }; |
644 | ||
e32eb50d | 645 | struct radeon_ring { |
4c788679 | 646 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
647 | volatile uint32_t *ring; |
648 | unsigned rptr; | |
5596a9db CK |
649 | unsigned rptr_offs; |
650 | unsigned rptr_reg; | |
45df6803 | 651 | unsigned rptr_save_reg; |
89d35807 AD |
652 | u64 next_rptr_gpu_addr; |
653 | volatile u32 *next_rptr_cpu_addr; | |
771fe6b9 JG |
654 | unsigned wptr; |
655 | unsigned wptr_old; | |
5596a9db | 656 | unsigned wptr_reg; |
771fe6b9 JG |
657 | unsigned ring_size; |
658 | unsigned ring_free_dw; | |
659 | int count_dw; | |
069211e5 CK |
660 | unsigned long last_activity; |
661 | unsigned last_rptr; | |
771fe6b9 JG |
662 | uint64_t gpu_addr; |
663 | uint32_t align_mask; | |
664 | uint32_t ptr_mask; | |
771fe6b9 | 665 | bool ready; |
78c5560a AD |
666 | u32 ptr_reg_shift; |
667 | u32 ptr_reg_mask; | |
668 | u32 nop; | |
8b25ed34 | 669 | u32 idx; |
5f0839c1 JG |
670 | u64 last_semaphore_signal_addr; |
671 | u64 last_semaphore_wait_addr; | |
771fe6b9 JG |
672 | }; |
673 | ||
721604a1 JG |
674 | /* |
675 | * VM | |
676 | */ | |
ee60e29f | 677 | |
fa87e62d | 678 | /* maximum number of VMIDs */ |
ee60e29f CK |
679 | #define RADEON_NUM_VM 16 |
680 | ||
fa87e62d DC |
681 | /* defines number of bits in page table versus page directory, |
682 | * a page is 4KB so we have 12 bits offset, 9 bits in the page | |
683 | * table and the remaining 19 bits are in the page directory */ | |
684 | #define RADEON_VM_BLOCK_SIZE 9 | |
685 | ||
686 | /* number of entries in page table */ | |
687 | #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) | |
688 | ||
721604a1 JG |
689 | struct radeon_vm { |
690 | struct list_head list; | |
691 | struct list_head va; | |
ee60e29f | 692 | unsigned id; |
90a51a32 CK |
693 | |
694 | /* contains the page directory */ | |
695 | struct radeon_sa_bo *page_directory; | |
696 | uint64_t pd_gpu_addr; | |
697 | ||
698 | /* array of page tables, one for each page directory entry */ | |
699 | struct radeon_sa_bo **page_tables; | |
700 | ||
721604a1 JG |
701 | struct mutex mutex; |
702 | /* last fence for cs using this vm */ | |
703 | struct radeon_fence *fence; | |
9b40e5d8 CK |
704 | /* last flush or NULL if we still need to flush */ |
705 | struct radeon_fence *last_flush; | |
721604a1 JG |
706 | }; |
707 | ||
721604a1 | 708 | struct radeon_vm_manager { |
36ff39c4 | 709 | struct mutex lock; |
721604a1 | 710 | struct list_head lru_vm; |
ee60e29f | 711 | struct radeon_fence *active[RADEON_NUM_VM]; |
721604a1 JG |
712 | struct radeon_sa_manager sa_manager; |
713 | uint32_t max_pfn; | |
721604a1 JG |
714 | /* number of VMIDs */ |
715 | unsigned nvm; | |
716 | /* vram base address for page table entry */ | |
717 | u64 vram_base_offset; | |
67e915e4 AD |
718 | /* is vm enabled? */ |
719 | bool enabled; | |
721604a1 JG |
720 | }; |
721 | ||
722 | /* | |
723 | * file private structure | |
724 | */ | |
725 | struct radeon_fpriv { | |
726 | struct radeon_vm vm; | |
727 | }; | |
728 | ||
d8f60cfc AD |
729 | /* |
730 | * R6xx+ IH ring | |
731 | */ | |
732 | struct r600_ih { | |
4c788679 | 733 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
734 | volatile uint32_t *ring; |
735 | unsigned rptr; | |
d8f60cfc AD |
736 | unsigned ring_size; |
737 | uint64_t gpu_addr; | |
d8f60cfc | 738 | uint32_t ptr_mask; |
c20dc369 | 739 | atomic_t lock; |
d8f60cfc AD |
740 | bool enabled; |
741 | }; | |
742 | ||
8eec9d6f IH |
743 | struct r600_blit_cp_primitives { |
744 | void (*set_render_target)(struct radeon_device *rdev, int format, | |
745 | int w, int h, u64 gpu_addr); | |
746 | void (*cp_set_surface_sync)(struct radeon_device *rdev, | |
747 | u32 sync_type, u32 size, | |
748 | u64 mc_addr); | |
749 | void (*set_shaders)(struct radeon_device *rdev); | |
750 | void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); | |
751 | void (*set_tex_resource)(struct radeon_device *rdev, | |
752 | int format, int w, int h, int pitch, | |
9bb7703c | 753 | u64 gpu_addr, u32 size); |
8eec9d6f IH |
754 | void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, |
755 | int x2, int y2); | |
756 | void (*draw_auto)(struct radeon_device *rdev); | |
757 | void (*set_default_state)(struct radeon_device *rdev); | |
758 | }; | |
759 | ||
3ce0a23d | 760 | struct r600_blit { |
4c788679 | 761 | struct radeon_bo *shader_obj; |
8eec9d6f IH |
762 | struct r600_blit_cp_primitives primitives; |
763 | int max_dim; | |
764 | int ring_size_common; | |
765 | int ring_size_per_loop; | |
3ce0a23d JG |
766 | u64 shader_gpu_addr; |
767 | u32 vs_offset, ps_offset; | |
768 | u32 state_offset; | |
769 | u32 state_len; | |
3ce0a23d JG |
770 | }; |
771 | ||
347e7592 AD |
772 | /* |
773 | * SI RLC stuff | |
774 | */ | |
775 | struct si_rlc { | |
776 | /* for power gating */ | |
777 | struct radeon_bo *save_restore_obj; | |
778 | uint64_t save_restore_gpu_addr; | |
779 | /* for clear state */ | |
780 | struct radeon_bo *clear_state_obj; | |
781 | uint64_t clear_state_gpu_addr; | |
782 | }; | |
783 | ||
69e130a6 | 784 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
785 | struct radeon_ib *ib, struct radeon_vm *vm, |
786 | unsigned size); | |
f2e39221 | 787 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
43f1214a | 788 | void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence); |
4ef72566 CK |
789 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
790 | struct radeon_ib *const_ib); | |
771fe6b9 JG |
791 | int radeon_ib_pool_init(struct radeon_device *rdev); |
792 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
7bd560e8 | 793 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
771fe6b9 | 794 | /* Ring access between begin & end cannot sleep */ |
89d35807 AD |
795 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
796 | struct radeon_ring *ring); | |
e32eb50d CK |
797 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
798 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
799 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
800 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
801 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
d6999bc7 | 802 | void radeon_ring_undo(struct radeon_ring *ring); |
e32eb50d CK |
803 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
804 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); | |
7b9ef16b | 805 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); |
069211e5 CK |
806 | void radeon_ring_lockup_update(struct radeon_ring *ring); |
807 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
55d7c221 CK |
808 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
809 | uint32_t **data); | |
810 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
811 | unsigned size, uint32_t *data); | |
e32eb50d | 812 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
78c5560a AD |
813 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
814 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); | |
e32eb50d | 815 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
771fe6b9 JG |
816 | |
817 | ||
4d75658b AD |
818 | /* r600 async dma */ |
819 | void r600_dma_stop(struct radeon_device *rdev); | |
820 | int r600_dma_resume(struct radeon_device *rdev); | |
821 | void r600_dma_fini(struct radeon_device *rdev); | |
822 | ||
8c5fd7ef AD |
823 | void cayman_dma_stop(struct radeon_device *rdev); |
824 | int cayman_dma_resume(struct radeon_device *rdev); | |
825 | void cayman_dma_fini(struct radeon_device *rdev); | |
826 | ||
771fe6b9 JG |
827 | /* |
828 | * CS. | |
829 | */ | |
830 | struct radeon_cs_reloc { | |
831 | struct drm_gem_object *gobj; | |
4c788679 JG |
832 | struct radeon_bo *robj; |
833 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
834 | uint32_t handle; |
835 | uint32_t flags; | |
836 | }; | |
837 | ||
838 | struct radeon_cs_chunk { | |
839 | uint32_t chunk_id; | |
840 | uint32_t length_dw; | |
721604a1 JG |
841 | int kpage_idx[2]; |
842 | uint32_t *kpage[2]; | |
771fe6b9 | 843 | uint32_t *kdata; |
721604a1 JG |
844 | void __user *user_ptr; |
845 | int last_copied_page; | |
846 | int last_page_index; | |
771fe6b9 JG |
847 | }; |
848 | ||
849 | struct radeon_cs_parser { | |
c8c15ff1 | 850 | struct device *dev; |
771fe6b9 JG |
851 | struct radeon_device *rdev; |
852 | struct drm_file *filp; | |
853 | /* chunks */ | |
854 | unsigned nchunks; | |
855 | struct radeon_cs_chunk *chunks; | |
856 | uint64_t *chunks_array; | |
857 | /* IB */ | |
858 | unsigned idx; | |
859 | /* relocations */ | |
860 | unsigned nrelocs; | |
861 | struct radeon_cs_reloc *relocs; | |
862 | struct radeon_cs_reloc **relocs_ptr; | |
863 | struct list_head validated; | |
cf4ccd01 | 864 | unsigned dma_reloc_idx; |
771fe6b9 JG |
865 | /* indices of various chunks */ |
866 | int chunk_ib_idx; | |
867 | int chunk_relocs_idx; | |
721604a1 | 868 | int chunk_flags_idx; |
dfcf5f36 | 869 | int chunk_const_ib_idx; |
f2e39221 JG |
870 | struct radeon_ib ib; |
871 | struct radeon_ib const_ib; | |
771fe6b9 | 872 | void *track; |
3ce0a23d | 873 | unsigned family; |
e70f224c | 874 | int parser_error; |
721604a1 JG |
875 | u32 cs_flags; |
876 | u32 ring; | |
877 | s32 priority; | |
771fe6b9 JG |
878 | }; |
879 | ||
513bcb46 | 880 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
ce580fab | 881 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
513bcb46 | 882 | |
771fe6b9 JG |
883 | struct radeon_cs_packet { |
884 | unsigned idx; | |
885 | unsigned type; | |
886 | unsigned reg; | |
887 | unsigned opcode; | |
888 | int count; | |
889 | unsigned one_reg_wr; | |
890 | }; | |
891 | ||
892 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
893 | struct radeon_cs_packet *pkt, | |
894 | unsigned idx, unsigned reg); | |
895 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
896 | struct radeon_cs_packet *pkt); | |
897 | ||
898 | ||
899 | /* | |
900 | * AGP | |
901 | */ | |
902 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 903 | void radeon_agp_resume(struct radeon_device *rdev); |
10b06122 | 904 | void radeon_agp_suspend(struct radeon_device *rdev); |
771fe6b9 JG |
905 | void radeon_agp_fini(struct radeon_device *rdev); |
906 | ||
907 | ||
908 | /* | |
909 | * Writeback | |
910 | */ | |
911 | struct radeon_wb { | |
4c788679 | 912 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
913 | volatile uint32_t *wb; |
914 | uint64_t gpu_addr; | |
724c80e1 | 915 | bool enabled; |
d0f8a854 | 916 | bool use_event; |
771fe6b9 JG |
917 | }; |
918 | ||
724c80e1 | 919 | #define RADEON_WB_SCRATCH_OFFSET 0 |
89d35807 | 920 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
724c80e1 | 921 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
0c88a02e AD |
922 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
923 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 | |
4d75658b | 924 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
724c80e1 | 925 | #define R600_WB_IH_WPTR_OFFSET 2048 |
f60cbd11 | 926 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
f2ba57b5 | 927 | #define R600_WB_UVD_RPTR_OFFSET 2560 |
d0f8a854 | 928 | #define R600_WB_EVENT_OFFSET 3072 |
724c80e1 | 929 | |
c93bb85b JG |
930 | /** |
931 | * struct radeon_pm - power management datas | |
932 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
933 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
934 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
935 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
936 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
937 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
938 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
939 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
940 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
25985edc | 941 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
c93bb85b JG |
942 | * @needed_bandwidth: current bandwidth needs |
943 | * | |
944 | * It keeps track of various data needed to take powermanagement decision. | |
25985edc | 945 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
c93bb85b JG |
946 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
947 | * (type of memory, bus size, efficiency, ...) | |
948 | */ | |
ce8f5370 AD |
949 | |
950 | enum radeon_pm_method { | |
951 | PM_METHOD_PROFILE, | |
952 | PM_METHOD_DYNPM, | |
953 | }; | |
954 | ||
955 | enum radeon_dynpm_state { | |
956 | DYNPM_STATE_DISABLED, | |
957 | DYNPM_STATE_MINIMUM, | |
958 | DYNPM_STATE_PAUSED, | |
3f53eb6f RW |
959 | DYNPM_STATE_ACTIVE, |
960 | DYNPM_STATE_SUSPENDED, | |
c913e23a | 961 | }; |
ce8f5370 AD |
962 | enum radeon_dynpm_action { |
963 | DYNPM_ACTION_NONE, | |
964 | DYNPM_ACTION_MINIMUM, | |
965 | DYNPM_ACTION_DOWNCLOCK, | |
966 | DYNPM_ACTION_UPCLOCK, | |
967 | DYNPM_ACTION_DEFAULT | |
c913e23a | 968 | }; |
56278a8e AD |
969 | |
970 | enum radeon_voltage_type { | |
971 | VOLTAGE_NONE = 0, | |
972 | VOLTAGE_GPIO, | |
973 | VOLTAGE_VDDC, | |
974 | VOLTAGE_SW | |
975 | }; | |
976 | ||
0ec0e74f AD |
977 | enum radeon_pm_state_type { |
978 | POWER_STATE_TYPE_DEFAULT, | |
979 | POWER_STATE_TYPE_POWERSAVE, | |
980 | POWER_STATE_TYPE_BATTERY, | |
981 | POWER_STATE_TYPE_BALANCED, | |
982 | POWER_STATE_TYPE_PERFORMANCE, | |
983 | }; | |
984 | ||
ce8f5370 AD |
985 | enum radeon_pm_profile_type { |
986 | PM_PROFILE_DEFAULT, | |
987 | PM_PROFILE_AUTO, | |
988 | PM_PROFILE_LOW, | |
c9e75b21 | 989 | PM_PROFILE_MID, |
ce8f5370 AD |
990 | PM_PROFILE_HIGH, |
991 | }; | |
992 | ||
993 | #define PM_PROFILE_DEFAULT_IDX 0 | |
994 | #define PM_PROFILE_LOW_SH_IDX 1 | |
c9e75b21 AD |
995 | #define PM_PROFILE_MID_SH_IDX 2 |
996 | #define PM_PROFILE_HIGH_SH_IDX 3 | |
997 | #define PM_PROFILE_LOW_MH_IDX 4 | |
998 | #define PM_PROFILE_MID_MH_IDX 5 | |
999 | #define PM_PROFILE_HIGH_MH_IDX 6 | |
1000 | #define PM_PROFILE_MAX 7 | |
ce8f5370 AD |
1001 | |
1002 | struct radeon_pm_profile { | |
1003 | int dpms_off_ps_idx; | |
1004 | int dpms_on_ps_idx; | |
1005 | int dpms_off_cm_idx; | |
1006 | int dpms_on_cm_idx; | |
516d0e46 AD |
1007 | }; |
1008 | ||
21a8122a AD |
1009 | enum radeon_int_thermal_type { |
1010 | THERMAL_TYPE_NONE, | |
1011 | THERMAL_TYPE_RV6XX, | |
1012 | THERMAL_TYPE_RV770, | |
1013 | THERMAL_TYPE_EVERGREEN, | |
e33df25f | 1014 | THERMAL_TYPE_SUMO, |
4fddba1f | 1015 | THERMAL_TYPE_NI, |
14607d08 | 1016 | THERMAL_TYPE_SI, |
21a8122a AD |
1017 | }; |
1018 | ||
56278a8e AD |
1019 | struct radeon_voltage { |
1020 | enum radeon_voltage_type type; | |
1021 | /* gpio voltage */ | |
1022 | struct radeon_gpio_rec gpio; | |
1023 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
1024 | bool active_high; /* voltage drop is active when bit is high */ | |
1025 | /* VDDC voltage */ | |
1026 | u8 vddc_id; /* index into vddc voltage table */ | |
1027 | u8 vddci_id; /* index into vddci voltage table */ | |
1028 | bool vddci_enabled; | |
1029 | /* r6xx+ sw */ | |
2feea49a AD |
1030 | u16 voltage; |
1031 | /* evergreen+ vddci */ | |
1032 | u16 vddci; | |
56278a8e AD |
1033 | }; |
1034 | ||
d7311171 AD |
1035 | /* clock mode flags */ |
1036 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) | |
1037 | ||
56278a8e AD |
1038 | struct radeon_pm_clock_info { |
1039 | /* memory clock */ | |
1040 | u32 mclk; | |
1041 | /* engine clock */ | |
1042 | u32 sclk; | |
1043 | /* voltage info */ | |
1044 | struct radeon_voltage voltage; | |
d7311171 | 1045 | /* standardized clock flags */ |
56278a8e AD |
1046 | u32 flags; |
1047 | }; | |
1048 | ||
a48b9b4e | 1049 | /* state flags */ |
d7311171 | 1050 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
a48b9b4e | 1051 | |
56278a8e | 1052 | struct radeon_power_state { |
0ec0e74f | 1053 | enum radeon_pm_state_type type; |
8f3f1c9a | 1054 | struct radeon_pm_clock_info *clock_info; |
56278a8e AD |
1055 | /* number of valid clock modes in this power state */ |
1056 | int num_clock_modes; | |
56278a8e | 1057 | struct radeon_pm_clock_info *default_clock_mode; |
a48b9b4e AD |
1058 | /* standardized state flags */ |
1059 | u32 flags; | |
79daedc9 AD |
1060 | u32 misc; /* vbios specific flags */ |
1061 | u32 misc2; /* vbios specific flags */ | |
1062 | int pcie_lanes; /* pcie lanes */ | |
56278a8e AD |
1063 | }; |
1064 | ||
27459324 RM |
1065 | /* |
1066 | * Some modes are overclocked by very low value, accept them | |
1067 | */ | |
1068 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
1069 | ||
c93bb85b | 1070 | struct radeon_pm { |
c913e23a | 1071 | struct mutex mutex; |
db7fce39 CK |
1072 | /* write locked while reprogramming mclk */ |
1073 | struct rw_semaphore mclk_lock; | |
a48b9b4e AD |
1074 | u32 active_crtcs; |
1075 | int active_crtc_count; | |
c913e23a | 1076 | int req_vblank; |
839461d3 | 1077 | bool vblank_sync; |
c93bb85b JG |
1078 | fixed20_12 max_bandwidth; |
1079 | fixed20_12 igp_sideport_mclk; | |
1080 | fixed20_12 igp_system_mclk; | |
1081 | fixed20_12 igp_ht_link_clk; | |
1082 | fixed20_12 igp_ht_link_width; | |
1083 | fixed20_12 k8_bandwidth; | |
1084 | fixed20_12 sideport_bandwidth; | |
1085 | fixed20_12 ht_bandwidth; | |
1086 | fixed20_12 core_bandwidth; | |
1087 | fixed20_12 sclk; | |
f47299c5 | 1088 | fixed20_12 mclk; |
c93bb85b | 1089 | fixed20_12 needed_bandwidth; |
0975b162 | 1090 | struct radeon_power_state *power_state; |
56278a8e AD |
1091 | /* number of valid power states */ |
1092 | int num_power_states; | |
a48b9b4e AD |
1093 | int current_power_state_index; |
1094 | int current_clock_mode_index; | |
1095 | int requested_power_state_index; | |
1096 | int requested_clock_mode_index; | |
1097 | int default_power_state_index; | |
1098 | u32 current_sclk; | |
1099 | u32 current_mclk; | |
2feea49a AD |
1100 | u16 current_vddc; |
1101 | u16 current_vddci; | |
9ace9f7b AD |
1102 | u32 default_sclk; |
1103 | u32 default_mclk; | |
2feea49a AD |
1104 | u16 default_vddc; |
1105 | u16 default_vddci; | |
29fb52ca | 1106 | struct radeon_i2c_chan *i2c_bus; |
ce8f5370 AD |
1107 | /* selected pm method */ |
1108 | enum radeon_pm_method pm_method; | |
1109 | /* dynpm power management */ | |
1110 | struct delayed_work dynpm_idle_work; | |
1111 | enum radeon_dynpm_state dynpm_state; | |
1112 | enum radeon_dynpm_action dynpm_planned_action; | |
1113 | unsigned long dynpm_action_timeout; | |
1114 | bool dynpm_can_upclock; | |
1115 | bool dynpm_can_downclock; | |
1116 | /* profile-based power management */ | |
1117 | enum radeon_pm_profile_type profile; | |
1118 | int profile_index; | |
1119 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; | |
21a8122a AD |
1120 | /* internal thermal controller on rv6xx+ */ |
1121 | enum radeon_int_thermal_type int_thermal_type; | |
1122 | struct device *int_hwmon_dev; | |
c93bb85b JG |
1123 | }; |
1124 | ||
a4c9e2ee AD |
1125 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1126 | enum radeon_pm_state_type ps_type, | |
1127 | int instance); | |
f2ba57b5 CK |
1128 | /* |
1129 | * UVD | |
1130 | */ | |
1131 | #define RADEON_MAX_UVD_HANDLES 10 | |
1132 | #define RADEON_UVD_STACK_SIZE (1024*1024) | |
1133 | #define RADEON_UVD_HEAP_SIZE (1024*1024) | |
1134 | ||
1135 | struct radeon_uvd { | |
1136 | struct radeon_bo *vcpu_bo; | |
1137 | void *cpu_addr; | |
1138 | uint64_t gpu_addr; | |
1139 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; | |
1140 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; | |
1141 | }; | |
1142 | ||
1143 | int radeon_uvd_init(struct radeon_device *rdev); | |
1144 | void radeon_uvd_fini(struct radeon_device *rdev); | |
1145 | int radeon_uvd_suspend(struct radeon_device *rdev); | |
1146 | int radeon_uvd_resume(struct radeon_device *rdev); | |
1147 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, | |
1148 | uint32_t handle, struct radeon_fence **fence); | |
1149 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, | |
1150 | uint32_t handle, struct radeon_fence **fence); | |
1151 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); | |
1152 | void radeon_uvd_free_handles(struct radeon_device *rdev, | |
1153 | struct drm_file *filp); | |
1154 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); | |
771fe6b9 | 1155 | |
a92553ab | 1156 | struct r600_audio { |
a92553ab RM |
1157 | int channels; |
1158 | int rate; | |
1159 | int bits_per_sample; | |
1160 | u8 status_bits; | |
1161 | u8 category_code; | |
1162 | }; | |
1163 | ||
771fe6b9 JG |
1164 | /* |
1165 | * Benchmarking | |
1166 | */ | |
638dd7db | 1167 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
771fe6b9 JG |
1168 | |
1169 | ||
ecc0b326 MD |
1170 | /* |
1171 | * Testing | |
1172 | */ | |
1173 | void radeon_test_moves(struct radeon_device *rdev); | |
60a7e396 | 1174 | void radeon_test_ring_sync(struct radeon_device *rdev, |
e32eb50d CK |
1175 | struct radeon_ring *cpA, |
1176 | struct radeon_ring *cpB); | |
60a7e396 | 1177 | void radeon_test_syncing(struct radeon_device *rdev); |
ecc0b326 MD |
1178 | |
1179 | ||
771fe6b9 JG |
1180 | /* |
1181 | * Debugfs | |
1182 | */ | |
4d8bf9ae CK |
1183 | struct radeon_debugfs { |
1184 | struct drm_info_list *files; | |
1185 | unsigned num_files; | |
1186 | }; | |
1187 | ||
771fe6b9 JG |
1188 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1189 | struct drm_info_list *files, | |
1190 | unsigned nfiles); | |
1191 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 JG |
1192 | |
1193 | ||
1194 | /* | |
1195 | * ASIC specific functions. | |
1196 | */ | |
1197 | struct radeon_asic { | |
068a117c | 1198 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
1199 | void (*fini)(struct radeon_device *rdev); |
1200 | int (*resume)(struct radeon_device *rdev); | |
1201 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 1202 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
a2d07b74 | 1203 | int (*asic_reset)(struct radeon_device *rdev); |
54e88e06 AD |
1204 | /* ioctl hw specific callback. Some hw might want to perform special |
1205 | * operation on specific ioctl. For instance on wait idle some hw | |
1206 | * might want to perform and HDP flush through MMIO as it seems that | |
1207 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
1208 | * through ring. | |
1209 | */ | |
1210 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
1211 | /* check if 3D engine is idle */ | |
1212 | bool (*gui_idle)(struct radeon_device *rdev); | |
1213 | /* wait for mc_idle */ | |
1214 | int (*mc_wait_for_idle)(struct radeon_device *rdev); | |
454d2e2a AD |
1215 | /* get the reference clock */ |
1216 | u32 (*get_xclk)(struct radeon_device *rdev); | |
d0418894 AD |
1217 | /* get the gpu clock counter */ |
1218 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); | |
54e88e06 | 1219 | /* gart */ |
c5b3b850 AD |
1220 | struct { |
1221 | void (*tlb_flush)(struct radeon_device *rdev); | |
1222 | int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
1223 | } gart; | |
05b07147 CK |
1224 | struct { |
1225 | int (*init)(struct radeon_device *rdev); | |
1226 | void (*fini)(struct radeon_device *rdev); | |
2a6f1abb CK |
1227 | |
1228 | u32 pt_ring_index; | |
43f1214a AD |
1229 | void (*set_page)(struct radeon_device *rdev, |
1230 | struct radeon_ib *ib, | |
1231 | uint64_t pe, | |
dce34bfd CK |
1232 | uint64_t addr, unsigned count, |
1233 | uint32_t incr, uint32_t flags); | |
05b07147 | 1234 | } vm; |
54e88e06 | 1235 | /* ring specific callbacks */ |
4c87bc26 CK |
1236 | struct { |
1237 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
721604a1 | 1238 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
4c87bc26 | 1239 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
e32eb50d | 1240 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
4c87bc26 | 1241 | struct radeon_semaphore *semaphore, bool emit_wait); |
eb0c19c5 | 1242 | int (*cs_parse)(struct radeon_cs_parser *p); |
f712812e AD |
1243 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
1244 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1245 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
312c4a8c | 1246 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
498522b4 | 1247 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
4c87bc26 | 1248 | } ring[RADEON_NUM_RINGS]; |
54e88e06 | 1249 | /* irqs */ |
b35ea4ab AD |
1250 | struct { |
1251 | int (*set)(struct radeon_device *rdev); | |
1252 | int (*process)(struct radeon_device *rdev); | |
1253 | } irq; | |
54e88e06 | 1254 | /* displays */ |
c79a49ca AD |
1255 | struct { |
1256 | /* display watermarks */ | |
1257 | void (*bandwidth_update)(struct radeon_device *rdev); | |
1258 | /* get frame count */ | |
1259 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); | |
1260 | /* wait for vblank */ | |
1261 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); | |
37e9b6a6 AD |
1262 | /* set backlight level */ |
1263 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); | |
6d92f81d AD |
1264 | /* get backlight level */ |
1265 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); | |
c79a49ca | 1266 | } display; |
54e88e06 | 1267 | /* copy functions for bo handling */ |
27cd7769 AD |
1268 | struct { |
1269 | int (*blit)(struct radeon_device *rdev, | |
1270 | uint64_t src_offset, | |
1271 | uint64_t dst_offset, | |
1272 | unsigned num_gpu_pages, | |
876dc9f3 | 1273 | struct radeon_fence **fence); |
27cd7769 AD |
1274 | u32 blit_ring_index; |
1275 | int (*dma)(struct radeon_device *rdev, | |
1276 | uint64_t src_offset, | |
1277 | uint64_t dst_offset, | |
1278 | unsigned num_gpu_pages, | |
876dc9f3 | 1279 | struct radeon_fence **fence); |
27cd7769 AD |
1280 | u32 dma_ring_index; |
1281 | /* method used for bo copy */ | |
1282 | int (*copy)(struct radeon_device *rdev, | |
1283 | uint64_t src_offset, | |
1284 | uint64_t dst_offset, | |
1285 | unsigned num_gpu_pages, | |
876dc9f3 | 1286 | struct radeon_fence **fence); |
27cd7769 AD |
1287 | /* ring used for bo copies */ |
1288 | u32 copy_ring_index; | |
1289 | } copy; | |
54e88e06 | 1290 | /* surfaces */ |
9e6f3d02 AD |
1291 | struct { |
1292 | int (*set_reg)(struct radeon_device *rdev, int reg, | |
1293 | uint32_t tiling_flags, uint32_t pitch, | |
1294 | uint32_t offset, uint32_t obj_size); | |
1295 | void (*clear_reg)(struct radeon_device *rdev, int reg); | |
1296 | } surface; | |
54e88e06 | 1297 | /* hotplug detect */ |
901ea57d AD |
1298 | struct { |
1299 | void (*init)(struct radeon_device *rdev); | |
1300 | void (*fini)(struct radeon_device *rdev); | |
1301 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1302 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1303 | } hpd; | |
ce8f5370 | 1304 | /* power management */ |
a02fa397 AD |
1305 | struct { |
1306 | void (*misc)(struct radeon_device *rdev); | |
1307 | void (*prepare)(struct radeon_device *rdev); | |
1308 | void (*finish)(struct radeon_device *rdev); | |
1309 | void (*init_profile)(struct radeon_device *rdev); | |
1310 | void (*get_dynpm_state)(struct radeon_device *rdev); | |
798bcf73 AD |
1311 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1312 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); | |
1313 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); | |
1314 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); | |
1315 | int (*get_pcie_lanes)(struct radeon_device *rdev); | |
1316 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); | |
1317 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
a02fa397 | 1318 | } pm; |
6f34be50 | 1319 | /* pageflipping */ |
0f9e006c AD |
1320 | struct { |
1321 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); | |
1322 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
1323 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); | |
1324 | } pflip; | |
771fe6b9 JG |
1325 | }; |
1326 | ||
21f9a437 JG |
1327 | /* |
1328 | * Asic structures | |
1329 | */ | |
551ebd83 | 1330 | struct r100_asic { |
225758d8 JG |
1331 | const unsigned *reg_safe_bm; |
1332 | unsigned reg_safe_bm_size; | |
1333 | u32 hdp_cntl; | |
551ebd83 DA |
1334 | }; |
1335 | ||
21f9a437 | 1336 | struct r300_asic { |
225758d8 JG |
1337 | const unsigned *reg_safe_bm; |
1338 | unsigned reg_safe_bm_size; | |
1339 | u32 resync_scratch; | |
1340 | u32 hdp_cntl; | |
21f9a437 JG |
1341 | }; |
1342 | ||
1343 | struct r600_asic { | |
225758d8 JG |
1344 | unsigned max_pipes; |
1345 | unsigned max_tile_pipes; | |
1346 | unsigned max_simds; | |
1347 | unsigned max_backends; | |
1348 | unsigned max_gprs; | |
1349 | unsigned max_threads; | |
1350 | unsigned max_stack_entries; | |
1351 | unsigned max_hw_contexts; | |
1352 | unsigned max_gs_threads; | |
1353 | unsigned sx_max_export_size; | |
1354 | unsigned sx_max_export_pos_size; | |
1355 | unsigned sx_max_export_smx_size; | |
1356 | unsigned sq_num_cf_insts; | |
1357 | unsigned tiling_nbanks; | |
1358 | unsigned tiling_npipes; | |
1359 | unsigned tiling_group_size; | |
e7aeeba6 | 1360 | unsigned tile_config; |
e55b9422 | 1361 | unsigned backend_map; |
21f9a437 JG |
1362 | }; |
1363 | ||
1364 | struct rv770_asic { | |
225758d8 JG |
1365 | unsigned max_pipes; |
1366 | unsigned max_tile_pipes; | |
1367 | unsigned max_simds; | |
1368 | unsigned max_backends; | |
1369 | unsigned max_gprs; | |
1370 | unsigned max_threads; | |
1371 | unsigned max_stack_entries; | |
1372 | unsigned max_hw_contexts; | |
1373 | unsigned max_gs_threads; | |
1374 | unsigned sx_max_export_size; | |
1375 | unsigned sx_max_export_pos_size; | |
1376 | unsigned sx_max_export_smx_size; | |
1377 | unsigned sq_num_cf_insts; | |
1378 | unsigned sx_num_of_sets; | |
1379 | unsigned sc_prim_fifo_size; | |
1380 | unsigned sc_hiz_tile_fifo_size; | |
1381 | unsigned sc_earlyz_tile_fifo_fize; | |
1382 | unsigned tiling_nbanks; | |
1383 | unsigned tiling_npipes; | |
1384 | unsigned tiling_group_size; | |
e7aeeba6 | 1385 | unsigned tile_config; |
e55b9422 | 1386 | unsigned backend_map; |
21f9a437 JG |
1387 | }; |
1388 | ||
32fcdbf4 AD |
1389 | struct evergreen_asic { |
1390 | unsigned num_ses; | |
1391 | unsigned max_pipes; | |
1392 | unsigned max_tile_pipes; | |
1393 | unsigned max_simds; | |
1394 | unsigned max_backends; | |
1395 | unsigned max_gprs; | |
1396 | unsigned max_threads; | |
1397 | unsigned max_stack_entries; | |
1398 | unsigned max_hw_contexts; | |
1399 | unsigned max_gs_threads; | |
1400 | unsigned sx_max_export_size; | |
1401 | unsigned sx_max_export_pos_size; | |
1402 | unsigned sx_max_export_smx_size; | |
1403 | unsigned sq_num_cf_insts; | |
1404 | unsigned sx_num_of_sets; | |
1405 | unsigned sc_prim_fifo_size; | |
1406 | unsigned sc_hiz_tile_fifo_size; | |
1407 | unsigned sc_earlyz_tile_fifo_size; | |
1408 | unsigned tiling_nbanks; | |
1409 | unsigned tiling_npipes; | |
1410 | unsigned tiling_group_size; | |
e7aeeba6 | 1411 | unsigned tile_config; |
e55b9422 | 1412 | unsigned backend_map; |
32fcdbf4 AD |
1413 | }; |
1414 | ||
fecf1d07 AD |
1415 | struct cayman_asic { |
1416 | unsigned max_shader_engines; | |
1417 | unsigned max_pipes_per_simd; | |
1418 | unsigned max_tile_pipes; | |
1419 | unsigned max_simds_per_se; | |
1420 | unsigned max_backends_per_se; | |
1421 | unsigned max_texture_channel_caches; | |
1422 | unsigned max_gprs; | |
1423 | unsigned max_threads; | |
1424 | unsigned max_gs_threads; | |
1425 | unsigned max_stack_entries; | |
1426 | unsigned sx_num_of_sets; | |
1427 | unsigned sx_max_export_size; | |
1428 | unsigned sx_max_export_pos_size; | |
1429 | unsigned sx_max_export_smx_size; | |
1430 | unsigned max_hw_contexts; | |
1431 | unsigned sq_num_cf_insts; | |
1432 | unsigned sc_prim_fifo_size; | |
1433 | unsigned sc_hiz_tile_fifo_size; | |
1434 | unsigned sc_earlyz_tile_fifo_size; | |
1435 | ||
1436 | unsigned num_shader_engines; | |
1437 | unsigned num_shader_pipes_per_simd; | |
1438 | unsigned num_tile_pipes; | |
1439 | unsigned num_simds_per_se; | |
1440 | unsigned num_backends_per_se; | |
1441 | unsigned backend_disable_mask_per_asic; | |
1442 | unsigned backend_map; | |
1443 | unsigned num_texture_channel_caches; | |
1444 | unsigned mem_max_burst_length_bytes; | |
1445 | unsigned mem_row_size_in_kb; | |
1446 | unsigned shader_engine_tile_size; | |
1447 | unsigned num_gpus; | |
1448 | unsigned multi_gpu_tile_size; | |
1449 | ||
1450 | unsigned tile_config; | |
fecf1d07 AD |
1451 | }; |
1452 | ||
0a96d72b AD |
1453 | struct si_asic { |
1454 | unsigned max_shader_engines; | |
0a96d72b | 1455 | unsigned max_tile_pipes; |
1a8ca750 AD |
1456 | unsigned max_cu_per_sh; |
1457 | unsigned max_sh_per_se; | |
0a96d72b AD |
1458 | unsigned max_backends_per_se; |
1459 | unsigned max_texture_channel_caches; | |
1460 | unsigned max_gprs; | |
1461 | unsigned max_gs_threads; | |
1462 | unsigned max_hw_contexts; | |
1463 | unsigned sc_prim_fifo_size_frontend; | |
1464 | unsigned sc_prim_fifo_size_backend; | |
1465 | unsigned sc_hiz_tile_fifo_size; | |
1466 | unsigned sc_earlyz_tile_fifo_size; | |
1467 | ||
0a96d72b AD |
1468 | unsigned num_tile_pipes; |
1469 | unsigned num_backends_per_se; | |
1470 | unsigned backend_disable_mask_per_asic; | |
1471 | unsigned backend_map; | |
1472 | unsigned num_texture_channel_caches; | |
1473 | unsigned mem_max_burst_length_bytes; | |
1474 | unsigned mem_row_size_in_kb; | |
1475 | unsigned shader_engine_tile_size; | |
1476 | unsigned num_gpus; | |
1477 | unsigned multi_gpu_tile_size; | |
1478 | ||
1479 | unsigned tile_config; | |
0a96d72b AD |
1480 | }; |
1481 | ||
068a117c JG |
1482 | union radeon_asic_config { |
1483 | struct r300_asic r300; | |
551ebd83 | 1484 | struct r100_asic r100; |
3ce0a23d JG |
1485 | struct r600_asic r600; |
1486 | struct rv770_asic rv770; | |
32fcdbf4 | 1487 | struct evergreen_asic evergreen; |
fecf1d07 | 1488 | struct cayman_asic cayman; |
0a96d72b | 1489 | struct si_asic si; |
068a117c JG |
1490 | }; |
1491 | ||
0a10c851 DV |
1492 | /* |
1493 | * asic initizalization from radeon_asic.c | |
1494 | */ | |
1495 | void radeon_agp_disable(struct radeon_device *rdev); | |
1496 | int radeon_asic_init(struct radeon_device *rdev); | |
1497 | ||
771fe6b9 JG |
1498 | |
1499 | /* | |
1500 | * IOCTL. | |
1501 | */ | |
1502 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
1503 | struct drm_file *filp); | |
1504 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
1505 | struct drm_file *filp); | |
1506 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
1507 | struct drm_file *file_priv); | |
1508 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1509 | struct drm_file *file_priv); | |
1510 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1511 | struct drm_file *file_priv); | |
1512 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1513 | struct drm_file *file_priv); | |
1514 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1515 | struct drm_file *filp); | |
1516 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1517 | struct drm_file *filp); | |
1518 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1519 | struct drm_file *filp); | |
1520 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1521 | struct drm_file *filp); | |
721604a1 JG |
1522 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
1523 | struct drm_file *filp); | |
771fe6b9 | 1524 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
e024e110 DA |
1525 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
1526 | struct drm_file *filp); | |
1527 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
1528 | struct drm_file *filp); | |
771fe6b9 | 1529 | |
16cdf04d AD |
1530 | /* VRAM scratch page for HDP bug, default vram page */ |
1531 | struct r600_vram_scratch { | |
87cbf8f2 AD |
1532 | struct radeon_bo *robj; |
1533 | volatile uint32_t *ptr; | |
16cdf04d | 1534 | u64 gpu_addr; |
87cbf8f2 | 1535 | }; |
771fe6b9 | 1536 | |
fd64ca8a LT |
1537 | /* |
1538 | * ACPI | |
1539 | */ | |
1540 | struct radeon_atif_notification_cfg { | |
1541 | bool enabled; | |
1542 | int command_code; | |
1543 | }; | |
1544 | ||
1545 | struct radeon_atif_notifications { | |
1546 | bool display_switch; | |
1547 | bool expansion_mode_change; | |
1548 | bool thermal_state; | |
1549 | bool forced_power_state; | |
1550 | bool system_power_state; | |
1551 | bool display_conf_change; | |
1552 | bool px_gfx_switch; | |
1553 | bool brightness_change; | |
1554 | bool dgpu_display_event; | |
1555 | }; | |
1556 | ||
1557 | struct radeon_atif_functions { | |
1558 | bool system_params; | |
1559 | bool sbios_requests; | |
1560 | bool select_active_disp; | |
1561 | bool lid_state; | |
1562 | bool get_tv_standard; | |
1563 | bool set_tv_standard; | |
1564 | bool get_panel_expansion_mode; | |
1565 | bool set_panel_expansion_mode; | |
1566 | bool temperature_change; | |
1567 | bool graphics_device_types; | |
1568 | }; | |
1569 | ||
1570 | struct radeon_atif { | |
1571 | struct radeon_atif_notifications notifications; | |
1572 | struct radeon_atif_functions functions; | |
1573 | struct radeon_atif_notification_cfg notification_cfg; | |
37e9b6a6 | 1574 | struct radeon_encoder *encoder_for_bl; |
fd64ca8a | 1575 | }; |
7a1619b9 | 1576 | |
e3a15920 AD |
1577 | struct radeon_atcs_functions { |
1578 | bool get_ext_state; | |
1579 | bool pcie_perf_req; | |
1580 | bool pcie_dev_rdy; | |
1581 | bool pcie_bus_width; | |
1582 | }; | |
1583 | ||
1584 | struct radeon_atcs { | |
1585 | struct radeon_atcs_functions functions; | |
1586 | }; | |
1587 | ||
771fe6b9 JG |
1588 | /* |
1589 | * Core structure, functions and helpers. | |
1590 | */ | |
1591 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
1592 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
1593 | ||
1594 | struct radeon_device { | |
9f022ddf | 1595 | struct device *dev; |
771fe6b9 JG |
1596 | struct drm_device *ddev; |
1597 | struct pci_dev *pdev; | |
dee53e7f | 1598 | struct rw_semaphore exclusive_lock; |
771fe6b9 | 1599 | /* ASIC */ |
068a117c | 1600 | union radeon_asic_config config; |
771fe6b9 JG |
1601 | enum radeon_family family; |
1602 | unsigned long flags; | |
1603 | int usec_timeout; | |
1604 | enum radeon_pll_errata pll_errata; | |
1605 | int num_gb_pipes; | |
f779b3e5 | 1606 | int num_z_pipes; |
771fe6b9 JG |
1607 | int disp_priority; |
1608 | /* BIOS */ | |
1609 | uint8_t *bios; | |
1610 | bool is_atom_bios; | |
1611 | uint16_t bios_header_start; | |
4c788679 | 1612 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 1613 | /* Register mmio */ |
4c9bc75c DA |
1614 | resource_size_t rmmio_base; |
1615 | resource_size_t rmmio_size; | |
2c385151 DV |
1616 | /* protects concurrent MM_INDEX/DATA based register access */ |
1617 | spinlock_t mmio_idx_lock; | |
a0533fbf | 1618 | void __iomem *rmmio; |
771fe6b9 JG |
1619 | radeon_rreg_t mc_rreg; |
1620 | radeon_wreg_t mc_wreg; | |
1621 | radeon_rreg_t pll_rreg; | |
1622 | radeon_wreg_t pll_wreg; | |
de1b2898 | 1623 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
1624 | radeon_rreg_t pciep_rreg; |
1625 | radeon_wreg_t pciep_wreg; | |
351a52a2 AD |
1626 | /* io port */ |
1627 | void __iomem *rio_mem; | |
1628 | resource_size_t rio_mem_size; | |
771fe6b9 JG |
1629 | struct radeon_clock clock; |
1630 | struct radeon_mc mc; | |
1631 | struct radeon_gart gart; | |
1632 | struct radeon_mode_info mode_info; | |
1633 | struct radeon_scratch scratch; | |
1634 | struct radeon_mman mman; | |
7465280c | 1635 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
0085c950 | 1636 | wait_queue_head_t fence_queue; |
d6999bc7 | 1637 | struct mutex ring_lock; |
e32eb50d | 1638 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
c507f7ef JG |
1639 | bool ib_pool_ready; |
1640 | struct radeon_sa_manager ring_tmp_bo; | |
771fe6b9 JG |
1641 | struct radeon_irq irq; |
1642 | struct radeon_asic *asic; | |
1643 | struct radeon_gem gem; | |
c93bb85b | 1644 | struct radeon_pm pm; |
f2ba57b5 | 1645 | struct radeon_uvd uvd; |
f657c2a7 | 1646 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 | 1647 | struct radeon_wb wb; |
3ce0a23d | 1648 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
1649 | bool shutdown; |
1650 | bool suspend; | |
ad49f501 | 1651 | bool need_dma32; |
733289c2 | 1652 | bool accel_working; |
a0a53aa8 | 1653 | bool fastfb_working; /* IGP feature*/ |
e024e110 | 1654 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
1655 | const struct firmware *me_fw; /* all family ME firmware */ |
1656 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 1657 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
0af62b01 | 1658 | const struct firmware *mc_fw; /* NI MC firmware */ |
0f0de06c | 1659 | const struct firmware *ce_fw; /* SI CE firmware */ |
f2ba57b5 | 1660 | const struct firmware *uvd_fw; /* UVD firmware */ |
3ce0a23d | 1661 | struct r600_blit r600_blit; |
16cdf04d | 1662 | struct r600_vram_scratch vram_scratch; |
3e5cb98d | 1663 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 1664 | struct r600_ih ih; /* r6/700 interrupt ring */ |
347e7592 | 1665 | struct si_rlc rlc; |
d4877cf2 | 1666 | struct work_struct hotplug_work; |
f122c610 | 1667 | struct work_struct audio_work; |
18917b60 | 1668 | int num_crtc; /* number of crtcs */ |
40bacf16 | 1669 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
3299de95 RM |
1670 | bool audio_enabled; |
1671 | struct r600_audio audio_status; /* audio stuff */ | |
ce8f5370 | 1672 | struct notifier_block acpi_nb; |
9eba4a93 | 1673 | /* only one userspace can use Hyperz features or CMASK at a time */ |
ab9e1f59 | 1674 | struct drm_file *hyperz_filp; |
9eba4a93 | 1675 | struct drm_file *cmask_filp; |
f376b94f AD |
1676 | /* i2c buses */ |
1677 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; | |
4d8bf9ae CK |
1678 | /* debugfs */ |
1679 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; | |
1680 | unsigned debugfs_count; | |
721604a1 JG |
1681 | /* virtual memory */ |
1682 | struct radeon_vm_manager vm_manager; | |
6759a0a7 | 1683 | struct mutex gpu_clock_mutex; |
fd64ca8a LT |
1684 | /* ACPI interface */ |
1685 | struct radeon_atif atif; | |
e3a15920 | 1686 | struct radeon_atcs atcs; |
771fe6b9 JG |
1687 | }; |
1688 | ||
1689 | int radeon_device_init(struct radeon_device *rdev, | |
1690 | struct drm_device *ddev, | |
1691 | struct pci_dev *pdev, | |
1692 | uint32_t flags); | |
1693 | void radeon_device_fini(struct radeon_device *rdev); | |
1694 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
1695 | ||
2ef9bdfe DV |
1696 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
1697 | bool always_indirect); | |
1698 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, | |
1699 | bool always_indirect); | |
6fcbef7a AK |
1700 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
1701 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
351a52a2 | 1702 | |
4c788679 JG |
1703 | /* |
1704 | * Cast helper | |
1705 | */ | |
1706 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
1707 | |
1708 | /* | |
1709 | * Registers read & write functions. | |
1710 | */ | |
a0533fbf BH |
1711 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
1712 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) | |
1713 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) | |
1714 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) | |
2ef9bdfe DV |
1715 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
1716 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) | |
1717 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) | |
1718 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) | |
1719 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) | |
771fe6b9 JG |
1720 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1721 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1722 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
1723 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
1724 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
1725 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
1726 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1727 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
aa5120d2 RM |
1728 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1729 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
1730 | #define WREG32_P(reg, val, mask) \ |
1731 | do { \ | |
1732 | uint32_t tmp_ = RREG32(reg); \ | |
1733 | tmp_ &= (mask); \ | |
1734 | tmp_ |= ((val) & ~(mask)); \ | |
1735 | WREG32(reg, tmp_); \ | |
1736 | } while (0) | |
1737 | #define WREG32_PLL_P(reg, val, mask) \ | |
1738 | do { \ | |
1739 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1740 | tmp_ &= (mask); \ | |
1741 | tmp_ |= ((val) & ~(mask)); \ | |
1742 | WREG32_PLL(reg, tmp_); \ | |
1743 | } while (0) | |
2ef9bdfe | 1744 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
351a52a2 AD |
1745 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1746 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) | |
771fe6b9 | 1747 | |
de1b2898 DA |
1748 | /* |
1749 | * Indirect registers accessor | |
1750 | */ | |
1751 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
1752 | { | |
1753 | uint32_t r; | |
1754 | ||
1755 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1756 | r = RREG32(RADEON_PCIE_DATA); | |
1757 | return r; | |
1758 | } | |
1759 | ||
1760 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1761 | { | |
1762 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1763 | WREG32(RADEON_PCIE_DATA, (v)); | |
1764 | } | |
1765 | ||
771fe6b9 JG |
1766 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1767 | ||
1768 | ||
1769 | /* | |
1770 | * ASICs helpers. | |
1771 | */ | |
b995e433 DA |
1772 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1773 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
1774 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1775 | (rdev->family == CHIP_RV200) || \ | |
1776 | (rdev->family == CHIP_RS100) || \ | |
1777 | (rdev->family == CHIP_RS200) || \ | |
1778 | (rdev->family == CHIP_RV250) || \ | |
1779 | (rdev->family == CHIP_RV280) || \ | |
1780 | (rdev->family == CHIP_RS300)) | |
1781 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
1782 | (rdev->family == CHIP_RV350) || \ | |
1783 | (rdev->family == CHIP_R350) || \ | |
1784 | (rdev->family == CHIP_RV380) || \ | |
1785 | (rdev->family == CHIP_R420) || \ | |
1786 | (rdev->family == CHIP_R423) || \ | |
1787 | (rdev->family == CHIP_RV410) || \ | |
1788 | (rdev->family == CHIP_RS400) || \ | |
1789 | (rdev->family == CHIP_RS480)) | |
3313e3d4 AD |
1790 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
1791 | (rdev->ddev->pdev->device == 0x9443) || \ | |
1792 | (rdev->ddev->pdev->device == 0x944B) || \ | |
1793 | (rdev->ddev->pdev->device == 0x9506) || \ | |
1794 | (rdev->ddev->pdev->device == 0x9509) || \ | |
1795 | (rdev->ddev->pdev->device == 0x950F) || \ | |
1796 | (rdev->ddev->pdev->device == 0x689C) || \ | |
1797 | (rdev->ddev->pdev->device == 0x689D)) | |
771fe6b9 | 1798 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
99999aaa AD |
1799 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
1800 | (rdev->family == CHIP_RS690) || \ | |
1801 | (rdev->family == CHIP_RS740) || \ | |
1802 | (rdev->family >= CHIP_R600)) | |
771fe6b9 JG |
1803 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1804 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 1805 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
633b9164 AD |
1806 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
1807 | (rdev->flags & RADEON_IS_IGP)) | |
1fe18305 | 1808 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
8848f759 AD |
1809 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
1810 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ | |
1811 | (rdev->flags & RADEON_IS_IGP)) | |
624d3524 | 1812 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
771fe6b9 JG |
1813 | |
1814 | /* | |
1815 | * BIOS helpers. | |
1816 | */ | |
1817 | #define RBIOS8(i) (rdev->bios[i]) | |
1818 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1819 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1820 | ||
1821 | int radeon_combios_init(struct radeon_device *rdev); | |
1822 | void radeon_combios_fini(struct radeon_device *rdev); | |
1823 | int radeon_atombios_init(struct radeon_device *rdev); | |
1824 | void radeon_atombios_fini(struct radeon_device *rdev); | |
1825 | ||
1826 | ||
1827 | /* | |
1828 | * RING helpers. | |
1829 | */ | |
ce580fab | 1830 | #if DRM_DEBUG_CODE == 0 |
e32eb50d | 1831 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
771fe6b9 | 1832 | { |
e32eb50d CK |
1833 | ring->ring[ring->wptr++] = v; |
1834 | ring->wptr &= ring->ptr_mask; | |
1835 | ring->count_dw--; | |
1836 | ring->ring_free_dw--; | |
771fe6b9 | 1837 | } |
ce580fab AK |
1838 | #else |
1839 | /* With debugging this is just too big to inline */ | |
e32eb50d | 1840 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
ce580fab | 1841 | #endif |
771fe6b9 JG |
1842 | |
1843 | /* | |
1844 | * ASICs macro. | |
1845 | */ | |
068a117c | 1846 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
1847 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1848 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
1849 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
eb0c19c5 | 1850 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) |
28d52043 | 1851 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
a2d07b74 | 1852 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
c5b3b850 AD |
1853 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
1854 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) | |
05b07147 CK |
1855 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
1856 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) | |
43f1214a | 1857 | #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
f712812e AD |
1858 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) |
1859 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) | |
1860 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) | |
4c87bc26 | 1861 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) |
721604a1 | 1862 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) |
312c4a8c | 1863 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) |
498522b4 | 1864 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) |
b35ea4ab AD |
1865 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
1866 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) | |
c79a49ca | 1867 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
37e9b6a6 | 1868 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
6d92f81d | 1869 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
4c87bc26 CK |
1870 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) |
1871 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) | |
27cd7769 AD |
1872 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
1873 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) | |
1874 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) | |
1875 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index | |
1876 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index | |
1877 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index | |
798bcf73 AD |
1878 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
1879 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) | |
1880 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) | |
1881 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) | |
1882 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) | |
1883 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) | |
1884 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) | |
9e6f3d02 AD |
1885 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
1886 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) | |
c79a49ca | 1887 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
901ea57d AD |
1888 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
1889 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) | |
1890 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) | |
1891 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) | |
def9ba9c | 1892 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
a02fa397 AD |
1893 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
1894 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) | |
1895 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) | |
1896 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) | |
1897 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) | |
69b62ad8 AD |
1898 | #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) |
1899 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) | |
1900 | #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) | |
1901 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) | |
1902 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) | |
454d2e2a | 1903 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
d0418894 | 1904 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
771fe6b9 | 1905 | |
6cf8a3f5 | 1906 | /* Common functions */ |
700a0cc0 | 1907 | /* AGP */ |
90aca4d2 | 1908 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
410a3418 | 1909 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
700a0cc0 | 1910 | extern void radeon_agp_disable(struct radeon_device *rdev); |
21f9a437 JG |
1911 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1912 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 1913 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 1914 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 1915 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 1916 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 | 1917 | extern void radeon_scratch_init(struct radeon_device *rdev); |
724c80e1 AD |
1918 | extern void radeon_wb_fini(struct radeon_device *rdev); |
1919 | extern int radeon_wb_init(struct radeon_device *rdev); | |
1920 | extern void radeon_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1921 | extern void radeon_surface_init(struct radeon_device *rdev); |
1922 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1923 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1924 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 1925 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 1926 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
d594e46a JG |
1927 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1928 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
6a9ee8af DA |
1929 | extern int radeon_resume_kms(struct drm_device *dev); |
1930 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
53595338 | 1931 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
6cf8a3f5 | 1932 | |
721604a1 JG |
1933 | /* |
1934 | * vm | |
1935 | */ | |
1936 | int radeon_vm_manager_init(struct radeon_device *rdev); | |
1937 | void radeon_vm_manager_fini(struct radeon_device *rdev); | |
d72d43cf | 1938 | void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
721604a1 | 1939 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
ddf03f5c | 1940 | int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); |
13e55c38 | 1941 | void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); |
ee60e29f CK |
1942 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
1943 | struct radeon_vm *vm, int ring); | |
1944 | void radeon_vm_fence(struct radeon_device *rdev, | |
1945 | struct radeon_vm *vm, | |
1946 | struct radeon_fence *fence); | |
dce34bfd | 1947 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
721604a1 JG |
1948 | int radeon_vm_bo_update_pte(struct radeon_device *rdev, |
1949 | struct radeon_vm *vm, | |
1950 | struct radeon_bo *bo, | |
1951 | struct ttm_mem_reg *mem); | |
1952 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, | |
1953 | struct radeon_bo *bo); | |
421ca7ab CK |
1954 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
1955 | struct radeon_bo *bo); | |
e971bd5e CK |
1956 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
1957 | struct radeon_vm *vm, | |
1958 | struct radeon_bo *bo); | |
1959 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, | |
1960 | struct radeon_bo_va *bo_va, | |
1961 | uint64_t offset, | |
1962 | uint32_t flags); | |
721604a1 | 1963 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
e971bd5e | 1964 | struct radeon_bo_va *bo_va); |
721604a1 | 1965 | |
f122c610 AD |
1966 | /* audio */ |
1967 | void r600_audio_update_hdmi(struct work_struct *work); | |
721604a1 | 1968 | |
16cdf04d AD |
1969 | /* |
1970 | * R600 vram scratch functions | |
1971 | */ | |
1972 | int r600_vram_scratch_init(struct radeon_device *rdev); | |
1973 | void r600_vram_scratch_fini(struct radeon_device *rdev); | |
1974 | ||
285484e2 JG |
1975 | /* |
1976 | * r600 cs checking helper | |
1977 | */ | |
1978 | unsigned r600_mip_minify(unsigned size, unsigned level); | |
1979 | bool r600_fmt_is_valid_color(u32 format); | |
1980 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); | |
1981 | int r600_fmt_get_blocksize(u32 format); | |
1982 | int r600_fmt_get_nblocksx(u32 format, u32 w); | |
1983 | int r600_fmt_get_nblocksy(u32 format, u32 h); | |
1984 | ||
3574dda4 DV |
1985 | /* |
1986 | * r600 functions used by radeon_encoder.c | |
1987 | */ | |
1b688d08 RM |
1988 | struct radeon_hdmi_acr { |
1989 | u32 clock; | |
1990 | ||
1991 | int n_32khz; | |
1992 | int cts_32khz; | |
1993 | ||
1994 | int n_44_1khz; | |
1995 | int cts_44_1khz; | |
1996 | ||
1997 | int n_48khz; | |
1998 | int cts_48khz; | |
1999 | ||
2000 | }; | |
2001 | ||
e55d3e6c RM |
2002 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
2003 | ||
2cd6218c RM |
2004 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
2005 | extern void r600_hdmi_disable(struct drm_encoder *encoder); | |
dafc3bd5 | 2006 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
416a2bd2 AD |
2007 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
2008 | u32 tiling_pipe_num, | |
2009 | u32 max_rb_num, | |
2010 | u32 total_max_rb_num, | |
2011 | u32 enabled_rb_mask); | |
fe251e2f | 2012 | |
e55d3e6c RM |
2013 | /* |
2014 | * evergreen functions used by radeon_encoder.c | |
2015 | */ | |
2016 | ||
2017 | extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
2018 | ||
0af62b01 | 2019 | extern int ni_init_microcode(struct radeon_device *rdev); |
755d819e | 2020 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
0af62b01 | 2021 | |
c4917074 AD |
2022 | /* radeon_acpi.c */ |
2023 | #if defined(CONFIG_ACPI) | |
2024 | extern int radeon_acpi_init(struct radeon_device *rdev); | |
2025 | extern void radeon_acpi_fini(struct radeon_device *rdev); | |
2026 | #else | |
2027 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } | |
2028 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } | |
2029 | #endif | |
d7a2952f | 2030 | |
c38f34b5 IH |
2031 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
2032 | struct radeon_cs_packet *pkt, | |
2033 | unsigned idx); | |
9ffb7a6d | 2034 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
c3ad63af IH |
2035 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
2036 | struct radeon_cs_packet *pkt); | |
e9716993 IH |
2037 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
2038 | struct radeon_cs_reloc **cs_reloc, | |
2039 | int nomm); | |
40592a17 IH |
2040 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
2041 | uint32_t *vline_start_end, | |
2042 | uint32_t *vline_status); | |
c38f34b5 | 2043 | |
4c788679 JG |
2044 | #include "radeon_object.h" |
2045 | ||
771fe6b9 | 2046 | #endif |