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gma500/oaktrail: panel display quality fix
[linux-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
771fe6b9
JG		 97
98/*
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 * symbol;
101 */
102#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
225758d8 103#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 104/* RADEON_IB_POOL_SIZE must be a power of 2 */
771fe6b9 105#define RADEON_IB_POOL_SIZE 16
c245cb9e 106#define RADEON_DEBUGFS_MAX_COMPONENTS 32
771fe6b9 107#define RADEONFB_CONN_LIMIT 4
f657c2a7 108#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 109
771fe6b9
JG		 110/*
111 * Errata workarounds.
112 */
113enum radeon_pll_errata {
114 CHIP_ERRATA_R300_CG = 0x00000001,
115 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
116 CHIP_ERRATA_PLL_DELAY = 0x00000004
117};
118
119
120struct radeon_device;
121
122
123/*
124 * BIOS.
125 */
6a9ee8af
DA		 126#define ATRM_BIOS_PAGE 4096
127
8edb381d 128#if defined(CONFIG_VGA_SWITCHEROO)
6a9ee8af
DA		 129bool radeon_atrm_supported(struct pci_dev *pdev);
130int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
8edb381d
DA		 131#else
132static inline bool radeon_atrm_supported(struct pci_dev *pdev)
133{
134 return false;
135}
136
137static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
138 return -EINVAL;
139}
140#endif
771fe6b9
JG		 141bool radeon_get_bios(struct radeon_device *rdev);
142
3ce0a23d 143
771fe6b9 144/*
3ce0a23d 145 * Dummy page
771fe6b9 146 */
3ce0a23d
JG		 147struct radeon_dummy_page {
148 struct page *page;
149 dma_addr_t addr;
150};
151int radeon_dummy_page_init(struct radeon_device *rdev);
152void radeon_dummy_page_fini(struct radeon_device *rdev);
153
771fe6b9 154
3ce0a23d
JG		 155/*
156 * Clocks
157 */
771fe6b9
JG		 158struct radeon_clock {
159 struct radeon_pll p1pll;
160 struct radeon_pll p2pll;
bcc1c2a1 161 struct radeon_pll dcpll;
771fe6b9
JG		 162 struct radeon_pll spll;
163 struct radeon_pll mpll;
164 /* 10 Khz units */
165 uint32_t default_mclk;
166 uint32_t default_sclk;
bcc1c2a1
AD		 167 uint32_t default_dispclk;
168 uint32_t dp_extclk;
b20f9bef 169 uint32_t max_pixel_clock;
771fe6b9
JG		 170};
171
7433874e
RM		 172/*
173 * Power management
174 */
175int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 176void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 177void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 178void radeon_pm_suspend(struct radeon_device *rdev);
179void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 180void radeon_combios_get_power_modes(struct radeon_device *rdev);
181void radeon_atombios_get_power_modes(struct radeon_device *rdev);
8a83ec5e 182void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ee4017f4 183int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
f892034a 184void rs690_pm_info(struct radeon_device *rdev);
20d391d7
AD		 185extern int rv6xx_get_temp(struct radeon_device *rdev);
186extern int rv770_get_temp(struct radeon_device *rdev);
187extern int evergreen_get_temp(struct radeon_device *rdev);
188extern int sumo_get_temp(struct radeon_device *rdev);
3ce0a23d 189
771fe6b9
JG		 190/*
191 * Fences.
192 */
193struct radeon_fence_driver {
194 uint32_t scratch_reg;
195 atomic_t seq;
196 uint32_t last_seq;
225758d8
JG		 197 unsigned long last_jiffies;
198 unsigned long last_timeout;
771fe6b9
JG		 199 wait_queue_head_t queue;
200 rwlock_t lock;
201 struct list_head created;
202 struct list_head emited;
203 struct list_head signaled;
0a0c7596 204 bool initialized;
771fe6b9
JG		 205};
206
207struct radeon_fence {
208 struct radeon_device *rdev;
209 struct kref kref;
210 struct list_head list;
211 /* protected by radeon_fence.lock */
212 uint32_t seq;
771fe6b9
JG		 213 bool emited;
214 bool signaled;
215};
216
217int radeon_fence_driver_init(struct radeon_device *rdev);
218void radeon_fence_driver_fini(struct radeon_device *rdev);
219int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
220int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
221void radeon_fence_process(struct radeon_device *rdev);
222bool radeon_fence_signaled(struct radeon_fence *fence);
223int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
224int radeon_fence_wait_next(struct radeon_device *rdev);
225int radeon_fence_wait_last(struct radeon_device *rdev);
226struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
227void radeon_fence_unref(struct radeon_fence **fence);
228
e024e110
DA		 229/*
230 * Tiling registers
231 */
232struct radeon_surface_reg {
4c788679 233 struct radeon_bo *bo;
e024e110
DA		 234};
235
236#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 237
238/*
4c788679 239 * TTM.
771fe6b9 240 */
4c788679
JG		 241struct radeon_mman {
242 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 243 struct drm_global_reference mem_global_ref;
4c788679 244 struct ttm_bo_device bdev;
0a0c7596
JG		 245 bool mem_global_referenced;
246 bool initialized;
4c788679
JG		 247};
248
249struct radeon_bo {
250 /* Protected by gem.mutex */
251 struct list_head list;
252 /* Protected by tbo.reserved */
312ea8da
JG		 253 u32 placements[3];
254 struct ttm_placement placement;
4c788679
JG		 255 struct ttm_buffer_object tbo;
256 struct ttm_bo_kmap_obj kmap;
257 unsigned pin_count;
258 void *kptr;
259 u32 tiling_flags;
260 u32 pitch;
261 int surface_reg;
262 /* Constant after initialization */
263 struct radeon_device *rdev;
441921d5 264 struct drm_gem_object gem_base;
4c788679 265};
7e4d15d9 266#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 267
4c788679 268struct radeon_bo_list {
147666fb 269 struct ttm_validate_buffer tv;
4c788679 270 struct radeon_bo *bo;
771fe6b9
JG		 271 uint64_t gpu_offset;
272 unsigned rdomain;
273 unsigned wdomain;
4c788679 274 u32 tiling_flags;
771fe6b9
JG		 275};
276
771fe6b9
JG		 277/*
278 * GEM objects.
279 */
280struct radeon_gem {
4c788679 281 struct mutex mutex;
771fe6b9
JG		 282 struct list_head objects;
283};
284
285int radeon_gem_init(struct radeon_device *rdev);
286void radeon_gem_fini(struct radeon_device *rdev);
287int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 288 int alignment, int initial_domain,
289 bool discardable, bool kernel,
290 struct drm_gem_object **obj);
771fe6b9
JG		 291int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
292 uint64_t *gpu_addr);
293void radeon_gem_object_unpin(struct drm_gem_object *obj);
294
ff72145b
DA		 295int radeon_mode_dumb_create(struct drm_file *file_priv,
296 struct drm_device *dev,
297 struct drm_mode_create_dumb *args);
298int radeon_mode_dumb_mmap(struct drm_file *filp,
299 struct drm_device *dev,
300 uint32_t handle, uint64_t *offset_p);
301int radeon_mode_dumb_destroy(struct drm_file *file_priv,
302 struct drm_device *dev,
303 uint32_t handle);
771fe6b9
JG		 304
305/*
306 * GART structures, functions & helpers
307 */
308struct radeon_mc;
309
a77f1718 310#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 311#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 312#define RADEON_GPU_PAGE_SHIFT 12
a77f1718 313
771fe6b9
JG		 314struct radeon_gart {
315 dma_addr_t table_addr;
c9a1be96
JG		 316 struct radeon_bo *robj;
317 void *ptr;
771fe6b9
JG		 318 unsigned num_gpu_pages;
319 unsigned num_cpu_pages;
320 unsigned table_size;
771fe6b9
JG		 321 struct page **pages;
322 dma_addr_t *pages_addr;
323 bool ready;
324};
325
326int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
327void radeon_gart_table_ram_free(struct radeon_device *rdev);
328int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
329void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 330int radeon_gart_table_vram_pin(struct radeon_device *rdev);
331void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 332int radeon_gart_init(struct radeon_device *rdev);
333void radeon_gart_fini(struct radeon_device *rdev);
334void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
335 int pages);
336int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 337 int pages, struct page **pagelist,
338 dma_addr_t *dma_addr);
c9a1be96 339void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 340
341
342/*
343 * GPU MC structures, functions & helpers
344 */
345struct radeon_mc {
346 resource_size_t aper_size;
347 resource_size_t aper_base;
348 resource_size_t agp_base;
7a50f01a
DA		 349 /* for some chips with <= 32MB we need to lie
350 * about vram size near mc fb location */
3ce0a23d 351 u64 mc_vram_size;
d594e46a 352 u64 visible_vram_size;
3ce0a23d
JG		 353 u64 gtt_size;
354 u64 gtt_start;
355 u64 gtt_end;
3ce0a23d
JG		 356 u64 vram_start;
357 u64 vram_end;
771fe6b9 358 unsigned vram_width;
3ce0a23d 359 u64 real_vram_size;
771fe6b9
JG		 360 int vram_mtrr;
361 bool vram_is_ddr;
d594e46a 362 bool igp_sideport_enabled;
8d369bb1 363 u64 gtt_base_align;
771fe6b9
JG		 364};
365
06b6476d
AD		 366bool radeon_combios_sideport_present(struct radeon_device *rdev);
367bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 368
369/*
370 * GPU scratch registers structures, functions & helpers
371 */
372struct radeon_scratch {
373 unsigned num_reg;
724c80e1 374 uint32_t reg_base;
771fe6b9
JG		 375 bool free[32];
376 uint32_t reg[32];
377};
378
379int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
380void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
381
382
383/*
384 * IRQS.
385 */
6f34be50
AD		 386
387struct radeon_unpin_work {
388 struct work_struct work;
389 struct radeon_device *rdev;
390 int crtc_id;
391 struct radeon_fence *fence;
392 struct drm_pending_vblank_event *event;
393 struct radeon_bo *old_rbo;
394 u64 new_crtc_base;
395};
396
397struct r500_irq_stat_regs {
398 u32 disp_int;
399};
400
401struct r600_irq_stat_regs {
402 u32 disp_int;
403 u32 disp_int_cont;
404 u32 disp_int_cont2;
405 u32 d1grph_int;
406 u32 d2grph_int;
407};
408
409struct evergreen_irq_stat_regs {
410 u32 disp_int;
411 u32 disp_int_cont;
412 u32 disp_int_cont2;
413 u32 disp_int_cont3;
414 u32 disp_int_cont4;
415 u32 disp_int_cont5;
416 u32 d1grph_int;
417 u32 d2grph_int;
418 u32 d3grph_int;
419 u32 d4grph_int;
420 u32 d5grph_int;
421 u32 d6grph_int;
422};
423
424union radeon_irq_stat_regs {
425 struct r500_irq_stat_regs r500;
426 struct r600_irq_stat_regs r600;
427 struct evergreen_irq_stat_regs evergreen;
428};
429
54bd5206
IH		 430#define RADEON_MAX_HPD_PINS 6
431#define RADEON_MAX_CRTCS 6
432#define RADEON_MAX_HDMI_BLOCKS 2
433
771fe6b9
JG		 434struct radeon_irq {
435 bool installed;
436 bool sw_int;
54bd5206
IH		 437 bool crtc_vblank_int[RADEON_MAX_CRTCS];
438 bool pflip[RADEON_MAX_CRTCS];
73a6d3fc 439 wait_queue_head_t vblank_queue;
54bd5206 440 bool hpd[RADEON_MAX_HPD_PINS];
2031f77c
AD		 441 bool gui_idle;
442 bool gui_idle_acked;
443 wait_queue_head_t idle_queue;
54bd5206 444 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
1614f8b1
DA		 445 spinlock_t sw_lock;
446 int sw_refcount;
6f34be50 447 union radeon_irq_stat_regs stat_regs;
54bd5206
IH		 448 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
449 int pflip_refcount[RADEON_MAX_CRTCS];
771fe6b9
JG		 450};
451
452int radeon_irq_kms_init(struct radeon_device *rdev);
453void radeon_irq_kms_fini(struct radeon_device *rdev);
1614f8b1
DA		 454void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
455void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
6f34be50
AD		 456void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
457void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 458
459/*
460 * CP & ring.
461 */
462struct radeon_ib {
463 struct list_head list;
e821767b 464 unsigned idx;
771fe6b9
JG		 465 uint64_t gpu_addr;
466 struct radeon_fence *fence;
e821767b 467 uint32_t *ptr;
771fe6b9 468 uint32_t length_dw;
e821767b 469 bool free;
771fe6b9
JG		 470};
471
ecb114a1
DA		 472/*
473 * locking -
474 * mutex protects scheduled_ibs, ready, alloc_bm
475 */
771fe6b9
JG		 476struct radeon_ib_pool {
477 struct mutex mutex;
4c788679 478 struct radeon_bo *robj;
9f93ed39 479 struct list_head bogus_ib;
771fe6b9
JG		 480 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
481 bool ready;
e821767b 482 unsigned head_id;
771fe6b9
JG		 483};
484
485struct radeon_cp {
4c788679 486 struct radeon_bo *ring_obj;
771fe6b9
JG		 487 volatile uint32_t *ring;
488 unsigned rptr;
489 unsigned wptr;
490 unsigned wptr_old;
491 unsigned ring_size;
492 unsigned ring_free_dw;
493 int count_dw;
494 uint64_t gpu_addr;
495 uint32_t align_mask;
496 uint32_t ptr_mask;
497 struct mutex mutex;
498 bool ready;
499};
500
d8f60cfc
AD		 501/*
502 * R6xx+ IH ring
503 */
504struct r600_ih {
4c788679 505 struct radeon_bo *ring_obj;
d8f60cfc
AD		 506 volatile uint32_t *ring;
507 unsigned rptr;
508 unsigned wptr;
509 unsigned wptr_old;
510 unsigned ring_size;
511 uint64_t gpu_addr;
d8f60cfc
AD		 512 uint32_t ptr_mask;
513 spinlock_t lock;
514 bool enabled;
515};
516
8eec9d6f
IH		 517struct r600_blit_cp_primitives {
518 void (*set_render_target)(struct radeon_device *rdev, int format,
519 int w, int h, u64 gpu_addr);
520 void (*cp_set_surface_sync)(struct radeon_device *rdev,
521 u32 sync_type, u32 size,
522 u64 mc_addr);
523 void (*set_shaders)(struct radeon_device *rdev);
524 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
525 void (*set_tex_resource)(struct radeon_device *rdev,
526 int format, int w, int h, int pitch,
9bb7703c 527 u64 gpu_addr, u32 size);
8eec9d6f
IH		 528 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
529 int x2, int y2);
530 void (*draw_auto)(struct radeon_device *rdev);
531 void (*set_default_state)(struct radeon_device *rdev);
532};
533
3ce0a23d 534struct r600_blit {
ff82f052 535 struct mutex mutex;
4c788679 536 struct radeon_bo *shader_obj;
8eec9d6f
IH		 537 struct r600_blit_cp_primitives primitives;
538 int max_dim;
539 int ring_size_common;
540 int ring_size_per_loop;
3ce0a23d
JG		 541 u64 shader_gpu_addr;
542 u32 vs_offset, ps_offset;
543 u32 state_offset;
544 u32 state_len;
545 u32 vb_used, vb_total;
546 struct radeon_ib *vb_ib;
547};
548
6ddddfe7
AD		 549void r600_blit_suspend(struct radeon_device *rdev);
550
771fe6b9
JG		 551int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
552void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
553int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
554int radeon_ib_pool_init(struct radeon_device *rdev);
555void radeon_ib_pool_fini(struct radeon_device *rdev);
556int radeon_ib_test(struct radeon_device *rdev);
9f93ed39 557extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 558/* Ring access between begin & end cannot sleep */
559void radeon_ring_free_size(struct radeon_device *rdev);
91700f3c 560int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
771fe6b9 561int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
91700f3c 562void radeon_ring_commit(struct radeon_device *rdev);
771fe6b9
JG		 563void radeon_ring_unlock_commit(struct radeon_device *rdev);
564void radeon_ring_unlock_undo(struct radeon_device *rdev);
565int radeon_ring_test(struct radeon_device *rdev);
566int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
567void radeon_ring_fini(struct radeon_device *rdev);
568
569
570/*
571 * CS.
572 */
573struct radeon_cs_reloc {
574 struct drm_gem_object *gobj;
4c788679
JG		 575 struct radeon_bo *robj;
576 struct radeon_bo_list lobj;
771fe6b9
JG		 577 uint32_t handle;
578 uint32_t flags;
579};
580
581struct radeon_cs_chunk {
582 uint32_t chunk_id;
583 uint32_t length_dw;
513bcb46
DA		 584 int kpage_idx[2];
585 uint32_t *kpage[2];
771fe6b9 586 uint32_t *kdata;
513bcb46
DA		 587 void __user *user_ptr;
588 int last_copied_page;
589 int last_page_index;
771fe6b9
JG		 590};
591
592struct radeon_cs_parser {
c8c15ff1 593 struct device *dev;
771fe6b9
JG		 594 struct radeon_device *rdev;
595 struct drm_file *filp;
596 /* chunks */
597 unsigned nchunks;
598 struct radeon_cs_chunk *chunks;
599 uint64_t *chunks_array;
600 /* IB */
601 unsigned idx;
602 /* relocations */
603 unsigned nrelocs;
604 struct radeon_cs_reloc *relocs;
605 struct radeon_cs_reloc **relocs_ptr;
606 struct list_head validated;
607 /* indices of various chunks */
608 int chunk_ib_idx;
609 int chunk_relocs_idx;
610 struct radeon_ib *ib;
611 void *track;
3ce0a23d 612 unsigned family;
e70f224c
MO		 613 int parser_error;
614 bool keep_tiling_flags;
771fe6b9
JG		 615};
616
513bcb46
DA		 617extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
618extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
ce580fab 619extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
513bcb46 620
771fe6b9
JG		 621struct radeon_cs_packet {
622 unsigned idx;
623 unsigned type;
624 unsigned reg;
625 unsigned opcode;
626 int count;
627 unsigned one_reg_wr;
628};
629
630typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
631 struct radeon_cs_packet *pkt,
632 unsigned idx, unsigned reg);
633typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
634 struct radeon_cs_packet *pkt);
635
636
637/*
638 * AGP
639 */
640int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 641void radeon_agp_resume(struct radeon_device *rdev);
10b06122 642void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 643void radeon_agp_fini(struct radeon_device *rdev);
644
645
646/*
647 * Writeback
648 */
649struct radeon_wb {
4c788679 650 struct radeon_bo *wb_obj;
771fe6b9
JG		 651 volatile uint32_t *wb;
652 uint64_t gpu_addr;
724c80e1 653 bool enabled;
d0f8a854 654 bool use_event;
771fe6b9
JG		 655};
656
724c80e1
AD		 657#define RADEON_WB_SCRATCH_OFFSET 0
658#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 659#define RADEON_WB_CP1_RPTR_OFFSET 1280
660#define RADEON_WB_CP2_RPTR_OFFSET 1536
724c80e1 661#define R600_WB_IH_WPTR_OFFSET 2048
d0f8a854 662#define R600_WB_EVENT_OFFSET 3072
724c80e1 663
c93bb85b
JG		 664/**
665 * struct radeon_pm - power management datas
666 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
667 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
668 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
669 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
670 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
671 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
672 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
673 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
674 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 675 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 676 * @needed_bandwidth: current bandwidth needs
677 *
678 * It keeps track of various data needed to take powermanagement decision.
25985edc 679 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 680 * Equation between gpu/memory clock and available bandwidth is hw dependent
681 * (type of memory, bus size, efficiency, ...)
682 */
ce8f5370
AD		 683
684enum radeon_pm_method {
685 PM_METHOD_PROFILE,
686 PM_METHOD_DYNPM,
687};
688
689enum radeon_dynpm_state {
690 DYNPM_STATE_DISABLED,
691 DYNPM_STATE_MINIMUM,
692 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 693 DYNPM_STATE_ACTIVE,
694 DYNPM_STATE_SUSPENDED,
c913e23a 695};
ce8f5370
AD		 696enum radeon_dynpm_action {
697 DYNPM_ACTION_NONE,
698 DYNPM_ACTION_MINIMUM,
699 DYNPM_ACTION_DOWNCLOCK,
700 DYNPM_ACTION_UPCLOCK,
701 DYNPM_ACTION_DEFAULT
c913e23a 702};
56278a8e
AD		 703
704enum radeon_voltage_type {
705 VOLTAGE_NONE = 0,
706 VOLTAGE_GPIO,
707 VOLTAGE_VDDC,
708 VOLTAGE_SW
709};
710
0ec0e74f
AD		 711enum radeon_pm_state_type {
712 POWER_STATE_TYPE_DEFAULT,
713 POWER_STATE_TYPE_POWERSAVE,
714 POWER_STATE_TYPE_BATTERY,
715 POWER_STATE_TYPE_BALANCED,
716 POWER_STATE_TYPE_PERFORMANCE,
717};
718
ce8f5370
AD		 719enum radeon_pm_profile_type {
720 PM_PROFILE_DEFAULT,
721 PM_PROFILE_AUTO,
722 PM_PROFILE_LOW,
c9e75b21 723 PM_PROFILE_MID,
ce8f5370
AD		 724 PM_PROFILE_HIGH,
725};
726
727#define PM_PROFILE_DEFAULT_IDX 0
728#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 729#define PM_PROFILE_MID_SH_IDX 2
730#define PM_PROFILE_HIGH_SH_IDX 3
731#define PM_PROFILE_LOW_MH_IDX 4
732#define PM_PROFILE_MID_MH_IDX 5
733#define PM_PROFILE_HIGH_MH_IDX 6
734#define PM_PROFILE_MAX 7
ce8f5370
AD		 735
736struct radeon_pm_profile {
737 int dpms_off_ps_idx;
738 int dpms_on_ps_idx;
739 int dpms_off_cm_idx;
740 int dpms_on_cm_idx;
516d0e46
AD		 741};
742
21a8122a
AD		 743enum radeon_int_thermal_type {
744 THERMAL_TYPE_NONE,
745 THERMAL_TYPE_RV6XX,
746 THERMAL_TYPE_RV770,
747 THERMAL_TYPE_EVERGREEN,
e33df25f 748 THERMAL_TYPE_SUMO,
4fddba1f 749 THERMAL_TYPE_NI,
21a8122a
AD		 750};
751
56278a8e
AD		 752struct radeon_voltage {
753 enum radeon_voltage_type type;
754 /* gpio voltage */
755 struct radeon_gpio_rec gpio;
756 u32 delay; /* delay in usec from voltage drop to sclk change */
757 bool active_high; /* voltage drop is active when bit is high */
758 /* VDDC voltage */
759 u8 vddc_id; /* index into vddc voltage table */
760 u8 vddci_id; /* index into vddci voltage table */
761 bool vddci_enabled;
762 /* r6xx+ sw */
2feea49a
AD		 763 u16 voltage;
764 /* evergreen+ vddci */
765 u16 vddci;
56278a8e
AD		 766};
767
d7311171
AD		 768/* clock mode flags */
769#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
770
56278a8e
AD		 771struct radeon_pm_clock_info {
772 /* memory clock */
773 u32 mclk;
774 /* engine clock */
775 u32 sclk;
776 /* voltage info */
777 struct radeon_voltage voltage;
d7311171 778 /* standardized clock flags */
56278a8e
AD		 779 u32 flags;
780};
781
a48b9b4e 782/* state flags */
d7311171 783#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 784
56278a8e 785struct radeon_power_state {
0ec0e74f 786 enum radeon_pm_state_type type;
8f3f1c9a 787 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 788 /* number of valid clock modes in this power state */
789 int num_clock_modes;
56278a8e 790 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 791 /* standardized state flags */
792 u32 flags;
79daedc9
AD		 793 u32 misc; /* vbios specific flags */
794 u32 misc2; /* vbios specific flags */
795 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 796};
797
27459324
RM		 798/*
799 * Some modes are overclocked by very low value, accept them
800 */
801#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
802
c93bb85b 803struct radeon_pm {
c913e23a 804 struct mutex mutex;
a48b9b4e
AD		 805 u32 active_crtcs;
806 int active_crtc_count;
c913e23a 807 int req_vblank;
839461d3 808 bool vblank_sync;
2031f77c 809 bool gui_idle;
c93bb85b
JG		 810 fixed20_12 max_bandwidth;
811 fixed20_12 igp_sideport_mclk;
812 fixed20_12 igp_system_mclk;
813 fixed20_12 igp_ht_link_clk;
814 fixed20_12 igp_ht_link_width;
815 fixed20_12 k8_bandwidth;
816 fixed20_12 sideport_bandwidth;
817 fixed20_12 ht_bandwidth;
818 fixed20_12 core_bandwidth;
819 fixed20_12 sclk;
f47299c5 820 fixed20_12 mclk;
c93bb85b 821 fixed20_12 needed_bandwidth;
0975b162 822 struct radeon_power_state *power_state;
56278a8e
AD		 823 /* number of valid power states */
824 int num_power_states;
a48b9b4e
AD		 825 int current_power_state_index;
826 int current_clock_mode_index;
827 int requested_power_state_index;
828 int requested_clock_mode_index;
829 int default_power_state_index;
830 u32 current_sclk;
831 u32 current_mclk;
2feea49a
AD		 832 u16 current_vddc;
833 u16 current_vddci;
9ace9f7b
AD		 834 u32 default_sclk;
835 u32 default_mclk;
2feea49a
AD		 836 u16 default_vddc;
837 u16 default_vddci;
29fb52ca 838 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 839 /* selected pm method */
840 enum radeon_pm_method pm_method;
841 /* dynpm power management */
842 struct delayed_work dynpm_idle_work;
843 enum radeon_dynpm_state dynpm_state;
844 enum radeon_dynpm_action dynpm_planned_action;
845 unsigned long dynpm_action_timeout;
846 bool dynpm_can_upclock;
847 bool dynpm_can_downclock;
848 /* profile-based power management */
849 enum radeon_pm_profile_type profile;
850 int profile_index;
851 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 852 /* internal thermal controller on rv6xx+ */
853 enum radeon_int_thermal_type int_thermal_type;
854 struct device *int_hwmon_dev;
c93bb85b
JG		 855};
856
a4c9e2ee
AD		 857int radeon_pm_get_type_index(struct radeon_device *rdev,
858 enum radeon_pm_state_type ps_type,
859 int instance);
771fe6b9
JG		 860
861/*
862 * Benchmarking
863 */
638dd7db 864void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 865
866
ecc0b326
MD		 867/*
868 * Testing
869 */
870void radeon_test_moves(struct radeon_device *rdev);
871
872
771fe6b9
JG		 873/*
874 * Debugfs
875 */
876int radeon_debugfs_add_files(struct radeon_device *rdev,
877 struct drm_info_list *files,
878 unsigned nfiles);
879int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9
JG		 880
881
882/*
883 * ASIC specific functions.
884 */
885struct radeon_asic {
068a117c 886 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 887 void (*fini)(struct radeon_device *rdev);
888 int (*resume)(struct radeon_device *rdev);
889 int (*suspend)(struct radeon_device *rdev);
28d52043 890 void (*vga_set_state)(struct radeon_device *rdev, bool state);
225758d8 891 bool (*gpu_is_lockup)(struct radeon_device *rdev);
a2d07b74 892 int (*asic_reset)(struct radeon_device *rdev);
771fe6b9
JG		 893 void (*gart_tlb_flush)(struct radeon_device *rdev);
894 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
895 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
896 void (*cp_fini)(struct radeon_device *rdev);
897 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 898 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 899 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 900 int (*ring_test)(struct radeon_device *rdev);
901 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 902 int (*irq_set)(struct radeon_device *rdev);
903 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 904 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 905 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
906 int (*cs_parse)(struct radeon_cs_parser *p);
907 int (*copy_blit)(struct radeon_device *rdev,
908 uint64_t src_offset,
909 uint64_t dst_offset,
003cefe0 910 unsigned num_gpu_pages,
771fe6b9
JG		 911 struct radeon_fence *fence);
912 int (*copy_dma)(struct radeon_device *rdev,
913 uint64_t src_offset,
914 uint64_t dst_offset,
003cefe0 915 unsigned num_gpu_pages,
771fe6b9
JG		 916 struct radeon_fence *fence);
917 int (*copy)(struct radeon_device *rdev,
918 uint64_t src_offset,
919 uint64_t dst_offset,
003cefe0 920 unsigned num_gpu_pages,
771fe6b9 921 struct radeon_fence *fence);
7433874e 922 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 923 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 924 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9 925 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
c836a412 926 int (*get_pcie_lanes)(struct radeon_device *rdev);
771fe6b9
JG		 927 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
928 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 929 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
930 uint32_t tiling_flags, uint32_t pitch,
931 uint32_t offset, uint32_t obj_size);
9479c54f 932 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 933 void (*bandwidth_update)(struct radeon_device *rdev);
429770b3
AD		 934 void (*hpd_init)(struct radeon_device *rdev);
935 void (*hpd_fini)(struct radeon_device *rdev);
936 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
937 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
062b389c
JG		 938 /* ioctl hw specific callback. Some hw might want to perform special
939 * operation on specific ioctl. For instance on wait idle some hw
940 * might want to perform and HDP flush through MMIO as it seems that
941 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
942 * through ring.
943 */
944 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
def9ba9c 945 bool (*gui_idle)(struct radeon_device *rdev);
ce8f5370 946 /* power management */
49e02b73
AD		 947 void (*pm_misc)(struct radeon_device *rdev);
948 void (*pm_prepare)(struct radeon_device *rdev);
949 void (*pm_finish)(struct radeon_device *rdev);
ce8f5370
AD		 950 void (*pm_init_profile)(struct radeon_device *rdev);
951 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
6f34be50
AD		 952 /* pageflipping */
953 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
954 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
955 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 956};
957
21f9a437
JG		 958/*
959 * Asic structures
960 */
225758d8
JG		 961struct r100_gpu_lockup {
962 unsigned long last_jiffies;
963 u32 last_cp_rptr;
964};
965
551ebd83 966struct r100_asic {
225758d8
JG		 967 const unsigned *reg_safe_bm;
968 unsigned reg_safe_bm_size;
969 u32 hdp_cntl;
970 struct r100_gpu_lockup lockup;
551ebd83
DA		 971};
972
21f9a437 973struct r300_asic {
225758d8
JG		 974 const unsigned *reg_safe_bm;
975 unsigned reg_safe_bm_size;
976 u32 resync_scratch;
977 u32 hdp_cntl;
978 struct r100_gpu_lockup lockup;
21f9a437
JG		 979};
980
981struct r600_asic {
225758d8
JG		 982 unsigned max_pipes;
983 unsigned max_tile_pipes;
984 unsigned max_simds;
985 unsigned max_backends;
986 unsigned max_gprs;
987 unsigned max_threads;
988 unsigned max_stack_entries;
989 unsigned max_hw_contexts;
990 unsigned max_gs_threads;
991 unsigned sx_max_export_size;
992 unsigned sx_max_export_pos_size;
993 unsigned sx_max_export_smx_size;
994 unsigned sq_num_cf_insts;
995 unsigned tiling_nbanks;
996 unsigned tiling_npipes;
997 unsigned tiling_group_size;
e7aeeba6 998 unsigned tile_config;
e55b9422 999 unsigned backend_map;
225758d8 1000 struct r100_gpu_lockup lockup;
21f9a437
JG		 1001};
1002
1003struct rv770_asic {
225758d8
JG		 1004 unsigned max_pipes;
1005 unsigned max_tile_pipes;
1006 unsigned max_simds;
1007 unsigned max_backends;
1008 unsigned max_gprs;
1009 unsigned max_threads;
1010 unsigned max_stack_entries;
1011 unsigned max_hw_contexts;
1012 unsigned max_gs_threads;
1013 unsigned sx_max_export_size;
1014 unsigned sx_max_export_pos_size;
1015 unsigned sx_max_export_smx_size;
1016 unsigned sq_num_cf_insts;
1017 unsigned sx_num_of_sets;
1018 unsigned sc_prim_fifo_size;
1019 unsigned sc_hiz_tile_fifo_size;
1020 unsigned sc_earlyz_tile_fifo_fize;
1021 unsigned tiling_nbanks;
1022 unsigned tiling_npipes;
1023 unsigned tiling_group_size;
e7aeeba6 1024 unsigned tile_config;
e55b9422 1025 unsigned backend_map;
225758d8 1026 struct r100_gpu_lockup lockup;
21f9a437
JG		 1027};
1028
32fcdbf4
AD		 1029struct evergreen_asic {
1030 unsigned num_ses;
1031 unsigned max_pipes;
1032 unsigned max_tile_pipes;
1033 unsigned max_simds;
1034 unsigned max_backends;
1035 unsigned max_gprs;
1036 unsigned max_threads;
1037 unsigned max_stack_entries;
1038 unsigned max_hw_contexts;
1039 unsigned max_gs_threads;
1040 unsigned sx_max_export_size;
1041 unsigned sx_max_export_pos_size;
1042 unsigned sx_max_export_smx_size;
1043 unsigned sq_num_cf_insts;
1044 unsigned sx_num_of_sets;
1045 unsigned sc_prim_fifo_size;
1046 unsigned sc_hiz_tile_fifo_size;
1047 unsigned sc_earlyz_tile_fifo_size;
1048 unsigned tiling_nbanks;
1049 unsigned tiling_npipes;
1050 unsigned tiling_group_size;
e7aeeba6 1051 unsigned tile_config;
e55b9422 1052 unsigned backend_map;
17db7042 1053 struct r100_gpu_lockup lockup;
32fcdbf4
AD		 1054};
1055
fecf1d07
AD		 1056struct cayman_asic {
1057 unsigned max_shader_engines;
1058 unsigned max_pipes_per_simd;
1059 unsigned max_tile_pipes;
1060 unsigned max_simds_per_se;
1061 unsigned max_backends_per_se;
1062 unsigned max_texture_channel_caches;
1063 unsigned max_gprs;
1064 unsigned max_threads;
1065 unsigned max_gs_threads;
1066 unsigned max_stack_entries;
1067 unsigned sx_num_of_sets;
1068 unsigned sx_max_export_size;
1069 unsigned sx_max_export_pos_size;
1070 unsigned sx_max_export_smx_size;
1071 unsigned max_hw_contexts;
1072 unsigned sq_num_cf_insts;
1073 unsigned sc_prim_fifo_size;
1074 unsigned sc_hiz_tile_fifo_size;
1075 unsigned sc_earlyz_tile_fifo_size;
1076
1077 unsigned num_shader_engines;
1078 unsigned num_shader_pipes_per_simd;
1079 unsigned num_tile_pipes;
1080 unsigned num_simds_per_se;
1081 unsigned num_backends_per_se;
1082 unsigned backend_disable_mask_per_asic;
1083 unsigned backend_map;
1084 unsigned num_texture_channel_caches;
1085 unsigned mem_max_burst_length_bytes;
1086 unsigned mem_row_size_in_kb;
1087 unsigned shader_engine_tile_size;
1088 unsigned num_gpus;
1089 unsigned multi_gpu_tile_size;
1090
1091 unsigned tile_config;
1092 struct r100_gpu_lockup lockup;
1093};
1094
068a117c
JG		 1095union radeon_asic_config {
1096 struct r300_asic r300;
551ebd83 1097 struct r100_asic r100;
3ce0a23d
JG		 1098 struct r600_asic r600;
1099 struct rv770_asic rv770;
32fcdbf4 1100 struct evergreen_asic evergreen;
fecf1d07 1101 struct cayman_asic cayman;
068a117c
JG		 1102};
1103
0a10c851
DV		 1104/*
1105 * asic initizalization from radeon_asic.c
1106 */
1107void radeon_agp_disable(struct radeon_device *rdev);
1108int radeon_asic_init(struct radeon_device *rdev);
1109
771fe6b9
JG		 1110
1111/*
1112 * IOCTL.
1113 */
1114int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1115 struct drm_file *filp);
1116int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1117 struct drm_file *filp);
1118int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv);
1120int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1121 struct drm_file *file_priv);
1122int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1123 struct drm_file *file_priv);
1124int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1125 struct drm_file *file_priv);
1126int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1127 struct drm_file *filp);
1128int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1129 struct drm_file *filp);
1130int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1131 struct drm_file *filp);
1132int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1133 struct drm_file *filp);
1134int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1135int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *filp);
1137int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1138 struct drm_file *filp);
771fe6b9 1139
16cdf04d
AD		 1140/* VRAM scratch page for HDP bug, default vram page */
1141struct r600_vram_scratch {
87cbf8f2
AD		 1142 struct radeon_bo *robj;
1143 volatile uint32_t *ptr;
16cdf04d 1144 u64 gpu_addr;
87cbf8f2 1145};
771fe6b9 1146
7a1619b9
MD		 1147
1148/*
1149 * Mutex which allows recursive locking from the same process.
1150 */
1151struct radeon_mutex {
1152 struct mutex mutex;
1153 struct task_struct *owner;
1154 int level;
1155};
1156
1157static inline void radeon_mutex_init(struct radeon_mutex *mutex)
1158{
1159 mutex_init(&mutex->mutex);
1160 mutex->owner = NULL;
1161 mutex->level = 0;
1162}
1163
1164static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
1165{
1166 if (mutex_trylock(&mutex->mutex)) {
1167 /* The mutex was unlocked before, so it's ours now */
1168 mutex->owner = current;
1169 } else if (mutex->owner != current) {
1170 /* Another process locked the mutex, take it */
1171 mutex_lock(&mutex->mutex);
1172 mutex->owner = current;
1173 }
1174 /* Otherwise the mutex was already locked by this process */
1175
1176 mutex->level++;
1177}
1178
1179static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
1180{
1181 if (--mutex->level > 0)
1182 return;
1183
1184 mutex->owner = NULL;
1185 mutex_unlock(&mutex->mutex);
1186}
1187
1188
771fe6b9
JG		 1189/*
1190 * Core structure, functions and helpers.
1191 */
1192typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1193typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1194
1195struct radeon_device {
9f022ddf 1196 struct device *dev;
771fe6b9
JG		 1197 struct drm_device *ddev;
1198 struct pci_dev *pdev;
1199 /* ASIC */
068a117c 1200 union radeon_asic_config config;
771fe6b9
JG		 1201 enum radeon_family family;
1202 unsigned long flags;
1203 int usec_timeout;
1204 enum radeon_pll_errata pll_errata;
1205 int num_gb_pipes;
f779b3e5 1206 int num_z_pipes;
771fe6b9
JG		 1207 int disp_priority;
1208 /* BIOS */
1209 uint8_t *bios;
1210 bool is_atom_bios;
1211 uint16_t bios_header_start;
4c788679 1212 struct radeon_bo *stollen_vga_memory;
771fe6b9 1213 /* Register mmio */
4c9bc75c
DA		 1214 resource_size_t rmmio_base;
1215 resource_size_t rmmio_size;
a0533fbf 1216 void __iomem *rmmio;
771fe6b9
JG		 1217 radeon_rreg_t mc_rreg;
1218 radeon_wreg_t mc_wreg;
1219 radeon_rreg_t pll_rreg;
1220 radeon_wreg_t pll_wreg;
de1b2898 1221 uint32_t pcie_reg_mask;
771fe6b9
JG		 1222 radeon_rreg_t pciep_rreg;
1223 radeon_wreg_t pciep_wreg;
351a52a2
AD		 1224 /* io port */
1225 void __iomem *rio_mem;
1226 resource_size_t rio_mem_size;
771fe6b9
JG		 1227 struct radeon_clock clock;
1228 struct radeon_mc mc;
1229 struct radeon_gart gart;
1230 struct radeon_mode_info mode_info;
1231 struct radeon_scratch scratch;
1232 struct radeon_mman mman;
1233 struct radeon_fence_driver fence_drv;
1234 struct radeon_cp cp;
0c88a02e
AD		 1235 /* cayman compute rings */
1236 struct radeon_cp cp1;
1237 struct radeon_cp cp2;
771fe6b9
JG		 1238 struct radeon_ib_pool ib_pool;
1239 struct radeon_irq irq;
1240 struct radeon_asic *asic;
1241 struct radeon_gem gem;
c93bb85b 1242 struct radeon_pm pm;
f657c2a7 1243 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
7a1619b9 1244 struct radeon_mutex cs_mutex;
771fe6b9 1245 struct radeon_wb wb;
3ce0a23d 1246 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 1247 bool gpu_lockup;
1248 bool shutdown;
1249 bool suspend;
ad49f501 1250 bool need_dma32;
733289c2 1251 bool accel_working;
e024e110 1252 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 1253 const struct firmware *me_fw; /* all family ME firmware */
1254 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 1255 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 1256 const struct firmware *mc_fw; /* NI MC firmware */
3ce0a23d 1257 struct r600_blit r600_blit;
16cdf04d 1258 struct r600_vram_scratch vram_scratch;
3e5cb98d 1259 int msi_enabled; /* msi enabled */
d8f60cfc 1260 struct r600_ih ih; /* r6/700 interrupt ring */
d4877cf2 1261 struct work_struct hotplug_work;
18917b60 1262 int num_crtc; /* number of crtcs */
40bacf16 1263 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
5876dd24 1264 struct mutex vram_mutex;
dafc3bd5
CK		 1265
1266 /* audio stuff */
7eea7e9e 1267 bool audio_enabled;
dafc3bd5
CK		 1268 struct timer_list audio_timer;
1269 int audio_channels;
1270 int audio_rate;
1271 int audio_bits_per_sample;
1272 uint8_t audio_status_bits;
1273 uint8_t audio_category_code;
6a9ee8af 1274
ce8f5370 1275 struct notifier_block acpi_nb;
9eba4a93 1276 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 1277 struct drm_file *hyperz_filp;
9eba4a93 1278 struct drm_file *cmask_filp;
f376b94f
AD		 1279 /* i2c buses */
1280 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
771fe6b9
JG		 1281};
1282
1283int radeon_device_init(struct radeon_device *rdev,
1284 struct drm_device *ddev,
1285 struct pci_dev *pdev,
1286 uint32_t flags);
1287void radeon_device_fini(struct radeon_device *rdev);
1288int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1289
6fcbef7a
AK		 1290uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1291void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1292u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1293void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 1294
4c788679
JG		 1295/*
1296 * Cast helper
1297 */
1298#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 1299
1300/*
1301 * Registers read & write functions.
1302 */
a0533fbf
BH		 1303#define RREG8(reg) readb((rdev->rmmio) + (reg))
1304#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1305#define RREG16(reg) readw((rdev->rmmio) + (reg))
1306#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
de1b2898 1307#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 1308#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 1309#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 1310#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1311#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1312#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1313#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1314#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1315#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 1316#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1317#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
aa5120d2
RM		 1318#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1319#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
771fe6b9
JG		 1320#define WREG32_P(reg, val, mask) \
1321 do { \
1322 uint32_t tmp_ = RREG32(reg); \
1323 tmp_ &= (mask); \
1324 tmp_ |= ((val) & ~(mask)); \
1325 WREG32(reg, tmp_); \
1326 } while (0)
1327#define WREG32_PLL_P(reg, val, mask) \
1328 do { \
1329 uint32_t tmp_ = RREG32_PLL(reg); \
1330 tmp_ &= (mask); \
1331 tmp_ |= ((val) & ~(mask)); \
1332 WREG32_PLL(reg, tmp_); \
1333 } while (0)
3ce0a23d 1334#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
351a52a2
AD		 1335#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1336#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 1337
de1b2898
DA		 1338/*
1339 * Indirect registers accessor
1340 */
1341static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1342{
1343 uint32_t r;
1344
1345 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1346 r = RREG32(RADEON_PCIE_DATA);
1347 return r;
1348}
1349
1350static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1351{
1352 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1353 WREG32(RADEON_PCIE_DATA, (v));
1354}
1355
771fe6b9
JG		 1356void r100_pll_errata_after_index(struct radeon_device *rdev);
1357
1358
1359/*
1360 * ASICs helpers.
1361 */
b995e433
DA		 1362#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1363 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 1364#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1365 (rdev->family == CHIP_RV200) || \
1366 (rdev->family == CHIP_RS100) || \
1367 (rdev->family == CHIP_RS200) || \
1368 (rdev->family == CHIP_RV250) || \
1369 (rdev->family == CHIP_RV280) || \
1370 (rdev->family == CHIP_RS300))
1371#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1372 (rdev->family == CHIP_RV350) || \
1373 (rdev->family == CHIP_R350) || \
1374 (rdev->family == CHIP_RV380) || \
1375 (rdev->family == CHIP_R420) || \
1376 (rdev->family == CHIP_R423) || \
1377 (rdev->family == CHIP_RV410) || \
1378 (rdev->family == CHIP_RS400) || \
1379 (rdev->family == CHIP_RS480))
3313e3d4
AD		 1380#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1381 (rdev->ddev->pdev->device == 0x9443) || \
1382 (rdev->ddev->pdev->device == 0x944B) || \
1383 (rdev->ddev->pdev->device == 0x9506) || \
1384 (rdev->ddev->pdev->device == 0x9509) || \
1385 (rdev->ddev->pdev->device == 0x950F) || \
1386 (rdev->ddev->pdev->device == 0x689C) || \
1387 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 1388#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 1389#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1390 (rdev->family == CHIP_RS690) || \
1391 (rdev->family == CHIP_RS740) || \
1392 (rdev->family >= CHIP_R600))
771fe6b9
JG		 1393#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1394#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 1395#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 1396#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1397 (rdev->flags & RADEON_IS_IGP))
1fe18305 1398#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
771fe6b9
JG		 1399
1400/*
1401 * BIOS helpers.
1402 */
1403#define RBIOS8(i) (rdev->bios[i])
1404#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1405#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1406
1407int radeon_combios_init(struct radeon_device *rdev);
1408void radeon_combios_fini(struct radeon_device *rdev);
1409int radeon_atombios_init(struct radeon_device *rdev);
1410void radeon_atombios_fini(struct radeon_device *rdev);
1411
1412
1413/*
1414 * RING helpers.
1415 */
ce580fab
AK		 1416
1417#if DRM_DEBUG_CODE == 0
771fe6b9
JG		 1418static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1419{
771fe6b9
JG		 1420 rdev->cp.ring[rdev->cp.wptr++] = v;
1421 rdev->cp.wptr &= rdev->cp.ptr_mask;
1422 rdev->cp.count_dw--;
1423 rdev->cp.ring_free_dw--;
1424}
ce580fab
AK		 1425#else
1426/* With debugging this is just too big to inline */
1427void radeon_ring_write(struct radeon_device *rdev, uint32_t v);
1428#endif
771fe6b9
JG		 1429
1430/*
1431 * ASICs macro.
1432 */
068a117c 1433#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 1434#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1435#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1436#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 1437#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 1438#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
225758d8 1439#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
a2d07b74 1440#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
771fe6b9
JG		 1441#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1442#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 1443#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 1444#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 1445#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1446#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 1447#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1448#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 1449#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 1450#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1451#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1452#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1453#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 1454#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 1455#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 1456#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
93e7de7b 1457#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
c836a412 1458#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
771fe6b9
JG		 1459#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1460#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 1461#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1462#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 1463#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
429770b3
AD		 1464#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1465#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1466#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1467#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
def9ba9c 1468#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a424816f
AD		 1469#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1470#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1471#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
ce8f5370
AD		 1472#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1473#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
6f34be50
AD		 1474#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1475#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1476#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
771fe6b9 1477
6cf8a3f5 1478/* Common functions */
700a0cc0 1479/* AGP */
90aca4d2 1480extern int radeon_gpu_reset(struct radeon_device *rdev);
700a0cc0 1481extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 1482extern int radeon_modeset_init(struct radeon_device *rdev);
1483extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1484extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 1485extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 1486extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 1487extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 1488extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 1489extern void radeon_wb_fini(struct radeon_device *rdev);
1490extern int radeon_wb_init(struct radeon_device *rdev);
1491extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1492extern void radeon_surface_init(struct radeon_device *rdev);
1493extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1494extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1495extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 1496extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 1497extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 1498extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1499extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 1500extern int radeon_resume_kms(struct drm_device *dev);
1501extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
53595338 1502extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
6cf8a3f5 1503
16cdf04d
AD		 1504/*
1505 * R600 vram scratch functions
1506 */
1507int r600_vram_scratch_init(struct radeon_device *rdev);
1508void r600_vram_scratch_fini(struct radeon_device *rdev);
1509
3574dda4
DV		 1510/*
1511 * r600 functions used by radeon_encoder.c
1512 */
2cd6218c
RM		 1513extern void r600_hdmi_enable(struct drm_encoder *encoder);
1514extern void r600_hdmi_disable(struct drm_encoder *encoder);
dafc3bd5 1515extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
fe251e2f 1516
0af62b01 1517extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 1518extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 1519
d7a2952f
AM		 1520/* radeon_acpi.c */
1521#if defined(CONFIG_ACPI)
1522extern int radeon_acpi_init(struct radeon_device *rdev);
1523#else
1524static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1525#endif
1526
4c788679
JG		 1527#include "radeon_object.h"
1528
771fe6b9 1529#endif
Linux 6.x block layer and io_uring tree(s)