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drm/radeon: fix audio disable on dce6+
[linux-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
363eb0b4 102extern int radeon_hard_reset;
771fe6b9
JG		 103
104/*
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 * symbol;
107 */
bb635567
JG		 108#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 110/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 111#define RADEON_IB_POOL_SIZE 16
112#define RADEON_DEBUGFS_MAX_COMPONENTS 32
113#define RADEONFB_CONN_LIMIT 4
114#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 115
1b37078b 116/* max number of rings */
f2ba57b5 117#define RADEON_NUM_RINGS 6
bb635567
JG		 118
119/* fence seq are set to this number when signaled */
120#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 121
122/* internal ring indices */
123/* r1xx+ has gfx CP ring */
f2ba57b5 124#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 125
126/* cayman has 2 compute CP rings */
f2ba57b5
CK		 127#define CAYMAN_RING_TYPE_CP1_INDEX 1
128#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 129
4d75658b
AD		 130/* R600+ has an async dma ring */
131#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 132/* cayman add a second async dma ring */
133#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 134
f2ba57b5
CK		 135/* R600+ */
136#define R600_RING_TYPE_UVD_INDEX 5
137
8f53492f
CK		 138/* number of hw syncs before falling back on blocking */
139#define RADEON_NUM_SYNCS 4
140
721604a1 141/* hardcode those limit for now */
ca19f21e 142#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 143#define RADEON_VA_RESERVED_SIZE (8 << 20)
144#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 145
1a0041b8
AD		 146/* hard reset data */
147#define RADEON_ASIC_RESET_DATA 0x39d5e86b
148
ec46c76d
AD		 149/* reset flags */
150#define RADEON_RESET_GFX (1 << 0)
151#define RADEON_RESET_COMPUTE (1 << 1)
152#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 153#define RADEON_RESET_CP (1 << 3)
154#define RADEON_RESET_GRBM (1 << 4)
155#define RADEON_RESET_DMA1 (1 << 5)
156#define RADEON_RESET_RLC (1 << 6)
157#define RADEON_RESET_SEM (1 << 7)
158#define RADEON_RESET_IH (1 << 8)
159#define RADEON_RESET_VMC (1 << 9)
160#define RADEON_RESET_MC (1 << 10)
161#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 162
22c775ce
AD		 163/* CG block flags */
164#define RADEON_CG_BLOCK_GFX (1 << 0)
165#define RADEON_CG_BLOCK_MC (1 << 1)
166#define RADEON_CG_BLOCK_SDMA (1 << 2)
167#define RADEON_CG_BLOCK_UVD (1 << 3)
168#define RADEON_CG_BLOCK_VCE (1 << 4)
169#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 170#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 171
64d8a728
AD		 172/* CG flags */
173#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
174#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
175#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
176#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
177#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
178#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
179#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
180#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
181#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
182#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
183#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
184#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
185#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
186#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
187#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
188#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
189#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
190
191/* PG flags */
2b19d17f 192#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 193#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
194#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
195#define RADEON_PG_SUPPORT_UVD (1 << 3)
196#define RADEON_PG_SUPPORT_VCE (1 << 4)
197#define RADEON_PG_SUPPORT_CP (1 << 5)
198#define RADEON_PG_SUPPORT_GDS (1 << 6)
199#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
200#define RADEON_PG_SUPPORT_SDMA (1 << 8)
201#define RADEON_PG_SUPPORT_ACP (1 << 9)
202#define RADEON_PG_SUPPORT_SAMU (1 << 10)
203
9e05fa1d
AD		 204/* max cursor sizes (in pixels) */
205#define CURSOR_WIDTH 64
206#define CURSOR_HEIGHT 64
207
208#define CIK_CURSOR_WIDTH 128
209#define CIK_CURSOR_HEIGHT 128
210
771fe6b9
JG		 211/*
212 * Errata workarounds.
213 */
214enum radeon_pll_errata {
215 CHIP_ERRATA_R300_CG = 0x00000001,
216 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
217 CHIP_ERRATA_PLL_DELAY = 0x00000004
218};
219
220
221struct radeon_device;
222
223
224/*
225 * BIOS.
226 */
227bool radeon_get_bios(struct radeon_device *rdev);
228
229/*
3ce0a23d 230 * Dummy page
771fe6b9 231 */
3ce0a23d
JG		 232struct radeon_dummy_page {
233 struct page *page;
234 dma_addr_t addr;
235};
236int radeon_dummy_page_init(struct radeon_device *rdev);
237void radeon_dummy_page_fini(struct radeon_device *rdev);
238
771fe6b9 239
3ce0a23d
JG		 240/*
241 * Clocks
242 */
771fe6b9
JG		 243struct radeon_clock {
244 struct radeon_pll p1pll;
245 struct radeon_pll p2pll;
bcc1c2a1 246 struct radeon_pll dcpll;
771fe6b9
JG		 247 struct radeon_pll spll;
248 struct radeon_pll mpll;
249 /* 10 Khz units */
250 uint32_t default_mclk;
251 uint32_t default_sclk;
bcc1c2a1 252 uint32_t default_dispclk;
4489cd62 253 uint32_t current_dispclk;
bcc1c2a1 254 uint32_t dp_extclk;
b20f9bef 255 uint32_t max_pixel_clock;
771fe6b9
JG		 256};
257
7433874e
RM		 258/*
259 * Power management
260 */
261int radeon_pm_init(struct radeon_device *rdev);
914a8987 262int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 263void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 264void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 265void radeon_pm_suspend(struct radeon_device *rdev);
266void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 267void radeon_combios_get_power_modes(struct radeon_device *rdev);
268void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 269int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
270 u8 clock_type,
271 u32 clock,
272 bool strobe_mode,
273 struct atom_clock_dividers *dividers);
eaa778af
AD		 274int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
275 u32 clock,
276 bool strobe_mode,
277 struct atom_mpll_param *mpll_param);
8a83ec5e 278void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 279int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
280 u16 voltage_level, u8 voltage_type,
281 u32 *gpio_value, u32 *gpio_mask);
282void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
283 u32 eng_clock, u32 mem_clock);
284int radeon_atom_get_voltage_step(struct radeon_device *rdev,
285 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 286int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
287 u16 voltage_id, u16 *voltage);
beb79f40
AD		 288int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
289 u16 *voltage,
290 u16 leakage_idx);
cc8dbbb4
AD		 291int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
292 u16 *leakage_id);
293int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
294 u16 *vddc, u16 *vddci,
295 u16 virtual_voltage_id,
296 u16 vbios_voltage_id);
ae5b0abb
AD		 297int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
298 u8 voltage_type,
299 u16 nominal_voltage,
300 u16 *true_voltage);
301int radeon_atom_get_min_voltage(struct radeon_device *rdev,
302 u8 voltage_type, u16 *min_voltage);
303int radeon_atom_get_max_voltage(struct radeon_device *rdev,
304 u8 voltage_type, u16 *max_voltage);
305int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 306 u8 voltage_type, u8 voltage_mode,
ae5b0abb 307 struct atom_voltage_table *voltage_table);
58653abd
AD		 308bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
309 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 310void radeon_atom_update_memory_dll(struct radeon_device *rdev,
311 u32 mem_clock);
312void radeon_atom_set_ac_timing(struct radeon_device *rdev,
313 u32 mem_clock);
314int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
315 u8 module_index,
316 struct atom_mc_reg_table *reg_table);
317int radeon_atom_get_memory_info(struct radeon_device *rdev,
318 u8 module_index, struct atom_memory_info *mem_info);
319int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
320 bool gddr5, u8 module_index,
321 struct atom_memory_clock_range_table *mclk_range_table);
322int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
323 u16 voltage_id, u16 *voltage);
f892034a 324void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 325extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
326 unsigned *bankh, unsigned *mtaspect,
327 unsigned *tile_split);
3ce0a23d 328
771fe6b9
JG		 329/*
330 * Fences.
331 */
332struct radeon_fence_driver {
333 uint32_t scratch_reg;
30eb77f4
JG		 334 uint64_t gpu_addr;
335 volatile uint32_t *cpu_addr;
68e250b7
CK		 336 /* sync_seq is protected by ring emission lock */
337 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 338 atomic64_t last_seq;
0a0c7596 339 bool initialized;
771fe6b9
JG		 340};
341
342struct radeon_fence {
343 struct radeon_device *rdev;
344 struct kref kref;
771fe6b9 345 /* protected by radeon_fence.lock */
bb635567 346 uint64_t seq;
7465280c 347 /* RB, DMA, etc. */
bb635567 348 unsigned ring;
771fe6b9
JG		 349};
350
30eb77f4
JG		 351int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
352int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 353void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 354void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 355int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 356void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 357bool radeon_fence_signaled(struct radeon_fence *fence);
358int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
1654b817 359int radeon_fence_wait_locked(struct radeon_fence *fence);
8a47cc9e 360int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 361int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 362int radeon_fence_wait_any(struct radeon_device *rdev,
363 struct radeon_fence **fences,
364 bool intr);
771fe6b9
JG		 365struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
366void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 367unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 368bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
369void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
370static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
371 struct radeon_fence *b)
372{
373 if (!a) {
374 return b;
375 }
376
377 if (!b) {
378 return a;
379 }
380
381 BUG_ON(a->ring != b->ring);
382
383 if (a->seq > b->seq) {
384 return a;
385 } else {
386 return b;
387 }
388}
771fe6b9 389
ee60e29f
CK		 390static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
391 struct radeon_fence *b)
392{
393 if (!a) {
394 return false;
395 }
396
397 if (!b) {
398 return true;
399 }
400
401 BUG_ON(a->ring != b->ring);
402
403 return a->seq < b->seq;
404}
405
e024e110
DA		 406/*
407 * Tiling registers
408 */
409struct radeon_surface_reg {
4c788679 410 struct radeon_bo *bo;
e024e110
DA		 411};
412
413#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 414
415/*
4c788679 416 * TTM.
771fe6b9 417 */
4c788679
JG		 418struct radeon_mman {
419 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 420 struct drm_global_reference mem_global_ref;
4c788679 421 struct ttm_bo_device bdev;
0a0c7596
JG		 422 bool mem_global_referenced;
423 bool initialized;
2014b569
CK		 424
425#if defined(CONFIG_DEBUG_FS)
426 struct dentry *vram;
dd66d20e 427 struct dentry *gtt;
2014b569 428#endif
4c788679
JG		 429};
430
721604a1
JG		 431/* bo virtual address in a specific vm */
432struct radeon_bo_va {
e971bd5e 433 /* protected by bo being reserved */
721604a1 434 struct list_head bo_list;
721604a1
JG		 435 uint64_t soffset;
436 uint64_t eoffset;
437 uint32_t flags;
438 bool valid;
e971bd5e
CK		 439 unsigned ref_count;
440
441 /* protected by vm mutex */
442 struct list_head vm_list;
443
444 /* constant after initialization */
445 struct radeon_vm *vm;
446 struct radeon_bo *bo;
721604a1
JG		 447};
448
4c788679
JG		 449struct radeon_bo {
450 /* Protected by gem.mutex */
451 struct list_head list;
452 /* Protected by tbo.reserved */
312ea8da
JG		 453 u32 placements[3];
454 struct ttm_placement placement;
4c788679
JG		 455 struct ttm_buffer_object tbo;
456 struct ttm_bo_kmap_obj kmap;
457 unsigned pin_count;
458 void *kptr;
459 u32 tiling_flags;
460 u32 pitch;
461 int surface_reg;
721604a1
JG		 462 /* list of all virtual address to which this bo
463 * is associated to
464 */
465 struct list_head va;
4c788679
JG		 466 /* Constant after initialization */
467 struct radeon_device *rdev;
441921d5 468 struct drm_gem_object gem_base;
63bc620b 469
409851f4
JG		 470 struct ttm_bo_kmap_obj dma_buf_vmap;
471 pid_t pid;
4c788679 472};
7e4d15d9 473#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 474
4c788679 475struct radeon_bo_list {
147666fb 476 struct ttm_validate_buffer tv;
4c788679 477 struct radeon_bo *bo;
771fe6b9 478 uint64_t gpu_offset;
4474f3a9
CK		 479 bool written;
480 unsigned domain;
481 unsigned alt_domain;
4c788679 482 u32 tiling_flags;
771fe6b9
JG		 483};
484
409851f4
JG		 485int radeon_gem_debugfs_init(struct radeon_device *rdev);
486
b15ba512
JG		 487/* sub-allocation manager, it has to be protected by another lock.
488 * By conception this is an helper for other part of the driver
489 * like the indirect buffer or semaphore, which both have their
490 * locking.
491 *
492 * Principe is simple, we keep a list of sub allocation in offset
493 * order (first entry has offset == 0, last entry has the highest
494 * offset).
495 *
496 * When allocating new object we first check if there is room at
497 * the end total_size - (last_object_offset + last_object_size) >=
498 * alloc_size. If so we allocate new object there.
499 *
500 * When there is not enough room at the end, we start waiting for
501 * each sub object until we reach object_offset+object_size >=
502 * alloc_size, this object then become the sub object we return.
503 *
504 * Alignment can't be bigger than page size.
505 *
506 * Hole are not considered for allocation to keep things simple.
507 * Assumption is that there won't be hole (all object on same
508 * alignment).
509 */
510struct radeon_sa_manager {
bfb38d35 511 wait_queue_head_t wq;
b15ba512 512 struct radeon_bo *bo;
c3b7fe8b
CK		 513 struct list_head *hole;
514 struct list_head flist[RADEON_NUM_RINGS];
515 struct list_head olist;
b15ba512
JG		 516 unsigned size;
517 uint64_t gpu_addr;
518 void *cpu_ptr;
519 uint32_t domain;
6c4f978b 520 uint32_t align;
b15ba512
JG		 521};
522
523struct radeon_sa_bo;
524
525/* sub-allocation buffer */
526struct radeon_sa_bo {
c3b7fe8b
CK		 527 struct list_head olist;
528 struct list_head flist;
b15ba512 529 struct radeon_sa_manager *manager;
e6661a96
CK		 530 unsigned soffset;
531 unsigned eoffset;
557017a0 532 struct radeon_fence *fence;
b15ba512
JG		 533};
534
771fe6b9
JG		 535/*
536 * GEM objects.
537 */
538struct radeon_gem {
4c788679 539 struct mutex mutex;
771fe6b9
JG		 540 struct list_head objects;
541};
542
543int radeon_gem_init(struct radeon_device *rdev);
544void radeon_gem_fini(struct radeon_device *rdev);
545int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 546 int alignment, int initial_domain,
547 bool discardable, bool kernel,
548 struct drm_gem_object **obj);
771fe6b9 549
ff72145b
DA		 550int radeon_mode_dumb_create(struct drm_file *file_priv,
551 struct drm_device *dev,
552 struct drm_mode_create_dumb *args);
553int radeon_mode_dumb_mmap(struct drm_file *filp,
554 struct drm_device *dev,
555 uint32_t handle, uint64_t *offset_p);
771fe6b9 556
c1341e52
JG		 557/*
558 * Semaphores.
559 */
c1341e52 560struct radeon_semaphore {
a8c05940
JG		 561 struct radeon_sa_bo *sa_bo;
562 signed waiters;
c1341e52 563 uint64_t gpu_addr;
1654b817 564 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 565};
566
c1341e52
JG		 567int radeon_semaphore_create(struct radeon_device *rdev,
568 struct radeon_semaphore **semaphore);
1654b817 569bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 570 struct radeon_semaphore *semaphore);
1654b817 571bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 572 struct radeon_semaphore *semaphore);
1654b817
CK		 573void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
574 struct radeon_fence *fence);
8f676c4c
CK		 575int radeon_semaphore_sync_rings(struct radeon_device *rdev,
576 struct radeon_semaphore *semaphore,
1654b817 577 int waiting_ring);
c1341e52 578void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 579 struct radeon_semaphore **semaphore,
a8c05940 580 struct radeon_fence *fence);
c1341e52 581
771fe6b9
JG		 582/*
583 * GART structures, functions & helpers
584 */
585struct radeon_mc;
586
a77f1718 587#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 588#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 589#define RADEON_GPU_PAGE_SHIFT 12
721604a1 590#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 591
771fe6b9
JG		 592struct radeon_gart {
593 dma_addr_t table_addr;
c9a1be96
JG		 594 struct radeon_bo *robj;
595 void *ptr;
771fe6b9
JG		 596 unsigned num_gpu_pages;
597 unsigned num_cpu_pages;
598 unsigned table_size;
771fe6b9
JG		 599 struct page **pages;
600 dma_addr_t *pages_addr;
601 bool ready;
602};
603
604int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
605void radeon_gart_table_ram_free(struct radeon_device *rdev);
606int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
607void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 608int radeon_gart_table_vram_pin(struct radeon_device *rdev);
609void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 610int radeon_gart_init(struct radeon_device *rdev);
611void radeon_gart_fini(struct radeon_device *rdev);
612void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
613 int pages);
614int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 615 int pages, struct page **pagelist,
616 dma_addr_t *dma_addr);
c9a1be96 617void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 618
619
620/*
621 * GPU MC structures, functions & helpers
622 */
623struct radeon_mc {
624 resource_size_t aper_size;
625 resource_size_t aper_base;
626 resource_size_t agp_base;
7a50f01a
DA		 627 /* for some chips with <= 32MB we need to lie
628 * about vram size near mc fb location */
3ce0a23d 629 u64 mc_vram_size;
d594e46a 630 u64 visible_vram_size;
3ce0a23d
JG		 631 u64 gtt_size;
632 u64 gtt_start;
633 u64 gtt_end;
3ce0a23d
JG		 634 u64 vram_start;
635 u64 vram_end;
771fe6b9 636 unsigned vram_width;
3ce0a23d 637 u64 real_vram_size;
771fe6b9
JG		 638 int vram_mtrr;
639 bool vram_is_ddr;
d594e46a 640 bool igp_sideport_enabled;
8d369bb1 641 u64 gtt_base_align;
9ed8b1f9 642 u64 mc_mask;
771fe6b9
JG		 643};
644
06b6476d
AD		 645bool radeon_combios_sideport_present(struct radeon_device *rdev);
646bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 647
648/*
649 * GPU scratch registers structures, functions & helpers
650 */
651struct radeon_scratch {
652 unsigned num_reg;
724c80e1 653 uint32_t reg_base;
771fe6b9
JG		 654 bool free[32];
655 uint32_t reg[32];
656};
657
658int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
659void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
660
75efdee1
AD		 661/*
662 * GPU doorbell structures, functions & helpers
663 */
d5754ab8
AL		 664#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
665
75efdee1 666struct radeon_doorbell {
75efdee1 667 /* doorbell mmio */
d5754ab8
AL		 668 resource_size_t base;
669 resource_size_t size;
670 u32 __iomem *ptr;
671 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
672 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 673};
674
675int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
676void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 677
678/*
679 * IRQS.
680 */
6f34be50
AD		 681
682struct radeon_unpin_work {
683 struct work_struct work;
684 struct radeon_device *rdev;
685 int crtc_id;
686 struct radeon_fence *fence;
687 struct drm_pending_vblank_event *event;
688 struct radeon_bo *old_rbo;
689 u64 new_crtc_base;
690};
691
692struct r500_irq_stat_regs {
693 u32 disp_int;
f122c610 694 u32 hdmi0_status;
6f34be50
AD		 695};
696
697struct r600_irq_stat_regs {
698 u32 disp_int;
699 u32 disp_int_cont;
700 u32 disp_int_cont2;
701 u32 d1grph_int;
702 u32 d2grph_int;
f122c610
AD		 703 u32 hdmi0_status;
704 u32 hdmi1_status;
6f34be50
AD		 705};
706
707struct evergreen_irq_stat_regs {
708 u32 disp_int;
709 u32 disp_int_cont;
710 u32 disp_int_cont2;
711 u32 disp_int_cont3;
712 u32 disp_int_cont4;
713 u32 disp_int_cont5;
714 u32 d1grph_int;
715 u32 d2grph_int;
716 u32 d3grph_int;
717 u32 d4grph_int;
718 u32 d5grph_int;
719 u32 d6grph_int;
f122c610
AD		 720 u32 afmt_status1;
721 u32 afmt_status2;
722 u32 afmt_status3;
723 u32 afmt_status4;
724 u32 afmt_status5;
725 u32 afmt_status6;
6f34be50
AD		 726};
727
a59781bb
AD		 728struct cik_irq_stat_regs {
729 u32 disp_int;
730 u32 disp_int_cont;
731 u32 disp_int_cont2;
732 u32 disp_int_cont3;
733 u32 disp_int_cont4;
734 u32 disp_int_cont5;
735 u32 disp_int_cont6;
736};
737
6f34be50
AD		 738union radeon_irq_stat_regs {
739 struct r500_irq_stat_regs r500;
740 struct r600_irq_stat_regs r600;
741 struct evergreen_irq_stat_regs evergreen;
a59781bb 742 struct cik_irq_stat_regs cik;
6f34be50
AD		 743};
744
54bd5206
IH		 745#define RADEON_MAX_HPD_PINS 6
746#define RADEON_MAX_CRTCS 6
b530602f 747#define RADEON_MAX_AFMT_BLOCKS 7
54bd5206 748
771fe6b9 749struct radeon_irq {
fb98257a
CK		 750 bool installed;
751 spinlock_t lock;
736fc37f 752 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 753 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 754 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 755 wait_queue_head_t vblank_queue;
756 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 757 bool afmt[RADEON_MAX_AFMT_BLOCKS];
758 union radeon_irq_stat_regs stat_regs;
4a6369e9 759 bool dpm_thermal;
771fe6b9
JG		 760};
761
762int radeon_irq_kms_init(struct radeon_device *rdev);
763void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 764void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
765void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 766void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
767void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 768void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
769void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
770void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 772
773/*
e32eb50d 774 * CP & rings.
771fe6b9 775 */
7465280c 776
771fe6b9 777struct radeon_ib {
68470ae7
JG		 778 struct radeon_sa_bo *sa_bo;
779 uint32_t length_dw;
780 uint64_t gpu_addr;
781 uint32_t *ptr;
876dc9f3 782 int ring;
68470ae7 783 struct radeon_fence *fence;
4bf3dd92 784 struct radeon_vm *vm;
68470ae7
JG		 785 bool is_const_ib;
786 struct radeon_semaphore *semaphore;
771fe6b9
JG		 787};
788
e32eb50d 789struct radeon_ring {
4c788679 790 struct radeon_bo *ring_obj;
771fe6b9
JG		 791 volatile uint32_t *ring;
792 unsigned rptr;
5596a9db 793 unsigned rptr_offs;
45df6803 794 unsigned rptr_save_reg;
89d35807
AD		 795 u64 next_rptr_gpu_addr;
796 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 797 unsigned wptr;
798 unsigned wptr_old;
799 unsigned ring_size;
800 unsigned ring_free_dw;
801 int count_dw;
069211e5
CK		 802 unsigned long last_activity;
803 unsigned last_rptr;
771fe6b9
JG		 804 uint64_t gpu_addr;
805 uint32_t align_mask;
806 uint32_t ptr_mask;
771fe6b9 807 bool ready;
78c5560a 808 u32 nop;
8b25ed34 809 u32 idx;
5f0839c1
JG		 810 u64 last_semaphore_signal_addr;
811 u64 last_semaphore_wait_addr;
963e81f9
AD		 812 /* for CIK queues */
813 u32 me;
814 u32 pipe;
815 u32 queue;
816 struct radeon_bo *mqd_obj;
d5754ab8 817 u32 doorbell_index;
963e81f9
AD		 818 unsigned wptr_offs;
819};
820
821struct radeon_mec {
822 struct radeon_bo *hpd_eop_obj;
823 u64 hpd_eop_gpu_addr;
824 u32 num_pipe;
825 u32 num_mec;
826 u32 num_queue;
771fe6b9
JG		 827};
828
721604a1
JG		 829/*
830 * VM
831 */
ee60e29f 832
fa87e62d 833/* maximum number of VMIDs */
ee60e29f
CK		 834#define RADEON_NUM_VM 16
835
fa87e62d
DC		 836/* defines number of bits in page table versus page directory,
837 * a page is 4KB so we have 12 bits offset, 9 bits in the page
838 * table and the remaining 19 bits are in the page directory */
839#define RADEON_VM_BLOCK_SIZE 9
840
841/* number of entries in page table */
842#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
843
1c01103c
AD		 844/* PTBs (Page Table Blocks) need to be aligned to 32K */
845#define RADEON_VM_PTB_ALIGN_SIZE 32768
846#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
847#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
848
24c16439
CK		 849#define R600_PTE_VALID (1 << 0)
850#define R600_PTE_SYSTEM (1 << 1)
851#define R600_PTE_SNOOPED (1 << 2)
852#define R600_PTE_READABLE (1 << 5)
853#define R600_PTE_WRITEABLE (1 << 6)
854
721604a1
JG		 855struct radeon_vm {
856 struct list_head list;
857 struct list_head va;
ee60e29f 858 unsigned id;
90a51a32
CK		 859
860 /* contains the page directory */
861 struct radeon_sa_bo *page_directory;
862 uint64_t pd_gpu_addr;
863
864 /* array of page tables, one for each page directory entry */
865 struct radeon_sa_bo **page_tables;
866
721604a1
JG		 867 struct mutex mutex;
868 /* last fence for cs using this vm */
869 struct radeon_fence *fence;
9b40e5d8
CK		 870 /* last flush or NULL if we still need to flush */
871 struct radeon_fence *last_flush;
593b2635
CK		 872 /* last use of vmid */
873 struct radeon_fence *last_id_use;
721604a1
JG		 874};
875
721604a1 876struct radeon_vm_manager {
36ff39c4 877 struct mutex lock;
721604a1 878 struct list_head lru_vm;
ee60e29f 879 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 880 struct radeon_sa_manager sa_manager;
881 uint32_t max_pfn;
721604a1
JG		 882 /* number of VMIDs */
883 unsigned nvm;
884 /* vram base address for page table entry */
885 u64 vram_base_offset;
67e915e4
AD		 886 /* is vm enabled? */
887 bool enabled;
721604a1
JG		 888};
889
890/*
891 * file private structure
892 */
893struct radeon_fpriv {
894 struct radeon_vm vm;
895};
896
d8f60cfc
AD		 897/*
898 * R6xx+ IH ring
899 */
900struct r600_ih {
4c788679 901 struct radeon_bo *ring_obj;
d8f60cfc
AD		 902 volatile uint32_t *ring;
903 unsigned rptr;
d8f60cfc
AD		 904 unsigned ring_size;
905 uint64_t gpu_addr;
d8f60cfc 906 uint32_t ptr_mask;
c20dc369 907 atomic_t lock;
d8f60cfc
AD		 908 bool enabled;
909};
910
347e7592 911/*
2948f5e6 912 * RLC stuff
347e7592 913 */
2948f5e6
AD		 914#include "clearstate_defs.h"
915
916struct radeon_rlc {
347e7592
AD		 917 /* for power gating */
918 struct radeon_bo *save_restore_obj;
919 uint64_t save_restore_gpu_addr;
2948f5e6 920 volatile uint32_t *sr_ptr;
1fd11777 921 const u32 *reg_list;
2948f5e6 922 u32 reg_list_size;
347e7592
AD		 923 /* for clear state */
924 struct radeon_bo *clear_state_obj;
925 uint64_t clear_state_gpu_addr;
2948f5e6 926 volatile uint32_t *cs_ptr;
1fd11777 927 const struct cs_section_def *cs_data;
22c775ce
AD		 928 u32 clear_state_size;
929 /* for cp tables */
930 struct radeon_bo *cp_table_obj;
931 uint64_t cp_table_gpu_addr;
932 volatile uint32_t *cp_table_ptr;
933 u32 cp_table_size;
347e7592
AD		 934};
935
69e130a6 936int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 937 struct radeon_ib *ib, struct radeon_vm *vm,
938 unsigned size);
f2e39221 939void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 940int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
941 struct radeon_ib *const_ib);
771fe6b9
JG		 942int radeon_ib_pool_init(struct radeon_device *rdev);
943void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 944int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 945/* Ring access between begin & end cannot sleep */
89d35807
AD		 946bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
947 struct radeon_ring *ring);
e32eb50d
CK		 948void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
949int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
950int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
951void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
952void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 953void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 954void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
955int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 956void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 957void radeon_ring_lockup_update(struct radeon_ring *ring);
958bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 959unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
960 uint32_t **data);
961int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
962 unsigned size, uint32_t *data);
e32eb50d 963int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 964 unsigned rptr_offs, u32 nop);
e32eb50d 965void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 966
967
4d75658b
AD		 968/* r600 async dma */
969void r600_dma_stop(struct radeon_device *rdev);
970int r600_dma_resume(struct radeon_device *rdev);
971void r600_dma_fini(struct radeon_device *rdev);
972
8c5fd7ef
AD		 973void cayman_dma_stop(struct radeon_device *rdev);
974int cayman_dma_resume(struct radeon_device *rdev);
975void cayman_dma_fini(struct radeon_device *rdev);
976
771fe6b9
JG		 977/*
978 * CS.
979 */
980struct radeon_cs_reloc {
981 struct drm_gem_object *gobj;
4c788679
JG		 982 struct radeon_bo *robj;
983 struct radeon_bo_list lobj;
771fe6b9
JG		 984 uint32_t handle;
985 uint32_t flags;
986};
987
988struct radeon_cs_chunk {
989 uint32_t chunk_id;
990 uint32_t length_dw;
991 uint32_t *kdata;
721604a1 992 void __user *user_ptr;
771fe6b9
JG		 993};
994
995struct radeon_cs_parser {
c8c15ff1 996 struct device *dev;
771fe6b9
JG		 997 struct radeon_device *rdev;
998 struct drm_file *filp;
999 /* chunks */
1000 unsigned nchunks;
1001 struct radeon_cs_chunk *chunks;
1002 uint64_t *chunks_array;
1003 /* IB */
1004 unsigned idx;
1005 /* relocations */
1006 unsigned nrelocs;
1007 struct radeon_cs_reloc *relocs;
1008 struct radeon_cs_reloc **relocs_ptr;
1009 struct list_head validated;
cf4ccd01 1010 unsigned dma_reloc_idx;
771fe6b9
JG		 1011 /* indices of various chunks */
1012 int chunk_ib_idx;
1013 int chunk_relocs_idx;
721604a1 1014 int chunk_flags_idx;
dfcf5f36 1015 int chunk_const_ib_idx;
f2e39221
JG		 1016 struct radeon_ib ib;
1017 struct radeon_ib const_ib;
771fe6b9 1018 void *track;
3ce0a23d 1019 unsigned family;
e70f224c 1020 int parser_error;
721604a1
JG		 1021 u32 cs_flags;
1022 u32 ring;
1023 s32 priority;
ecff665f 1024 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1025};
1026
28a326c5
ML		 1027static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1028{
1029 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1030
1031 if (ibc->kdata)
1032 return ibc->kdata[idx];
1033 return p->ib.ptr[idx];
1034}
1035
513bcb46 1036
771fe6b9
JG		 1037struct radeon_cs_packet {
1038 unsigned idx;
1039 unsigned type;
1040 unsigned reg;
1041 unsigned opcode;
1042 int count;
1043 unsigned one_reg_wr;
1044};
1045
1046typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1047 struct radeon_cs_packet *pkt,
1048 unsigned idx, unsigned reg);
1049typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1050 struct radeon_cs_packet *pkt);
1051
1052
1053/*
1054 * AGP
1055 */
1056int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1057void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1058void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1059void radeon_agp_fini(struct radeon_device *rdev);
1060
1061
1062/*
1063 * Writeback
1064 */
1065struct radeon_wb {
4c788679 1066 struct radeon_bo *wb_obj;
771fe6b9
JG		 1067 volatile uint32_t *wb;
1068 uint64_t gpu_addr;
724c80e1 1069 bool enabled;
d0f8a854 1070 bool use_event;
771fe6b9
JG		 1071};
1072
724c80e1 1073#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1074#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1075#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1076#define RADEON_WB_CP1_RPTR_OFFSET 1280
1077#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1078#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1079#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1080#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1081#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1082#define CIK_WB_CP1_WPTR_OFFSET 3328
1083#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1084
c93bb85b
JG		 1085/**
1086 * struct radeon_pm - power management datas
1087 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1088 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1089 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1090 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1091 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1092 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1093 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1094 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1095 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1096 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1097 * @needed_bandwidth: current bandwidth needs
1098 *
1099 * It keeps track of various data needed to take powermanagement decision.
25985edc 1100 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1101 * Equation between gpu/memory clock and available bandwidth is hw dependent
1102 * (type of memory, bus size, efficiency, ...)
1103 */
ce8f5370
AD		 1104
1105enum radeon_pm_method {
1106 PM_METHOD_PROFILE,
1107 PM_METHOD_DYNPM,
da321c8a 1108 PM_METHOD_DPM,
ce8f5370
AD		 1109};
1110
1111enum radeon_dynpm_state {
1112 DYNPM_STATE_DISABLED,
1113 DYNPM_STATE_MINIMUM,
1114 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1115 DYNPM_STATE_ACTIVE,
1116 DYNPM_STATE_SUSPENDED,
c913e23a 1117};
ce8f5370
AD		 1118enum radeon_dynpm_action {
1119 DYNPM_ACTION_NONE,
1120 DYNPM_ACTION_MINIMUM,
1121 DYNPM_ACTION_DOWNCLOCK,
1122 DYNPM_ACTION_UPCLOCK,
1123 DYNPM_ACTION_DEFAULT
c913e23a 1124};
56278a8e
AD		 1125
1126enum radeon_voltage_type {
1127 VOLTAGE_NONE = 0,
1128 VOLTAGE_GPIO,
1129 VOLTAGE_VDDC,
1130 VOLTAGE_SW
1131};
1132
0ec0e74f 1133enum radeon_pm_state_type {
da321c8a 1134 /* not used for dpm */
0ec0e74f
AD		 1135 POWER_STATE_TYPE_DEFAULT,
1136 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1137 /* user selectable states */
0ec0e74f
AD		 1138 POWER_STATE_TYPE_BATTERY,
1139 POWER_STATE_TYPE_BALANCED,
1140 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1141 /* internal states */
1142 POWER_STATE_TYPE_INTERNAL_UVD,
1143 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1144 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1145 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1146 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1147 POWER_STATE_TYPE_INTERNAL_BOOT,
1148 POWER_STATE_TYPE_INTERNAL_THERMAL,
1149 POWER_STATE_TYPE_INTERNAL_ACPI,
1150 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1151 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1152};
1153
ce8f5370
AD		 1154enum radeon_pm_profile_type {
1155 PM_PROFILE_DEFAULT,
1156 PM_PROFILE_AUTO,
1157 PM_PROFILE_LOW,
c9e75b21 1158 PM_PROFILE_MID,
ce8f5370
AD		 1159 PM_PROFILE_HIGH,
1160};
1161
1162#define PM_PROFILE_DEFAULT_IDX 0
1163#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1164#define PM_PROFILE_MID_SH_IDX 2
1165#define PM_PROFILE_HIGH_SH_IDX 3
1166#define PM_PROFILE_LOW_MH_IDX 4
1167#define PM_PROFILE_MID_MH_IDX 5
1168#define PM_PROFILE_HIGH_MH_IDX 6
1169#define PM_PROFILE_MAX 7
ce8f5370
AD		 1170
1171struct radeon_pm_profile {
1172 int dpms_off_ps_idx;
1173 int dpms_on_ps_idx;
1174 int dpms_off_cm_idx;
1175 int dpms_on_cm_idx;
516d0e46
AD		 1176};
1177
21a8122a
AD		 1178enum radeon_int_thermal_type {
1179 THERMAL_TYPE_NONE,
da321c8a
AD		 1180 THERMAL_TYPE_EXTERNAL,
1181 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1182 THERMAL_TYPE_RV6XX,
1183 THERMAL_TYPE_RV770,
da321c8a 1184 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1185 THERMAL_TYPE_EVERGREEN,
e33df25f 1186 THERMAL_TYPE_SUMO,
4fddba1f 1187 THERMAL_TYPE_NI,
14607d08 1188 THERMAL_TYPE_SI,
da321c8a 1189 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1190 THERMAL_TYPE_CI,
16fbe00d 1191 THERMAL_TYPE_KV,
21a8122a
AD		 1192};
1193
56278a8e
AD		 1194struct radeon_voltage {
1195 enum radeon_voltage_type type;
1196 /* gpio voltage */
1197 struct radeon_gpio_rec gpio;
1198 u32 delay; /* delay in usec from voltage drop to sclk change */
1199 bool active_high; /* voltage drop is active when bit is high */
1200 /* VDDC voltage */
1201 u8 vddc_id; /* index into vddc voltage table */
1202 u8 vddci_id; /* index into vddci voltage table */
1203 bool vddci_enabled;
1204 /* r6xx+ sw */
2feea49a
AD		 1205 u16 voltage;
1206 /* evergreen+ vddci */
1207 u16 vddci;
56278a8e
AD		 1208};
1209
d7311171
AD		 1210/* clock mode flags */
1211#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1212
56278a8e
AD		 1213struct radeon_pm_clock_info {
1214 /* memory clock */
1215 u32 mclk;
1216 /* engine clock */
1217 u32 sclk;
1218 /* voltage info */
1219 struct radeon_voltage voltage;
d7311171 1220 /* standardized clock flags */
56278a8e
AD		 1221 u32 flags;
1222};
1223
a48b9b4e 1224/* state flags */
d7311171 1225#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1226
56278a8e 1227struct radeon_power_state {
0ec0e74f 1228 enum radeon_pm_state_type type;
8f3f1c9a 1229 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1230 /* number of valid clock modes in this power state */
1231 int num_clock_modes;
56278a8e 1232 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1233 /* standardized state flags */
1234 u32 flags;
79daedc9
AD		 1235 u32 misc; /* vbios specific flags */
1236 u32 misc2; /* vbios specific flags */
1237 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1238};
1239
27459324
RM		 1240/*
1241 * Some modes are overclocked by very low value, accept them
1242 */
1243#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1244
2e9d4c05
AD		 1245enum radeon_dpm_auto_throttle_src {
1246 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1247 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1248};
1249
1250enum radeon_dpm_event_src {
1251 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1252 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1253 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1254 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1255 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1256};
1257
da321c8a
AD		 1258struct radeon_ps {
1259 u32 caps; /* vbios flags */
1260 u32 class; /* vbios flags */
1261 u32 class2; /* vbios flags */
1262 /* UVD clocks */
1263 u32 vclk;
1264 u32 dclk;
c4453e66
AD		 1265 /* VCE clocks */
1266 u32 evclk;
1267 u32 ecclk;
da321c8a
AD		 1268 /* asic priv */
1269 void *ps_priv;
1270};
1271
1272struct radeon_dpm_thermal {
1273 /* thermal interrupt work */
1274 struct work_struct work;
1275 /* low temperature threshold */
1276 int min_temp;
1277 /* high temperature threshold */
1278 int max_temp;
1279 /* was interrupt low to high or high to low */
1280 bool high_to_low;
1281};
1282
d22b7e40
AD		 1283enum radeon_clk_action
1284{
1285 RADEON_SCLK_UP = 1,
1286 RADEON_SCLK_DOWN
1287};
1288
1289struct radeon_blacklist_clocks
1290{
1291 u32 sclk;
1292 u32 mclk;
1293 enum radeon_clk_action action;
1294};
1295
61b7d601
AD		 1296struct radeon_clock_and_voltage_limits {
1297 u32 sclk;
1298 u32 mclk;
cdf6e805
AD		 1299 u16 vddc;
1300 u16 vddci;
61b7d601
AD		 1301};
1302
1303struct radeon_clock_array {
1304 u32 count;
1305 u32 *values;
1306};
1307
1308struct radeon_clock_voltage_dependency_entry {
1309 u32 clk;
1310 u16 v;
1311};
1312
1313struct radeon_clock_voltage_dependency_table {
1314 u32 count;
1315 struct radeon_clock_voltage_dependency_entry *entries;
1316};
1317
ef976ec4
AD		 1318union radeon_cac_leakage_entry {
1319 struct {
1320 u16 vddc;
1321 u32 leakage;
1322 };
1323 struct {
1324 u16 vddc1;
1325 u16 vddc2;
1326 u16 vddc3;
1327 };
61b7d601
AD		 1328};
1329
1330struct radeon_cac_leakage_table {
1331 u32 count;
ef976ec4 1332 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1333};
1334
929ee7a8
AD		 1335struct radeon_phase_shedding_limits_entry {
1336 u16 voltage;
1337 u32 sclk;
1338 u32 mclk;
1339};
1340
1341struct radeon_phase_shedding_limits_table {
1342 u32 count;
1343 struct radeon_phase_shedding_limits_entry *entries;
1344};
1345
84a9d9ee
AD		 1346struct radeon_uvd_clock_voltage_dependency_entry {
1347 u32 vclk;
1348 u32 dclk;
1349 u16 v;
1350};
1351
1352struct radeon_uvd_clock_voltage_dependency_table {
1353 u8 count;
1354 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1355};
1356
d29f013b
AD		 1357struct radeon_vce_clock_voltage_dependency_entry {
1358 u32 ecclk;
1359 u32 evclk;
1360 u16 v;
1361};
1362
1363struct radeon_vce_clock_voltage_dependency_table {
1364 u8 count;
1365 struct radeon_vce_clock_voltage_dependency_entry *entries;
1366};
1367
a5cb318e
AD		 1368struct radeon_ppm_table {
1369 u8 ppm_design;
1370 u16 cpu_core_number;
1371 u32 platform_tdp;
1372 u32 small_ac_platform_tdp;
1373 u32 platform_tdc;
1374 u32 small_ac_platform_tdc;
1375 u32 apu_tdp;
1376 u32 dgpu_tdp;
1377 u32 dgpu_ulv_power;
1378 u32 tj_max;
1379};
1380
58cb7632
AD		 1381struct radeon_cac_tdp_table {
1382 u16 tdp;
1383 u16 configurable_tdp;
1384 u16 tdc;
1385 u16 battery_power_limit;
1386 u16 small_power_limit;
1387 u16 low_cac_leakage;
1388 u16 high_cac_leakage;
1389 u16 maximum_power_delivery_limit;
1390};
1391
61b7d601
AD		 1392struct radeon_dpm_dynamic_state {
1393 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1394 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1395 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1396 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1397 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1398 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1399 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1400 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1401 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1402 struct radeon_clock_array valid_sclk_values;
1403 struct radeon_clock_array valid_mclk_values;
1404 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1405 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1406 u32 mclk_sclk_ratio;
1407 u32 sclk_mclk_delta;
1408 u16 vddc_vddci_delta;
1409 u16 min_vddc_for_pcie_gen2;
1410 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1411 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1412 struct radeon_ppm_table *ppm_table;
58cb7632 1413 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1414};
1415
1416struct radeon_dpm_fan {
1417 u16 t_min;
1418 u16 t_med;
1419 u16 t_high;
1420 u16 pwm_min;
1421 u16 pwm_med;
1422 u16 pwm_high;
1423 u8 t_hyst;
1424 u32 cycle_delay;
1425 u16 t_max;
1426 bool ucode_fan_control;
1427};
1428
32ce4652
AD		 1429enum radeon_pcie_gen {
1430 RADEON_PCIE_GEN1 = 0,
1431 RADEON_PCIE_GEN2 = 1,
1432 RADEON_PCIE_GEN3 = 2,
1433 RADEON_PCIE_GEN_INVALID = 0xffff
1434};
1435
70d01a5e
AD		 1436enum radeon_dpm_forced_level {
1437 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1438 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1439 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1440};
1441
da321c8a
AD		 1442struct radeon_dpm {
1443 struct radeon_ps *ps;
1444 /* number of valid power states */
1445 int num_ps;
1446 /* current power state that is active */
1447 struct radeon_ps *current_ps;
1448 /* requested power state */
1449 struct radeon_ps *requested_ps;
1450 /* boot up power state */
1451 struct radeon_ps *boot_ps;
1452 /* default uvd power state */
1453 struct radeon_ps *uvd_ps;
1454 enum radeon_pm_state_type state;
1455 enum radeon_pm_state_type user_state;
1456 u32 platform_caps;
1457 u32 voltage_response_time;
1458 u32 backbias_response_time;
1459 void *priv;
1460 u32 new_active_crtcs;
1461 int new_active_crtc_count;
1462 u32 current_active_crtcs;
1463 int current_active_crtc_count;
61b7d601
AD		 1464 struct radeon_dpm_dynamic_state dyn_state;
1465 struct radeon_dpm_fan fan;
1466 u32 tdp_limit;
1467 u32 near_tdp_limit;
a9e61410 1468 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1469 u32 sq_ramping_threshold;
1470 u32 cac_leakage;
1471 u16 tdp_od_limit;
1472 u32 tdp_adjustment;
1473 u16 load_line_slope;
1474 bool power_control;
5ca302f7 1475 bool ac_power;
da321c8a
AD		 1476 /* special states active */
1477 bool thermal_active;
8a227555 1478 bool uvd_active;
da321c8a
AD		 1479 /* thermal handling */
1480 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1481 /* forced levels */
1482 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1483 /* track UVD streams */
1484 unsigned sd;
1485 unsigned hd;
da321c8a
AD		 1486};
1487
ce3537d5 1488void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
da321c8a 1489
c93bb85b 1490struct radeon_pm {
c913e23a 1491 struct mutex mutex;
db7fce39
CK		 1492 /* write locked while reprogramming mclk */
1493 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1494 u32 active_crtcs;
1495 int active_crtc_count;
c913e23a 1496 int req_vblank;
839461d3 1497 bool vblank_sync;
c93bb85b
JG		 1498 fixed20_12 max_bandwidth;
1499 fixed20_12 igp_sideport_mclk;
1500 fixed20_12 igp_system_mclk;
1501 fixed20_12 igp_ht_link_clk;
1502 fixed20_12 igp_ht_link_width;
1503 fixed20_12 k8_bandwidth;
1504 fixed20_12 sideport_bandwidth;
1505 fixed20_12 ht_bandwidth;
1506 fixed20_12 core_bandwidth;
1507 fixed20_12 sclk;
f47299c5 1508 fixed20_12 mclk;
c93bb85b 1509 fixed20_12 needed_bandwidth;
0975b162 1510 struct radeon_power_state *power_state;
56278a8e
AD		 1511 /* number of valid power states */
1512 int num_power_states;
a48b9b4e
AD		 1513 int current_power_state_index;
1514 int current_clock_mode_index;
1515 int requested_power_state_index;
1516 int requested_clock_mode_index;
1517 int default_power_state_index;
1518 u32 current_sclk;
1519 u32 current_mclk;
2feea49a
AD		 1520 u16 current_vddc;
1521 u16 current_vddci;
9ace9f7b
AD		 1522 u32 default_sclk;
1523 u32 default_mclk;
2feea49a
AD		 1524 u16 default_vddc;
1525 u16 default_vddci;
29fb52ca 1526 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1527 /* selected pm method */
1528 enum radeon_pm_method pm_method;
1529 /* dynpm power management */
1530 struct delayed_work dynpm_idle_work;
1531 enum radeon_dynpm_state dynpm_state;
1532 enum radeon_dynpm_action dynpm_planned_action;
1533 unsigned long dynpm_action_timeout;
1534 bool dynpm_can_upclock;
1535 bool dynpm_can_downclock;
1536 /* profile-based power management */
1537 enum radeon_pm_profile_type profile;
1538 int profile_index;
1539 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1540 /* internal thermal controller on rv6xx+ */
1541 enum radeon_int_thermal_type int_thermal_type;
1542 struct device *int_hwmon_dev;
da321c8a
AD		 1543 /* dpm */
1544 bool dpm_enabled;
1545 struct radeon_dpm dpm;
c93bb85b
JG		 1546};
1547
a4c9e2ee
AD		 1548int radeon_pm_get_type_index(struct radeon_device *rdev,
1549 enum radeon_pm_state_type ps_type,
1550 int instance);
f2ba57b5
CK		 1551/*
1552 * UVD
1553 */
1554#define RADEON_MAX_UVD_HANDLES 10
1555#define RADEON_UVD_STACK_SIZE (1024*1024)
1556#define RADEON_UVD_HEAP_SIZE (1024*1024)
1557
1558struct radeon_uvd {
1559 struct radeon_bo *vcpu_bo;
1560 void *cpu_addr;
1561 uint64_t gpu_addr;
9cc2e0e9 1562 void *saved_bo;
f2ba57b5
CK		 1563 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1564 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1565 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1566 struct delayed_work idle_work;
f2ba57b5
CK		 1567};
1568
1569int radeon_uvd_init(struct radeon_device *rdev);
1570void radeon_uvd_fini(struct radeon_device *rdev);
1571int radeon_uvd_suspend(struct radeon_device *rdev);
1572int radeon_uvd_resume(struct radeon_device *rdev);
1573int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1574 uint32_t handle, struct radeon_fence **fence);
1575int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1576 uint32_t handle, struct radeon_fence **fence);
1577void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1578void radeon_uvd_free_handles(struct radeon_device *rdev,
1579 struct drm_file *filp);
1580int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1581void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1582int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1583 unsigned vclk, unsigned dclk,
1584 unsigned vco_min, unsigned vco_max,
1585 unsigned fb_factor, unsigned fb_mask,
1586 unsigned pd_min, unsigned pd_max,
1587 unsigned pd_even,
1588 unsigned *optimal_fb_div,
1589 unsigned *optimal_vclk_div,
1590 unsigned *optimal_dclk_div);
1591int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1592 unsigned cg_upll_func_cntl);
771fe6b9 1593
b530602f 1594struct r600_audio_pin {
a92553ab
RM		 1595 int channels;
1596 int rate;
1597 int bits_per_sample;
1598 u8 status_bits;
1599 u8 category_code;
b530602f
AD		 1600 u32 offset;
1601 bool connected;
1602 u32 id;
1603};
1604
1605struct r600_audio {
1606 bool enabled;
1607 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1608 int num_pins;
a92553ab
RM		 1609};
1610
771fe6b9
JG		 1611/*
1612 * Benchmarking
1613 */
638dd7db 1614void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1615
1616
ecc0b326
MD		 1617/*
1618 * Testing
1619 */
1620void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1621void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1622 struct radeon_ring *cpA,
1623 struct radeon_ring *cpB);
60a7e396 1624void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1625
1626
771fe6b9
JG		 1627/*
1628 * Debugfs
1629 */
4d8bf9ae
CK		 1630struct radeon_debugfs {
1631 struct drm_info_list *files;
1632 unsigned num_files;
1633};
1634
771fe6b9
JG		 1635int radeon_debugfs_add_files(struct radeon_device *rdev,
1636 struct drm_info_list *files,
1637 unsigned nfiles);
1638int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1639
76a0df85
CK		 1640/*
1641 * ASIC ring specific functions.
1642 */
1643struct radeon_asic_ring {
1644 /* ring read/write ptr handling */
1645 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1646 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1647 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1648
1649 /* validating and patching of IBs */
1650 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1651 int (*cs_parse)(struct radeon_cs_parser *p);
1652
1653 /* command emmit functions */
1654 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1655 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1654b817 1656 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1657 struct radeon_semaphore *semaphore, bool emit_wait);
1658 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1659
1660 /* testing functions */
1661 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1662 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1663 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1664
1665 /* deprecated */
1666 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1667};
771fe6b9
JG		 1668
1669/*
1670 * ASIC specific functions.
1671 */
1672struct radeon_asic {
068a117c 1673 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1674 void (*fini)(struct radeon_device *rdev);
1675 int (*resume)(struct radeon_device *rdev);
1676 int (*suspend)(struct radeon_device *rdev);
28d52043 1677 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1678 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1679 /* ioctl hw specific callback. Some hw might want to perform special
1680 * operation on specific ioctl. For instance on wait idle some hw
1681 * might want to perform and HDP flush through MMIO as it seems that
1682 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1683 * through ring.
1684 */
1685 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1686 /* check if 3D engine is idle */
1687 bool (*gui_idle)(struct radeon_device *rdev);
1688 /* wait for mc_idle */
1689 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1690 /* get the reference clock */
1691 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1692 /* get the gpu clock counter */
1693 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1694 /* gart */
c5b3b850
AD		 1695 struct {
1696 void (*tlb_flush)(struct radeon_device *rdev);
1697 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1698 } gart;
05b07147
CK		 1699 struct {
1700 int (*init)(struct radeon_device *rdev);
1701 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1702 void (*set_page)(struct radeon_device *rdev,
1703 struct radeon_ib *ib,
1704 uint64_t pe,
dce34bfd
CK		 1705 uint64_t addr, unsigned count,
1706 uint32_t incr, uint32_t flags);
05b07147 1707 } vm;
54e88e06 1708 /* ring specific callbacks */
76a0df85 1709 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1710 /* irqs */
b35ea4ab
AD		 1711 struct {
1712 int (*set)(struct radeon_device *rdev);
1713 int (*process)(struct radeon_device *rdev);
1714 } irq;
54e88e06 1715 /* displays */
c79a49ca
AD		 1716 struct {
1717 /* display watermarks */
1718 void (*bandwidth_update)(struct radeon_device *rdev);
1719 /* get frame count */
1720 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1721 /* wait for vblank */
1722 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1723 /* set backlight level */
1724 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1725 /* get backlight level */
1726 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1727 /* audio callbacks */
1728 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1729 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1730 } display;
54e88e06 1731 /* copy functions for bo handling */
27cd7769
AD		 1732 struct {
1733 int (*blit)(struct radeon_device *rdev,
1734 uint64_t src_offset,
1735 uint64_t dst_offset,
1736 unsigned num_gpu_pages,
876dc9f3 1737 struct radeon_fence **fence);
27cd7769
AD		 1738 u32 blit_ring_index;
1739 int (*dma)(struct radeon_device *rdev,
1740 uint64_t src_offset,
1741 uint64_t dst_offset,
1742 unsigned num_gpu_pages,
876dc9f3 1743 struct radeon_fence **fence);
27cd7769
AD		 1744 u32 dma_ring_index;
1745 /* method used for bo copy */
1746 int (*copy)(struct radeon_device *rdev,
1747 uint64_t src_offset,
1748 uint64_t dst_offset,
1749 unsigned num_gpu_pages,
876dc9f3 1750 struct radeon_fence **fence);
27cd7769
AD		 1751 /* ring used for bo copies */
1752 u32 copy_ring_index;
1753 } copy;
54e88e06 1754 /* surfaces */
9e6f3d02
AD		 1755 struct {
1756 int (*set_reg)(struct radeon_device *rdev, int reg,
1757 uint32_t tiling_flags, uint32_t pitch,
1758 uint32_t offset, uint32_t obj_size);
1759 void (*clear_reg)(struct radeon_device *rdev, int reg);
1760 } surface;
54e88e06 1761 /* hotplug detect */
901ea57d
AD		 1762 struct {
1763 void (*init)(struct radeon_device *rdev);
1764 void (*fini)(struct radeon_device *rdev);
1765 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1766 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1767 } hpd;
da321c8a 1768 /* static power management */
a02fa397
AD		 1769 struct {
1770 void (*misc)(struct radeon_device *rdev);
1771 void (*prepare)(struct radeon_device *rdev);
1772 void (*finish)(struct radeon_device *rdev);
1773 void (*init_profile)(struct radeon_device *rdev);
1774 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1775 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1776 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1777 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1778 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1779 int (*get_pcie_lanes)(struct radeon_device *rdev);
1780 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1781 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1782 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1783 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1784 } pm;
da321c8a
AD		 1785 /* dynamic power management */
1786 struct {
1787 int (*init)(struct radeon_device *rdev);
1788 void (*setup_asic)(struct radeon_device *rdev);
1789 int (*enable)(struct radeon_device *rdev);
914a8987 1790 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1791 void (*disable)(struct radeon_device *rdev);
84dd1928 1792 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1793 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1794 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1795 void (*display_configuration_changed)(struct radeon_device *rdev);
1796 void (*fini)(struct radeon_device *rdev);
1797 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1798 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1799 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1800 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1801 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1802 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1803 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1804 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1805 } dpm;
6f34be50 1806 /* pageflipping */
0f9e006c
AD		 1807 struct {
1808 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1809 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1810 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1811 } pflip;
771fe6b9
JG		 1812};
1813
21f9a437
JG		 1814/*
1815 * Asic structures
1816 */
551ebd83 1817struct r100_asic {
225758d8
JG		 1818 const unsigned *reg_safe_bm;
1819 unsigned reg_safe_bm_size;
1820 u32 hdp_cntl;
551ebd83
DA		 1821};
1822
21f9a437 1823struct r300_asic {
225758d8
JG		 1824 const unsigned *reg_safe_bm;
1825 unsigned reg_safe_bm_size;
1826 u32 resync_scratch;
1827 u32 hdp_cntl;
21f9a437
JG		 1828};
1829
1830struct r600_asic {
225758d8
JG		 1831 unsigned max_pipes;
1832 unsigned max_tile_pipes;
1833 unsigned max_simds;
1834 unsigned max_backends;
1835 unsigned max_gprs;
1836 unsigned max_threads;
1837 unsigned max_stack_entries;
1838 unsigned max_hw_contexts;
1839 unsigned max_gs_threads;
1840 unsigned sx_max_export_size;
1841 unsigned sx_max_export_pos_size;
1842 unsigned sx_max_export_smx_size;
1843 unsigned sq_num_cf_insts;
1844 unsigned tiling_nbanks;
1845 unsigned tiling_npipes;
1846 unsigned tiling_group_size;
e7aeeba6 1847 unsigned tile_config;
e55b9422 1848 unsigned backend_map;
21f9a437
JG		 1849};
1850
1851struct rv770_asic {
225758d8
JG		 1852 unsigned max_pipes;
1853 unsigned max_tile_pipes;
1854 unsigned max_simds;
1855 unsigned max_backends;
1856 unsigned max_gprs;
1857 unsigned max_threads;
1858 unsigned max_stack_entries;
1859 unsigned max_hw_contexts;
1860 unsigned max_gs_threads;
1861 unsigned sx_max_export_size;
1862 unsigned sx_max_export_pos_size;
1863 unsigned sx_max_export_smx_size;
1864 unsigned sq_num_cf_insts;
1865 unsigned sx_num_of_sets;
1866 unsigned sc_prim_fifo_size;
1867 unsigned sc_hiz_tile_fifo_size;
1868 unsigned sc_earlyz_tile_fifo_fize;
1869 unsigned tiling_nbanks;
1870 unsigned tiling_npipes;
1871 unsigned tiling_group_size;
e7aeeba6 1872 unsigned tile_config;
e55b9422 1873 unsigned backend_map;
21f9a437
JG		 1874};
1875
32fcdbf4
AD		 1876struct evergreen_asic {
1877 unsigned num_ses;
1878 unsigned max_pipes;
1879 unsigned max_tile_pipes;
1880 unsigned max_simds;
1881 unsigned max_backends;
1882 unsigned max_gprs;
1883 unsigned max_threads;
1884 unsigned max_stack_entries;
1885 unsigned max_hw_contexts;
1886 unsigned max_gs_threads;
1887 unsigned sx_max_export_size;
1888 unsigned sx_max_export_pos_size;
1889 unsigned sx_max_export_smx_size;
1890 unsigned sq_num_cf_insts;
1891 unsigned sx_num_of_sets;
1892 unsigned sc_prim_fifo_size;
1893 unsigned sc_hiz_tile_fifo_size;
1894 unsigned sc_earlyz_tile_fifo_size;
1895 unsigned tiling_nbanks;
1896 unsigned tiling_npipes;
1897 unsigned tiling_group_size;
e7aeeba6 1898 unsigned tile_config;
e55b9422 1899 unsigned backend_map;
32fcdbf4
AD		 1900};
1901
fecf1d07
AD		 1902struct cayman_asic {
1903 unsigned max_shader_engines;
1904 unsigned max_pipes_per_simd;
1905 unsigned max_tile_pipes;
1906 unsigned max_simds_per_se;
1907 unsigned max_backends_per_se;
1908 unsigned max_texture_channel_caches;
1909 unsigned max_gprs;
1910 unsigned max_threads;
1911 unsigned max_gs_threads;
1912 unsigned max_stack_entries;
1913 unsigned sx_num_of_sets;
1914 unsigned sx_max_export_size;
1915 unsigned sx_max_export_pos_size;
1916 unsigned sx_max_export_smx_size;
1917 unsigned max_hw_contexts;
1918 unsigned sq_num_cf_insts;
1919 unsigned sc_prim_fifo_size;
1920 unsigned sc_hiz_tile_fifo_size;
1921 unsigned sc_earlyz_tile_fifo_size;
1922
1923 unsigned num_shader_engines;
1924 unsigned num_shader_pipes_per_simd;
1925 unsigned num_tile_pipes;
1926 unsigned num_simds_per_se;
1927 unsigned num_backends_per_se;
1928 unsigned backend_disable_mask_per_asic;
1929 unsigned backend_map;
1930 unsigned num_texture_channel_caches;
1931 unsigned mem_max_burst_length_bytes;
1932 unsigned mem_row_size_in_kb;
1933 unsigned shader_engine_tile_size;
1934 unsigned num_gpus;
1935 unsigned multi_gpu_tile_size;
1936
1937 unsigned tile_config;
fecf1d07
AD		 1938};
1939
0a96d72b
AD		 1940struct si_asic {
1941 unsigned max_shader_engines;
0a96d72b 1942 unsigned max_tile_pipes;
1a8ca750
AD		 1943 unsigned max_cu_per_sh;
1944 unsigned max_sh_per_se;
0a96d72b
AD		 1945 unsigned max_backends_per_se;
1946 unsigned max_texture_channel_caches;
1947 unsigned max_gprs;
1948 unsigned max_gs_threads;
1949 unsigned max_hw_contexts;
1950 unsigned sc_prim_fifo_size_frontend;
1951 unsigned sc_prim_fifo_size_backend;
1952 unsigned sc_hiz_tile_fifo_size;
1953 unsigned sc_earlyz_tile_fifo_size;
1954
0a96d72b 1955 unsigned num_tile_pipes;
439a1cff 1956 unsigned backend_enable_mask;
0a96d72b
AD		 1957 unsigned backend_disable_mask_per_asic;
1958 unsigned backend_map;
1959 unsigned num_texture_channel_caches;
1960 unsigned mem_max_burst_length_bytes;
1961 unsigned mem_row_size_in_kb;
1962 unsigned shader_engine_tile_size;
1963 unsigned num_gpus;
1964 unsigned multi_gpu_tile_size;
1965
1966 unsigned tile_config;
64d7b8be 1967 uint32_t tile_mode_array[32];
0a96d72b
AD		 1968};
1969
8cc1a532
AD		 1970struct cik_asic {
1971 unsigned max_shader_engines;
1972 unsigned max_tile_pipes;
1973 unsigned max_cu_per_sh;
1974 unsigned max_sh_per_se;
1975 unsigned max_backends_per_se;
1976 unsigned max_texture_channel_caches;
1977 unsigned max_gprs;
1978 unsigned max_gs_threads;
1979 unsigned max_hw_contexts;
1980 unsigned sc_prim_fifo_size_frontend;
1981 unsigned sc_prim_fifo_size_backend;
1982 unsigned sc_hiz_tile_fifo_size;
1983 unsigned sc_earlyz_tile_fifo_size;
1984
1985 unsigned num_tile_pipes;
439a1cff 1986 unsigned backend_enable_mask;
8cc1a532
AD		 1987 unsigned backend_disable_mask_per_asic;
1988 unsigned backend_map;
1989 unsigned num_texture_channel_caches;
1990 unsigned mem_max_burst_length_bytes;
1991 unsigned mem_row_size_in_kb;
1992 unsigned shader_engine_tile_size;
1993 unsigned num_gpus;
1994 unsigned multi_gpu_tile_size;
1995
1996 unsigned tile_config;
39aee490 1997 uint32_t tile_mode_array[32];
32f79a8a 1998 uint32_t macrotile_mode_array[16];
8cc1a532
AD		 1999};
2000
068a117c
JG		 2001union radeon_asic_config {
2002 struct r300_asic r300;
551ebd83 2003 struct r100_asic r100;
3ce0a23d
JG		 2004 struct r600_asic r600;
2005 struct rv770_asic rv770;
32fcdbf4 2006 struct evergreen_asic evergreen;
fecf1d07 2007 struct cayman_asic cayman;
0a96d72b 2008 struct si_asic si;
8cc1a532 2009 struct cik_asic cik;
068a117c
JG		 2010};
2011
0a10c851
DV		 2012/*
2013 * asic initizalization from radeon_asic.c
2014 */
2015void radeon_agp_disable(struct radeon_device *rdev);
2016int radeon_asic_init(struct radeon_device *rdev);
2017
771fe6b9
JG		 2018
2019/*
2020 * IOCTL.
2021 */
2022int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2023 struct drm_file *filp);
2024int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2025 struct drm_file *filp);
2026int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2027 struct drm_file *file_priv);
2028int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2029 struct drm_file *file_priv);
2030int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2031 struct drm_file *file_priv);
2032int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2033 struct drm_file *file_priv);
2034int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2035 struct drm_file *filp);
2036int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2037 struct drm_file *filp);
2038int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2039 struct drm_file *filp);
2040int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2041 struct drm_file *filp);
721604a1
JG		 2042int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2043 struct drm_file *filp);
771fe6b9 2044int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2045int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2046 struct drm_file *filp);
2047int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2048 struct drm_file *filp);
771fe6b9 2049
16cdf04d
AD		 2050/* VRAM scratch page for HDP bug, default vram page */
2051struct r600_vram_scratch {
87cbf8f2
AD		 2052 struct radeon_bo *robj;
2053 volatile uint32_t *ptr;
16cdf04d 2054 u64 gpu_addr;
87cbf8f2 2055};
771fe6b9 2056
fd64ca8a
LT		 2057/*
2058 * ACPI
2059 */
2060struct radeon_atif_notification_cfg {
2061 bool enabled;
2062 int command_code;
2063};
2064
2065struct radeon_atif_notifications {
2066 bool display_switch;
2067 bool expansion_mode_change;
2068 bool thermal_state;
2069 bool forced_power_state;
2070 bool system_power_state;
2071 bool display_conf_change;
2072 bool px_gfx_switch;
2073 bool brightness_change;
2074 bool dgpu_display_event;
2075};
2076
2077struct radeon_atif_functions {
2078 bool system_params;
2079 bool sbios_requests;
2080 bool select_active_disp;
2081 bool lid_state;
2082 bool get_tv_standard;
2083 bool set_tv_standard;
2084 bool get_panel_expansion_mode;
2085 bool set_panel_expansion_mode;
2086 bool temperature_change;
2087 bool graphics_device_types;
2088};
2089
2090struct radeon_atif {
2091 struct radeon_atif_notifications notifications;
2092 struct radeon_atif_functions functions;
2093 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2094 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2095};
7a1619b9 2096
e3a15920
AD		 2097struct radeon_atcs_functions {
2098 bool get_ext_state;
2099 bool pcie_perf_req;
2100 bool pcie_dev_rdy;
2101 bool pcie_bus_width;
2102};
2103
2104struct radeon_atcs {
2105 struct radeon_atcs_functions functions;
2106};
2107
771fe6b9
JG		 2108/*
2109 * Core structure, functions and helpers.
2110 */
2111typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2112typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2113
2114struct radeon_device {
9f022ddf 2115 struct device *dev;
771fe6b9
JG		 2116 struct drm_device *ddev;
2117 struct pci_dev *pdev;
dee53e7f 2118 struct rw_semaphore exclusive_lock;
771fe6b9 2119 /* ASIC */
068a117c 2120 union radeon_asic_config config;
771fe6b9
JG		 2121 enum radeon_family family;
2122 unsigned long flags;
2123 int usec_timeout;
2124 enum radeon_pll_errata pll_errata;
2125 int num_gb_pipes;
f779b3e5 2126 int num_z_pipes;
771fe6b9
JG		 2127 int disp_priority;
2128 /* BIOS */
2129 uint8_t *bios;
2130 bool is_atom_bios;
2131 uint16_t bios_header_start;
4c788679 2132 struct radeon_bo *stollen_vga_memory;
771fe6b9 2133 /* Register mmio */
4c9bc75c
DA		 2134 resource_size_t rmmio_base;
2135 resource_size_t rmmio_size;
2c385151
DV		 2136 /* protects concurrent MM_INDEX/DATA based register access */
2137 spinlock_t mmio_idx_lock;
fe78118c
AD		 2138 /* protects concurrent SMC based register access */
2139 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2140 /* protects concurrent PLL register access */
2141 spinlock_t pll_idx_lock;
2142 /* protects concurrent MC register access */
2143 spinlock_t mc_idx_lock;
2144 /* protects concurrent PCIE register access */
2145 spinlock_t pcie_idx_lock;
2146 /* protects concurrent PCIE_PORT register access */
2147 spinlock_t pciep_idx_lock;
2148 /* protects concurrent PIF register access */
2149 spinlock_t pif_idx_lock;
2150 /* protects concurrent CG register access */
2151 spinlock_t cg_idx_lock;
2152 /* protects concurrent UVD register access */
2153 spinlock_t uvd_idx_lock;
2154 /* protects concurrent RCU register access */
2155 spinlock_t rcu_idx_lock;
2156 /* protects concurrent DIDT register access */
2157 spinlock_t didt_idx_lock;
2158 /* protects concurrent ENDPOINT (audio) register access */
2159 spinlock_t end_idx_lock;
a0533fbf 2160 void __iomem *rmmio;
771fe6b9
JG		 2161 radeon_rreg_t mc_rreg;
2162 radeon_wreg_t mc_wreg;
2163 radeon_rreg_t pll_rreg;
2164 radeon_wreg_t pll_wreg;
de1b2898 2165 uint32_t pcie_reg_mask;
771fe6b9
JG		 2166 radeon_rreg_t pciep_rreg;
2167 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2168 /* io port */
2169 void __iomem *rio_mem;
2170 resource_size_t rio_mem_size;
771fe6b9
JG		 2171 struct radeon_clock clock;
2172 struct radeon_mc mc;
2173 struct radeon_gart gart;
2174 struct radeon_mode_info mode_info;
2175 struct radeon_scratch scratch;
75efdee1 2176 struct radeon_doorbell doorbell;
771fe6b9 2177 struct radeon_mman mman;
7465280c 2178 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2179 wait_queue_head_t fence_queue;
d6999bc7 2180 struct mutex ring_lock;
e32eb50d 2181 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2182 bool ib_pool_ready;
2183 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2184 struct radeon_irq irq;
2185 struct radeon_asic *asic;
2186 struct radeon_gem gem;
c93bb85b 2187 struct radeon_pm pm;
f2ba57b5 2188 struct radeon_uvd uvd;
f657c2a7 2189 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2190 struct radeon_wb wb;
3ce0a23d 2191 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2192 bool shutdown;
2193 bool suspend;
ad49f501 2194 bool need_dma32;
733289c2 2195 bool accel_working;
a0a53aa8 2196 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2197 bool needs_reset;
e024e110 2198 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2199 const struct firmware *me_fw; /* all family ME firmware */
2200 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2201 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2202 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2203 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2204 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2205 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2206 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2207 const struct firmware *uvd_fw; /* UVD firmware */
16cdf04d 2208 struct r600_vram_scratch vram_scratch;
3e5cb98d 2209 int msi_enabled; /* msi enabled */
d8f60cfc 2210 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2211 struct radeon_rlc rlc;
963e81f9 2212 struct radeon_mec mec;
d4877cf2 2213 struct work_struct hotplug_work;
f122c610 2214 struct work_struct audio_work;
8f61b34c 2215 struct work_struct reset_work;
18917b60 2216 int num_crtc; /* number of crtcs */
40bacf16 2217 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2218 bool has_uvd;
b530602f 2219 struct r600_audio audio; /* audio stuff */
ce8f5370 2220 struct notifier_block acpi_nb;
9eba4a93 2221 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2222 struct drm_file *hyperz_filp;
9eba4a93 2223 struct drm_file *cmask_filp;
f376b94f
AD		 2224 /* i2c buses */
2225 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2226 /* debugfs */
2227 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2228 unsigned debugfs_count;
721604a1
JG		 2229 /* virtual memory */
2230 struct radeon_vm_manager vm_manager;
6759a0a7 2231 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2232 /* ACPI interface */
2233 struct radeon_atif atif;
e3a15920 2234 struct radeon_atcs atcs;
f61d5b46
AD		 2235 /* srbm instance registers */
2236 struct mutex srbm_mutex;
64d8a728
AD		 2237 /* clock, powergating flags */
2238 u32 cg_flags;
2239 u32 pg_flags;
10ebc0bc
DA		 2240
2241 struct dev_pm_domain vga_pm_domain;
2242 bool have_disp_power_ref;
771fe6b9
JG		 2243};
2244
2245int radeon_device_init(struct radeon_device *rdev,
2246 struct drm_device *ddev,
2247 struct pci_dev *pdev,
2248 uint32_t flags);
2249void radeon_device_fini(struct radeon_device *rdev);
2250int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2251
2ef9bdfe
DV		 2252uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2253 bool always_indirect);
2254void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2255 bool always_indirect);
6fcbef7a
AK		 2256u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2257void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2258
d5754ab8
AL		 2259u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2260void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2261
4c788679
JG		 2262/*
2263 * Cast helper
2264 */
2265#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2266
2267/*
2268 * Registers read & write functions.
2269 */
a0533fbf
BH		 2270#define RREG8(reg) readb((rdev->rmmio) + (reg))
2271#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2272#define RREG16(reg) readw((rdev->rmmio) + (reg))
2273#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2274#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2275#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2276#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2277#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2278#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2279#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2280#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2281#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2282#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2283#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2284#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2285#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2286#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2287#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2288#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2289#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2290#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2291#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2292#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2293#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2294#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2295#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2296#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2297#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2298#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2299#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2300#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2301#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2302#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2303#define WREG32_P(reg, val, mask) \
2304 do { \
2305 uint32_t tmp_ = RREG32(reg); \
2306 tmp_ &= (mask); \
2307 tmp_ |= ((val) & ~(mask)); \
2308 WREG32(reg, tmp_); \
2309 } while (0)
d5169fc4 2310#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2311#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2312#define WREG32_PLL_P(reg, val, mask) \
2313 do { \
2314 uint32_t tmp_ = RREG32_PLL(reg); \
2315 tmp_ &= (mask); \
2316 tmp_ |= ((val) & ~(mask)); \
2317 WREG32_PLL(reg, tmp_); \
2318 } while (0)
2ef9bdfe 2319#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2320#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2321#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2322
d5754ab8
AL		 2323#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2324#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2325
de1b2898
DA		 2326/*
2327 * Indirect registers accessor
2328 */
2329static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2330{
0a5b7b0b 2331 unsigned long flags;
de1b2898
DA		 2332 uint32_t r;
2333
0a5b7b0b 2334 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2335 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2336 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2337 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2338 return r;
2339}
2340
2341static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2342{
0a5b7b0b
AD		 2343 unsigned long flags;
2344
2345 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2346 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2347 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2348 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2349}
2350
1d5d0c34
AD		 2351static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2352{
fe78118c 2353 unsigned long flags;
1d5d0c34
AD		 2354 u32 r;
2355
fe78118c 2356 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2357 WREG32(TN_SMC_IND_INDEX_0, (reg));
2358 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2359 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2360 return r;
2361}
2362
2363static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2364{
fe78118c
AD		 2365 unsigned long flags;
2366
2367 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2368 WREG32(TN_SMC_IND_INDEX_0, (reg));
2369 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2370 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2371}
2372
ff82bbc4
AD		 2373static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2374{
0a5b7b0b 2375 unsigned long flags;
ff82bbc4
AD		 2376 u32 r;
2377
0a5b7b0b 2378 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2379 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2380 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2381 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2382 return r;
2383}
2384
2385static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2386{
0a5b7b0b
AD		 2387 unsigned long flags;
2388
2389 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2390 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2391 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2392 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2393}
2394
46f9564a
AD		 2395static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2396{
0a5b7b0b 2397 unsigned long flags;
46f9564a
AD		 2398 u32 r;
2399
0a5b7b0b 2400 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2401 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2402 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2403 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2404 return r;
2405}
2406
2407static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2408{
0a5b7b0b
AD		 2409 unsigned long flags;
2410
2411 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2412 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2413 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2414 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2415}
2416
792edd69
AD		 2417static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2418{
0a5b7b0b 2419 unsigned long flags;
792edd69
AD		 2420 u32 r;
2421
0a5b7b0b 2422 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2423 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2424 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2425 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2426 return r;
2427}
2428
2429static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2430{
0a5b7b0b
AD		 2431 unsigned long flags;
2432
2433 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2434 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2435 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2436 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2437}
2438
2439static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2440{
0a5b7b0b 2441 unsigned long flags;
792edd69
AD		 2442 u32 r;
2443
0a5b7b0b 2444 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2445 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2446 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2447 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2448 return r;
2449}
2450
2451static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2452{
0a5b7b0b
AD		 2453 unsigned long flags;
2454
2455 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2456 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2457 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2458 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2459}
2460
93656cdd
AD		 2461static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2462{
0a5b7b0b 2463 unsigned long flags;
93656cdd
AD		 2464 u32 r;
2465
0a5b7b0b 2466 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2467 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2468 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2469 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2470 return r;
2471}
2472
2473static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2474{
0a5b7b0b
AD		 2475 unsigned long flags;
2476
2477 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2478 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2479 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2480 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2481}
2482
1d58234d
AD		 2483
2484static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2485{
0a5b7b0b 2486 unsigned long flags;
1d58234d
AD		 2487 u32 r;
2488
0a5b7b0b 2489 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2490 WREG32(CIK_DIDT_IND_INDEX, (reg));
2491 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2492 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2493 return r;
2494}
2495
2496static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2497{
0a5b7b0b
AD		 2498 unsigned long flags;
2499
2500 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2501 WREG32(CIK_DIDT_IND_INDEX, (reg));
2502 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2503 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2504}
2505
771fe6b9
JG		 2506void r100_pll_errata_after_index(struct radeon_device *rdev);
2507
2508
2509/*
2510 * ASICs helpers.
2511 */
b995e433
DA		 2512#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2513 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2514#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2515 (rdev->family == CHIP_RV200) || \
2516 (rdev->family == CHIP_RS100) || \
2517 (rdev->family == CHIP_RS200) || \
2518 (rdev->family == CHIP_RV250) || \
2519 (rdev->family == CHIP_RV280) || \
2520 (rdev->family == CHIP_RS300))
2521#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2522 (rdev->family == CHIP_RV350) || \
2523 (rdev->family == CHIP_R350) || \
2524 (rdev->family == CHIP_RV380) || \
2525 (rdev->family == CHIP_R420) || \
2526 (rdev->family == CHIP_R423) || \
2527 (rdev->family == CHIP_RV410) || \
2528 (rdev->family == CHIP_RS400) || \
2529 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2530#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2531 (rdev->ddev->pdev->device == 0x9443) || \
2532 (rdev->ddev->pdev->device == 0x944B) || \
2533 (rdev->ddev->pdev->device == 0x9506) || \
2534 (rdev->ddev->pdev->device == 0x9509) || \
2535 (rdev->ddev->pdev->device == 0x950F) || \
2536 (rdev->ddev->pdev->device == 0x689C) || \
2537 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2538#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2539#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2540 (rdev->family == CHIP_RS690) || \
2541 (rdev->family == CHIP_RS740) || \
2542 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2543#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2544#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2545#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2546#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2547 (rdev->flags & RADEON_IS_IGP))
1fe18305 2548#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2549#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2550#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2551 (rdev->flags & RADEON_IS_IGP))
624d3524 2552#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2553#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2554#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2555
dc50ba7f
AD		 2556#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2557 (rdev->ddev->pdev->device == 0x6850) || \
2558 (rdev->ddev->pdev->device == 0x6858) || \
2559 (rdev->ddev->pdev->device == 0x6859) || \
2560 (rdev->ddev->pdev->device == 0x6840) || \
2561 (rdev->ddev->pdev->device == 0x6841) || \
2562 (rdev->ddev->pdev->device == 0x6842) || \
2563 (rdev->ddev->pdev->device == 0x6843))
2564
771fe6b9
JG		 2565/*
2566 * BIOS helpers.
2567 */
2568#define RBIOS8(i) (rdev->bios[i])
2569#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2570#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2571
2572int radeon_combios_init(struct radeon_device *rdev);
2573void radeon_combios_fini(struct radeon_device *rdev);
2574int radeon_atombios_init(struct radeon_device *rdev);
2575void radeon_atombios_fini(struct radeon_device *rdev);
2576
2577
2578/*
2579 * RING helpers.
2580 */
ce580fab 2581#if DRM_DEBUG_CODE == 0
e32eb50d 2582static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2583{
e32eb50d
CK		 2584 ring->ring[ring->wptr++] = v;
2585 ring->wptr &= ring->ptr_mask;
2586 ring->count_dw--;
2587 ring->ring_free_dw--;
771fe6b9 2588}
ce580fab
AK		 2589#else
2590/* With debugging this is just too big to inline */
e32eb50d 2591void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2592#endif
771fe6b9
JG		 2593
2594/*
2595 * ASICs macro.
2596 */
068a117c 2597#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2598#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2599#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2600#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2601#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2602#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2603#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2604#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2605#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2606#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2607#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2608#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2609#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2610#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2611#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2612#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2613#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2614#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2615#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2616#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2617#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2618#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2619#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2620#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2621#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2622#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2623#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2624#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2625#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2626#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2627#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2628#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2629#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2630#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2631#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2632#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2633#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2634#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2635#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2636#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2637#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2638#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2639#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2640#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2641#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2642#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2643#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2644#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2645#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2646#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2647#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2648#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2649#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2650#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2651#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2652#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2653#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2654#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2655#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2656#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2657#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2658#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2659#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2660#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2661#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2662#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2663#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2664#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2665#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2666#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2667#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2668#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2669#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2670#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2671#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2672#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2673#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2674#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2675#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2676#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2677#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2678#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2679#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2680#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2681
6cf8a3f5 2682/* Common functions */
700a0cc0 2683/* AGP */
90aca4d2 2684extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2685extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2686extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2687extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2688extern int radeon_modeset_init(struct radeon_device *rdev);
2689extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2690extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2691extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2692extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2693extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2694extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2695extern void radeon_wb_fini(struct radeon_device *rdev);
2696extern int radeon_wb_init(struct radeon_device *rdev);
2697extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2698extern void radeon_surface_init(struct radeon_device *rdev);
2699extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2700extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2701extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2702extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2703extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2704extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2705extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2706extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2707extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2708extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2709extern void radeon_program_register_sequence(struct radeon_device *rdev,
2710 const u32 *registers,
2711 const u32 array_size);
6cf8a3f5 2712
721604a1
JG		 2713/*
2714 * vm
2715 */
2716int radeon_vm_manager_init(struct radeon_device *rdev);
2717void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2718void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2719void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2720int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2721void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2722struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2723 struct radeon_vm *vm, int ring);
2724void radeon_vm_fence(struct radeon_device *rdev,
2725 struct radeon_vm *vm,
2726 struct radeon_fence *fence);
dce34bfd 2727uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
9c57a6bd
CK		 2728int radeon_vm_bo_update(struct radeon_device *rdev,
2729 struct radeon_vm *vm,
2730 struct radeon_bo *bo,
2731 struct ttm_mem_reg *mem);
721604a1
JG		 2732void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2733 struct radeon_bo *bo);
421ca7ab
CK		 2734struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2735 struct radeon_bo *bo);
e971bd5e
CK		 2736struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2737 struct radeon_vm *vm,
2738 struct radeon_bo *bo);
2739int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2740 struct radeon_bo_va *bo_va,
2741 uint64_t offset,
2742 uint32_t flags);
721604a1 2743int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2744 struct radeon_bo_va *bo_va);
721604a1 2745
f122c610
AD		 2746/* audio */
2747void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2748struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2749struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
721604a1 2750
16cdf04d
AD		 2751/*
2752 * R600 vram scratch functions
2753 */
2754int r600_vram_scratch_init(struct radeon_device *rdev);
2755void r600_vram_scratch_fini(struct radeon_device *rdev);
2756
285484e2
JG		 2757/*
2758 * r600 cs checking helper
2759 */
2760unsigned r600_mip_minify(unsigned size, unsigned level);
2761bool r600_fmt_is_valid_color(u32 format);
2762bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2763int r600_fmt_get_blocksize(u32 format);
2764int r600_fmt_get_nblocksx(u32 format, u32 w);
2765int r600_fmt_get_nblocksy(u32 format, u32 h);
2766
3574dda4
DV		 2767/*
2768 * r600 functions used by radeon_encoder.c
2769 */
1b688d08
RM		 2770struct radeon_hdmi_acr {
2771 u32 clock;
2772
2773 int n_32khz;
2774 int cts_32khz;
2775
2776 int n_44_1khz;
2777 int cts_44_1khz;
2778
2779 int n_48khz;
2780 int cts_48khz;
2781
2782};
2783
e55d3e6c
RM		 2784extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2785
416a2bd2
AD		 2786extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2787 u32 tiling_pipe_num,
2788 u32 max_rb_num,
2789 u32 total_max_rb_num,
2790 u32 enabled_rb_mask);
fe251e2f 2791
e55d3e6c
RM		 2792/*
2793 * evergreen functions used by radeon_encoder.c
2794 */
2795
0af62b01 2796extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2797extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2798
c4917074
AD		 2799/* radeon_acpi.c */
2800#if defined(CONFIG_ACPI)
2801extern int radeon_acpi_init(struct radeon_device *rdev);
2802extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2803extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2804extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2805 u8 perf_req, bool advertise);
dc50ba7f 2806extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2807#else
2808static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2809static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2810#endif
d7a2952f 2811
c38f34b5
IH		 2812int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2813 struct radeon_cs_packet *pkt,
2814 unsigned idx);
9ffb7a6d 2815bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2816void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2817 struct radeon_cs_packet *pkt);
e9716993
IH		 2818int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2819 struct radeon_cs_reloc **cs_reloc,
2820 int nomm);
40592a17
IH		 2821int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2822 uint32_t *vline_start_end,
2823 uint32_t *vline_status);
c38f34b5 2824
4c788679
JG		 2825#include "radeon_object.h"
2826
771fe6b9 2827#endif
Linux 6.x block layer and io_uring tree(s)