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drm/radeon/kms: add cvt mode if we only have lvds w/h and no edid (v4)
[linux-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
771fe6b9
JG		 63#include <asm/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72
c2142715 73#include "radeon_family.h"
771fe6b9
JG		 74#include "radeon_mode.h"
75#include "radeon_reg.h"
771fe6b9
JG		 76
77/*
78 * Modules parameters.
79 */
80extern int radeon_no_wb;
81extern int radeon_modeset;
82extern int radeon_dynclks;
83extern int radeon_r4xx_atom;
84extern int radeon_agpmode;
85extern int radeon_vram_limit;
86extern int radeon_gart_size;
87extern int radeon_benchmarking;
ecc0b326 88extern int radeon_testing;
771fe6b9 89extern int radeon_connector_table;
4ce001ab 90extern int radeon_tv;
b27b6375 91extern int radeon_new_pll;
dafc3bd5 92extern int radeon_audio;
771fe6b9
JG		 93
94/*
95 * Copy from radeon_drv.h so we don't have to include both and have conflicting
96 * symbol;
97 */
98#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
99#define RADEON_IB_POOL_SIZE 16
100#define RADEON_DEBUGFS_MAX_NUM_FILES 32
101#define RADEONFB_CONN_LIMIT 4
f657c2a7 102#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 103
771fe6b9
JG		 104/*
105 * Errata workarounds.
106 */
107enum radeon_pll_errata {
108 CHIP_ERRATA_R300_CG = 0x00000001,
109 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
110 CHIP_ERRATA_PLL_DELAY = 0x00000004
111};
112
113
114struct radeon_device;
115
116
117/*
118 * BIOS.
119 */
120bool radeon_get_bios(struct radeon_device *rdev);
121
3ce0a23d 122
771fe6b9 123/*
3ce0a23d 124 * Dummy page
771fe6b9 125 */
3ce0a23d
JG		 126struct radeon_dummy_page {
127 struct page *page;
128 dma_addr_t addr;
129};
130int radeon_dummy_page_init(struct radeon_device *rdev);
131void radeon_dummy_page_fini(struct radeon_device *rdev);
132
771fe6b9 133
3ce0a23d
JG		 134/*
135 * Clocks
136 */
771fe6b9
JG		 137struct radeon_clock {
138 struct radeon_pll p1pll;
139 struct radeon_pll p2pll;
140 struct radeon_pll spll;
141 struct radeon_pll mpll;
142 /* 10 Khz units */
143 uint32_t default_mclk;
144 uint32_t default_sclk;
145};
146
7433874e
RM		 147/*
148 * Power management
149 */
150int radeon_pm_init(struct radeon_device *rdev);
3ce0a23d 151
771fe6b9
JG		 152/*
153 * Fences.
154 */
155struct radeon_fence_driver {
156 uint32_t scratch_reg;
157 atomic_t seq;
158 uint32_t last_seq;
159 unsigned long count_timeout;
160 wait_queue_head_t queue;
161 rwlock_t lock;
162 struct list_head created;
163 struct list_head emited;
164 struct list_head signaled;
165};
166
167struct radeon_fence {
168 struct radeon_device *rdev;
169 struct kref kref;
170 struct list_head list;
171 /* protected by radeon_fence.lock */
172 uint32_t seq;
173 unsigned long timeout;
174 bool emited;
175 bool signaled;
176};
177
178int radeon_fence_driver_init(struct radeon_device *rdev);
179void radeon_fence_driver_fini(struct radeon_device *rdev);
180int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
181int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
182void radeon_fence_process(struct radeon_device *rdev);
183bool radeon_fence_signaled(struct radeon_fence *fence);
184int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
185int radeon_fence_wait_next(struct radeon_device *rdev);
186int radeon_fence_wait_last(struct radeon_device *rdev);
187struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
188void radeon_fence_unref(struct radeon_fence **fence);
189
e024e110
DA		 190/*
191 * Tiling registers
192 */
193struct radeon_surface_reg {
4c788679 194 struct radeon_bo *bo;
e024e110
DA		 195};
196
197#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 198
199/*
4c788679 200 * TTM.
771fe6b9 201 */
4c788679
JG		 202struct radeon_mman {
203 struct ttm_bo_global_ref bo_global_ref;
204 struct ttm_global_reference mem_global_ref;
205 bool mem_global_referenced;
206 struct ttm_bo_device bdev;
207};
208
209struct radeon_bo {
210 /* Protected by gem.mutex */
211 struct list_head list;
212 /* Protected by tbo.reserved */
312ea8da
JG		 213 u32 placements[3];
214 struct ttm_placement placement;
4c788679
JG		 215 struct ttm_buffer_object tbo;
216 struct ttm_bo_kmap_obj kmap;
217 unsigned pin_count;
218 void *kptr;
219 u32 tiling_flags;
220 u32 pitch;
221 int surface_reg;
222 /* Constant after initialization */
223 struct radeon_device *rdev;
224 struct drm_gem_object *gobj;
225};
771fe6b9 226
4c788679 227struct radeon_bo_list {
771fe6b9 228 struct list_head list;
4c788679 229 struct radeon_bo *bo;
771fe6b9
JG		 230 uint64_t gpu_offset;
231 unsigned rdomain;
232 unsigned wdomain;
4c788679 233 u32 tiling_flags;
771fe6b9
JG		 234};
235
771fe6b9
JG		 236/*
237 * GEM objects.
238 */
239struct radeon_gem {
4c788679 240 struct mutex mutex;
771fe6b9
JG		 241 struct list_head objects;
242};
243
244int radeon_gem_init(struct radeon_device *rdev);
245void radeon_gem_fini(struct radeon_device *rdev);
246int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 247 int alignment, int initial_domain,
248 bool discardable, bool kernel,
249 struct drm_gem_object **obj);
771fe6b9
JG		 250int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
251 uint64_t *gpu_addr);
252void radeon_gem_object_unpin(struct drm_gem_object *obj);
253
254
255/*
256 * GART structures, functions & helpers
257 */
258struct radeon_mc;
259
260struct radeon_gart_table_ram {
261 volatile uint32_t *ptr;
262};
263
264struct radeon_gart_table_vram {
4c788679 265 struct radeon_bo *robj;
771fe6b9
JG		 266 volatile uint32_t *ptr;
267};
268
269union radeon_gart_table {
270 struct radeon_gart_table_ram ram;
271 struct radeon_gart_table_vram vram;
272};
273
a77f1718
MT		 274#define RADEON_GPU_PAGE_SIZE 4096
275
771fe6b9
JG		 276struct radeon_gart {
277 dma_addr_t table_addr;
278 unsigned num_gpu_pages;
279 unsigned num_cpu_pages;
280 unsigned table_size;
281 union radeon_gart_table table;
282 struct page **pages;
283 dma_addr_t *pages_addr;
284 bool ready;
285};
286
287int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
288void radeon_gart_table_ram_free(struct radeon_device *rdev);
289int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
290void radeon_gart_table_vram_free(struct radeon_device *rdev);
291int radeon_gart_init(struct radeon_device *rdev);
292void radeon_gart_fini(struct radeon_device *rdev);
293void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
294 int pages);
295int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
296 int pages, struct page **pagelist);
297
298
299/*
300 * GPU MC structures, functions & helpers
301 */
302struct radeon_mc {
303 resource_size_t aper_size;
304 resource_size_t aper_base;
305 resource_size_t agp_base;
7a50f01a
DA		 306 /* for some chips with <= 32MB we need to lie
307 * about vram size near mc fb location */
3ce0a23d
JG		 308 u64 mc_vram_size;
309 u64 gtt_location;
310 u64 gtt_size;
311 u64 gtt_start;
312 u64 gtt_end;
313 u64 vram_location;
314 u64 vram_start;
315 u64 vram_end;
771fe6b9 316 unsigned vram_width;
3ce0a23d 317 u64 real_vram_size;
771fe6b9
JG		 318 int vram_mtrr;
319 bool vram_is_ddr;
320};
321
322int radeon_mc_setup(struct radeon_device *rdev);
323
324
325/*
326 * GPU scratch registers structures, functions & helpers
327 */
328struct radeon_scratch {
329 unsigned num_reg;
330 bool free[32];
331 uint32_t reg[32];
332};
333
334int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
335void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
336
337
338/*
339 * IRQS.
340 */
341struct radeon_irq {
342 bool installed;
343 bool sw_int;
344 /* FIXME: use a define max crtc rather than hardcode it */
345 bool crtc_vblank_int[2];
b500f680
AD		 346 /* FIXME: use defines for max hpd/dacs */
347 bool hpd[6];
1614f8b1
DA		 348 spinlock_t sw_lock;
349 int sw_refcount;
771fe6b9
JG		 350};
351
352int radeon_irq_kms_init(struct radeon_device *rdev);
353void radeon_irq_kms_fini(struct radeon_device *rdev);
1614f8b1
DA		 354void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
355void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
771fe6b9
JG		 356
357/*
358 * CP & ring.
359 */
360struct radeon_ib {
361 struct list_head list;
362 unsigned long idx;
363 uint64_t gpu_addr;
364 struct radeon_fence *fence;
513bcb46 365 uint32_t *ptr;
771fe6b9
JG		 366 uint32_t length_dw;
367};
368
ecb114a1
DA		 369/*
370 * locking -
371 * mutex protects scheduled_ibs, ready, alloc_bm
372 */
771fe6b9
JG		 373struct radeon_ib_pool {
374 struct mutex mutex;
4c788679 375 struct radeon_bo *robj;
771fe6b9
JG		 376 struct list_head scheduled_ibs;
377 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
378 bool ready;
379 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
380};
381
382struct radeon_cp {
4c788679 383 struct radeon_bo *ring_obj;
771fe6b9
JG		 384 volatile uint32_t *ring;
385 unsigned rptr;
386 unsigned wptr;
387 unsigned wptr_old;
388 unsigned ring_size;
389 unsigned ring_free_dw;
390 int count_dw;
391 uint64_t gpu_addr;
392 uint32_t align_mask;
393 uint32_t ptr_mask;
394 struct mutex mutex;
395 bool ready;
396};
397
d8f60cfc
AD		 398/*
399 * R6xx+ IH ring
400 */
401struct r600_ih {
4c788679 402 struct radeon_bo *ring_obj;
d8f60cfc
AD		 403 volatile uint32_t *ring;
404 unsigned rptr;
405 unsigned wptr;
406 unsigned wptr_old;
407 unsigned ring_size;
408 uint64_t gpu_addr;
409 uint32_t align_mask;
410 uint32_t ptr_mask;
411 spinlock_t lock;
412 bool enabled;
413};
414
3ce0a23d 415struct r600_blit {
4c788679 416 struct radeon_bo *shader_obj;
3ce0a23d
JG		 417 u64 shader_gpu_addr;
418 u32 vs_offset, ps_offset;
419 u32 state_offset;
420 u32 state_len;
421 u32 vb_used, vb_total;
422 struct radeon_ib *vb_ib;
423};
424
771fe6b9
JG		 425int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
426void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
427int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
428int radeon_ib_pool_init(struct radeon_device *rdev);
429void radeon_ib_pool_fini(struct radeon_device *rdev);
430int radeon_ib_test(struct radeon_device *rdev);
431/* Ring access between begin & end cannot sleep */
432void radeon_ring_free_size(struct radeon_device *rdev);
433int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
434void radeon_ring_unlock_commit(struct radeon_device *rdev);
435void radeon_ring_unlock_undo(struct radeon_device *rdev);
436int radeon_ring_test(struct radeon_device *rdev);
437int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
438void radeon_ring_fini(struct radeon_device *rdev);
439
440
441/*
442 * CS.
443 */
444struct radeon_cs_reloc {
445 struct drm_gem_object *gobj;
4c788679
JG		 446 struct radeon_bo *robj;
447 struct radeon_bo_list lobj;
771fe6b9
JG		 448 uint32_t handle;
449 uint32_t flags;
450};
451
452struct radeon_cs_chunk {
453 uint32_t chunk_id;
454 uint32_t length_dw;
513bcb46
DA		 455 int kpage_idx[2];
456 uint32_t *kpage[2];
771fe6b9 457 uint32_t *kdata;
513bcb46
DA		 458 void __user *user_ptr;
459 int last_copied_page;
460 int last_page_index;
771fe6b9
JG		 461};
462
463struct radeon_cs_parser {
464 struct radeon_device *rdev;
465 struct drm_file *filp;
466 /* chunks */
467 unsigned nchunks;
468 struct radeon_cs_chunk *chunks;
469 uint64_t *chunks_array;
470 /* IB */
471 unsigned idx;
472 /* relocations */
473 unsigned nrelocs;
474 struct radeon_cs_reloc *relocs;
475 struct radeon_cs_reloc **relocs_ptr;
476 struct list_head validated;
477 /* indices of various chunks */
478 int chunk_ib_idx;
479 int chunk_relocs_idx;
480 struct radeon_ib *ib;
481 void *track;
3ce0a23d 482 unsigned family;
513bcb46 483 int parser_error;
771fe6b9
JG		 484};
485
513bcb46
DA		 486extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
487extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
488
489
490static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
491{
492 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
493 u32 pg_idx, pg_offset;
494 u32 idx_value = 0;
495 int new_page;
496
497 pg_idx = (idx * 4) / PAGE_SIZE;
498 pg_offset = (idx * 4) % PAGE_SIZE;
499
500 if (ibc->kpage_idx[0] == pg_idx)
501 return ibc->kpage[0][pg_offset/4];
502 if (ibc->kpage_idx[1] == pg_idx)
503 return ibc->kpage[1][pg_offset/4];
504
505 new_page = radeon_cs_update_pages(p, pg_idx);
506 if (new_page < 0) {
507 p->parser_error = new_page;
508 return 0;
509 }
510
511 idx_value = ibc->kpage[new_page][pg_offset/4];
512 return idx_value;
513}
514
771fe6b9
JG		 515struct radeon_cs_packet {
516 unsigned idx;
517 unsigned type;
518 unsigned reg;
519 unsigned opcode;
520 int count;
521 unsigned one_reg_wr;
522};
523
524typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
525 struct radeon_cs_packet *pkt,
526 unsigned idx, unsigned reg);
527typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
528 struct radeon_cs_packet *pkt);
529
530
531/*
532 * AGP
533 */
534int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 535void radeon_agp_resume(struct radeon_device *rdev);
771fe6b9
JG		 536void radeon_agp_fini(struct radeon_device *rdev);
537
538
539/*
540 * Writeback
541 */
542struct radeon_wb {
4c788679 543 struct radeon_bo *wb_obj;
771fe6b9
JG		 544 volatile uint32_t *wb;
545 uint64_t gpu_addr;
546};
547
c93bb85b
JG		 548/**
549 * struct radeon_pm - power management datas
550 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
551 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
552 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
553 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
554 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
555 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
556 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
557 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
558 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
559 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
560 * @needed_bandwidth: current bandwidth needs
561 *
562 * It keeps track of various data needed to take powermanagement decision.
563 * Bandwith need is used to determine minimun clock of the GPU and memory.
564 * Equation between gpu/memory clock and available bandwidth is hw dependent
565 * (type of memory, bus size, efficiency, ...)
566 */
567struct radeon_pm {
568 fixed20_12 max_bandwidth;
569 fixed20_12 igp_sideport_mclk;
570 fixed20_12 igp_system_mclk;
571 fixed20_12 igp_ht_link_clk;
572 fixed20_12 igp_ht_link_width;
573 fixed20_12 k8_bandwidth;
574 fixed20_12 sideport_bandwidth;
575 fixed20_12 ht_bandwidth;
576 fixed20_12 core_bandwidth;
577 fixed20_12 sclk;
578 fixed20_12 needed_bandwidth;
579};
580
771fe6b9
JG		 581
582/*
583 * Benchmarking
584 */
585void radeon_benchmark(struct radeon_device *rdev);
586
587
ecc0b326
MD		 588/*
589 * Testing
590 */
591void radeon_test_moves(struct radeon_device *rdev);
592
593
771fe6b9
JG		 594/*
595 * Debugfs
596 */
597int radeon_debugfs_add_files(struct radeon_device *rdev,
598 struct drm_info_list *files,
599 unsigned nfiles);
600int radeon_debugfs_fence_init(struct radeon_device *rdev);
601int r100_debugfs_rbbm_init(struct radeon_device *rdev);
602int r100_debugfs_cp_init(struct radeon_device *rdev);
603
604
605/*
606 * ASIC specific functions.
607 */
608struct radeon_asic {
068a117c 609 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 610 void (*fini)(struct radeon_device *rdev);
611 int (*resume)(struct radeon_device *rdev);
612 int (*suspend)(struct radeon_device *rdev);
28d52043 613 void (*vga_set_state)(struct radeon_device *rdev, bool state);
771fe6b9 614 int (*gpu_reset)(struct radeon_device *rdev);
771fe6b9
JG		 615 void (*gart_tlb_flush)(struct radeon_device *rdev);
616 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
617 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
618 void (*cp_fini)(struct radeon_device *rdev);
619 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 620 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 621 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 622 int (*ring_test)(struct radeon_device *rdev);
623 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 624 int (*irq_set)(struct radeon_device *rdev);
625 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 626 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 627 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
628 int (*cs_parse)(struct radeon_cs_parser *p);
629 int (*copy_blit)(struct radeon_device *rdev,
630 uint64_t src_offset,
631 uint64_t dst_offset,
632 unsigned num_pages,
633 struct radeon_fence *fence);
634 int (*copy_dma)(struct radeon_device *rdev,
635 uint64_t src_offset,
636 uint64_t dst_offset,
637 unsigned num_pages,
638 struct radeon_fence *fence);
639 int (*copy)(struct radeon_device *rdev,
640 uint64_t src_offset,
641 uint64_t dst_offset,
642 unsigned num_pages,
643 struct radeon_fence *fence);
7433874e 644 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 645 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 646 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9
JG		 647 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
648 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
649 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 650 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
651 uint32_t tiling_flags, uint32_t pitch,
652 uint32_t offset, uint32_t obj_size);
653 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 654 void (*bandwidth_update)(struct radeon_device *rdev);
23956dfa 655 void (*hdp_flush)(struct radeon_device *rdev);
429770b3
AD		 656 void (*hpd_init)(struct radeon_device *rdev);
657 void (*hpd_fini)(struct radeon_device *rdev);
658 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
659 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
771fe6b9
JG		 660};
661
21f9a437
JG		 662/*
663 * Asic structures
664 */
551ebd83
DA		 665struct r100_asic {
666 const unsigned *reg_safe_bm;
667 unsigned reg_safe_bm_size;
668};
669
21f9a437
JG		 670struct r300_asic {
671 const unsigned *reg_safe_bm;
672 unsigned reg_safe_bm_size;
673};
674
675struct r600_asic {
676 unsigned max_pipes;
677 unsigned max_tile_pipes;
678 unsigned max_simds;
679 unsigned max_backends;
680 unsigned max_gprs;
681 unsigned max_threads;
682 unsigned max_stack_entries;
683 unsigned max_hw_contexts;
684 unsigned max_gs_threads;
685 unsigned sx_max_export_size;
686 unsigned sx_max_export_pos_size;
687 unsigned sx_max_export_smx_size;
688 unsigned sq_num_cf_insts;
689};
690
691struct rv770_asic {
692 unsigned max_pipes;
693 unsigned max_tile_pipes;
694 unsigned max_simds;
695 unsigned max_backends;
696 unsigned max_gprs;
697 unsigned max_threads;
698 unsigned max_stack_entries;
699 unsigned max_hw_contexts;
700 unsigned max_gs_threads;
701 unsigned sx_max_export_size;
702 unsigned sx_max_export_pos_size;
703 unsigned sx_max_export_smx_size;
704 unsigned sq_num_cf_insts;
705 unsigned sx_num_of_sets;
706 unsigned sc_prim_fifo_size;
707 unsigned sc_hiz_tile_fifo_size;
708 unsigned sc_earlyz_tile_fifo_fize;
709};
710
068a117c
JG		 711union radeon_asic_config {
712 struct r300_asic r300;
551ebd83 713 struct r100_asic r100;
3ce0a23d
JG		 714 struct r600_asic r600;
715 struct rv770_asic rv770;
068a117c
JG		 716};
717
771fe6b9
JG		 718
719/*
720 * IOCTL.
721 */
722int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
723 struct drm_file *filp);
724int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
725 struct drm_file *filp);
726int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
727 struct drm_file *file_priv);
728int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
729 struct drm_file *file_priv);
730int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
731 struct drm_file *file_priv);
732int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
733 struct drm_file *file_priv);
734int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
735 struct drm_file *filp);
736int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
737 struct drm_file *filp);
738int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
739 struct drm_file *filp);
740int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
741 struct drm_file *filp);
742int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 743int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
744 struct drm_file *filp);
745int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
746 struct drm_file *filp);
771fe6b9
JG		 747
748
749/*
750 * Core structure, functions and helpers.
751 */
752typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
753typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
754
755struct radeon_device {
9f022ddf 756 struct device *dev;
771fe6b9
JG		 757 struct drm_device *ddev;
758 struct pci_dev *pdev;
759 /* ASIC */
068a117c 760 union radeon_asic_config config;
771fe6b9
JG		 761 enum radeon_family family;
762 unsigned long flags;
763 int usec_timeout;
764 enum radeon_pll_errata pll_errata;
765 int num_gb_pipes;
f779b3e5 766 int num_z_pipes;
771fe6b9
JG		 767 int disp_priority;
768 /* BIOS */
769 uint8_t *bios;
770 bool is_atom_bios;
771 uint16_t bios_header_start;
4c788679 772 struct radeon_bo *stollen_vga_memory;
771fe6b9 773 struct fb_info *fbdev_info;
4c788679 774 struct radeon_bo *fbdev_rbo;
771fe6b9
JG		 775 struct radeon_framebuffer *fbdev_rfb;
776 /* Register mmio */
4c9bc75c
DA		 777 resource_size_t rmmio_base;
778 resource_size_t rmmio_size;
771fe6b9 779 void *rmmio;
771fe6b9
JG		 780 radeon_rreg_t mc_rreg;
781 radeon_wreg_t mc_wreg;
782 radeon_rreg_t pll_rreg;
783 radeon_wreg_t pll_wreg;
de1b2898 784 uint32_t pcie_reg_mask;
771fe6b9
JG		 785 radeon_rreg_t pciep_rreg;
786 radeon_wreg_t pciep_wreg;
787 struct radeon_clock clock;
788 struct radeon_mc mc;
789 struct radeon_gart gart;
790 struct radeon_mode_info mode_info;
791 struct radeon_scratch scratch;
792 struct radeon_mman mman;
793 struct radeon_fence_driver fence_drv;
794 struct radeon_cp cp;
795 struct radeon_ib_pool ib_pool;
796 struct radeon_irq irq;
797 struct radeon_asic *asic;
798 struct radeon_gem gem;
c93bb85b 799 struct radeon_pm pm;
f657c2a7 800 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 801 struct mutex cs_mutex;
802 struct radeon_wb wb;
3ce0a23d 803 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 804 bool gpu_lockup;
805 bool shutdown;
806 bool suspend;
ad49f501 807 bool need_dma32;
733289c2 808 bool accel_working;
e024e110 809 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 810 const struct firmware *me_fw; /* all family ME firmware */
811 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 812 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
3ce0a23d 813 struct r600_blit r600_blit;
3e5cb98d 814 int msi_enabled; /* msi enabled */
d8f60cfc 815 struct r600_ih ih; /* r6/700 interrupt ring */
d4877cf2
AD		 816 struct workqueue_struct *wq;
817 struct work_struct hotplug_work;
dafc3bd5
CK		 818
819 /* audio stuff */
820 struct timer_list audio_timer;
821 int audio_channels;
822 int audio_rate;
823 int audio_bits_per_sample;
824 uint8_t audio_status_bits;
825 uint8_t audio_category_code;
771fe6b9
JG		 826};
827
828int radeon_device_init(struct radeon_device *rdev,
829 struct drm_device *ddev,
830 struct pci_dev *pdev,
831 uint32_t flags);
832void radeon_device_fini(struct radeon_device *rdev);
833int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
834
3ce0a23d
JG		 835/* r600 blit */
836int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
837void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
838void r600_kms_blit_copy(struct radeon_device *rdev,
839 u64 src_gpu_addr, u64 dst_gpu_addr,
840 int size_bytes);
841
de1b2898
DA		 842static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
843{
844 if (reg < 0x10000)
845 return readl(((void __iomem *)rdev->rmmio) + reg);
846 else {
847 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
848 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
849 }
850}
851
852static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
853{
854 if (reg < 0x10000)
855 writel(v, ((void __iomem *)rdev->rmmio) + reg);
856 else {
857 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
858 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
859 }
860}
861
4c788679
JG		 862/*
863 * Cast helper
864 */
865#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 866
867/*
868 * Registers read & write functions.
869 */
870#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
871#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 872#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 873#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 874#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 875#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
876#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
877#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
878#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
879#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
880#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 881#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
882#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
771fe6b9
JG		 883#define WREG32_P(reg, val, mask) \
884 do { \
885 uint32_t tmp_ = RREG32(reg); \
886 tmp_ &= (mask); \
887 tmp_ |= ((val) & ~(mask)); \
888 WREG32(reg, tmp_); \
889 } while (0)
890#define WREG32_PLL_P(reg, val, mask) \
891 do { \
892 uint32_t tmp_ = RREG32_PLL(reg); \
893 tmp_ &= (mask); \
894 tmp_ |= ((val) & ~(mask)); \
895 WREG32_PLL(reg, tmp_); \
896 } while (0)
3ce0a23d 897#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 898
de1b2898
DA		 899/*
900 * Indirect registers accessor
901 */
902static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
903{
904 uint32_t r;
905
906 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
907 r = RREG32(RADEON_PCIE_DATA);
908 return r;
909}
910
911static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
912{
913 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
914 WREG32(RADEON_PCIE_DATA, (v));
915}
916
771fe6b9
JG		 917void r100_pll_errata_after_index(struct radeon_device *rdev);
918
919
920/*
921 * ASICs helpers.
922 */
b995e433
DA		 923#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
924 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 925#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
926 (rdev->family == CHIP_RV200) || \
927 (rdev->family == CHIP_RS100) || \
928 (rdev->family == CHIP_RS200) || \
929 (rdev->family == CHIP_RV250) || \
930 (rdev->family == CHIP_RV280) || \
931 (rdev->family == CHIP_RS300))
932#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
933 (rdev->family == CHIP_RV350) || \
934 (rdev->family == CHIP_R350) || \
935 (rdev->family == CHIP_RV380) || \
936 (rdev->family == CHIP_R420) || \
937 (rdev->family == CHIP_R423) || \
938 (rdev->family == CHIP_RV410) || \
939 (rdev->family == CHIP_RS400) || \
940 (rdev->family == CHIP_RS480))
941#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
942#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
943#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
944
945
946/*
947 * BIOS helpers.
948 */
949#define RBIOS8(i) (rdev->bios[i])
950#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
951#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
952
953int radeon_combios_init(struct radeon_device *rdev);
954void radeon_combios_fini(struct radeon_device *rdev);
955int radeon_atombios_init(struct radeon_device *rdev);
956void radeon_atombios_fini(struct radeon_device *rdev);
957
958
959/*
960 * RING helpers.
961 */
771fe6b9
JG		 962static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
963{
964#if DRM_DEBUG_CODE
965 if (rdev->cp.count_dw <= 0) {
966 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
967 }
968#endif
969 rdev->cp.ring[rdev->cp.wptr++] = v;
970 rdev->cp.wptr &= rdev->cp.ptr_mask;
971 rdev->cp.count_dw--;
972 rdev->cp.ring_free_dw--;
973}
974
975
976/*
977 * ASICs macro.
978 */
068a117c 979#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 980#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
981#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
982#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 983#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 984#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
771fe6b9 985#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
771fe6b9
JG		 986#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
987#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 988#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 989#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 990#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
991#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 992#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
993#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 994#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 995#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
996#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
997#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
998#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 999#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 1000#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 1001#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
93e7de7b 1002#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
771fe6b9
JG		 1003#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1004#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 1005#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1006#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 1007#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
23956dfa 1008#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
429770b3
AD		 1009#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1010#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1011#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1012#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
771fe6b9 1013
6cf8a3f5 1014/* Common functions */
4aac0473 1015extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
21f9a437
JG		 1016extern int radeon_modeset_init(struct radeon_device *rdev);
1017extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1018extern bool radeon_card_posted(struct radeon_device *rdev);
72542d77 1019extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437
JG		 1020extern int radeon_clocks_init(struct radeon_device *rdev);
1021extern void radeon_clocks_fini(struct radeon_device *rdev);
1022extern void radeon_scratch_init(struct radeon_device *rdev);
1023extern void radeon_surface_init(struct radeon_device *rdev);
1024extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1025extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1026extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 1027extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 1028extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
6cf8a3f5 1029
a18d7ea1 1030/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
9f022ddf
JG		 1031struct r100_mc_save {
1032 u32 GENMO_WT;
1033 u32 CRTC_EXT_CNTL;
1034 u32 CRTC_GEN_CNTL;
1035 u32 CRTC2_GEN_CNTL;
1036 u32 CUR_OFFSET;
1037 u32 CUR2_OFFSET;
1038};
1039extern void r100_cp_disable(struct radeon_device *rdev);
1040extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1041extern void r100_cp_fini(struct radeon_device *rdev);
21f9a437 1042extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
4aac0473
JG		 1043extern int r100_pci_gart_init(struct radeon_device *rdev);
1044extern void r100_pci_gart_fini(struct radeon_device *rdev);
21f9a437
JG		 1045extern int r100_pci_gart_enable(struct radeon_device *rdev);
1046extern void r100_pci_gart_disable(struct radeon_device *rdev);
1047extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
9f022ddf
JG		 1048extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1049extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1050extern void r100_ib_fini(struct radeon_device *rdev);
1051extern int r100_ib_init(struct radeon_device *rdev);
1052extern void r100_irq_disable(struct radeon_device *rdev);
1053extern int r100_irq_set(struct radeon_device *rdev);
1054extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1055extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
21f9a437 1056extern void r100_vram_init_sizes(struct radeon_device *rdev);
9f022ddf
JG		 1057extern void r100_wb_disable(struct radeon_device *rdev);
1058extern void r100_wb_fini(struct radeon_device *rdev);
1059extern int r100_wb_init(struct radeon_device *rdev);
d39c3b89
JG		 1060extern void r100_hdp_reset(struct radeon_device *rdev);
1061extern int r100_rb2d_reset(struct radeon_device *rdev);
1062extern int r100_cp_reset(struct radeon_device *rdev);
ca6ffc64 1063extern void r100_vga_render_disable(struct radeon_device *rdev);
207bf9e9
JG		 1064extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1065 struct radeon_cs_packet *pkt,
4c788679 1066 struct radeon_bo *robj);
207bf9e9
JG		 1067extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1068 struct radeon_cs_packet *pkt,
1069 const unsigned *auth, unsigned n,
1070 radeon_packet0_check_t check);
1071extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1072 struct radeon_cs_packet *pkt,
1073 unsigned idx);
17e15b0c 1074extern void r100_enable_bm(struct radeon_device *rdev);
92cde00c 1075extern void r100_set_common_regs(struct radeon_device *rdev);
9f022ddf 1076
d4550907
JG		 1077/* rv200,rv250,rv280 */
1078extern void r200_set_safe_registers(struct radeon_device *rdev);
9f022ddf
JG		 1079
1080/* r300,r350,rv350,rv370,rv380 */
1081extern void r300_set_reg_safe(struct radeon_device *rdev);
1082extern void r300_mc_program(struct radeon_device *rdev);
1083extern void r300_vram_info(struct radeon_device *rdev);
ca6ffc64
JG		 1084extern void r300_clock_startup(struct radeon_device *rdev);
1085extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473
JG		 1086extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1087extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1088extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1089extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1090
905b6822 1091/* r420,r423,rv410 */
d39c3b89 1092extern int r420_mc_init(struct radeon_device *rdev);
21f9a437
JG		 1093extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1094extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1095extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
d39c3b89 1096extern void r420_pipes_init(struct radeon_device *rdev);
905b6822 1097
21f9a437 1098/* rv515 */
d39c3b89
JG		 1099struct rv515_mc_save {
1100 u32 d1vga_control;
1101 u32 d2vga_control;
1102 u32 vga_render_control;
1103 u32 vga_hdp_control;
1104 u32 d1crtc_control;
1105 u32 d2crtc_control;
1106};
21f9a437 1107extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
d39c3b89
JG		 1108extern void rv515_vga_render_disable(struct radeon_device *rdev);
1109extern void rv515_set_safe_registers(struct radeon_device *rdev);
f0ed1f65
JG		 1110extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1111extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1112extern void rv515_clock_startup(struct radeon_device *rdev);
1113extern void rv515_debugfs(struct radeon_device *rdev);
1114extern int rv515_suspend(struct radeon_device *rdev);
21f9a437 1115
3bc68535
JG		 1116/* rs400 */
1117extern int rs400_gart_init(struct radeon_device *rdev);
1118extern int rs400_gart_enable(struct radeon_device *rdev);
1119extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1120extern void rs400_gart_disable(struct radeon_device *rdev);
1121extern void rs400_gart_fini(struct radeon_device *rdev);
1122
1123/* rs600 */
1124extern void rs600_set_safe_registers(struct radeon_device *rdev);
ac447df4
JG		 1125extern int rs600_irq_set(struct radeon_device *rdev);
1126extern void rs600_irq_disable(struct radeon_device *rdev);
3bc68535 1127
21f9a437
JG		 1128/* rs690, rs740 */
1129extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1130 struct drm_display_mode *mode1,
1131 struct drm_display_mode *mode2);
1132
1133/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1134extern bool r600_card_posted(struct radeon_device *rdev);
1135extern void r600_cp_stop(struct radeon_device *rdev);
1136extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1137extern int r600_cp_resume(struct radeon_device *rdev);
1138extern int r600_count_pipe_bits(uint32_t val);
1139extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1140extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1141extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1142extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1143extern int r600_ib_test(struct radeon_device *rdev);
1144extern int r600_ring_test(struct radeon_device *rdev);
21f9a437 1145extern void r600_wb_fini(struct radeon_device *rdev);
81cc35bf
JG		 1146extern int r600_wb_enable(struct radeon_device *rdev);
1147extern void r600_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1148extern void r600_scratch_init(struct radeon_device *rdev);
1149extern int r600_blit_init(struct radeon_device *rdev);
1150extern void r600_blit_fini(struct radeon_device *rdev);
d8f60cfc 1151extern int r600_init_microcode(struct radeon_device *rdev);
fe62e1a4 1152extern int r600_gpu_reset(struct radeon_device *rdev);
d8f60cfc
AD		 1153/* r600 irq */
1154extern int r600_irq_init(struct radeon_device *rdev);
1155extern void r600_irq_fini(struct radeon_device *rdev);
1156extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1157extern int r600_irq_set(struct radeon_device *rdev);
21f9a437 1158
dafc3bd5
CK		 1159extern int r600_audio_init(struct radeon_device *rdev);
1160extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1161extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1162extern void r600_audio_fini(struct radeon_device *rdev);
1163extern void r600_hdmi_init(struct drm_encoder *encoder);
1164extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
1165extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1166extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1167extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1168 int channels,
1169 int rate,
1170 int bps,
1171 uint8_t status_bits,
1172 uint8_t category_code);
1173
4c788679
JG		 1174#include "radeon_object.h"
1175
771fe6b9 1176#endif
Linux 6.x block layer and io_uring tree(s)