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drm/radeon: add structs to store vce clock voltage deps
[linux-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
771fe6b9
JG		 101
102/*
103 * Copy from radeon_drv.h so we don't have to include both and have conflicting
104 * symbol;
105 */
bb635567
JG		 106#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 108/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 109#define RADEON_IB_POOL_SIZE 16
110#define RADEON_DEBUGFS_MAX_COMPONENTS 32
111#define RADEONFB_CONN_LIMIT 4
112#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 113
1b37078b 114/* max number of rings */
f2ba57b5 115#define RADEON_NUM_RINGS 6
bb635567
JG		 116
117/* fence seq are set to this number when signaled */
118#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 119
120/* internal ring indices */
121/* r1xx+ has gfx CP ring */
f2ba57b5 122#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 123
124/* cayman has 2 compute CP rings */
f2ba57b5
CK		 125#define CAYMAN_RING_TYPE_CP1_INDEX 1
126#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 127
4d75658b
AD		 128/* R600+ has an async dma ring */
129#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 130/* cayman add a second async dma ring */
131#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 132
f2ba57b5
CK		 133/* R600+ */
134#define R600_RING_TYPE_UVD_INDEX 5
135
721604a1 136/* hardcode those limit for now */
ca19f21e 137#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 138#define RADEON_VA_RESERVED_SIZE (8 << 20)
139#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 140
ec46c76d
AD		 141/* reset flags */
142#define RADEON_RESET_GFX (1 << 0)
143#define RADEON_RESET_COMPUTE (1 << 1)
144#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 145#define RADEON_RESET_CP (1 << 3)
146#define RADEON_RESET_GRBM (1 << 4)
147#define RADEON_RESET_DMA1 (1 << 5)
148#define RADEON_RESET_RLC (1 << 6)
149#define RADEON_RESET_SEM (1 << 7)
150#define RADEON_RESET_IH (1 << 8)
151#define RADEON_RESET_VMC (1 << 9)
152#define RADEON_RESET_MC (1 << 10)
153#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 154
22c775ce
AD		 155/* CG block flags */
156#define RADEON_CG_BLOCK_GFX (1 << 0)
157#define RADEON_CG_BLOCK_MC (1 << 1)
158#define RADEON_CG_BLOCK_SDMA (1 << 2)
159#define RADEON_CG_BLOCK_UVD (1 << 3)
160#define RADEON_CG_BLOCK_VCE (1 << 4)
161#define RADEON_CG_BLOCK_HDP (1 << 5)
162
9e05fa1d
AD		 163/* max cursor sizes (in pixels) */
164#define CURSOR_WIDTH 64
165#define CURSOR_HEIGHT 64
166
167#define CIK_CURSOR_WIDTH 128
168#define CIK_CURSOR_HEIGHT 128
169
771fe6b9
JG		 170/*
171 * Errata workarounds.
172 */
173enum radeon_pll_errata {
174 CHIP_ERRATA_R300_CG = 0x00000001,
175 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
176 CHIP_ERRATA_PLL_DELAY = 0x00000004
177};
178
179
180struct radeon_device;
181
182
183/*
184 * BIOS.
185 */
186bool radeon_get_bios(struct radeon_device *rdev);
187
188/*
3ce0a23d 189 * Dummy page
771fe6b9 190 */
3ce0a23d
JG		 191struct radeon_dummy_page {
192 struct page *page;
193 dma_addr_t addr;
194};
195int radeon_dummy_page_init(struct radeon_device *rdev);
196void radeon_dummy_page_fini(struct radeon_device *rdev);
197
771fe6b9 198
3ce0a23d
JG		 199/*
200 * Clocks
201 */
771fe6b9
JG		 202struct radeon_clock {
203 struct radeon_pll p1pll;
204 struct radeon_pll p2pll;
bcc1c2a1 205 struct radeon_pll dcpll;
771fe6b9
JG		 206 struct radeon_pll spll;
207 struct radeon_pll mpll;
208 /* 10 Khz units */
209 uint32_t default_mclk;
210 uint32_t default_sclk;
bcc1c2a1 211 uint32_t default_dispclk;
4489cd62 212 uint32_t current_dispclk;
bcc1c2a1 213 uint32_t dp_extclk;
b20f9bef 214 uint32_t max_pixel_clock;
771fe6b9
JG		 215};
216
7433874e
RM		 217/*
218 * Power management
219 */
220int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 221void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 222void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 223void radeon_pm_suspend(struct radeon_device *rdev);
224void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 225void radeon_combios_get_power_modes(struct radeon_device *rdev);
226void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 227int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
228 u8 clock_type,
229 u32 clock,
230 bool strobe_mode,
231 struct atom_clock_dividers *dividers);
eaa778af
AD		 232int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
233 u32 clock,
234 bool strobe_mode,
235 struct atom_mpll_param *mpll_param);
8a83ec5e 236void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 237int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
238 u16 voltage_level, u8 voltage_type,
239 u32 *gpio_value, u32 *gpio_mask);
240void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
241 u32 eng_clock, u32 mem_clock);
242int radeon_atom_get_voltage_step(struct radeon_device *rdev,
243 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 244int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
245 u16 voltage_id, u16 *voltage);
beb79f40
AD		 246int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
247 u16 *voltage,
248 u16 leakage_idx);
ae5b0abb
AD		 249int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
250 u8 voltage_type,
251 u16 nominal_voltage,
252 u16 *true_voltage);
253int radeon_atom_get_min_voltage(struct radeon_device *rdev,
254 u8 voltage_type, u16 *min_voltage);
255int radeon_atom_get_max_voltage(struct radeon_device *rdev,
256 u8 voltage_type, u16 *max_voltage);
257int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 258 u8 voltage_type, u8 voltage_mode,
ae5b0abb 259 struct atom_voltage_table *voltage_table);
58653abd
AD		 260bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
261 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 262void radeon_atom_update_memory_dll(struct radeon_device *rdev,
263 u32 mem_clock);
264void radeon_atom_set_ac_timing(struct radeon_device *rdev,
265 u32 mem_clock);
266int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
267 u8 module_index,
268 struct atom_mc_reg_table *reg_table);
269int radeon_atom_get_memory_info(struct radeon_device *rdev,
270 u8 module_index, struct atom_memory_info *mem_info);
271int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
272 bool gddr5, u8 module_index,
273 struct atom_memory_clock_range_table *mclk_range_table);
274int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
275 u16 voltage_id, u16 *voltage);
f892034a 276void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 277extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
278 unsigned *bankh, unsigned *mtaspect,
279 unsigned *tile_split);
3ce0a23d 280
771fe6b9
JG		 281/*
282 * Fences.
283 */
284struct radeon_fence_driver {
285 uint32_t scratch_reg;
30eb77f4
JG		 286 uint64_t gpu_addr;
287 volatile uint32_t *cpu_addr;
68e250b7
CK		 288 /* sync_seq is protected by ring emission lock */
289 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 290 atomic64_t last_seq;
36abacae 291 unsigned long last_activity;
0a0c7596 292 bool initialized;
771fe6b9
JG		 293};
294
295struct radeon_fence {
296 struct radeon_device *rdev;
297 struct kref kref;
771fe6b9 298 /* protected by radeon_fence.lock */
bb635567 299 uint64_t seq;
7465280c 300 /* RB, DMA, etc. */
bb635567 301 unsigned ring;
771fe6b9
JG		 302};
303
30eb77f4
JG		 304int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
305int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 306void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 307void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 308int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 309void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 310bool radeon_fence_signaled(struct radeon_fence *fence);
311int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
8a47cc9e 312int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 313int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 314int radeon_fence_wait_any(struct radeon_device *rdev,
315 struct radeon_fence **fences,
316 bool intr);
771fe6b9
JG		 317struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
318void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 319unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 320bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
321void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
322static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
323 struct radeon_fence *b)
324{
325 if (!a) {
326 return b;
327 }
328
329 if (!b) {
330 return a;
331 }
332
333 BUG_ON(a->ring != b->ring);
334
335 if (a->seq > b->seq) {
336 return a;
337 } else {
338 return b;
339 }
340}
771fe6b9 341
ee60e29f
CK		 342static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
343 struct radeon_fence *b)
344{
345 if (!a) {
346 return false;
347 }
348
349 if (!b) {
350 return true;
351 }
352
353 BUG_ON(a->ring != b->ring);
354
355 return a->seq < b->seq;
356}
357
e024e110
DA		 358/*
359 * Tiling registers
360 */
361struct radeon_surface_reg {
4c788679 362 struct radeon_bo *bo;
e024e110
DA		 363};
364
365#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 366
367/*
4c788679 368 * TTM.
771fe6b9 369 */
4c788679
JG		 370struct radeon_mman {
371 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 372 struct drm_global_reference mem_global_ref;
4c788679 373 struct ttm_bo_device bdev;
0a0c7596
JG		 374 bool mem_global_referenced;
375 bool initialized;
4c788679
JG		 376};
377
721604a1
JG		 378/* bo virtual address in a specific vm */
379struct radeon_bo_va {
e971bd5e 380 /* protected by bo being reserved */
721604a1 381 struct list_head bo_list;
721604a1
JG		 382 uint64_t soffset;
383 uint64_t eoffset;
384 uint32_t flags;
385 bool valid;
e971bd5e
CK		 386 unsigned ref_count;
387
388 /* protected by vm mutex */
389 struct list_head vm_list;
390
391 /* constant after initialization */
392 struct radeon_vm *vm;
393 struct radeon_bo *bo;
721604a1
JG		 394};
395
4c788679
JG		 396struct radeon_bo {
397 /* Protected by gem.mutex */
398 struct list_head list;
399 /* Protected by tbo.reserved */
312ea8da
JG		 400 u32 placements[3];
401 struct ttm_placement placement;
4c788679
JG		 402 struct ttm_buffer_object tbo;
403 struct ttm_bo_kmap_obj kmap;
404 unsigned pin_count;
405 void *kptr;
406 u32 tiling_flags;
407 u32 pitch;
408 int surface_reg;
721604a1
JG		 409 /* list of all virtual address to which this bo
410 * is associated to
411 */
412 struct list_head va;
4c788679
JG		 413 /* Constant after initialization */
414 struct radeon_device *rdev;
441921d5 415 struct drm_gem_object gem_base;
63bc620b 416
409851f4
JG		 417 struct ttm_bo_kmap_obj dma_buf_vmap;
418 pid_t pid;
4c788679 419};
7e4d15d9 420#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 421
4c788679 422struct radeon_bo_list {
147666fb 423 struct ttm_validate_buffer tv;
4c788679 424 struct radeon_bo *bo;
771fe6b9 425 uint64_t gpu_offset;
4474f3a9
CK		 426 bool written;
427 unsigned domain;
428 unsigned alt_domain;
4c788679 429 u32 tiling_flags;
771fe6b9
JG		 430};
431
409851f4
JG		 432int radeon_gem_debugfs_init(struct radeon_device *rdev);
433
b15ba512
JG		 434/* sub-allocation manager, it has to be protected by another lock.
435 * By conception this is an helper for other part of the driver
436 * like the indirect buffer or semaphore, which both have their
437 * locking.
438 *
439 * Principe is simple, we keep a list of sub allocation in offset
440 * order (first entry has offset == 0, last entry has the highest
441 * offset).
442 *
443 * When allocating new object we first check if there is room at
444 * the end total_size - (last_object_offset + last_object_size) >=
445 * alloc_size. If so we allocate new object there.
446 *
447 * When there is not enough room at the end, we start waiting for
448 * each sub object until we reach object_offset+object_size >=
449 * alloc_size, this object then become the sub object we return.
450 *
451 * Alignment can't be bigger than page size.
452 *
453 * Hole are not considered for allocation to keep things simple.
454 * Assumption is that there won't be hole (all object on same
455 * alignment).
456 */
457struct radeon_sa_manager {
bfb38d35 458 wait_queue_head_t wq;
b15ba512 459 struct radeon_bo *bo;
c3b7fe8b
CK		 460 struct list_head *hole;
461 struct list_head flist[RADEON_NUM_RINGS];
462 struct list_head olist;
b15ba512
JG		 463 unsigned size;
464 uint64_t gpu_addr;
465 void *cpu_ptr;
466 uint32_t domain;
6c4f978b 467 uint32_t align;
b15ba512
JG		 468};
469
470struct radeon_sa_bo;
471
472/* sub-allocation buffer */
473struct radeon_sa_bo {
c3b7fe8b
CK		 474 struct list_head olist;
475 struct list_head flist;
b15ba512 476 struct radeon_sa_manager *manager;
e6661a96
CK		 477 unsigned soffset;
478 unsigned eoffset;
557017a0 479 struct radeon_fence *fence;
b15ba512
JG		 480};
481
771fe6b9
JG		 482/*
483 * GEM objects.
484 */
485struct radeon_gem {
4c788679 486 struct mutex mutex;
771fe6b9
JG		 487 struct list_head objects;
488};
489
490int radeon_gem_init(struct radeon_device *rdev);
491void radeon_gem_fini(struct radeon_device *rdev);
492int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 493 int alignment, int initial_domain,
494 bool discardable, bool kernel,
495 struct drm_gem_object **obj);
771fe6b9 496
ff72145b
DA		 497int radeon_mode_dumb_create(struct drm_file *file_priv,
498 struct drm_device *dev,
499 struct drm_mode_create_dumb *args);
500int radeon_mode_dumb_mmap(struct drm_file *filp,
501 struct drm_device *dev,
502 uint32_t handle, uint64_t *offset_p);
503int radeon_mode_dumb_destroy(struct drm_file *file_priv,
504 struct drm_device *dev,
505 uint32_t handle);
771fe6b9 506
c1341e52
JG		 507/*
508 * Semaphores.
509 */
c1341e52
JG		 510/* everything here is constant */
511struct radeon_semaphore {
a8c05940
JG		 512 struct radeon_sa_bo *sa_bo;
513 signed waiters;
c1341e52 514 uint64_t gpu_addr;
c1341e52
JG		 515};
516
c1341e52
JG		 517int radeon_semaphore_create(struct radeon_device *rdev,
518 struct radeon_semaphore **semaphore);
519void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
520 struct radeon_semaphore *semaphore);
521void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
522 struct radeon_semaphore *semaphore);
8f676c4c
CK		 523int radeon_semaphore_sync_rings(struct radeon_device *rdev,
524 struct radeon_semaphore *semaphore,
220907d9 525 int signaler, int waiter);
c1341e52 526void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 527 struct radeon_semaphore **semaphore,
a8c05940 528 struct radeon_fence *fence);
c1341e52 529
771fe6b9
JG		 530/*
531 * GART structures, functions & helpers
532 */
533struct radeon_mc;
534
a77f1718 535#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 536#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 537#define RADEON_GPU_PAGE_SHIFT 12
721604a1 538#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 539
771fe6b9
JG		 540struct radeon_gart {
541 dma_addr_t table_addr;
c9a1be96
JG		 542 struct radeon_bo *robj;
543 void *ptr;
771fe6b9
JG		 544 unsigned num_gpu_pages;
545 unsigned num_cpu_pages;
546 unsigned table_size;
771fe6b9
JG		 547 struct page **pages;
548 dma_addr_t *pages_addr;
549 bool ready;
550};
551
552int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
553void radeon_gart_table_ram_free(struct radeon_device *rdev);
554int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
555void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 556int radeon_gart_table_vram_pin(struct radeon_device *rdev);
557void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 558int radeon_gart_init(struct radeon_device *rdev);
559void radeon_gart_fini(struct radeon_device *rdev);
560void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
561 int pages);
562int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 563 int pages, struct page **pagelist,
564 dma_addr_t *dma_addr);
c9a1be96 565void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 566
567
568/*
569 * GPU MC structures, functions & helpers
570 */
571struct radeon_mc {
572 resource_size_t aper_size;
573 resource_size_t aper_base;
574 resource_size_t agp_base;
7a50f01a
DA		 575 /* for some chips with <= 32MB we need to lie
576 * about vram size near mc fb location */
3ce0a23d 577 u64 mc_vram_size;
d594e46a 578 u64 visible_vram_size;
3ce0a23d
JG		 579 u64 gtt_size;
580 u64 gtt_start;
581 u64 gtt_end;
3ce0a23d
JG		 582 u64 vram_start;
583 u64 vram_end;
771fe6b9 584 unsigned vram_width;
3ce0a23d 585 u64 real_vram_size;
771fe6b9
JG		 586 int vram_mtrr;
587 bool vram_is_ddr;
d594e46a 588 bool igp_sideport_enabled;
8d369bb1 589 u64 gtt_base_align;
9ed8b1f9 590 u64 mc_mask;
771fe6b9
JG		 591};
592
06b6476d
AD		 593bool radeon_combios_sideport_present(struct radeon_device *rdev);
594bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 595
596/*
597 * GPU scratch registers structures, functions & helpers
598 */
599struct radeon_scratch {
600 unsigned num_reg;
724c80e1 601 uint32_t reg_base;
771fe6b9
JG		 602 bool free[32];
603 uint32_t reg[32];
604};
605
606int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
607void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
608
75efdee1
AD		 609/*
610 * GPU doorbell structures, functions & helpers
611 */
612struct radeon_doorbell {
613 u32 num_pages;
614 bool free[1024];
615 /* doorbell mmio */
616 resource_size_t base;
617 resource_size_t size;
618 void __iomem *ptr;
619};
620
621int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
622void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 623
624/*
625 * IRQS.
626 */
6f34be50
AD		 627
628struct radeon_unpin_work {
629 struct work_struct work;
630 struct radeon_device *rdev;
631 int crtc_id;
632 struct radeon_fence *fence;
633 struct drm_pending_vblank_event *event;
634 struct radeon_bo *old_rbo;
635 u64 new_crtc_base;
636};
637
638struct r500_irq_stat_regs {
639 u32 disp_int;
f122c610 640 u32 hdmi0_status;
6f34be50
AD		 641};
642
643struct r600_irq_stat_regs {
644 u32 disp_int;
645 u32 disp_int_cont;
646 u32 disp_int_cont2;
647 u32 d1grph_int;
648 u32 d2grph_int;
f122c610
AD		 649 u32 hdmi0_status;
650 u32 hdmi1_status;
6f34be50
AD		 651};
652
653struct evergreen_irq_stat_regs {
654 u32 disp_int;
655 u32 disp_int_cont;
656 u32 disp_int_cont2;
657 u32 disp_int_cont3;
658 u32 disp_int_cont4;
659 u32 disp_int_cont5;
660 u32 d1grph_int;
661 u32 d2grph_int;
662 u32 d3grph_int;
663 u32 d4grph_int;
664 u32 d5grph_int;
665 u32 d6grph_int;
f122c610
AD		 666 u32 afmt_status1;
667 u32 afmt_status2;
668 u32 afmt_status3;
669 u32 afmt_status4;
670 u32 afmt_status5;
671 u32 afmt_status6;
6f34be50
AD		 672};
673
a59781bb
AD		 674struct cik_irq_stat_regs {
675 u32 disp_int;
676 u32 disp_int_cont;
677 u32 disp_int_cont2;
678 u32 disp_int_cont3;
679 u32 disp_int_cont4;
680 u32 disp_int_cont5;
681 u32 disp_int_cont6;
682};
683
6f34be50
AD		 684union radeon_irq_stat_regs {
685 struct r500_irq_stat_regs r500;
686 struct r600_irq_stat_regs r600;
687 struct evergreen_irq_stat_regs evergreen;
a59781bb 688 struct cik_irq_stat_regs cik;
6f34be50
AD		 689};
690
54bd5206
IH		 691#define RADEON_MAX_HPD_PINS 6
692#define RADEON_MAX_CRTCS 6
f122c610 693#define RADEON_MAX_AFMT_BLOCKS 6
54bd5206 694
771fe6b9 695struct radeon_irq {
fb98257a
CK		 696 bool installed;
697 spinlock_t lock;
736fc37f 698 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 699 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 700 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 701 wait_queue_head_t vblank_queue;
702 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 703 bool afmt[RADEON_MAX_AFMT_BLOCKS];
704 union radeon_irq_stat_regs stat_regs;
4a6369e9 705 bool dpm_thermal;
771fe6b9
JG		 706};
707
708int radeon_irq_kms_init(struct radeon_device *rdev);
709void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 710void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
711void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 712void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
713void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 714void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
715void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
716void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
717void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 718
719/*
e32eb50d 720 * CP & rings.
771fe6b9 721 */
7465280c 722
771fe6b9 723struct radeon_ib {
68470ae7
JG		 724 struct radeon_sa_bo *sa_bo;
725 uint32_t length_dw;
726 uint64_t gpu_addr;
727 uint32_t *ptr;
876dc9f3 728 int ring;
68470ae7 729 struct radeon_fence *fence;
4bf3dd92 730 struct radeon_vm *vm;
68470ae7 731 bool is_const_ib;
220907d9 732 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
68470ae7 733 struct radeon_semaphore *semaphore;
771fe6b9
JG		 734};
735
e32eb50d 736struct radeon_ring {
4c788679 737 struct radeon_bo *ring_obj;
771fe6b9
JG		 738 volatile uint32_t *ring;
739 unsigned rptr;
5596a9db
CK		 740 unsigned rptr_offs;
741 unsigned rptr_reg;
45df6803 742 unsigned rptr_save_reg;
89d35807
AD		 743 u64 next_rptr_gpu_addr;
744 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 745 unsigned wptr;
746 unsigned wptr_old;
5596a9db 747 unsigned wptr_reg;
771fe6b9
JG		 748 unsigned ring_size;
749 unsigned ring_free_dw;
750 int count_dw;
069211e5
CK		 751 unsigned long last_activity;
752 unsigned last_rptr;
771fe6b9
JG		 753 uint64_t gpu_addr;
754 uint32_t align_mask;
755 uint32_t ptr_mask;
771fe6b9 756 bool ready;
78c5560a
AD		 757 u32 ptr_reg_shift;
758 u32 ptr_reg_mask;
759 u32 nop;
8b25ed34 760 u32 idx;
5f0839c1
JG		 761 u64 last_semaphore_signal_addr;
762 u64 last_semaphore_wait_addr;
963e81f9
AD		 763 /* for CIK queues */
764 u32 me;
765 u32 pipe;
766 u32 queue;
767 struct radeon_bo *mqd_obj;
768 u32 doorbell_page_num;
769 u32 doorbell_offset;
770 unsigned wptr_offs;
771};
772
773struct radeon_mec {
774 struct radeon_bo *hpd_eop_obj;
775 u64 hpd_eop_gpu_addr;
776 u32 num_pipe;
777 u32 num_mec;
778 u32 num_queue;
771fe6b9
JG		 779};
780
721604a1
JG		 781/*
782 * VM
783 */
ee60e29f 784
fa87e62d 785/* maximum number of VMIDs */
ee60e29f
CK		 786#define RADEON_NUM_VM 16
787
fa87e62d
DC		 788/* defines number of bits in page table versus page directory,
789 * a page is 4KB so we have 12 bits offset, 9 bits in the page
790 * table and the remaining 19 bits are in the page directory */
791#define RADEON_VM_BLOCK_SIZE 9
792
793/* number of entries in page table */
794#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
795
1c01103c
AD		 796/* PTBs (Page Table Blocks) need to be aligned to 32K */
797#define RADEON_VM_PTB_ALIGN_SIZE 32768
798#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
799#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
800
721604a1
JG		 801struct radeon_vm {
802 struct list_head list;
803 struct list_head va;
ee60e29f 804 unsigned id;
90a51a32
CK		 805
806 /* contains the page directory */
807 struct radeon_sa_bo *page_directory;
808 uint64_t pd_gpu_addr;
809
810 /* array of page tables, one for each page directory entry */
811 struct radeon_sa_bo **page_tables;
812
721604a1
JG		 813 struct mutex mutex;
814 /* last fence for cs using this vm */
815 struct radeon_fence *fence;
9b40e5d8
CK		 816 /* last flush or NULL if we still need to flush */
817 struct radeon_fence *last_flush;
721604a1
JG		 818};
819
721604a1 820struct radeon_vm_manager {
36ff39c4 821 struct mutex lock;
721604a1 822 struct list_head lru_vm;
ee60e29f 823 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 824 struct radeon_sa_manager sa_manager;
825 uint32_t max_pfn;
721604a1
JG		 826 /* number of VMIDs */
827 unsigned nvm;
828 /* vram base address for page table entry */
829 u64 vram_base_offset;
67e915e4
AD		 830 /* is vm enabled? */
831 bool enabled;
721604a1
JG		 832};
833
834/*
835 * file private structure
836 */
837struct radeon_fpriv {
838 struct radeon_vm vm;
839};
840
d8f60cfc
AD		 841/*
842 * R6xx+ IH ring
843 */
844struct r600_ih {
4c788679 845 struct radeon_bo *ring_obj;
d8f60cfc
AD		 846 volatile uint32_t *ring;
847 unsigned rptr;
d8f60cfc
AD		 848 unsigned ring_size;
849 uint64_t gpu_addr;
d8f60cfc 850 uint32_t ptr_mask;
c20dc369 851 atomic_t lock;
d8f60cfc
AD		 852 bool enabled;
853};
854
347e7592 855/*
2948f5e6 856 * RLC stuff
347e7592 857 */
2948f5e6
AD		 858#include "clearstate_defs.h"
859
860struct radeon_rlc {
347e7592
AD		 861 /* for power gating */
862 struct radeon_bo *save_restore_obj;
863 uint64_t save_restore_gpu_addr;
2948f5e6 864 volatile uint32_t *sr_ptr;
1fd11777 865 const u32 *reg_list;
2948f5e6 866 u32 reg_list_size;
347e7592
AD		 867 /* for clear state */
868 struct radeon_bo *clear_state_obj;
869 uint64_t clear_state_gpu_addr;
2948f5e6 870 volatile uint32_t *cs_ptr;
1fd11777 871 const struct cs_section_def *cs_data;
22c775ce
AD		 872 u32 clear_state_size;
873 /* for cp tables */
874 struct radeon_bo *cp_table_obj;
875 uint64_t cp_table_gpu_addr;
876 volatile uint32_t *cp_table_ptr;
877 u32 cp_table_size;
347e7592
AD		 878};
879
69e130a6 880int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 881 struct radeon_ib *ib, struct radeon_vm *vm,
882 unsigned size);
f2e39221 883void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
43f1214a 884void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
4ef72566
CK		 885int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
886 struct radeon_ib *const_ib);
771fe6b9
JG		 887int radeon_ib_pool_init(struct radeon_device *rdev);
888void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 889int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 890/* Ring access between begin & end cannot sleep */
89d35807
AD		 891bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
892 struct radeon_ring *ring);
e32eb50d
CK		 893void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
894int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
895int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
896void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
897void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 898void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 899void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
900int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 901void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 902void radeon_ring_lockup_update(struct radeon_ring *ring);
903bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 904unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
905 uint32_t **data);
906int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
907 unsigned size, uint32_t *data);
e32eb50d 908int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
78c5560a
AD		 909 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
910 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
e32eb50d 911void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 912
913
4d75658b
AD		 914/* r600 async dma */
915void r600_dma_stop(struct radeon_device *rdev);
916int r600_dma_resume(struct radeon_device *rdev);
917void r600_dma_fini(struct radeon_device *rdev);
918
8c5fd7ef
AD		 919void cayman_dma_stop(struct radeon_device *rdev);
920int cayman_dma_resume(struct radeon_device *rdev);
921void cayman_dma_fini(struct radeon_device *rdev);
922
771fe6b9
JG		 923/*
924 * CS.
925 */
926struct radeon_cs_reloc {
927 struct drm_gem_object *gobj;
4c788679
JG		 928 struct radeon_bo *robj;
929 struct radeon_bo_list lobj;
771fe6b9
JG		 930 uint32_t handle;
931 uint32_t flags;
932};
933
934struct radeon_cs_chunk {
935 uint32_t chunk_id;
936 uint32_t length_dw;
721604a1
JG		 937 int kpage_idx[2];
938 uint32_t *kpage[2];
771fe6b9 939 uint32_t *kdata;
721604a1
JG		 940 void __user *user_ptr;
941 int last_copied_page;
942 int last_page_index;
771fe6b9
JG		 943};
944
945struct radeon_cs_parser {
c8c15ff1 946 struct device *dev;
771fe6b9
JG		 947 struct radeon_device *rdev;
948 struct drm_file *filp;
949 /* chunks */
950 unsigned nchunks;
951 struct radeon_cs_chunk *chunks;
952 uint64_t *chunks_array;
953 /* IB */
954 unsigned idx;
955 /* relocations */
956 unsigned nrelocs;
957 struct radeon_cs_reloc *relocs;
958 struct radeon_cs_reloc **relocs_ptr;
959 struct list_head validated;
cf4ccd01 960 unsigned dma_reloc_idx;
771fe6b9
JG		 961 /* indices of various chunks */
962 int chunk_ib_idx;
963 int chunk_relocs_idx;
721604a1 964 int chunk_flags_idx;
dfcf5f36 965 int chunk_const_ib_idx;
f2e39221
JG		 966 struct radeon_ib ib;
967 struct radeon_ib const_ib;
771fe6b9 968 void *track;
3ce0a23d 969 unsigned family;
e70f224c 970 int parser_error;
721604a1
JG		 971 u32 cs_flags;
972 u32 ring;
973 s32 priority;
ecff665f 974 struct ww_acquire_ctx ticket;
771fe6b9
JG		 975};
976
513bcb46 977extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
ce580fab 978extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
513bcb46 979
771fe6b9
JG		 980struct radeon_cs_packet {
981 unsigned idx;
982 unsigned type;
983 unsigned reg;
984 unsigned opcode;
985 int count;
986 unsigned one_reg_wr;
987};
988
989typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
990 struct radeon_cs_packet *pkt,
991 unsigned idx, unsigned reg);
992typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
993 struct radeon_cs_packet *pkt);
994
995
996/*
997 * AGP
998 */
999int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1000void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1001void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1002void radeon_agp_fini(struct radeon_device *rdev);
1003
1004
1005/*
1006 * Writeback
1007 */
1008struct radeon_wb {
4c788679 1009 struct radeon_bo *wb_obj;
771fe6b9
JG		 1010 volatile uint32_t *wb;
1011 uint64_t gpu_addr;
724c80e1 1012 bool enabled;
d0f8a854 1013 bool use_event;
771fe6b9
JG		 1014};
1015
724c80e1 1016#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1017#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1018#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1019#define RADEON_WB_CP1_RPTR_OFFSET 1280
1020#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1021#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1022#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1023#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
f2ba57b5 1024#define R600_WB_UVD_RPTR_OFFSET 2560
d0f8a854 1025#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1026#define CIK_WB_CP1_WPTR_OFFSET 3328
1027#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1028
c93bb85b
JG		 1029/**
1030 * struct radeon_pm - power management datas
1031 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1032 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1033 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1034 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1035 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1036 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1037 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1038 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1039 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1040 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1041 * @needed_bandwidth: current bandwidth needs
1042 *
1043 * It keeps track of various data needed to take powermanagement decision.
25985edc 1044 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1045 * Equation between gpu/memory clock and available bandwidth is hw dependent
1046 * (type of memory, bus size, efficiency, ...)
1047 */
ce8f5370
AD		 1048
1049enum radeon_pm_method {
1050 PM_METHOD_PROFILE,
1051 PM_METHOD_DYNPM,
da321c8a 1052 PM_METHOD_DPM,
ce8f5370
AD		 1053};
1054
1055enum radeon_dynpm_state {
1056 DYNPM_STATE_DISABLED,
1057 DYNPM_STATE_MINIMUM,
1058 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1059 DYNPM_STATE_ACTIVE,
1060 DYNPM_STATE_SUSPENDED,
c913e23a 1061};
ce8f5370
AD		 1062enum radeon_dynpm_action {
1063 DYNPM_ACTION_NONE,
1064 DYNPM_ACTION_MINIMUM,
1065 DYNPM_ACTION_DOWNCLOCK,
1066 DYNPM_ACTION_UPCLOCK,
1067 DYNPM_ACTION_DEFAULT
c913e23a 1068};
56278a8e
AD		 1069
1070enum radeon_voltage_type {
1071 VOLTAGE_NONE = 0,
1072 VOLTAGE_GPIO,
1073 VOLTAGE_VDDC,
1074 VOLTAGE_SW
1075};
1076
0ec0e74f 1077enum radeon_pm_state_type {
da321c8a 1078 /* not used for dpm */
0ec0e74f
AD		 1079 POWER_STATE_TYPE_DEFAULT,
1080 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1081 /* user selectable states */
0ec0e74f
AD		 1082 POWER_STATE_TYPE_BATTERY,
1083 POWER_STATE_TYPE_BALANCED,
1084 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1085 /* internal states */
1086 POWER_STATE_TYPE_INTERNAL_UVD,
1087 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1088 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1089 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1090 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1091 POWER_STATE_TYPE_INTERNAL_BOOT,
1092 POWER_STATE_TYPE_INTERNAL_THERMAL,
1093 POWER_STATE_TYPE_INTERNAL_ACPI,
1094 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1095 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1096};
1097
ce8f5370
AD		 1098enum radeon_pm_profile_type {
1099 PM_PROFILE_DEFAULT,
1100 PM_PROFILE_AUTO,
1101 PM_PROFILE_LOW,
c9e75b21 1102 PM_PROFILE_MID,
ce8f5370
AD		 1103 PM_PROFILE_HIGH,
1104};
1105
1106#define PM_PROFILE_DEFAULT_IDX 0
1107#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1108#define PM_PROFILE_MID_SH_IDX 2
1109#define PM_PROFILE_HIGH_SH_IDX 3
1110#define PM_PROFILE_LOW_MH_IDX 4
1111#define PM_PROFILE_MID_MH_IDX 5
1112#define PM_PROFILE_HIGH_MH_IDX 6
1113#define PM_PROFILE_MAX 7
ce8f5370
AD		 1114
1115struct radeon_pm_profile {
1116 int dpms_off_ps_idx;
1117 int dpms_on_ps_idx;
1118 int dpms_off_cm_idx;
1119 int dpms_on_cm_idx;
516d0e46
AD		 1120};
1121
21a8122a
AD		 1122enum radeon_int_thermal_type {
1123 THERMAL_TYPE_NONE,
da321c8a
AD		 1124 THERMAL_TYPE_EXTERNAL,
1125 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1126 THERMAL_TYPE_RV6XX,
1127 THERMAL_TYPE_RV770,
da321c8a 1128 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1129 THERMAL_TYPE_EVERGREEN,
e33df25f 1130 THERMAL_TYPE_SUMO,
4fddba1f 1131 THERMAL_TYPE_NI,
14607d08 1132 THERMAL_TYPE_SI,
da321c8a 1133 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1134 THERMAL_TYPE_CI,
16fbe00d 1135 THERMAL_TYPE_KV,
21a8122a
AD		 1136};
1137
56278a8e
AD		 1138struct radeon_voltage {
1139 enum radeon_voltage_type type;
1140 /* gpio voltage */
1141 struct radeon_gpio_rec gpio;
1142 u32 delay; /* delay in usec from voltage drop to sclk change */
1143 bool active_high; /* voltage drop is active when bit is high */
1144 /* VDDC voltage */
1145 u8 vddc_id; /* index into vddc voltage table */
1146 u8 vddci_id; /* index into vddci voltage table */
1147 bool vddci_enabled;
1148 /* r6xx+ sw */
2feea49a
AD		 1149 u16 voltage;
1150 /* evergreen+ vddci */
1151 u16 vddci;
56278a8e
AD		 1152};
1153
d7311171
AD		 1154/* clock mode flags */
1155#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1156
56278a8e
AD		 1157struct radeon_pm_clock_info {
1158 /* memory clock */
1159 u32 mclk;
1160 /* engine clock */
1161 u32 sclk;
1162 /* voltage info */
1163 struct radeon_voltage voltage;
d7311171 1164 /* standardized clock flags */
56278a8e
AD		 1165 u32 flags;
1166};
1167
a48b9b4e 1168/* state flags */
d7311171 1169#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1170
56278a8e 1171struct radeon_power_state {
0ec0e74f 1172 enum radeon_pm_state_type type;
8f3f1c9a 1173 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1174 /* number of valid clock modes in this power state */
1175 int num_clock_modes;
56278a8e 1176 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1177 /* standardized state flags */
1178 u32 flags;
79daedc9
AD		 1179 u32 misc; /* vbios specific flags */
1180 u32 misc2; /* vbios specific flags */
1181 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1182};
1183
27459324
RM		 1184/*
1185 * Some modes are overclocked by very low value, accept them
1186 */
1187#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1188
2e9d4c05
AD		 1189enum radeon_dpm_auto_throttle_src {
1190 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1191 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1192};
1193
1194enum radeon_dpm_event_src {
1195 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1196 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1197 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1198 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1199 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1200};
1201
da321c8a
AD		 1202struct radeon_ps {
1203 u32 caps; /* vbios flags */
1204 u32 class; /* vbios flags */
1205 u32 class2; /* vbios flags */
1206 /* UVD clocks */
1207 u32 vclk;
1208 u32 dclk;
1209 /* asic priv */
1210 void *ps_priv;
1211};
1212
1213struct radeon_dpm_thermal {
1214 /* thermal interrupt work */
1215 struct work_struct work;
1216 /* low temperature threshold */
1217 int min_temp;
1218 /* high temperature threshold */
1219 int max_temp;
1220 /* was interrupt low to high or high to low */
1221 bool high_to_low;
1222};
1223
d22b7e40
AD		 1224enum radeon_clk_action
1225{
1226 RADEON_SCLK_UP = 1,
1227 RADEON_SCLK_DOWN
1228};
1229
1230struct radeon_blacklist_clocks
1231{
1232 u32 sclk;
1233 u32 mclk;
1234 enum radeon_clk_action action;
1235};
1236
61b7d601
AD		 1237struct radeon_clock_and_voltage_limits {
1238 u32 sclk;
1239 u32 mclk;
1240 u32 vddc;
1241 u32 vddci;
1242};
1243
1244struct radeon_clock_array {
1245 u32 count;
1246 u32 *values;
1247};
1248
1249struct radeon_clock_voltage_dependency_entry {
1250 u32 clk;
1251 u16 v;
1252};
1253
1254struct radeon_clock_voltage_dependency_table {
1255 u32 count;
1256 struct radeon_clock_voltage_dependency_entry *entries;
1257};
1258
ef976ec4
AD		 1259union radeon_cac_leakage_entry {
1260 struct {
1261 u16 vddc;
1262 u32 leakage;
1263 };
1264 struct {
1265 u16 vddc1;
1266 u16 vddc2;
1267 u16 vddc3;
1268 };
61b7d601
AD		 1269};
1270
1271struct radeon_cac_leakage_table {
1272 u32 count;
ef976ec4 1273 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1274};
1275
929ee7a8
AD		 1276struct radeon_phase_shedding_limits_entry {
1277 u16 voltage;
1278 u32 sclk;
1279 u32 mclk;
1280};
1281
1282struct radeon_phase_shedding_limits_table {
1283 u32 count;
1284 struct radeon_phase_shedding_limits_entry *entries;
1285};
1286
84a9d9ee
AD		 1287struct radeon_uvd_clock_voltage_dependency_entry {
1288 u32 vclk;
1289 u32 dclk;
1290 u16 v;
1291};
1292
1293struct radeon_uvd_clock_voltage_dependency_table {
1294 u8 count;
1295 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1296};
1297
d29f013b
AD		 1298struct radeon_vce_clock_voltage_dependency_entry {
1299 u32 ecclk;
1300 u32 evclk;
1301 u16 v;
1302};
1303
1304struct radeon_vce_clock_voltage_dependency_table {
1305 u8 count;
1306 struct radeon_vce_clock_voltage_dependency_entry *entries;
1307};
1308
a5cb318e
AD		 1309struct radeon_ppm_table {
1310 u8 ppm_design;
1311 u16 cpu_core_number;
1312 u32 platform_tdp;
1313 u32 small_ac_platform_tdp;
1314 u32 platform_tdc;
1315 u32 small_ac_platform_tdc;
1316 u32 apu_tdp;
1317 u32 dgpu_tdp;
1318 u32 dgpu_ulv_power;
1319 u32 tj_max;
1320};
1321
58cb7632
AD		 1322struct radeon_cac_tdp_table {
1323 u16 tdp;
1324 u16 configurable_tdp;
1325 u16 tdc;
1326 u16 battery_power_limit;
1327 u16 small_power_limit;
1328 u16 low_cac_leakage;
1329 u16 high_cac_leakage;
1330 u16 maximum_power_delivery_limit;
1331};
1332
61b7d601
AD		 1333struct radeon_dpm_dynamic_state {
1334 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1335 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1336 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1337 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1338 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1339 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1340 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
61b7d601
AD		 1341 struct radeon_clock_array valid_sclk_values;
1342 struct radeon_clock_array valid_mclk_values;
1343 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1344 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1345 u32 mclk_sclk_ratio;
1346 u32 sclk_mclk_delta;
1347 u16 vddc_vddci_delta;
1348 u16 min_vddc_for_pcie_gen2;
1349 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1350 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1351 struct radeon_ppm_table *ppm_table;
58cb7632 1352 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1353};
1354
1355struct radeon_dpm_fan {
1356 u16 t_min;
1357 u16 t_med;
1358 u16 t_high;
1359 u16 pwm_min;
1360 u16 pwm_med;
1361 u16 pwm_high;
1362 u8 t_hyst;
1363 u32 cycle_delay;
1364 u16 t_max;
1365 bool ucode_fan_control;
1366};
1367
32ce4652
AD		 1368enum radeon_pcie_gen {
1369 RADEON_PCIE_GEN1 = 0,
1370 RADEON_PCIE_GEN2 = 1,
1371 RADEON_PCIE_GEN3 = 2,
1372 RADEON_PCIE_GEN_INVALID = 0xffff
1373};
1374
70d01a5e
AD		 1375enum radeon_dpm_forced_level {
1376 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1377 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1378 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1379};
1380
da321c8a
AD		 1381struct radeon_dpm {
1382 struct radeon_ps *ps;
1383 /* number of valid power states */
1384 int num_ps;
1385 /* current power state that is active */
1386 struct radeon_ps *current_ps;
1387 /* requested power state */
1388 struct radeon_ps *requested_ps;
1389 /* boot up power state */
1390 struct radeon_ps *boot_ps;
1391 /* default uvd power state */
1392 struct radeon_ps *uvd_ps;
1393 enum radeon_pm_state_type state;
1394 enum radeon_pm_state_type user_state;
1395 u32 platform_caps;
1396 u32 voltage_response_time;
1397 u32 backbias_response_time;
1398 void *priv;
1399 u32 new_active_crtcs;
1400 int new_active_crtc_count;
1401 u32 current_active_crtcs;
1402 int current_active_crtc_count;
61b7d601
AD		 1403 struct radeon_dpm_dynamic_state dyn_state;
1404 struct radeon_dpm_fan fan;
1405 u32 tdp_limit;
1406 u32 near_tdp_limit;
a9e61410 1407 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1408 u32 sq_ramping_threshold;
1409 u32 cac_leakage;
1410 u16 tdp_od_limit;
1411 u32 tdp_adjustment;
1412 u16 load_line_slope;
1413 bool power_control;
5ca302f7 1414 bool ac_power;
da321c8a
AD		 1415 /* special states active */
1416 bool thermal_active;
8a227555 1417 bool uvd_active;
da321c8a
AD		 1418 /* thermal handling */
1419 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1420 /* forced levels */
1421 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1422 /* track UVD streams */
1423 unsigned sd;
1424 unsigned hd;
da321c8a
AD		 1425};
1426
ce3537d5 1427void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
da321c8a 1428
c93bb85b 1429struct radeon_pm {
c913e23a 1430 struct mutex mutex;
db7fce39
CK		 1431 /* write locked while reprogramming mclk */
1432 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1433 u32 active_crtcs;
1434 int active_crtc_count;
c913e23a 1435 int req_vblank;
839461d3 1436 bool vblank_sync;
c93bb85b
JG		 1437 fixed20_12 max_bandwidth;
1438 fixed20_12 igp_sideport_mclk;
1439 fixed20_12 igp_system_mclk;
1440 fixed20_12 igp_ht_link_clk;
1441 fixed20_12 igp_ht_link_width;
1442 fixed20_12 k8_bandwidth;
1443 fixed20_12 sideport_bandwidth;
1444 fixed20_12 ht_bandwidth;
1445 fixed20_12 core_bandwidth;
1446 fixed20_12 sclk;
f47299c5 1447 fixed20_12 mclk;
c93bb85b 1448 fixed20_12 needed_bandwidth;
0975b162 1449 struct radeon_power_state *power_state;
56278a8e
AD		 1450 /* number of valid power states */
1451 int num_power_states;
a48b9b4e
AD		 1452 int current_power_state_index;
1453 int current_clock_mode_index;
1454 int requested_power_state_index;
1455 int requested_clock_mode_index;
1456 int default_power_state_index;
1457 u32 current_sclk;
1458 u32 current_mclk;
2feea49a
AD		 1459 u16 current_vddc;
1460 u16 current_vddci;
9ace9f7b
AD		 1461 u32 default_sclk;
1462 u32 default_mclk;
2feea49a
AD		 1463 u16 default_vddc;
1464 u16 default_vddci;
29fb52ca 1465 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1466 /* selected pm method */
1467 enum radeon_pm_method pm_method;
1468 /* dynpm power management */
1469 struct delayed_work dynpm_idle_work;
1470 enum radeon_dynpm_state dynpm_state;
1471 enum radeon_dynpm_action dynpm_planned_action;
1472 unsigned long dynpm_action_timeout;
1473 bool dynpm_can_upclock;
1474 bool dynpm_can_downclock;
1475 /* profile-based power management */
1476 enum radeon_pm_profile_type profile;
1477 int profile_index;
1478 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1479 /* internal thermal controller on rv6xx+ */
1480 enum radeon_int_thermal_type int_thermal_type;
1481 struct device *int_hwmon_dev;
da321c8a
AD		 1482 /* dpm */
1483 bool dpm_enabled;
1484 struct radeon_dpm dpm;
c93bb85b
JG		 1485};
1486
a4c9e2ee
AD		 1487int radeon_pm_get_type_index(struct radeon_device *rdev,
1488 enum radeon_pm_state_type ps_type,
1489 int instance);
f2ba57b5
CK		 1490/*
1491 * UVD
1492 */
1493#define RADEON_MAX_UVD_HANDLES 10
1494#define RADEON_UVD_STACK_SIZE (1024*1024)
1495#define RADEON_UVD_HEAP_SIZE (1024*1024)
1496
1497struct radeon_uvd {
1498 struct radeon_bo *vcpu_bo;
1499 void *cpu_addr;
1500 uint64_t gpu_addr;
9cc2e0e9 1501 void *saved_bo;
f2ba57b5
CK		 1502 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1503 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1504 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1505 struct delayed_work idle_work;
f2ba57b5
CK		 1506};
1507
1508int radeon_uvd_init(struct radeon_device *rdev);
1509void radeon_uvd_fini(struct radeon_device *rdev);
1510int radeon_uvd_suspend(struct radeon_device *rdev);
1511int radeon_uvd_resume(struct radeon_device *rdev);
1512int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1513 uint32_t handle, struct radeon_fence **fence);
1514int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1515 uint32_t handle, struct radeon_fence **fence);
1516void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1517void radeon_uvd_free_handles(struct radeon_device *rdev,
1518 struct drm_file *filp);
1519int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1520void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1521int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1522 unsigned vclk, unsigned dclk,
1523 unsigned vco_min, unsigned vco_max,
1524 unsigned fb_factor, unsigned fb_mask,
1525 unsigned pd_min, unsigned pd_max,
1526 unsigned pd_even,
1527 unsigned *optimal_fb_div,
1528 unsigned *optimal_vclk_div,
1529 unsigned *optimal_dclk_div);
1530int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1531 unsigned cg_upll_func_cntl);
771fe6b9 1532
a92553ab 1533struct r600_audio {
a92553ab
RM		 1534 int channels;
1535 int rate;
1536 int bits_per_sample;
1537 u8 status_bits;
1538 u8 category_code;
1539};
1540
771fe6b9
JG		 1541/*
1542 * Benchmarking
1543 */
638dd7db 1544void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1545
1546
ecc0b326
MD		 1547/*
1548 * Testing
1549 */
1550void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1551void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1552 struct radeon_ring *cpA,
1553 struct radeon_ring *cpB);
60a7e396 1554void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1555
1556
771fe6b9
JG		 1557/*
1558 * Debugfs
1559 */
4d8bf9ae
CK		 1560struct radeon_debugfs {
1561 struct drm_info_list *files;
1562 unsigned num_files;
1563};
1564
771fe6b9
JG		 1565int radeon_debugfs_add_files(struct radeon_device *rdev,
1566 struct drm_info_list *files,
1567 unsigned nfiles);
1568int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9
JG		 1569
1570
1571/*
1572 * ASIC specific functions.
1573 */
1574struct radeon_asic {
068a117c 1575 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1576 void (*fini)(struct radeon_device *rdev);
1577 int (*resume)(struct radeon_device *rdev);
1578 int (*suspend)(struct radeon_device *rdev);
28d52043 1579 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1580 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1581 /* ioctl hw specific callback. Some hw might want to perform special
1582 * operation on specific ioctl. For instance on wait idle some hw
1583 * might want to perform and HDP flush through MMIO as it seems that
1584 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1585 * through ring.
1586 */
1587 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1588 /* check if 3D engine is idle */
1589 bool (*gui_idle)(struct radeon_device *rdev);
1590 /* wait for mc_idle */
1591 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1592 /* get the reference clock */
1593 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1594 /* get the gpu clock counter */
1595 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1596 /* gart */
c5b3b850
AD		 1597 struct {
1598 void (*tlb_flush)(struct radeon_device *rdev);
1599 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1600 } gart;
05b07147
CK		 1601 struct {
1602 int (*init)(struct radeon_device *rdev);
1603 void (*fini)(struct radeon_device *rdev);
2a6f1abb
CK		 1604
1605 u32 pt_ring_index;
43f1214a
AD		 1606 void (*set_page)(struct radeon_device *rdev,
1607 struct radeon_ib *ib,
1608 uint64_t pe,
dce34bfd
CK		 1609 uint64_t addr, unsigned count,
1610 uint32_t incr, uint32_t flags);
05b07147 1611 } vm;
54e88e06 1612 /* ring specific callbacks */
4c87bc26
CK		 1613 struct {
1614 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
721604a1 1615 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
4c87bc26 1616 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
e32eb50d 1617 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
4c87bc26 1618 struct radeon_semaphore *semaphore, bool emit_wait);
eb0c19c5 1619 int (*cs_parse)(struct radeon_cs_parser *p);
f712812e
AD		 1620 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1621 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1622 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
312c4a8c 1623 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
498522b4 1624 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
f93bdefe
AD		 1625
1626 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1627 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1628 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
4c87bc26 1629 } ring[RADEON_NUM_RINGS];
54e88e06 1630 /* irqs */
b35ea4ab
AD		 1631 struct {
1632 int (*set)(struct radeon_device *rdev);
1633 int (*process)(struct radeon_device *rdev);
1634 } irq;
54e88e06 1635 /* displays */
c79a49ca
AD		 1636 struct {
1637 /* display watermarks */
1638 void (*bandwidth_update)(struct radeon_device *rdev);
1639 /* get frame count */
1640 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1641 /* wait for vblank */
1642 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1643 /* set backlight level */
1644 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1645 /* get backlight level */
1646 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1647 /* audio callbacks */
1648 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1649 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1650 } display;
54e88e06 1651 /* copy functions for bo handling */
27cd7769
AD		 1652 struct {
1653 int (*blit)(struct radeon_device *rdev,
1654 uint64_t src_offset,
1655 uint64_t dst_offset,
1656 unsigned num_gpu_pages,
876dc9f3 1657 struct radeon_fence **fence);
27cd7769
AD		 1658 u32 blit_ring_index;
1659 int (*dma)(struct radeon_device *rdev,
1660 uint64_t src_offset,
1661 uint64_t dst_offset,
1662 unsigned num_gpu_pages,
876dc9f3 1663 struct radeon_fence **fence);
27cd7769
AD		 1664 u32 dma_ring_index;
1665 /* method used for bo copy */
1666 int (*copy)(struct radeon_device *rdev,
1667 uint64_t src_offset,
1668 uint64_t dst_offset,
1669 unsigned num_gpu_pages,
876dc9f3 1670 struct radeon_fence **fence);
27cd7769
AD		 1671 /* ring used for bo copies */
1672 u32 copy_ring_index;
1673 } copy;
54e88e06 1674 /* surfaces */
9e6f3d02
AD		 1675 struct {
1676 int (*set_reg)(struct radeon_device *rdev, int reg,
1677 uint32_t tiling_flags, uint32_t pitch,
1678 uint32_t offset, uint32_t obj_size);
1679 void (*clear_reg)(struct radeon_device *rdev, int reg);
1680 } surface;
54e88e06 1681 /* hotplug detect */
901ea57d
AD		 1682 struct {
1683 void (*init)(struct radeon_device *rdev);
1684 void (*fini)(struct radeon_device *rdev);
1685 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1686 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1687 } hpd;
da321c8a 1688 /* static power management */
a02fa397
AD		 1689 struct {
1690 void (*misc)(struct radeon_device *rdev);
1691 void (*prepare)(struct radeon_device *rdev);
1692 void (*finish)(struct radeon_device *rdev);
1693 void (*init_profile)(struct radeon_device *rdev);
1694 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1695 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1696 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1697 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1698 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1699 int (*get_pcie_lanes)(struct radeon_device *rdev);
1700 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1701 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1702 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1703 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1704 } pm;
da321c8a
AD		 1705 /* dynamic power management */
1706 struct {
1707 int (*init)(struct radeon_device *rdev);
1708 void (*setup_asic)(struct radeon_device *rdev);
1709 int (*enable)(struct radeon_device *rdev);
1710 void (*disable)(struct radeon_device *rdev);
84dd1928 1711 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1712 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1713 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1714 void (*display_configuration_changed)(struct radeon_device *rdev);
1715 void (*fini)(struct radeon_device *rdev);
1716 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1717 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1718 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1719 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1720 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1721 bool (*vblank_too_short)(struct radeon_device *rdev);
da321c8a 1722 } dpm;
6f34be50 1723 /* pageflipping */
0f9e006c
AD		 1724 struct {
1725 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1726 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1727 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1728 } pflip;
771fe6b9
JG		 1729};
1730
21f9a437
JG		 1731/*
1732 * Asic structures
1733 */
551ebd83 1734struct r100_asic {
225758d8
JG		 1735 const unsigned *reg_safe_bm;
1736 unsigned reg_safe_bm_size;
1737 u32 hdp_cntl;
551ebd83
DA		 1738};
1739
21f9a437 1740struct r300_asic {
225758d8
JG		 1741 const unsigned *reg_safe_bm;
1742 unsigned reg_safe_bm_size;
1743 u32 resync_scratch;
1744 u32 hdp_cntl;
21f9a437
JG		 1745};
1746
1747struct r600_asic {
225758d8
JG		 1748 unsigned max_pipes;
1749 unsigned max_tile_pipes;
1750 unsigned max_simds;
1751 unsigned max_backends;
1752 unsigned max_gprs;
1753 unsigned max_threads;
1754 unsigned max_stack_entries;
1755 unsigned max_hw_contexts;
1756 unsigned max_gs_threads;
1757 unsigned sx_max_export_size;
1758 unsigned sx_max_export_pos_size;
1759 unsigned sx_max_export_smx_size;
1760 unsigned sq_num_cf_insts;
1761 unsigned tiling_nbanks;
1762 unsigned tiling_npipes;
1763 unsigned tiling_group_size;
e7aeeba6 1764 unsigned tile_config;
e55b9422 1765 unsigned backend_map;
21f9a437
JG		 1766};
1767
1768struct rv770_asic {
225758d8
JG		 1769 unsigned max_pipes;
1770 unsigned max_tile_pipes;
1771 unsigned max_simds;
1772 unsigned max_backends;
1773 unsigned max_gprs;
1774 unsigned max_threads;
1775 unsigned max_stack_entries;
1776 unsigned max_hw_contexts;
1777 unsigned max_gs_threads;
1778 unsigned sx_max_export_size;
1779 unsigned sx_max_export_pos_size;
1780 unsigned sx_max_export_smx_size;
1781 unsigned sq_num_cf_insts;
1782 unsigned sx_num_of_sets;
1783 unsigned sc_prim_fifo_size;
1784 unsigned sc_hiz_tile_fifo_size;
1785 unsigned sc_earlyz_tile_fifo_fize;
1786 unsigned tiling_nbanks;
1787 unsigned tiling_npipes;
1788 unsigned tiling_group_size;
e7aeeba6 1789 unsigned tile_config;
e55b9422 1790 unsigned backend_map;
21f9a437
JG		 1791};
1792
32fcdbf4
AD		 1793struct evergreen_asic {
1794 unsigned num_ses;
1795 unsigned max_pipes;
1796 unsigned max_tile_pipes;
1797 unsigned max_simds;
1798 unsigned max_backends;
1799 unsigned max_gprs;
1800 unsigned max_threads;
1801 unsigned max_stack_entries;
1802 unsigned max_hw_contexts;
1803 unsigned max_gs_threads;
1804 unsigned sx_max_export_size;
1805 unsigned sx_max_export_pos_size;
1806 unsigned sx_max_export_smx_size;
1807 unsigned sq_num_cf_insts;
1808 unsigned sx_num_of_sets;
1809 unsigned sc_prim_fifo_size;
1810 unsigned sc_hiz_tile_fifo_size;
1811 unsigned sc_earlyz_tile_fifo_size;
1812 unsigned tiling_nbanks;
1813 unsigned tiling_npipes;
1814 unsigned tiling_group_size;
e7aeeba6 1815 unsigned tile_config;
e55b9422 1816 unsigned backend_map;
32fcdbf4
AD		 1817};
1818
fecf1d07
AD		 1819struct cayman_asic {
1820 unsigned max_shader_engines;
1821 unsigned max_pipes_per_simd;
1822 unsigned max_tile_pipes;
1823 unsigned max_simds_per_se;
1824 unsigned max_backends_per_se;
1825 unsigned max_texture_channel_caches;
1826 unsigned max_gprs;
1827 unsigned max_threads;
1828 unsigned max_gs_threads;
1829 unsigned max_stack_entries;
1830 unsigned sx_num_of_sets;
1831 unsigned sx_max_export_size;
1832 unsigned sx_max_export_pos_size;
1833 unsigned sx_max_export_smx_size;
1834 unsigned max_hw_contexts;
1835 unsigned sq_num_cf_insts;
1836 unsigned sc_prim_fifo_size;
1837 unsigned sc_hiz_tile_fifo_size;
1838 unsigned sc_earlyz_tile_fifo_size;
1839
1840 unsigned num_shader_engines;
1841 unsigned num_shader_pipes_per_simd;
1842 unsigned num_tile_pipes;
1843 unsigned num_simds_per_se;
1844 unsigned num_backends_per_se;
1845 unsigned backend_disable_mask_per_asic;
1846 unsigned backend_map;
1847 unsigned num_texture_channel_caches;
1848 unsigned mem_max_burst_length_bytes;
1849 unsigned mem_row_size_in_kb;
1850 unsigned shader_engine_tile_size;
1851 unsigned num_gpus;
1852 unsigned multi_gpu_tile_size;
1853
1854 unsigned tile_config;
fecf1d07
AD		 1855};
1856
0a96d72b
AD		 1857struct si_asic {
1858 unsigned max_shader_engines;
0a96d72b 1859 unsigned max_tile_pipes;
1a8ca750
AD		 1860 unsigned max_cu_per_sh;
1861 unsigned max_sh_per_se;
0a96d72b
AD		 1862 unsigned max_backends_per_se;
1863 unsigned max_texture_channel_caches;
1864 unsigned max_gprs;
1865 unsigned max_gs_threads;
1866 unsigned max_hw_contexts;
1867 unsigned sc_prim_fifo_size_frontend;
1868 unsigned sc_prim_fifo_size_backend;
1869 unsigned sc_hiz_tile_fifo_size;
1870 unsigned sc_earlyz_tile_fifo_size;
1871
0a96d72b
AD		 1872 unsigned num_tile_pipes;
1873 unsigned num_backends_per_se;
1874 unsigned backend_disable_mask_per_asic;
1875 unsigned backend_map;
1876 unsigned num_texture_channel_caches;
1877 unsigned mem_max_burst_length_bytes;
1878 unsigned mem_row_size_in_kb;
1879 unsigned shader_engine_tile_size;
1880 unsigned num_gpus;
1881 unsigned multi_gpu_tile_size;
1882
1883 unsigned tile_config;
64d7b8be 1884 uint32_t tile_mode_array[32];
0a96d72b
AD		 1885};
1886
8cc1a532
AD		 1887struct cik_asic {
1888 unsigned max_shader_engines;
1889 unsigned max_tile_pipes;
1890 unsigned max_cu_per_sh;
1891 unsigned max_sh_per_se;
1892 unsigned max_backends_per_se;
1893 unsigned max_texture_channel_caches;
1894 unsigned max_gprs;
1895 unsigned max_gs_threads;
1896 unsigned max_hw_contexts;
1897 unsigned sc_prim_fifo_size_frontend;
1898 unsigned sc_prim_fifo_size_backend;
1899 unsigned sc_hiz_tile_fifo_size;
1900 unsigned sc_earlyz_tile_fifo_size;
1901
1902 unsigned num_tile_pipes;
1903 unsigned num_backends_per_se;
1904 unsigned backend_disable_mask_per_asic;
1905 unsigned backend_map;
1906 unsigned num_texture_channel_caches;
1907 unsigned mem_max_burst_length_bytes;
1908 unsigned mem_row_size_in_kb;
1909 unsigned shader_engine_tile_size;
1910 unsigned num_gpus;
1911 unsigned multi_gpu_tile_size;
1912
1913 unsigned tile_config;
39aee490 1914 uint32_t tile_mode_array[32];
8cc1a532
AD		 1915};
1916
068a117c
JG		 1917union radeon_asic_config {
1918 struct r300_asic r300;
551ebd83 1919 struct r100_asic r100;
3ce0a23d
JG		 1920 struct r600_asic r600;
1921 struct rv770_asic rv770;
32fcdbf4 1922 struct evergreen_asic evergreen;
fecf1d07 1923 struct cayman_asic cayman;
0a96d72b 1924 struct si_asic si;
8cc1a532 1925 struct cik_asic cik;
068a117c
JG		 1926};
1927
0a10c851
DV		 1928/*
1929 * asic initizalization from radeon_asic.c
1930 */
1931void radeon_agp_disable(struct radeon_device *rdev);
1932int radeon_asic_init(struct radeon_device *rdev);
1933
771fe6b9
JG		 1934
1935/*
1936 * IOCTL.
1937 */
1938int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1939 struct drm_file *filp);
1940int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1941 struct drm_file *filp);
1942int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1943 struct drm_file *file_priv);
1944int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1945 struct drm_file *file_priv);
1946int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1947 struct drm_file *file_priv);
1948int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1949 struct drm_file *file_priv);
1950int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1951 struct drm_file *filp);
1952int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1953 struct drm_file *filp);
1954int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1955 struct drm_file *filp);
1956int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1957 struct drm_file *filp);
721604a1
JG		 1958int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1959 struct drm_file *filp);
771fe6b9 1960int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1961int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1962 struct drm_file *filp);
1963int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1964 struct drm_file *filp);
771fe6b9 1965
16cdf04d
AD		 1966/* VRAM scratch page for HDP bug, default vram page */
1967struct r600_vram_scratch {
87cbf8f2
AD		 1968 struct radeon_bo *robj;
1969 volatile uint32_t *ptr;
16cdf04d 1970 u64 gpu_addr;
87cbf8f2 1971};
771fe6b9 1972
fd64ca8a
LT		 1973/*
1974 * ACPI
1975 */
1976struct radeon_atif_notification_cfg {
1977 bool enabled;
1978 int command_code;
1979};
1980
1981struct radeon_atif_notifications {
1982 bool display_switch;
1983 bool expansion_mode_change;
1984 bool thermal_state;
1985 bool forced_power_state;
1986 bool system_power_state;
1987 bool display_conf_change;
1988 bool px_gfx_switch;
1989 bool brightness_change;
1990 bool dgpu_display_event;
1991};
1992
1993struct radeon_atif_functions {
1994 bool system_params;
1995 bool sbios_requests;
1996 bool select_active_disp;
1997 bool lid_state;
1998 bool get_tv_standard;
1999 bool set_tv_standard;
2000 bool get_panel_expansion_mode;
2001 bool set_panel_expansion_mode;
2002 bool temperature_change;
2003 bool graphics_device_types;
2004};
2005
2006struct radeon_atif {
2007 struct radeon_atif_notifications notifications;
2008 struct radeon_atif_functions functions;
2009 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2010 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2011};
7a1619b9 2012
e3a15920
AD		 2013struct radeon_atcs_functions {
2014 bool get_ext_state;
2015 bool pcie_perf_req;
2016 bool pcie_dev_rdy;
2017 bool pcie_bus_width;
2018};
2019
2020struct radeon_atcs {
2021 struct radeon_atcs_functions functions;
2022};
2023
771fe6b9
JG		 2024/*
2025 * Core structure, functions and helpers.
2026 */
2027typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2028typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2029
2030struct radeon_device {
9f022ddf 2031 struct device *dev;
771fe6b9
JG		 2032 struct drm_device *ddev;
2033 struct pci_dev *pdev;
dee53e7f 2034 struct rw_semaphore exclusive_lock;
771fe6b9 2035 /* ASIC */
068a117c 2036 union radeon_asic_config config;
771fe6b9
JG		 2037 enum radeon_family family;
2038 unsigned long flags;
2039 int usec_timeout;
2040 enum radeon_pll_errata pll_errata;
2041 int num_gb_pipes;
f779b3e5 2042 int num_z_pipes;
771fe6b9
JG		 2043 int disp_priority;
2044 /* BIOS */
2045 uint8_t *bios;
2046 bool is_atom_bios;
2047 uint16_t bios_header_start;
4c788679 2048 struct radeon_bo *stollen_vga_memory;
771fe6b9 2049 /* Register mmio */
4c9bc75c
DA		 2050 resource_size_t rmmio_base;
2051 resource_size_t rmmio_size;
2c385151
DV		 2052 /* protects concurrent MM_INDEX/DATA based register access */
2053 spinlock_t mmio_idx_lock;
a0533fbf 2054 void __iomem *rmmio;
771fe6b9
JG		 2055 radeon_rreg_t mc_rreg;
2056 radeon_wreg_t mc_wreg;
2057 radeon_rreg_t pll_rreg;
2058 radeon_wreg_t pll_wreg;
de1b2898 2059 uint32_t pcie_reg_mask;
771fe6b9
JG		 2060 radeon_rreg_t pciep_rreg;
2061 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2062 /* io port */
2063 void __iomem *rio_mem;
2064 resource_size_t rio_mem_size;
771fe6b9
JG		 2065 struct radeon_clock clock;
2066 struct radeon_mc mc;
2067 struct radeon_gart gart;
2068 struct radeon_mode_info mode_info;
2069 struct radeon_scratch scratch;
75efdee1 2070 struct radeon_doorbell doorbell;
771fe6b9 2071 struct radeon_mman mman;
7465280c 2072 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2073 wait_queue_head_t fence_queue;
d6999bc7 2074 struct mutex ring_lock;
e32eb50d 2075 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2076 bool ib_pool_ready;
2077 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2078 struct radeon_irq irq;
2079 struct radeon_asic *asic;
2080 struct radeon_gem gem;
c93bb85b 2081 struct radeon_pm pm;
f2ba57b5 2082 struct radeon_uvd uvd;
f657c2a7 2083 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2084 struct radeon_wb wb;
3ce0a23d 2085 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2086 bool shutdown;
2087 bool suspend;
ad49f501 2088 bool need_dma32;
733289c2 2089 bool accel_working;
a0a53aa8 2090 bool fastfb_working; /* IGP feature*/
e024e110 2091 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2092 const struct firmware *me_fw; /* all family ME firmware */
2093 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2094 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2095 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2096 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2097 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2098 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2099 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2100 const struct firmware *uvd_fw; /* UVD firmware */
16cdf04d 2101 struct r600_vram_scratch vram_scratch;
3e5cb98d 2102 int msi_enabled; /* msi enabled */
d8f60cfc 2103 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2104 struct radeon_rlc rlc;
963e81f9 2105 struct radeon_mec mec;
d4877cf2 2106 struct work_struct hotplug_work;
f122c610 2107 struct work_struct audio_work;
8f61b34c 2108 struct work_struct reset_work;
18917b60 2109 int num_crtc; /* number of crtcs */
40bacf16 2110 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
3299de95 2111 bool audio_enabled;
948bee3f 2112 bool has_uvd;
3299de95 2113 struct r600_audio audio_status; /* audio stuff */
ce8f5370 2114 struct notifier_block acpi_nb;
9eba4a93 2115 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2116 struct drm_file *hyperz_filp;
9eba4a93 2117 struct drm_file *cmask_filp;
f376b94f
AD		 2118 /* i2c buses */
2119 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2120 /* debugfs */
2121 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2122 unsigned debugfs_count;
721604a1
JG		 2123 /* virtual memory */
2124 struct radeon_vm_manager vm_manager;
6759a0a7 2125 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2126 /* ACPI interface */
2127 struct radeon_atif atif;
e3a15920 2128 struct radeon_atcs atcs;
f61d5b46
AD		 2129 /* srbm instance registers */
2130 struct mutex srbm_mutex;
771fe6b9
JG		 2131};
2132
2133int radeon_device_init(struct radeon_device *rdev,
2134 struct drm_device *ddev,
2135 struct pci_dev *pdev,
2136 uint32_t flags);
2137void radeon_device_fini(struct radeon_device *rdev);
2138int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2139
2ef9bdfe
DV		 2140uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2141 bool always_indirect);
2142void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2143 bool always_indirect);
6fcbef7a
AK		 2144u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2145void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2146
75efdee1
AD		 2147u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2148void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2149
4c788679
JG		 2150/*
2151 * Cast helper
2152 */
2153#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2154
2155/*
2156 * Registers read & write functions.
2157 */
a0533fbf
BH		 2158#define RREG8(reg) readb((rdev->rmmio) + (reg))
2159#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2160#define RREG16(reg) readw((rdev->rmmio) + (reg))
2161#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2162#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2163#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2164#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2165#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2166#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2167#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2168#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2169#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2170#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2171#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2172#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2173#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2174#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2175#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2176#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2177#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2178#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2179#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2180#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2181#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2182#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2183#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2184#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2185#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2186#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2187#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2188#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2189#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2190#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2191#define WREG32_P(reg, val, mask) \
2192 do { \
2193 uint32_t tmp_ = RREG32(reg); \
2194 tmp_ &= (mask); \
2195 tmp_ |= ((val) & ~(mask)); \
2196 WREG32(reg, tmp_); \
2197 } while (0)
d5169fc4 2198#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2199#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2200#define WREG32_PLL_P(reg, val, mask) \
2201 do { \
2202 uint32_t tmp_ = RREG32_PLL(reg); \
2203 tmp_ &= (mask); \
2204 tmp_ |= ((val) & ~(mask)); \
2205 WREG32_PLL(reg, tmp_); \
2206 } while (0)
2ef9bdfe 2207#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2208#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2209#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2210
75efdee1
AD		 2211#define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2212#define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2213
de1b2898
DA		 2214/*
2215 * Indirect registers accessor
2216 */
2217static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2218{
2219 uint32_t r;
2220
2221 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2222 r = RREG32(RADEON_PCIE_DATA);
2223 return r;
2224}
2225
2226static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2227{
2228 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2229 WREG32(RADEON_PCIE_DATA, (v));
2230}
2231
1d5d0c34
AD		 2232static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2233{
2234 u32 r;
2235
2236 WREG32(TN_SMC_IND_INDEX_0, (reg));
2237 r = RREG32(TN_SMC_IND_DATA_0);
2238 return r;
2239}
2240
2241static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2242{
2243 WREG32(TN_SMC_IND_INDEX_0, (reg));
2244 WREG32(TN_SMC_IND_DATA_0, (v));
2245}
2246
ff82bbc4
AD		 2247static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2248{
2249 u32 r;
2250
2251 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2252 r = RREG32(R600_RCU_DATA);
2253 return r;
2254}
2255
2256static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2257{
2258 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2259 WREG32(R600_RCU_DATA, (v));
2260}
2261
46f9564a
AD		 2262static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2263{
2264 u32 r;
2265
2266 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2267 r = RREG32(EVERGREEN_CG_IND_DATA);
2268 return r;
2269}
2270
2271static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2272{
2273 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2274 WREG32(EVERGREEN_CG_IND_DATA, (v));
2275}
2276
792edd69
AD		 2277static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2278{
2279 u32 r;
2280
2281 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2282 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2283 return r;
2284}
2285
2286static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2287{
2288 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2289 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2290}
2291
2292static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2293{
2294 u32 r;
2295
2296 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2297 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2298 return r;
2299}
2300
2301static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2302{
2303 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2304 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2305}
2306
93656cdd
AD		 2307static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2308{
2309 u32 r;
2310
2311 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2312 r = RREG32(R600_UVD_CTX_DATA);
2313 return r;
2314}
2315
2316static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2317{
2318 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2319 WREG32(R600_UVD_CTX_DATA, (v));
2320}
2321
1d58234d
AD		 2322
2323static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2324{
2325 u32 r;
2326
2327 WREG32(CIK_DIDT_IND_INDEX, (reg));
2328 r = RREG32(CIK_DIDT_IND_DATA);
2329 return r;
2330}
2331
2332static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2333{
2334 WREG32(CIK_DIDT_IND_INDEX, (reg));
2335 WREG32(CIK_DIDT_IND_DATA, (v));
2336}
2337
771fe6b9
JG		 2338void r100_pll_errata_after_index(struct radeon_device *rdev);
2339
2340
2341/*
2342 * ASICs helpers.
2343 */
b995e433
DA		 2344#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2345 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2346#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2347 (rdev->family == CHIP_RV200) || \
2348 (rdev->family == CHIP_RS100) || \
2349 (rdev->family == CHIP_RS200) || \
2350 (rdev->family == CHIP_RV250) || \
2351 (rdev->family == CHIP_RV280) || \
2352 (rdev->family == CHIP_RS300))
2353#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2354 (rdev->family == CHIP_RV350) || \
2355 (rdev->family == CHIP_R350) || \
2356 (rdev->family == CHIP_RV380) || \
2357 (rdev->family == CHIP_R420) || \
2358 (rdev->family == CHIP_R423) || \
2359 (rdev->family == CHIP_RV410) || \
2360 (rdev->family == CHIP_RS400) || \
2361 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2362#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2363 (rdev->ddev->pdev->device == 0x9443) || \
2364 (rdev->ddev->pdev->device == 0x944B) || \
2365 (rdev->ddev->pdev->device == 0x9506) || \
2366 (rdev->ddev->pdev->device == 0x9509) || \
2367 (rdev->ddev->pdev->device == 0x950F) || \
2368 (rdev->ddev->pdev->device == 0x689C) || \
2369 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2370#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2371#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2372 (rdev->family == CHIP_RS690) || \
2373 (rdev->family == CHIP_RS740) || \
2374 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2375#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2376#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2377#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2378#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2379 (rdev->flags & RADEON_IS_IGP))
1fe18305 2380#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2381#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2382#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2383 (rdev->flags & RADEON_IS_IGP))
624d3524 2384#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2385#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2386#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2387
dc50ba7f
AD		 2388#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2389 (rdev->ddev->pdev->device == 0x6850) || \
2390 (rdev->ddev->pdev->device == 0x6858) || \
2391 (rdev->ddev->pdev->device == 0x6859) || \
2392 (rdev->ddev->pdev->device == 0x6840) || \
2393 (rdev->ddev->pdev->device == 0x6841) || \
2394 (rdev->ddev->pdev->device == 0x6842) || \
2395 (rdev->ddev->pdev->device == 0x6843))
2396
771fe6b9
JG		 2397/*
2398 * BIOS helpers.
2399 */
2400#define RBIOS8(i) (rdev->bios[i])
2401#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2402#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2403
2404int radeon_combios_init(struct radeon_device *rdev);
2405void radeon_combios_fini(struct radeon_device *rdev);
2406int radeon_atombios_init(struct radeon_device *rdev);
2407void radeon_atombios_fini(struct radeon_device *rdev);
2408
2409
2410/*
2411 * RING helpers.
2412 */
ce580fab 2413#if DRM_DEBUG_CODE == 0
e32eb50d 2414static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2415{
e32eb50d
CK		 2416 ring->ring[ring->wptr++] = v;
2417 ring->wptr &= ring->ptr_mask;
2418 ring->count_dw--;
2419 ring->ring_free_dw--;
771fe6b9 2420}
ce580fab
AK		 2421#else
2422/* With debugging this is just too big to inline */
e32eb50d 2423void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2424#endif
771fe6b9
JG		 2425
2426/*
2427 * ASICs macro.
2428 */
068a117c 2429#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2430#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2431#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2432#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
eb0c19c5 2433#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
28d52043 2434#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2435#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2436#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2437#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2438#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2439#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2440#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
f712812e
AD		 2441#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2442#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2443#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
4c87bc26 2444#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
721604a1 2445#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
312c4a8c 2446#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
498522b4 2447#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
f93bdefe
AD		 2448#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2449#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2450#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
b35ea4ab
AD		 2451#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2452#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2453#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2454#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2455#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2456#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2457#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
4c87bc26
CK		 2458#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2459#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2460#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2461#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2462#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2463#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2464#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2465#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2466#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2467#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2468#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2469#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2470#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2471#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2472#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2473#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2474#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2475#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2476#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2477#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2478#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2479#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2480#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2481#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2482#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2483#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2484#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2485#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2486#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2487#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2488#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2489#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2490#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2491#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2492#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2493#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2494#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2495#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2496#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2497#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2498#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2499#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2500#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2501#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2502#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2503#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2504#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2505#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2506#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2507#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2508#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2509#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
771fe6b9 2510
6cf8a3f5 2511/* Common functions */
700a0cc0 2512/* AGP */
90aca4d2 2513extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2514extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2515extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2516extern int radeon_modeset_init(struct radeon_device *rdev);
2517extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2518extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2519extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2520extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2521extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2522extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2523extern void radeon_wb_fini(struct radeon_device *rdev);
2524extern int radeon_wb_init(struct radeon_device *rdev);
2525extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2526extern void radeon_surface_init(struct radeon_device *rdev);
2527extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2528extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2529extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2530extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2531extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2532extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2533extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 2534extern int radeon_resume_kms(struct drm_device *dev);
2535extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
53595338 2536extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2537extern void radeon_program_register_sequence(struct radeon_device *rdev,
2538 const u32 *registers,
2539 const u32 array_size);
6cf8a3f5 2540
721604a1
JG		 2541/*
2542 * vm
2543 */
2544int radeon_vm_manager_init(struct radeon_device *rdev);
2545void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2546void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2547void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2548int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2549void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2550struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2551 struct radeon_vm *vm, int ring);
2552void radeon_vm_fence(struct radeon_device *rdev,
2553 struct radeon_vm *vm,
2554 struct radeon_fence *fence);
dce34bfd 2555uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
721604a1
JG		 2556int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2557 struct radeon_vm *vm,
2558 struct radeon_bo *bo,
2559 struct ttm_mem_reg *mem);
2560void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2561 struct radeon_bo *bo);
421ca7ab
CK		 2562struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2563 struct radeon_bo *bo);
e971bd5e
CK		 2564struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2565 struct radeon_vm *vm,
2566 struct radeon_bo *bo);
2567int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2568 struct radeon_bo_va *bo_va,
2569 uint64_t offset,
2570 uint32_t flags);
721604a1 2571int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2572 struct radeon_bo_va *bo_va);
721604a1 2573
f122c610
AD		 2574/* audio */
2575void r600_audio_update_hdmi(struct work_struct *work);
721604a1 2576
16cdf04d
AD		 2577/*
2578 * R600 vram scratch functions
2579 */
2580int r600_vram_scratch_init(struct radeon_device *rdev);
2581void r600_vram_scratch_fini(struct radeon_device *rdev);
2582
285484e2
JG		 2583/*
2584 * r600 cs checking helper
2585 */
2586unsigned r600_mip_minify(unsigned size, unsigned level);
2587bool r600_fmt_is_valid_color(u32 format);
2588bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2589int r600_fmt_get_blocksize(u32 format);
2590int r600_fmt_get_nblocksx(u32 format, u32 w);
2591int r600_fmt_get_nblocksy(u32 format, u32 h);
2592
3574dda4
DV		 2593/*
2594 * r600 functions used by radeon_encoder.c
2595 */
1b688d08
RM		 2596struct radeon_hdmi_acr {
2597 u32 clock;
2598
2599 int n_32khz;
2600 int cts_32khz;
2601
2602 int n_44_1khz;
2603 int cts_44_1khz;
2604
2605 int n_48khz;
2606 int cts_48khz;
2607
2608};
2609
e55d3e6c
RM		 2610extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2611
416a2bd2
AD		 2612extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2613 u32 tiling_pipe_num,
2614 u32 max_rb_num,
2615 u32 total_max_rb_num,
2616 u32 enabled_rb_mask);
fe251e2f 2617
e55d3e6c
RM		 2618/*
2619 * evergreen functions used by radeon_encoder.c
2620 */
2621
0af62b01 2622extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2623extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2624
c4917074
AD		 2625/* radeon_acpi.c */
2626#if defined(CONFIG_ACPI)
2627extern int radeon_acpi_init(struct radeon_device *rdev);
2628extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2629extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2630extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2631 u8 perf_req, bool advertise);
dc50ba7f 2632extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2633#else
2634static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2635static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2636#endif
d7a2952f 2637
c38f34b5
IH		 2638int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2639 struct radeon_cs_packet *pkt,
2640 unsigned idx);
9ffb7a6d 2641bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2642void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2643 struct radeon_cs_packet *pkt);
e9716993
IH		 2644int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2645 struct radeon_cs_reloc **cs_reloc,
2646 int nomm);
40592a17
IH		 2647int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2648 uint32_t *vline_start_end,
2649 uint32_t *vline_status);
c38f34b5 2650
4c788679
JG		 2651#include "radeon_object.h"
2652
771fe6b9 2653#endif
Linux 6.x block layer and io_uring tree(s)