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drm/radeon/dpm: fill in some initial vce infrastructure
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
363eb0b4 102extern int radeon_hard_reset;
771fe6b9
JG		 103
104/*
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 * symbol;
107 */
bb635567
JG		 108#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 110/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 111#define RADEON_IB_POOL_SIZE 16
112#define RADEON_DEBUGFS_MAX_COMPONENTS 32
113#define RADEONFB_CONN_LIMIT 4
114#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 115
bb635567
JG		 116/* fence seq are set to this number when signaled */
117#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 118
119/* internal ring indices */
120/* r1xx+ has gfx CP ring */
d93f7937 121#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 122
123/* cayman has 2 compute CP rings */
d93f7937
CK		 124#define CAYMAN_RING_TYPE_CP1_INDEX 1
125#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 126
4d75658b
AD		 127/* R600+ has an async dma ring */
128#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 129/* cayman add a second async dma ring */
130#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 131
f2ba57b5 132/* R600+ */
d93f7937
CK		 133#define R600_RING_TYPE_UVD_INDEX 5
134
135/* TN+ */
136#define TN_RING_TYPE_VCE1_INDEX 6
137#define TN_RING_TYPE_VCE2_INDEX 7
138
139/* max number of rings */
140#define RADEON_NUM_RINGS 8
f2ba57b5 141
1c61eae4
CK		 142/* number of hw syncs before falling back on blocking */
143#define RADEON_NUM_SYNCS 4
144
721604a1 145/* hardcode those limit for now */
ca19f21e 146#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 147#define RADEON_VA_RESERVED_SIZE (8 << 20)
148#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 149
1a0041b8
AD		 150/* hard reset data */
151#define RADEON_ASIC_RESET_DATA 0x39d5e86b
152
ec46c76d
AD		 153/* reset flags */
154#define RADEON_RESET_GFX (1 << 0)
155#define RADEON_RESET_COMPUTE (1 << 1)
156#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 157#define RADEON_RESET_CP (1 << 3)
158#define RADEON_RESET_GRBM (1 << 4)
159#define RADEON_RESET_DMA1 (1 << 5)
160#define RADEON_RESET_RLC (1 << 6)
161#define RADEON_RESET_SEM (1 << 7)
162#define RADEON_RESET_IH (1 << 8)
163#define RADEON_RESET_VMC (1 << 9)
164#define RADEON_RESET_MC (1 << 10)
165#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 166
22c775ce
AD		 167/* CG block flags */
168#define RADEON_CG_BLOCK_GFX (1 << 0)
169#define RADEON_CG_BLOCK_MC (1 << 1)
170#define RADEON_CG_BLOCK_SDMA (1 << 2)
171#define RADEON_CG_BLOCK_UVD (1 << 3)
172#define RADEON_CG_BLOCK_VCE (1 << 4)
173#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 174#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 175
64d8a728
AD		 176/* CG flags */
177#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
178#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
179#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
180#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
181#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
182#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
183#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
184#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
185#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
186#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
187#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
188#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
189#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
190#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
191#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
192#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
193#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
194
195/* PG flags */
2b19d17f 196#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 197#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
198#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
199#define RADEON_PG_SUPPORT_UVD (1 << 3)
200#define RADEON_PG_SUPPORT_VCE (1 << 4)
201#define RADEON_PG_SUPPORT_CP (1 << 5)
202#define RADEON_PG_SUPPORT_GDS (1 << 6)
203#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
204#define RADEON_PG_SUPPORT_SDMA (1 << 8)
205#define RADEON_PG_SUPPORT_ACP (1 << 9)
206#define RADEON_PG_SUPPORT_SAMU (1 << 10)
207
9e05fa1d
AD		 208/* max cursor sizes (in pixels) */
209#define CURSOR_WIDTH 64
210#define CURSOR_HEIGHT 64
211
212#define CIK_CURSOR_WIDTH 128
213#define CIK_CURSOR_HEIGHT 128
214
771fe6b9
JG		 215/*
216 * Errata workarounds.
217 */
218enum radeon_pll_errata {
219 CHIP_ERRATA_R300_CG = 0x00000001,
220 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
221 CHIP_ERRATA_PLL_DELAY = 0x00000004
222};
223
224
225struct radeon_device;
226
227
228/*
229 * BIOS.
230 */
231bool radeon_get_bios(struct radeon_device *rdev);
232
233/*
3ce0a23d 234 * Dummy page
771fe6b9 235 */
3ce0a23d
JG		 236struct radeon_dummy_page {
237 struct page *page;
238 dma_addr_t addr;
239};
240int radeon_dummy_page_init(struct radeon_device *rdev);
241void radeon_dummy_page_fini(struct radeon_device *rdev);
242
771fe6b9 243
3ce0a23d
JG		 244/*
245 * Clocks
246 */
771fe6b9
JG		 247struct radeon_clock {
248 struct radeon_pll p1pll;
249 struct radeon_pll p2pll;
bcc1c2a1 250 struct radeon_pll dcpll;
771fe6b9
JG		 251 struct radeon_pll spll;
252 struct radeon_pll mpll;
253 /* 10 Khz units */
254 uint32_t default_mclk;
255 uint32_t default_sclk;
bcc1c2a1 256 uint32_t default_dispclk;
4489cd62 257 uint32_t current_dispclk;
bcc1c2a1 258 uint32_t dp_extclk;
b20f9bef 259 uint32_t max_pixel_clock;
771fe6b9
JG		 260};
261
7433874e
RM		 262/*
263 * Power management
264 */
265int radeon_pm_init(struct radeon_device *rdev);
914a8987 266int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 267void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 268void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 269void radeon_pm_suspend(struct radeon_device *rdev);
270void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 271void radeon_combios_get_power_modes(struct radeon_device *rdev);
272void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 273int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
274 u8 clock_type,
275 u32 clock,
276 bool strobe_mode,
277 struct atom_clock_dividers *dividers);
eaa778af
AD		 278int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
279 u32 clock,
280 bool strobe_mode,
281 struct atom_mpll_param *mpll_param);
8a83ec5e 282void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 283int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
284 u16 voltage_level, u8 voltage_type,
285 u32 *gpio_value, u32 *gpio_mask);
286void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
287 u32 eng_clock, u32 mem_clock);
288int radeon_atom_get_voltage_step(struct radeon_device *rdev,
289 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 290int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
291 u16 voltage_id, u16 *voltage);
beb79f40
AD		 292int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
293 u16 *voltage,
294 u16 leakage_idx);
cc8dbbb4
AD		 295int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
296 u16 *leakage_id);
297int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
298 u16 *vddc, u16 *vddci,
299 u16 virtual_voltage_id,
300 u16 vbios_voltage_id);
ae5b0abb
AD		 301int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
302 u8 voltage_type,
303 u16 nominal_voltage,
304 u16 *true_voltage);
305int radeon_atom_get_min_voltage(struct radeon_device *rdev,
306 u8 voltage_type, u16 *min_voltage);
307int radeon_atom_get_max_voltage(struct radeon_device *rdev,
308 u8 voltage_type, u16 *max_voltage);
309int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 310 u8 voltage_type, u8 voltage_mode,
ae5b0abb 311 struct atom_voltage_table *voltage_table);
58653abd
AD		 312bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
313 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 314void radeon_atom_update_memory_dll(struct radeon_device *rdev,
315 u32 mem_clock);
316void radeon_atom_set_ac_timing(struct radeon_device *rdev,
317 u32 mem_clock);
318int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
319 u8 module_index,
320 struct atom_mc_reg_table *reg_table);
321int radeon_atom_get_memory_info(struct radeon_device *rdev,
322 u8 module_index, struct atom_memory_info *mem_info);
323int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
324 bool gddr5, u8 module_index,
325 struct atom_memory_clock_range_table *mclk_range_table);
326int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
327 u16 voltage_id, u16 *voltage);
f892034a 328void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 329extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
330 unsigned *bankh, unsigned *mtaspect,
331 unsigned *tile_split);
3ce0a23d 332
771fe6b9
JG		 333/*
334 * Fences.
335 */
336struct radeon_fence_driver {
337 uint32_t scratch_reg;
30eb77f4
JG		 338 uint64_t gpu_addr;
339 volatile uint32_t *cpu_addr;
68e250b7
CK		 340 /* sync_seq is protected by ring emission lock */
341 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 342 atomic64_t last_seq;
0a0c7596 343 bool initialized;
771fe6b9
JG		 344};
345
346struct radeon_fence {
347 struct radeon_device *rdev;
348 struct kref kref;
771fe6b9 349 /* protected by radeon_fence.lock */
bb635567 350 uint64_t seq;
7465280c 351 /* RB, DMA, etc. */
bb635567 352 unsigned ring;
771fe6b9
JG		 353};
354
30eb77f4
JG		 355int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
356int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 357void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 358void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 359int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 360void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 361bool radeon_fence_signaled(struct radeon_fence *fence);
362int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
1654b817 363int radeon_fence_wait_locked(struct radeon_fence *fence);
8a47cc9e 364int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 365int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 366int radeon_fence_wait_any(struct radeon_device *rdev,
367 struct radeon_fence **fences,
368 bool intr);
771fe6b9
JG		 369struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
370void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 371unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 372bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
373void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
374static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
375 struct radeon_fence *b)
376{
377 if (!a) {
378 return b;
379 }
380
381 if (!b) {
382 return a;
383 }
384
385 BUG_ON(a->ring != b->ring);
386
387 if (a->seq > b->seq) {
388 return a;
389 } else {
390 return b;
391 }
392}
771fe6b9 393
ee60e29f
CK		 394static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
395 struct radeon_fence *b)
396{
397 if (!a) {
398 return false;
399 }
400
401 if (!b) {
402 return true;
403 }
404
405 BUG_ON(a->ring != b->ring);
406
407 return a->seq < b->seq;
408}
409
e024e110
DA		 410/*
411 * Tiling registers
412 */
413struct radeon_surface_reg {
4c788679 414 struct radeon_bo *bo;
e024e110
DA		 415};
416
417#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 418
419/*
4c788679 420 * TTM.
771fe6b9 421 */
4c788679
JG		 422struct radeon_mman {
423 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 424 struct drm_global_reference mem_global_ref;
4c788679 425 struct ttm_bo_device bdev;
0a0c7596
JG		 426 bool mem_global_referenced;
427 bool initialized;
2014b569
CK		 428
429#if defined(CONFIG_DEBUG_FS)
430 struct dentry *vram;
dd66d20e 431 struct dentry *gtt;
2014b569 432#endif
4c788679
JG		 433};
434
721604a1
JG		 435/* bo virtual address in a specific vm */
436struct radeon_bo_va {
e971bd5e 437 /* protected by bo being reserved */
721604a1 438 struct list_head bo_list;
721604a1
JG		 439 uint64_t soffset;
440 uint64_t eoffset;
441 uint32_t flags;
442 bool valid;
e971bd5e
CK		 443 unsigned ref_count;
444
445 /* protected by vm mutex */
446 struct list_head vm_list;
447
448 /* constant after initialization */
449 struct radeon_vm *vm;
450 struct radeon_bo *bo;
721604a1
JG		 451};
452
4c788679
JG		 453struct radeon_bo {
454 /* Protected by gem.mutex */
455 struct list_head list;
456 /* Protected by tbo.reserved */
312ea8da
JG		 457 u32 placements[3];
458 struct ttm_placement placement;
4c788679
JG		 459 struct ttm_buffer_object tbo;
460 struct ttm_bo_kmap_obj kmap;
461 unsigned pin_count;
462 void *kptr;
463 u32 tiling_flags;
464 u32 pitch;
465 int surface_reg;
721604a1
JG		 466 /* list of all virtual address to which this bo
467 * is associated to
468 */
469 struct list_head va;
4c788679
JG		 470 /* Constant after initialization */
471 struct radeon_device *rdev;
441921d5 472 struct drm_gem_object gem_base;
63bc620b 473
409851f4
JG		 474 struct ttm_bo_kmap_obj dma_buf_vmap;
475 pid_t pid;
4c788679 476};
7e4d15d9 477#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 478
4c788679 479struct radeon_bo_list {
147666fb 480 struct ttm_validate_buffer tv;
4c788679 481 struct radeon_bo *bo;
771fe6b9 482 uint64_t gpu_offset;
4474f3a9
CK		 483 bool written;
484 unsigned domain;
485 unsigned alt_domain;
4c788679 486 u32 tiling_flags;
771fe6b9
JG		 487};
488
409851f4
JG		 489int radeon_gem_debugfs_init(struct radeon_device *rdev);
490
b15ba512
JG		 491/* sub-allocation manager, it has to be protected by another lock.
492 * By conception this is an helper for other part of the driver
493 * like the indirect buffer or semaphore, which both have their
494 * locking.
495 *
496 * Principe is simple, we keep a list of sub allocation in offset
497 * order (first entry has offset == 0, last entry has the highest
498 * offset).
499 *
500 * When allocating new object we first check if there is room at
501 * the end total_size - (last_object_offset + last_object_size) >=
502 * alloc_size. If so we allocate new object there.
503 *
504 * When there is not enough room at the end, we start waiting for
505 * each sub object until we reach object_offset+object_size >=
506 * alloc_size, this object then become the sub object we return.
507 *
508 * Alignment can't be bigger than page size.
509 *
510 * Hole are not considered for allocation to keep things simple.
511 * Assumption is that there won't be hole (all object on same
512 * alignment).
513 */
514struct radeon_sa_manager {
bfb38d35 515 wait_queue_head_t wq;
b15ba512 516 struct radeon_bo *bo;
c3b7fe8b
CK		 517 struct list_head *hole;
518 struct list_head flist[RADEON_NUM_RINGS];
519 struct list_head olist;
b15ba512
JG		 520 unsigned size;
521 uint64_t gpu_addr;
522 void *cpu_ptr;
523 uint32_t domain;
6c4f978b 524 uint32_t align;
b15ba512
JG		 525};
526
527struct radeon_sa_bo;
528
529/* sub-allocation buffer */
530struct radeon_sa_bo {
c3b7fe8b
CK		 531 struct list_head olist;
532 struct list_head flist;
b15ba512 533 struct radeon_sa_manager *manager;
e6661a96
CK		 534 unsigned soffset;
535 unsigned eoffset;
557017a0 536 struct radeon_fence *fence;
b15ba512
JG		 537};
538
771fe6b9
JG		 539/*
540 * GEM objects.
541 */
542struct radeon_gem {
4c788679 543 struct mutex mutex;
771fe6b9
JG		 544 struct list_head objects;
545};
546
547int radeon_gem_init(struct radeon_device *rdev);
548void radeon_gem_fini(struct radeon_device *rdev);
549int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 550 int alignment, int initial_domain,
551 bool discardable, bool kernel,
552 struct drm_gem_object **obj);
771fe6b9 553
ff72145b
DA		 554int radeon_mode_dumb_create(struct drm_file *file_priv,
555 struct drm_device *dev,
556 struct drm_mode_create_dumb *args);
557int radeon_mode_dumb_mmap(struct drm_file *filp,
558 struct drm_device *dev,
559 uint32_t handle, uint64_t *offset_p);
771fe6b9 560
c1341e52
JG		 561/*
562 * Semaphores.
563 */
c1341e52 564struct radeon_semaphore {
a8c05940
JG		 565 struct radeon_sa_bo *sa_bo;
566 signed waiters;
c1341e52 567 uint64_t gpu_addr;
1654b817 568 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 569};
570
c1341e52
JG		 571int radeon_semaphore_create(struct radeon_device *rdev,
572 struct radeon_semaphore **semaphore);
1654b817 573bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 574 struct radeon_semaphore *semaphore);
1654b817 575bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 576 struct radeon_semaphore *semaphore);
1654b817
CK		 577void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
578 struct radeon_fence *fence);
8f676c4c
CK		 579int radeon_semaphore_sync_rings(struct radeon_device *rdev,
580 struct radeon_semaphore *semaphore,
1654b817 581 int waiting_ring);
c1341e52 582void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 583 struct radeon_semaphore **semaphore,
a8c05940 584 struct radeon_fence *fence);
c1341e52 585
771fe6b9
JG		 586/*
587 * GART structures, functions & helpers
588 */
589struct radeon_mc;
590
a77f1718 591#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 592#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 593#define RADEON_GPU_PAGE_SHIFT 12
721604a1 594#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 595
771fe6b9
JG		 596struct radeon_gart {
597 dma_addr_t table_addr;
c9a1be96
JG		 598 struct radeon_bo *robj;
599 void *ptr;
771fe6b9
JG		 600 unsigned num_gpu_pages;
601 unsigned num_cpu_pages;
602 unsigned table_size;
771fe6b9
JG		 603 struct page **pages;
604 dma_addr_t *pages_addr;
605 bool ready;
606};
607
608int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
609void radeon_gart_table_ram_free(struct radeon_device *rdev);
610int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
611void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 612int radeon_gart_table_vram_pin(struct radeon_device *rdev);
613void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 614int radeon_gart_init(struct radeon_device *rdev);
615void radeon_gart_fini(struct radeon_device *rdev);
616void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
617 int pages);
618int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 619 int pages, struct page **pagelist,
620 dma_addr_t *dma_addr);
c9a1be96 621void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 622
623
624/*
625 * GPU MC structures, functions & helpers
626 */
627struct radeon_mc {
628 resource_size_t aper_size;
629 resource_size_t aper_base;
630 resource_size_t agp_base;
7a50f01a
DA		 631 /* for some chips with <= 32MB we need to lie
632 * about vram size near mc fb location */
3ce0a23d 633 u64 mc_vram_size;
d594e46a 634 u64 visible_vram_size;
3ce0a23d
JG		 635 u64 gtt_size;
636 u64 gtt_start;
637 u64 gtt_end;
3ce0a23d
JG		 638 u64 vram_start;
639 u64 vram_end;
771fe6b9 640 unsigned vram_width;
3ce0a23d 641 u64 real_vram_size;
771fe6b9
JG		 642 int vram_mtrr;
643 bool vram_is_ddr;
d594e46a 644 bool igp_sideport_enabled;
8d369bb1 645 u64 gtt_base_align;
9ed8b1f9 646 u64 mc_mask;
771fe6b9
JG		 647};
648
06b6476d
AD		 649bool radeon_combios_sideport_present(struct radeon_device *rdev);
650bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 651
652/*
653 * GPU scratch registers structures, functions & helpers
654 */
655struct radeon_scratch {
656 unsigned num_reg;
724c80e1 657 uint32_t reg_base;
771fe6b9
JG		 658 bool free[32];
659 uint32_t reg[32];
660};
661
662int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
663void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
664
75efdee1
AD		 665/*
666 * GPU doorbell structures, functions & helpers
667 */
d5754ab8
AL		 668#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
669
75efdee1 670struct radeon_doorbell {
75efdee1 671 /* doorbell mmio */
d5754ab8
AL		 672 resource_size_t base;
673 resource_size_t size;
674 u32 __iomem *ptr;
675 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
676 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 677};
678
679int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
680void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 681
682/*
683 * IRQS.
684 */
6f34be50
AD		 685
686struct radeon_unpin_work {
687 struct work_struct work;
688 struct radeon_device *rdev;
689 int crtc_id;
690 struct radeon_fence *fence;
691 struct drm_pending_vblank_event *event;
692 struct radeon_bo *old_rbo;
693 u64 new_crtc_base;
694};
695
696struct r500_irq_stat_regs {
697 u32 disp_int;
f122c610 698 u32 hdmi0_status;
6f34be50
AD		 699};
700
701struct r600_irq_stat_regs {
702 u32 disp_int;
703 u32 disp_int_cont;
704 u32 disp_int_cont2;
705 u32 d1grph_int;
706 u32 d2grph_int;
f122c610
AD		 707 u32 hdmi0_status;
708 u32 hdmi1_status;
6f34be50
AD		 709};
710
711struct evergreen_irq_stat_regs {
712 u32 disp_int;
713 u32 disp_int_cont;
714 u32 disp_int_cont2;
715 u32 disp_int_cont3;
716 u32 disp_int_cont4;
717 u32 disp_int_cont5;
718 u32 d1grph_int;
719 u32 d2grph_int;
720 u32 d3grph_int;
721 u32 d4grph_int;
722 u32 d5grph_int;
723 u32 d6grph_int;
f122c610
AD		 724 u32 afmt_status1;
725 u32 afmt_status2;
726 u32 afmt_status3;
727 u32 afmt_status4;
728 u32 afmt_status5;
729 u32 afmt_status6;
6f34be50
AD		 730};
731
a59781bb
AD		 732struct cik_irq_stat_regs {
733 u32 disp_int;
734 u32 disp_int_cont;
735 u32 disp_int_cont2;
736 u32 disp_int_cont3;
737 u32 disp_int_cont4;
738 u32 disp_int_cont5;
739 u32 disp_int_cont6;
740};
741
6f34be50
AD		 742union radeon_irq_stat_regs {
743 struct r500_irq_stat_regs r500;
744 struct r600_irq_stat_regs r600;
745 struct evergreen_irq_stat_regs evergreen;
a59781bb 746 struct cik_irq_stat_regs cik;
6f34be50
AD		 747};
748
54bd5206
IH		 749#define RADEON_MAX_HPD_PINS 6
750#define RADEON_MAX_CRTCS 6
b530602f 751#define RADEON_MAX_AFMT_BLOCKS 7
54bd5206 752
771fe6b9 753struct radeon_irq {
fb98257a
CK		 754 bool installed;
755 spinlock_t lock;
736fc37f 756 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 757 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 758 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 759 wait_queue_head_t vblank_queue;
760 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 761 bool afmt[RADEON_MAX_AFMT_BLOCKS];
762 union radeon_irq_stat_regs stat_regs;
4a6369e9 763 bool dpm_thermal;
771fe6b9
JG		 764};
765
766int radeon_irq_kms_init(struct radeon_device *rdev);
767void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 768void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
769void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 770void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
771void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 772void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
773void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
774void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
775void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 776
777/*
e32eb50d 778 * CP & rings.
771fe6b9 779 */
7465280c 780
771fe6b9 781struct radeon_ib {
68470ae7
JG		 782 struct radeon_sa_bo *sa_bo;
783 uint32_t length_dw;
784 uint64_t gpu_addr;
785 uint32_t *ptr;
876dc9f3 786 int ring;
68470ae7 787 struct radeon_fence *fence;
4bf3dd92 788 struct radeon_vm *vm;
68470ae7
JG		 789 bool is_const_ib;
790 struct radeon_semaphore *semaphore;
771fe6b9
JG		 791};
792
e32eb50d 793struct radeon_ring {
4c788679 794 struct radeon_bo *ring_obj;
771fe6b9
JG		 795 volatile uint32_t *ring;
796 unsigned rptr;
5596a9db 797 unsigned rptr_offs;
45df6803 798 unsigned rptr_save_reg;
89d35807
AD		 799 u64 next_rptr_gpu_addr;
800 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 801 unsigned wptr;
802 unsigned wptr_old;
803 unsigned ring_size;
804 unsigned ring_free_dw;
805 int count_dw;
069211e5
CK		 806 unsigned long last_activity;
807 unsigned last_rptr;
771fe6b9
JG		 808 uint64_t gpu_addr;
809 uint32_t align_mask;
810 uint32_t ptr_mask;
771fe6b9 811 bool ready;
78c5560a 812 u32 nop;
8b25ed34 813 u32 idx;
5f0839c1
JG		 814 u64 last_semaphore_signal_addr;
815 u64 last_semaphore_wait_addr;
963e81f9
AD		 816 /* for CIK queues */
817 u32 me;
818 u32 pipe;
819 u32 queue;
820 struct radeon_bo *mqd_obj;
d5754ab8 821 u32 doorbell_index;
963e81f9
AD		 822 unsigned wptr_offs;
823};
824
825struct radeon_mec {
826 struct radeon_bo *hpd_eop_obj;
827 u64 hpd_eop_gpu_addr;
828 u32 num_pipe;
829 u32 num_mec;
830 u32 num_queue;
771fe6b9
JG		 831};
832
721604a1
JG		 833/*
834 * VM
835 */
ee60e29f 836
fa87e62d 837/* maximum number of VMIDs */
ee60e29f
CK		 838#define RADEON_NUM_VM 16
839
fa87e62d
DC		 840/* defines number of bits in page table versus page directory,
841 * a page is 4KB so we have 12 bits offset, 9 bits in the page
842 * table and the remaining 19 bits are in the page directory */
843#define RADEON_VM_BLOCK_SIZE 9
844
845/* number of entries in page table */
846#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
847
1c01103c
AD		 848/* PTBs (Page Table Blocks) need to be aligned to 32K */
849#define RADEON_VM_PTB_ALIGN_SIZE 32768
850#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
851#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
852
24c16439
CK		 853#define R600_PTE_VALID (1 << 0)
854#define R600_PTE_SYSTEM (1 << 1)
855#define R600_PTE_SNOOPED (1 << 2)
856#define R600_PTE_READABLE (1 << 5)
857#define R600_PTE_WRITEABLE (1 << 6)
858
721604a1
JG		 859struct radeon_vm {
860 struct list_head list;
861 struct list_head va;
ee60e29f 862 unsigned id;
90a51a32
CK		 863
864 /* contains the page directory */
865 struct radeon_sa_bo *page_directory;
866 uint64_t pd_gpu_addr;
867
868 /* array of page tables, one for each page directory entry */
869 struct radeon_sa_bo **page_tables;
870
721604a1
JG		 871 struct mutex mutex;
872 /* last fence for cs using this vm */
873 struct radeon_fence *fence;
9b40e5d8
CK		 874 /* last flush or NULL if we still need to flush */
875 struct radeon_fence *last_flush;
593b2635
CK		 876 /* last use of vmid */
877 struct radeon_fence *last_id_use;
721604a1
JG		 878};
879
721604a1 880struct radeon_vm_manager {
36ff39c4 881 struct mutex lock;
721604a1 882 struct list_head lru_vm;
ee60e29f 883 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 884 struct radeon_sa_manager sa_manager;
885 uint32_t max_pfn;
721604a1
JG		 886 /* number of VMIDs */
887 unsigned nvm;
888 /* vram base address for page table entry */
889 u64 vram_base_offset;
67e915e4
AD		 890 /* is vm enabled? */
891 bool enabled;
721604a1
JG		 892};
893
894/*
895 * file private structure
896 */
897struct radeon_fpriv {
898 struct radeon_vm vm;
899};
900
d8f60cfc
AD		 901/*
902 * R6xx+ IH ring
903 */
904struct r600_ih {
4c788679 905 struct radeon_bo *ring_obj;
d8f60cfc
AD		 906 volatile uint32_t *ring;
907 unsigned rptr;
d8f60cfc
AD		 908 unsigned ring_size;
909 uint64_t gpu_addr;
d8f60cfc 910 uint32_t ptr_mask;
c20dc369 911 atomic_t lock;
d8f60cfc
AD		 912 bool enabled;
913};
914
347e7592 915/*
2948f5e6 916 * RLC stuff
347e7592 917 */
2948f5e6
AD		 918#include "clearstate_defs.h"
919
920struct radeon_rlc {
347e7592
AD		 921 /* for power gating */
922 struct radeon_bo *save_restore_obj;
923 uint64_t save_restore_gpu_addr;
2948f5e6 924 volatile uint32_t *sr_ptr;
1fd11777 925 const u32 *reg_list;
2948f5e6 926 u32 reg_list_size;
347e7592
AD		 927 /* for clear state */
928 struct radeon_bo *clear_state_obj;
929 uint64_t clear_state_gpu_addr;
2948f5e6 930 volatile uint32_t *cs_ptr;
1fd11777 931 const struct cs_section_def *cs_data;
22c775ce
AD		 932 u32 clear_state_size;
933 /* for cp tables */
934 struct radeon_bo *cp_table_obj;
935 uint64_t cp_table_gpu_addr;
936 volatile uint32_t *cp_table_ptr;
937 u32 cp_table_size;
347e7592
AD		 938};
939
69e130a6 940int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 941 struct radeon_ib *ib, struct radeon_vm *vm,
942 unsigned size);
f2e39221 943void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 944int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
945 struct radeon_ib *const_ib);
771fe6b9
JG		 946int radeon_ib_pool_init(struct radeon_device *rdev);
947void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 948int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 949/* Ring access between begin & end cannot sleep */
89d35807
AD		 950bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
951 struct radeon_ring *ring);
e32eb50d
CK		 952void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
953int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
954int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
955void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
956void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 957void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 958void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
959int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 960void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 961void radeon_ring_lockup_update(struct radeon_ring *ring);
962bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 963unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
964 uint32_t **data);
965int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
966 unsigned size, uint32_t *data);
e32eb50d 967int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 968 unsigned rptr_offs, u32 nop);
e32eb50d 969void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 970
971
4d75658b
AD		 972/* r600 async dma */
973void r600_dma_stop(struct radeon_device *rdev);
974int r600_dma_resume(struct radeon_device *rdev);
975void r600_dma_fini(struct radeon_device *rdev);
976
8c5fd7ef
AD		 977void cayman_dma_stop(struct radeon_device *rdev);
978int cayman_dma_resume(struct radeon_device *rdev);
979void cayman_dma_fini(struct radeon_device *rdev);
980
771fe6b9
JG		 981/*
982 * CS.
983 */
984struct radeon_cs_reloc {
985 struct drm_gem_object *gobj;
4c788679
JG		 986 struct radeon_bo *robj;
987 struct radeon_bo_list lobj;
771fe6b9
JG		 988 uint32_t handle;
989 uint32_t flags;
990};
991
992struct radeon_cs_chunk {
993 uint32_t chunk_id;
994 uint32_t length_dw;
995 uint32_t *kdata;
721604a1 996 void __user *user_ptr;
771fe6b9
JG		 997};
998
999struct radeon_cs_parser {
c8c15ff1 1000 struct device *dev;
771fe6b9
JG		 1001 struct radeon_device *rdev;
1002 struct drm_file *filp;
1003 /* chunks */
1004 unsigned nchunks;
1005 struct radeon_cs_chunk *chunks;
1006 uint64_t *chunks_array;
1007 /* IB */
1008 unsigned idx;
1009 /* relocations */
1010 unsigned nrelocs;
1011 struct radeon_cs_reloc *relocs;
1012 struct radeon_cs_reloc **relocs_ptr;
1013 struct list_head validated;
cf4ccd01 1014 unsigned dma_reloc_idx;
771fe6b9
JG		 1015 /* indices of various chunks */
1016 int chunk_ib_idx;
1017 int chunk_relocs_idx;
721604a1 1018 int chunk_flags_idx;
dfcf5f36 1019 int chunk_const_ib_idx;
f2e39221
JG		 1020 struct radeon_ib ib;
1021 struct radeon_ib const_ib;
771fe6b9 1022 void *track;
3ce0a23d 1023 unsigned family;
e70f224c 1024 int parser_error;
721604a1
JG		 1025 u32 cs_flags;
1026 u32 ring;
1027 s32 priority;
ecff665f 1028 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1029};
1030
28a326c5
ML		 1031static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1032{
1033 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1034
1035 if (ibc->kdata)
1036 return ibc->kdata[idx];
1037 return p->ib.ptr[idx];
1038}
1039
513bcb46 1040
771fe6b9
JG		 1041struct radeon_cs_packet {
1042 unsigned idx;
1043 unsigned type;
1044 unsigned reg;
1045 unsigned opcode;
1046 int count;
1047 unsigned one_reg_wr;
1048};
1049
1050typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1051 struct radeon_cs_packet *pkt,
1052 unsigned idx, unsigned reg);
1053typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1054 struct radeon_cs_packet *pkt);
1055
1056
1057/*
1058 * AGP
1059 */
1060int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1061void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1062void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1063void radeon_agp_fini(struct radeon_device *rdev);
1064
1065
1066/*
1067 * Writeback
1068 */
1069struct radeon_wb {
4c788679 1070 struct radeon_bo *wb_obj;
771fe6b9
JG		 1071 volatile uint32_t *wb;
1072 uint64_t gpu_addr;
724c80e1 1073 bool enabled;
d0f8a854 1074 bool use_event;
771fe6b9
JG		 1075};
1076
724c80e1 1077#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1078#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1079#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1080#define RADEON_WB_CP1_RPTR_OFFSET 1280
1081#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1082#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1083#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1084#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1085#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1086#define CIK_WB_CP1_WPTR_OFFSET 3328
1087#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1088
c93bb85b
JG		 1089/**
1090 * struct radeon_pm - power management datas
1091 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1092 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1093 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1094 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1095 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1096 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1097 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1098 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1099 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1100 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1101 * @needed_bandwidth: current bandwidth needs
1102 *
1103 * It keeps track of various data needed to take powermanagement decision.
25985edc 1104 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1105 * Equation between gpu/memory clock and available bandwidth is hw dependent
1106 * (type of memory, bus size, efficiency, ...)
1107 */
ce8f5370
AD		 1108
1109enum radeon_pm_method {
1110 PM_METHOD_PROFILE,
1111 PM_METHOD_DYNPM,
da321c8a 1112 PM_METHOD_DPM,
ce8f5370
AD		 1113};
1114
1115enum radeon_dynpm_state {
1116 DYNPM_STATE_DISABLED,
1117 DYNPM_STATE_MINIMUM,
1118 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1119 DYNPM_STATE_ACTIVE,
1120 DYNPM_STATE_SUSPENDED,
c913e23a 1121};
ce8f5370
AD		 1122enum radeon_dynpm_action {
1123 DYNPM_ACTION_NONE,
1124 DYNPM_ACTION_MINIMUM,
1125 DYNPM_ACTION_DOWNCLOCK,
1126 DYNPM_ACTION_UPCLOCK,
1127 DYNPM_ACTION_DEFAULT
c913e23a 1128};
56278a8e
AD		 1129
1130enum radeon_voltage_type {
1131 VOLTAGE_NONE = 0,
1132 VOLTAGE_GPIO,
1133 VOLTAGE_VDDC,
1134 VOLTAGE_SW
1135};
1136
0ec0e74f 1137enum radeon_pm_state_type {
da321c8a 1138 /* not used for dpm */
0ec0e74f
AD		 1139 POWER_STATE_TYPE_DEFAULT,
1140 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1141 /* user selectable states */
0ec0e74f
AD		 1142 POWER_STATE_TYPE_BATTERY,
1143 POWER_STATE_TYPE_BALANCED,
1144 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1145 /* internal states */
1146 POWER_STATE_TYPE_INTERNAL_UVD,
1147 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1148 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1149 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1150 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1151 POWER_STATE_TYPE_INTERNAL_BOOT,
1152 POWER_STATE_TYPE_INTERNAL_THERMAL,
1153 POWER_STATE_TYPE_INTERNAL_ACPI,
1154 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1155 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1156};
1157
ce8f5370
AD		 1158enum radeon_pm_profile_type {
1159 PM_PROFILE_DEFAULT,
1160 PM_PROFILE_AUTO,
1161 PM_PROFILE_LOW,
c9e75b21 1162 PM_PROFILE_MID,
ce8f5370
AD		 1163 PM_PROFILE_HIGH,
1164};
1165
1166#define PM_PROFILE_DEFAULT_IDX 0
1167#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1168#define PM_PROFILE_MID_SH_IDX 2
1169#define PM_PROFILE_HIGH_SH_IDX 3
1170#define PM_PROFILE_LOW_MH_IDX 4
1171#define PM_PROFILE_MID_MH_IDX 5
1172#define PM_PROFILE_HIGH_MH_IDX 6
1173#define PM_PROFILE_MAX 7
ce8f5370
AD		 1174
1175struct radeon_pm_profile {
1176 int dpms_off_ps_idx;
1177 int dpms_on_ps_idx;
1178 int dpms_off_cm_idx;
1179 int dpms_on_cm_idx;
516d0e46
AD		 1180};
1181
21a8122a
AD		 1182enum radeon_int_thermal_type {
1183 THERMAL_TYPE_NONE,
da321c8a
AD		 1184 THERMAL_TYPE_EXTERNAL,
1185 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1186 THERMAL_TYPE_RV6XX,
1187 THERMAL_TYPE_RV770,
da321c8a 1188 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1189 THERMAL_TYPE_EVERGREEN,
e33df25f 1190 THERMAL_TYPE_SUMO,
4fddba1f 1191 THERMAL_TYPE_NI,
14607d08 1192 THERMAL_TYPE_SI,
da321c8a 1193 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1194 THERMAL_TYPE_CI,
16fbe00d 1195 THERMAL_TYPE_KV,
21a8122a
AD		 1196};
1197
56278a8e
AD		 1198struct radeon_voltage {
1199 enum radeon_voltage_type type;
1200 /* gpio voltage */
1201 struct radeon_gpio_rec gpio;
1202 u32 delay; /* delay in usec from voltage drop to sclk change */
1203 bool active_high; /* voltage drop is active when bit is high */
1204 /* VDDC voltage */
1205 u8 vddc_id; /* index into vddc voltage table */
1206 u8 vddci_id; /* index into vddci voltage table */
1207 bool vddci_enabled;
1208 /* r6xx+ sw */
2feea49a
AD		 1209 u16 voltage;
1210 /* evergreen+ vddci */
1211 u16 vddci;
56278a8e
AD		 1212};
1213
d7311171
AD		 1214/* clock mode flags */
1215#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1216
56278a8e
AD		 1217struct radeon_pm_clock_info {
1218 /* memory clock */
1219 u32 mclk;
1220 /* engine clock */
1221 u32 sclk;
1222 /* voltage info */
1223 struct radeon_voltage voltage;
d7311171 1224 /* standardized clock flags */
56278a8e
AD		 1225 u32 flags;
1226};
1227
a48b9b4e 1228/* state flags */
d7311171 1229#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1230
56278a8e 1231struct radeon_power_state {
0ec0e74f 1232 enum radeon_pm_state_type type;
8f3f1c9a 1233 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1234 /* number of valid clock modes in this power state */
1235 int num_clock_modes;
56278a8e 1236 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1237 /* standardized state flags */
1238 u32 flags;
79daedc9
AD		 1239 u32 misc; /* vbios specific flags */
1240 u32 misc2; /* vbios specific flags */
1241 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1242};
1243
27459324
RM		 1244/*
1245 * Some modes are overclocked by very low value, accept them
1246 */
1247#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1248
2e9d4c05
AD		 1249enum radeon_dpm_auto_throttle_src {
1250 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1251 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1252};
1253
1254enum radeon_dpm_event_src {
1255 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1256 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1257 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1258 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1259 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1260};
1261
b62d628b
AD		 1262enum radeon_vce_level {
1263 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1264 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1265 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1266 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1267 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1268 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1269};
1270
da321c8a
AD		 1271struct radeon_ps {
1272 u32 caps; /* vbios flags */
1273 u32 class; /* vbios flags */
1274 u32 class2; /* vbios flags */
1275 /* UVD clocks */
1276 u32 vclk;
1277 u32 dclk;
c4453e66
AD		 1278 /* VCE clocks */
1279 u32 evclk;
1280 u32 ecclk;
b62d628b
AD		 1281 bool vce_active;
1282 enum radeon_vce_level vce_level;
da321c8a
AD		 1283 /* asic priv */
1284 void *ps_priv;
1285};
1286
1287struct radeon_dpm_thermal {
1288 /* thermal interrupt work */
1289 struct work_struct work;
1290 /* low temperature threshold */
1291 int min_temp;
1292 /* high temperature threshold */
1293 int max_temp;
1294 /* was interrupt low to high or high to low */
1295 bool high_to_low;
1296};
1297
d22b7e40
AD		 1298enum radeon_clk_action
1299{
1300 RADEON_SCLK_UP = 1,
1301 RADEON_SCLK_DOWN
1302};
1303
1304struct radeon_blacklist_clocks
1305{
1306 u32 sclk;
1307 u32 mclk;
1308 enum radeon_clk_action action;
1309};
1310
61b7d601
AD		 1311struct radeon_clock_and_voltage_limits {
1312 u32 sclk;
1313 u32 mclk;
cdf6e805
AD		 1314 u16 vddc;
1315 u16 vddci;
61b7d601
AD		 1316};
1317
1318struct radeon_clock_array {
1319 u32 count;
1320 u32 *values;
1321};
1322
1323struct radeon_clock_voltage_dependency_entry {
1324 u32 clk;
1325 u16 v;
1326};
1327
1328struct radeon_clock_voltage_dependency_table {
1329 u32 count;
1330 struct radeon_clock_voltage_dependency_entry *entries;
1331};
1332
ef976ec4
AD		 1333union radeon_cac_leakage_entry {
1334 struct {
1335 u16 vddc;
1336 u32 leakage;
1337 };
1338 struct {
1339 u16 vddc1;
1340 u16 vddc2;
1341 u16 vddc3;
1342 };
61b7d601
AD		 1343};
1344
1345struct radeon_cac_leakage_table {
1346 u32 count;
ef976ec4 1347 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1348};
1349
929ee7a8
AD		 1350struct radeon_phase_shedding_limits_entry {
1351 u16 voltage;
1352 u32 sclk;
1353 u32 mclk;
1354};
1355
1356struct radeon_phase_shedding_limits_table {
1357 u32 count;
1358 struct radeon_phase_shedding_limits_entry *entries;
1359};
1360
84a9d9ee
AD		 1361struct radeon_uvd_clock_voltage_dependency_entry {
1362 u32 vclk;
1363 u32 dclk;
1364 u16 v;
1365};
1366
1367struct radeon_uvd_clock_voltage_dependency_table {
1368 u8 count;
1369 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1370};
1371
d29f013b
AD		 1372struct radeon_vce_clock_voltage_dependency_entry {
1373 u32 ecclk;
1374 u32 evclk;
1375 u16 v;
1376};
1377
1378struct radeon_vce_clock_voltage_dependency_table {
1379 u8 count;
1380 struct radeon_vce_clock_voltage_dependency_entry *entries;
1381};
1382
a5cb318e
AD		 1383struct radeon_ppm_table {
1384 u8 ppm_design;
1385 u16 cpu_core_number;
1386 u32 platform_tdp;
1387 u32 small_ac_platform_tdp;
1388 u32 platform_tdc;
1389 u32 small_ac_platform_tdc;
1390 u32 apu_tdp;
1391 u32 dgpu_tdp;
1392 u32 dgpu_ulv_power;
1393 u32 tj_max;
1394};
1395
58cb7632
AD		 1396struct radeon_cac_tdp_table {
1397 u16 tdp;
1398 u16 configurable_tdp;
1399 u16 tdc;
1400 u16 battery_power_limit;
1401 u16 small_power_limit;
1402 u16 low_cac_leakage;
1403 u16 high_cac_leakage;
1404 u16 maximum_power_delivery_limit;
1405};
1406
61b7d601
AD		 1407struct radeon_dpm_dynamic_state {
1408 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1409 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1410 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1411 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1412 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1413 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1414 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1415 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1416 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1417 struct radeon_clock_array valid_sclk_values;
1418 struct radeon_clock_array valid_mclk_values;
1419 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1420 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1421 u32 mclk_sclk_ratio;
1422 u32 sclk_mclk_delta;
1423 u16 vddc_vddci_delta;
1424 u16 min_vddc_for_pcie_gen2;
1425 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1426 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1427 struct radeon_ppm_table *ppm_table;
58cb7632 1428 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1429};
1430
1431struct radeon_dpm_fan {
1432 u16 t_min;
1433 u16 t_med;
1434 u16 t_high;
1435 u16 pwm_min;
1436 u16 pwm_med;
1437 u16 pwm_high;
1438 u8 t_hyst;
1439 u32 cycle_delay;
1440 u16 t_max;
1441 bool ucode_fan_control;
1442};
1443
32ce4652
AD		 1444enum radeon_pcie_gen {
1445 RADEON_PCIE_GEN1 = 0,
1446 RADEON_PCIE_GEN2 = 1,
1447 RADEON_PCIE_GEN3 = 2,
1448 RADEON_PCIE_GEN_INVALID = 0xffff
1449};
1450
70d01a5e
AD		 1451enum radeon_dpm_forced_level {
1452 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1453 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1454 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1455};
1456
da321c8a
AD		 1457struct radeon_dpm {
1458 struct radeon_ps *ps;
1459 /* number of valid power states */
1460 int num_ps;
1461 /* current power state that is active */
1462 struct radeon_ps *current_ps;
1463 /* requested power state */
1464 struct radeon_ps *requested_ps;
1465 /* boot up power state */
1466 struct radeon_ps *boot_ps;
1467 /* default uvd power state */
1468 struct radeon_ps *uvd_ps;
1469 enum radeon_pm_state_type state;
1470 enum radeon_pm_state_type user_state;
1471 u32 platform_caps;
1472 u32 voltage_response_time;
1473 u32 backbias_response_time;
1474 void *priv;
1475 u32 new_active_crtcs;
1476 int new_active_crtc_count;
1477 u32 current_active_crtcs;
1478 int current_active_crtc_count;
61b7d601
AD		 1479 struct radeon_dpm_dynamic_state dyn_state;
1480 struct radeon_dpm_fan fan;
1481 u32 tdp_limit;
1482 u32 near_tdp_limit;
a9e61410 1483 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1484 u32 sq_ramping_threshold;
1485 u32 cac_leakage;
1486 u16 tdp_od_limit;
1487 u32 tdp_adjustment;
1488 u16 load_line_slope;
1489 bool power_control;
5ca302f7 1490 bool ac_power;
da321c8a
AD		 1491 /* special states active */
1492 bool thermal_active;
8a227555 1493 bool uvd_active;
b62d628b 1494 bool vce_active;
da321c8a
AD		 1495 /* thermal handling */
1496 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1497 /* forced levels */
1498 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1499 /* track UVD streams */
1500 unsigned sd;
1501 unsigned hd;
da321c8a
AD		 1502};
1503
ce3537d5 1504void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
da321c8a 1505
c93bb85b 1506struct radeon_pm {
c913e23a 1507 struct mutex mutex;
db7fce39
CK		 1508 /* write locked while reprogramming mclk */
1509 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1510 u32 active_crtcs;
1511 int active_crtc_count;
c913e23a 1512 int req_vblank;
839461d3 1513 bool vblank_sync;
c93bb85b
JG		 1514 fixed20_12 max_bandwidth;
1515 fixed20_12 igp_sideport_mclk;
1516 fixed20_12 igp_system_mclk;
1517 fixed20_12 igp_ht_link_clk;
1518 fixed20_12 igp_ht_link_width;
1519 fixed20_12 k8_bandwidth;
1520 fixed20_12 sideport_bandwidth;
1521 fixed20_12 ht_bandwidth;
1522 fixed20_12 core_bandwidth;
1523 fixed20_12 sclk;
f47299c5 1524 fixed20_12 mclk;
c93bb85b 1525 fixed20_12 needed_bandwidth;
0975b162 1526 struct radeon_power_state *power_state;
56278a8e
AD		 1527 /* number of valid power states */
1528 int num_power_states;
a48b9b4e
AD		 1529 int current_power_state_index;
1530 int current_clock_mode_index;
1531 int requested_power_state_index;
1532 int requested_clock_mode_index;
1533 int default_power_state_index;
1534 u32 current_sclk;
1535 u32 current_mclk;
2feea49a
AD		 1536 u16 current_vddc;
1537 u16 current_vddci;
9ace9f7b
AD		 1538 u32 default_sclk;
1539 u32 default_mclk;
2feea49a
AD		 1540 u16 default_vddc;
1541 u16 default_vddci;
29fb52ca 1542 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1543 /* selected pm method */
1544 enum radeon_pm_method pm_method;
1545 /* dynpm power management */
1546 struct delayed_work dynpm_idle_work;
1547 enum radeon_dynpm_state dynpm_state;
1548 enum radeon_dynpm_action dynpm_planned_action;
1549 unsigned long dynpm_action_timeout;
1550 bool dynpm_can_upclock;
1551 bool dynpm_can_downclock;
1552 /* profile-based power management */
1553 enum radeon_pm_profile_type profile;
1554 int profile_index;
1555 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1556 /* internal thermal controller on rv6xx+ */
1557 enum radeon_int_thermal_type int_thermal_type;
1558 struct device *int_hwmon_dev;
da321c8a
AD		 1559 /* dpm */
1560 bool dpm_enabled;
1561 struct radeon_dpm dpm;
c93bb85b
JG		 1562};
1563
a4c9e2ee
AD		 1564int radeon_pm_get_type_index(struct radeon_device *rdev,
1565 enum radeon_pm_state_type ps_type,
1566 int instance);
f2ba57b5
CK		 1567/*
1568 * UVD
1569 */
1570#define RADEON_MAX_UVD_HANDLES 10
1571#define RADEON_UVD_STACK_SIZE (1024*1024)
1572#define RADEON_UVD_HEAP_SIZE (1024*1024)
1573
1574struct radeon_uvd {
1575 struct radeon_bo *vcpu_bo;
1576 void *cpu_addr;
1577 uint64_t gpu_addr;
9cc2e0e9 1578 void *saved_bo;
f2ba57b5
CK		 1579 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1580 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1581 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1582 struct delayed_work idle_work;
f2ba57b5
CK		 1583};
1584
1585int radeon_uvd_init(struct radeon_device *rdev);
1586void radeon_uvd_fini(struct radeon_device *rdev);
1587int radeon_uvd_suspend(struct radeon_device *rdev);
1588int radeon_uvd_resume(struct radeon_device *rdev);
1589int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1590 uint32_t handle, struct radeon_fence **fence);
1591int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1592 uint32_t handle, struct radeon_fence **fence);
1593void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1594void radeon_uvd_free_handles(struct radeon_device *rdev,
1595 struct drm_file *filp);
1596int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1597void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1598int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1599 unsigned vclk, unsigned dclk,
1600 unsigned vco_min, unsigned vco_max,
1601 unsigned fb_factor, unsigned fb_mask,
1602 unsigned pd_min, unsigned pd_max,
1603 unsigned pd_even,
1604 unsigned *optimal_fb_div,
1605 unsigned *optimal_vclk_div,
1606 unsigned *optimal_dclk_div);
1607int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1608 unsigned cg_upll_func_cntl);
771fe6b9 1609
d93f7937
CK		 1610/*
1611 * VCE
1612 */
1613#define RADEON_MAX_VCE_HANDLES 16
1614#define RADEON_VCE_STACK_SIZE (1024*1024)
1615#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1616
1617struct radeon_vce {
1618 struct radeon_bo *vcpu_bo;
1619 void *cpu_addr;
1620 uint64_t gpu_addr;
98ccc291
CK		 1621 unsigned fw_version;
1622 unsigned fb_version;
d93f7937
CK		 1623 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1624 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1625};
1626
1627int radeon_vce_init(struct radeon_device *rdev);
1628void radeon_vce_fini(struct radeon_device *rdev);
1629int radeon_vce_suspend(struct radeon_device *rdev);
1630int radeon_vce_resume(struct radeon_device *rdev);
1631int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1632 uint32_t handle, struct radeon_fence **fence);
1633int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1634 uint32_t handle, struct radeon_fence **fence);
1635void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1636int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi);
1637int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1638bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1639 struct radeon_ring *ring,
1640 struct radeon_semaphore *semaphore,
1641 bool emit_wait);
1642void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1643void radeon_vce_fence_emit(struct radeon_device *rdev,
1644 struct radeon_fence *fence);
1645int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1646int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1647
b530602f 1648struct r600_audio_pin {
a92553ab
RM		 1649 int channels;
1650 int rate;
1651 int bits_per_sample;
1652 u8 status_bits;
1653 u8 category_code;
b530602f
AD		 1654 u32 offset;
1655 bool connected;
1656 u32 id;
1657};
1658
1659struct r600_audio {
1660 bool enabled;
1661 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1662 int num_pins;
a92553ab
RM		 1663};
1664
771fe6b9
JG		 1665/*
1666 * Benchmarking
1667 */
638dd7db 1668void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1669
1670
ecc0b326
MD		 1671/*
1672 * Testing
1673 */
1674void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1675void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1676 struct radeon_ring *cpA,
1677 struct radeon_ring *cpB);
60a7e396 1678void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1679
1680
771fe6b9
JG		 1681/*
1682 * Debugfs
1683 */
4d8bf9ae
CK		 1684struct radeon_debugfs {
1685 struct drm_info_list *files;
1686 unsigned num_files;
1687};
1688
771fe6b9
JG		 1689int radeon_debugfs_add_files(struct radeon_device *rdev,
1690 struct drm_info_list *files,
1691 unsigned nfiles);
1692int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1693
76a0df85
CK		 1694/*
1695 * ASIC ring specific functions.
1696 */
1697struct radeon_asic_ring {
1698 /* ring read/write ptr handling */
1699 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1700 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1701 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1702
1703 /* validating and patching of IBs */
1704 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1705 int (*cs_parse)(struct radeon_cs_parser *p);
1706
1707 /* command emmit functions */
1708 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1709 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1654b817 1710 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1711 struct radeon_semaphore *semaphore, bool emit_wait);
1712 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1713
1714 /* testing functions */
1715 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1716 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1717 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1718
1719 /* deprecated */
1720 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1721};
771fe6b9
JG		 1722
1723/*
1724 * ASIC specific functions.
1725 */
1726struct radeon_asic {
068a117c 1727 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1728 void (*fini)(struct radeon_device *rdev);
1729 int (*resume)(struct radeon_device *rdev);
1730 int (*suspend)(struct radeon_device *rdev);
28d52043 1731 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1732 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1733 /* ioctl hw specific callback. Some hw might want to perform special
1734 * operation on specific ioctl. For instance on wait idle some hw
1735 * might want to perform and HDP flush through MMIO as it seems that
1736 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1737 * through ring.
1738 */
1739 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1740 /* check if 3D engine is idle */
1741 bool (*gui_idle)(struct radeon_device *rdev);
1742 /* wait for mc_idle */
1743 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1744 /* get the reference clock */
1745 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1746 /* get the gpu clock counter */
1747 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1748 /* gart */
c5b3b850
AD		 1749 struct {
1750 void (*tlb_flush)(struct radeon_device *rdev);
1751 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1752 } gart;
05b07147
CK		 1753 struct {
1754 int (*init)(struct radeon_device *rdev);
1755 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1756 void (*set_page)(struct radeon_device *rdev,
1757 struct radeon_ib *ib,
1758 uint64_t pe,
dce34bfd
CK		 1759 uint64_t addr, unsigned count,
1760 uint32_t incr, uint32_t flags);
05b07147 1761 } vm;
54e88e06 1762 /* ring specific callbacks */
76a0df85 1763 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1764 /* irqs */
b35ea4ab
AD		 1765 struct {
1766 int (*set)(struct radeon_device *rdev);
1767 int (*process)(struct radeon_device *rdev);
1768 } irq;
54e88e06 1769 /* displays */
c79a49ca
AD		 1770 struct {
1771 /* display watermarks */
1772 void (*bandwidth_update)(struct radeon_device *rdev);
1773 /* get frame count */
1774 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1775 /* wait for vblank */
1776 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1777 /* set backlight level */
1778 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1779 /* get backlight level */
1780 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1781 /* audio callbacks */
1782 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1783 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1784 } display;
54e88e06 1785 /* copy functions for bo handling */
27cd7769
AD		 1786 struct {
1787 int (*blit)(struct radeon_device *rdev,
1788 uint64_t src_offset,
1789 uint64_t dst_offset,
1790 unsigned num_gpu_pages,
876dc9f3 1791 struct radeon_fence **fence);
27cd7769
AD		 1792 u32 blit_ring_index;
1793 int (*dma)(struct radeon_device *rdev,
1794 uint64_t src_offset,
1795 uint64_t dst_offset,
1796 unsigned num_gpu_pages,
876dc9f3 1797 struct radeon_fence **fence);
27cd7769
AD		 1798 u32 dma_ring_index;
1799 /* method used for bo copy */
1800 int (*copy)(struct radeon_device *rdev,
1801 uint64_t src_offset,
1802 uint64_t dst_offset,
1803 unsigned num_gpu_pages,
876dc9f3 1804 struct radeon_fence **fence);
27cd7769
AD		 1805 /* ring used for bo copies */
1806 u32 copy_ring_index;
1807 } copy;
54e88e06 1808 /* surfaces */
9e6f3d02
AD		 1809 struct {
1810 int (*set_reg)(struct radeon_device *rdev, int reg,
1811 uint32_t tiling_flags, uint32_t pitch,
1812 uint32_t offset, uint32_t obj_size);
1813 void (*clear_reg)(struct radeon_device *rdev, int reg);
1814 } surface;
54e88e06 1815 /* hotplug detect */
901ea57d
AD		 1816 struct {
1817 void (*init)(struct radeon_device *rdev);
1818 void (*fini)(struct radeon_device *rdev);
1819 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1820 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1821 } hpd;
da321c8a 1822 /* static power management */
a02fa397
AD		 1823 struct {
1824 void (*misc)(struct radeon_device *rdev);
1825 void (*prepare)(struct radeon_device *rdev);
1826 void (*finish)(struct radeon_device *rdev);
1827 void (*init_profile)(struct radeon_device *rdev);
1828 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1829 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1830 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1831 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1832 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1833 int (*get_pcie_lanes)(struct radeon_device *rdev);
1834 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1835 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1836 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1837 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1838 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1839 } pm;
da321c8a
AD		 1840 /* dynamic power management */
1841 struct {
1842 int (*init)(struct radeon_device *rdev);
1843 void (*setup_asic)(struct radeon_device *rdev);
1844 int (*enable)(struct radeon_device *rdev);
914a8987 1845 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1846 void (*disable)(struct radeon_device *rdev);
84dd1928 1847 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1848 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1849 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1850 void (*display_configuration_changed)(struct radeon_device *rdev);
1851 void (*fini)(struct radeon_device *rdev);
1852 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1853 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1854 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1855 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1856 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1857 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1858 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1859 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1860 } dpm;
6f34be50 1861 /* pageflipping */
0f9e006c
AD		 1862 struct {
1863 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1864 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1865 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1866 } pflip;
771fe6b9
JG		 1867};
1868
21f9a437
JG		 1869/*
1870 * Asic structures
1871 */
551ebd83 1872struct r100_asic {
225758d8
JG		 1873 const unsigned *reg_safe_bm;
1874 unsigned reg_safe_bm_size;
1875 u32 hdp_cntl;
551ebd83
DA		 1876};
1877
21f9a437 1878struct r300_asic {
225758d8
JG		 1879 const unsigned *reg_safe_bm;
1880 unsigned reg_safe_bm_size;
1881 u32 resync_scratch;
1882 u32 hdp_cntl;
21f9a437
JG		 1883};
1884
1885struct r600_asic {
225758d8
JG		 1886 unsigned max_pipes;
1887 unsigned max_tile_pipes;
1888 unsigned max_simds;
1889 unsigned max_backends;
1890 unsigned max_gprs;
1891 unsigned max_threads;
1892 unsigned max_stack_entries;
1893 unsigned max_hw_contexts;
1894 unsigned max_gs_threads;
1895 unsigned sx_max_export_size;
1896 unsigned sx_max_export_pos_size;
1897 unsigned sx_max_export_smx_size;
1898 unsigned sq_num_cf_insts;
1899 unsigned tiling_nbanks;
1900 unsigned tiling_npipes;
1901 unsigned tiling_group_size;
e7aeeba6 1902 unsigned tile_config;
e55b9422 1903 unsigned backend_map;
21f9a437
JG		 1904};
1905
1906struct rv770_asic {
225758d8
JG		 1907 unsigned max_pipes;
1908 unsigned max_tile_pipes;
1909 unsigned max_simds;
1910 unsigned max_backends;
1911 unsigned max_gprs;
1912 unsigned max_threads;
1913 unsigned max_stack_entries;
1914 unsigned max_hw_contexts;
1915 unsigned max_gs_threads;
1916 unsigned sx_max_export_size;
1917 unsigned sx_max_export_pos_size;
1918 unsigned sx_max_export_smx_size;
1919 unsigned sq_num_cf_insts;
1920 unsigned sx_num_of_sets;
1921 unsigned sc_prim_fifo_size;
1922 unsigned sc_hiz_tile_fifo_size;
1923 unsigned sc_earlyz_tile_fifo_fize;
1924 unsigned tiling_nbanks;
1925 unsigned tiling_npipes;
1926 unsigned tiling_group_size;
e7aeeba6 1927 unsigned tile_config;
e55b9422 1928 unsigned backend_map;
21f9a437
JG		 1929};
1930
32fcdbf4
AD		 1931struct evergreen_asic {
1932 unsigned num_ses;
1933 unsigned max_pipes;
1934 unsigned max_tile_pipes;
1935 unsigned max_simds;
1936 unsigned max_backends;
1937 unsigned max_gprs;
1938 unsigned max_threads;
1939 unsigned max_stack_entries;
1940 unsigned max_hw_contexts;
1941 unsigned max_gs_threads;
1942 unsigned sx_max_export_size;
1943 unsigned sx_max_export_pos_size;
1944 unsigned sx_max_export_smx_size;
1945 unsigned sq_num_cf_insts;
1946 unsigned sx_num_of_sets;
1947 unsigned sc_prim_fifo_size;
1948 unsigned sc_hiz_tile_fifo_size;
1949 unsigned sc_earlyz_tile_fifo_size;
1950 unsigned tiling_nbanks;
1951 unsigned tiling_npipes;
1952 unsigned tiling_group_size;
e7aeeba6 1953 unsigned tile_config;
e55b9422 1954 unsigned backend_map;
32fcdbf4
AD		 1955};
1956
fecf1d07
AD		 1957struct cayman_asic {
1958 unsigned max_shader_engines;
1959 unsigned max_pipes_per_simd;
1960 unsigned max_tile_pipes;
1961 unsigned max_simds_per_se;
1962 unsigned max_backends_per_se;
1963 unsigned max_texture_channel_caches;
1964 unsigned max_gprs;
1965 unsigned max_threads;
1966 unsigned max_gs_threads;
1967 unsigned max_stack_entries;
1968 unsigned sx_num_of_sets;
1969 unsigned sx_max_export_size;
1970 unsigned sx_max_export_pos_size;
1971 unsigned sx_max_export_smx_size;
1972 unsigned max_hw_contexts;
1973 unsigned sq_num_cf_insts;
1974 unsigned sc_prim_fifo_size;
1975 unsigned sc_hiz_tile_fifo_size;
1976 unsigned sc_earlyz_tile_fifo_size;
1977
1978 unsigned num_shader_engines;
1979 unsigned num_shader_pipes_per_simd;
1980 unsigned num_tile_pipes;
1981 unsigned num_simds_per_se;
1982 unsigned num_backends_per_se;
1983 unsigned backend_disable_mask_per_asic;
1984 unsigned backend_map;
1985 unsigned num_texture_channel_caches;
1986 unsigned mem_max_burst_length_bytes;
1987 unsigned mem_row_size_in_kb;
1988 unsigned shader_engine_tile_size;
1989 unsigned num_gpus;
1990 unsigned multi_gpu_tile_size;
1991
1992 unsigned tile_config;
fecf1d07
AD		 1993};
1994
0a96d72b
AD		 1995struct si_asic {
1996 unsigned max_shader_engines;
0a96d72b 1997 unsigned max_tile_pipes;
1a8ca750
AD		 1998 unsigned max_cu_per_sh;
1999 unsigned max_sh_per_se;
0a96d72b
AD		 2000 unsigned max_backends_per_se;
2001 unsigned max_texture_channel_caches;
2002 unsigned max_gprs;
2003 unsigned max_gs_threads;
2004 unsigned max_hw_contexts;
2005 unsigned sc_prim_fifo_size_frontend;
2006 unsigned sc_prim_fifo_size_backend;
2007 unsigned sc_hiz_tile_fifo_size;
2008 unsigned sc_earlyz_tile_fifo_size;
2009
0a96d72b 2010 unsigned num_tile_pipes;
439a1cff 2011 unsigned backend_enable_mask;
0a96d72b
AD		 2012 unsigned backend_disable_mask_per_asic;
2013 unsigned backend_map;
2014 unsigned num_texture_channel_caches;
2015 unsigned mem_max_burst_length_bytes;
2016 unsigned mem_row_size_in_kb;
2017 unsigned shader_engine_tile_size;
2018 unsigned num_gpus;
2019 unsigned multi_gpu_tile_size;
2020
2021 unsigned tile_config;
64d7b8be 2022 uint32_t tile_mode_array[32];
0a96d72b
AD		 2023};
2024
8cc1a532
AD		 2025struct cik_asic {
2026 unsigned max_shader_engines;
2027 unsigned max_tile_pipes;
2028 unsigned max_cu_per_sh;
2029 unsigned max_sh_per_se;
2030 unsigned max_backends_per_se;
2031 unsigned max_texture_channel_caches;
2032 unsigned max_gprs;
2033 unsigned max_gs_threads;
2034 unsigned max_hw_contexts;
2035 unsigned sc_prim_fifo_size_frontend;
2036 unsigned sc_prim_fifo_size_backend;
2037 unsigned sc_hiz_tile_fifo_size;
2038 unsigned sc_earlyz_tile_fifo_size;
2039
2040 unsigned num_tile_pipes;
439a1cff 2041 unsigned backend_enable_mask;
8cc1a532
AD		 2042 unsigned backend_disable_mask_per_asic;
2043 unsigned backend_map;
2044 unsigned num_texture_channel_caches;
2045 unsigned mem_max_burst_length_bytes;
2046 unsigned mem_row_size_in_kb;
2047 unsigned shader_engine_tile_size;
2048 unsigned num_gpus;
2049 unsigned multi_gpu_tile_size;
2050
2051 unsigned tile_config;
39aee490 2052 uint32_t tile_mode_array[32];
32f79a8a 2053 uint32_t macrotile_mode_array[16];
8cc1a532
AD		 2054};
2055
068a117c
JG		 2056union radeon_asic_config {
2057 struct r300_asic r300;
551ebd83 2058 struct r100_asic r100;
3ce0a23d
JG		 2059 struct r600_asic r600;
2060 struct rv770_asic rv770;
32fcdbf4 2061 struct evergreen_asic evergreen;
fecf1d07 2062 struct cayman_asic cayman;
0a96d72b 2063 struct si_asic si;
8cc1a532 2064 struct cik_asic cik;
068a117c
JG		 2065};
2066
0a10c851
DV		 2067/*
2068 * asic initizalization from radeon_asic.c
2069 */
2070void radeon_agp_disable(struct radeon_device *rdev);
2071int radeon_asic_init(struct radeon_device *rdev);
2072
771fe6b9
JG		 2073
2074/*
2075 * IOCTL.
2076 */
2077int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2078 struct drm_file *filp);
2079int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2080 struct drm_file *filp);
2081int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2082 struct drm_file *file_priv);
2083int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2084 struct drm_file *file_priv);
2085int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2086 struct drm_file *file_priv);
2087int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2088 struct drm_file *file_priv);
2089int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2090 struct drm_file *filp);
2091int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2092 struct drm_file *filp);
2093int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2094 struct drm_file *filp);
2095int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2096 struct drm_file *filp);
721604a1
JG		 2097int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2098 struct drm_file *filp);
771fe6b9 2099int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2100int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2101 struct drm_file *filp);
2102int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2103 struct drm_file *filp);
771fe6b9 2104
16cdf04d
AD		 2105/* VRAM scratch page for HDP bug, default vram page */
2106struct r600_vram_scratch {
87cbf8f2
AD		 2107 struct radeon_bo *robj;
2108 volatile uint32_t *ptr;
16cdf04d 2109 u64 gpu_addr;
87cbf8f2 2110};
771fe6b9 2111
fd64ca8a
LT		 2112/*
2113 * ACPI
2114 */
2115struct radeon_atif_notification_cfg {
2116 bool enabled;
2117 int command_code;
2118};
2119
2120struct radeon_atif_notifications {
2121 bool display_switch;
2122 bool expansion_mode_change;
2123 bool thermal_state;
2124 bool forced_power_state;
2125 bool system_power_state;
2126 bool display_conf_change;
2127 bool px_gfx_switch;
2128 bool brightness_change;
2129 bool dgpu_display_event;
2130};
2131
2132struct radeon_atif_functions {
2133 bool system_params;
2134 bool sbios_requests;
2135 bool select_active_disp;
2136 bool lid_state;
2137 bool get_tv_standard;
2138 bool set_tv_standard;
2139 bool get_panel_expansion_mode;
2140 bool set_panel_expansion_mode;
2141 bool temperature_change;
2142 bool graphics_device_types;
2143};
2144
2145struct radeon_atif {
2146 struct radeon_atif_notifications notifications;
2147 struct radeon_atif_functions functions;
2148 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2149 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2150};
7a1619b9 2151
e3a15920
AD		 2152struct radeon_atcs_functions {
2153 bool get_ext_state;
2154 bool pcie_perf_req;
2155 bool pcie_dev_rdy;
2156 bool pcie_bus_width;
2157};
2158
2159struct radeon_atcs {
2160 struct radeon_atcs_functions functions;
2161};
2162
771fe6b9
JG		 2163/*
2164 * Core structure, functions and helpers.
2165 */
2166typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2167typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2168
2169struct radeon_device {
9f022ddf 2170 struct device *dev;
771fe6b9
JG		 2171 struct drm_device *ddev;
2172 struct pci_dev *pdev;
dee53e7f 2173 struct rw_semaphore exclusive_lock;
771fe6b9 2174 /* ASIC */
068a117c 2175 union radeon_asic_config config;
771fe6b9
JG		 2176 enum radeon_family family;
2177 unsigned long flags;
2178 int usec_timeout;
2179 enum radeon_pll_errata pll_errata;
2180 int num_gb_pipes;
f779b3e5 2181 int num_z_pipes;
771fe6b9
JG		 2182 int disp_priority;
2183 /* BIOS */
2184 uint8_t *bios;
2185 bool is_atom_bios;
2186 uint16_t bios_header_start;
4c788679 2187 struct radeon_bo *stollen_vga_memory;
771fe6b9 2188 /* Register mmio */
4c9bc75c
DA		 2189 resource_size_t rmmio_base;
2190 resource_size_t rmmio_size;
2c385151
DV		 2191 /* protects concurrent MM_INDEX/DATA based register access */
2192 spinlock_t mmio_idx_lock;
fe78118c
AD		 2193 /* protects concurrent SMC based register access */
2194 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2195 /* protects concurrent PLL register access */
2196 spinlock_t pll_idx_lock;
2197 /* protects concurrent MC register access */
2198 spinlock_t mc_idx_lock;
2199 /* protects concurrent PCIE register access */
2200 spinlock_t pcie_idx_lock;
2201 /* protects concurrent PCIE_PORT register access */
2202 spinlock_t pciep_idx_lock;
2203 /* protects concurrent PIF register access */
2204 spinlock_t pif_idx_lock;
2205 /* protects concurrent CG register access */
2206 spinlock_t cg_idx_lock;
2207 /* protects concurrent UVD register access */
2208 spinlock_t uvd_idx_lock;
2209 /* protects concurrent RCU register access */
2210 spinlock_t rcu_idx_lock;
2211 /* protects concurrent DIDT register access */
2212 spinlock_t didt_idx_lock;
2213 /* protects concurrent ENDPOINT (audio) register access */
2214 spinlock_t end_idx_lock;
a0533fbf 2215 void __iomem *rmmio;
771fe6b9
JG		 2216 radeon_rreg_t mc_rreg;
2217 radeon_wreg_t mc_wreg;
2218 radeon_rreg_t pll_rreg;
2219 radeon_wreg_t pll_wreg;
de1b2898 2220 uint32_t pcie_reg_mask;
771fe6b9
JG		 2221 radeon_rreg_t pciep_rreg;
2222 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2223 /* io port */
2224 void __iomem *rio_mem;
2225 resource_size_t rio_mem_size;
771fe6b9
JG		 2226 struct radeon_clock clock;
2227 struct radeon_mc mc;
2228 struct radeon_gart gart;
2229 struct radeon_mode_info mode_info;
2230 struct radeon_scratch scratch;
75efdee1 2231 struct radeon_doorbell doorbell;
771fe6b9 2232 struct radeon_mman mman;
7465280c 2233 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2234 wait_queue_head_t fence_queue;
d6999bc7 2235 struct mutex ring_lock;
e32eb50d 2236 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2237 bool ib_pool_ready;
2238 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2239 struct radeon_irq irq;
2240 struct radeon_asic *asic;
2241 struct radeon_gem gem;
c93bb85b 2242 struct radeon_pm pm;
f2ba57b5 2243 struct radeon_uvd uvd;
d93f7937 2244 struct radeon_vce vce;
f657c2a7 2245 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2246 struct radeon_wb wb;
3ce0a23d 2247 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2248 bool shutdown;
2249 bool suspend;
ad49f501 2250 bool need_dma32;
733289c2 2251 bool accel_working;
a0a53aa8 2252 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2253 bool needs_reset;
e024e110 2254 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2255 const struct firmware *me_fw; /* all family ME firmware */
2256 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2257 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2258 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2259 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2260 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2261 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2262 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2263 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2264 const struct firmware *vce_fw; /* VCE firmware */
16cdf04d 2265 struct r600_vram_scratch vram_scratch;
3e5cb98d 2266 int msi_enabled; /* msi enabled */
d8f60cfc 2267 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2268 struct radeon_rlc rlc;
963e81f9 2269 struct radeon_mec mec;
d4877cf2 2270 struct work_struct hotplug_work;
f122c610 2271 struct work_struct audio_work;
8f61b34c 2272 struct work_struct reset_work;
18917b60 2273 int num_crtc; /* number of crtcs */
40bacf16 2274 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2275 bool has_uvd;
b530602f 2276 struct r600_audio audio; /* audio stuff */
ce8f5370 2277 struct notifier_block acpi_nb;
9eba4a93 2278 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2279 struct drm_file *hyperz_filp;
9eba4a93 2280 struct drm_file *cmask_filp;
f376b94f
AD		 2281 /* i2c buses */
2282 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2283 /* debugfs */
2284 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2285 unsigned debugfs_count;
721604a1
JG		 2286 /* virtual memory */
2287 struct radeon_vm_manager vm_manager;
6759a0a7 2288 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2289 /* ACPI interface */
2290 struct radeon_atif atif;
e3a15920 2291 struct radeon_atcs atcs;
f61d5b46
AD		 2292 /* srbm instance registers */
2293 struct mutex srbm_mutex;
64d8a728
AD		 2294 /* clock, powergating flags */
2295 u32 cg_flags;
2296 u32 pg_flags;
10ebc0bc
DA		 2297
2298 struct dev_pm_domain vga_pm_domain;
2299 bool have_disp_power_ref;
771fe6b9
JG		 2300};
2301
2302int radeon_device_init(struct radeon_device *rdev,
2303 struct drm_device *ddev,
2304 struct pci_dev *pdev,
2305 uint32_t flags);
2306void radeon_device_fini(struct radeon_device *rdev);
2307int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2308
2ef9bdfe
DV		 2309uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2310 bool always_indirect);
2311void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2312 bool always_indirect);
6fcbef7a
AK		 2313u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2314void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2315
d5754ab8
AL		 2316u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2317void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2318
4c788679
JG		 2319/*
2320 * Cast helper
2321 */
2322#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2323
2324/*
2325 * Registers read & write functions.
2326 */
a0533fbf
BH		 2327#define RREG8(reg) readb((rdev->rmmio) + (reg))
2328#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2329#define RREG16(reg) readw((rdev->rmmio) + (reg))
2330#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2331#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2332#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2333#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2334#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2335#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2336#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2337#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2338#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2339#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2340#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2341#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2342#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2343#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2344#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2345#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2346#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2347#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2348#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2349#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2350#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2351#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2352#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2353#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2354#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2355#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2356#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2357#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2358#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2359#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2360#define WREG32_P(reg, val, mask) \
2361 do { \
2362 uint32_t tmp_ = RREG32(reg); \
2363 tmp_ &= (mask); \
2364 tmp_ |= ((val) & ~(mask)); \
2365 WREG32(reg, tmp_); \
2366 } while (0)
d5169fc4 2367#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2368#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2369#define WREG32_PLL_P(reg, val, mask) \
2370 do { \
2371 uint32_t tmp_ = RREG32_PLL(reg); \
2372 tmp_ &= (mask); \
2373 tmp_ |= ((val) & ~(mask)); \
2374 WREG32_PLL(reg, tmp_); \
2375 } while (0)
2ef9bdfe 2376#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2377#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2378#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2379
d5754ab8
AL		 2380#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2381#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2382
de1b2898
DA		 2383/*
2384 * Indirect registers accessor
2385 */
2386static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2387{
0a5b7b0b 2388 unsigned long flags;
de1b2898
DA		 2389 uint32_t r;
2390
0a5b7b0b 2391 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2392 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2393 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2394 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2395 return r;
2396}
2397
2398static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2399{
0a5b7b0b
AD		 2400 unsigned long flags;
2401
2402 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2403 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2404 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2405 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2406}
2407
1d5d0c34
AD		 2408static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2409{
fe78118c 2410 unsigned long flags;
1d5d0c34
AD		 2411 u32 r;
2412
fe78118c 2413 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2414 WREG32(TN_SMC_IND_INDEX_0, (reg));
2415 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2416 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2417 return r;
2418}
2419
2420static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2421{
fe78118c
AD		 2422 unsigned long flags;
2423
2424 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2425 WREG32(TN_SMC_IND_INDEX_0, (reg));
2426 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2427 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2428}
2429
ff82bbc4
AD		 2430static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2431{
0a5b7b0b 2432 unsigned long flags;
ff82bbc4
AD		 2433 u32 r;
2434
0a5b7b0b 2435 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2436 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2437 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2438 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2439 return r;
2440}
2441
2442static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2443{
0a5b7b0b
AD		 2444 unsigned long flags;
2445
2446 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2447 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2448 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2449 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2450}
2451
46f9564a
AD		 2452static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2453{
0a5b7b0b 2454 unsigned long flags;
46f9564a
AD		 2455 u32 r;
2456
0a5b7b0b 2457 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2458 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2459 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2460 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2461 return r;
2462}
2463
2464static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2465{
0a5b7b0b
AD		 2466 unsigned long flags;
2467
2468 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2469 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2470 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2471 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2472}
2473
792edd69
AD		 2474static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2475{
0a5b7b0b 2476 unsigned long flags;
792edd69
AD		 2477 u32 r;
2478
0a5b7b0b 2479 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2480 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2481 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2482 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2483 return r;
2484}
2485
2486static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2487{
0a5b7b0b
AD		 2488 unsigned long flags;
2489
2490 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2491 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2492 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2493 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2494}
2495
2496static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2497{
0a5b7b0b 2498 unsigned long flags;
792edd69
AD		 2499 u32 r;
2500
0a5b7b0b 2501 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2502 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2503 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2504 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2505 return r;
2506}
2507
2508static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2509{
0a5b7b0b
AD		 2510 unsigned long flags;
2511
2512 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2513 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2514 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2515 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2516}
2517
93656cdd
AD		 2518static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2519{
0a5b7b0b 2520 unsigned long flags;
93656cdd
AD		 2521 u32 r;
2522
0a5b7b0b 2523 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2524 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2525 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2526 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2527 return r;
2528}
2529
2530static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2531{
0a5b7b0b
AD		 2532 unsigned long flags;
2533
2534 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2535 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2536 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2537 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2538}
2539
1d58234d
AD		 2540
2541static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2542{
0a5b7b0b 2543 unsigned long flags;
1d58234d
AD		 2544 u32 r;
2545
0a5b7b0b 2546 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2547 WREG32(CIK_DIDT_IND_INDEX, (reg));
2548 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2549 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2550 return r;
2551}
2552
2553static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2554{
0a5b7b0b
AD		 2555 unsigned long flags;
2556
2557 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2558 WREG32(CIK_DIDT_IND_INDEX, (reg));
2559 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2560 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2561}
2562
771fe6b9
JG		 2563void r100_pll_errata_after_index(struct radeon_device *rdev);
2564
2565
2566/*
2567 * ASICs helpers.
2568 */
b995e433
DA		 2569#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2570 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2571#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2572 (rdev->family == CHIP_RV200) || \
2573 (rdev->family == CHIP_RS100) || \
2574 (rdev->family == CHIP_RS200) || \
2575 (rdev->family == CHIP_RV250) || \
2576 (rdev->family == CHIP_RV280) || \
2577 (rdev->family == CHIP_RS300))
2578#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2579 (rdev->family == CHIP_RV350) || \
2580 (rdev->family == CHIP_R350) || \
2581 (rdev->family == CHIP_RV380) || \
2582 (rdev->family == CHIP_R420) || \
2583 (rdev->family == CHIP_R423) || \
2584 (rdev->family == CHIP_RV410) || \
2585 (rdev->family == CHIP_RS400) || \
2586 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2587#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2588 (rdev->ddev->pdev->device == 0x9443) || \
2589 (rdev->ddev->pdev->device == 0x944B) || \
2590 (rdev->ddev->pdev->device == 0x9506) || \
2591 (rdev->ddev->pdev->device == 0x9509) || \
2592 (rdev->ddev->pdev->device == 0x950F) || \
2593 (rdev->ddev->pdev->device == 0x689C) || \
2594 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2595#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2596#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2597 (rdev->family == CHIP_RS690) || \
2598 (rdev->family == CHIP_RS740) || \
2599 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2600#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2601#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2602#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2603#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2604 (rdev->flags & RADEON_IS_IGP))
1fe18305 2605#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2606#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2607#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2608 (rdev->flags & RADEON_IS_IGP))
624d3524 2609#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2610#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2611#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2612
dc50ba7f
AD		 2613#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2614 (rdev->ddev->pdev->device == 0x6850) || \
2615 (rdev->ddev->pdev->device == 0x6858) || \
2616 (rdev->ddev->pdev->device == 0x6859) || \
2617 (rdev->ddev->pdev->device == 0x6840) || \
2618 (rdev->ddev->pdev->device == 0x6841) || \
2619 (rdev->ddev->pdev->device == 0x6842) || \
2620 (rdev->ddev->pdev->device == 0x6843))
2621
771fe6b9
JG		 2622/*
2623 * BIOS helpers.
2624 */
2625#define RBIOS8(i) (rdev->bios[i])
2626#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2627#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2628
2629int radeon_combios_init(struct radeon_device *rdev);
2630void radeon_combios_fini(struct radeon_device *rdev);
2631int radeon_atombios_init(struct radeon_device *rdev);
2632void radeon_atombios_fini(struct radeon_device *rdev);
2633
2634
2635/*
2636 * RING helpers.
2637 */
ce580fab 2638#if DRM_DEBUG_CODE == 0
e32eb50d 2639static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2640{
e32eb50d
CK		 2641 ring->ring[ring->wptr++] = v;
2642 ring->wptr &= ring->ptr_mask;
2643 ring->count_dw--;
2644 ring->ring_free_dw--;
771fe6b9 2645}
ce580fab
AK		 2646#else
2647/* With debugging this is just too big to inline */
e32eb50d 2648void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2649#endif
771fe6b9
JG		 2650
2651/*
2652 * ASICs macro.
2653 */
068a117c 2654#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2655#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2656#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2657#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2658#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2659#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2660#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2661#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2662#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2663#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2664#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2665#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2666#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2667#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2668#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2669#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2670#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2671#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2672#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2673#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2674#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2675#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2676#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2677#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2678#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2679#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2680#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2681#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2682#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2683#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2684#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2685#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2686#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2687#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2688#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2689#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2690#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2691#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2692#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2693#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2694#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2695#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2696#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2697#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2698#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2699#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2700#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2701#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2702#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2703#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2704#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2705#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2706#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2707#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2708#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2709#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2710#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2711#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2712#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2713#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2714#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2715#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2716#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2717#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2718#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2719#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2720#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2721#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2722#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2723#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2724#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2725#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2726#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2727#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2728#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2729#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2730#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2731#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2732#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2733#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2734#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2735#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2736#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2737#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2738#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2739
6cf8a3f5 2740/* Common functions */
700a0cc0 2741/* AGP */
90aca4d2 2742extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2743extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2744extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2745extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2746extern int radeon_modeset_init(struct radeon_device *rdev);
2747extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2748extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2749extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2750extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2751extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2752extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2753extern void radeon_wb_fini(struct radeon_device *rdev);
2754extern int radeon_wb_init(struct radeon_device *rdev);
2755extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2756extern void radeon_surface_init(struct radeon_device *rdev);
2757extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2758extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2759extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2760extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2761extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2762extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2763extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2764extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2765extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2766extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2767extern void radeon_program_register_sequence(struct radeon_device *rdev,
2768 const u32 *registers,
2769 const u32 array_size);
6cf8a3f5 2770
721604a1
JG		 2771/*
2772 * vm
2773 */
2774int radeon_vm_manager_init(struct radeon_device *rdev);
2775void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2776void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2777void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2778int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2779void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2780struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2781 struct radeon_vm *vm, int ring);
2782void radeon_vm_fence(struct radeon_device *rdev,
2783 struct radeon_vm *vm,
2784 struct radeon_fence *fence);
dce34bfd 2785uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
9c57a6bd
CK		 2786int radeon_vm_bo_update(struct radeon_device *rdev,
2787 struct radeon_vm *vm,
2788 struct radeon_bo *bo,
2789 struct ttm_mem_reg *mem);
721604a1
JG		 2790void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2791 struct radeon_bo *bo);
421ca7ab
CK		 2792struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2793 struct radeon_bo *bo);
e971bd5e
CK		 2794struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2795 struct radeon_vm *vm,
2796 struct radeon_bo *bo);
2797int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2798 struct radeon_bo_va *bo_va,
2799 uint64_t offset,
2800 uint32_t flags);
721604a1 2801int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2802 struct radeon_bo_va *bo_va);
721604a1 2803
f122c610
AD		 2804/* audio */
2805void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2806struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2807struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
721604a1 2808
16cdf04d
AD		 2809/*
2810 * R600 vram scratch functions
2811 */
2812int r600_vram_scratch_init(struct radeon_device *rdev);
2813void r600_vram_scratch_fini(struct radeon_device *rdev);
2814
285484e2
JG		 2815/*
2816 * r600 cs checking helper
2817 */
2818unsigned r600_mip_minify(unsigned size, unsigned level);
2819bool r600_fmt_is_valid_color(u32 format);
2820bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2821int r600_fmt_get_blocksize(u32 format);
2822int r600_fmt_get_nblocksx(u32 format, u32 w);
2823int r600_fmt_get_nblocksy(u32 format, u32 h);
2824
3574dda4
DV		 2825/*
2826 * r600 functions used by radeon_encoder.c
2827 */
1b688d08
RM		 2828struct radeon_hdmi_acr {
2829 u32 clock;
2830
2831 int n_32khz;
2832 int cts_32khz;
2833
2834 int n_44_1khz;
2835 int cts_44_1khz;
2836
2837 int n_48khz;
2838 int cts_48khz;
2839
2840};
2841
e55d3e6c
RM		 2842extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2843
416a2bd2
AD		 2844extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2845 u32 tiling_pipe_num,
2846 u32 max_rb_num,
2847 u32 total_max_rb_num,
2848 u32 enabled_rb_mask);
fe251e2f 2849
e55d3e6c
RM		 2850/*
2851 * evergreen functions used by radeon_encoder.c
2852 */
2853
0af62b01 2854extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2855extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2856
c4917074
AD		 2857/* radeon_acpi.c */
2858#if defined(CONFIG_ACPI)
2859extern int radeon_acpi_init(struct radeon_device *rdev);
2860extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2861extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2862extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2863 u8 perf_req, bool advertise);
dc50ba7f 2864extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2865#else
2866static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2867static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2868#endif
d7a2952f 2869
c38f34b5
IH		 2870int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2871 struct radeon_cs_packet *pkt,
2872 unsigned idx);
9ffb7a6d 2873bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2874void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2875 struct radeon_cs_packet *pkt);
e9716993
IH		 2876int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2877 struct radeon_cs_reloc **cs_reloc,
2878 int nomm);
40592a17
IH		 2879int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2880 uint32_t *vline_start_end,
2881 uint32_t *vline_status);
c38f34b5 2882
4c788679
JG		 2883#include "radeon_object.h"
2884
771fe6b9 2885#endif
Linux 6.x block layer and io_uring tree(s)