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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
31 | #include "radeon_object.h" | |
32 | ||
33 | /* TODO: Here are things that needs to be done : | |
34 | * - surface allocator & initializer : (bit like scratch reg) should | |
35 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
36 | * related to surface | |
37 | * - WB : write back stuff (do it bit like scratch reg things) | |
38 | * - Vblank : look at Jesse's rework and what we should do | |
39 | * - r600/r700: gart & cp | |
40 | * - cs : clean cs ioctl use bitmap & things like that. | |
41 | * - power management stuff | |
42 | * - Barrier in gart code | |
43 | * - Unmappabled vram ? | |
44 | * - TESTING, TESTING, TESTING | |
45 | */ | |
46 | ||
d39c3b89 JG |
47 | /* Initialization path: |
48 | * We expect that acceleration initialization might fail for various | |
49 | * reasons even thought we work hard to make it works on most | |
50 | * configurations. In order to still have a working userspace in such | |
51 | * situation the init path must succeed up to the memory controller | |
52 | * initialization point. Failure before this point are considered as | |
53 | * fatal error. Here is the init callchain : | |
54 | * radeon_device_init perform common structure, mutex initialization | |
55 | * asic_init setup the GPU memory layout and perform all | |
56 | * one time initialization (failure in this | |
57 | * function are considered fatal) | |
58 | * asic_startup setup the GPU acceleration, in order to | |
59 | * follow guideline the first thing this | |
60 | * function should do is setting the GPU | |
61 | * memory controller (only MC setup failure | |
62 | * are considered as fatal) | |
63 | */ | |
64 | ||
771fe6b9 JG |
65 | #include <asm/atomic.h> |
66 | #include <linux/wait.h> | |
67 | #include <linux/list.h> | |
68 | #include <linux/kref.h> | |
69 | ||
c2142715 | 70 | #include "radeon_family.h" |
771fe6b9 JG |
71 | #include "radeon_mode.h" |
72 | #include "radeon_reg.h" | |
771fe6b9 JG |
73 | |
74 | /* | |
75 | * Modules parameters. | |
76 | */ | |
77 | extern int radeon_no_wb; | |
78 | extern int radeon_modeset; | |
79 | extern int radeon_dynclks; | |
80 | extern int radeon_r4xx_atom; | |
81 | extern int radeon_agpmode; | |
82 | extern int radeon_vram_limit; | |
83 | extern int radeon_gart_size; | |
84 | extern int radeon_benchmarking; | |
ecc0b326 | 85 | extern int radeon_testing; |
771fe6b9 | 86 | extern int radeon_connector_table; |
4ce001ab | 87 | extern int radeon_tv; |
771fe6b9 JG |
88 | |
89 | /* | |
90 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
91 | * symbol; | |
92 | */ | |
93 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | |
94 | #define RADEON_IB_POOL_SIZE 16 | |
95 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 | |
96 | #define RADEONFB_CONN_LIMIT 4 | |
f657c2a7 | 97 | #define RADEON_BIOS_NUM_SCRATCH 8 |
771fe6b9 | 98 | |
771fe6b9 JG |
99 | /* |
100 | * Errata workarounds. | |
101 | */ | |
102 | enum radeon_pll_errata { | |
103 | CHIP_ERRATA_R300_CG = 0x00000001, | |
104 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
105 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
106 | }; | |
107 | ||
108 | ||
109 | struct radeon_device; | |
110 | ||
111 | ||
112 | /* | |
113 | * BIOS. | |
114 | */ | |
115 | bool radeon_get_bios(struct radeon_device *rdev); | |
116 | ||
3ce0a23d | 117 | |
771fe6b9 | 118 | /* |
3ce0a23d | 119 | * Dummy page |
771fe6b9 | 120 | */ |
3ce0a23d JG |
121 | struct radeon_dummy_page { |
122 | struct page *page; | |
123 | dma_addr_t addr; | |
124 | }; | |
125 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
126 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
127 | ||
771fe6b9 | 128 | |
3ce0a23d JG |
129 | /* |
130 | * Clocks | |
131 | */ | |
771fe6b9 JG |
132 | struct radeon_clock { |
133 | struct radeon_pll p1pll; | |
134 | struct radeon_pll p2pll; | |
135 | struct radeon_pll spll; | |
136 | struct radeon_pll mpll; | |
137 | /* 10 Khz units */ | |
138 | uint32_t default_mclk; | |
139 | uint32_t default_sclk; | |
140 | }; | |
141 | ||
3ce0a23d | 142 | |
771fe6b9 JG |
143 | /* |
144 | * Fences. | |
145 | */ | |
146 | struct radeon_fence_driver { | |
147 | uint32_t scratch_reg; | |
148 | atomic_t seq; | |
149 | uint32_t last_seq; | |
150 | unsigned long count_timeout; | |
151 | wait_queue_head_t queue; | |
152 | rwlock_t lock; | |
153 | struct list_head created; | |
154 | struct list_head emited; | |
155 | struct list_head signaled; | |
156 | }; | |
157 | ||
158 | struct radeon_fence { | |
159 | struct radeon_device *rdev; | |
160 | struct kref kref; | |
161 | struct list_head list; | |
162 | /* protected by radeon_fence.lock */ | |
163 | uint32_t seq; | |
164 | unsigned long timeout; | |
165 | bool emited; | |
166 | bool signaled; | |
167 | }; | |
168 | ||
169 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
170 | void radeon_fence_driver_fini(struct radeon_device *rdev); | |
171 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); | |
172 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); | |
173 | void radeon_fence_process(struct radeon_device *rdev); | |
174 | bool radeon_fence_signaled(struct radeon_fence *fence); | |
175 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
176 | int radeon_fence_wait_next(struct radeon_device *rdev); | |
177 | int radeon_fence_wait_last(struct radeon_device *rdev); | |
178 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); | |
179 | void radeon_fence_unref(struct radeon_fence **fence); | |
180 | ||
e024e110 DA |
181 | /* |
182 | * Tiling registers | |
183 | */ | |
184 | struct radeon_surface_reg { | |
185 | struct radeon_object *robj; | |
186 | }; | |
187 | ||
188 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
189 | |
190 | /* | |
191 | * Radeon buffer. | |
192 | */ | |
193 | struct radeon_object; | |
194 | ||
195 | struct radeon_object_list { | |
196 | struct list_head list; | |
197 | struct radeon_object *robj; | |
198 | uint64_t gpu_offset; | |
199 | unsigned rdomain; | |
200 | unsigned wdomain; | |
e024e110 | 201 | uint32_t tiling_flags; |
771fe6b9 JG |
202 | }; |
203 | ||
204 | int radeon_object_init(struct radeon_device *rdev); | |
205 | void radeon_object_fini(struct radeon_device *rdev); | |
206 | int radeon_object_create(struct radeon_device *rdev, | |
207 | struct drm_gem_object *gobj, | |
208 | unsigned long size, | |
209 | bool kernel, | |
210 | uint32_t domain, | |
211 | bool interruptible, | |
212 | struct radeon_object **robj_ptr); | |
213 | int radeon_object_kmap(struct radeon_object *robj, void **ptr); | |
214 | void radeon_object_kunmap(struct radeon_object *robj); | |
215 | void radeon_object_unref(struct radeon_object **robj); | |
216 | int radeon_object_pin(struct radeon_object *robj, uint32_t domain, | |
217 | uint64_t *gpu_addr); | |
218 | void radeon_object_unpin(struct radeon_object *robj); | |
219 | int radeon_object_wait(struct radeon_object *robj); | |
cefb87ef | 220 | int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement); |
771fe6b9 JG |
221 | int radeon_object_evict_vram(struct radeon_device *rdev); |
222 | int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset); | |
223 | void radeon_object_force_delete(struct radeon_device *rdev); | |
224 | void radeon_object_list_add_object(struct radeon_object_list *lobj, | |
225 | struct list_head *head); | |
226 | int radeon_object_list_validate(struct list_head *head, void *fence); | |
227 | void radeon_object_list_unvalidate(struct list_head *head); | |
228 | void radeon_object_list_clean(struct list_head *head); | |
229 | int radeon_object_fbdev_mmap(struct radeon_object *robj, | |
230 | struct vm_area_struct *vma); | |
231 | unsigned long radeon_object_size(struct radeon_object *robj); | |
e024e110 DA |
232 | void radeon_object_clear_surface_reg(struct radeon_object *robj); |
233 | int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved, | |
234 | bool force_drop); | |
235 | void radeon_object_set_tiling_flags(struct radeon_object *robj, | |
236 | uint32_t tiling_flags, uint32_t pitch); | |
237 | void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch); | |
238 | void radeon_bo_move_notify(struct ttm_buffer_object *bo, | |
239 | struct ttm_mem_reg *mem); | |
240 | void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo); | |
771fe6b9 JG |
241 | /* |
242 | * GEM objects. | |
243 | */ | |
244 | struct radeon_gem { | |
245 | struct list_head objects; | |
246 | }; | |
247 | ||
248 | int radeon_gem_init(struct radeon_device *rdev); | |
249 | void radeon_gem_fini(struct radeon_device *rdev); | |
250 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
251 | int alignment, int initial_domain, | |
252 | bool discardable, bool kernel, | |
253 | bool interruptible, | |
254 | struct drm_gem_object **obj); | |
255 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, | |
256 | uint64_t *gpu_addr); | |
257 | void radeon_gem_object_unpin(struct drm_gem_object *obj); | |
258 | ||
259 | ||
260 | /* | |
261 | * GART structures, functions & helpers | |
262 | */ | |
263 | struct radeon_mc; | |
264 | ||
265 | struct radeon_gart_table_ram { | |
266 | volatile uint32_t *ptr; | |
267 | }; | |
268 | ||
269 | struct radeon_gart_table_vram { | |
270 | struct radeon_object *robj; | |
271 | volatile uint32_t *ptr; | |
272 | }; | |
273 | ||
274 | union radeon_gart_table { | |
275 | struct radeon_gart_table_ram ram; | |
276 | struct radeon_gart_table_vram vram; | |
277 | }; | |
278 | ||
a77f1718 MT |
279 | #define RADEON_GPU_PAGE_SIZE 4096 |
280 | ||
771fe6b9 JG |
281 | struct radeon_gart { |
282 | dma_addr_t table_addr; | |
283 | unsigned num_gpu_pages; | |
284 | unsigned num_cpu_pages; | |
285 | unsigned table_size; | |
286 | union radeon_gart_table table; | |
287 | struct page **pages; | |
288 | dma_addr_t *pages_addr; | |
289 | bool ready; | |
290 | }; | |
291 | ||
292 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
293 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
294 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
295 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
296 | int radeon_gart_init(struct radeon_device *rdev); | |
297 | void radeon_gart_fini(struct radeon_device *rdev); | |
298 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
299 | int pages); | |
300 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
301 | int pages, struct page **pagelist); | |
302 | ||
303 | ||
304 | /* | |
305 | * GPU MC structures, functions & helpers | |
306 | */ | |
307 | struct radeon_mc { | |
308 | resource_size_t aper_size; | |
309 | resource_size_t aper_base; | |
310 | resource_size_t agp_base; | |
7a50f01a DA |
311 | /* for some chips with <= 32MB we need to lie |
312 | * about vram size near mc fb location */ | |
3ce0a23d JG |
313 | u64 mc_vram_size; |
314 | u64 gtt_location; | |
315 | u64 gtt_size; | |
316 | u64 gtt_start; | |
317 | u64 gtt_end; | |
318 | u64 vram_location; | |
319 | u64 vram_start; | |
320 | u64 vram_end; | |
771fe6b9 | 321 | unsigned vram_width; |
3ce0a23d | 322 | u64 real_vram_size; |
771fe6b9 JG |
323 | int vram_mtrr; |
324 | bool vram_is_ddr; | |
325 | }; | |
326 | ||
327 | int radeon_mc_setup(struct radeon_device *rdev); | |
328 | ||
329 | ||
330 | /* | |
331 | * GPU scratch registers structures, functions & helpers | |
332 | */ | |
333 | struct radeon_scratch { | |
334 | unsigned num_reg; | |
335 | bool free[32]; | |
336 | uint32_t reg[32]; | |
337 | }; | |
338 | ||
339 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
340 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
341 | ||
342 | ||
343 | /* | |
344 | * IRQS. | |
345 | */ | |
346 | struct radeon_irq { | |
347 | bool installed; | |
348 | bool sw_int; | |
349 | /* FIXME: use a define max crtc rather than hardcode it */ | |
350 | bool crtc_vblank_int[2]; | |
351 | }; | |
352 | ||
353 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
354 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
355 | ||
356 | ||
357 | /* | |
358 | * CP & ring. | |
359 | */ | |
360 | struct radeon_ib { | |
361 | struct list_head list; | |
362 | unsigned long idx; | |
363 | uint64_t gpu_addr; | |
364 | struct radeon_fence *fence; | |
513bcb46 | 365 | uint32_t *ptr; |
771fe6b9 JG |
366 | uint32_t length_dw; |
367 | }; | |
368 | ||
ecb114a1 DA |
369 | /* |
370 | * locking - | |
371 | * mutex protects scheduled_ibs, ready, alloc_bm | |
372 | */ | |
771fe6b9 JG |
373 | struct radeon_ib_pool { |
374 | struct mutex mutex; | |
375 | struct radeon_object *robj; | |
376 | struct list_head scheduled_ibs; | |
377 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; | |
378 | bool ready; | |
379 | DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); | |
380 | }; | |
381 | ||
382 | struct radeon_cp { | |
383 | struct radeon_object *ring_obj; | |
384 | volatile uint32_t *ring; | |
385 | unsigned rptr; | |
386 | unsigned wptr; | |
387 | unsigned wptr_old; | |
388 | unsigned ring_size; | |
389 | unsigned ring_free_dw; | |
390 | int count_dw; | |
391 | uint64_t gpu_addr; | |
392 | uint32_t align_mask; | |
393 | uint32_t ptr_mask; | |
394 | struct mutex mutex; | |
395 | bool ready; | |
396 | }; | |
397 | ||
3ce0a23d JG |
398 | struct r600_blit { |
399 | struct radeon_object *shader_obj; | |
400 | u64 shader_gpu_addr; | |
401 | u32 vs_offset, ps_offset; | |
402 | u32 state_offset; | |
403 | u32 state_len; | |
404 | u32 vb_used, vb_total; | |
405 | struct radeon_ib *vb_ib; | |
406 | }; | |
407 | ||
771fe6b9 JG |
408 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
409 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); | |
410 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); | |
411 | int radeon_ib_pool_init(struct radeon_device *rdev); | |
412 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
413 | int radeon_ib_test(struct radeon_device *rdev); | |
414 | /* Ring access between begin & end cannot sleep */ | |
415 | void radeon_ring_free_size(struct radeon_device *rdev); | |
416 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); | |
417 | void radeon_ring_unlock_commit(struct radeon_device *rdev); | |
418 | void radeon_ring_unlock_undo(struct radeon_device *rdev); | |
419 | int radeon_ring_test(struct radeon_device *rdev); | |
420 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
421 | void radeon_ring_fini(struct radeon_device *rdev); | |
422 | ||
423 | ||
424 | /* | |
425 | * CS. | |
426 | */ | |
427 | struct radeon_cs_reloc { | |
428 | struct drm_gem_object *gobj; | |
429 | struct radeon_object *robj; | |
430 | struct radeon_object_list lobj; | |
431 | uint32_t handle; | |
432 | uint32_t flags; | |
433 | }; | |
434 | ||
435 | struct radeon_cs_chunk { | |
436 | uint32_t chunk_id; | |
437 | uint32_t length_dw; | |
513bcb46 DA |
438 | int kpage_idx[2]; |
439 | uint32_t *kpage[2]; | |
771fe6b9 | 440 | uint32_t *kdata; |
513bcb46 DA |
441 | void __user *user_ptr; |
442 | int last_copied_page; | |
443 | int last_page_index; | |
771fe6b9 JG |
444 | }; |
445 | ||
446 | struct radeon_cs_parser { | |
447 | struct radeon_device *rdev; | |
448 | struct drm_file *filp; | |
449 | /* chunks */ | |
450 | unsigned nchunks; | |
451 | struct radeon_cs_chunk *chunks; | |
452 | uint64_t *chunks_array; | |
453 | /* IB */ | |
454 | unsigned idx; | |
455 | /* relocations */ | |
456 | unsigned nrelocs; | |
457 | struct radeon_cs_reloc *relocs; | |
458 | struct radeon_cs_reloc **relocs_ptr; | |
459 | struct list_head validated; | |
460 | /* indices of various chunks */ | |
461 | int chunk_ib_idx; | |
462 | int chunk_relocs_idx; | |
463 | struct radeon_ib *ib; | |
464 | void *track; | |
3ce0a23d | 465 | unsigned family; |
513bcb46 | 466 | int parser_error; |
771fe6b9 JG |
467 | }; |
468 | ||
513bcb46 DA |
469 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
470 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); | |
471 | ||
472 | ||
473 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | |
474 | { | |
475 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
476 | u32 pg_idx, pg_offset; | |
477 | u32 idx_value = 0; | |
478 | int new_page; | |
479 | ||
480 | pg_idx = (idx * 4) / PAGE_SIZE; | |
481 | pg_offset = (idx * 4) % PAGE_SIZE; | |
482 | ||
483 | if (ibc->kpage_idx[0] == pg_idx) | |
484 | return ibc->kpage[0][pg_offset/4]; | |
485 | if (ibc->kpage_idx[1] == pg_idx) | |
486 | return ibc->kpage[1][pg_offset/4]; | |
487 | ||
488 | new_page = radeon_cs_update_pages(p, pg_idx); | |
489 | if (new_page < 0) { | |
490 | p->parser_error = new_page; | |
491 | return 0; | |
492 | } | |
493 | ||
494 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
495 | return idx_value; | |
496 | } | |
497 | ||
771fe6b9 JG |
498 | struct radeon_cs_packet { |
499 | unsigned idx; | |
500 | unsigned type; | |
501 | unsigned reg; | |
502 | unsigned opcode; | |
503 | int count; | |
504 | unsigned one_reg_wr; | |
505 | }; | |
506 | ||
507 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
508 | struct radeon_cs_packet *pkt, | |
509 | unsigned idx, unsigned reg); | |
510 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
511 | struct radeon_cs_packet *pkt); | |
512 | ||
513 | ||
514 | /* | |
515 | * AGP | |
516 | */ | |
517 | int radeon_agp_init(struct radeon_device *rdev); | |
518 | void radeon_agp_fini(struct radeon_device *rdev); | |
519 | ||
520 | ||
521 | /* | |
522 | * Writeback | |
523 | */ | |
524 | struct radeon_wb { | |
525 | struct radeon_object *wb_obj; | |
526 | volatile uint32_t *wb; | |
527 | uint64_t gpu_addr; | |
528 | }; | |
529 | ||
c93bb85b JG |
530 | /** |
531 | * struct radeon_pm - power management datas | |
532 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
533 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
534 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
535 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
536 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
537 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
538 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
539 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
540 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
541 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) | |
542 | * @needed_bandwidth: current bandwidth needs | |
543 | * | |
544 | * It keeps track of various data needed to take powermanagement decision. | |
545 | * Bandwith need is used to determine minimun clock of the GPU and memory. | |
546 | * Equation between gpu/memory clock and available bandwidth is hw dependent | |
547 | * (type of memory, bus size, efficiency, ...) | |
548 | */ | |
549 | struct radeon_pm { | |
550 | fixed20_12 max_bandwidth; | |
551 | fixed20_12 igp_sideport_mclk; | |
552 | fixed20_12 igp_system_mclk; | |
553 | fixed20_12 igp_ht_link_clk; | |
554 | fixed20_12 igp_ht_link_width; | |
555 | fixed20_12 k8_bandwidth; | |
556 | fixed20_12 sideport_bandwidth; | |
557 | fixed20_12 ht_bandwidth; | |
558 | fixed20_12 core_bandwidth; | |
559 | fixed20_12 sclk; | |
560 | fixed20_12 needed_bandwidth; | |
561 | }; | |
562 | ||
771fe6b9 JG |
563 | |
564 | /* | |
565 | * Benchmarking | |
566 | */ | |
567 | void radeon_benchmark(struct radeon_device *rdev); | |
568 | ||
569 | ||
ecc0b326 MD |
570 | /* |
571 | * Testing | |
572 | */ | |
573 | void radeon_test_moves(struct radeon_device *rdev); | |
574 | ||
575 | ||
771fe6b9 JG |
576 | /* |
577 | * Debugfs | |
578 | */ | |
579 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
580 | struct drm_info_list *files, | |
581 | unsigned nfiles); | |
582 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
583 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); | |
584 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
585 | ||
586 | ||
587 | /* | |
588 | * ASIC specific functions. | |
589 | */ | |
590 | struct radeon_asic { | |
068a117c | 591 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
592 | void (*fini)(struct radeon_device *rdev); |
593 | int (*resume)(struct radeon_device *rdev); | |
594 | int (*suspend)(struct radeon_device *rdev); | |
771fe6b9 | 595 | int (*gpu_reset)(struct radeon_device *rdev); |
771fe6b9 JG |
596 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
597 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
598 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); | |
599 | void (*cp_fini)(struct radeon_device *rdev); | |
600 | void (*cp_disable)(struct radeon_device *rdev); | |
3ce0a23d | 601 | void (*cp_commit)(struct radeon_device *rdev); |
771fe6b9 | 602 | void (*ring_start)(struct radeon_device *rdev); |
3ce0a23d JG |
603 | int (*ring_test)(struct radeon_device *rdev); |
604 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
771fe6b9 JG |
605 | int (*irq_set)(struct radeon_device *rdev); |
606 | int (*irq_process)(struct radeon_device *rdev); | |
7ed220d7 | 607 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
608 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
609 | int (*cs_parse)(struct radeon_cs_parser *p); | |
610 | int (*copy_blit)(struct radeon_device *rdev, | |
611 | uint64_t src_offset, | |
612 | uint64_t dst_offset, | |
613 | unsigned num_pages, | |
614 | struct radeon_fence *fence); | |
615 | int (*copy_dma)(struct radeon_device *rdev, | |
616 | uint64_t src_offset, | |
617 | uint64_t dst_offset, | |
618 | unsigned num_pages, | |
619 | struct radeon_fence *fence); | |
620 | int (*copy)(struct radeon_device *rdev, | |
621 | uint64_t src_offset, | |
622 | uint64_t dst_offset, | |
623 | unsigned num_pages, | |
624 | struct radeon_fence *fence); | |
625 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); | |
626 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); | |
627 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); | |
628 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
e024e110 DA |
629 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
630 | uint32_t tiling_flags, uint32_t pitch, | |
631 | uint32_t offset, uint32_t obj_size); | |
632 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); | |
c93bb85b | 633 | void (*bandwidth_update)(struct radeon_device *rdev); |
771fe6b9 JG |
634 | }; |
635 | ||
21f9a437 JG |
636 | /* |
637 | * Asic structures | |
638 | */ | |
551ebd83 DA |
639 | struct r100_asic { |
640 | const unsigned *reg_safe_bm; | |
641 | unsigned reg_safe_bm_size; | |
642 | }; | |
643 | ||
21f9a437 JG |
644 | struct r300_asic { |
645 | const unsigned *reg_safe_bm; | |
646 | unsigned reg_safe_bm_size; | |
647 | }; | |
648 | ||
649 | struct r600_asic { | |
650 | unsigned max_pipes; | |
651 | unsigned max_tile_pipes; | |
652 | unsigned max_simds; | |
653 | unsigned max_backends; | |
654 | unsigned max_gprs; | |
655 | unsigned max_threads; | |
656 | unsigned max_stack_entries; | |
657 | unsigned max_hw_contexts; | |
658 | unsigned max_gs_threads; | |
659 | unsigned sx_max_export_size; | |
660 | unsigned sx_max_export_pos_size; | |
661 | unsigned sx_max_export_smx_size; | |
662 | unsigned sq_num_cf_insts; | |
663 | }; | |
664 | ||
665 | struct rv770_asic { | |
666 | unsigned max_pipes; | |
667 | unsigned max_tile_pipes; | |
668 | unsigned max_simds; | |
669 | unsigned max_backends; | |
670 | unsigned max_gprs; | |
671 | unsigned max_threads; | |
672 | unsigned max_stack_entries; | |
673 | unsigned max_hw_contexts; | |
674 | unsigned max_gs_threads; | |
675 | unsigned sx_max_export_size; | |
676 | unsigned sx_max_export_pos_size; | |
677 | unsigned sx_max_export_smx_size; | |
678 | unsigned sq_num_cf_insts; | |
679 | unsigned sx_num_of_sets; | |
680 | unsigned sc_prim_fifo_size; | |
681 | unsigned sc_hiz_tile_fifo_size; | |
682 | unsigned sc_earlyz_tile_fifo_fize; | |
683 | }; | |
684 | ||
068a117c JG |
685 | union radeon_asic_config { |
686 | struct r300_asic r300; | |
551ebd83 | 687 | struct r100_asic r100; |
3ce0a23d JG |
688 | struct r600_asic r600; |
689 | struct rv770_asic rv770; | |
068a117c JG |
690 | }; |
691 | ||
771fe6b9 JG |
692 | |
693 | /* | |
694 | * IOCTL. | |
695 | */ | |
696 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
697 | struct drm_file *filp); | |
698 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
699 | struct drm_file *filp); | |
700 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
701 | struct drm_file *file_priv); | |
702 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
703 | struct drm_file *file_priv); | |
704 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
705 | struct drm_file *file_priv); | |
706 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
707 | struct drm_file *file_priv); | |
708 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
709 | struct drm_file *filp); | |
710 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
711 | struct drm_file *filp); | |
712 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
713 | struct drm_file *filp); | |
714 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
715 | struct drm_file *filp); | |
716 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
e024e110 DA |
717 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
718 | struct drm_file *filp); | |
719 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
720 | struct drm_file *filp); | |
771fe6b9 JG |
721 | |
722 | ||
723 | /* | |
724 | * Core structure, functions and helpers. | |
725 | */ | |
726 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
727 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
728 | ||
729 | struct radeon_device { | |
9f022ddf | 730 | struct device *dev; |
771fe6b9 JG |
731 | struct drm_device *ddev; |
732 | struct pci_dev *pdev; | |
733 | /* ASIC */ | |
068a117c | 734 | union radeon_asic_config config; |
771fe6b9 JG |
735 | enum radeon_family family; |
736 | unsigned long flags; | |
737 | int usec_timeout; | |
738 | enum radeon_pll_errata pll_errata; | |
739 | int num_gb_pipes; | |
f779b3e5 | 740 | int num_z_pipes; |
771fe6b9 JG |
741 | int disp_priority; |
742 | /* BIOS */ | |
743 | uint8_t *bios; | |
744 | bool is_atom_bios; | |
745 | uint16_t bios_header_start; | |
746 | struct radeon_object *stollen_vga_memory; | |
747 | struct fb_info *fbdev_info; | |
748 | struct radeon_object *fbdev_robj; | |
749 | struct radeon_framebuffer *fbdev_rfb; | |
750 | /* Register mmio */ | |
4c9bc75c DA |
751 | resource_size_t rmmio_base; |
752 | resource_size_t rmmio_size; | |
771fe6b9 | 753 | void *rmmio; |
771fe6b9 JG |
754 | radeon_rreg_t mc_rreg; |
755 | radeon_wreg_t mc_wreg; | |
756 | radeon_rreg_t pll_rreg; | |
757 | radeon_wreg_t pll_wreg; | |
de1b2898 | 758 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
759 | radeon_rreg_t pciep_rreg; |
760 | radeon_wreg_t pciep_wreg; | |
761 | struct radeon_clock clock; | |
762 | struct radeon_mc mc; | |
763 | struct radeon_gart gart; | |
764 | struct radeon_mode_info mode_info; | |
765 | struct radeon_scratch scratch; | |
766 | struct radeon_mman mman; | |
767 | struct radeon_fence_driver fence_drv; | |
768 | struct radeon_cp cp; | |
769 | struct radeon_ib_pool ib_pool; | |
770 | struct radeon_irq irq; | |
771 | struct radeon_asic *asic; | |
772 | struct radeon_gem gem; | |
c93bb85b | 773 | struct radeon_pm pm; |
f657c2a7 | 774 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 JG |
775 | struct mutex cs_mutex; |
776 | struct radeon_wb wb; | |
3ce0a23d | 777 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
778 | bool gpu_lockup; |
779 | bool shutdown; | |
780 | bool suspend; | |
ad49f501 | 781 | bool need_dma32; |
733289c2 | 782 | bool accel_working; |
e024e110 | 783 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
784 | const struct firmware *me_fw; /* all family ME firmware */ |
785 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
786 | struct r600_blit r600_blit; | |
3e5cb98d | 787 | int msi_enabled; /* msi enabled */ |
771fe6b9 JG |
788 | }; |
789 | ||
790 | int radeon_device_init(struct radeon_device *rdev, | |
791 | struct drm_device *ddev, | |
792 | struct pci_dev *pdev, | |
793 | uint32_t flags); | |
794 | void radeon_device_fini(struct radeon_device *rdev); | |
795 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
796 | ||
3ce0a23d JG |
797 | /* r600 blit */ |
798 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); | |
799 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); | |
800 | void r600_kms_blit_copy(struct radeon_device *rdev, | |
801 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
802 | int size_bytes); | |
803 | ||
de1b2898 DA |
804 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
805 | { | |
806 | if (reg < 0x10000) | |
807 | return readl(((void __iomem *)rdev->rmmio) + reg); | |
808 | else { | |
809 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
810 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
811 | } | |
812 | } | |
813 | ||
814 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
815 | { | |
816 | if (reg < 0x10000) | |
817 | writel(v, ((void __iomem *)rdev->rmmio) + reg); | |
818 | else { | |
819 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
820 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
821 | } | |
822 | } | |
823 | ||
771fe6b9 JG |
824 | |
825 | /* | |
826 | * Registers read & write functions. | |
827 | */ | |
828 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) | |
829 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) | |
de1b2898 | 830 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
3ce0a23d | 831 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
de1b2898 | 832 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
771fe6b9 JG |
833 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
834 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
835 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
836 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
837 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
838 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
839 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
840 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
841 | #define WREG32_P(reg, val, mask) \ |
842 | do { \ | |
843 | uint32_t tmp_ = RREG32(reg); \ | |
844 | tmp_ &= (mask); \ | |
845 | tmp_ |= ((val) & ~(mask)); \ | |
846 | WREG32(reg, tmp_); \ | |
847 | } while (0) | |
848 | #define WREG32_PLL_P(reg, val, mask) \ | |
849 | do { \ | |
850 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
851 | tmp_ &= (mask); \ | |
852 | tmp_ |= ((val) & ~(mask)); \ | |
853 | WREG32_PLL(reg, tmp_); \ | |
854 | } while (0) | |
3ce0a23d | 855 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
771fe6b9 | 856 | |
de1b2898 DA |
857 | /* |
858 | * Indirect registers accessor | |
859 | */ | |
860 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
861 | { | |
862 | uint32_t r; | |
863 | ||
864 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
865 | r = RREG32(RADEON_PCIE_DATA); | |
866 | return r; | |
867 | } | |
868 | ||
869 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
870 | { | |
871 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
872 | WREG32(RADEON_PCIE_DATA, (v)); | |
873 | } | |
874 | ||
771fe6b9 JG |
875 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
876 | ||
877 | ||
878 | /* | |
879 | * ASICs helpers. | |
880 | */ | |
b995e433 DA |
881 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
882 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
883 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
884 | (rdev->family == CHIP_RV200) || \ | |
885 | (rdev->family == CHIP_RS100) || \ | |
886 | (rdev->family == CHIP_RS200) || \ | |
887 | (rdev->family == CHIP_RV250) || \ | |
888 | (rdev->family == CHIP_RV280) || \ | |
889 | (rdev->family == CHIP_RS300)) | |
890 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
891 | (rdev->family == CHIP_RV350) || \ | |
892 | (rdev->family == CHIP_R350) || \ | |
893 | (rdev->family == CHIP_RV380) || \ | |
894 | (rdev->family == CHIP_R420) || \ | |
895 | (rdev->family == CHIP_R423) || \ | |
896 | (rdev->family == CHIP_RV410) || \ | |
897 | (rdev->family == CHIP_RS400) || \ | |
898 | (rdev->family == CHIP_RS480)) | |
899 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) | |
900 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) | |
901 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
902 | ||
903 | ||
904 | /* | |
905 | * BIOS helpers. | |
906 | */ | |
907 | #define RBIOS8(i) (rdev->bios[i]) | |
908 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
909 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
910 | ||
911 | int radeon_combios_init(struct radeon_device *rdev); | |
912 | void radeon_combios_fini(struct radeon_device *rdev); | |
913 | int radeon_atombios_init(struct radeon_device *rdev); | |
914 | void radeon_atombios_fini(struct radeon_device *rdev); | |
915 | ||
916 | ||
917 | /* | |
918 | * RING helpers. | |
919 | */ | |
771fe6b9 JG |
920 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
921 | { | |
922 | #if DRM_DEBUG_CODE | |
923 | if (rdev->cp.count_dw <= 0) { | |
924 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); | |
925 | } | |
926 | #endif | |
927 | rdev->cp.ring[rdev->cp.wptr++] = v; | |
928 | rdev->cp.wptr &= rdev->cp.ptr_mask; | |
929 | rdev->cp.count_dw--; | |
930 | rdev->cp.ring_free_dw--; | |
931 | } | |
932 | ||
933 | ||
934 | /* | |
935 | * ASICs macro. | |
936 | */ | |
068a117c | 937 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
938 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
939 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
940 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
771fe6b9 | 941 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
771fe6b9 | 942 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
771fe6b9 JG |
943 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
944 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) | |
3ce0a23d | 945 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
771fe6b9 | 946 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
3ce0a23d JG |
947 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
948 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) | |
771fe6b9 JG |
949 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
950 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) | |
7ed220d7 | 951 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
771fe6b9 JG |
952 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
953 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) | |
954 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) | |
955 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) | |
956 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) | |
957 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) | |
958 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) | |
959 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) | |
e024e110 DA |
960 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
961 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) | |
c93bb85b | 962 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
771fe6b9 | 963 | |
6cf8a3f5 | 964 | /* Common functions */ |
4aac0473 | 965 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
21f9a437 JG |
966 | extern int radeon_modeset_init(struct radeon_device *rdev); |
967 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 968 | extern bool radeon_card_posted(struct radeon_device *rdev); |
21f9a437 JG |
969 | extern int radeon_clocks_init(struct radeon_device *rdev); |
970 | extern void radeon_clocks_fini(struct radeon_device *rdev); | |
971 | extern void radeon_scratch_init(struct radeon_device *rdev); | |
972 | extern void radeon_surface_init(struct radeon_device *rdev); | |
973 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 974 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 975 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
6cf8a3f5 | 976 | |
a18d7ea1 | 977 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
9f022ddf JG |
978 | struct r100_mc_save { |
979 | u32 GENMO_WT; | |
980 | u32 CRTC_EXT_CNTL; | |
981 | u32 CRTC_GEN_CNTL; | |
982 | u32 CRTC2_GEN_CNTL; | |
983 | u32 CUR_OFFSET; | |
984 | u32 CUR2_OFFSET; | |
985 | }; | |
986 | extern void r100_cp_disable(struct radeon_device *rdev); | |
987 | extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
988 | extern void r100_cp_fini(struct radeon_device *rdev); | |
21f9a437 | 989 | extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
4aac0473 JG |
990 | extern int r100_pci_gart_init(struct radeon_device *rdev); |
991 | extern void r100_pci_gart_fini(struct radeon_device *rdev); | |
21f9a437 JG |
992 | extern int r100_pci_gart_enable(struct radeon_device *rdev); |
993 | extern void r100_pci_gart_disable(struct radeon_device *rdev); | |
994 | extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
9f022ddf JG |
995 | extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
996 | extern int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
997 | extern void r100_ib_fini(struct radeon_device *rdev); | |
998 | extern int r100_ib_init(struct radeon_device *rdev); | |
999 | extern void r100_irq_disable(struct radeon_device *rdev); | |
1000 | extern int r100_irq_set(struct radeon_device *rdev); | |
1001 | extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
1002 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
21f9a437 | 1003 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
9f022ddf JG |
1004 | extern void r100_wb_disable(struct radeon_device *rdev); |
1005 | extern void r100_wb_fini(struct radeon_device *rdev); | |
1006 | extern int r100_wb_init(struct radeon_device *rdev); | |
d39c3b89 JG |
1007 | extern void r100_hdp_reset(struct radeon_device *rdev); |
1008 | extern int r100_rb2d_reset(struct radeon_device *rdev); | |
1009 | extern int r100_cp_reset(struct radeon_device *rdev); | |
ca6ffc64 | 1010 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
207bf9e9 JG |
1011 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1012 | struct radeon_cs_packet *pkt, | |
1013 | struct radeon_object *robj); | |
1014 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |
1015 | struct radeon_cs_packet *pkt, | |
1016 | const unsigned *auth, unsigned n, | |
1017 | radeon_packet0_check_t check); | |
1018 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
1019 | struct radeon_cs_packet *pkt, | |
1020 | unsigned idx); | |
9f022ddf | 1021 | |
d4550907 JG |
1022 | /* rv200,rv250,rv280 */ |
1023 | extern void r200_set_safe_registers(struct radeon_device *rdev); | |
1024 | ||
9f022ddf JG |
1025 | /* r300,r350,rv350,rv370,rv380 */ |
1026 | extern void r300_set_reg_safe(struct radeon_device *rdev); | |
1027 | extern void r300_mc_program(struct radeon_device *rdev); | |
1028 | extern void r300_vram_info(struct radeon_device *rdev); | |
ca6ffc64 JG |
1029 | extern void r300_clock_startup(struct radeon_device *rdev); |
1030 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
4aac0473 JG |
1031 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1032 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
1033 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
9f022ddf | 1034 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
a18d7ea1 | 1035 | |
905b6822 | 1036 | /* r420,r423,rv410 */ |
d39c3b89 | 1037 | extern int r420_mc_init(struct radeon_device *rdev); |
21f9a437 JG |
1038 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1039 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
9f022ddf | 1040 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
d39c3b89 | 1041 | extern void r420_pipes_init(struct radeon_device *rdev); |
905b6822 | 1042 | |
21f9a437 | 1043 | /* rv515 */ |
d39c3b89 JG |
1044 | struct rv515_mc_save { |
1045 | u32 d1vga_control; | |
1046 | u32 d2vga_control; | |
1047 | u32 vga_render_control; | |
1048 | u32 vga_hdp_control; | |
1049 | u32 d1crtc_control; | |
1050 | u32 d2crtc_control; | |
1051 | }; | |
21f9a437 | 1052 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
d39c3b89 JG |
1053 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1054 | extern void rv515_set_safe_registers(struct radeon_device *rdev); | |
f0ed1f65 JG |
1055 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
1056 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
1057 | extern void rv515_clock_startup(struct radeon_device *rdev); | |
1058 | extern void rv515_debugfs(struct radeon_device *rdev); | |
1059 | extern int rv515_suspend(struct radeon_device *rdev); | |
21f9a437 | 1060 | |
3bc68535 JG |
1061 | /* rs400 */ |
1062 | extern int rs400_gart_init(struct radeon_device *rdev); | |
1063 | extern int rs400_gart_enable(struct radeon_device *rdev); | |
1064 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); | |
1065 | extern void rs400_gart_disable(struct radeon_device *rdev); | |
1066 | extern void rs400_gart_fini(struct radeon_device *rdev); | |
1067 | ||
1068 | /* rs600 */ | |
1069 | extern void rs600_set_safe_registers(struct radeon_device *rdev); | |
ac447df4 JG |
1070 | extern int rs600_irq_set(struct radeon_device *rdev); |
1071 | extern void rs600_irq_disable(struct radeon_device *rdev); | |
3bc68535 | 1072 | |
21f9a437 JG |
1073 | /* rs690, rs740 */ |
1074 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, | |
1075 | struct drm_display_mode *mode1, | |
1076 | struct drm_display_mode *mode2); | |
1077 | ||
1078 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ | |
1079 | extern bool r600_card_posted(struct radeon_device *rdev); | |
1080 | extern void r600_cp_stop(struct radeon_device *rdev); | |
1081 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
1082 | extern int r600_cp_resume(struct radeon_device *rdev); | |
1083 | extern int r600_count_pipe_bits(uint32_t val); | |
1084 | extern int r600_gart_clear_page(struct radeon_device *rdev, int i); | |
1085 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
4aac0473 | 1086 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
21f9a437 JG |
1087 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1088 | extern int r600_ib_test(struct radeon_device *rdev); | |
1089 | extern int r600_ring_test(struct radeon_device *rdev); | |
21f9a437 | 1090 | extern void r600_wb_fini(struct radeon_device *rdev); |
81cc35bf JG |
1091 | extern int r600_wb_enable(struct radeon_device *rdev); |
1092 | extern void r600_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1093 | extern void r600_scratch_init(struct radeon_device *rdev); |
1094 | extern int r600_blit_init(struct radeon_device *rdev); | |
1095 | extern void r600_blit_fini(struct radeon_device *rdev); | |
1096 | extern int r600_cp_init_microcode(struct radeon_device *rdev); | |
fe62e1a4 | 1097 | extern int r600_gpu_reset(struct radeon_device *rdev); |
21f9a437 | 1098 | |
771fe6b9 | 1099 | #endif |