Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
60063497 | 63 | #include <linux/atomic.h> |
771fe6b9 JG |
64 | #include <linux/wait.h> |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
0aea5e4a | 67 | #include <linux/interval_tree.h> |
341cb9e4 | 68 | #include <linux/hashtable.h> |
954605ca | 69 | #include <linux/fence.h> |
771fe6b9 | 70 | |
4c788679 JG |
71 | #include <ttm/ttm_bo_api.h> |
72 | #include <ttm/ttm_bo_driver.h> | |
73 | #include <ttm/ttm_placement.h> | |
74 | #include <ttm/ttm_module.h> | |
147666fb | 75 | #include <ttm/ttm_execbuf_util.h> |
4c788679 | 76 | |
d9fc9413 DV |
77 | #include <drm/drm_gem.h> |
78 | ||
c2142715 | 79 | #include "radeon_family.h" |
771fe6b9 JG |
80 | #include "radeon_mode.h" |
81 | #include "radeon_reg.h" | |
771fe6b9 JG |
82 | |
83 | /* | |
84 | * Modules parameters. | |
85 | */ | |
86 | extern int radeon_no_wb; | |
87 | extern int radeon_modeset; | |
88 | extern int radeon_dynclks; | |
89 | extern int radeon_r4xx_atom; | |
90 | extern int radeon_agpmode; | |
91 | extern int radeon_vram_limit; | |
92 | extern int radeon_gart_size; | |
93 | extern int radeon_benchmarking; | |
ecc0b326 | 94 | extern int radeon_testing; |
771fe6b9 | 95 | extern int radeon_connector_table; |
4ce001ab | 96 | extern int radeon_tv; |
dafc3bd5 | 97 | extern int radeon_audio; |
f46c0120 | 98 | extern int radeon_disp_priority; |
e2b0a8e1 | 99 | extern int radeon_hw_i2c; |
d42dd579 | 100 | extern int radeon_pcie_gen2; |
a18cee15 | 101 | extern int radeon_msi; |
3368ff0c | 102 | extern int radeon_lockup_timeout; |
a0a53aa8 | 103 | extern int radeon_fastfb; |
da321c8a | 104 | extern int radeon_dpm; |
1294d4a3 | 105 | extern int radeon_aspm; |
10ebc0bc | 106 | extern int radeon_runtime_pm; |
363eb0b4 | 107 | extern int radeon_hard_reset; |
c1c44132 | 108 | extern int radeon_vm_size; |
4510fb98 | 109 | extern int radeon_vm_block_size; |
a624f429 | 110 | extern int radeon_deep_color; |
39dc5454 | 111 | extern int radeon_use_pflipirq; |
6e909f74 | 112 | extern int radeon_bapm; |
bc13018b | 113 | extern int radeon_backlight; |
771fe6b9 JG |
114 | |
115 | /* | |
116 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
117 | * symbol; | |
118 | */ | |
bb635567 JG |
119 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
120 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
e821767b | 121 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
bb635567 JG |
122 | #define RADEON_IB_POOL_SIZE 16 |
123 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 | |
124 | #define RADEONFB_CONN_LIMIT 4 | |
125 | #define RADEON_BIOS_NUM_SCRATCH 8 | |
771fe6b9 | 126 | |
1b37078b AD |
127 | /* internal ring indices */ |
128 | /* r1xx+ has gfx CP ring */ | |
d93f7937 | 129 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
1b37078b AD |
130 | |
131 | /* cayman has 2 compute CP rings */ | |
d93f7937 CK |
132 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
133 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 | |
1b37078b | 134 | |
4d75658b AD |
135 | /* R600+ has an async dma ring */ |
136 | #define R600_RING_TYPE_DMA_INDEX 3 | |
f60cbd11 AD |
137 | /* cayman add a second async dma ring */ |
138 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 | |
4d75658b | 139 | |
f2ba57b5 | 140 | /* R600+ */ |
d93f7937 CK |
141 | #define R600_RING_TYPE_UVD_INDEX 5 |
142 | ||
143 | /* TN+ */ | |
144 | #define TN_RING_TYPE_VCE1_INDEX 6 | |
145 | #define TN_RING_TYPE_VCE2_INDEX 7 | |
146 | ||
147 | /* max number of rings */ | |
148 | #define RADEON_NUM_RINGS 8 | |
f2ba57b5 | 149 | |
1c61eae4 CK |
150 | /* number of hw syncs before falling back on blocking */ |
151 | #define RADEON_NUM_SYNCS 4 | |
f2ba57b5 | 152 | |
721604a1 | 153 | /* hardcode those limit for now */ |
ca19f21e | 154 | #define RADEON_VA_IB_OFFSET (1 << 20) |
bb635567 JG |
155 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
156 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) | |
721604a1 | 157 | |
1a0041b8 AD |
158 | /* hard reset data */ |
159 | #define RADEON_ASIC_RESET_DATA 0x39d5e86b | |
160 | ||
ec46c76d AD |
161 | /* reset flags */ |
162 | #define RADEON_RESET_GFX (1 << 0) | |
163 | #define RADEON_RESET_COMPUTE (1 << 1) | |
164 | #define RADEON_RESET_DMA (1 << 2) | |
9ff0744c AD |
165 | #define RADEON_RESET_CP (1 << 3) |
166 | #define RADEON_RESET_GRBM (1 << 4) | |
167 | #define RADEON_RESET_DMA1 (1 << 5) | |
168 | #define RADEON_RESET_RLC (1 << 6) | |
169 | #define RADEON_RESET_SEM (1 << 7) | |
170 | #define RADEON_RESET_IH (1 << 8) | |
171 | #define RADEON_RESET_VMC (1 << 9) | |
172 | #define RADEON_RESET_MC (1 << 10) | |
173 | #define RADEON_RESET_DISPLAY (1 << 11) | |
ec46c76d | 174 | |
22c775ce AD |
175 | /* CG block flags */ |
176 | #define RADEON_CG_BLOCK_GFX (1 << 0) | |
177 | #define RADEON_CG_BLOCK_MC (1 << 1) | |
178 | #define RADEON_CG_BLOCK_SDMA (1 << 2) | |
179 | #define RADEON_CG_BLOCK_UVD (1 << 3) | |
180 | #define RADEON_CG_BLOCK_VCE (1 << 4) | |
181 | #define RADEON_CG_BLOCK_HDP (1 << 5) | |
e16866ec | 182 | #define RADEON_CG_BLOCK_BIF (1 << 6) |
22c775ce | 183 | |
64d8a728 AD |
184 | /* CG flags */ |
185 | #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) | |
186 | #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) | |
187 | #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) | |
188 | #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) | |
189 | #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) | |
190 | #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) | |
191 | #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) | |
192 | #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) | |
193 | #define RADEON_CG_SUPPORT_MC_LS (1 << 8) | |
194 | #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) | |
195 | #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) | |
196 | #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) | |
197 | #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) | |
198 | #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) | |
199 | #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) | |
200 | #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) | |
201 | #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) | |
202 | ||
203 | /* PG flags */ | |
2b19d17f | 204 | #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) |
64d8a728 AD |
205 | #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) |
206 | #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) | |
207 | #define RADEON_PG_SUPPORT_UVD (1 << 3) | |
208 | #define RADEON_PG_SUPPORT_VCE (1 << 4) | |
209 | #define RADEON_PG_SUPPORT_CP (1 << 5) | |
210 | #define RADEON_PG_SUPPORT_GDS (1 << 6) | |
211 | #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) | |
212 | #define RADEON_PG_SUPPORT_SDMA (1 << 8) | |
213 | #define RADEON_PG_SUPPORT_ACP (1 << 9) | |
214 | #define RADEON_PG_SUPPORT_SAMU (1 << 10) | |
215 | ||
9e05fa1d AD |
216 | /* max cursor sizes (in pixels) */ |
217 | #define CURSOR_WIDTH 64 | |
218 | #define CURSOR_HEIGHT 64 | |
219 | ||
220 | #define CIK_CURSOR_WIDTH 128 | |
221 | #define CIK_CURSOR_HEIGHT 128 | |
222 | ||
771fe6b9 JG |
223 | /* |
224 | * Errata workarounds. | |
225 | */ | |
226 | enum radeon_pll_errata { | |
227 | CHIP_ERRATA_R300_CG = 0x00000001, | |
228 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
229 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
230 | }; | |
231 | ||
232 | ||
233 | struct radeon_device; | |
234 | ||
235 | ||
236 | /* | |
237 | * BIOS. | |
238 | */ | |
239 | bool radeon_get_bios(struct radeon_device *rdev); | |
240 | ||
241 | /* | |
3ce0a23d | 242 | * Dummy page |
771fe6b9 | 243 | */ |
3ce0a23d JG |
244 | struct radeon_dummy_page { |
245 | struct page *page; | |
246 | dma_addr_t addr; | |
247 | }; | |
248 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
249 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
250 | ||
771fe6b9 | 251 | |
3ce0a23d JG |
252 | /* |
253 | * Clocks | |
254 | */ | |
771fe6b9 JG |
255 | struct radeon_clock { |
256 | struct radeon_pll p1pll; | |
257 | struct radeon_pll p2pll; | |
bcc1c2a1 | 258 | struct radeon_pll dcpll; |
771fe6b9 JG |
259 | struct radeon_pll spll; |
260 | struct radeon_pll mpll; | |
261 | /* 10 Khz units */ | |
262 | uint32_t default_mclk; | |
263 | uint32_t default_sclk; | |
bcc1c2a1 | 264 | uint32_t default_dispclk; |
4489cd62 | 265 | uint32_t current_dispclk; |
bcc1c2a1 | 266 | uint32_t dp_extclk; |
b20f9bef | 267 | uint32_t max_pixel_clock; |
771fe6b9 JG |
268 | }; |
269 | ||
7433874e RM |
270 | /* |
271 | * Power management | |
272 | */ | |
273 | int radeon_pm_init(struct radeon_device *rdev); | |
914a8987 | 274 | int radeon_pm_late_init(struct radeon_device *rdev); |
29fb52ca | 275 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 276 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
ce8f5370 AD |
277 | void radeon_pm_suspend(struct radeon_device *rdev); |
278 | void radeon_pm_resume(struct radeon_device *rdev); | |
56278a8e AD |
279 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
280 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
7062ab67 CK |
281 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
282 | u8 clock_type, | |
283 | u32 clock, | |
284 | bool strobe_mode, | |
285 | struct atom_clock_dividers *dividers); | |
eaa778af AD |
286 | int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, |
287 | u32 clock, | |
288 | bool strobe_mode, | |
289 | struct atom_mpll_param *mpll_param); | |
8a83ec5e | 290 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
ae5b0abb AD |
291 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
292 | u16 voltage_level, u8 voltage_type, | |
293 | u32 *gpio_value, u32 *gpio_mask); | |
294 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, | |
295 | u32 eng_clock, u32 mem_clock); | |
296 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, | |
297 | u8 voltage_type, u16 *voltage_step); | |
4a6369e9 AD |
298 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
299 | u16 voltage_id, u16 *voltage); | |
beb79f40 AD |
300 | int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, |
301 | u16 *voltage, | |
302 | u16 leakage_idx); | |
cc8dbbb4 AD |
303 | int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, |
304 | u16 *leakage_id); | |
305 | int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, | |
306 | u16 *vddc, u16 *vddci, | |
307 | u16 virtual_voltage_id, | |
308 | u16 vbios_voltage_id); | |
e9f274b2 AD |
309 | int radeon_atom_get_voltage_evv(struct radeon_device *rdev, |
310 | u16 virtual_voltage_id, | |
311 | u16 *voltage); | |
ae5b0abb AD |
312 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, |
313 | u8 voltage_type, | |
314 | u16 nominal_voltage, | |
315 | u16 *true_voltage); | |
316 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, | |
317 | u8 voltage_type, u16 *min_voltage); | |
318 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, | |
319 | u8 voltage_type, u16 *max_voltage); | |
320 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, | |
65171944 | 321 | u8 voltage_type, u8 voltage_mode, |
ae5b0abb | 322 | struct atom_voltage_table *voltage_table); |
58653abd AD |
323 | bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, |
324 | u8 voltage_type, u8 voltage_mode); | |
636e2582 AD |
325 | int radeon_atom_get_svi2_info(struct radeon_device *rdev, |
326 | u8 voltage_type, | |
327 | u8 *svd_gpio_id, u8 *svc_gpio_id); | |
ae5b0abb AD |
328 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, |
329 | u32 mem_clock); | |
330 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, | |
331 | u32 mem_clock); | |
332 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, | |
333 | u8 module_index, | |
334 | struct atom_mc_reg_table *reg_table); | |
335 | int radeon_atom_get_memory_info(struct radeon_device *rdev, | |
336 | u8 module_index, struct atom_memory_info *mem_info); | |
337 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, | |
338 | bool gddr5, u8 module_index, | |
339 | struct atom_memory_clock_range_table *mclk_range_table); | |
340 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, | |
341 | u16 voltage_id, u16 *voltage); | |
f892034a | 342 | void rs690_pm_info(struct radeon_device *rdev); |
285484e2 JG |
343 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
344 | unsigned *bankh, unsigned *mtaspect, | |
345 | unsigned *tile_split); | |
3ce0a23d | 346 | |
771fe6b9 JG |
347 | /* |
348 | * Fences. | |
349 | */ | |
350 | struct radeon_fence_driver { | |
0bfa4b41 | 351 | struct radeon_device *rdev; |
771fe6b9 | 352 | uint32_t scratch_reg; |
30eb77f4 JG |
353 | uint64_t gpu_addr; |
354 | volatile uint32_t *cpu_addr; | |
68e250b7 CK |
355 | /* sync_seq is protected by ring emission lock */ |
356 | uint64_t sync_seq[RADEON_NUM_RINGS]; | |
bb635567 | 357 | atomic64_t last_seq; |
954605ca | 358 | bool initialized, delayed_irq; |
0bfa4b41 | 359 | struct delayed_work lockup_work; |
771fe6b9 JG |
360 | }; |
361 | ||
362 | struct radeon_fence { | |
ad1a58a4 | 363 | struct fence base; |
954605ca | 364 | |
ad1a58a4 CK |
365 | struct radeon_device *rdev; |
366 | uint64_t seq; | |
7465280c | 367 | /* RB, DMA, etc. */ |
ad1a58a4 CK |
368 | unsigned ring; |
369 | bool is_vm_update; | |
954605ca | 370 | |
ad1a58a4 | 371 | wait_queue_t fence_wake; |
771fe6b9 JG |
372 | }; |
373 | ||
30eb77f4 JG |
374 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
375 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
771fe6b9 | 376 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
eb98c709 | 377 | void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); |
876dc9f3 | 378 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
7465280c | 379 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
771fe6b9 JG |
380 | bool radeon_fence_signaled(struct radeon_fence *fence); |
381 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
37615527 CK |
382 | int radeon_fence_wait_next(struct radeon_device *rdev, int ring); |
383 | int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); | |
0085c950 JG |
384 | int radeon_fence_wait_any(struct radeon_device *rdev, |
385 | struct radeon_fence **fences, | |
386 | bool intr); | |
771fe6b9 JG |
387 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
388 | void radeon_fence_unref(struct radeon_fence **fence); | |
3b7a2b24 | 389 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
68e250b7 CK |
390 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
391 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); | |
392 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, | |
393 | struct radeon_fence *b) | |
394 | { | |
395 | if (!a) { | |
396 | return b; | |
397 | } | |
398 | ||
399 | if (!b) { | |
400 | return a; | |
401 | } | |
402 | ||
403 | BUG_ON(a->ring != b->ring); | |
404 | ||
405 | if (a->seq > b->seq) { | |
406 | return a; | |
407 | } else { | |
408 | return b; | |
409 | } | |
410 | } | |
771fe6b9 | 411 | |
ee60e29f CK |
412 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
413 | struct radeon_fence *b) | |
414 | { | |
415 | if (!a) { | |
416 | return false; | |
417 | } | |
418 | ||
419 | if (!b) { | |
420 | return true; | |
421 | } | |
422 | ||
423 | BUG_ON(a->ring != b->ring); | |
424 | ||
425 | return a->seq < b->seq; | |
426 | } | |
427 | ||
e024e110 DA |
428 | /* |
429 | * Tiling registers | |
430 | */ | |
431 | struct radeon_surface_reg { | |
4c788679 | 432 | struct radeon_bo *bo; |
e024e110 DA |
433 | }; |
434 | ||
435 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
436 | |
437 | /* | |
4c788679 | 438 | * TTM. |
771fe6b9 | 439 | */ |
4c788679 JG |
440 | struct radeon_mman { |
441 | struct ttm_bo_global_ref bo_global_ref; | |
ba4420c2 | 442 | struct drm_global_reference mem_global_ref; |
4c788679 | 443 | struct ttm_bo_device bdev; |
0a0c7596 JG |
444 | bool mem_global_referenced; |
445 | bool initialized; | |
2014b569 CK |
446 | |
447 | #if defined(CONFIG_DEBUG_FS) | |
448 | struct dentry *vram; | |
dd66d20e | 449 | struct dentry *gtt; |
2014b569 | 450 | #endif |
4c788679 JG |
451 | }; |
452 | ||
721604a1 JG |
453 | /* bo virtual address in a specific vm */ |
454 | struct radeon_bo_va { | |
e971bd5e | 455 | /* protected by bo being reserved */ |
721604a1 | 456 | struct list_head bo_list; |
721604a1 | 457 | uint32_t flags; |
e31ad969 | 458 | uint64_t addr; |
e971bd5e CK |
459 | unsigned ref_count; |
460 | ||
461 | /* protected by vm mutex */ | |
0aea5e4a | 462 | struct interval_tree_node it; |
036bf46a | 463 | struct list_head vm_status; |
e971bd5e CK |
464 | |
465 | /* constant after initialization */ | |
466 | struct radeon_vm *vm; | |
467 | struct radeon_bo *bo; | |
721604a1 JG |
468 | }; |
469 | ||
4c788679 JG |
470 | struct radeon_bo { |
471 | /* Protected by gem.mutex */ | |
472 | struct list_head list; | |
473 | /* Protected by tbo.reserved */ | |
bda72d58 | 474 | u32 initial_domain; |
c9da4a4b | 475 | struct ttm_place placements[4]; |
312ea8da | 476 | struct ttm_placement placement; |
4c788679 JG |
477 | struct ttm_buffer_object tbo; |
478 | struct ttm_bo_kmap_obj kmap; | |
02376d82 | 479 | u32 flags; |
4c788679 JG |
480 | unsigned pin_count; |
481 | void *kptr; | |
482 | u32 tiling_flags; | |
483 | u32 pitch; | |
484 | int surface_reg; | |
721604a1 JG |
485 | /* list of all virtual address to which this bo |
486 | * is associated to | |
487 | */ | |
488 | struct list_head va; | |
4c788679 JG |
489 | /* Constant after initialization */ |
490 | struct radeon_device *rdev; | |
441921d5 | 491 | struct drm_gem_object gem_base; |
63bc620b | 492 | |
409851f4 JG |
493 | struct ttm_bo_kmap_obj dma_buf_vmap; |
494 | pid_t pid; | |
341cb9e4 CK |
495 | |
496 | struct radeon_mn *mn; | |
497 | struct interval_tree_node mn_it; | |
4c788679 | 498 | }; |
7e4d15d9 | 499 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
771fe6b9 | 500 | |
409851f4 JG |
501 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
502 | ||
b15ba512 JG |
503 | /* sub-allocation manager, it has to be protected by another lock. |
504 | * By conception this is an helper for other part of the driver | |
505 | * like the indirect buffer or semaphore, which both have their | |
506 | * locking. | |
507 | * | |
508 | * Principe is simple, we keep a list of sub allocation in offset | |
509 | * order (first entry has offset == 0, last entry has the highest | |
510 | * offset). | |
511 | * | |
512 | * When allocating new object we first check if there is room at | |
513 | * the end total_size - (last_object_offset + last_object_size) >= | |
514 | * alloc_size. If so we allocate new object there. | |
515 | * | |
516 | * When there is not enough room at the end, we start waiting for | |
517 | * each sub object until we reach object_offset+object_size >= | |
518 | * alloc_size, this object then become the sub object we return. | |
519 | * | |
520 | * Alignment can't be bigger than page size. | |
521 | * | |
522 | * Hole are not considered for allocation to keep things simple. | |
523 | * Assumption is that there won't be hole (all object on same | |
524 | * alignment). | |
525 | */ | |
526 | struct radeon_sa_manager { | |
bfb38d35 | 527 | wait_queue_head_t wq; |
b15ba512 | 528 | struct radeon_bo *bo; |
c3b7fe8b CK |
529 | struct list_head *hole; |
530 | struct list_head flist[RADEON_NUM_RINGS]; | |
531 | struct list_head olist; | |
b15ba512 JG |
532 | unsigned size; |
533 | uint64_t gpu_addr; | |
534 | void *cpu_ptr; | |
535 | uint32_t domain; | |
6c4f978b | 536 | uint32_t align; |
b15ba512 JG |
537 | }; |
538 | ||
539 | struct radeon_sa_bo; | |
540 | ||
541 | /* sub-allocation buffer */ | |
542 | struct radeon_sa_bo { | |
c3b7fe8b CK |
543 | struct list_head olist; |
544 | struct list_head flist; | |
b15ba512 | 545 | struct radeon_sa_manager *manager; |
e6661a96 CK |
546 | unsigned soffset; |
547 | unsigned eoffset; | |
557017a0 | 548 | struct radeon_fence *fence; |
b15ba512 JG |
549 | }; |
550 | ||
771fe6b9 JG |
551 | /* |
552 | * GEM objects. | |
553 | */ | |
554 | struct radeon_gem { | |
4c788679 | 555 | struct mutex mutex; |
771fe6b9 JG |
556 | struct list_head objects; |
557 | }; | |
558 | ||
559 | int radeon_gem_init(struct radeon_device *rdev); | |
560 | void radeon_gem_fini(struct radeon_device *rdev); | |
391bfec3 | 561 | int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, |
4c788679 | 562 | int alignment, int initial_domain, |
ed5cb43f | 563 | u32 flags, bool kernel, |
4c788679 | 564 | struct drm_gem_object **obj); |
771fe6b9 | 565 | |
ff72145b DA |
566 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
567 | struct drm_device *dev, | |
568 | struct drm_mode_create_dumb *args); | |
569 | int radeon_mode_dumb_mmap(struct drm_file *filp, | |
570 | struct drm_device *dev, | |
571 | uint32_t handle, uint64_t *offset_p); | |
771fe6b9 | 572 | |
c1341e52 JG |
573 | /* |
574 | * Semaphores. | |
575 | */ | |
c1341e52 | 576 | struct radeon_semaphore { |
975700d2 CK |
577 | struct radeon_sa_bo *sa_bo; |
578 | signed waiters; | |
579 | uint64_t gpu_addr; | |
c1341e52 JG |
580 | }; |
581 | ||
c1341e52 JG |
582 | int radeon_semaphore_create(struct radeon_device *rdev, |
583 | struct radeon_semaphore **semaphore); | |
1654b817 | 584 | bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
c1341e52 | 585 | struct radeon_semaphore *semaphore); |
1654b817 | 586 | bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
c1341e52 JG |
587 | struct radeon_semaphore *semaphore); |
588 | void radeon_semaphore_free(struct radeon_device *rdev, | |
220907d9 | 589 | struct radeon_semaphore **semaphore, |
a8c05940 | 590 | struct radeon_fence *fence); |
c1341e52 | 591 | |
975700d2 CK |
592 | /* |
593 | * Synchronization | |
594 | */ | |
595 | struct radeon_sync { | |
596 | struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; | |
597 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; | |
ad1a58a4 | 598 | struct radeon_fence *last_vm_update; |
975700d2 CK |
599 | }; |
600 | ||
601 | void radeon_sync_create(struct radeon_sync *sync); | |
602 | void radeon_sync_fence(struct radeon_sync *sync, | |
603 | struct radeon_fence *fence); | |
604 | int radeon_sync_resv(struct radeon_device *rdev, | |
605 | struct radeon_sync *sync, | |
606 | struct reservation_object *resv, | |
607 | bool shared); | |
608 | int radeon_sync_rings(struct radeon_device *rdev, | |
609 | struct radeon_sync *sync, | |
610 | int waiting_ring); | |
611 | void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, | |
612 | struct radeon_fence *fence); | |
613 | ||
771fe6b9 JG |
614 | /* |
615 | * GART structures, functions & helpers | |
616 | */ | |
617 | struct radeon_mc; | |
618 | ||
a77f1718 | 619 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 620 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
003cefe0 | 621 | #define RADEON_GPU_PAGE_SHIFT 12 |
721604a1 | 622 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
a77f1718 | 623 | |
77497f27 MD |
624 | #define RADEON_GART_PAGE_DUMMY 0 |
625 | #define RADEON_GART_PAGE_VALID (1 << 0) | |
626 | #define RADEON_GART_PAGE_READ (1 << 1) | |
627 | #define RADEON_GART_PAGE_WRITE (1 << 2) | |
628 | #define RADEON_GART_PAGE_SNOOP (1 << 3) | |
629 | ||
771fe6b9 JG |
630 | struct radeon_gart { |
631 | dma_addr_t table_addr; | |
c9a1be96 JG |
632 | struct radeon_bo *robj; |
633 | void *ptr; | |
771fe6b9 JG |
634 | unsigned num_gpu_pages; |
635 | unsigned num_cpu_pages; | |
636 | unsigned table_size; | |
771fe6b9 JG |
637 | struct page **pages; |
638 | dma_addr_t *pages_addr; | |
639 | bool ready; | |
640 | }; | |
641 | ||
642 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
643 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
644 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
645 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
c9a1be96 JG |
646 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
647 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); | |
771fe6b9 JG |
648 | int radeon_gart_init(struct radeon_device *rdev); |
649 | void radeon_gart_fini(struct radeon_device *rdev); | |
650 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
651 | int pages); | |
652 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
c39d3516 | 653 | int pages, struct page **pagelist, |
77497f27 | 654 | dma_addr_t *dma_addr, uint32_t flags); |
771fe6b9 JG |
655 | |
656 | ||
657 | /* | |
658 | * GPU MC structures, functions & helpers | |
659 | */ | |
660 | struct radeon_mc { | |
661 | resource_size_t aper_size; | |
662 | resource_size_t aper_base; | |
663 | resource_size_t agp_base; | |
7a50f01a DA |
664 | /* for some chips with <= 32MB we need to lie |
665 | * about vram size near mc fb location */ | |
3ce0a23d | 666 | u64 mc_vram_size; |
d594e46a | 667 | u64 visible_vram_size; |
3ce0a23d JG |
668 | u64 gtt_size; |
669 | u64 gtt_start; | |
670 | u64 gtt_end; | |
3ce0a23d JG |
671 | u64 vram_start; |
672 | u64 vram_end; | |
771fe6b9 | 673 | unsigned vram_width; |
3ce0a23d | 674 | u64 real_vram_size; |
771fe6b9 JG |
675 | int vram_mtrr; |
676 | bool vram_is_ddr; | |
d594e46a | 677 | bool igp_sideport_enabled; |
8d369bb1 | 678 | u64 gtt_base_align; |
9ed8b1f9 | 679 | u64 mc_mask; |
771fe6b9 JG |
680 | }; |
681 | ||
06b6476d AD |
682 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
683 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
684 | |
685 | /* | |
686 | * GPU scratch registers structures, functions & helpers | |
687 | */ | |
688 | struct radeon_scratch { | |
689 | unsigned num_reg; | |
724c80e1 | 690 | uint32_t reg_base; |
771fe6b9 JG |
691 | bool free[32]; |
692 | uint32_t reg[32]; | |
693 | }; | |
694 | ||
695 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
696 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
697 | ||
75efdee1 AD |
698 | /* |
699 | * GPU doorbell structures, functions & helpers | |
700 | */ | |
d5754ab8 AL |
701 | #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ |
702 | ||
75efdee1 | 703 | struct radeon_doorbell { |
75efdee1 | 704 | /* doorbell mmio */ |
d5754ab8 AL |
705 | resource_size_t base; |
706 | resource_size_t size; | |
707 | u32 __iomem *ptr; | |
708 | u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ | |
709 | unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; | |
75efdee1 AD |
710 | }; |
711 | ||
712 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); | |
713 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); | |
ebff8453 OG |
714 | void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, |
715 | phys_addr_t *aperture_base, | |
716 | size_t *aperture_size, | |
717 | size_t *start_offset); | |
771fe6b9 JG |
718 | |
719 | /* | |
720 | * IRQS. | |
721 | */ | |
6f34be50 | 722 | |
fa7f517c CK |
723 | struct radeon_flip_work { |
724 | struct work_struct flip_work; | |
725 | struct work_struct unpin_work; | |
726 | struct radeon_device *rdev; | |
727 | int crtc_id; | |
c60381bd | 728 | uint64_t base; |
6f34be50 | 729 | struct drm_pending_vblank_event *event; |
fa7f517c | 730 | struct radeon_bo *old_rbo; |
a0e84764 | 731 | struct fence *fence; |
6f34be50 AD |
732 | }; |
733 | ||
734 | struct r500_irq_stat_regs { | |
735 | u32 disp_int; | |
f122c610 | 736 | u32 hdmi0_status; |
6f34be50 AD |
737 | }; |
738 | ||
739 | struct r600_irq_stat_regs { | |
740 | u32 disp_int; | |
741 | u32 disp_int_cont; | |
742 | u32 disp_int_cont2; | |
743 | u32 d1grph_int; | |
744 | u32 d2grph_int; | |
f122c610 AD |
745 | u32 hdmi0_status; |
746 | u32 hdmi1_status; | |
6f34be50 AD |
747 | }; |
748 | ||
749 | struct evergreen_irq_stat_regs { | |
750 | u32 disp_int; | |
751 | u32 disp_int_cont; | |
752 | u32 disp_int_cont2; | |
753 | u32 disp_int_cont3; | |
754 | u32 disp_int_cont4; | |
755 | u32 disp_int_cont5; | |
756 | u32 d1grph_int; | |
757 | u32 d2grph_int; | |
758 | u32 d3grph_int; | |
759 | u32 d4grph_int; | |
760 | u32 d5grph_int; | |
761 | u32 d6grph_int; | |
f122c610 AD |
762 | u32 afmt_status1; |
763 | u32 afmt_status2; | |
764 | u32 afmt_status3; | |
765 | u32 afmt_status4; | |
766 | u32 afmt_status5; | |
767 | u32 afmt_status6; | |
6f34be50 AD |
768 | }; |
769 | ||
a59781bb AD |
770 | struct cik_irq_stat_regs { |
771 | u32 disp_int; | |
772 | u32 disp_int_cont; | |
773 | u32 disp_int_cont2; | |
774 | u32 disp_int_cont3; | |
775 | u32 disp_int_cont4; | |
776 | u32 disp_int_cont5; | |
777 | u32 disp_int_cont6; | |
f5d636d2 CK |
778 | u32 d1grph_int; |
779 | u32 d2grph_int; | |
780 | u32 d3grph_int; | |
781 | u32 d4grph_int; | |
782 | u32 d5grph_int; | |
783 | u32 d6grph_int; | |
a59781bb AD |
784 | }; |
785 | ||
6f34be50 AD |
786 | union radeon_irq_stat_regs { |
787 | struct r500_irq_stat_regs r500; | |
788 | struct r600_irq_stat_regs r600; | |
789 | struct evergreen_irq_stat_regs evergreen; | |
a59781bb | 790 | struct cik_irq_stat_regs cik; |
6f34be50 AD |
791 | }; |
792 | ||
771fe6b9 | 793 | struct radeon_irq { |
fb98257a CK |
794 | bool installed; |
795 | spinlock_t lock; | |
736fc37f | 796 | atomic_t ring_int[RADEON_NUM_RINGS]; |
fb98257a | 797 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
736fc37f | 798 | atomic_t pflip[RADEON_MAX_CRTCS]; |
fb98257a CK |
799 | wait_queue_head_t vblank_queue; |
800 | bool hpd[RADEON_MAX_HPD_PINS]; | |
fb98257a CK |
801 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
802 | union radeon_irq_stat_regs stat_regs; | |
4a6369e9 | 803 | bool dpm_thermal; |
771fe6b9 JG |
804 | }; |
805 | ||
806 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
807 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1b37078b | 808 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
954605ca | 809 | bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); |
1b37078b | 810 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
6f34be50 AD |
811 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
812 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); | |
fb98257a CK |
813 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
814 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); | |
815 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
816 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
771fe6b9 JG |
817 | |
818 | /* | |
e32eb50d | 819 | * CP & rings. |
771fe6b9 | 820 | */ |
7465280c | 821 | |
771fe6b9 | 822 | struct radeon_ib { |
68470ae7 JG |
823 | struct radeon_sa_bo *sa_bo; |
824 | uint32_t length_dw; | |
825 | uint64_t gpu_addr; | |
826 | uint32_t *ptr; | |
876dc9f3 | 827 | int ring; |
68470ae7 | 828 | struct radeon_fence *fence; |
4bf3dd92 | 829 | struct radeon_vm *vm; |
68470ae7 | 830 | bool is_const_ib; |
975700d2 | 831 | struct radeon_sync sync; |
771fe6b9 JG |
832 | }; |
833 | ||
e32eb50d | 834 | struct radeon_ring { |
4c788679 | 835 | struct radeon_bo *ring_obj; |
771fe6b9 | 836 | volatile uint32_t *ring; |
5596a9db | 837 | unsigned rptr_offs; |
45df6803 | 838 | unsigned rptr_save_reg; |
89d35807 AD |
839 | u64 next_rptr_gpu_addr; |
840 | volatile u32 *next_rptr_cpu_addr; | |
771fe6b9 JG |
841 | unsigned wptr; |
842 | unsigned wptr_old; | |
843 | unsigned ring_size; | |
844 | unsigned ring_free_dw; | |
845 | int count_dw; | |
aee4aa73 CK |
846 | atomic_t last_rptr; |
847 | atomic64_t last_activity; | |
771fe6b9 JG |
848 | uint64_t gpu_addr; |
849 | uint32_t align_mask; | |
850 | uint32_t ptr_mask; | |
771fe6b9 | 851 | bool ready; |
78c5560a | 852 | u32 nop; |
8b25ed34 | 853 | u32 idx; |
5f0839c1 JG |
854 | u64 last_semaphore_signal_addr; |
855 | u64 last_semaphore_wait_addr; | |
963e81f9 AD |
856 | /* for CIK queues */ |
857 | u32 me; | |
858 | u32 pipe; | |
859 | u32 queue; | |
860 | struct radeon_bo *mqd_obj; | |
d5754ab8 | 861 | u32 doorbell_index; |
963e81f9 AD |
862 | unsigned wptr_offs; |
863 | }; | |
864 | ||
865 | struct radeon_mec { | |
866 | struct radeon_bo *hpd_eop_obj; | |
867 | u64 hpd_eop_gpu_addr; | |
868 | u32 num_pipe; | |
869 | u32 num_mec; | |
870 | u32 num_queue; | |
771fe6b9 JG |
871 | }; |
872 | ||
721604a1 JG |
873 | /* |
874 | * VM | |
875 | */ | |
ee60e29f | 876 | |
fa87e62d | 877 | /* maximum number of VMIDs */ |
ee60e29f CK |
878 | #define RADEON_NUM_VM 16 |
879 | ||
fa87e62d | 880 | /* number of entries in page table */ |
4510fb98 | 881 | #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) |
fa87e62d | 882 | |
1c01103c AD |
883 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ |
884 | #define RADEON_VM_PTB_ALIGN_SIZE 32768 | |
885 | #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) | |
886 | #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) | |
887 | ||
24c16439 CK |
888 | #define R600_PTE_VALID (1 << 0) |
889 | #define R600_PTE_SYSTEM (1 << 1) | |
890 | #define R600_PTE_SNOOPED (1 << 2) | |
891 | #define R600_PTE_READABLE (1 << 5) | |
892 | #define R600_PTE_WRITEABLE (1 << 6) | |
893 | ||
ec3dbbcb CK |
894 | /* PTE (Page Table Entry) fragment field for different page sizes */ |
895 | #define R600_PTE_FRAG_4KB (0 << 7) | |
896 | #define R600_PTE_FRAG_64KB (4 << 7) | |
897 | #define R600_PTE_FRAG_256KB (6 << 7) | |
898 | ||
33fa9fe3 CK |
899 | /* flags needed to be set so we can copy directly from the GART table */ |
900 | #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ | |
901 | R600_PTE_SYSTEM | R600_PTE_VALID ) | |
0e97703c | 902 | |
6d2f2944 CK |
903 | struct radeon_vm_pt { |
904 | struct radeon_bo *bo; | |
905 | uint64_t addr; | |
906 | }; | |
907 | ||
7c42bc1a CK |
908 | struct radeon_vm_id { |
909 | unsigned id; | |
910 | uint64_t pd_gpu_addr; | |
911 | /* last flushed PD/PT update */ | |
912 | struct radeon_fence *flushed_updates; | |
913 | /* last use of vmid */ | |
914 | struct radeon_fence *last_id_use; | |
915 | }; | |
916 | ||
721604a1 | 917 | struct radeon_vm { |
7c42bc1a | 918 | struct rb_root va; |
90a51a32 | 919 | |
e31ad969 | 920 | /* BOs moved, but not yet updated in the PT */ |
7c42bc1a | 921 | struct list_head invalidated; |
e31ad969 | 922 | |
036bf46a | 923 | /* BOs freed, but not yet updated in the PT */ |
7c42bc1a | 924 | struct list_head freed; |
036bf46a | 925 | |
90a51a32 | 926 | /* contains the page directory */ |
7c42bc1a CK |
927 | struct radeon_bo *page_directory; |
928 | unsigned max_pde_used; | |
90a51a32 CK |
929 | |
930 | /* array of page tables, one for each page directory entry */ | |
7c42bc1a | 931 | struct radeon_vm_pt *page_tables; |
90a51a32 | 932 | |
7c42bc1a | 933 | struct radeon_bo_va *ib_bo_va; |
cc9e67e3 | 934 | |
7c42bc1a | 935 | struct mutex mutex; |
721604a1 | 936 | /* last fence for cs using this vm */ |
7c42bc1a CK |
937 | struct radeon_fence *fence; |
938 | ||
939 | /* for id and flush management per ring */ | |
940 | struct radeon_vm_id ids[RADEON_NUM_RINGS]; | |
721604a1 JG |
941 | }; |
942 | ||
721604a1 | 943 | struct radeon_vm_manager { |
ee60e29f | 944 | struct radeon_fence *active[RADEON_NUM_VM]; |
721604a1 | 945 | uint32_t max_pfn; |
721604a1 JG |
946 | /* number of VMIDs */ |
947 | unsigned nvm; | |
948 | /* vram base address for page table entry */ | |
949 | u64 vram_base_offset; | |
67e915e4 AD |
950 | /* is vm enabled? */ |
951 | bool enabled; | |
054e01d6 CK |
952 | /* for hw to save the PD addr on suspend/resume */ |
953 | uint32_t saved_table_addr[RADEON_NUM_VM]; | |
721604a1 JG |
954 | }; |
955 | ||
956 | /* | |
957 | * file private structure | |
958 | */ | |
959 | struct radeon_fpriv { | |
960 | struct radeon_vm vm; | |
961 | }; | |
962 | ||
d8f60cfc AD |
963 | /* |
964 | * R6xx+ IH ring | |
965 | */ | |
966 | struct r600_ih { | |
4c788679 | 967 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
968 | volatile uint32_t *ring; |
969 | unsigned rptr; | |
d8f60cfc AD |
970 | unsigned ring_size; |
971 | uint64_t gpu_addr; | |
d8f60cfc | 972 | uint32_t ptr_mask; |
c20dc369 | 973 | atomic_t lock; |
d8f60cfc AD |
974 | bool enabled; |
975 | }; | |
976 | ||
347e7592 | 977 | /* |
2948f5e6 | 978 | * RLC stuff |
347e7592 | 979 | */ |
2948f5e6 AD |
980 | #include "clearstate_defs.h" |
981 | ||
982 | struct radeon_rlc { | |
347e7592 AD |
983 | /* for power gating */ |
984 | struct radeon_bo *save_restore_obj; | |
985 | uint64_t save_restore_gpu_addr; | |
2948f5e6 | 986 | volatile uint32_t *sr_ptr; |
1fd11777 | 987 | const u32 *reg_list; |
2948f5e6 | 988 | u32 reg_list_size; |
347e7592 AD |
989 | /* for clear state */ |
990 | struct radeon_bo *clear_state_obj; | |
991 | uint64_t clear_state_gpu_addr; | |
2948f5e6 | 992 | volatile uint32_t *cs_ptr; |
1fd11777 | 993 | const struct cs_section_def *cs_data; |
22c775ce AD |
994 | u32 clear_state_size; |
995 | /* for cp tables */ | |
996 | struct radeon_bo *cp_table_obj; | |
997 | uint64_t cp_table_gpu_addr; | |
998 | volatile uint32_t *cp_table_ptr; | |
999 | u32 cp_table_size; | |
347e7592 AD |
1000 | }; |
1001 | ||
69e130a6 | 1002 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
1003 | struct radeon_ib *ib, struct radeon_vm *vm, |
1004 | unsigned size); | |
f2e39221 | 1005 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
4ef72566 | 1006 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
1538a9e0 | 1007 | struct radeon_ib *const_ib, bool hdp_flush); |
771fe6b9 JG |
1008 | int radeon_ib_pool_init(struct radeon_device *rdev); |
1009 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
7bd560e8 | 1010 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
771fe6b9 | 1011 | /* Ring access between begin & end cannot sleep */ |
89d35807 AD |
1012 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
1013 | struct radeon_ring *ring); | |
e32eb50d CK |
1014 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
1015 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
1016 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
1538a9e0 MD |
1017 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, |
1018 | bool hdp_flush); | |
1019 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, | |
1020 | bool hdp_flush); | |
d6999bc7 | 1021 | void radeon_ring_undo(struct radeon_ring *ring); |
e32eb50d CK |
1022 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
1023 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); | |
ff212f25 CK |
1024 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
1025 | struct radeon_ring *ring); | |
069211e5 | 1026 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
55d7c221 CK |
1027 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
1028 | uint32_t **data); | |
1029 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
1030 | unsigned size, uint32_t *data); | |
e32eb50d | 1031 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
ea31bf69 | 1032 | unsigned rptr_offs, u32 nop); |
e32eb50d | 1033 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
771fe6b9 JG |
1034 | |
1035 | ||
4d75658b AD |
1036 | /* r600 async dma */ |
1037 | void r600_dma_stop(struct radeon_device *rdev); | |
1038 | int r600_dma_resume(struct radeon_device *rdev); | |
1039 | void r600_dma_fini(struct radeon_device *rdev); | |
1040 | ||
8c5fd7ef AD |
1041 | void cayman_dma_stop(struct radeon_device *rdev); |
1042 | int cayman_dma_resume(struct radeon_device *rdev); | |
1043 | void cayman_dma_fini(struct radeon_device *rdev); | |
1044 | ||
771fe6b9 JG |
1045 | /* |
1046 | * CS. | |
1047 | */ | |
1048 | struct radeon_cs_reloc { | |
1049 | struct drm_gem_object *gobj; | |
4c788679 | 1050 | struct radeon_bo *robj; |
df0af440 CK |
1051 | struct ttm_validate_buffer tv; |
1052 | uint64_t gpu_offset; | |
ce6758c8 CK |
1053 | unsigned prefered_domains; |
1054 | unsigned allowed_domains; | |
df0af440 | 1055 | uint32_t tiling_flags; |
771fe6b9 | 1056 | uint32_t handle; |
771fe6b9 JG |
1057 | }; |
1058 | ||
1059 | struct radeon_cs_chunk { | |
1060 | uint32_t chunk_id; | |
1061 | uint32_t length_dw; | |
1062 | uint32_t *kdata; | |
721604a1 | 1063 | void __user *user_ptr; |
771fe6b9 JG |
1064 | }; |
1065 | ||
1066 | struct radeon_cs_parser { | |
c8c15ff1 | 1067 | struct device *dev; |
771fe6b9 JG |
1068 | struct radeon_device *rdev; |
1069 | struct drm_file *filp; | |
1070 | /* chunks */ | |
1071 | unsigned nchunks; | |
1072 | struct radeon_cs_chunk *chunks; | |
1073 | uint64_t *chunks_array; | |
1074 | /* IB */ | |
1075 | unsigned idx; | |
1076 | /* relocations */ | |
1077 | unsigned nrelocs; | |
1078 | struct radeon_cs_reloc *relocs; | |
1079 | struct radeon_cs_reloc **relocs_ptr; | |
df0af440 | 1080 | struct radeon_cs_reloc *vm_bos; |
771fe6b9 | 1081 | struct list_head validated; |
cf4ccd01 | 1082 | unsigned dma_reloc_idx; |
771fe6b9 JG |
1083 | /* indices of various chunks */ |
1084 | int chunk_ib_idx; | |
1085 | int chunk_relocs_idx; | |
721604a1 | 1086 | int chunk_flags_idx; |
dfcf5f36 | 1087 | int chunk_const_ib_idx; |
f2e39221 JG |
1088 | struct radeon_ib ib; |
1089 | struct radeon_ib const_ib; | |
771fe6b9 | 1090 | void *track; |
3ce0a23d | 1091 | unsigned family; |
e70f224c | 1092 | int parser_error; |
721604a1 JG |
1093 | u32 cs_flags; |
1094 | u32 ring; | |
1095 | s32 priority; | |
ecff665f | 1096 | struct ww_acquire_ctx ticket; |
771fe6b9 JG |
1097 | }; |
1098 | ||
28a326c5 ML |
1099 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
1100 | { | |
1101 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
1102 | ||
1103 | if (ibc->kdata) | |
1104 | return ibc->kdata[idx]; | |
1105 | return p->ib.ptr[idx]; | |
1106 | } | |
1107 | ||
513bcb46 | 1108 | |
771fe6b9 JG |
1109 | struct radeon_cs_packet { |
1110 | unsigned idx; | |
1111 | unsigned type; | |
1112 | unsigned reg; | |
1113 | unsigned opcode; | |
1114 | int count; | |
1115 | unsigned one_reg_wr; | |
1116 | }; | |
1117 | ||
1118 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
1119 | struct radeon_cs_packet *pkt, | |
1120 | unsigned idx, unsigned reg); | |
1121 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
1122 | struct radeon_cs_packet *pkt); | |
1123 | ||
1124 | ||
1125 | /* | |
1126 | * AGP | |
1127 | */ | |
1128 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 1129 | void radeon_agp_resume(struct radeon_device *rdev); |
10b06122 | 1130 | void radeon_agp_suspend(struct radeon_device *rdev); |
771fe6b9 JG |
1131 | void radeon_agp_fini(struct radeon_device *rdev); |
1132 | ||
1133 | ||
1134 | /* | |
1135 | * Writeback | |
1136 | */ | |
1137 | struct radeon_wb { | |
4c788679 | 1138 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
1139 | volatile uint32_t *wb; |
1140 | uint64_t gpu_addr; | |
724c80e1 | 1141 | bool enabled; |
d0f8a854 | 1142 | bool use_event; |
771fe6b9 JG |
1143 | }; |
1144 | ||
724c80e1 | 1145 | #define RADEON_WB_SCRATCH_OFFSET 0 |
89d35807 | 1146 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
724c80e1 | 1147 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
0c88a02e AD |
1148 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
1149 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 | |
4d75658b | 1150 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
724c80e1 | 1151 | #define R600_WB_IH_WPTR_OFFSET 2048 |
f60cbd11 | 1152 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
d0f8a854 | 1153 | #define R600_WB_EVENT_OFFSET 3072 |
963e81f9 AD |
1154 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
1155 | #define CIK_WB_CP2_WPTR_OFFSET 3584 | |
adfed2b0 AD |
1156 | #define R600_WB_DMA_RING_TEST_OFFSET 3588 |
1157 | #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 | |
724c80e1 | 1158 | |
c93bb85b JG |
1159 | /** |
1160 | * struct radeon_pm - power management datas | |
1161 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
1162 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
1163 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
1164 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
1165 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
1166 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
1167 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
1168 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
1169 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
25985edc | 1170 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
c93bb85b JG |
1171 | * @needed_bandwidth: current bandwidth needs |
1172 | * | |
1173 | * It keeps track of various data needed to take powermanagement decision. | |
25985edc | 1174 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
c93bb85b JG |
1175 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
1176 | * (type of memory, bus size, efficiency, ...) | |
1177 | */ | |
ce8f5370 AD |
1178 | |
1179 | enum radeon_pm_method { | |
1180 | PM_METHOD_PROFILE, | |
1181 | PM_METHOD_DYNPM, | |
da321c8a | 1182 | PM_METHOD_DPM, |
ce8f5370 AD |
1183 | }; |
1184 | ||
1185 | enum radeon_dynpm_state { | |
1186 | DYNPM_STATE_DISABLED, | |
1187 | DYNPM_STATE_MINIMUM, | |
1188 | DYNPM_STATE_PAUSED, | |
3f53eb6f RW |
1189 | DYNPM_STATE_ACTIVE, |
1190 | DYNPM_STATE_SUSPENDED, | |
c913e23a | 1191 | }; |
ce8f5370 AD |
1192 | enum radeon_dynpm_action { |
1193 | DYNPM_ACTION_NONE, | |
1194 | DYNPM_ACTION_MINIMUM, | |
1195 | DYNPM_ACTION_DOWNCLOCK, | |
1196 | DYNPM_ACTION_UPCLOCK, | |
1197 | DYNPM_ACTION_DEFAULT | |
c913e23a | 1198 | }; |
56278a8e AD |
1199 | |
1200 | enum radeon_voltage_type { | |
1201 | VOLTAGE_NONE = 0, | |
1202 | VOLTAGE_GPIO, | |
1203 | VOLTAGE_VDDC, | |
1204 | VOLTAGE_SW | |
1205 | }; | |
1206 | ||
0ec0e74f | 1207 | enum radeon_pm_state_type { |
da321c8a | 1208 | /* not used for dpm */ |
0ec0e74f AD |
1209 | POWER_STATE_TYPE_DEFAULT, |
1210 | POWER_STATE_TYPE_POWERSAVE, | |
da321c8a | 1211 | /* user selectable states */ |
0ec0e74f AD |
1212 | POWER_STATE_TYPE_BATTERY, |
1213 | POWER_STATE_TYPE_BALANCED, | |
1214 | POWER_STATE_TYPE_PERFORMANCE, | |
da321c8a AD |
1215 | /* internal states */ |
1216 | POWER_STATE_TYPE_INTERNAL_UVD, | |
1217 | POWER_STATE_TYPE_INTERNAL_UVD_SD, | |
1218 | POWER_STATE_TYPE_INTERNAL_UVD_HD, | |
1219 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, | |
1220 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, | |
1221 | POWER_STATE_TYPE_INTERNAL_BOOT, | |
1222 | POWER_STATE_TYPE_INTERNAL_THERMAL, | |
1223 | POWER_STATE_TYPE_INTERNAL_ACPI, | |
1224 | POWER_STATE_TYPE_INTERNAL_ULV, | |
edcaa5b1 | 1225 | POWER_STATE_TYPE_INTERNAL_3DPERF, |
0ec0e74f AD |
1226 | }; |
1227 | ||
ce8f5370 AD |
1228 | enum radeon_pm_profile_type { |
1229 | PM_PROFILE_DEFAULT, | |
1230 | PM_PROFILE_AUTO, | |
1231 | PM_PROFILE_LOW, | |
c9e75b21 | 1232 | PM_PROFILE_MID, |
ce8f5370 AD |
1233 | PM_PROFILE_HIGH, |
1234 | }; | |
1235 | ||
1236 | #define PM_PROFILE_DEFAULT_IDX 0 | |
1237 | #define PM_PROFILE_LOW_SH_IDX 1 | |
c9e75b21 AD |
1238 | #define PM_PROFILE_MID_SH_IDX 2 |
1239 | #define PM_PROFILE_HIGH_SH_IDX 3 | |
1240 | #define PM_PROFILE_LOW_MH_IDX 4 | |
1241 | #define PM_PROFILE_MID_MH_IDX 5 | |
1242 | #define PM_PROFILE_HIGH_MH_IDX 6 | |
1243 | #define PM_PROFILE_MAX 7 | |
ce8f5370 AD |
1244 | |
1245 | struct radeon_pm_profile { | |
1246 | int dpms_off_ps_idx; | |
1247 | int dpms_on_ps_idx; | |
1248 | int dpms_off_cm_idx; | |
1249 | int dpms_on_cm_idx; | |
516d0e46 AD |
1250 | }; |
1251 | ||
21a8122a AD |
1252 | enum radeon_int_thermal_type { |
1253 | THERMAL_TYPE_NONE, | |
da321c8a AD |
1254 | THERMAL_TYPE_EXTERNAL, |
1255 | THERMAL_TYPE_EXTERNAL_GPIO, | |
21a8122a AD |
1256 | THERMAL_TYPE_RV6XX, |
1257 | THERMAL_TYPE_RV770, | |
da321c8a | 1258 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, |
21a8122a | 1259 | THERMAL_TYPE_EVERGREEN, |
e33df25f | 1260 | THERMAL_TYPE_SUMO, |
4fddba1f | 1261 | THERMAL_TYPE_NI, |
14607d08 | 1262 | THERMAL_TYPE_SI, |
da321c8a | 1263 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, |
51150207 | 1264 | THERMAL_TYPE_CI, |
16fbe00d | 1265 | THERMAL_TYPE_KV, |
21a8122a AD |
1266 | }; |
1267 | ||
56278a8e AD |
1268 | struct radeon_voltage { |
1269 | enum radeon_voltage_type type; | |
1270 | /* gpio voltage */ | |
1271 | struct radeon_gpio_rec gpio; | |
1272 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
1273 | bool active_high; /* voltage drop is active when bit is high */ | |
1274 | /* VDDC voltage */ | |
1275 | u8 vddc_id; /* index into vddc voltage table */ | |
1276 | u8 vddci_id; /* index into vddci voltage table */ | |
1277 | bool vddci_enabled; | |
1278 | /* r6xx+ sw */ | |
2feea49a AD |
1279 | u16 voltage; |
1280 | /* evergreen+ vddci */ | |
1281 | u16 vddci; | |
56278a8e AD |
1282 | }; |
1283 | ||
d7311171 AD |
1284 | /* clock mode flags */ |
1285 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) | |
1286 | ||
56278a8e AD |
1287 | struct radeon_pm_clock_info { |
1288 | /* memory clock */ | |
1289 | u32 mclk; | |
1290 | /* engine clock */ | |
1291 | u32 sclk; | |
1292 | /* voltage info */ | |
1293 | struct radeon_voltage voltage; | |
d7311171 | 1294 | /* standardized clock flags */ |
56278a8e AD |
1295 | u32 flags; |
1296 | }; | |
1297 | ||
a48b9b4e | 1298 | /* state flags */ |
d7311171 | 1299 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
a48b9b4e | 1300 | |
56278a8e | 1301 | struct radeon_power_state { |
0ec0e74f | 1302 | enum radeon_pm_state_type type; |
8f3f1c9a | 1303 | struct radeon_pm_clock_info *clock_info; |
56278a8e AD |
1304 | /* number of valid clock modes in this power state */ |
1305 | int num_clock_modes; | |
56278a8e | 1306 | struct radeon_pm_clock_info *default_clock_mode; |
a48b9b4e AD |
1307 | /* standardized state flags */ |
1308 | u32 flags; | |
79daedc9 AD |
1309 | u32 misc; /* vbios specific flags */ |
1310 | u32 misc2; /* vbios specific flags */ | |
1311 | int pcie_lanes; /* pcie lanes */ | |
56278a8e AD |
1312 | }; |
1313 | ||
27459324 RM |
1314 | /* |
1315 | * Some modes are overclocked by very low value, accept them | |
1316 | */ | |
1317 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
1318 | ||
2e9d4c05 AD |
1319 | enum radeon_dpm_auto_throttle_src { |
1320 | RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, | |
1321 | RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL | |
1322 | }; | |
1323 | ||
1324 | enum radeon_dpm_event_src { | |
1325 | RADEON_DPM_EVENT_SRC_ANALOG = 0, | |
1326 | RADEON_DPM_EVENT_SRC_EXTERNAL = 1, | |
1327 | RADEON_DPM_EVENT_SRC_DIGITAL = 2, | |
1328 | RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, | |
1329 | RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 | |
1330 | }; | |
1331 | ||
58bd2a88 AD |
1332 | #define RADEON_MAX_VCE_LEVELS 6 |
1333 | ||
b62d628b AD |
1334 | enum radeon_vce_level { |
1335 | RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ | |
1336 | RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ | |
1337 | RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ | |
1338 | RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ | |
1339 | RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ | |
1340 | RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ | |
1341 | }; | |
1342 | ||
da321c8a AD |
1343 | struct radeon_ps { |
1344 | u32 caps; /* vbios flags */ | |
1345 | u32 class; /* vbios flags */ | |
1346 | u32 class2; /* vbios flags */ | |
1347 | /* UVD clocks */ | |
1348 | u32 vclk; | |
1349 | u32 dclk; | |
c4453e66 AD |
1350 | /* VCE clocks */ |
1351 | u32 evclk; | |
1352 | u32 ecclk; | |
b62d628b AD |
1353 | bool vce_active; |
1354 | enum radeon_vce_level vce_level; | |
da321c8a AD |
1355 | /* asic priv */ |
1356 | void *ps_priv; | |
1357 | }; | |
1358 | ||
1359 | struct radeon_dpm_thermal { | |
1360 | /* thermal interrupt work */ | |
1361 | struct work_struct work; | |
1362 | /* low temperature threshold */ | |
1363 | int min_temp; | |
1364 | /* high temperature threshold */ | |
1365 | int max_temp; | |
1366 | /* was interrupt low to high or high to low */ | |
1367 | bool high_to_low; | |
1368 | }; | |
1369 | ||
d22b7e40 AD |
1370 | enum radeon_clk_action |
1371 | { | |
1372 | RADEON_SCLK_UP = 1, | |
1373 | RADEON_SCLK_DOWN | |
1374 | }; | |
1375 | ||
1376 | struct radeon_blacklist_clocks | |
1377 | { | |
1378 | u32 sclk; | |
1379 | u32 mclk; | |
1380 | enum radeon_clk_action action; | |
1381 | }; | |
1382 | ||
61b7d601 AD |
1383 | struct radeon_clock_and_voltage_limits { |
1384 | u32 sclk; | |
1385 | u32 mclk; | |
cdf6e805 AD |
1386 | u16 vddc; |
1387 | u16 vddci; | |
61b7d601 AD |
1388 | }; |
1389 | ||
1390 | struct radeon_clock_array { | |
1391 | u32 count; | |
1392 | u32 *values; | |
1393 | }; | |
1394 | ||
1395 | struct radeon_clock_voltage_dependency_entry { | |
1396 | u32 clk; | |
1397 | u16 v; | |
1398 | }; | |
1399 | ||
1400 | struct radeon_clock_voltage_dependency_table { | |
1401 | u32 count; | |
1402 | struct radeon_clock_voltage_dependency_entry *entries; | |
1403 | }; | |
1404 | ||
ef976ec4 AD |
1405 | union radeon_cac_leakage_entry { |
1406 | struct { | |
1407 | u16 vddc; | |
1408 | u32 leakage; | |
1409 | }; | |
1410 | struct { | |
1411 | u16 vddc1; | |
1412 | u16 vddc2; | |
1413 | u16 vddc3; | |
1414 | }; | |
61b7d601 AD |
1415 | }; |
1416 | ||
1417 | struct radeon_cac_leakage_table { | |
1418 | u32 count; | |
ef976ec4 | 1419 | union radeon_cac_leakage_entry *entries; |
61b7d601 AD |
1420 | }; |
1421 | ||
929ee7a8 AD |
1422 | struct radeon_phase_shedding_limits_entry { |
1423 | u16 voltage; | |
1424 | u32 sclk; | |
1425 | u32 mclk; | |
1426 | }; | |
1427 | ||
1428 | struct radeon_phase_shedding_limits_table { | |
1429 | u32 count; | |
1430 | struct radeon_phase_shedding_limits_entry *entries; | |
1431 | }; | |
1432 | ||
84a9d9ee AD |
1433 | struct radeon_uvd_clock_voltage_dependency_entry { |
1434 | u32 vclk; | |
1435 | u32 dclk; | |
1436 | u16 v; | |
1437 | }; | |
1438 | ||
1439 | struct radeon_uvd_clock_voltage_dependency_table { | |
1440 | u8 count; | |
1441 | struct radeon_uvd_clock_voltage_dependency_entry *entries; | |
1442 | }; | |
1443 | ||
d29f013b AD |
1444 | struct radeon_vce_clock_voltage_dependency_entry { |
1445 | u32 ecclk; | |
1446 | u32 evclk; | |
1447 | u16 v; | |
1448 | }; | |
1449 | ||
1450 | struct radeon_vce_clock_voltage_dependency_table { | |
1451 | u8 count; | |
1452 | struct radeon_vce_clock_voltage_dependency_entry *entries; | |
1453 | }; | |
1454 | ||
a5cb318e AD |
1455 | struct radeon_ppm_table { |
1456 | u8 ppm_design; | |
1457 | u16 cpu_core_number; | |
1458 | u32 platform_tdp; | |
1459 | u32 small_ac_platform_tdp; | |
1460 | u32 platform_tdc; | |
1461 | u32 small_ac_platform_tdc; | |
1462 | u32 apu_tdp; | |
1463 | u32 dgpu_tdp; | |
1464 | u32 dgpu_ulv_power; | |
1465 | u32 tj_max; | |
1466 | }; | |
1467 | ||
58cb7632 AD |
1468 | struct radeon_cac_tdp_table { |
1469 | u16 tdp; | |
1470 | u16 configurable_tdp; | |
1471 | u16 tdc; | |
1472 | u16 battery_power_limit; | |
1473 | u16 small_power_limit; | |
1474 | u16 low_cac_leakage; | |
1475 | u16 high_cac_leakage; | |
1476 | u16 maximum_power_delivery_limit; | |
1477 | }; | |
1478 | ||
61b7d601 AD |
1479 | struct radeon_dpm_dynamic_state { |
1480 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; | |
1481 | struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; | |
1482 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; | |
dd621a22 | 1483 | struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; |
4489cd62 | 1484 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; |
84a9d9ee | 1485 | struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; |
d29f013b | 1486 | struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; |
94a914f5 AD |
1487 | struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; |
1488 | struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; | |
61b7d601 AD |
1489 | struct radeon_clock_array valid_sclk_values; |
1490 | struct radeon_clock_array valid_mclk_values; | |
1491 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; | |
1492 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; | |
1493 | u32 mclk_sclk_ratio; | |
1494 | u32 sclk_mclk_delta; | |
1495 | u16 vddc_vddci_delta; | |
1496 | u16 min_vddc_for_pcie_gen2; | |
1497 | struct radeon_cac_leakage_table cac_leakage_table; | |
929ee7a8 | 1498 | struct radeon_phase_shedding_limits_table phase_shedding_limits_table; |
a5cb318e | 1499 | struct radeon_ppm_table *ppm_table; |
58cb7632 | 1500 | struct radeon_cac_tdp_table *cac_tdp_table; |
61b7d601 AD |
1501 | }; |
1502 | ||
1503 | struct radeon_dpm_fan { | |
1504 | u16 t_min; | |
1505 | u16 t_med; | |
1506 | u16 t_high; | |
1507 | u16 pwm_min; | |
1508 | u16 pwm_med; | |
1509 | u16 pwm_high; | |
1510 | u8 t_hyst; | |
1511 | u32 cycle_delay; | |
1512 | u16 t_max; | |
e03cea36 AD |
1513 | u8 control_mode; |
1514 | u16 default_max_fan_pwm; | |
1515 | u16 default_fan_output_sensitivity; | |
1516 | u16 fan_output_sensitivity; | |
61b7d601 AD |
1517 | bool ucode_fan_control; |
1518 | }; | |
1519 | ||
32ce4652 AD |
1520 | enum radeon_pcie_gen { |
1521 | RADEON_PCIE_GEN1 = 0, | |
1522 | RADEON_PCIE_GEN2 = 1, | |
1523 | RADEON_PCIE_GEN3 = 2, | |
1524 | RADEON_PCIE_GEN_INVALID = 0xffff | |
1525 | }; | |
1526 | ||
70d01a5e AD |
1527 | enum radeon_dpm_forced_level { |
1528 | RADEON_DPM_FORCED_LEVEL_AUTO = 0, | |
1529 | RADEON_DPM_FORCED_LEVEL_LOW = 1, | |
1530 | RADEON_DPM_FORCED_LEVEL_HIGH = 2, | |
1531 | }; | |
1532 | ||
58bd2a88 AD |
1533 | struct radeon_vce_state { |
1534 | /* vce clocks */ | |
1535 | u32 evclk; | |
1536 | u32 ecclk; | |
1537 | /* gpu clocks */ | |
1538 | u32 sclk; | |
1539 | u32 mclk; | |
1540 | u8 clk_idx; | |
1541 | u8 pstate; | |
1542 | }; | |
1543 | ||
da321c8a AD |
1544 | struct radeon_dpm { |
1545 | struct radeon_ps *ps; | |
1546 | /* number of valid power states */ | |
1547 | int num_ps; | |
1548 | /* current power state that is active */ | |
1549 | struct radeon_ps *current_ps; | |
1550 | /* requested power state */ | |
1551 | struct radeon_ps *requested_ps; | |
1552 | /* boot up power state */ | |
1553 | struct radeon_ps *boot_ps; | |
1554 | /* default uvd power state */ | |
1555 | struct radeon_ps *uvd_ps; | |
58bd2a88 AD |
1556 | /* vce requirements */ |
1557 | struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; | |
1558 | enum radeon_vce_level vce_level; | |
da321c8a AD |
1559 | enum radeon_pm_state_type state; |
1560 | enum radeon_pm_state_type user_state; | |
1561 | u32 platform_caps; | |
1562 | u32 voltage_response_time; | |
1563 | u32 backbias_response_time; | |
1564 | void *priv; | |
1565 | u32 new_active_crtcs; | |
1566 | int new_active_crtc_count; | |
1567 | u32 current_active_crtcs; | |
1568 | int current_active_crtc_count; | |
61b7d601 AD |
1569 | struct radeon_dpm_dynamic_state dyn_state; |
1570 | struct radeon_dpm_fan fan; | |
1571 | u32 tdp_limit; | |
1572 | u32 near_tdp_limit; | |
a9e61410 | 1573 | u32 near_tdp_limit_adjusted; |
61b7d601 AD |
1574 | u32 sq_ramping_threshold; |
1575 | u32 cac_leakage; | |
1576 | u16 tdp_od_limit; | |
1577 | u32 tdp_adjustment; | |
1578 | u16 load_line_slope; | |
1579 | bool power_control; | |
5ca302f7 | 1580 | bool ac_power; |
da321c8a AD |
1581 | /* special states active */ |
1582 | bool thermal_active; | |
8a227555 | 1583 | bool uvd_active; |
b62d628b | 1584 | bool vce_active; |
da321c8a AD |
1585 | /* thermal handling */ |
1586 | struct radeon_dpm_thermal thermal; | |
70d01a5e AD |
1587 | /* forced levels */ |
1588 | enum radeon_dpm_forced_level forced_level; | |
ce3537d5 AD |
1589 | /* track UVD streams */ |
1590 | unsigned sd; | |
1591 | unsigned hd; | |
da321c8a AD |
1592 | }; |
1593 | ||
ce3537d5 | 1594 | void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); |
03afe6f6 | 1595 | void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); |
da321c8a | 1596 | |
c93bb85b | 1597 | struct radeon_pm { |
c913e23a | 1598 | struct mutex mutex; |
db7fce39 CK |
1599 | /* write locked while reprogramming mclk */ |
1600 | struct rw_semaphore mclk_lock; | |
a48b9b4e AD |
1601 | u32 active_crtcs; |
1602 | int active_crtc_count; | |
c913e23a | 1603 | int req_vblank; |
839461d3 | 1604 | bool vblank_sync; |
c93bb85b JG |
1605 | fixed20_12 max_bandwidth; |
1606 | fixed20_12 igp_sideport_mclk; | |
1607 | fixed20_12 igp_system_mclk; | |
1608 | fixed20_12 igp_ht_link_clk; | |
1609 | fixed20_12 igp_ht_link_width; | |
1610 | fixed20_12 k8_bandwidth; | |
1611 | fixed20_12 sideport_bandwidth; | |
1612 | fixed20_12 ht_bandwidth; | |
1613 | fixed20_12 core_bandwidth; | |
1614 | fixed20_12 sclk; | |
f47299c5 | 1615 | fixed20_12 mclk; |
c93bb85b | 1616 | fixed20_12 needed_bandwidth; |
0975b162 | 1617 | struct radeon_power_state *power_state; |
56278a8e AD |
1618 | /* number of valid power states */ |
1619 | int num_power_states; | |
a48b9b4e AD |
1620 | int current_power_state_index; |
1621 | int current_clock_mode_index; | |
1622 | int requested_power_state_index; | |
1623 | int requested_clock_mode_index; | |
1624 | int default_power_state_index; | |
1625 | u32 current_sclk; | |
1626 | u32 current_mclk; | |
2feea49a AD |
1627 | u16 current_vddc; |
1628 | u16 current_vddci; | |
9ace9f7b AD |
1629 | u32 default_sclk; |
1630 | u32 default_mclk; | |
2feea49a AD |
1631 | u16 default_vddc; |
1632 | u16 default_vddci; | |
29fb52ca | 1633 | struct radeon_i2c_chan *i2c_bus; |
ce8f5370 AD |
1634 | /* selected pm method */ |
1635 | enum radeon_pm_method pm_method; | |
1636 | /* dynpm power management */ | |
1637 | struct delayed_work dynpm_idle_work; | |
1638 | enum radeon_dynpm_state dynpm_state; | |
1639 | enum radeon_dynpm_action dynpm_planned_action; | |
1640 | unsigned long dynpm_action_timeout; | |
1641 | bool dynpm_can_upclock; | |
1642 | bool dynpm_can_downclock; | |
1643 | /* profile-based power management */ | |
1644 | enum radeon_pm_profile_type profile; | |
1645 | int profile_index; | |
1646 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; | |
21a8122a AD |
1647 | /* internal thermal controller on rv6xx+ */ |
1648 | enum radeon_int_thermal_type int_thermal_type; | |
1649 | struct device *int_hwmon_dev; | |
9b92d1ec AD |
1650 | /* fan control parameters */ |
1651 | bool no_fan; | |
1652 | u8 fan_pulses_per_revolution; | |
1653 | u8 fan_min_rpm; | |
1654 | u8 fan_max_rpm; | |
da321c8a AD |
1655 | /* dpm */ |
1656 | bool dpm_enabled; | |
1657 | struct radeon_dpm dpm; | |
c93bb85b JG |
1658 | }; |
1659 | ||
a4c9e2ee AD |
1660 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1661 | enum radeon_pm_state_type ps_type, | |
1662 | int instance); | |
f2ba57b5 CK |
1663 | /* |
1664 | * UVD | |
1665 | */ | |
1666 | #define RADEON_MAX_UVD_HANDLES 10 | |
1667 | #define RADEON_UVD_STACK_SIZE (1024*1024) | |
1668 | #define RADEON_UVD_HEAP_SIZE (1024*1024) | |
1669 | ||
1670 | struct radeon_uvd { | |
1671 | struct radeon_bo *vcpu_bo; | |
1672 | void *cpu_addr; | |
1673 | uint64_t gpu_addr; | |
9cc2e0e9 | 1674 | void *saved_bo; |
f2ba57b5 CK |
1675 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; |
1676 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; | |
85a129ca | 1677 | unsigned img_size[RADEON_MAX_UVD_HANDLES]; |
55b51c88 | 1678 | struct delayed_work idle_work; |
f2ba57b5 CK |
1679 | }; |
1680 | ||
1681 | int radeon_uvd_init(struct radeon_device *rdev); | |
1682 | void radeon_uvd_fini(struct radeon_device *rdev); | |
1683 | int radeon_uvd_suspend(struct radeon_device *rdev); | |
1684 | int radeon_uvd_resume(struct radeon_device *rdev); | |
1685 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, | |
1686 | uint32_t handle, struct radeon_fence **fence); | |
1687 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, | |
1688 | uint32_t handle, struct radeon_fence **fence); | |
3852752c CK |
1689 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, |
1690 | uint32_t allowed_domains); | |
f2ba57b5 CK |
1691 | void radeon_uvd_free_handles(struct radeon_device *rdev, |
1692 | struct drm_file *filp); | |
1693 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); | |
55b51c88 | 1694 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
facd112d CK |
1695 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
1696 | unsigned vclk, unsigned dclk, | |
1697 | unsigned vco_min, unsigned vco_max, | |
1698 | unsigned fb_factor, unsigned fb_mask, | |
1699 | unsigned pd_min, unsigned pd_max, | |
1700 | unsigned pd_even, | |
1701 | unsigned *optimal_fb_div, | |
1702 | unsigned *optimal_vclk_div, | |
1703 | unsigned *optimal_dclk_div); | |
1704 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, | |
1705 | unsigned cg_upll_func_cntl); | |
771fe6b9 | 1706 | |
d93f7937 CK |
1707 | /* |
1708 | * VCE | |
1709 | */ | |
1710 | #define RADEON_MAX_VCE_HANDLES 16 | |
1711 | #define RADEON_VCE_STACK_SIZE (1024*1024) | |
1712 | #define RADEON_VCE_HEAP_SIZE (4*1024*1024) | |
1713 | ||
1714 | struct radeon_vce { | |
1715 | struct radeon_bo *vcpu_bo; | |
d93f7937 | 1716 | uint64_t gpu_addr; |
98ccc291 CK |
1717 | unsigned fw_version; |
1718 | unsigned fb_version; | |
d93f7937 CK |
1719 | atomic_t handles[RADEON_MAX_VCE_HANDLES]; |
1720 | struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; | |
2fc5703a | 1721 | unsigned img_size[RADEON_MAX_VCE_HANDLES]; |
03afe6f6 | 1722 | struct delayed_work idle_work; |
d93f7937 CK |
1723 | }; |
1724 | ||
1725 | int radeon_vce_init(struct radeon_device *rdev); | |
1726 | void radeon_vce_fini(struct radeon_device *rdev); | |
1727 | int radeon_vce_suspend(struct radeon_device *rdev); | |
1728 | int radeon_vce_resume(struct radeon_device *rdev); | |
1729 | int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, | |
1730 | uint32_t handle, struct radeon_fence **fence); | |
1731 | int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, | |
1732 | uint32_t handle, struct radeon_fence **fence); | |
1733 | void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); | |
03afe6f6 | 1734 | void radeon_vce_note_usage(struct radeon_device *rdev); |
2fc5703a | 1735 | int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); |
d93f7937 CK |
1736 | int radeon_vce_cs_parse(struct radeon_cs_parser *p); |
1737 | bool radeon_vce_semaphore_emit(struct radeon_device *rdev, | |
1738 | struct radeon_ring *ring, | |
1739 | struct radeon_semaphore *semaphore, | |
1740 | bool emit_wait); | |
1741 | void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
1742 | void radeon_vce_fence_emit(struct radeon_device *rdev, | |
1743 | struct radeon_fence *fence); | |
1744 | int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
1745 | int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
1746 | ||
b530602f | 1747 | struct r600_audio_pin { |
a92553ab RM |
1748 | int channels; |
1749 | int rate; | |
1750 | int bits_per_sample; | |
1751 | u8 status_bits; | |
1752 | u8 category_code; | |
b530602f AD |
1753 | u32 offset; |
1754 | bool connected; | |
1755 | u32 id; | |
1756 | }; | |
1757 | ||
1758 | struct r600_audio { | |
1759 | bool enabled; | |
1760 | struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; | |
1761 | int num_pins; | |
a92553ab RM |
1762 | }; |
1763 | ||
771fe6b9 JG |
1764 | /* |
1765 | * Benchmarking | |
1766 | */ | |
638dd7db | 1767 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
771fe6b9 JG |
1768 | |
1769 | ||
ecc0b326 MD |
1770 | /* |
1771 | * Testing | |
1772 | */ | |
1773 | void radeon_test_moves(struct radeon_device *rdev); | |
60a7e396 | 1774 | void radeon_test_ring_sync(struct radeon_device *rdev, |
e32eb50d CK |
1775 | struct radeon_ring *cpA, |
1776 | struct radeon_ring *cpB); | |
60a7e396 | 1777 | void radeon_test_syncing(struct radeon_device *rdev); |
ecc0b326 | 1778 | |
341cb9e4 CK |
1779 | /* |
1780 | * MMU Notifier | |
1781 | */ | |
1782 | int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); | |
1783 | void radeon_mn_unregister(struct radeon_bo *bo); | |
ecc0b326 | 1784 | |
771fe6b9 JG |
1785 | /* |
1786 | * Debugfs | |
1787 | */ | |
4d8bf9ae CK |
1788 | struct radeon_debugfs { |
1789 | struct drm_info_list *files; | |
1790 | unsigned num_files; | |
1791 | }; | |
1792 | ||
771fe6b9 JG |
1793 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1794 | struct drm_info_list *files, | |
1795 | unsigned nfiles); | |
1796 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 | 1797 | |
76a0df85 CK |
1798 | /* |
1799 | * ASIC ring specific functions. | |
1800 | */ | |
1801 | struct radeon_asic_ring { | |
1802 | /* ring read/write ptr handling */ | |
1803 | u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); | |
1804 | u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); | |
1805 | void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); | |
1806 | ||
1807 | /* validating and patching of IBs */ | |
1808 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); | |
1809 | int (*cs_parse)(struct radeon_cs_parser *p); | |
1810 | ||
1811 | /* command emmit functions */ | |
1812 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
1813 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); | |
72a9987e | 1814 | void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); |
1654b817 | 1815 | bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
76a0df85 | 1816 | struct radeon_semaphore *semaphore, bool emit_wait); |
faffaf62 CK |
1817 | void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, |
1818 | unsigned vm_id, uint64_t pd_addr); | |
76a0df85 CK |
1819 | |
1820 | /* testing functions */ | |
1821 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1822 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1823 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1824 | ||
1825 | /* deprecated */ | |
1826 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1827 | }; | |
771fe6b9 JG |
1828 | |
1829 | /* | |
1830 | * ASIC specific functions. | |
1831 | */ | |
1832 | struct radeon_asic { | |
068a117c | 1833 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
1834 | void (*fini)(struct radeon_device *rdev); |
1835 | int (*resume)(struct radeon_device *rdev); | |
1836 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 1837 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
a2d07b74 | 1838 | int (*asic_reset)(struct radeon_device *rdev); |
124764f1 MD |
1839 | /* Flush the HDP cache via MMIO */ |
1840 | void (*mmio_hdp_flush)(struct radeon_device *rdev); | |
54e88e06 AD |
1841 | /* check if 3D engine is idle */ |
1842 | bool (*gui_idle)(struct radeon_device *rdev); | |
1843 | /* wait for mc_idle */ | |
1844 | int (*mc_wait_for_idle)(struct radeon_device *rdev); | |
454d2e2a AD |
1845 | /* get the reference clock */ |
1846 | u32 (*get_xclk)(struct radeon_device *rdev); | |
d0418894 AD |
1847 | /* get the gpu clock counter */ |
1848 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); | |
54e88e06 | 1849 | /* gart */ |
c5b3b850 AD |
1850 | struct { |
1851 | void (*tlb_flush)(struct radeon_device *rdev); | |
7f90fc96 | 1852 | void (*set_page)(struct radeon_device *rdev, unsigned i, |
77497f27 | 1853 | uint64_t addr, uint32_t flags); |
c5b3b850 | 1854 | } gart; |
05b07147 CK |
1855 | struct { |
1856 | int (*init)(struct radeon_device *rdev); | |
1857 | void (*fini)(struct radeon_device *rdev); | |
03f62abd CK |
1858 | void (*copy_pages)(struct radeon_device *rdev, |
1859 | struct radeon_ib *ib, | |
1860 | uint64_t pe, uint64_t src, | |
1861 | unsigned count); | |
1862 | void (*write_pages)(struct radeon_device *rdev, | |
1863 | struct radeon_ib *ib, | |
1864 | uint64_t pe, | |
1865 | uint64_t addr, unsigned count, | |
1866 | uint32_t incr, uint32_t flags); | |
1867 | void (*set_pages)(struct radeon_device *rdev, | |
1868 | struct radeon_ib *ib, | |
1869 | uint64_t pe, | |
1870 | uint64_t addr, unsigned count, | |
1871 | uint32_t incr, uint32_t flags); | |
1872 | void (*pad_ib)(struct radeon_ib *ib); | |
05b07147 | 1873 | } vm; |
54e88e06 | 1874 | /* ring specific callbacks */ |
76a0df85 | 1875 | struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; |
54e88e06 | 1876 | /* irqs */ |
b35ea4ab AD |
1877 | struct { |
1878 | int (*set)(struct radeon_device *rdev); | |
1879 | int (*process)(struct radeon_device *rdev); | |
1880 | } irq; | |
54e88e06 | 1881 | /* displays */ |
c79a49ca AD |
1882 | struct { |
1883 | /* display watermarks */ | |
1884 | void (*bandwidth_update)(struct radeon_device *rdev); | |
1885 | /* get frame count */ | |
1886 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); | |
1887 | /* wait for vblank */ | |
1888 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); | |
37e9b6a6 AD |
1889 | /* set backlight level */ |
1890 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); | |
6d92f81d AD |
1891 | /* get backlight level */ |
1892 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); | |
a973bea1 AD |
1893 | /* audio callbacks */ |
1894 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); | |
1895 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
c79a49ca | 1896 | } display; |
54e88e06 | 1897 | /* copy functions for bo handling */ |
27cd7769 | 1898 | struct { |
57d20a43 CK |
1899 | struct radeon_fence *(*blit)(struct radeon_device *rdev, |
1900 | uint64_t src_offset, | |
1901 | uint64_t dst_offset, | |
1902 | unsigned num_gpu_pages, | |
1903 | struct reservation_object *resv); | |
27cd7769 | 1904 | u32 blit_ring_index; |
57d20a43 CK |
1905 | struct radeon_fence *(*dma)(struct radeon_device *rdev, |
1906 | uint64_t src_offset, | |
1907 | uint64_t dst_offset, | |
1908 | unsigned num_gpu_pages, | |
1909 | struct reservation_object *resv); | |
27cd7769 AD |
1910 | u32 dma_ring_index; |
1911 | /* method used for bo copy */ | |
57d20a43 CK |
1912 | struct radeon_fence *(*copy)(struct radeon_device *rdev, |
1913 | uint64_t src_offset, | |
1914 | uint64_t dst_offset, | |
1915 | unsigned num_gpu_pages, | |
1916 | struct reservation_object *resv); | |
27cd7769 AD |
1917 | /* ring used for bo copies */ |
1918 | u32 copy_ring_index; | |
1919 | } copy; | |
54e88e06 | 1920 | /* surfaces */ |
9e6f3d02 AD |
1921 | struct { |
1922 | int (*set_reg)(struct radeon_device *rdev, int reg, | |
1923 | uint32_t tiling_flags, uint32_t pitch, | |
1924 | uint32_t offset, uint32_t obj_size); | |
1925 | void (*clear_reg)(struct radeon_device *rdev, int reg); | |
1926 | } surface; | |
54e88e06 | 1927 | /* hotplug detect */ |
901ea57d AD |
1928 | struct { |
1929 | void (*init)(struct radeon_device *rdev); | |
1930 | void (*fini)(struct radeon_device *rdev); | |
1931 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1932 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1933 | } hpd; | |
da321c8a | 1934 | /* static power management */ |
a02fa397 AD |
1935 | struct { |
1936 | void (*misc)(struct radeon_device *rdev); | |
1937 | void (*prepare)(struct radeon_device *rdev); | |
1938 | void (*finish)(struct radeon_device *rdev); | |
1939 | void (*init_profile)(struct radeon_device *rdev); | |
1940 | void (*get_dynpm_state)(struct radeon_device *rdev); | |
798bcf73 AD |
1941 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1942 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); | |
1943 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); | |
1944 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); | |
1945 | int (*get_pcie_lanes)(struct radeon_device *rdev); | |
1946 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); | |
1947 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
73afc70d | 1948 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
b59b7333 | 1949 | int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
6bd1c385 | 1950 | int (*get_temperature)(struct radeon_device *rdev); |
a02fa397 | 1951 | } pm; |
da321c8a AD |
1952 | /* dynamic power management */ |
1953 | struct { | |
1954 | int (*init)(struct radeon_device *rdev); | |
1955 | void (*setup_asic)(struct radeon_device *rdev); | |
1956 | int (*enable)(struct radeon_device *rdev); | |
914a8987 | 1957 | int (*late_enable)(struct radeon_device *rdev); |
da321c8a | 1958 | void (*disable)(struct radeon_device *rdev); |
84dd1928 | 1959 | int (*pre_set_power_state)(struct radeon_device *rdev); |
da321c8a | 1960 | int (*set_power_state)(struct radeon_device *rdev); |
84dd1928 | 1961 | void (*post_set_power_state)(struct radeon_device *rdev); |
da321c8a AD |
1962 | void (*display_configuration_changed)(struct radeon_device *rdev); |
1963 | void (*fini)(struct radeon_device *rdev); | |
1964 | u32 (*get_sclk)(struct radeon_device *rdev, bool low); | |
1965 | u32 (*get_mclk)(struct radeon_device *rdev, bool low); | |
1966 | void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); | |
1316b792 | 1967 | void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); |
70d01a5e | 1968 | int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); |
48783069 | 1969 | bool (*vblank_too_short)(struct radeon_device *rdev); |
9e9d9762 | 1970 | void (*powergate_uvd)(struct radeon_device *rdev, bool gate); |
1c71bda0 | 1971 | void (*enable_bapm)(struct radeon_device *rdev, bool enable); |
da321c8a | 1972 | } dpm; |
6f34be50 | 1973 | /* pageflipping */ |
0f9e006c | 1974 | struct { |
157fa14d CK |
1975 | void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
1976 | bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); | |
0f9e006c | 1977 | } pflip; |
771fe6b9 JG |
1978 | }; |
1979 | ||
21f9a437 JG |
1980 | /* |
1981 | * Asic structures | |
1982 | */ | |
551ebd83 | 1983 | struct r100_asic { |
225758d8 JG |
1984 | const unsigned *reg_safe_bm; |
1985 | unsigned reg_safe_bm_size; | |
1986 | u32 hdp_cntl; | |
551ebd83 DA |
1987 | }; |
1988 | ||
21f9a437 | 1989 | struct r300_asic { |
225758d8 JG |
1990 | const unsigned *reg_safe_bm; |
1991 | unsigned reg_safe_bm_size; | |
1992 | u32 resync_scratch; | |
1993 | u32 hdp_cntl; | |
21f9a437 JG |
1994 | }; |
1995 | ||
1996 | struct r600_asic { | |
225758d8 JG |
1997 | unsigned max_pipes; |
1998 | unsigned max_tile_pipes; | |
1999 | unsigned max_simds; | |
2000 | unsigned max_backends; | |
2001 | unsigned max_gprs; | |
2002 | unsigned max_threads; | |
2003 | unsigned max_stack_entries; | |
2004 | unsigned max_hw_contexts; | |
2005 | unsigned max_gs_threads; | |
2006 | unsigned sx_max_export_size; | |
2007 | unsigned sx_max_export_pos_size; | |
2008 | unsigned sx_max_export_smx_size; | |
2009 | unsigned sq_num_cf_insts; | |
2010 | unsigned tiling_nbanks; | |
2011 | unsigned tiling_npipes; | |
2012 | unsigned tiling_group_size; | |
e7aeeba6 | 2013 | unsigned tile_config; |
e55b9422 | 2014 | unsigned backend_map; |
65fcf668 | 2015 | unsigned active_simds; |
21f9a437 JG |
2016 | }; |
2017 | ||
2018 | struct rv770_asic { | |
225758d8 JG |
2019 | unsigned max_pipes; |
2020 | unsigned max_tile_pipes; | |
2021 | unsigned max_simds; | |
2022 | unsigned max_backends; | |
2023 | unsigned max_gprs; | |
2024 | unsigned max_threads; | |
2025 | unsigned max_stack_entries; | |
2026 | unsigned max_hw_contexts; | |
2027 | unsigned max_gs_threads; | |
2028 | unsigned sx_max_export_size; | |
2029 | unsigned sx_max_export_pos_size; | |
2030 | unsigned sx_max_export_smx_size; | |
2031 | unsigned sq_num_cf_insts; | |
2032 | unsigned sx_num_of_sets; | |
2033 | unsigned sc_prim_fifo_size; | |
2034 | unsigned sc_hiz_tile_fifo_size; | |
2035 | unsigned sc_earlyz_tile_fifo_fize; | |
2036 | unsigned tiling_nbanks; | |
2037 | unsigned tiling_npipes; | |
2038 | unsigned tiling_group_size; | |
e7aeeba6 | 2039 | unsigned tile_config; |
e55b9422 | 2040 | unsigned backend_map; |
65fcf668 | 2041 | unsigned active_simds; |
21f9a437 JG |
2042 | }; |
2043 | ||
32fcdbf4 AD |
2044 | struct evergreen_asic { |
2045 | unsigned num_ses; | |
2046 | unsigned max_pipes; | |
2047 | unsigned max_tile_pipes; | |
2048 | unsigned max_simds; | |
2049 | unsigned max_backends; | |
2050 | unsigned max_gprs; | |
2051 | unsigned max_threads; | |
2052 | unsigned max_stack_entries; | |
2053 | unsigned max_hw_contexts; | |
2054 | unsigned max_gs_threads; | |
2055 | unsigned sx_max_export_size; | |
2056 | unsigned sx_max_export_pos_size; | |
2057 | unsigned sx_max_export_smx_size; | |
2058 | unsigned sq_num_cf_insts; | |
2059 | unsigned sx_num_of_sets; | |
2060 | unsigned sc_prim_fifo_size; | |
2061 | unsigned sc_hiz_tile_fifo_size; | |
2062 | unsigned sc_earlyz_tile_fifo_size; | |
2063 | unsigned tiling_nbanks; | |
2064 | unsigned tiling_npipes; | |
2065 | unsigned tiling_group_size; | |
e7aeeba6 | 2066 | unsigned tile_config; |
e55b9422 | 2067 | unsigned backend_map; |
65fcf668 | 2068 | unsigned active_simds; |
32fcdbf4 AD |
2069 | }; |
2070 | ||
fecf1d07 AD |
2071 | struct cayman_asic { |
2072 | unsigned max_shader_engines; | |
2073 | unsigned max_pipes_per_simd; | |
2074 | unsigned max_tile_pipes; | |
2075 | unsigned max_simds_per_se; | |
2076 | unsigned max_backends_per_se; | |
2077 | unsigned max_texture_channel_caches; | |
2078 | unsigned max_gprs; | |
2079 | unsigned max_threads; | |
2080 | unsigned max_gs_threads; | |
2081 | unsigned max_stack_entries; | |
2082 | unsigned sx_num_of_sets; | |
2083 | unsigned sx_max_export_size; | |
2084 | unsigned sx_max_export_pos_size; | |
2085 | unsigned sx_max_export_smx_size; | |
2086 | unsigned max_hw_contexts; | |
2087 | unsigned sq_num_cf_insts; | |
2088 | unsigned sc_prim_fifo_size; | |
2089 | unsigned sc_hiz_tile_fifo_size; | |
2090 | unsigned sc_earlyz_tile_fifo_size; | |
2091 | ||
2092 | unsigned num_shader_engines; | |
2093 | unsigned num_shader_pipes_per_simd; | |
2094 | unsigned num_tile_pipes; | |
2095 | unsigned num_simds_per_se; | |
2096 | unsigned num_backends_per_se; | |
2097 | unsigned backend_disable_mask_per_asic; | |
2098 | unsigned backend_map; | |
2099 | unsigned num_texture_channel_caches; | |
2100 | unsigned mem_max_burst_length_bytes; | |
2101 | unsigned mem_row_size_in_kb; | |
2102 | unsigned shader_engine_tile_size; | |
2103 | unsigned num_gpus; | |
2104 | unsigned multi_gpu_tile_size; | |
2105 | ||
2106 | unsigned tile_config; | |
65fcf668 | 2107 | unsigned active_simds; |
fecf1d07 AD |
2108 | }; |
2109 | ||
0a96d72b AD |
2110 | struct si_asic { |
2111 | unsigned max_shader_engines; | |
0a96d72b | 2112 | unsigned max_tile_pipes; |
1a8ca750 AD |
2113 | unsigned max_cu_per_sh; |
2114 | unsigned max_sh_per_se; | |
0a96d72b AD |
2115 | unsigned max_backends_per_se; |
2116 | unsigned max_texture_channel_caches; | |
2117 | unsigned max_gprs; | |
2118 | unsigned max_gs_threads; | |
2119 | unsigned max_hw_contexts; | |
2120 | unsigned sc_prim_fifo_size_frontend; | |
2121 | unsigned sc_prim_fifo_size_backend; | |
2122 | unsigned sc_hiz_tile_fifo_size; | |
2123 | unsigned sc_earlyz_tile_fifo_size; | |
2124 | ||
0a96d72b | 2125 | unsigned num_tile_pipes; |
439a1cff | 2126 | unsigned backend_enable_mask; |
0a96d72b AD |
2127 | unsigned backend_disable_mask_per_asic; |
2128 | unsigned backend_map; | |
2129 | unsigned num_texture_channel_caches; | |
2130 | unsigned mem_max_burst_length_bytes; | |
2131 | unsigned mem_row_size_in_kb; | |
2132 | unsigned shader_engine_tile_size; | |
2133 | unsigned num_gpus; | |
2134 | unsigned multi_gpu_tile_size; | |
2135 | ||
2136 | unsigned tile_config; | |
64d7b8be | 2137 | uint32_t tile_mode_array[32]; |
65fcf668 | 2138 | uint32_t active_cus; |
0a96d72b AD |
2139 | }; |
2140 | ||
8cc1a532 AD |
2141 | struct cik_asic { |
2142 | unsigned max_shader_engines; | |
2143 | unsigned max_tile_pipes; | |
2144 | unsigned max_cu_per_sh; | |
2145 | unsigned max_sh_per_se; | |
2146 | unsigned max_backends_per_se; | |
2147 | unsigned max_texture_channel_caches; | |
2148 | unsigned max_gprs; | |
2149 | unsigned max_gs_threads; | |
2150 | unsigned max_hw_contexts; | |
2151 | unsigned sc_prim_fifo_size_frontend; | |
2152 | unsigned sc_prim_fifo_size_backend; | |
2153 | unsigned sc_hiz_tile_fifo_size; | |
2154 | unsigned sc_earlyz_tile_fifo_size; | |
2155 | ||
2156 | unsigned num_tile_pipes; | |
439a1cff | 2157 | unsigned backend_enable_mask; |
8cc1a532 AD |
2158 | unsigned backend_disable_mask_per_asic; |
2159 | unsigned backend_map; | |
2160 | unsigned num_texture_channel_caches; | |
2161 | unsigned mem_max_burst_length_bytes; | |
2162 | unsigned mem_row_size_in_kb; | |
2163 | unsigned shader_engine_tile_size; | |
2164 | unsigned num_gpus; | |
2165 | unsigned multi_gpu_tile_size; | |
2166 | ||
2167 | unsigned tile_config; | |
39aee490 | 2168 | uint32_t tile_mode_array[32]; |
32f79a8a | 2169 | uint32_t macrotile_mode_array[16]; |
65fcf668 | 2170 | uint32_t active_cus; |
8cc1a532 AD |
2171 | }; |
2172 | ||
068a117c JG |
2173 | union radeon_asic_config { |
2174 | struct r300_asic r300; | |
551ebd83 | 2175 | struct r100_asic r100; |
3ce0a23d JG |
2176 | struct r600_asic r600; |
2177 | struct rv770_asic rv770; | |
32fcdbf4 | 2178 | struct evergreen_asic evergreen; |
fecf1d07 | 2179 | struct cayman_asic cayman; |
0a96d72b | 2180 | struct si_asic si; |
8cc1a532 | 2181 | struct cik_asic cik; |
068a117c JG |
2182 | }; |
2183 | ||
0a10c851 DV |
2184 | /* |
2185 | * asic initizalization from radeon_asic.c | |
2186 | */ | |
2187 | void radeon_agp_disable(struct radeon_device *rdev); | |
2188 | int radeon_asic_init(struct radeon_device *rdev); | |
2189 | ||
771fe6b9 JG |
2190 | |
2191 | /* | |
2192 | * IOCTL. | |
2193 | */ | |
2194 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
2195 | struct drm_file *filp); | |
2196 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
2197 | struct drm_file *filp); | |
f72a113a CK |
2198 | int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, |
2199 | struct drm_file *filp); | |
771fe6b9 JG |
2200 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, |
2201 | struct drm_file *file_priv); | |
2202 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
2203 | struct drm_file *file_priv); | |
2204 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2205 | struct drm_file *file_priv); | |
2206 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2207 | struct drm_file *file_priv); | |
2208 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
2209 | struct drm_file *filp); | |
2210 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2211 | struct drm_file *filp); | |
2212 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
2213 | struct drm_file *filp); | |
2214 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
2215 | struct drm_file *filp); | |
721604a1 JG |
2216 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
2217 | struct drm_file *filp); | |
bda72d58 MO |
2218 | int radeon_gem_op_ioctl(struct drm_device *dev, void *data, |
2219 | struct drm_file *filp); | |
771fe6b9 | 2220 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
e024e110 DA |
2221 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
2222 | struct drm_file *filp); | |
2223 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
2224 | struct drm_file *filp); | |
771fe6b9 | 2225 | |
16cdf04d AD |
2226 | /* VRAM scratch page for HDP bug, default vram page */ |
2227 | struct r600_vram_scratch { | |
87cbf8f2 AD |
2228 | struct radeon_bo *robj; |
2229 | volatile uint32_t *ptr; | |
16cdf04d | 2230 | u64 gpu_addr; |
87cbf8f2 | 2231 | }; |
771fe6b9 | 2232 | |
fd64ca8a LT |
2233 | /* |
2234 | * ACPI | |
2235 | */ | |
2236 | struct radeon_atif_notification_cfg { | |
2237 | bool enabled; | |
2238 | int command_code; | |
2239 | }; | |
2240 | ||
2241 | struct radeon_atif_notifications { | |
2242 | bool display_switch; | |
2243 | bool expansion_mode_change; | |
2244 | bool thermal_state; | |
2245 | bool forced_power_state; | |
2246 | bool system_power_state; | |
2247 | bool display_conf_change; | |
2248 | bool px_gfx_switch; | |
2249 | bool brightness_change; | |
2250 | bool dgpu_display_event; | |
2251 | }; | |
2252 | ||
2253 | struct radeon_atif_functions { | |
2254 | bool system_params; | |
2255 | bool sbios_requests; | |
2256 | bool select_active_disp; | |
2257 | bool lid_state; | |
2258 | bool get_tv_standard; | |
2259 | bool set_tv_standard; | |
2260 | bool get_panel_expansion_mode; | |
2261 | bool set_panel_expansion_mode; | |
2262 | bool temperature_change; | |
2263 | bool graphics_device_types; | |
2264 | }; | |
2265 | ||
2266 | struct radeon_atif { | |
2267 | struct radeon_atif_notifications notifications; | |
2268 | struct radeon_atif_functions functions; | |
2269 | struct radeon_atif_notification_cfg notification_cfg; | |
37e9b6a6 | 2270 | struct radeon_encoder *encoder_for_bl; |
fd64ca8a | 2271 | }; |
7a1619b9 | 2272 | |
e3a15920 AD |
2273 | struct radeon_atcs_functions { |
2274 | bool get_ext_state; | |
2275 | bool pcie_perf_req; | |
2276 | bool pcie_dev_rdy; | |
2277 | bool pcie_bus_width; | |
2278 | }; | |
2279 | ||
2280 | struct radeon_atcs { | |
2281 | struct radeon_atcs_functions functions; | |
2282 | }; | |
2283 | ||
771fe6b9 JG |
2284 | /* |
2285 | * Core structure, functions and helpers. | |
2286 | */ | |
2287 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
2288 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
2289 | ||
2290 | struct radeon_device { | |
9f022ddf | 2291 | struct device *dev; |
771fe6b9 JG |
2292 | struct drm_device *ddev; |
2293 | struct pci_dev *pdev; | |
dee53e7f | 2294 | struct rw_semaphore exclusive_lock; |
771fe6b9 | 2295 | /* ASIC */ |
068a117c | 2296 | union radeon_asic_config config; |
771fe6b9 JG |
2297 | enum radeon_family family; |
2298 | unsigned long flags; | |
2299 | int usec_timeout; | |
2300 | enum radeon_pll_errata pll_errata; | |
2301 | int num_gb_pipes; | |
f779b3e5 | 2302 | int num_z_pipes; |
771fe6b9 JG |
2303 | int disp_priority; |
2304 | /* BIOS */ | |
2305 | uint8_t *bios; | |
2306 | bool is_atom_bios; | |
2307 | uint16_t bios_header_start; | |
4c788679 | 2308 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 2309 | /* Register mmio */ |
4c9bc75c DA |
2310 | resource_size_t rmmio_base; |
2311 | resource_size_t rmmio_size; | |
2c385151 DV |
2312 | /* protects concurrent MM_INDEX/DATA based register access */ |
2313 | spinlock_t mmio_idx_lock; | |
fe78118c AD |
2314 | /* protects concurrent SMC based register access */ |
2315 | spinlock_t smc_idx_lock; | |
0a5b7b0b AD |
2316 | /* protects concurrent PLL register access */ |
2317 | spinlock_t pll_idx_lock; | |
2318 | /* protects concurrent MC register access */ | |
2319 | spinlock_t mc_idx_lock; | |
2320 | /* protects concurrent PCIE register access */ | |
2321 | spinlock_t pcie_idx_lock; | |
2322 | /* protects concurrent PCIE_PORT register access */ | |
2323 | spinlock_t pciep_idx_lock; | |
2324 | /* protects concurrent PIF register access */ | |
2325 | spinlock_t pif_idx_lock; | |
2326 | /* protects concurrent CG register access */ | |
2327 | spinlock_t cg_idx_lock; | |
2328 | /* protects concurrent UVD register access */ | |
2329 | spinlock_t uvd_idx_lock; | |
2330 | /* protects concurrent RCU register access */ | |
2331 | spinlock_t rcu_idx_lock; | |
2332 | /* protects concurrent DIDT register access */ | |
2333 | spinlock_t didt_idx_lock; | |
2334 | /* protects concurrent ENDPOINT (audio) register access */ | |
2335 | spinlock_t end_idx_lock; | |
a0533fbf | 2336 | void __iomem *rmmio; |
771fe6b9 JG |
2337 | radeon_rreg_t mc_rreg; |
2338 | radeon_wreg_t mc_wreg; | |
2339 | radeon_rreg_t pll_rreg; | |
2340 | radeon_wreg_t pll_wreg; | |
de1b2898 | 2341 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
2342 | radeon_rreg_t pciep_rreg; |
2343 | radeon_wreg_t pciep_wreg; | |
351a52a2 AD |
2344 | /* io port */ |
2345 | void __iomem *rio_mem; | |
2346 | resource_size_t rio_mem_size; | |
771fe6b9 JG |
2347 | struct radeon_clock clock; |
2348 | struct radeon_mc mc; | |
2349 | struct radeon_gart gart; | |
2350 | struct radeon_mode_info mode_info; | |
2351 | struct radeon_scratch scratch; | |
75efdee1 | 2352 | struct radeon_doorbell doorbell; |
771fe6b9 | 2353 | struct radeon_mman mman; |
7465280c | 2354 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
0085c950 | 2355 | wait_queue_head_t fence_queue; |
954605ca | 2356 | unsigned fence_context; |
d6999bc7 | 2357 | struct mutex ring_lock; |
e32eb50d | 2358 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
c507f7ef JG |
2359 | bool ib_pool_ready; |
2360 | struct radeon_sa_manager ring_tmp_bo; | |
771fe6b9 JG |
2361 | struct radeon_irq irq; |
2362 | struct radeon_asic *asic; | |
2363 | struct radeon_gem gem; | |
c93bb85b | 2364 | struct radeon_pm pm; |
f2ba57b5 | 2365 | struct radeon_uvd uvd; |
d93f7937 | 2366 | struct radeon_vce vce; |
f657c2a7 | 2367 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 | 2368 | struct radeon_wb wb; |
3ce0a23d | 2369 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
2370 | bool shutdown; |
2371 | bool suspend; | |
ad49f501 | 2372 | bool need_dma32; |
733289c2 | 2373 | bool accel_working; |
a0a53aa8 | 2374 | bool fastfb_working; /* IGP feature*/ |
9bb39ff4 | 2375 | bool needs_reset, in_reset; |
e024e110 | 2376 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
2377 | const struct firmware *me_fw; /* all family ME firmware */ |
2378 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 2379 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
0af62b01 | 2380 | const struct firmware *mc_fw; /* NI MC firmware */ |
0f0de06c | 2381 | const struct firmware *ce_fw; /* SI CE firmware */ |
02c81327 | 2382 | const struct firmware *mec_fw; /* CIK MEC firmware */ |
f2c6b0f4 | 2383 | const struct firmware *mec2_fw; /* KV MEC2 firmware */ |
21a93e13 | 2384 | const struct firmware *sdma_fw; /* CIK SDMA firmware */ |
66229b20 | 2385 | const struct firmware *smc_fw; /* SMC firmware */ |
4ad9c1c7 | 2386 | const struct firmware *uvd_fw; /* UVD firmware */ |
d93f7937 | 2387 | const struct firmware *vce_fw; /* VCE firmware */ |
629bd33c | 2388 | bool new_fw; |
16cdf04d | 2389 | struct r600_vram_scratch vram_scratch; |
3e5cb98d | 2390 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 2391 | struct r600_ih ih; /* r6/700 interrupt ring */ |
2948f5e6 | 2392 | struct radeon_rlc rlc; |
963e81f9 | 2393 | struct radeon_mec mec; |
d4877cf2 | 2394 | struct work_struct hotplug_work; |
f122c610 | 2395 | struct work_struct audio_work; |
18917b60 | 2396 | int num_crtc; /* number of crtcs */ |
40bacf16 | 2397 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
948bee3f | 2398 | bool has_uvd; |
b530602f | 2399 | struct r600_audio audio; /* audio stuff */ |
ce8f5370 | 2400 | struct notifier_block acpi_nb; |
9eba4a93 | 2401 | /* only one userspace can use Hyperz features or CMASK at a time */ |
ab9e1f59 | 2402 | struct drm_file *hyperz_filp; |
9eba4a93 | 2403 | struct drm_file *cmask_filp; |
f376b94f AD |
2404 | /* i2c buses */ |
2405 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; | |
4d8bf9ae CK |
2406 | /* debugfs */ |
2407 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; | |
2408 | unsigned debugfs_count; | |
721604a1 JG |
2409 | /* virtual memory */ |
2410 | struct radeon_vm_manager vm_manager; | |
6759a0a7 | 2411 | struct mutex gpu_clock_mutex; |
67e8e3f9 MO |
2412 | /* memory stats */ |
2413 | atomic64_t vram_usage; | |
2414 | atomic64_t gtt_usage; | |
2415 | atomic64_t num_bytes_moved; | |
fd64ca8a LT |
2416 | /* ACPI interface */ |
2417 | struct radeon_atif atif; | |
e3a15920 | 2418 | struct radeon_atcs atcs; |
f61d5b46 AD |
2419 | /* srbm instance registers */ |
2420 | struct mutex srbm_mutex; | |
1c0a4625 OG |
2421 | /* GRBM index mutex. Protects concurrents access to GRBM index */ |
2422 | struct mutex grbm_idx_mutex; | |
64d8a728 AD |
2423 | /* clock, powergating flags */ |
2424 | u32 cg_flags; | |
2425 | u32 pg_flags; | |
10ebc0bc DA |
2426 | |
2427 | struct dev_pm_domain vga_pm_domain; | |
2428 | bool have_disp_power_ref; | |
4807c5a8 | 2429 | u32 px_quirk_flags; |
71ecc97e AD |
2430 | |
2431 | /* tracking pinned memory */ | |
2432 | u64 vram_pin_size; | |
2433 | u64 gart_pin_size; | |
341cb9e4 | 2434 | |
e28740ec OG |
2435 | /* amdkfd interface */ |
2436 | struct kfd_dev *kfd; | |
2437 | struct radeon_sa_manager kfd_bo; | |
2438 | ||
341cb9e4 CK |
2439 | struct mutex mn_lock; |
2440 | DECLARE_HASHTABLE(mn_hash, 7); | |
771fe6b9 JG |
2441 | }; |
2442 | ||
90c4cde9 | 2443 | bool radeon_is_px(struct drm_device *dev); |
771fe6b9 JG |
2444 | int radeon_device_init(struct radeon_device *rdev, |
2445 | struct drm_device *ddev, | |
2446 | struct pci_dev *pdev, | |
2447 | uint32_t flags); | |
2448 | void radeon_device_fini(struct radeon_device *rdev); | |
2449 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
2450 | ||
59bc1d89 LK |
2451 | #define RADEON_MIN_MMIO_SIZE 0x10000 |
2452 | ||
2453 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, | |
2454 | bool always_indirect) | |
2455 | { | |
2456 | /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ | |
2457 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) | |
2458 | return readl(((void __iomem *)rdev->rmmio) + reg); | |
2459 | else { | |
2460 | unsigned long flags; | |
2461 | uint32_t ret; | |
2462 | ||
2463 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
2464 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
2465 | ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
2466 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); | |
2467 | ||
2468 | return ret; | |
2469 | } | |
2470 | } | |
2471 | ||
2472 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, | |
2473 | bool always_indirect) | |
2474 | { | |
2475 | if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) | |
2476 | writel(v, ((void __iomem *)rdev->rmmio) + reg); | |
2477 | else { | |
2478 | unsigned long flags; | |
2479 | ||
2480 | spin_lock_irqsave(&rdev->mmio_idx_lock, flags); | |
2481 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
2482 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
2483 | spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); | |
2484 | } | |
2485 | } | |
2486 | ||
6fcbef7a AK |
2487 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
2488 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
351a52a2 | 2489 | |
d5754ab8 AL |
2490 | u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); |
2491 | void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); | |
75efdee1 | 2492 | |
4c788679 JG |
2493 | /* |
2494 | * Cast helper | |
2495 | */ | |
954605ca ML |
2496 | extern const struct fence_ops radeon_fence_ops; |
2497 | ||
2498 | static inline struct radeon_fence *to_radeon_fence(struct fence *f) | |
2499 | { | |
2500 | struct radeon_fence *__f = container_of(f, struct radeon_fence, base); | |
2501 | ||
2502 | if (__f->base.ops == &radeon_fence_ops) | |
2503 | return __f; | |
2504 | ||
2505 | return NULL; | |
2506 | } | |
771fe6b9 JG |
2507 | |
2508 | /* | |
2509 | * Registers read & write functions. | |
2510 | */ | |
a0533fbf BH |
2511 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
2512 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) | |
2513 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) | |
2514 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) | |
2ef9bdfe DV |
2515 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
2516 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) | |
2517 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) | |
2518 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) | |
2519 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) | |
771fe6b9 JG |
2520 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2521 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
2522 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
2523 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
2524 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
2525 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
2526 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
2527 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
492d2b61 AD |
2528 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
2529 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
1d5d0c34 AD |
2530 | #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) |
2531 | #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) | |
ff82bbc4 AD |
2532 | #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) |
2533 | #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) | |
46f9564a AD |
2534 | #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) |
2535 | #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) | |
792edd69 AD |
2536 | #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) |
2537 | #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) | |
2538 | #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) | |
2539 | #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) | |
93656cdd AD |
2540 | #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) |
2541 | #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) | |
1d58234d AD |
2542 | #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) |
2543 | #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
2544 | #define WREG32_P(reg, val, mask) \ |
2545 | do { \ | |
2546 | uint32_t tmp_ = RREG32(reg); \ | |
2547 | tmp_ &= (mask); \ | |
2548 | tmp_ |= ((val) & ~(mask)); \ | |
2549 | WREG32(reg, tmp_); \ | |
2550 | } while (0) | |
d5169fc4 | 2551 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
d43a93c8 | 2552 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
771fe6b9 JG |
2553 | #define WREG32_PLL_P(reg, val, mask) \ |
2554 | do { \ | |
2555 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
2556 | tmp_ &= (mask); \ | |
2557 | tmp_ |= ((val) & ~(mask)); \ | |
2558 | WREG32_PLL(reg, tmp_); \ | |
2559 | } while (0) | |
2ef9bdfe | 2560 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
351a52a2 AD |
2561 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
2562 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) | |
771fe6b9 | 2563 | |
d5754ab8 AL |
2564 | #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) |
2565 | #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) | |
75efdee1 | 2566 | |
de1b2898 DA |
2567 | /* |
2568 | * Indirect registers accessor | |
2569 | */ | |
2570 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
2571 | { | |
0a5b7b0b | 2572 | unsigned long flags; |
de1b2898 DA |
2573 | uint32_t r; |
2574 | ||
0a5b7b0b | 2575 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); |
de1b2898 DA |
2576 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
2577 | r = RREG32(RADEON_PCIE_DATA); | |
0a5b7b0b | 2578 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
de1b2898 DA |
2579 | return r; |
2580 | } | |
2581 | ||
2582 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
2583 | { | |
0a5b7b0b AD |
2584 | unsigned long flags; |
2585 | ||
2586 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); | |
de1b2898 DA |
2587 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
2588 | WREG32(RADEON_PCIE_DATA, (v)); | |
0a5b7b0b | 2589 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
de1b2898 DA |
2590 | } |
2591 | ||
1d5d0c34 AD |
2592 | static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) |
2593 | { | |
fe78118c | 2594 | unsigned long flags; |
1d5d0c34 AD |
2595 | u32 r; |
2596 | ||
fe78118c | 2597 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); |
1d5d0c34 AD |
2598 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
2599 | r = RREG32(TN_SMC_IND_DATA_0); | |
fe78118c | 2600 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
1d5d0c34 AD |
2601 | return r; |
2602 | } | |
2603 | ||
2604 | static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2605 | { | |
fe78118c AD |
2606 | unsigned long flags; |
2607 | ||
2608 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); | |
1d5d0c34 AD |
2609 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
2610 | WREG32(TN_SMC_IND_DATA_0, (v)); | |
fe78118c | 2611 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
1d5d0c34 AD |
2612 | } |
2613 | ||
ff82bbc4 AD |
2614 | static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) |
2615 | { | |
0a5b7b0b | 2616 | unsigned long flags; |
ff82bbc4 AD |
2617 | u32 r; |
2618 | ||
0a5b7b0b | 2619 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); |
ff82bbc4 AD |
2620 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
2621 | r = RREG32(R600_RCU_DATA); | |
0a5b7b0b | 2622 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
ff82bbc4 AD |
2623 | return r; |
2624 | } | |
2625 | ||
2626 | static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2627 | { | |
0a5b7b0b AD |
2628 | unsigned long flags; |
2629 | ||
2630 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); | |
ff82bbc4 AD |
2631 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
2632 | WREG32(R600_RCU_DATA, (v)); | |
0a5b7b0b | 2633 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
ff82bbc4 AD |
2634 | } |
2635 | ||
46f9564a AD |
2636 | static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) |
2637 | { | |
0a5b7b0b | 2638 | unsigned long flags; |
46f9564a AD |
2639 | u32 r; |
2640 | ||
0a5b7b0b | 2641 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
46f9564a AD |
2642 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
2643 | r = RREG32(EVERGREEN_CG_IND_DATA); | |
0a5b7b0b | 2644 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
46f9564a AD |
2645 | return r; |
2646 | } | |
2647 | ||
2648 | static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2649 | { | |
0a5b7b0b AD |
2650 | unsigned long flags; |
2651 | ||
2652 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); | |
46f9564a AD |
2653 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
2654 | WREG32(EVERGREEN_CG_IND_DATA, (v)); | |
0a5b7b0b | 2655 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
46f9564a AD |
2656 | } |
2657 | ||
792edd69 AD |
2658 | static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) |
2659 | { | |
0a5b7b0b | 2660 | unsigned long flags; |
792edd69 AD |
2661 | u32 r; |
2662 | ||
0a5b7b0b | 2663 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2664 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
2665 | r = RREG32(EVERGREEN_PIF_PHY0_DATA); | |
0a5b7b0b | 2666 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2667 | return r; |
2668 | } | |
2669 | ||
2670 | static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2671 | { | |
0a5b7b0b AD |
2672 | unsigned long flags; |
2673 | ||
2674 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); | |
792edd69 AD |
2675 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
2676 | WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); | |
0a5b7b0b | 2677 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2678 | } |
2679 | ||
2680 | static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) | |
2681 | { | |
0a5b7b0b | 2682 | unsigned long flags; |
792edd69 AD |
2683 | u32 r; |
2684 | ||
0a5b7b0b | 2685 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2686 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
2687 | r = RREG32(EVERGREEN_PIF_PHY1_DATA); | |
0a5b7b0b | 2688 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2689 | return r; |
2690 | } | |
2691 | ||
2692 | static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2693 | { | |
0a5b7b0b AD |
2694 | unsigned long flags; |
2695 | ||
2696 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); | |
792edd69 AD |
2697 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
2698 | WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); | |
0a5b7b0b | 2699 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2700 | } |
2701 | ||
93656cdd AD |
2702 | static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) |
2703 | { | |
0a5b7b0b | 2704 | unsigned long flags; |
93656cdd AD |
2705 | u32 r; |
2706 | ||
0a5b7b0b | 2707 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); |
93656cdd AD |
2708 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
2709 | r = RREG32(R600_UVD_CTX_DATA); | |
0a5b7b0b | 2710 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
93656cdd AD |
2711 | return r; |
2712 | } | |
2713 | ||
2714 | static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2715 | { | |
0a5b7b0b AD |
2716 | unsigned long flags; |
2717 | ||
2718 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); | |
93656cdd AD |
2719 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
2720 | WREG32(R600_UVD_CTX_DATA, (v)); | |
0a5b7b0b | 2721 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
93656cdd AD |
2722 | } |
2723 | ||
1d58234d AD |
2724 | |
2725 | static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) | |
2726 | { | |
0a5b7b0b | 2727 | unsigned long flags; |
1d58234d AD |
2728 | u32 r; |
2729 | ||
0a5b7b0b | 2730 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
1d58234d AD |
2731 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
2732 | r = RREG32(CIK_DIDT_IND_DATA); | |
0a5b7b0b | 2733 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
1d58234d AD |
2734 | return r; |
2735 | } | |
2736 | ||
2737 | static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2738 | { | |
0a5b7b0b AD |
2739 | unsigned long flags; |
2740 | ||
2741 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); | |
1d58234d AD |
2742 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
2743 | WREG32(CIK_DIDT_IND_DATA, (v)); | |
0a5b7b0b | 2744 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
1d58234d AD |
2745 | } |
2746 | ||
771fe6b9 JG |
2747 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
2748 | ||
2749 | ||
2750 | /* | |
2751 | * ASICs helpers. | |
2752 | */ | |
b995e433 DA |
2753 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
2754 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
2755 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
2756 | (rdev->family == CHIP_RV200) || \ | |
2757 | (rdev->family == CHIP_RS100) || \ | |
2758 | (rdev->family == CHIP_RS200) || \ | |
2759 | (rdev->family == CHIP_RV250) || \ | |
2760 | (rdev->family == CHIP_RV280) || \ | |
2761 | (rdev->family == CHIP_RS300)) | |
2762 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
2763 | (rdev->family == CHIP_RV350) || \ | |
2764 | (rdev->family == CHIP_R350) || \ | |
2765 | (rdev->family == CHIP_RV380) || \ | |
2766 | (rdev->family == CHIP_R420) || \ | |
2767 | (rdev->family == CHIP_R423) || \ | |
2768 | (rdev->family == CHIP_RV410) || \ | |
2769 | (rdev->family == CHIP_RS400) || \ | |
2770 | (rdev->family == CHIP_RS480)) | |
3313e3d4 AD |
2771 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
2772 | (rdev->ddev->pdev->device == 0x9443) || \ | |
2773 | (rdev->ddev->pdev->device == 0x944B) || \ | |
2774 | (rdev->ddev->pdev->device == 0x9506) || \ | |
2775 | (rdev->ddev->pdev->device == 0x9509) || \ | |
2776 | (rdev->ddev->pdev->device == 0x950F) || \ | |
2777 | (rdev->ddev->pdev->device == 0x689C) || \ | |
2778 | (rdev->ddev->pdev->device == 0x689D)) | |
771fe6b9 | 2779 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
99999aaa AD |
2780 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
2781 | (rdev->family == CHIP_RS690) || \ | |
2782 | (rdev->family == CHIP_RS740) || \ | |
2783 | (rdev->family >= CHIP_R600)) | |
771fe6b9 JG |
2784 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
2785 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 2786 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
633b9164 AD |
2787 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
2788 | (rdev->flags & RADEON_IS_IGP)) | |
1fe18305 | 2789 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
8848f759 AD |
2790 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
2791 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ | |
2792 | (rdev->flags & RADEON_IS_IGP)) | |
624d3524 | 2793 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
b5d9d726 | 2794 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
e282917c | 2795 | #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) |
be0949f5 AD |
2796 | #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) |
2797 | #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) | |
89d2618d AD |
2798 | #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ |
2799 | (rdev->family == CHIP_MULLINS)) | |
771fe6b9 | 2800 | |
dc50ba7f AD |
2801 | #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ |
2802 | (rdev->ddev->pdev->device == 0x6850) || \ | |
2803 | (rdev->ddev->pdev->device == 0x6858) || \ | |
2804 | (rdev->ddev->pdev->device == 0x6859) || \ | |
2805 | (rdev->ddev->pdev->device == 0x6840) || \ | |
2806 | (rdev->ddev->pdev->device == 0x6841) || \ | |
2807 | (rdev->ddev->pdev->device == 0x6842) || \ | |
2808 | (rdev->ddev->pdev->device == 0x6843)) | |
2809 | ||
771fe6b9 JG |
2810 | /* |
2811 | * BIOS helpers. | |
2812 | */ | |
2813 | #define RBIOS8(i) (rdev->bios[i]) | |
2814 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
2815 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
2816 | ||
2817 | int radeon_combios_init(struct radeon_device *rdev); | |
2818 | void radeon_combios_fini(struct radeon_device *rdev); | |
2819 | int radeon_atombios_init(struct radeon_device *rdev); | |
2820 | void radeon_atombios_fini(struct radeon_device *rdev); | |
2821 | ||
2822 | ||
2823 | /* | |
2824 | * RING helpers. | |
2825 | */ | |
edf0ac7c DH |
2826 | |
2827 | /** | |
2828 | * radeon_ring_write - write a value to the ring | |
2829 | * | |
2830 | * @ring: radeon_ring structure holding ring information | |
2831 | * @v: dword (dw) value to write | |
2832 | * | |
2833 | * Write a value to the requested ring buffer (all asics). | |
2834 | */ | |
e32eb50d | 2835 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
771fe6b9 | 2836 | { |
edf0ac7c DH |
2837 | if (ring->count_dw <= 0) |
2838 | DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); | |
2839 | ||
e32eb50d CK |
2840 | ring->ring[ring->wptr++] = v; |
2841 | ring->wptr &= ring->ptr_mask; | |
2842 | ring->count_dw--; | |
2843 | ring->ring_free_dw--; | |
771fe6b9 | 2844 | } |
771fe6b9 JG |
2845 | |
2846 | /* | |
2847 | * ASICs macro. | |
2848 | */ | |
068a117c | 2849 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
2850 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
2851 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
2852 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
76a0df85 | 2853 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) |
28d52043 | 2854 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
a2d07b74 | 2855 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
c5b3b850 | 2856 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
77497f27 | 2857 | #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f)) |
05b07147 CK |
2858 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
2859 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) | |
03f62abd CK |
2860 | #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) |
2861 | #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) | |
2862 | #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) | |
2863 | #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) | |
76a0df85 CK |
2864 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) |
2865 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) | |
2866 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) | |
2867 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) | |
2868 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) | |
2869 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) | |
faffaf62 | 2870 | #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) |
76a0df85 CK |
2871 | #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) |
2872 | #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) | |
2873 | #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) | |
b35ea4ab AD |
2874 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
2875 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) | |
c79a49ca | 2876 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
37e9b6a6 | 2877 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
6d92f81d | 2878 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
a973bea1 AD |
2879 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
2880 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) | |
76a0df85 CK |
2881 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) |
2882 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) | |
57d20a43 CK |
2883 | #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) |
2884 | #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) | |
2885 | #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) | |
27cd7769 AD |
2886 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
2887 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index | |
2888 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index | |
798bcf73 AD |
2889 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
2890 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) | |
2891 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) | |
2892 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) | |
2893 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) | |
2894 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) | |
2895 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) | |
73afc70d | 2896 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
b59b7333 | 2897 | #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) |
6bd1c385 | 2898 | #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) |
9e6f3d02 AD |
2899 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
2900 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) | |
c79a49ca | 2901 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
901ea57d AD |
2902 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
2903 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) | |
2904 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) | |
2905 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) | |
def9ba9c | 2906 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
a02fa397 AD |
2907 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
2908 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) | |
2909 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) | |
2910 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) | |
2911 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) | |
69b62ad8 | 2912 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
157fa14d | 2913 | #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) |
69b62ad8 AD |
2914 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
2915 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) | |
454d2e2a | 2916 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
d0418894 | 2917 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
da321c8a AD |
2918 | #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) |
2919 | #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) | |
2920 | #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) | |
914a8987 | 2921 | #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) |
da321c8a | 2922 | #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) |
84dd1928 | 2923 | #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) |
da321c8a | 2924 | #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) |
84dd1928 | 2925 | #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) |
da321c8a AD |
2926 | #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) |
2927 | #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) | |
2928 | #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) | |
2929 | #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) | |
2930 | #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) | |
1316b792 | 2931 | #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) |
70d01a5e | 2932 | #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) |
48783069 | 2933 | #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) |
9e9d9762 | 2934 | #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) |
1c71bda0 | 2935 | #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) |
771fe6b9 | 2936 | |
6cf8a3f5 | 2937 | /* Common functions */ |
700a0cc0 | 2938 | /* AGP */ |
90aca4d2 | 2939 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
1a0041b8 | 2940 | extern void radeon_pci_config_reset(struct radeon_device *rdev); |
410a3418 | 2941 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
700a0cc0 | 2942 | extern void radeon_agp_disable(struct radeon_device *rdev); |
21f9a437 JG |
2943 | extern int radeon_modeset_init(struct radeon_device *rdev); |
2944 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 2945 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 2946 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 2947 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 2948 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 | 2949 | extern void radeon_scratch_init(struct radeon_device *rdev); |
724c80e1 AD |
2950 | extern void radeon_wb_fini(struct radeon_device *rdev); |
2951 | extern int radeon_wb_init(struct radeon_device *rdev); | |
2952 | extern void radeon_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
2953 | extern void radeon_surface_init(struct radeon_device *rdev); |
2954 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 2955 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 2956 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 2957 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 2958 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
f72a113a CK |
2959 | extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, |
2960 | uint32_t flags); | |
2961 | extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); | |
2962 | extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); | |
d594e46a JG |
2963 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
2964 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
10ebc0bc DA |
2965 | extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); |
2966 | extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); | |
53595338 | 2967 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
2e1b65f9 AD |
2968 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
2969 | const u32 *registers, | |
2970 | const u32 array_size); | |
6cf8a3f5 | 2971 | |
721604a1 JG |
2972 | /* |
2973 | * vm | |
2974 | */ | |
2975 | int radeon_vm_manager_init(struct radeon_device *rdev); | |
2976 | void radeon_vm_manager_fini(struct radeon_device *rdev); | |
6d2f2944 | 2977 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
721604a1 | 2978 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
df0af440 CK |
2979 | struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, |
2980 | struct radeon_vm *vm, | |
2981 | struct list_head *head); | |
ee60e29f CK |
2982 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
2983 | struct radeon_vm *vm, int ring); | |
fa688343 CK |
2984 | void radeon_vm_flush(struct radeon_device *rdev, |
2985 | struct radeon_vm *vm, | |
ad1a58a4 | 2986 | int ring, struct radeon_fence *fence); |
ee60e29f CK |
2987 | void radeon_vm_fence(struct radeon_device *rdev, |
2988 | struct radeon_vm *vm, | |
2989 | struct radeon_fence *fence); | |
dce34bfd | 2990 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
6d2f2944 CK |
2991 | int radeon_vm_update_page_directory(struct radeon_device *rdev, |
2992 | struct radeon_vm *vm); | |
036bf46a CK |
2993 | int radeon_vm_clear_freed(struct radeon_device *rdev, |
2994 | struct radeon_vm *vm); | |
e31ad969 CK |
2995 | int radeon_vm_clear_invalids(struct radeon_device *rdev, |
2996 | struct radeon_vm *vm); | |
9c57a6bd | 2997 | int radeon_vm_bo_update(struct radeon_device *rdev, |
036bf46a | 2998 | struct radeon_bo_va *bo_va, |
9c57a6bd | 2999 | struct ttm_mem_reg *mem); |
721604a1 JG |
3000 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
3001 | struct radeon_bo *bo); | |
421ca7ab CK |
3002 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
3003 | struct radeon_bo *bo); | |
e971bd5e CK |
3004 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
3005 | struct radeon_vm *vm, | |
3006 | struct radeon_bo *bo); | |
3007 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, | |
3008 | struct radeon_bo_va *bo_va, | |
3009 | uint64_t offset, | |
3010 | uint32_t flags); | |
036bf46a CK |
3011 | void radeon_vm_bo_rmv(struct radeon_device *rdev, |
3012 | struct radeon_bo_va *bo_va); | |
721604a1 | 3013 | |
f122c610 AD |
3014 | /* audio */ |
3015 | void r600_audio_update_hdmi(struct work_struct *work); | |
b530602f AD |
3016 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); |
3017 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); | |
832eafaf AD |
3018 | void r600_audio_enable(struct radeon_device *rdev, |
3019 | struct r600_audio_pin *pin, | |
d3d8c141 | 3020 | u8 enable_mask); |
832eafaf AD |
3021 | void dce6_audio_enable(struct radeon_device *rdev, |
3022 | struct r600_audio_pin *pin, | |
d3d8c141 | 3023 | u8 enable_mask); |
721604a1 | 3024 | |
16cdf04d AD |
3025 | /* |
3026 | * R600 vram scratch functions | |
3027 | */ | |
3028 | int r600_vram_scratch_init(struct radeon_device *rdev); | |
3029 | void r600_vram_scratch_fini(struct radeon_device *rdev); | |
3030 | ||
285484e2 JG |
3031 | /* |
3032 | * r600 cs checking helper | |
3033 | */ | |
3034 | unsigned r600_mip_minify(unsigned size, unsigned level); | |
3035 | bool r600_fmt_is_valid_color(u32 format); | |
3036 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); | |
3037 | int r600_fmt_get_blocksize(u32 format); | |
3038 | int r600_fmt_get_nblocksx(u32 format, u32 w); | |
3039 | int r600_fmt_get_nblocksy(u32 format, u32 h); | |
3040 | ||
3574dda4 DV |
3041 | /* |
3042 | * r600 functions used by radeon_encoder.c | |
3043 | */ | |
1b688d08 RM |
3044 | struct radeon_hdmi_acr { |
3045 | u32 clock; | |
3046 | ||
3047 | int n_32khz; | |
3048 | int cts_32khz; | |
3049 | ||
3050 | int n_44_1khz; | |
3051 | int cts_44_1khz; | |
3052 | ||
3053 | int n_48khz; | |
3054 | int cts_48khz; | |
3055 | ||
3056 | }; | |
3057 | ||
e55d3e6c RM |
3058 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
3059 | ||
416a2bd2 AD |
3060 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
3061 | u32 tiling_pipe_num, | |
3062 | u32 max_rb_num, | |
3063 | u32 total_max_rb_num, | |
3064 | u32 enabled_rb_mask); | |
fe251e2f | 3065 | |
e55d3e6c RM |
3066 | /* |
3067 | * evergreen functions used by radeon_encoder.c | |
3068 | */ | |
3069 | ||
0af62b01 | 3070 | extern int ni_init_microcode(struct radeon_device *rdev); |
755d819e | 3071 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
0af62b01 | 3072 | |
c4917074 AD |
3073 | /* radeon_acpi.c */ |
3074 | #if defined(CONFIG_ACPI) | |
3075 | extern int radeon_acpi_init(struct radeon_device *rdev); | |
3076 | extern void radeon_acpi_fini(struct radeon_device *rdev); | |
dc50ba7f AD |
3077 | extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); |
3078 | extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, | |
e37e6a0e | 3079 | u8 perf_req, bool advertise); |
dc50ba7f | 3080 | extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); |
c4917074 AD |
3081 | #else |
3082 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } | |
3083 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } | |
3084 | #endif | |
d7a2952f | 3085 | |
c38f34b5 IH |
3086 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
3087 | struct radeon_cs_packet *pkt, | |
3088 | unsigned idx); | |
9ffb7a6d | 3089 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
c3ad63af IH |
3090 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
3091 | struct radeon_cs_packet *pkt); | |
e9716993 IH |
3092 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
3093 | struct radeon_cs_reloc **cs_reloc, | |
3094 | int nomm); | |
40592a17 IH |
3095 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
3096 | uint32_t *vline_start_end, | |
3097 | uint32_t *vline_status); | |
c38f34b5 | 3098 | |
4c788679 JG |
3099 | #include "radeon_object.h" |
3100 | ||
771fe6b9 | 3101 | #endif |