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drm/radeon/kms: make sure mc is initialized before mapping blit bo
[linux-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
771fe6b9
JG		 63#include <asm/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72
c2142715 73#include "radeon_family.h"
771fe6b9
JG		 74#include "radeon_mode.h"
75#include "radeon_reg.h"
771fe6b9
JG		 76
77/*
78 * Modules parameters.
79 */
80extern int radeon_no_wb;
81extern int radeon_modeset;
82extern int radeon_dynclks;
83extern int radeon_r4xx_atom;
84extern int radeon_agpmode;
85extern int radeon_vram_limit;
86extern int radeon_gart_size;
87extern int radeon_benchmarking;
ecc0b326 88extern int radeon_testing;
771fe6b9 89extern int radeon_connector_table;
4ce001ab 90extern int radeon_tv;
b27b6375 91extern int radeon_new_pll;
771fe6b9
JG		 92
93/*
94 * Copy from radeon_drv.h so we don't have to include both and have conflicting
95 * symbol;
96 */
97#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
98#define RADEON_IB_POOL_SIZE 16
99#define RADEON_DEBUGFS_MAX_NUM_FILES 32
100#define RADEONFB_CONN_LIMIT 4
f657c2a7 101#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 102
771fe6b9
JG		 103/*
104 * Errata workarounds.
105 */
106enum radeon_pll_errata {
107 CHIP_ERRATA_R300_CG = 0x00000001,
108 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
109 CHIP_ERRATA_PLL_DELAY = 0x00000004
110};
111
112
113struct radeon_device;
114
115
116/*
117 * BIOS.
118 */
119bool radeon_get_bios(struct radeon_device *rdev);
120
3ce0a23d 121
771fe6b9 122/*
3ce0a23d 123 * Dummy page
771fe6b9 124 */
3ce0a23d
JG		 125struct radeon_dummy_page {
126 struct page *page;
127 dma_addr_t addr;
128};
129int radeon_dummy_page_init(struct radeon_device *rdev);
130void radeon_dummy_page_fini(struct radeon_device *rdev);
131
771fe6b9 132
3ce0a23d
JG		 133/*
134 * Clocks
135 */
771fe6b9
JG		 136struct radeon_clock {
137 struct radeon_pll p1pll;
138 struct radeon_pll p2pll;
139 struct radeon_pll spll;
140 struct radeon_pll mpll;
141 /* 10 Khz units */
142 uint32_t default_mclk;
143 uint32_t default_sclk;
144};
145
7433874e
RM		 146/*
147 * Power management
148 */
149int radeon_pm_init(struct radeon_device *rdev);
3ce0a23d 150
771fe6b9
JG		 151/*
152 * Fences.
153 */
154struct radeon_fence_driver {
155 uint32_t scratch_reg;
156 atomic_t seq;
157 uint32_t last_seq;
158 unsigned long count_timeout;
159 wait_queue_head_t queue;
160 rwlock_t lock;
161 struct list_head created;
162 struct list_head emited;
163 struct list_head signaled;
164};
165
166struct radeon_fence {
167 struct radeon_device *rdev;
168 struct kref kref;
169 struct list_head list;
170 /* protected by radeon_fence.lock */
171 uint32_t seq;
172 unsigned long timeout;
173 bool emited;
174 bool signaled;
175};
176
177int radeon_fence_driver_init(struct radeon_device *rdev);
178void radeon_fence_driver_fini(struct radeon_device *rdev);
179int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
180int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
181void radeon_fence_process(struct radeon_device *rdev);
182bool radeon_fence_signaled(struct radeon_fence *fence);
183int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
184int radeon_fence_wait_next(struct radeon_device *rdev);
185int radeon_fence_wait_last(struct radeon_device *rdev);
186struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
187void radeon_fence_unref(struct radeon_fence **fence);
188
e024e110
DA		 189/*
190 * Tiling registers
191 */
192struct radeon_surface_reg {
4c788679 193 struct radeon_bo *bo;
e024e110
DA		 194};
195
196#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 197
198/*
4c788679 199 * TTM.
771fe6b9 200 */
4c788679
JG		 201struct radeon_mman {
202 struct ttm_bo_global_ref bo_global_ref;
203 struct ttm_global_reference mem_global_ref;
204 bool mem_global_referenced;
205 struct ttm_bo_device bdev;
206};
207
208struct radeon_bo {
209 /* Protected by gem.mutex */
210 struct list_head list;
211 /* Protected by tbo.reserved */
312ea8da
JG		 212 u32 placements[3];
213 struct ttm_placement placement;
4c788679
JG		 214 struct ttm_buffer_object tbo;
215 struct ttm_bo_kmap_obj kmap;
216 unsigned pin_count;
217 void *kptr;
218 u32 tiling_flags;
219 u32 pitch;
220 int surface_reg;
221 /* Constant after initialization */
222 struct radeon_device *rdev;
223 struct drm_gem_object *gobj;
224};
771fe6b9 225
4c788679 226struct radeon_bo_list {
771fe6b9 227 struct list_head list;
4c788679 228 struct radeon_bo *bo;
771fe6b9
JG		 229 uint64_t gpu_offset;
230 unsigned rdomain;
231 unsigned wdomain;
4c788679 232 u32 tiling_flags;
771fe6b9
JG		 233};
234
771fe6b9
JG		 235/*
236 * GEM objects.
237 */
238struct radeon_gem {
4c788679 239 struct mutex mutex;
771fe6b9
JG		 240 struct list_head objects;
241};
242
243int radeon_gem_init(struct radeon_device *rdev);
244void radeon_gem_fini(struct radeon_device *rdev);
245int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 246 int alignment, int initial_domain,
247 bool discardable, bool kernel,
248 struct drm_gem_object **obj);
771fe6b9
JG		 249int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
250 uint64_t *gpu_addr);
251void radeon_gem_object_unpin(struct drm_gem_object *obj);
252
253
254/*
255 * GART structures, functions & helpers
256 */
257struct radeon_mc;
258
259struct radeon_gart_table_ram {
260 volatile uint32_t *ptr;
261};
262
263struct radeon_gart_table_vram {
4c788679 264 struct radeon_bo *robj;
771fe6b9
JG		 265 volatile uint32_t *ptr;
266};
267
268union radeon_gart_table {
269 struct radeon_gart_table_ram ram;
270 struct radeon_gart_table_vram vram;
271};
272
a77f1718
MT		 273#define RADEON_GPU_PAGE_SIZE 4096
274
771fe6b9
JG		 275struct radeon_gart {
276 dma_addr_t table_addr;
277 unsigned num_gpu_pages;
278 unsigned num_cpu_pages;
279 unsigned table_size;
280 union radeon_gart_table table;
281 struct page **pages;
282 dma_addr_t *pages_addr;
283 bool ready;
284};
285
286int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
287void radeon_gart_table_ram_free(struct radeon_device *rdev);
288int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
289void radeon_gart_table_vram_free(struct radeon_device *rdev);
290int radeon_gart_init(struct radeon_device *rdev);
291void radeon_gart_fini(struct radeon_device *rdev);
292void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
293 int pages);
294int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
295 int pages, struct page **pagelist);
296
297
298/*
299 * GPU MC structures, functions & helpers
300 */
301struct radeon_mc {
302 resource_size_t aper_size;
303 resource_size_t aper_base;
304 resource_size_t agp_base;
7a50f01a
DA		 305 /* for some chips with <= 32MB we need to lie
306 * about vram size near mc fb location */
3ce0a23d
JG		 307 u64 mc_vram_size;
308 u64 gtt_location;
309 u64 gtt_size;
310 u64 gtt_start;
311 u64 gtt_end;
312 u64 vram_location;
313 u64 vram_start;
314 u64 vram_end;
771fe6b9 315 unsigned vram_width;
3ce0a23d 316 u64 real_vram_size;
771fe6b9
JG		 317 int vram_mtrr;
318 bool vram_is_ddr;
319};
320
321int radeon_mc_setup(struct radeon_device *rdev);
322
323
324/*
325 * GPU scratch registers structures, functions & helpers
326 */
327struct radeon_scratch {
328 unsigned num_reg;
329 bool free[32];
330 uint32_t reg[32];
331};
332
333int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
334void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
335
336
337/*
338 * IRQS.
339 */
340struct radeon_irq {
341 bool installed;
342 bool sw_int;
343 /* FIXME: use a define max crtc rather than hardcode it */
344 bool crtc_vblank_int[2];
b500f680
AD		 345 /* FIXME: use defines for max hpd/dacs */
346 bool hpd[6];
1614f8b1
DA		 347 spinlock_t sw_lock;
348 int sw_refcount;
771fe6b9
JG		 349};
350
351int radeon_irq_kms_init(struct radeon_device *rdev);
352void radeon_irq_kms_fini(struct radeon_device *rdev);
1614f8b1
DA		 353void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
354void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
771fe6b9
JG		 355
356/*
357 * CP & ring.
358 */
359struct radeon_ib {
360 struct list_head list;
361 unsigned long idx;
362 uint64_t gpu_addr;
363 struct radeon_fence *fence;
513bcb46 364 uint32_t *ptr;
771fe6b9
JG		 365 uint32_t length_dw;
366};
367
ecb114a1
DA		 368/*
369 * locking -
370 * mutex protects scheduled_ibs, ready, alloc_bm
371 */
771fe6b9
JG		 372struct radeon_ib_pool {
373 struct mutex mutex;
4c788679 374 struct radeon_bo *robj;
771fe6b9
JG		 375 struct list_head scheduled_ibs;
376 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
377 bool ready;
378 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
379};
380
381struct radeon_cp {
4c788679 382 struct radeon_bo *ring_obj;
771fe6b9
JG		 383 volatile uint32_t *ring;
384 unsigned rptr;
385 unsigned wptr;
386 unsigned wptr_old;
387 unsigned ring_size;
388 unsigned ring_free_dw;
389 int count_dw;
390 uint64_t gpu_addr;
391 uint32_t align_mask;
392 uint32_t ptr_mask;
393 struct mutex mutex;
394 bool ready;
395};
396
d8f60cfc
AD		 397/*
398 * R6xx+ IH ring
399 */
400struct r600_ih {
4c788679 401 struct radeon_bo *ring_obj;
d8f60cfc
AD		 402 volatile uint32_t *ring;
403 unsigned rptr;
404 unsigned wptr;
405 unsigned wptr_old;
406 unsigned ring_size;
407 uint64_t gpu_addr;
408 uint32_t align_mask;
409 uint32_t ptr_mask;
410 spinlock_t lock;
411 bool enabled;
412};
413
3ce0a23d 414struct r600_blit {
4c788679 415 struct radeon_bo *shader_obj;
3ce0a23d
JG		 416 u64 shader_gpu_addr;
417 u32 vs_offset, ps_offset;
418 u32 state_offset;
419 u32 state_len;
420 u32 vb_used, vb_total;
421 struct radeon_ib *vb_ib;
422};
423
771fe6b9
JG		 424int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
425void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
426int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
427int radeon_ib_pool_init(struct radeon_device *rdev);
428void radeon_ib_pool_fini(struct radeon_device *rdev);
429int radeon_ib_test(struct radeon_device *rdev);
430/* Ring access between begin & end cannot sleep */
431void radeon_ring_free_size(struct radeon_device *rdev);
432int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
433void radeon_ring_unlock_commit(struct radeon_device *rdev);
434void radeon_ring_unlock_undo(struct radeon_device *rdev);
435int radeon_ring_test(struct radeon_device *rdev);
436int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
437void radeon_ring_fini(struct radeon_device *rdev);
438
439
440/*
441 * CS.
442 */
443struct radeon_cs_reloc {
444 struct drm_gem_object *gobj;
4c788679
JG		 445 struct radeon_bo *robj;
446 struct radeon_bo_list lobj;
771fe6b9
JG		 447 uint32_t handle;
448 uint32_t flags;
449};
450
451struct radeon_cs_chunk {
452 uint32_t chunk_id;
453 uint32_t length_dw;
513bcb46
DA		 454 int kpage_idx[2];
455 uint32_t *kpage[2];
771fe6b9 456 uint32_t *kdata;
513bcb46
DA		 457 void __user *user_ptr;
458 int last_copied_page;
459 int last_page_index;
771fe6b9
JG		 460};
461
462struct radeon_cs_parser {
463 struct radeon_device *rdev;
464 struct drm_file *filp;
465 /* chunks */
466 unsigned nchunks;
467 struct radeon_cs_chunk *chunks;
468 uint64_t *chunks_array;
469 /* IB */
470 unsigned idx;
471 /* relocations */
472 unsigned nrelocs;
473 struct radeon_cs_reloc *relocs;
474 struct radeon_cs_reloc **relocs_ptr;
475 struct list_head validated;
476 /* indices of various chunks */
477 int chunk_ib_idx;
478 int chunk_relocs_idx;
479 struct radeon_ib *ib;
480 void *track;
3ce0a23d 481 unsigned family;
513bcb46 482 int parser_error;
771fe6b9
JG		 483};
484
513bcb46
DA		 485extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
486extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
487
488
489static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
490{
491 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
492 u32 pg_idx, pg_offset;
493 u32 idx_value = 0;
494 int new_page;
495
496 pg_idx = (idx * 4) / PAGE_SIZE;
497 pg_offset = (idx * 4) % PAGE_SIZE;
498
499 if (ibc->kpage_idx[0] == pg_idx)
500 return ibc->kpage[0][pg_offset/4];
501 if (ibc->kpage_idx[1] == pg_idx)
502 return ibc->kpage[1][pg_offset/4];
503
504 new_page = radeon_cs_update_pages(p, pg_idx);
505 if (new_page < 0) {
506 p->parser_error = new_page;
507 return 0;
508 }
509
510 idx_value = ibc->kpage[new_page][pg_offset/4];
511 return idx_value;
512}
513
771fe6b9
JG		 514struct radeon_cs_packet {
515 unsigned idx;
516 unsigned type;
517 unsigned reg;
518 unsigned opcode;
519 int count;
520 unsigned one_reg_wr;
521};
522
523typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
524 struct radeon_cs_packet *pkt,
525 unsigned idx, unsigned reg);
526typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
527 struct radeon_cs_packet *pkt);
528
529
530/*
531 * AGP
532 */
533int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 534void radeon_agp_resume(struct radeon_device *rdev);
771fe6b9
JG		 535void radeon_agp_fini(struct radeon_device *rdev);
536
537
538/*
539 * Writeback
540 */
541struct radeon_wb {
4c788679 542 struct radeon_bo *wb_obj;
771fe6b9
JG		 543 volatile uint32_t *wb;
544 uint64_t gpu_addr;
545};
546
c93bb85b
JG		 547/**
548 * struct radeon_pm - power management datas
549 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
550 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
551 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
552 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
553 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
554 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
555 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
556 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
557 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
558 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
559 * @needed_bandwidth: current bandwidth needs
560 *
561 * It keeps track of various data needed to take powermanagement decision.
562 * Bandwith need is used to determine minimun clock of the GPU and memory.
563 * Equation between gpu/memory clock and available bandwidth is hw dependent
564 * (type of memory, bus size, efficiency, ...)
565 */
566struct radeon_pm {
567 fixed20_12 max_bandwidth;
568 fixed20_12 igp_sideport_mclk;
569 fixed20_12 igp_system_mclk;
570 fixed20_12 igp_ht_link_clk;
571 fixed20_12 igp_ht_link_width;
572 fixed20_12 k8_bandwidth;
573 fixed20_12 sideport_bandwidth;
574 fixed20_12 ht_bandwidth;
575 fixed20_12 core_bandwidth;
576 fixed20_12 sclk;
577 fixed20_12 needed_bandwidth;
578};
579
771fe6b9
JG		 580
581/*
582 * Benchmarking
583 */
584void radeon_benchmark(struct radeon_device *rdev);
585
586
ecc0b326
MD		 587/*
588 * Testing
589 */
590void radeon_test_moves(struct radeon_device *rdev);
591
592
771fe6b9
JG		 593/*
594 * Debugfs
595 */
596int radeon_debugfs_add_files(struct radeon_device *rdev,
597 struct drm_info_list *files,
598 unsigned nfiles);
599int radeon_debugfs_fence_init(struct radeon_device *rdev);
600int r100_debugfs_rbbm_init(struct radeon_device *rdev);
601int r100_debugfs_cp_init(struct radeon_device *rdev);
602
603
604/*
605 * ASIC specific functions.
606 */
607struct radeon_asic {
068a117c 608 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 609 void (*fini)(struct radeon_device *rdev);
610 int (*resume)(struct radeon_device *rdev);
611 int (*suspend)(struct radeon_device *rdev);
28d52043 612 void (*vga_set_state)(struct radeon_device *rdev, bool state);
771fe6b9 613 int (*gpu_reset)(struct radeon_device *rdev);
771fe6b9
JG		 614 void (*gart_tlb_flush)(struct radeon_device *rdev);
615 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
616 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
617 void (*cp_fini)(struct radeon_device *rdev);
618 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 619 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 620 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 621 int (*ring_test)(struct radeon_device *rdev);
622 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 623 int (*irq_set)(struct radeon_device *rdev);
624 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 625 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 626 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
627 int (*cs_parse)(struct radeon_cs_parser *p);
628 int (*copy_blit)(struct radeon_device *rdev,
629 uint64_t src_offset,
630 uint64_t dst_offset,
631 unsigned num_pages,
632 struct radeon_fence *fence);
633 int (*copy_dma)(struct radeon_device *rdev,
634 uint64_t src_offset,
635 uint64_t dst_offset,
636 unsigned num_pages,
637 struct radeon_fence *fence);
638 int (*copy)(struct radeon_device *rdev,
639 uint64_t src_offset,
640 uint64_t dst_offset,
641 unsigned num_pages,
642 struct radeon_fence *fence);
7433874e 643 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 644 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 645 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9
JG		 646 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
647 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
648 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 649 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
650 uint32_t tiling_flags, uint32_t pitch,
651 uint32_t offset, uint32_t obj_size);
652 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 653 void (*bandwidth_update)(struct radeon_device *rdev);
23956dfa 654 void (*hdp_flush)(struct radeon_device *rdev);
429770b3
AD		 655 void (*hpd_init)(struct radeon_device *rdev);
656 void (*hpd_fini)(struct radeon_device *rdev);
657 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
658 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
771fe6b9
JG		 659};
660
21f9a437
JG		 661/*
662 * Asic structures
663 */
551ebd83
DA		 664struct r100_asic {
665 const unsigned *reg_safe_bm;
666 unsigned reg_safe_bm_size;
667};
668
21f9a437
JG		 669struct r300_asic {
670 const unsigned *reg_safe_bm;
671 unsigned reg_safe_bm_size;
672};
673
674struct r600_asic {
675 unsigned max_pipes;
676 unsigned max_tile_pipes;
677 unsigned max_simds;
678 unsigned max_backends;
679 unsigned max_gprs;
680 unsigned max_threads;
681 unsigned max_stack_entries;
682 unsigned max_hw_contexts;
683 unsigned max_gs_threads;
684 unsigned sx_max_export_size;
685 unsigned sx_max_export_pos_size;
686 unsigned sx_max_export_smx_size;
687 unsigned sq_num_cf_insts;
688};
689
690struct rv770_asic {
691 unsigned max_pipes;
692 unsigned max_tile_pipes;
693 unsigned max_simds;
694 unsigned max_backends;
695 unsigned max_gprs;
696 unsigned max_threads;
697 unsigned max_stack_entries;
698 unsigned max_hw_contexts;
699 unsigned max_gs_threads;
700 unsigned sx_max_export_size;
701 unsigned sx_max_export_pos_size;
702 unsigned sx_max_export_smx_size;
703 unsigned sq_num_cf_insts;
704 unsigned sx_num_of_sets;
705 unsigned sc_prim_fifo_size;
706 unsigned sc_hiz_tile_fifo_size;
707 unsigned sc_earlyz_tile_fifo_fize;
708};
709
068a117c
JG		 710union radeon_asic_config {
711 struct r300_asic r300;
551ebd83 712 struct r100_asic r100;
3ce0a23d
JG		 713 struct r600_asic r600;
714 struct rv770_asic rv770;
068a117c
JG		 715};
716
771fe6b9
JG		 717
718/*
719 * IOCTL.
720 */
721int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
722 struct drm_file *filp);
723int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
724 struct drm_file *filp);
725int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
726 struct drm_file *file_priv);
727int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
728 struct drm_file *file_priv);
729int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
730 struct drm_file *file_priv);
731int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
732 struct drm_file *file_priv);
733int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
734 struct drm_file *filp);
735int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
736 struct drm_file *filp);
737int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
738 struct drm_file *filp);
739int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
740 struct drm_file *filp);
741int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 742int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
743 struct drm_file *filp);
744int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
745 struct drm_file *filp);
771fe6b9
JG		 746
747
748/*
749 * Core structure, functions and helpers.
750 */
751typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
752typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
753
754struct radeon_device {
9f022ddf 755 struct device *dev;
771fe6b9
JG		 756 struct drm_device *ddev;
757 struct pci_dev *pdev;
758 /* ASIC */
068a117c 759 union radeon_asic_config config;
771fe6b9
JG		 760 enum radeon_family family;
761 unsigned long flags;
762 int usec_timeout;
763 enum radeon_pll_errata pll_errata;
764 int num_gb_pipes;
f779b3e5 765 int num_z_pipes;
771fe6b9
JG		 766 int disp_priority;
767 /* BIOS */
768 uint8_t *bios;
769 bool is_atom_bios;
770 uint16_t bios_header_start;
4c788679 771 struct radeon_bo *stollen_vga_memory;
771fe6b9 772 struct fb_info *fbdev_info;
4c788679 773 struct radeon_bo *fbdev_rbo;
771fe6b9
JG		 774 struct radeon_framebuffer *fbdev_rfb;
775 /* Register mmio */
4c9bc75c
DA		 776 resource_size_t rmmio_base;
777 resource_size_t rmmio_size;
771fe6b9 778 void *rmmio;
771fe6b9
JG		 779 radeon_rreg_t mc_rreg;
780 radeon_wreg_t mc_wreg;
781 radeon_rreg_t pll_rreg;
782 radeon_wreg_t pll_wreg;
de1b2898 783 uint32_t pcie_reg_mask;
771fe6b9
JG		 784 radeon_rreg_t pciep_rreg;
785 radeon_wreg_t pciep_wreg;
786 struct radeon_clock clock;
787 struct radeon_mc mc;
788 struct radeon_gart gart;
789 struct radeon_mode_info mode_info;
790 struct radeon_scratch scratch;
791 struct radeon_mman mman;
792 struct radeon_fence_driver fence_drv;
793 struct radeon_cp cp;
794 struct radeon_ib_pool ib_pool;
795 struct radeon_irq irq;
796 struct radeon_asic *asic;
797 struct radeon_gem gem;
c93bb85b 798 struct radeon_pm pm;
f657c2a7 799 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 800 struct mutex cs_mutex;
801 struct radeon_wb wb;
3ce0a23d 802 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 803 bool gpu_lockup;
804 bool shutdown;
805 bool suspend;
ad49f501 806 bool need_dma32;
733289c2 807 bool accel_working;
e024e110 808 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 809 const struct firmware *me_fw; /* all family ME firmware */
810 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 811 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
3ce0a23d 812 struct r600_blit r600_blit;
3e5cb98d 813 int msi_enabled; /* msi enabled */
d8f60cfc 814 struct r600_ih ih; /* r6/700 interrupt ring */
d4877cf2
AD		 815 struct workqueue_struct *wq;
816 struct work_struct hotplug_work;
771fe6b9
JG		 817};
818
819int radeon_device_init(struct radeon_device *rdev,
820 struct drm_device *ddev,
821 struct pci_dev *pdev,
822 uint32_t flags);
823void radeon_device_fini(struct radeon_device *rdev);
824int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
825
3ce0a23d
JG		 826/* r600 blit */
827int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
828void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
829void r600_kms_blit_copy(struct radeon_device *rdev,
830 u64 src_gpu_addr, u64 dst_gpu_addr,
831 int size_bytes);
832
de1b2898
DA		 833static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
834{
835 if (reg < 0x10000)
836 return readl(((void __iomem *)rdev->rmmio) + reg);
837 else {
838 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
839 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
840 }
841}
842
843static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
844{
845 if (reg < 0x10000)
846 writel(v, ((void __iomem *)rdev->rmmio) + reg);
847 else {
848 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
849 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
850 }
851}
852
4c788679
JG		 853/*
854 * Cast helper
855 */
856#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 857
858/*
859 * Registers read & write functions.
860 */
861#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
862#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 863#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 864#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 865#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 866#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
867#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
868#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
869#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
870#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
871#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 872#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
873#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
771fe6b9
JG		 874#define WREG32_P(reg, val, mask) \
875 do { \
876 uint32_t tmp_ = RREG32(reg); \
877 tmp_ &= (mask); \
878 tmp_ |= ((val) & ~(mask)); \
879 WREG32(reg, tmp_); \
880 } while (0)
881#define WREG32_PLL_P(reg, val, mask) \
882 do { \
883 uint32_t tmp_ = RREG32_PLL(reg); \
884 tmp_ &= (mask); \
885 tmp_ |= ((val) & ~(mask)); \
886 WREG32_PLL(reg, tmp_); \
887 } while (0)
3ce0a23d 888#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 889
de1b2898
DA		 890/*
891 * Indirect registers accessor
892 */
893static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
894{
895 uint32_t r;
896
897 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
898 r = RREG32(RADEON_PCIE_DATA);
899 return r;
900}
901
902static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
903{
904 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
905 WREG32(RADEON_PCIE_DATA, (v));
906}
907
771fe6b9
JG		 908void r100_pll_errata_after_index(struct radeon_device *rdev);
909
910
911/*
912 * ASICs helpers.
913 */
b995e433
DA		 914#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
915 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 916#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
917 (rdev->family == CHIP_RV200) || \
918 (rdev->family == CHIP_RS100) || \
919 (rdev->family == CHIP_RS200) || \
920 (rdev->family == CHIP_RV250) || \
921 (rdev->family == CHIP_RV280) || \
922 (rdev->family == CHIP_RS300))
923#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
924 (rdev->family == CHIP_RV350) || \
925 (rdev->family == CHIP_R350) || \
926 (rdev->family == CHIP_RV380) || \
927 (rdev->family == CHIP_R420) || \
928 (rdev->family == CHIP_R423) || \
929 (rdev->family == CHIP_RV410) || \
930 (rdev->family == CHIP_RS400) || \
931 (rdev->family == CHIP_RS480))
932#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
933#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
934#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
935
936
937/*
938 * BIOS helpers.
939 */
940#define RBIOS8(i) (rdev->bios[i])
941#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
942#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
943
944int radeon_combios_init(struct radeon_device *rdev);
945void radeon_combios_fini(struct radeon_device *rdev);
946int radeon_atombios_init(struct radeon_device *rdev);
947void radeon_atombios_fini(struct radeon_device *rdev);
948
949
950/*
951 * RING helpers.
952 */
771fe6b9
JG		 953static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
954{
955#if DRM_DEBUG_CODE
956 if (rdev->cp.count_dw <= 0) {
957 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
958 }
959#endif
960 rdev->cp.ring[rdev->cp.wptr++] = v;
961 rdev->cp.wptr &= rdev->cp.ptr_mask;
962 rdev->cp.count_dw--;
963 rdev->cp.ring_free_dw--;
964}
965
966
967/*
968 * ASICs macro.
969 */
068a117c 970#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 971#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
972#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
973#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 974#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 975#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
771fe6b9 976#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
771fe6b9
JG		 977#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
978#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 979#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 980#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 981#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
982#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 983#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
984#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 985#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 986#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
987#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
988#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
989#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 990#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 991#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 992#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
93e7de7b 993#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
771fe6b9
JG		 994#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
995#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 996#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
997#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 998#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
23956dfa 999#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
429770b3
AD		 1000#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1001#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1002#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1003#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
771fe6b9 1004
6cf8a3f5 1005/* Common functions */
4aac0473 1006extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
21f9a437
JG		 1007extern int radeon_modeset_init(struct radeon_device *rdev);
1008extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1009extern bool radeon_card_posted(struct radeon_device *rdev);
72542d77 1010extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437
JG		 1011extern int radeon_clocks_init(struct radeon_device *rdev);
1012extern void radeon_clocks_fini(struct radeon_device *rdev);
1013extern void radeon_scratch_init(struct radeon_device *rdev);
1014extern void radeon_surface_init(struct radeon_device *rdev);
1015extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1016extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1017extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 1018extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 1019extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
6cf8a3f5 1020
a18d7ea1 1021/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
9f022ddf
JG		 1022struct r100_mc_save {
1023 u32 GENMO_WT;
1024 u32 CRTC_EXT_CNTL;
1025 u32 CRTC_GEN_CNTL;
1026 u32 CRTC2_GEN_CNTL;
1027 u32 CUR_OFFSET;
1028 u32 CUR2_OFFSET;
1029};
1030extern void r100_cp_disable(struct radeon_device *rdev);
1031extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1032extern void r100_cp_fini(struct radeon_device *rdev);
21f9a437 1033extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
4aac0473
JG		 1034extern int r100_pci_gart_init(struct radeon_device *rdev);
1035extern void r100_pci_gart_fini(struct radeon_device *rdev);
21f9a437
JG		 1036extern int r100_pci_gart_enable(struct radeon_device *rdev);
1037extern void r100_pci_gart_disable(struct radeon_device *rdev);
1038extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
9f022ddf
JG		 1039extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1040extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1041extern void r100_ib_fini(struct radeon_device *rdev);
1042extern int r100_ib_init(struct radeon_device *rdev);
1043extern void r100_irq_disable(struct radeon_device *rdev);
1044extern int r100_irq_set(struct radeon_device *rdev);
1045extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1046extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
21f9a437 1047extern void r100_vram_init_sizes(struct radeon_device *rdev);
9f022ddf
JG		 1048extern void r100_wb_disable(struct radeon_device *rdev);
1049extern void r100_wb_fini(struct radeon_device *rdev);
1050extern int r100_wb_init(struct radeon_device *rdev);
d39c3b89
JG		 1051extern void r100_hdp_reset(struct radeon_device *rdev);
1052extern int r100_rb2d_reset(struct radeon_device *rdev);
1053extern int r100_cp_reset(struct radeon_device *rdev);
ca6ffc64 1054extern void r100_vga_render_disable(struct radeon_device *rdev);
207bf9e9
JG		 1055extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1056 struct radeon_cs_packet *pkt,
4c788679 1057 struct radeon_bo *robj);
207bf9e9
JG		 1058extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1059 struct radeon_cs_packet *pkt,
1060 const unsigned *auth, unsigned n,
1061 radeon_packet0_check_t check);
1062extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1063 struct radeon_cs_packet *pkt,
1064 unsigned idx);
17e15b0c 1065extern void r100_enable_bm(struct radeon_device *rdev);
92cde00c 1066extern void r100_set_common_regs(struct radeon_device *rdev);
9f022ddf 1067
d4550907
JG		 1068/* rv200,rv250,rv280 */
1069extern void r200_set_safe_registers(struct radeon_device *rdev);
9f022ddf
JG		 1070
1071/* r300,r350,rv350,rv370,rv380 */
1072extern void r300_set_reg_safe(struct radeon_device *rdev);
1073extern void r300_mc_program(struct radeon_device *rdev);
1074extern void r300_vram_info(struct radeon_device *rdev);
ca6ffc64
JG		 1075extern void r300_clock_startup(struct radeon_device *rdev);
1076extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473
JG		 1077extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1078extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1079extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1080extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1081
905b6822 1082/* r420,r423,rv410 */
d39c3b89 1083extern int r420_mc_init(struct radeon_device *rdev);
21f9a437
JG		 1084extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1085extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1086extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
d39c3b89 1087extern void r420_pipes_init(struct radeon_device *rdev);
905b6822 1088
21f9a437 1089/* rv515 */
d39c3b89
JG		 1090struct rv515_mc_save {
1091 u32 d1vga_control;
1092 u32 d2vga_control;
1093 u32 vga_render_control;
1094 u32 vga_hdp_control;
1095 u32 d1crtc_control;
1096 u32 d2crtc_control;
1097};
21f9a437 1098extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
d39c3b89
JG		 1099extern void rv515_vga_render_disable(struct radeon_device *rdev);
1100extern void rv515_set_safe_registers(struct radeon_device *rdev);
f0ed1f65
JG		 1101extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1102extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1103extern void rv515_clock_startup(struct radeon_device *rdev);
1104extern void rv515_debugfs(struct radeon_device *rdev);
1105extern int rv515_suspend(struct radeon_device *rdev);
21f9a437 1106
3bc68535
JG		 1107/* rs400 */
1108extern int rs400_gart_init(struct radeon_device *rdev);
1109extern int rs400_gart_enable(struct radeon_device *rdev);
1110extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1111extern void rs400_gart_disable(struct radeon_device *rdev);
1112extern void rs400_gart_fini(struct radeon_device *rdev);
1113
1114/* rs600 */
1115extern void rs600_set_safe_registers(struct radeon_device *rdev);
ac447df4
JG		 1116extern int rs600_irq_set(struct radeon_device *rdev);
1117extern void rs600_irq_disable(struct radeon_device *rdev);
3bc68535 1118
21f9a437
JG		 1119/* rs690, rs740 */
1120extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1121 struct drm_display_mode *mode1,
1122 struct drm_display_mode *mode2);
1123
1124/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1125extern bool r600_card_posted(struct radeon_device *rdev);
1126extern void r600_cp_stop(struct radeon_device *rdev);
1127extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1128extern int r600_cp_resume(struct radeon_device *rdev);
1129extern int r600_count_pipe_bits(uint32_t val);
1130extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1131extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1132extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1133extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1134extern int r600_ib_test(struct radeon_device *rdev);
1135extern int r600_ring_test(struct radeon_device *rdev);
21f9a437 1136extern void r600_wb_fini(struct radeon_device *rdev);
81cc35bf
JG		 1137extern int r600_wb_enable(struct radeon_device *rdev);
1138extern void r600_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1139extern void r600_scratch_init(struct radeon_device *rdev);
1140extern int r600_blit_init(struct radeon_device *rdev);
1141extern void r600_blit_fini(struct radeon_device *rdev);
d8f60cfc 1142extern int r600_init_microcode(struct radeon_device *rdev);
fe62e1a4 1143extern int r600_gpu_reset(struct radeon_device *rdev);
d8f60cfc
AD		 1144/* r600 irq */
1145extern int r600_irq_init(struct radeon_device *rdev);
1146extern void r600_irq_fini(struct radeon_device *rdev);
1147extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1148extern int r600_irq_set(struct radeon_device *rdev);
21f9a437 1149
4c788679
JG		 1150#include "radeon_object.h"
1151
771fe6b9 1152#endif
Linux 6.x block layer and io_uring tree(s)