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drm/radeon: properly document reloc priority mask
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
0aea5e4a 67#include <linux/interval_tree.h>
771fe6b9 68
4c788679
JG		 69#include <ttm/ttm_bo_api.h>
70#include <ttm/ttm_bo_driver.h>
71#include <ttm/ttm_placement.h>
72#include <ttm/ttm_module.h>
147666fb 73#include <ttm/ttm_execbuf_util.h>
4c788679 74
c2142715 75#include "radeon_family.h"
771fe6b9
JG		 76#include "radeon_mode.h"
77#include "radeon_reg.h"
771fe6b9
JG		 78
79/*
80 * Modules parameters.
81 */
82extern int radeon_no_wb;
83extern int radeon_modeset;
84extern int radeon_dynclks;
85extern int radeon_r4xx_atom;
86extern int radeon_agpmode;
87extern int radeon_vram_limit;
88extern int radeon_gart_size;
89extern int radeon_benchmarking;
ecc0b326 90extern int radeon_testing;
771fe6b9 91extern int radeon_connector_table;
4ce001ab 92extern int radeon_tv;
dafc3bd5 93extern int radeon_audio;
f46c0120 94extern int radeon_disp_priority;
e2b0a8e1 95extern int radeon_hw_i2c;
d42dd579 96extern int radeon_pcie_gen2;
a18cee15 97extern int radeon_msi;
3368ff0c 98extern int radeon_lockup_timeout;
a0a53aa8 99extern int radeon_fastfb;
da321c8a 100extern int radeon_dpm;
1294d4a3 101extern int radeon_aspm;
10ebc0bc 102extern int radeon_runtime_pm;
363eb0b4 103extern int radeon_hard_reset;
c1c44132 104extern int radeon_vm_size;
4510fb98 105extern int radeon_vm_block_size;
a624f429 106extern int radeon_deep_color;
39dc5454 107extern int radeon_use_pflipirq;
6e909f74 108extern int radeon_bapm;
771fe6b9
JG		 109
110/*
111 * Copy from radeon_drv.h so we don't have to include both and have conflicting
112 * symbol;
113 */
bb635567
JG		 114#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
115#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 116/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 117#define RADEON_IB_POOL_SIZE 16
118#define RADEON_DEBUGFS_MAX_COMPONENTS 32
119#define RADEONFB_CONN_LIMIT 4
120#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 121
bb635567
JG		 122/* fence seq are set to this number when signaled */
123#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 124
125/* internal ring indices */
126/* r1xx+ has gfx CP ring */
d93f7937 127#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 128
129/* cayman has 2 compute CP rings */
d93f7937
CK		 130#define CAYMAN_RING_TYPE_CP1_INDEX 1
131#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 132
4d75658b
AD		 133/* R600+ has an async dma ring */
134#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 135/* cayman add a second async dma ring */
136#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 137
f2ba57b5 138/* R600+ */
d93f7937
CK		 139#define R600_RING_TYPE_UVD_INDEX 5
140
141/* TN+ */
142#define TN_RING_TYPE_VCE1_INDEX 6
143#define TN_RING_TYPE_VCE2_INDEX 7
144
145/* max number of rings */
146#define RADEON_NUM_RINGS 8
f2ba57b5 147
1c61eae4
CK		 148/* number of hw syncs before falling back on blocking */
149#define RADEON_NUM_SYNCS 4
f2ba57b5 150
8f53492f
CK		 151/* number of hw syncs before falling back on blocking */
152#define RADEON_NUM_SYNCS 4
153
721604a1 154/* hardcode those limit for now */
ca19f21e 155#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 156#define RADEON_VA_RESERVED_SIZE (8 << 20)
157#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 158
1a0041b8
AD		 159/* hard reset data */
160#define RADEON_ASIC_RESET_DATA 0x39d5e86b
161
ec46c76d
AD		 162/* reset flags */
163#define RADEON_RESET_GFX (1 << 0)
164#define RADEON_RESET_COMPUTE (1 << 1)
165#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 166#define RADEON_RESET_CP (1 << 3)
167#define RADEON_RESET_GRBM (1 << 4)
168#define RADEON_RESET_DMA1 (1 << 5)
169#define RADEON_RESET_RLC (1 << 6)
170#define RADEON_RESET_SEM (1 << 7)
171#define RADEON_RESET_IH (1 << 8)
172#define RADEON_RESET_VMC (1 << 9)
173#define RADEON_RESET_MC (1 << 10)
174#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 175
22c775ce
AD		 176/* CG block flags */
177#define RADEON_CG_BLOCK_GFX (1 << 0)
178#define RADEON_CG_BLOCK_MC (1 << 1)
179#define RADEON_CG_BLOCK_SDMA (1 << 2)
180#define RADEON_CG_BLOCK_UVD (1 << 3)
181#define RADEON_CG_BLOCK_VCE (1 << 4)
182#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 183#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 184
64d8a728
AD		 185/* CG flags */
186#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
187#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
188#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
189#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
190#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
191#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
192#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
193#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
194#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
195#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
196#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
197#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
198#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
199#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
200#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
201#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
202#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
203
204/* PG flags */
2b19d17f 205#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 206#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
207#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
208#define RADEON_PG_SUPPORT_UVD (1 << 3)
209#define RADEON_PG_SUPPORT_VCE (1 << 4)
210#define RADEON_PG_SUPPORT_CP (1 << 5)
211#define RADEON_PG_SUPPORT_GDS (1 << 6)
212#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
213#define RADEON_PG_SUPPORT_SDMA (1 << 8)
214#define RADEON_PG_SUPPORT_ACP (1 << 9)
215#define RADEON_PG_SUPPORT_SAMU (1 << 10)
216
9e05fa1d
AD		 217/* max cursor sizes (in pixels) */
218#define CURSOR_WIDTH 64
219#define CURSOR_HEIGHT 64
220
221#define CIK_CURSOR_WIDTH 128
222#define CIK_CURSOR_HEIGHT 128
223
771fe6b9
JG		 224/*
225 * Errata workarounds.
226 */
227enum radeon_pll_errata {
228 CHIP_ERRATA_R300_CG = 0x00000001,
229 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
230 CHIP_ERRATA_PLL_DELAY = 0x00000004
231};
232
233
234struct radeon_device;
235
236
237/*
238 * BIOS.
239 */
240bool radeon_get_bios(struct radeon_device *rdev);
241
242/*
3ce0a23d 243 * Dummy page
771fe6b9 244 */
3ce0a23d
JG		 245struct radeon_dummy_page {
246 struct page *page;
247 dma_addr_t addr;
248};
249int radeon_dummy_page_init(struct radeon_device *rdev);
250void radeon_dummy_page_fini(struct radeon_device *rdev);
251
771fe6b9 252
3ce0a23d
JG		 253/*
254 * Clocks
255 */
771fe6b9
JG		 256struct radeon_clock {
257 struct radeon_pll p1pll;
258 struct radeon_pll p2pll;
bcc1c2a1 259 struct radeon_pll dcpll;
771fe6b9
JG		 260 struct radeon_pll spll;
261 struct radeon_pll mpll;
262 /* 10 Khz units */
263 uint32_t default_mclk;
264 uint32_t default_sclk;
bcc1c2a1 265 uint32_t default_dispclk;
4489cd62 266 uint32_t current_dispclk;
bcc1c2a1 267 uint32_t dp_extclk;
b20f9bef 268 uint32_t max_pixel_clock;
771fe6b9
JG		 269};
270
7433874e
RM		 271/*
272 * Power management
273 */
274int radeon_pm_init(struct radeon_device *rdev);
914a8987 275int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 276void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 277void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 278void radeon_pm_suspend(struct radeon_device *rdev);
279void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 280void radeon_combios_get_power_modes(struct radeon_device *rdev);
281void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 282int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
283 u8 clock_type,
284 u32 clock,
285 bool strobe_mode,
286 struct atom_clock_dividers *dividers);
eaa778af
AD		 287int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
288 u32 clock,
289 bool strobe_mode,
290 struct atom_mpll_param *mpll_param);
8a83ec5e 291void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 292int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
293 u16 voltage_level, u8 voltage_type,
294 u32 *gpio_value, u32 *gpio_mask);
295void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
296 u32 eng_clock, u32 mem_clock);
297int radeon_atom_get_voltage_step(struct radeon_device *rdev,
298 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 299int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
300 u16 voltage_id, u16 *voltage);
beb79f40
AD		 301int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
302 u16 *voltage,
303 u16 leakage_idx);
cc8dbbb4
AD		 304int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
305 u16 *leakage_id);
306int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
307 u16 *vddc, u16 *vddci,
308 u16 virtual_voltage_id,
309 u16 vbios_voltage_id);
e9f274b2
AD		 310int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
311 u16 virtual_voltage_id,
312 u16 *voltage);
ae5b0abb
AD		 313int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
314 u8 voltage_type,
315 u16 nominal_voltage,
316 u16 *true_voltage);
317int radeon_atom_get_min_voltage(struct radeon_device *rdev,
318 u8 voltage_type, u16 *min_voltage);
319int radeon_atom_get_max_voltage(struct radeon_device *rdev,
320 u8 voltage_type, u16 *max_voltage);
321int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 322 u8 voltage_type, u8 voltage_mode,
ae5b0abb 323 struct atom_voltage_table *voltage_table);
58653abd
AD		 324bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
325 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 326int radeon_atom_get_svi2_info(struct radeon_device *rdev,
327 u8 voltage_type,
328 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 329void radeon_atom_update_memory_dll(struct radeon_device *rdev,
330 u32 mem_clock);
331void radeon_atom_set_ac_timing(struct radeon_device *rdev,
332 u32 mem_clock);
333int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
334 u8 module_index,
335 struct atom_mc_reg_table *reg_table);
336int radeon_atom_get_memory_info(struct radeon_device *rdev,
337 u8 module_index, struct atom_memory_info *mem_info);
338int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
339 bool gddr5, u8 module_index,
340 struct atom_memory_clock_range_table *mclk_range_table);
341int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
342 u16 voltage_id, u16 *voltage);
f892034a 343void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 344extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
345 unsigned *bankh, unsigned *mtaspect,
346 unsigned *tile_split);
3ce0a23d 347
771fe6b9
JG		 348/*
349 * Fences.
350 */
351struct radeon_fence_driver {
352 uint32_t scratch_reg;
30eb77f4
JG		 353 uint64_t gpu_addr;
354 volatile uint32_t *cpu_addr;
68e250b7
CK		 355 /* sync_seq is protected by ring emission lock */
356 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 357 atomic64_t last_seq;
0a0c7596 358 bool initialized;
771fe6b9
JG		 359};
360
361struct radeon_fence {
362 struct radeon_device *rdev;
363 struct kref kref;
771fe6b9 364 /* protected by radeon_fence.lock */
bb635567 365 uint64_t seq;
7465280c 366 /* RB, DMA, etc. */
bb635567 367 unsigned ring;
771fe6b9
JG		 368};
369
30eb77f4
JG		 370int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
371int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 372void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 373void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 374int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 375void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 376bool radeon_fence_signaled(struct radeon_fence *fence);
377int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 378int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
379int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 380int radeon_fence_wait_any(struct radeon_device *rdev,
381 struct radeon_fence **fences,
382 bool intr);
771fe6b9
JG		 383struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
384void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 385unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 386bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
387void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
388static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
389 struct radeon_fence *b)
390{
391 if (!a) {
392 return b;
393 }
394
395 if (!b) {
396 return a;
397 }
398
399 BUG_ON(a->ring != b->ring);
400
401 if (a->seq > b->seq) {
402 return a;
403 } else {
404 return b;
405 }
406}
771fe6b9 407
ee60e29f
CK		 408static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
409 struct radeon_fence *b)
410{
411 if (!a) {
412 return false;
413 }
414
415 if (!b) {
416 return true;
417 }
418
419 BUG_ON(a->ring != b->ring);
420
421 return a->seq < b->seq;
422}
423
e024e110
DA		 424/*
425 * Tiling registers
426 */
427struct radeon_surface_reg {
4c788679 428 struct radeon_bo *bo;
e024e110
DA		 429};
430
431#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 432
433/*
4c788679 434 * TTM.
771fe6b9 435 */
4c788679
JG		 436struct radeon_mman {
437 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 438 struct drm_global_reference mem_global_ref;
4c788679 439 struct ttm_bo_device bdev;
0a0c7596
JG		 440 bool mem_global_referenced;
441 bool initialized;
2014b569
CK		 442
443#if defined(CONFIG_DEBUG_FS)
444 struct dentry *vram;
dd66d20e 445 struct dentry *gtt;
2014b569 446#endif
4c788679
JG		 447};
448
721604a1
JG		 449/* bo virtual address in a specific vm */
450struct radeon_bo_va {
e971bd5e 451 /* protected by bo being reserved */
721604a1 452 struct list_head bo_list;
721604a1 453 uint32_t flags;
e31ad969 454 uint64_t addr;
e971bd5e
CK		 455 unsigned ref_count;
456
457 /* protected by vm mutex */
0aea5e4a 458 struct interval_tree_node it;
036bf46a 459 struct list_head vm_status;
e971bd5e
CK		 460
461 /* constant after initialization */
462 struct radeon_vm *vm;
463 struct radeon_bo *bo;
721604a1
JG		 464};
465
4c788679
JG		 466struct radeon_bo {
467 /* Protected by gem.mutex */
468 struct list_head list;
469 /* Protected by tbo.reserved */
bda72d58 470 u32 initial_domain;
312ea8da
JG		 471 u32 placements[3];
472 struct ttm_placement placement;
4c788679
JG		 473 struct ttm_buffer_object tbo;
474 struct ttm_bo_kmap_obj kmap;
02376d82 475 u32 flags;
4c788679
JG		 476 unsigned pin_count;
477 void *kptr;
478 u32 tiling_flags;
479 u32 pitch;
480 int surface_reg;
721604a1
JG		 481 /* list of all virtual address to which this bo
482 * is associated to
483 */
484 struct list_head va;
4c788679
JG		 485 /* Constant after initialization */
486 struct radeon_device *rdev;
441921d5 487 struct drm_gem_object gem_base;
63bc620b 488
409851f4
JG		 489 struct ttm_bo_kmap_obj dma_buf_vmap;
490 pid_t pid;
4c788679 491};
7e4d15d9 492#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 493
409851f4
JG		 494int radeon_gem_debugfs_init(struct radeon_device *rdev);
495
b15ba512
JG		 496/* sub-allocation manager, it has to be protected by another lock.
497 * By conception this is an helper for other part of the driver
498 * like the indirect buffer or semaphore, which both have their
499 * locking.
500 *
501 * Principe is simple, we keep a list of sub allocation in offset
502 * order (first entry has offset == 0, last entry has the highest
503 * offset).
504 *
505 * When allocating new object we first check if there is room at
506 * the end total_size - (last_object_offset + last_object_size) >=
507 * alloc_size. If so we allocate new object there.
508 *
509 * When there is not enough room at the end, we start waiting for
510 * each sub object until we reach object_offset+object_size >=
511 * alloc_size, this object then become the sub object we return.
512 *
513 * Alignment can't be bigger than page size.
514 *
515 * Hole are not considered for allocation to keep things simple.
516 * Assumption is that there won't be hole (all object on same
517 * alignment).
518 */
519struct radeon_sa_manager {
bfb38d35 520 wait_queue_head_t wq;
b15ba512 521 struct radeon_bo *bo;
c3b7fe8b
CK		 522 struct list_head *hole;
523 struct list_head flist[RADEON_NUM_RINGS];
524 struct list_head olist;
b15ba512
JG		 525 unsigned size;
526 uint64_t gpu_addr;
527 void *cpu_ptr;
528 uint32_t domain;
6c4f978b 529 uint32_t align;
b15ba512
JG		 530};
531
532struct radeon_sa_bo;
533
534/* sub-allocation buffer */
535struct radeon_sa_bo {
c3b7fe8b
CK		 536 struct list_head olist;
537 struct list_head flist;
b15ba512 538 struct radeon_sa_manager *manager;
e6661a96
CK		 539 unsigned soffset;
540 unsigned eoffset;
557017a0 541 struct radeon_fence *fence;
b15ba512
JG		 542};
543
771fe6b9
JG		 544/*
545 * GEM objects.
546 */
547struct radeon_gem {
4c788679 548 struct mutex mutex;
771fe6b9
JG		 549 struct list_head objects;
550};
551
552int radeon_gem_init(struct radeon_device *rdev);
553void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 554int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 555 int alignment, int initial_domain,
ed5cb43f 556 u32 flags, bool kernel,
4c788679 557 struct drm_gem_object **obj);
771fe6b9 558
ff72145b
DA		 559int radeon_mode_dumb_create(struct drm_file *file_priv,
560 struct drm_device *dev,
561 struct drm_mode_create_dumb *args);
562int radeon_mode_dumb_mmap(struct drm_file *filp,
563 struct drm_device *dev,
564 uint32_t handle, uint64_t *offset_p);
771fe6b9 565
c1341e52
JG		 566/*
567 * Semaphores.
568 */
c1341e52 569struct radeon_semaphore {
a8c05940
JG		 570 struct radeon_sa_bo *sa_bo;
571 signed waiters;
c1341e52 572 uint64_t gpu_addr;
1654b817 573 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 574};
575
c1341e52
JG		 576int radeon_semaphore_create(struct radeon_device *rdev,
577 struct radeon_semaphore **semaphore);
1654b817 578bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 579 struct radeon_semaphore *semaphore);
1654b817 580bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 581 struct radeon_semaphore *semaphore);
1654b817
CK		 582void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
583 struct radeon_fence *fence);
8f676c4c
CK		 584int radeon_semaphore_sync_rings(struct radeon_device *rdev,
585 struct radeon_semaphore *semaphore,
1654b817 586 int waiting_ring);
c1341e52 587void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 588 struct radeon_semaphore **semaphore,
a8c05940 589 struct radeon_fence *fence);
c1341e52 590
771fe6b9
JG		 591/*
592 * GART structures, functions & helpers
593 */
594struct radeon_mc;
595
a77f1718 596#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 597#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 598#define RADEON_GPU_PAGE_SHIFT 12
721604a1 599#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 600
77497f27
MD		 601#define RADEON_GART_PAGE_DUMMY 0
602#define RADEON_GART_PAGE_VALID (1 << 0)
603#define RADEON_GART_PAGE_READ (1 << 1)
604#define RADEON_GART_PAGE_WRITE (1 << 2)
605#define RADEON_GART_PAGE_SNOOP (1 << 3)
606
771fe6b9
JG		 607struct radeon_gart {
608 dma_addr_t table_addr;
c9a1be96
JG		 609 struct radeon_bo *robj;
610 void *ptr;
771fe6b9
JG		 611 unsigned num_gpu_pages;
612 unsigned num_cpu_pages;
613 unsigned table_size;
771fe6b9
JG		 614 struct page **pages;
615 dma_addr_t *pages_addr;
616 bool ready;
617};
618
619int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
620void radeon_gart_table_ram_free(struct radeon_device *rdev);
621int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
622void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 623int radeon_gart_table_vram_pin(struct radeon_device *rdev);
624void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 625int radeon_gart_init(struct radeon_device *rdev);
626void radeon_gart_fini(struct radeon_device *rdev);
627void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
628 int pages);
629int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 630 int pages, struct page **pagelist,
77497f27 631 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 632
633
634/*
635 * GPU MC structures, functions & helpers
636 */
637struct radeon_mc {
638 resource_size_t aper_size;
639 resource_size_t aper_base;
640 resource_size_t agp_base;
7a50f01a
DA		 641 /* for some chips with <= 32MB we need to lie
642 * about vram size near mc fb location */
3ce0a23d 643 u64 mc_vram_size;
d594e46a 644 u64 visible_vram_size;
3ce0a23d
JG		 645 u64 gtt_size;
646 u64 gtt_start;
647 u64 gtt_end;
3ce0a23d
JG		 648 u64 vram_start;
649 u64 vram_end;
771fe6b9 650 unsigned vram_width;
3ce0a23d 651 u64 real_vram_size;
771fe6b9
JG		 652 int vram_mtrr;
653 bool vram_is_ddr;
d594e46a 654 bool igp_sideport_enabled;
8d369bb1 655 u64 gtt_base_align;
9ed8b1f9 656 u64 mc_mask;
771fe6b9
JG		 657};
658
06b6476d
AD		 659bool radeon_combios_sideport_present(struct radeon_device *rdev);
660bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 661
662/*
663 * GPU scratch registers structures, functions & helpers
664 */
665struct radeon_scratch {
666 unsigned num_reg;
724c80e1 667 uint32_t reg_base;
771fe6b9
JG		 668 bool free[32];
669 uint32_t reg[32];
670};
671
672int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
673void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
674
75efdee1
AD		 675/*
676 * GPU doorbell structures, functions & helpers
677 */
d5754ab8
AL		 678#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
679
75efdee1 680struct radeon_doorbell {
75efdee1 681 /* doorbell mmio */
d5754ab8
AL		 682 resource_size_t base;
683 resource_size_t size;
684 u32 __iomem *ptr;
685 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
686 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 687};
688
689int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
690void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 691
692/*
693 * IRQS.
694 */
6f34be50 695
fa7f517c
CK		 696struct radeon_flip_work {
697 struct work_struct flip_work;
698 struct work_struct unpin_work;
699 struct radeon_device *rdev;
700 int crtc_id;
c60381bd 701 uint64_t base;
6f34be50 702 struct drm_pending_vblank_event *event;
fa7f517c 703 struct radeon_bo *old_rbo;
fa7f517c 704 struct radeon_fence *fence;
6f34be50
AD		 705};
706
707struct r500_irq_stat_regs {
708 u32 disp_int;
f122c610 709 u32 hdmi0_status;
6f34be50
AD		 710};
711
712struct r600_irq_stat_regs {
713 u32 disp_int;
714 u32 disp_int_cont;
715 u32 disp_int_cont2;
716 u32 d1grph_int;
717 u32 d2grph_int;
f122c610
AD		 718 u32 hdmi0_status;
719 u32 hdmi1_status;
6f34be50
AD		 720};
721
722struct evergreen_irq_stat_regs {
723 u32 disp_int;
724 u32 disp_int_cont;
725 u32 disp_int_cont2;
726 u32 disp_int_cont3;
727 u32 disp_int_cont4;
728 u32 disp_int_cont5;
729 u32 d1grph_int;
730 u32 d2grph_int;
731 u32 d3grph_int;
732 u32 d4grph_int;
733 u32 d5grph_int;
734 u32 d6grph_int;
f122c610
AD		 735 u32 afmt_status1;
736 u32 afmt_status2;
737 u32 afmt_status3;
738 u32 afmt_status4;
739 u32 afmt_status5;
740 u32 afmt_status6;
6f34be50
AD		 741};
742
a59781bb
AD		 743struct cik_irq_stat_regs {
744 u32 disp_int;
745 u32 disp_int_cont;
746 u32 disp_int_cont2;
747 u32 disp_int_cont3;
748 u32 disp_int_cont4;
749 u32 disp_int_cont5;
750 u32 disp_int_cont6;
f5d636d2
CK		 751 u32 d1grph_int;
752 u32 d2grph_int;
753 u32 d3grph_int;
754 u32 d4grph_int;
755 u32 d5grph_int;
756 u32 d6grph_int;
a59781bb
AD		 757};
758
6f34be50
AD		 759union radeon_irq_stat_regs {
760 struct r500_irq_stat_regs r500;
761 struct r600_irq_stat_regs r600;
762 struct evergreen_irq_stat_regs evergreen;
a59781bb 763 struct cik_irq_stat_regs cik;
6f34be50
AD		 764};
765
771fe6b9 766struct radeon_irq {
fb98257a
CK		 767 bool installed;
768 spinlock_t lock;
736fc37f 769 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 770 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 771 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 772 wait_queue_head_t vblank_queue;
773 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 774 bool afmt[RADEON_MAX_AFMT_BLOCKS];
775 union radeon_irq_stat_regs stat_regs;
4a6369e9 776 bool dpm_thermal;
771fe6b9
JG		 777};
778
779int radeon_irq_kms_init(struct radeon_device *rdev);
780void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 781void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
782void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 783void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
784void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 785void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
786void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
787void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
788void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 789
790/*
e32eb50d 791 * CP & rings.
771fe6b9 792 */
7465280c 793
771fe6b9 794struct radeon_ib {
68470ae7
JG		 795 struct radeon_sa_bo *sa_bo;
796 uint32_t length_dw;
797 uint64_t gpu_addr;
798 uint32_t *ptr;
876dc9f3 799 int ring;
68470ae7 800 struct radeon_fence *fence;
4bf3dd92 801 struct radeon_vm *vm;
68470ae7
JG		 802 bool is_const_ib;
803 struct radeon_semaphore *semaphore;
771fe6b9
JG		 804};
805
e32eb50d 806struct radeon_ring {
4c788679 807 struct radeon_bo *ring_obj;
771fe6b9 808 volatile uint32_t *ring;
5596a9db 809 unsigned rptr_offs;
45df6803 810 unsigned rptr_save_reg;
89d35807
AD		 811 u64 next_rptr_gpu_addr;
812 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 813 unsigned wptr;
814 unsigned wptr_old;
815 unsigned ring_size;
816 unsigned ring_free_dw;
817 int count_dw;
aee4aa73
CK		 818 atomic_t last_rptr;
819 atomic64_t last_activity;
771fe6b9
JG		 820 uint64_t gpu_addr;
821 uint32_t align_mask;
822 uint32_t ptr_mask;
771fe6b9 823 bool ready;
78c5560a 824 u32 nop;
8b25ed34 825 u32 idx;
5f0839c1
JG		 826 u64 last_semaphore_signal_addr;
827 u64 last_semaphore_wait_addr;
963e81f9
AD		 828 /* for CIK queues */
829 u32 me;
830 u32 pipe;
831 u32 queue;
832 struct radeon_bo *mqd_obj;
d5754ab8 833 u32 doorbell_index;
963e81f9
AD		 834 unsigned wptr_offs;
835};
836
837struct radeon_mec {
838 struct radeon_bo *hpd_eop_obj;
839 u64 hpd_eop_gpu_addr;
840 u32 num_pipe;
841 u32 num_mec;
842 u32 num_queue;
771fe6b9
JG		 843};
844
721604a1
JG		 845/*
846 * VM
847 */
ee60e29f 848
fa87e62d 849/* maximum number of VMIDs */
ee60e29f
CK		 850#define RADEON_NUM_VM 16
851
fa87e62d 852/* number of entries in page table */
4510fb98 853#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 854
1c01103c
AD		 855/* PTBs (Page Table Blocks) need to be aligned to 32K */
856#define RADEON_VM_PTB_ALIGN_SIZE 32768
857#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
858#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
859
24c16439
CK		 860#define R600_PTE_VALID (1 << 0)
861#define R600_PTE_SYSTEM (1 << 1)
862#define R600_PTE_SNOOPED (1 << 2)
863#define R600_PTE_READABLE (1 << 5)
864#define R600_PTE_WRITEABLE (1 << 6)
865
ec3dbbcb
CK		 866/* PTE (Page Table Entry) fragment field for different page sizes */
867#define R600_PTE_FRAG_4KB (0 << 7)
868#define R600_PTE_FRAG_64KB (4 << 7)
869#define R600_PTE_FRAG_256KB (6 << 7)
870
33fa9fe3
CK		 871/* flags needed to be set so we can copy directly from the GART table */
872#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
873 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 874
6d2f2944
CK		 875struct radeon_vm_pt {
876 struct radeon_bo *bo;
877 uint64_t addr;
878};
879
721604a1 880struct radeon_vm {
0aea5e4a 881 struct rb_root va;
ee60e29f 882 unsigned id;
90a51a32 883
e31ad969
CK		 884 /* BOs moved, but not yet updated in the PT */
885 struct list_head invalidated;
886
036bf46a
CK		 887 /* BOs freed, but not yet updated in the PT */
888 struct list_head freed;
889
90a51a32 890 /* contains the page directory */
6d2f2944 891 struct radeon_bo *page_directory;
90a51a32 892 uint64_t pd_gpu_addr;
6d2f2944 893 unsigned max_pde_used;
90a51a32
CK		 894
895 /* array of page tables, one for each page directory entry */
6d2f2944 896 struct radeon_vm_pt *page_tables;
90a51a32 897
cc9e67e3
CK		 898 struct radeon_bo_va *ib_bo_va;
899
721604a1
JG		 900 struct mutex mutex;
901 /* last fence for cs using this vm */
902 struct radeon_fence *fence;
9b40e5d8
CK		 903 /* last flush or NULL if we still need to flush */
904 struct radeon_fence *last_flush;
593b2635
CK		 905 /* last use of vmid */
906 struct radeon_fence *last_id_use;
721604a1
JG		 907};
908
721604a1 909struct radeon_vm_manager {
ee60e29f 910 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 911 uint32_t max_pfn;
721604a1
JG		 912 /* number of VMIDs */
913 unsigned nvm;
914 /* vram base address for page table entry */
915 u64 vram_base_offset;
67e915e4
AD		 916 /* is vm enabled? */
917 bool enabled;
721604a1
JG		 918};
919
920/*
921 * file private structure
922 */
923struct radeon_fpriv {
924 struct radeon_vm vm;
925};
926
d8f60cfc
AD		 927/*
928 * R6xx+ IH ring
929 */
930struct r600_ih {
4c788679 931 struct radeon_bo *ring_obj;
d8f60cfc
AD		 932 volatile uint32_t *ring;
933 unsigned rptr;
d8f60cfc
AD		 934 unsigned ring_size;
935 uint64_t gpu_addr;
d8f60cfc 936 uint32_t ptr_mask;
c20dc369 937 atomic_t lock;
d8f60cfc
AD		 938 bool enabled;
939};
940
347e7592 941/*
2948f5e6 942 * RLC stuff
347e7592 943 */
2948f5e6
AD		 944#include "clearstate_defs.h"
945
946struct radeon_rlc {
347e7592
AD		 947 /* for power gating */
948 struct radeon_bo *save_restore_obj;
949 uint64_t save_restore_gpu_addr;
2948f5e6 950 volatile uint32_t *sr_ptr;
1fd11777 951 const u32 *reg_list;
2948f5e6 952 u32 reg_list_size;
347e7592
AD		 953 /* for clear state */
954 struct radeon_bo *clear_state_obj;
955 uint64_t clear_state_gpu_addr;
2948f5e6 956 volatile uint32_t *cs_ptr;
1fd11777 957 const struct cs_section_def *cs_data;
22c775ce
AD		 958 u32 clear_state_size;
959 /* for cp tables */
960 struct radeon_bo *cp_table_obj;
961 uint64_t cp_table_gpu_addr;
962 volatile uint32_t *cp_table_ptr;
963 u32 cp_table_size;
347e7592
AD		 964};
965
69e130a6 966int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 967 struct radeon_ib *ib, struct radeon_vm *vm,
968 unsigned size);
f2e39221 969void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 970int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
971 struct radeon_ib *const_ib);
771fe6b9
JG		 972int radeon_ib_pool_init(struct radeon_device *rdev);
973void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 974int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 975/* Ring access between begin & end cannot sleep */
89d35807
AD		 976bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
977 struct radeon_ring *ring);
e32eb50d
CK		 978void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
979int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
980int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
981void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
982void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 983void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 984void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
985int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 986void radeon_ring_lockup_update(struct radeon_device *rdev,
987 struct radeon_ring *ring);
069211e5 988bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 989unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
990 uint32_t **data);
991int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
992 unsigned size, uint32_t *data);
e32eb50d 993int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 994 unsigned rptr_offs, u32 nop);
e32eb50d 995void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 996
997
4d75658b
AD		 998/* r600 async dma */
999void r600_dma_stop(struct radeon_device *rdev);
1000int r600_dma_resume(struct radeon_device *rdev);
1001void r600_dma_fini(struct radeon_device *rdev);
1002
8c5fd7ef
AD		 1003void cayman_dma_stop(struct radeon_device *rdev);
1004int cayman_dma_resume(struct radeon_device *rdev);
1005void cayman_dma_fini(struct radeon_device *rdev);
1006
771fe6b9
JG		 1007/*
1008 * CS.
1009 */
1010struct radeon_cs_reloc {
1011 struct drm_gem_object *gobj;
4c788679 1012 struct radeon_bo *robj;
df0af440
CK		 1013 struct ttm_validate_buffer tv;
1014 uint64_t gpu_offset;
ce6758c8
CK		 1015 unsigned prefered_domains;
1016 unsigned allowed_domains;
df0af440 1017 uint32_t tiling_flags;
771fe6b9 1018 uint32_t handle;
771fe6b9
JG		 1019};
1020
1021struct radeon_cs_chunk {
1022 uint32_t chunk_id;
1023 uint32_t length_dw;
1024 uint32_t *kdata;
721604a1 1025 void __user *user_ptr;
771fe6b9
JG		 1026};
1027
1028struct radeon_cs_parser {
c8c15ff1 1029 struct device *dev;
771fe6b9
JG		 1030 struct radeon_device *rdev;
1031 struct drm_file *filp;
1032 /* chunks */
1033 unsigned nchunks;
1034 struct radeon_cs_chunk *chunks;
1035 uint64_t *chunks_array;
1036 /* IB */
1037 unsigned idx;
1038 /* relocations */
1039 unsigned nrelocs;
1040 struct radeon_cs_reloc *relocs;
1041 struct radeon_cs_reloc **relocs_ptr;
df0af440 1042 struct radeon_cs_reloc *vm_bos;
771fe6b9 1043 struct list_head validated;
cf4ccd01 1044 unsigned dma_reloc_idx;
771fe6b9
JG		 1045 /* indices of various chunks */
1046 int chunk_ib_idx;
1047 int chunk_relocs_idx;
721604a1 1048 int chunk_flags_idx;
dfcf5f36 1049 int chunk_const_ib_idx;
f2e39221
JG		 1050 struct radeon_ib ib;
1051 struct radeon_ib const_ib;
771fe6b9 1052 void *track;
3ce0a23d 1053 unsigned family;
e70f224c 1054 int parser_error;
721604a1
JG		 1055 u32 cs_flags;
1056 u32 ring;
1057 s32 priority;
ecff665f 1058 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1059};
1060
28a326c5
ML		 1061static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1062{
1063 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1064
1065 if (ibc->kdata)
1066 return ibc->kdata[idx];
1067 return p->ib.ptr[idx];
1068}
1069
513bcb46 1070
771fe6b9
JG		 1071struct radeon_cs_packet {
1072 unsigned idx;
1073 unsigned type;
1074 unsigned reg;
1075 unsigned opcode;
1076 int count;
1077 unsigned one_reg_wr;
1078};
1079
1080typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1081 struct radeon_cs_packet *pkt,
1082 unsigned idx, unsigned reg);
1083typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1084 struct radeon_cs_packet *pkt);
1085
1086
1087/*
1088 * AGP
1089 */
1090int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1091void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1092void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1093void radeon_agp_fini(struct radeon_device *rdev);
1094
1095
1096/*
1097 * Writeback
1098 */
1099struct radeon_wb {
4c788679 1100 struct radeon_bo *wb_obj;
771fe6b9
JG		 1101 volatile uint32_t *wb;
1102 uint64_t gpu_addr;
724c80e1 1103 bool enabled;
d0f8a854 1104 bool use_event;
771fe6b9
JG		 1105};
1106
724c80e1 1107#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1108#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1109#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1110#define RADEON_WB_CP1_RPTR_OFFSET 1280
1111#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1112#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1113#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1114#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1115#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1116#define CIK_WB_CP1_WPTR_OFFSET 3328
1117#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1118
c93bb85b
JG		 1119/**
1120 * struct radeon_pm - power management datas
1121 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1122 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1123 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1124 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1125 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1126 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1127 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1128 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1129 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1130 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1131 * @needed_bandwidth: current bandwidth needs
1132 *
1133 * It keeps track of various data needed to take powermanagement decision.
25985edc 1134 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1135 * Equation between gpu/memory clock and available bandwidth is hw dependent
1136 * (type of memory, bus size, efficiency, ...)
1137 */
ce8f5370
AD		 1138
1139enum radeon_pm_method {
1140 PM_METHOD_PROFILE,
1141 PM_METHOD_DYNPM,
da321c8a 1142 PM_METHOD_DPM,
ce8f5370
AD		 1143};
1144
1145enum radeon_dynpm_state {
1146 DYNPM_STATE_DISABLED,
1147 DYNPM_STATE_MINIMUM,
1148 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1149 DYNPM_STATE_ACTIVE,
1150 DYNPM_STATE_SUSPENDED,
c913e23a 1151};
ce8f5370
AD		 1152enum radeon_dynpm_action {
1153 DYNPM_ACTION_NONE,
1154 DYNPM_ACTION_MINIMUM,
1155 DYNPM_ACTION_DOWNCLOCK,
1156 DYNPM_ACTION_UPCLOCK,
1157 DYNPM_ACTION_DEFAULT
c913e23a 1158};
56278a8e
AD		 1159
1160enum radeon_voltage_type {
1161 VOLTAGE_NONE = 0,
1162 VOLTAGE_GPIO,
1163 VOLTAGE_VDDC,
1164 VOLTAGE_SW
1165};
1166
0ec0e74f 1167enum radeon_pm_state_type {
da321c8a 1168 /* not used for dpm */
0ec0e74f
AD		 1169 POWER_STATE_TYPE_DEFAULT,
1170 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1171 /* user selectable states */
0ec0e74f
AD		 1172 POWER_STATE_TYPE_BATTERY,
1173 POWER_STATE_TYPE_BALANCED,
1174 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1175 /* internal states */
1176 POWER_STATE_TYPE_INTERNAL_UVD,
1177 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1178 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1179 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1180 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1181 POWER_STATE_TYPE_INTERNAL_BOOT,
1182 POWER_STATE_TYPE_INTERNAL_THERMAL,
1183 POWER_STATE_TYPE_INTERNAL_ACPI,
1184 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1185 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1186};
1187
ce8f5370
AD		 1188enum radeon_pm_profile_type {
1189 PM_PROFILE_DEFAULT,
1190 PM_PROFILE_AUTO,
1191 PM_PROFILE_LOW,
c9e75b21 1192 PM_PROFILE_MID,
ce8f5370
AD		 1193 PM_PROFILE_HIGH,
1194};
1195
1196#define PM_PROFILE_DEFAULT_IDX 0
1197#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1198#define PM_PROFILE_MID_SH_IDX 2
1199#define PM_PROFILE_HIGH_SH_IDX 3
1200#define PM_PROFILE_LOW_MH_IDX 4
1201#define PM_PROFILE_MID_MH_IDX 5
1202#define PM_PROFILE_HIGH_MH_IDX 6
1203#define PM_PROFILE_MAX 7
ce8f5370
AD		 1204
1205struct radeon_pm_profile {
1206 int dpms_off_ps_idx;
1207 int dpms_on_ps_idx;
1208 int dpms_off_cm_idx;
1209 int dpms_on_cm_idx;
516d0e46
AD		 1210};
1211
21a8122a
AD		 1212enum radeon_int_thermal_type {
1213 THERMAL_TYPE_NONE,
da321c8a
AD		 1214 THERMAL_TYPE_EXTERNAL,
1215 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1216 THERMAL_TYPE_RV6XX,
1217 THERMAL_TYPE_RV770,
da321c8a 1218 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1219 THERMAL_TYPE_EVERGREEN,
e33df25f 1220 THERMAL_TYPE_SUMO,
4fddba1f 1221 THERMAL_TYPE_NI,
14607d08 1222 THERMAL_TYPE_SI,
da321c8a 1223 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1224 THERMAL_TYPE_CI,
16fbe00d 1225 THERMAL_TYPE_KV,
21a8122a
AD		 1226};
1227
56278a8e
AD		 1228struct radeon_voltage {
1229 enum radeon_voltage_type type;
1230 /* gpio voltage */
1231 struct radeon_gpio_rec gpio;
1232 u32 delay; /* delay in usec from voltage drop to sclk change */
1233 bool active_high; /* voltage drop is active when bit is high */
1234 /* VDDC voltage */
1235 u8 vddc_id; /* index into vddc voltage table */
1236 u8 vddci_id; /* index into vddci voltage table */
1237 bool vddci_enabled;
1238 /* r6xx+ sw */
2feea49a
AD		 1239 u16 voltage;
1240 /* evergreen+ vddci */
1241 u16 vddci;
56278a8e
AD		 1242};
1243
d7311171
AD		 1244/* clock mode flags */
1245#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1246
56278a8e
AD		 1247struct radeon_pm_clock_info {
1248 /* memory clock */
1249 u32 mclk;
1250 /* engine clock */
1251 u32 sclk;
1252 /* voltage info */
1253 struct radeon_voltage voltage;
d7311171 1254 /* standardized clock flags */
56278a8e
AD		 1255 u32 flags;
1256};
1257
a48b9b4e 1258/* state flags */
d7311171 1259#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1260
56278a8e 1261struct radeon_power_state {
0ec0e74f 1262 enum radeon_pm_state_type type;
8f3f1c9a 1263 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1264 /* number of valid clock modes in this power state */
1265 int num_clock_modes;
56278a8e 1266 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1267 /* standardized state flags */
1268 u32 flags;
79daedc9
AD		 1269 u32 misc; /* vbios specific flags */
1270 u32 misc2; /* vbios specific flags */
1271 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1272};
1273
27459324
RM		 1274/*
1275 * Some modes are overclocked by very low value, accept them
1276 */
1277#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1278
2e9d4c05
AD		 1279enum radeon_dpm_auto_throttle_src {
1280 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1281 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1282};
1283
1284enum radeon_dpm_event_src {
1285 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1286 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1287 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1288 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1289 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1290};
1291
58bd2a88
AD		 1292#define RADEON_MAX_VCE_LEVELS 6
1293
b62d628b
AD		 1294enum radeon_vce_level {
1295 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1296 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1297 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1298 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1299 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1300 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1301};
1302
da321c8a
AD		 1303struct radeon_ps {
1304 u32 caps; /* vbios flags */
1305 u32 class; /* vbios flags */
1306 u32 class2; /* vbios flags */
1307 /* UVD clocks */
1308 u32 vclk;
1309 u32 dclk;
c4453e66
AD		 1310 /* VCE clocks */
1311 u32 evclk;
1312 u32 ecclk;
b62d628b
AD		 1313 bool vce_active;
1314 enum radeon_vce_level vce_level;
da321c8a
AD		 1315 /* asic priv */
1316 void *ps_priv;
1317};
1318
1319struct radeon_dpm_thermal {
1320 /* thermal interrupt work */
1321 struct work_struct work;
1322 /* low temperature threshold */
1323 int min_temp;
1324 /* high temperature threshold */
1325 int max_temp;
1326 /* was interrupt low to high or high to low */
1327 bool high_to_low;
1328};
1329
d22b7e40
AD		 1330enum radeon_clk_action
1331{
1332 RADEON_SCLK_UP = 1,
1333 RADEON_SCLK_DOWN
1334};
1335
1336struct radeon_blacklist_clocks
1337{
1338 u32 sclk;
1339 u32 mclk;
1340 enum radeon_clk_action action;
1341};
1342
61b7d601
AD		 1343struct radeon_clock_and_voltage_limits {
1344 u32 sclk;
1345 u32 mclk;
cdf6e805
AD		 1346 u16 vddc;
1347 u16 vddci;
61b7d601
AD		 1348};
1349
1350struct radeon_clock_array {
1351 u32 count;
1352 u32 *values;
1353};
1354
1355struct radeon_clock_voltage_dependency_entry {
1356 u32 clk;
1357 u16 v;
1358};
1359
1360struct radeon_clock_voltage_dependency_table {
1361 u32 count;
1362 struct radeon_clock_voltage_dependency_entry *entries;
1363};
1364
ef976ec4
AD		 1365union radeon_cac_leakage_entry {
1366 struct {
1367 u16 vddc;
1368 u32 leakage;
1369 };
1370 struct {
1371 u16 vddc1;
1372 u16 vddc2;
1373 u16 vddc3;
1374 };
61b7d601
AD		 1375};
1376
1377struct radeon_cac_leakage_table {
1378 u32 count;
ef976ec4 1379 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1380};
1381
929ee7a8
AD		 1382struct radeon_phase_shedding_limits_entry {
1383 u16 voltage;
1384 u32 sclk;
1385 u32 mclk;
1386};
1387
1388struct radeon_phase_shedding_limits_table {
1389 u32 count;
1390 struct radeon_phase_shedding_limits_entry *entries;
1391};
1392
84a9d9ee
AD		 1393struct radeon_uvd_clock_voltage_dependency_entry {
1394 u32 vclk;
1395 u32 dclk;
1396 u16 v;
1397};
1398
1399struct radeon_uvd_clock_voltage_dependency_table {
1400 u8 count;
1401 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1402};
1403
d29f013b
AD		 1404struct radeon_vce_clock_voltage_dependency_entry {
1405 u32 ecclk;
1406 u32 evclk;
1407 u16 v;
1408};
1409
1410struct radeon_vce_clock_voltage_dependency_table {
1411 u8 count;
1412 struct radeon_vce_clock_voltage_dependency_entry *entries;
1413};
1414
a5cb318e
AD		 1415struct radeon_ppm_table {
1416 u8 ppm_design;
1417 u16 cpu_core_number;
1418 u32 platform_tdp;
1419 u32 small_ac_platform_tdp;
1420 u32 platform_tdc;
1421 u32 small_ac_platform_tdc;
1422 u32 apu_tdp;
1423 u32 dgpu_tdp;
1424 u32 dgpu_ulv_power;
1425 u32 tj_max;
1426};
1427
58cb7632
AD		 1428struct radeon_cac_tdp_table {
1429 u16 tdp;
1430 u16 configurable_tdp;
1431 u16 tdc;
1432 u16 battery_power_limit;
1433 u16 small_power_limit;
1434 u16 low_cac_leakage;
1435 u16 high_cac_leakage;
1436 u16 maximum_power_delivery_limit;
1437};
1438
61b7d601
AD		 1439struct radeon_dpm_dynamic_state {
1440 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1441 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1442 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1443 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1444 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1445 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1446 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1447 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1448 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1449 struct radeon_clock_array valid_sclk_values;
1450 struct radeon_clock_array valid_mclk_values;
1451 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1452 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1453 u32 mclk_sclk_ratio;
1454 u32 sclk_mclk_delta;
1455 u16 vddc_vddci_delta;
1456 u16 min_vddc_for_pcie_gen2;
1457 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1458 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1459 struct radeon_ppm_table *ppm_table;
58cb7632 1460 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1461};
1462
1463struct radeon_dpm_fan {
1464 u16 t_min;
1465 u16 t_med;
1466 u16 t_high;
1467 u16 pwm_min;
1468 u16 pwm_med;
1469 u16 pwm_high;
1470 u8 t_hyst;
1471 u32 cycle_delay;
1472 u16 t_max;
1473 bool ucode_fan_control;
1474};
1475
32ce4652
AD		 1476enum radeon_pcie_gen {
1477 RADEON_PCIE_GEN1 = 0,
1478 RADEON_PCIE_GEN2 = 1,
1479 RADEON_PCIE_GEN3 = 2,
1480 RADEON_PCIE_GEN_INVALID = 0xffff
1481};
1482
70d01a5e
AD		 1483enum radeon_dpm_forced_level {
1484 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1485 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1486 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1487};
1488
58bd2a88
AD		 1489struct radeon_vce_state {
1490 /* vce clocks */
1491 u32 evclk;
1492 u32 ecclk;
1493 /* gpu clocks */
1494 u32 sclk;
1495 u32 mclk;
1496 u8 clk_idx;
1497 u8 pstate;
1498};
1499
da321c8a
AD		 1500struct radeon_dpm {
1501 struct radeon_ps *ps;
1502 /* number of valid power states */
1503 int num_ps;
1504 /* current power state that is active */
1505 struct radeon_ps *current_ps;
1506 /* requested power state */
1507 struct radeon_ps *requested_ps;
1508 /* boot up power state */
1509 struct radeon_ps *boot_ps;
1510 /* default uvd power state */
1511 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1512 /* vce requirements */
1513 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1514 enum radeon_vce_level vce_level;
da321c8a
AD		 1515 enum radeon_pm_state_type state;
1516 enum radeon_pm_state_type user_state;
1517 u32 platform_caps;
1518 u32 voltage_response_time;
1519 u32 backbias_response_time;
1520 void *priv;
1521 u32 new_active_crtcs;
1522 int new_active_crtc_count;
1523 u32 current_active_crtcs;
1524 int current_active_crtc_count;
61b7d601
AD		 1525 struct radeon_dpm_dynamic_state dyn_state;
1526 struct radeon_dpm_fan fan;
1527 u32 tdp_limit;
1528 u32 near_tdp_limit;
a9e61410 1529 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1530 u32 sq_ramping_threshold;
1531 u32 cac_leakage;
1532 u16 tdp_od_limit;
1533 u32 tdp_adjustment;
1534 u16 load_line_slope;
1535 bool power_control;
5ca302f7 1536 bool ac_power;
da321c8a
AD		 1537 /* special states active */
1538 bool thermal_active;
8a227555 1539 bool uvd_active;
b62d628b 1540 bool vce_active;
da321c8a
AD		 1541 /* thermal handling */
1542 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1543 /* forced levels */
1544 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1545 /* track UVD streams */
1546 unsigned sd;
1547 unsigned hd;
da321c8a
AD		 1548};
1549
ce3537d5 1550void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1551void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1552
c93bb85b 1553struct radeon_pm {
c913e23a 1554 struct mutex mutex;
db7fce39
CK		 1555 /* write locked while reprogramming mclk */
1556 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1557 u32 active_crtcs;
1558 int active_crtc_count;
c913e23a 1559 int req_vblank;
839461d3 1560 bool vblank_sync;
c93bb85b
JG		 1561 fixed20_12 max_bandwidth;
1562 fixed20_12 igp_sideport_mclk;
1563 fixed20_12 igp_system_mclk;
1564 fixed20_12 igp_ht_link_clk;
1565 fixed20_12 igp_ht_link_width;
1566 fixed20_12 k8_bandwidth;
1567 fixed20_12 sideport_bandwidth;
1568 fixed20_12 ht_bandwidth;
1569 fixed20_12 core_bandwidth;
1570 fixed20_12 sclk;
f47299c5 1571 fixed20_12 mclk;
c93bb85b 1572 fixed20_12 needed_bandwidth;
0975b162 1573 struct radeon_power_state *power_state;
56278a8e
AD		 1574 /* number of valid power states */
1575 int num_power_states;
a48b9b4e
AD		 1576 int current_power_state_index;
1577 int current_clock_mode_index;
1578 int requested_power_state_index;
1579 int requested_clock_mode_index;
1580 int default_power_state_index;
1581 u32 current_sclk;
1582 u32 current_mclk;
2feea49a
AD		 1583 u16 current_vddc;
1584 u16 current_vddci;
9ace9f7b
AD		 1585 u32 default_sclk;
1586 u32 default_mclk;
2feea49a
AD		 1587 u16 default_vddc;
1588 u16 default_vddci;
29fb52ca 1589 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1590 /* selected pm method */
1591 enum radeon_pm_method pm_method;
1592 /* dynpm power management */
1593 struct delayed_work dynpm_idle_work;
1594 enum radeon_dynpm_state dynpm_state;
1595 enum radeon_dynpm_action dynpm_planned_action;
1596 unsigned long dynpm_action_timeout;
1597 bool dynpm_can_upclock;
1598 bool dynpm_can_downclock;
1599 /* profile-based power management */
1600 enum radeon_pm_profile_type profile;
1601 int profile_index;
1602 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1603 /* internal thermal controller on rv6xx+ */
1604 enum radeon_int_thermal_type int_thermal_type;
1605 struct device *int_hwmon_dev;
da321c8a
AD		 1606 /* dpm */
1607 bool dpm_enabled;
1608 struct radeon_dpm dpm;
c93bb85b
JG		 1609};
1610
a4c9e2ee
AD		 1611int radeon_pm_get_type_index(struct radeon_device *rdev,
1612 enum radeon_pm_state_type ps_type,
1613 int instance);
f2ba57b5
CK		 1614/*
1615 * UVD
1616 */
1617#define RADEON_MAX_UVD_HANDLES 10
1618#define RADEON_UVD_STACK_SIZE (1024*1024)
1619#define RADEON_UVD_HEAP_SIZE (1024*1024)
1620
1621struct radeon_uvd {
1622 struct radeon_bo *vcpu_bo;
1623 void *cpu_addr;
1624 uint64_t gpu_addr;
9cc2e0e9 1625 void *saved_bo;
f2ba57b5
CK		 1626 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1627 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1628 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1629 struct delayed_work idle_work;
f2ba57b5
CK		 1630};
1631
1632int radeon_uvd_init(struct radeon_device *rdev);
1633void radeon_uvd_fini(struct radeon_device *rdev);
1634int radeon_uvd_suspend(struct radeon_device *rdev);
1635int radeon_uvd_resume(struct radeon_device *rdev);
1636int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1637 uint32_t handle, struct radeon_fence **fence);
1638int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1639 uint32_t handle, struct radeon_fence **fence);
1640void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1641void radeon_uvd_free_handles(struct radeon_device *rdev,
1642 struct drm_file *filp);
1643int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1644void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1645int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1646 unsigned vclk, unsigned dclk,
1647 unsigned vco_min, unsigned vco_max,
1648 unsigned fb_factor, unsigned fb_mask,
1649 unsigned pd_min, unsigned pd_max,
1650 unsigned pd_even,
1651 unsigned *optimal_fb_div,
1652 unsigned *optimal_vclk_div,
1653 unsigned *optimal_dclk_div);
1654int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1655 unsigned cg_upll_func_cntl);
771fe6b9 1656
d93f7937
CK		 1657/*
1658 * VCE
1659 */
1660#define RADEON_MAX_VCE_HANDLES 16
1661#define RADEON_VCE_STACK_SIZE (1024*1024)
1662#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1663
1664struct radeon_vce {
1665 struct radeon_bo *vcpu_bo;
d93f7937 1666 uint64_t gpu_addr;
98ccc291
CK		 1667 unsigned fw_version;
1668 unsigned fb_version;
d93f7937
CK		 1669 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1670 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1671 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1672 struct delayed_work idle_work;
d93f7937
CK		 1673};
1674
1675int radeon_vce_init(struct radeon_device *rdev);
1676void radeon_vce_fini(struct radeon_device *rdev);
1677int radeon_vce_suspend(struct radeon_device *rdev);
1678int radeon_vce_resume(struct radeon_device *rdev);
1679int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1680 uint32_t handle, struct radeon_fence **fence);
1681int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1682 uint32_t handle, struct radeon_fence **fence);
1683void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1684void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1685int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1686int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1687bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1688 struct radeon_ring *ring,
1689 struct radeon_semaphore *semaphore,
1690 bool emit_wait);
1691void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1692void radeon_vce_fence_emit(struct radeon_device *rdev,
1693 struct radeon_fence *fence);
1694int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1695int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1696
b530602f 1697struct r600_audio_pin {
a92553ab
RM		 1698 int channels;
1699 int rate;
1700 int bits_per_sample;
1701 u8 status_bits;
1702 u8 category_code;
b530602f
AD		 1703 u32 offset;
1704 bool connected;
1705 u32 id;
1706};
1707
1708struct r600_audio {
1709 bool enabled;
1710 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1711 int num_pins;
a92553ab
RM		 1712};
1713
771fe6b9
JG		 1714/*
1715 * Benchmarking
1716 */
638dd7db 1717void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1718
1719
ecc0b326
MD		 1720/*
1721 * Testing
1722 */
1723void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1724void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1725 struct radeon_ring *cpA,
1726 struct radeon_ring *cpB);
60a7e396 1727void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1728
1729
771fe6b9
JG		 1730/*
1731 * Debugfs
1732 */
4d8bf9ae
CK		 1733struct radeon_debugfs {
1734 struct drm_info_list *files;
1735 unsigned num_files;
1736};
1737
771fe6b9
JG		 1738int radeon_debugfs_add_files(struct radeon_device *rdev,
1739 struct drm_info_list *files,
1740 unsigned nfiles);
1741int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1742
76a0df85
CK		 1743/*
1744 * ASIC ring specific functions.
1745 */
1746struct radeon_asic_ring {
1747 /* ring read/write ptr handling */
1748 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1749 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1750 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1751
1752 /* validating and patching of IBs */
1753 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1754 int (*cs_parse)(struct radeon_cs_parser *p);
1755
1756 /* command emmit functions */
1757 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1758 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1759 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1760 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1761 struct radeon_semaphore *semaphore, bool emit_wait);
1762 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1763
1764 /* testing functions */
1765 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1766 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1767 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1768
1769 /* deprecated */
1770 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1771};
771fe6b9
JG		 1772
1773/*
1774 * ASIC specific functions.
1775 */
1776struct radeon_asic {
068a117c 1777 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1778 void (*fini)(struct radeon_device *rdev);
1779 int (*resume)(struct radeon_device *rdev);
1780 int (*suspend)(struct radeon_device *rdev);
28d52043 1781 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1782 int (*asic_reset)(struct radeon_device *rdev);
124764f1
MD		 1783 /* Flush the HDP cache via MMIO */
1784 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1785 /* check if 3D engine is idle */
1786 bool (*gui_idle)(struct radeon_device *rdev);
1787 /* wait for mc_idle */
1788 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1789 /* get the reference clock */
1790 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1791 /* get the gpu clock counter */
1792 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1793 /* gart */
c5b3b850
AD		 1794 struct {
1795 void (*tlb_flush)(struct radeon_device *rdev);
7f90fc96 1796 void (*set_page)(struct radeon_device *rdev, unsigned i,
77497f27 1797 uint64_t addr, uint32_t flags);
c5b3b850 1798 } gart;
05b07147
CK		 1799 struct {
1800 int (*init)(struct radeon_device *rdev);
1801 void (*fini)(struct radeon_device *rdev);
03f62abd
CK		 1802 void (*copy_pages)(struct radeon_device *rdev,
1803 struct radeon_ib *ib,
1804 uint64_t pe, uint64_t src,
1805 unsigned count);
1806 void (*write_pages)(struct radeon_device *rdev,
1807 struct radeon_ib *ib,
1808 uint64_t pe,
1809 uint64_t addr, unsigned count,
1810 uint32_t incr, uint32_t flags);
1811 void (*set_pages)(struct radeon_device *rdev,
1812 struct radeon_ib *ib,
1813 uint64_t pe,
1814 uint64_t addr, unsigned count,
1815 uint32_t incr, uint32_t flags);
1816 void (*pad_ib)(struct radeon_ib *ib);
05b07147 1817 } vm;
54e88e06 1818 /* ring specific callbacks */
76a0df85 1819 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1820 /* irqs */
b35ea4ab
AD		 1821 struct {
1822 int (*set)(struct radeon_device *rdev);
1823 int (*process)(struct radeon_device *rdev);
1824 } irq;
54e88e06 1825 /* displays */
c79a49ca
AD		 1826 struct {
1827 /* display watermarks */
1828 void (*bandwidth_update)(struct radeon_device *rdev);
1829 /* get frame count */
1830 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1831 /* wait for vblank */
1832 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1833 /* set backlight level */
1834 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1835 /* get backlight level */
1836 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1837 /* audio callbacks */
1838 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1839 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1840 } display;
54e88e06 1841 /* copy functions for bo handling */
27cd7769
AD		 1842 struct {
1843 int (*blit)(struct radeon_device *rdev,
1844 uint64_t src_offset,
1845 uint64_t dst_offset,
1846 unsigned num_gpu_pages,
876dc9f3 1847 struct radeon_fence **fence);
27cd7769
AD		 1848 u32 blit_ring_index;
1849 int (*dma)(struct radeon_device *rdev,
1850 uint64_t src_offset,
1851 uint64_t dst_offset,
1852 unsigned num_gpu_pages,
876dc9f3 1853 struct radeon_fence **fence);
27cd7769
AD		 1854 u32 dma_ring_index;
1855 /* method used for bo copy */
1856 int (*copy)(struct radeon_device *rdev,
1857 uint64_t src_offset,
1858 uint64_t dst_offset,
1859 unsigned num_gpu_pages,
876dc9f3 1860 struct radeon_fence **fence);
27cd7769
AD		 1861 /* ring used for bo copies */
1862 u32 copy_ring_index;
1863 } copy;
54e88e06 1864 /* surfaces */
9e6f3d02
AD		 1865 struct {
1866 int (*set_reg)(struct radeon_device *rdev, int reg,
1867 uint32_t tiling_flags, uint32_t pitch,
1868 uint32_t offset, uint32_t obj_size);
1869 void (*clear_reg)(struct radeon_device *rdev, int reg);
1870 } surface;
54e88e06 1871 /* hotplug detect */
901ea57d
AD		 1872 struct {
1873 void (*init)(struct radeon_device *rdev);
1874 void (*fini)(struct radeon_device *rdev);
1875 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1876 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1877 } hpd;
da321c8a 1878 /* static power management */
a02fa397
AD		 1879 struct {
1880 void (*misc)(struct radeon_device *rdev);
1881 void (*prepare)(struct radeon_device *rdev);
1882 void (*finish)(struct radeon_device *rdev);
1883 void (*init_profile)(struct radeon_device *rdev);
1884 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1885 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1886 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1887 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1888 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1889 int (*get_pcie_lanes)(struct radeon_device *rdev);
1890 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1891 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1892 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1893 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1894 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1895 } pm;
da321c8a
AD		 1896 /* dynamic power management */
1897 struct {
1898 int (*init)(struct radeon_device *rdev);
1899 void (*setup_asic)(struct radeon_device *rdev);
1900 int (*enable)(struct radeon_device *rdev);
914a8987 1901 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1902 void (*disable)(struct radeon_device *rdev);
84dd1928 1903 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1904 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1905 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1906 void (*display_configuration_changed)(struct radeon_device *rdev);
1907 void (*fini)(struct radeon_device *rdev);
1908 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1909 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1910 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1911 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1912 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1913 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1914 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1915 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1916 } dpm;
6f34be50 1917 /* pageflipping */
0f9e006c 1918 struct {
157fa14d
CK		 1919 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1920 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 1921 } pflip;
771fe6b9
JG		 1922};
1923
21f9a437
JG		 1924/*
1925 * Asic structures
1926 */
551ebd83 1927struct r100_asic {
225758d8
JG		 1928 const unsigned *reg_safe_bm;
1929 unsigned reg_safe_bm_size;
1930 u32 hdp_cntl;
551ebd83
DA		 1931};
1932
21f9a437 1933struct r300_asic {
225758d8
JG		 1934 const unsigned *reg_safe_bm;
1935 unsigned reg_safe_bm_size;
1936 u32 resync_scratch;
1937 u32 hdp_cntl;
21f9a437
JG		 1938};
1939
1940struct r600_asic {
225758d8
JG		 1941 unsigned max_pipes;
1942 unsigned max_tile_pipes;
1943 unsigned max_simds;
1944 unsigned max_backends;
1945 unsigned max_gprs;
1946 unsigned max_threads;
1947 unsigned max_stack_entries;
1948 unsigned max_hw_contexts;
1949 unsigned max_gs_threads;
1950 unsigned sx_max_export_size;
1951 unsigned sx_max_export_pos_size;
1952 unsigned sx_max_export_smx_size;
1953 unsigned sq_num_cf_insts;
1954 unsigned tiling_nbanks;
1955 unsigned tiling_npipes;
1956 unsigned tiling_group_size;
e7aeeba6 1957 unsigned tile_config;
e55b9422 1958 unsigned backend_map;
65fcf668 1959 unsigned active_simds;
21f9a437
JG		 1960};
1961
1962struct rv770_asic {
225758d8
JG		 1963 unsigned max_pipes;
1964 unsigned max_tile_pipes;
1965 unsigned max_simds;
1966 unsigned max_backends;
1967 unsigned max_gprs;
1968 unsigned max_threads;
1969 unsigned max_stack_entries;
1970 unsigned max_hw_contexts;
1971 unsigned max_gs_threads;
1972 unsigned sx_max_export_size;
1973 unsigned sx_max_export_pos_size;
1974 unsigned sx_max_export_smx_size;
1975 unsigned sq_num_cf_insts;
1976 unsigned sx_num_of_sets;
1977 unsigned sc_prim_fifo_size;
1978 unsigned sc_hiz_tile_fifo_size;
1979 unsigned sc_earlyz_tile_fifo_fize;
1980 unsigned tiling_nbanks;
1981 unsigned tiling_npipes;
1982 unsigned tiling_group_size;
e7aeeba6 1983 unsigned tile_config;
e55b9422 1984 unsigned backend_map;
65fcf668 1985 unsigned active_simds;
21f9a437
JG		 1986};
1987
32fcdbf4
AD		 1988struct evergreen_asic {
1989 unsigned num_ses;
1990 unsigned max_pipes;
1991 unsigned max_tile_pipes;
1992 unsigned max_simds;
1993 unsigned max_backends;
1994 unsigned max_gprs;
1995 unsigned max_threads;
1996 unsigned max_stack_entries;
1997 unsigned max_hw_contexts;
1998 unsigned max_gs_threads;
1999 unsigned sx_max_export_size;
2000 unsigned sx_max_export_pos_size;
2001 unsigned sx_max_export_smx_size;
2002 unsigned sq_num_cf_insts;
2003 unsigned sx_num_of_sets;
2004 unsigned sc_prim_fifo_size;
2005 unsigned sc_hiz_tile_fifo_size;
2006 unsigned sc_earlyz_tile_fifo_size;
2007 unsigned tiling_nbanks;
2008 unsigned tiling_npipes;
2009 unsigned tiling_group_size;
e7aeeba6 2010 unsigned tile_config;
e55b9422 2011 unsigned backend_map;
65fcf668 2012 unsigned active_simds;
32fcdbf4
AD		 2013};
2014
fecf1d07
AD		 2015struct cayman_asic {
2016 unsigned max_shader_engines;
2017 unsigned max_pipes_per_simd;
2018 unsigned max_tile_pipes;
2019 unsigned max_simds_per_se;
2020 unsigned max_backends_per_se;
2021 unsigned max_texture_channel_caches;
2022 unsigned max_gprs;
2023 unsigned max_threads;
2024 unsigned max_gs_threads;
2025 unsigned max_stack_entries;
2026 unsigned sx_num_of_sets;
2027 unsigned sx_max_export_size;
2028 unsigned sx_max_export_pos_size;
2029 unsigned sx_max_export_smx_size;
2030 unsigned max_hw_contexts;
2031 unsigned sq_num_cf_insts;
2032 unsigned sc_prim_fifo_size;
2033 unsigned sc_hiz_tile_fifo_size;
2034 unsigned sc_earlyz_tile_fifo_size;
2035
2036 unsigned num_shader_engines;
2037 unsigned num_shader_pipes_per_simd;
2038 unsigned num_tile_pipes;
2039 unsigned num_simds_per_se;
2040 unsigned num_backends_per_se;
2041 unsigned backend_disable_mask_per_asic;
2042 unsigned backend_map;
2043 unsigned num_texture_channel_caches;
2044 unsigned mem_max_burst_length_bytes;
2045 unsigned mem_row_size_in_kb;
2046 unsigned shader_engine_tile_size;
2047 unsigned num_gpus;
2048 unsigned multi_gpu_tile_size;
2049
2050 unsigned tile_config;
65fcf668 2051 unsigned active_simds;
fecf1d07
AD		 2052};
2053
0a96d72b
AD		 2054struct si_asic {
2055 unsigned max_shader_engines;
0a96d72b 2056 unsigned max_tile_pipes;
1a8ca750
AD		 2057 unsigned max_cu_per_sh;
2058 unsigned max_sh_per_se;
0a96d72b
AD		 2059 unsigned max_backends_per_se;
2060 unsigned max_texture_channel_caches;
2061 unsigned max_gprs;
2062 unsigned max_gs_threads;
2063 unsigned max_hw_contexts;
2064 unsigned sc_prim_fifo_size_frontend;
2065 unsigned sc_prim_fifo_size_backend;
2066 unsigned sc_hiz_tile_fifo_size;
2067 unsigned sc_earlyz_tile_fifo_size;
2068
0a96d72b 2069 unsigned num_tile_pipes;
439a1cff 2070 unsigned backend_enable_mask;
0a96d72b
AD		 2071 unsigned backend_disable_mask_per_asic;
2072 unsigned backend_map;
2073 unsigned num_texture_channel_caches;
2074 unsigned mem_max_burst_length_bytes;
2075 unsigned mem_row_size_in_kb;
2076 unsigned shader_engine_tile_size;
2077 unsigned num_gpus;
2078 unsigned multi_gpu_tile_size;
2079
2080 unsigned tile_config;
64d7b8be 2081 uint32_t tile_mode_array[32];
65fcf668 2082 uint32_t active_cus;
0a96d72b
AD		 2083};
2084
8cc1a532
AD		 2085struct cik_asic {
2086 unsigned max_shader_engines;
2087 unsigned max_tile_pipes;
2088 unsigned max_cu_per_sh;
2089 unsigned max_sh_per_se;
2090 unsigned max_backends_per_se;
2091 unsigned max_texture_channel_caches;
2092 unsigned max_gprs;
2093 unsigned max_gs_threads;
2094 unsigned max_hw_contexts;
2095 unsigned sc_prim_fifo_size_frontend;
2096 unsigned sc_prim_fifo_size_backend;
2097 unsigned sc_hiz_tile_fifo_size;
2098 unsigned sc_earlyz_tile_fifo_size;
2099
2100 unsigned num_tile_pipes;
439a1cff 2101 unsigned backend_enable_mask;
8cc1a532
AD		 2102 unsigned backend_disable_mask_per_asic;
2103 unsigned backend_map;
2104 unsigned num_texture_channel_caches;
2105 unsigned mem_max_burst_length_bytes;
2106 unsigned mem_row_size_in_kb;
2107 unsigned shader_engine_tile_size;
2108 unsigned num_gpus;
2109 unsigned multi_gpu_tile_size;
2110
2111 unsigned tile_config;
39aee490 2112 uint32_t tile_mode_array[32];
32f79a8a 2113 uint32_t macrotile_mode_array[16];
65fcf668 2114 uint32_t active_cus;
8cc1a532
AD		 2115};
2116
068a117c
JG		 2117union radeon_asic_config {
2118 struct r300_asic r300;
551ebd83 2119 struct r100_asic r100;
3ce0a23d
JG		 2120 struct r600_asic r600;
2121 struct rv770_asic rv770;
32fcdbf4 2122 struct evergreen_asic evergreen;
fecf1d07 2123 struct cayman_asic cayman;
0a96d72b 2124 struct si_asic si;
8cc1a532 2125 struct cik_asic cik;
068a117c
JG		 2126};
2127
0a10c851
DV		 2128/*
2129 * asic initizalization from radeon_asic.c
2130 */
2131void radeon_agp_disable(struct radeon_device *rdev);
2132int radeon_asic_init(struct radeon_device *rdev);
2133
771fe6b9
JG		 2134
2135/*
2136 * IOCTL.
2137 */
2138int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2139 struct drm_file *filp);
2140int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2141 struct drm_file *filp);
2142int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2143 struct drm_file *file_priv);
2144int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2145 struct drm_file *file_priv);
2146int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2147 struct drm_file *file_priv);
2148int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2149 struct drm_file *file_priv);
2150int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2151 struct drm_file *filp);
2152int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2153 struct drm_file *filp);
2154int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2155 struct drm_file *filp);
2156int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2157 struct drm_file *filp);
721604a1
JG		 2158int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2159 struct drm_file *filp);
bda72d58
MO		 2160int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2161 struct drm_file *filp);
771fe6b9 2162int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2163int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *filp);
2165int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2166 struct drm_file *filp);
771fe6b9 2167
16cdf04d
AD		 2168/* VRAM scratch page for HDP bug, default vram page */
2169struct r600_vram_scratch {
87cbf8f2
AD		 2170 struct radeon_bo *robj;
2171 volatile uint32_t *ptr;
16cdf04d 2172 u64 gpu_addr;
87cbf8f2 2173};
771fe6b9 2174
fd64ca8a
LT		 2175/*
2176 * ACPI
2177 */
2178struct radeon_atif_notification_cfg {
2179 bool enabled;
2180 int command_code;
2181};
2182
2183struct radeon_atif_notifications {
2184 bool display_switch;
2185 bool expansion_mode_change;
2186 bool thermal_state;
2187 bool forced_power_state;
2188 bool system_power_state;
2189 bool display_conf_change;
2190 bool px_gfx_switch;
2191 bool brightness_change;
2192 bool dgpu_display_event;
2193};
2194
2195struct radeon_atif_functions {
2196 bool system_params;
2197 bool sbios_requests;
2198 bool select_active_disp;
2199 bool lid_state;
2200 bool get_tv_standard;
2201 bool set_tv_standard;
2202 bool get_panel_expansion_mode;
2203 bool set_panel_expansion_mode;
2204 bool temperature_change;
2205 bool graphics_device_types;
2206};
2207
2208struct radeon_atif {
2209 struct radeon_atif_notifications notifications;
2210 struct radeon_atif_functions functions;
2211 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2212 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2213};
7a1619b9 2214
e3a15920
AD		 2215struct radeon_atcs_functions {
2216 bool get_ext_state;
2217 bool pcie_perf_req;
2218 bool pcie_dev_rdy;
2219 bool pcie_bus_width;
2220};
2221
2222struct radeon_atcs {
2223 struct radeon_atcs_functions functions;
2224};
2225
771fe6b9
JG		 2226/*
2227 * Core structure, functions and helpers.
2228 */
2229typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2230typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2231
2232struct radeon_device {
9f022ddf 2233 struct device *dev;
771fe6b9
JG		 2234 struct drm_device *ddev;
2235 struct pci_dev *pdev;
dee53e7f 2236 struct rw_semaphore exclusive_lock;
771fe6b9 2237 /* ASIC */
068a117c 2238 union radeon_asic_config config;
771fe6b9
JG		 2239 enum radeon_family family;
2240 unsigned long flags;
2241 int usec_timeout;
2242 enum radeon_pll_errata pll_errata;
2243 int num_gb_pipes;
f779b3e5 2244 int num_z_pipes;
771fe6b9
JG		 2245 int disp_priority;
2246 /* BIOS */
2247 uint8_t *bios;
2248 bool is_atom_bios;
2249 uint16_t bios_header_start;
4c788679 2250 struct radeon_bo *stollen_vga_memory;
771fe6b9 2251 /* Register mmio */
4c9bc75c
DA		 2252 resource_size_t rmmio_base;
2253 resource_size_t rmmio_size;
2c385151
DV		 2254 /* protects concurrent MM_INDEX/DATA based register access */
2255 spinlock_t mmio_idx_lock;
fe78118c
AD		 2256 /* protects concurrent SMC based register access */
2257 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2258 /* protects concurrent PLL register access */
2259 spinlock_t pll_idx_lock;
2260 /* protects concurrent MC register access */
2261 spinlock_t mc_idx_lock;
2262 /* protects concurrent PCIE register access */
2263 spinlock_t pcie_idx_lock;
2264 /* protects concurrent PCIE_PORT register access */
2265 spinlock_t pciep_idx_lock;
2266 /* protects concurrent PIF register access */
2267 spinlock_t pif_idx_lock;
2268 /* protects concurrent CG register access */
2269 spinlock_t cg_idx_lock;
2270 /* protects concurrent UVD register access */
2271 spinlock_t uvd_idx_lock;
2272 /* protects concurrent RCU register access */
2273 spinlock_t rcu_idx_lock;
2274 /* protects concurrent DIDT register access */
2275 spinlock_t didt_idx_lock;
2276 /* protects concurrent ENDPOINT (audio) register access */
2277 spinlock_t end_idx_lock;
a0533fbf 2278 void __iomem *rmmio;
771fe6b9
JG		 2279 radeon_rreg_t mc_rreg;
2280 radeon_wreg_t mc_wreg;
2281 radeon_rreg_t pll_rreg;
2282 radeon_wreg_t pll_wreg;
de1b2898 2283 uint32_t pcie_reg_mask;
771fe6b9
JG		 2284 radeon_rreg_t pciep_rreg;
2285 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2286 /* io port */
2287 void __iomem *rio_mem;
2288 resource_size_t rio_mem_size;
771fe6b9
JG		 2289 struct radeon_clock clock;
2290 struct radeon_mc mc;
2291 struct radeon_gart gart;
2292 struct radeon_mode_info mode_info;
2293 struct radeon_scratch scratch;
75efdee1 2294 struct radeon_doorbell doorbell;
771fe6b9 2295 struct radeon_mman mman;
7465280c 2296 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2297 wait_queue_head_t fence_queue;
d6999bc7 2298 struct mutex ring_lock;
e32eb50d 2299 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2300 bool ib_pool_ready;
2301 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2302 struct radeon_irq irq;
2303 struct radeon_asic *asic;
2304 struct radeon_gem gem;
c93bb85b 2305 struct radeon_pm pm;
f2ba57b5 2306 struct radeon_uvd uvd;
d93f7937 2307 struct radeon_vce vce;
f657c2a7 2308 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2309 struct radeon_wb wb;
3ce0a23d 2310 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2311 bool shutdown;
2312 bool suspend;
ad49f501 2313 bool need_dma32;
733289c2 2314 bool accel_working;
a0a53aa8 2315 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2316 bool needs_reset;
e024e110 2317 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2318 const struct firmware *me_fw; /* all family ME firmware */
2319 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2320 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2321 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2322 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2323 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2324 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2325 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2326 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2327 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2328 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2329 bool new_fw;
16cdf04d 2330 struct r600_vram_scratch vram_scratch;
3e5cb98d 2331 int msi_enabled; /* msi enabled */
d8f60cfc 2332 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2333 struct radeon_rlc rlc;
963e81f9 2334 struct radeon_mec mec;
d4877cf2 2335 struct work_struct hotplug_work;
f122c610 2336 struct work_struct audio_work;
8f61b34c 2337 struct work_struct reset_work;
18917b60 2338 int num_crtc; /* number of crtcs */
40bacf16 2339 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2340 bool has_uvd;
b530602f 2341 struct r600_audio audio; /* audio stuff */
ce8f5370 2342 struct notifier_block acpi_nb;
9eba4a93 2343 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2344 struct drm_file *hyperz_filp;
9eba4a93 2345 struct drm_file *cmask_filp;
f376b94f
AD		 2346 /* i2c buses */
2347 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2348 /* debugfs */
2349 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2350 unsigned debugfs_count;
721604a1
JG		 2351 /* virtual memory */
2352 struct radeon_vm_manager vm_manager;
6759a0a7 2353 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2354 /* memory stats */
2355 atomic64_t vram_usage;
2356 atomic64_t gtt_usage;
2357 atomic64_t num_bytes_moved;
fd64ca8a
LT		 2358 /* ACPI interface */
2359 struct radeon_atif atif;
e3a15920 2360 struct radeon_atcs atcs;
f61d5b46
AD		 2361 /* srbm instance registers */
2362 struct mutex srbm_mutex;
64d8a728
AD		 2363 /* clock, powergating flags */
2364 u32 cg_flags;
2365 u32 pg_flags;
10ebc0bc
DA		 2366
2367 struct dev_pm_domain vga_pm_domain;
2368 bool have_disp_power_ref;
4807c5a8 2369 u32 px_quirk_flags;
71ecc97e
AD		 2370
2371 /* tracking pinned memory */
2372 u64 vram_pin_size;
2373 u64 gart_pin_size;
771fe6b9
JG		 2374};
2375
90c4cde9 2376bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2377int radeon_device_init(struct radeon_device *rdev,
2378 struct drm_device *ddev,
2379 struct pci_dev *pdev,
2380 uint32_t flags);
2381void radeon_device_fini(struct radeon_device *rdev);
2382int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2383
59bc1d89
LK		 2384#define RADEON_MIN_MMIO_SIZE 0x10000
2385
2386static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2387 bool always_indirect)
2388{
2389 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2390 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2391 return readl(((void __iomem *)rdev->rmmio) + reg);
2392 else {
2393 unsigned long flags;
2394 uint32_t ret;
2395
2396 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2397 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2398 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2399 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2400
2401 return ret;
2402 }
2403}
2404
2405static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2406 bool always_indirect)
2407{
2408 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2409 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2410 else {
2411 unsigned long flags;
2412
2413 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2414 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2415 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2416 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2417 }
2418}
2419
6fcbef7a
AK		 2420u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2421void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2422
d5754ab8
AL		 2423u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2424void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2425
4c788679
JG		 2426/*
2427 * Cast helper
2428 */
2429#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2430
2431/*
2432 * Registers read & write functions.
2433 */
a0533fbf
BH		 2434#define RREG8(reg) readb((rdev->rmmio) + (reg))
2435#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2436#define RREG16(reg) readw((rdev->rmmio) + (reg))
2437#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2438#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2439#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2440#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2441#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2442#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2443#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2444#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2445#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2446#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2447#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2448#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2449#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2450#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2451#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2452#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2453#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2454#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2455#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2456#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2457#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2458#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2459#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2460#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2461#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2462#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2463#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2464#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2465#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2466#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2467#define WREG32_P(reg, val, mask) \
2468 do { \
2469 uint32_t tmp_ = RREG32(reg); \
2470 tmp_ &= (mask); \
2471 tmp_ |= ((val) & ~(mask)); \
2472 WREG32(reg, tmp_); \
2473 } while (0)
d5169fc4 2474#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2475#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2476#define WREG32_PLL_P(reg, val, mask) \
2477 do { \
2478 uint32_t tmp_ = RREG32_PLL(reg); \
2479 tmp_ &= (mask); \
2480 tmp_ |= ((val) & ~(mask)); \
2481 WREG32_PLL(reg, tmp_); \
2482 } while (0)
2ef9bdfe 2483#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2484#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2485#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2486
d5754ab8
AL		 2487#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2488#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2489
de1b2898
DA		 2490/*
2491 * Indirect registers accessor
2492 */
2493static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2494{
0a5b7b0b 2495 unsigned long flags;
de1b2898
DA		 2496 uint32_t r;
2497
0a5b7b0b 2498 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2499 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2500 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2501 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2502 return r;
2503}
2504
2505static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2506{
0a5b7b0b
AD		 2507 unsigned long flags;
2508
2509 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2510 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2511 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2512 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2513}
2514
1d5d0c34
AD		 2515static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2516{
fe78118c 2517 unsigned long flags;
1d5d0c34
AD		 2518 u32 r;
2519
fe78118c 2520 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2521 WREG32(TN_SMC_IND_INDEX_0, (reg));
2522 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2523 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2524 return r;
2525}
2526
2527static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2528{
fe78118c
AD		 2529 unsigned long flags;
2530
2531 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2532 WREG32(TN_SMC_IND_INDEX_0, (reg));
2533 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2534 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2535}
2536
ff82bbc4
AD		 2537static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2538{
0a5b7b0b 2539 unsigned long flags;
ff82bbc4
AD		 2540 u32 r;
2541
0a5b7b0b 2542 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2543 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2544 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2545 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2546 return r;
2547}
2548
2549static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2550{
0a5b7b0b
AD		 2551 unsigned long flags;
2552
2553 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2554 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2555 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2556 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2557}
2558
46f9564a
AD		 2559static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2560{
0a5b7b0b 2561 unsigned long flags;
46f9564a
AD		 2562 u32 r;
2563
0a5b7b0b 2564 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2565 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2566 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2567 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2568 return r;
2569}
2570
2571static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2572{
0a5b7b0b
AD		 2573 unsigned long flags;
2574
2575 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2576 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2577 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2578 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2579}
2580
792edd69
AD		 2581static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2582{
0a5b7b0b 2583 unsigned long flags;
792edd69
AD		 2584 u32 r;
2585
0a5b7b0b 2586 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2587 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2588 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2589 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2590 return r;
2591}
2592
2593static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2594{
0a5b7b0b
AD		 2595 unsigned long flags;
2596
2597 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2598 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2599 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2600 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2601}
2602
2603static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2604{
0a5b7b0b 2605 unsigned long flags;
792edd69
AD		 2606 u32 r;
2607
0a5b7b0b 2608 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2609 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2610 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2611 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2612 return r;
2613}
2614
2615static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2616{
0a5b7b0b
AD		 2617 unsigned long flags;
2618
2619 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2620 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2621 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2622 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2623}
2624
93656cdd
AD		 2625static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2626{
0a5b7b0b 2627 unsigned long flags;
93656cdd
AD		 2628 u32 r;
2629
0a5b7b0b 2630 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2631 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2632 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2633 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2634 return r;
2635}
2636
2637static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2638{
0a5b7b0b
AD		 2639 unsigned long flags;
2640
2641 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2642 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2643 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2644 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2645}
2646
1d58234d
AD		 2647
2648static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2649{
0a5b7b0b 2650 unsigned long flags;
1d58234d
AD		 2651 u32 r;
2652
0a5b7b0b 2653 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2654 WREG32(CIK_DIDT_IND_INDEX, (reg));
2655 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2656 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2657 return r;
2658}
2659
2660static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2661{
0a5b7b0b
AD		 2662 unsigned long flags;
2663
2664 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2665 WREG32(CIK_DIDT_IND_INDEX, (reg));
2666 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2667 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2668}
2669
771fe6b9
JG		 2670void r100_pll_errata_after_index(struct radeon_device *rdev);
2671
2672
2673/*
2674 * ASICs helpers.
2675 */
b995e433
DA		 2676#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2677 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2678#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2679 (rdev->family == CHIP_RV200) || \
2680 (rdev->family == CHIP_RS100) || \
2681 (rdev->family == CHIP_RS200) || \
2682 (rdev->family == CHIP_RV250) || \
2683 (rdev->family == CHIP_RV280) || \
2684 (rdev->family == CHIP_RS300))
2685#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2686 (rdev->family == CHIP_RV350) || \
2687 (rdev->family == CHIP_R350) || \
2688 (rdev->family == CHIP_RV380) || \
2689 (rdev->family == CHIP_R420) || \
2690 (rdev->family == CHIP_R423) || \
2691 (rdev->family == CHIP_RV410) || \
2692 (rdev->family == CHIP_RS400) || \
2693 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2694#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2695 (rdev->ddev->pdev->device == 0x9443) || \
2696 (rdev->ddev->pdev->device == 0x944B) || \
2697 (rdev->ddev->pdev->device == 0x9506) || \
2698 (rdev->ddev->pdev->device == 0x9509) || \
2699 (rdev->ddev->pdev->device == 0x950F) || \
2700 (rdev->ddev->pdev->device == 0x689C) || \
2701 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2702#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2703#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2704 (rdev->family == CHIP_RS690) || \
2705 (rdev->family == CHIP_RS740) || \
2706 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2707#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2708#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2709#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2710#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2711 (rdev->flags & RADEON_IS_IGP))
1fe18305 2712#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2713#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2714#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2715 (rdev->flags & RADEON_IS_IGP))
624d3524 2716#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2717#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2718#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2719#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2720#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2721#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2722 (rdev->family == CHIP_MULLINS))
771fe6b9 2723
dc50ba7f
AD		 2724#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2725 (rdev->ddev->pdev->device == 0x6850) || \
2726 (rdev->ddev->pdev->device == 0x6858) || \
2727 (rdev->ddev->pdev->device == 0x6859) || \
2728 (rdev->ddev->pdev->device == 0x6840) || \
2729 (rdev->ddev->pdev->device == 0x6841) || \
2730 (rdev->ddev->pdev->device == 0x6842) || \
2731 (rdev->ddev->pdev->device == 0x6843))
2732
771fe6b9
JG		 2733/*
2734 * BIOS helpers.
2735 */
2736#define RBIOS8(i) (rdev->bios[i])
2737#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2738#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2739
2740int radeon_combios_init(struct radeon_device *rdev);
2741void radeon_combios_fini(struct radeon_device *rdev);
2742int radeon_atombios_init(struct radeon_device *rdev);
2743void radeon_atombios_fini(struct radeon_device *rdev);
2744
2745
2746/*
2747 * RING helpers.
2748 */
ce580fab 2749#if DRM_DEBUG_CODE == 0
e32eb50d 2750static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2751{
e32eb50d
CK		 2752 ring->ring[ring->wptr++] = v;
2753 ring->wptr &= ring->ptr_mask;
2754 ring->count_dw--;
2755 ring->ring_free_dw--;
771fe6b9 2756}
ce580fab
AK		 2757#else
2758/* With debugging this is just too big to inline */
e32eb50d 2759void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2760#endif
771fe6b9
JG		 2761
2762/*
2763 * ASICs macro.
2764 */
068a117c 2765#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2766#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2767#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2768#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2769#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2770#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2771#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850 2772#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
77497f27 2773#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
05b07147
CK		 2774#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2775#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
03f62abd
CK		 2776#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2777#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2778#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2779#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
76a0df85
CK		 2780#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2781#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2782#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2783#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2784#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2785#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2786#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2787#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2788#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2789#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2790#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2791#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2792#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2793#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2794#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2795#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2796#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2797#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2798#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2799#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2800#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2801#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2802#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2803#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2804#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2805#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2806#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2807#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2808#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2809#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2810#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2811#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2812#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2813#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2814#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2815#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2816#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2817#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2818#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2819#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2820#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2821#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2822#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2823#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2824#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2825#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2826#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2827#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2828#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2829#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2830#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2831#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2832#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2833#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2834#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2835#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2836#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2837#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2838#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2839#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2840#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2841#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2842#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2843#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2844#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2845#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2846#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2847#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2848#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2849#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2850#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2851#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2852
6cf8a3f5 2853/* Common functions */
700a0cc0 2854/* AGP */
90aca4d2 2855extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2856extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2857extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2858extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2859extern int radeon_modeset_init(struct radeon_device *rdev);
2860extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2861extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2862extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2863extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2864extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2865extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2866extern void radeon_wb_fini(struct radeon_device *rdev);
2867extern int radeon_wb_init(struct radeon_device *rdev);
2868extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2869extern void radeon_surface_init(struct radeon_device *rdev);
2870extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2871extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2872extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2873extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2874extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2875extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2876extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2877extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2878extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2879extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2880extern void radeon_program_register_sequence(struct radeon_device *rdev,
2881 const u32 *registers,
2882 const u32 array_size);
6cf8a3f5 2883
721604a1
JG		 2884/*
2885 * vm
2886 */
2887int radeon_vm_manager_init(struct radeon_device *rdev);
2888void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2889int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2890void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
df0af440
CK		 2891struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2892 struct radeon_vm *vm,
2893 struct list_head *head);
ee60e29f
CK		 2894struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2895 struct radeon_vm *vm, int ring);
fa688343
CK		 2896void radeon_vm_flush(struct radeon_device *rdev,
2897 struct radeon_vm *vm,
2898 int ring);
ee60e29f
CK		 2899void radeon_vm_fence(struct radeon_device *rdev,
2900 struct radeon_vm *vm,
2901 struct radeon_fence *fence);
dce34bfd 2902uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2903int radeon_vm_update_page_directory(struct radeon_device *rdev,
2904 struct radeon_vm *vm);
036bf46a
CK		 2905int radeon_vm_clear_freed(struct radeon_device *rdev,
2906 struct radeon_vm *vm);
e31ad969
CK		 2907int radeon_vm_clear_invalids(struct radeon_device *rdev,
2908 struct radeon_vm *vm);
9c57a6bd 2909int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 2910 struct radeon_bo_va *bo_va,
9c57a6bd 2911 struct ttm_mem_reg *mem);
721604a1
JG		 2912void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2913 struct radeon_bo *bo);
421ca7ab
CK		 2914struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2915 struct radeon_bo *bo);
e971bd5e
CK		 2916struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2917 struct radeon_vm *vm,
2918 struct radeon_bo *bo);
2919int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2920 struct radeon_bo_va *bo_va,
2921 uint64_t offset,
2922 uint32_t flags);
036bf46a
CK		 2923void radeon_vm_bo_rmv(struct radeon_device *rdev,
2924 struct radeon_bo_va *bo_va);
721604a1 2925
f122c610
AD		 2926/* audio */
2927void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2928struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2929struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2930void r600_audio_enable(struct radeon_device *rdev,
2931 struct r600_audio_pin *pin,
2932 bool enable);
2933void dce6_audio_enable(struct radeon_device *rdev,
2934 struct r600_audio_pin *pin,
2935 bool enable);
721604a1 2936
16cdf04d
AD		 2937/*
2938 * R600 vram scratch functions
2939 */
2940int r600_vram_scratch_init(struct radeon_device *rdev);
2941void r600_vram_scratch_fini(struct radeon_device *rdev);
2942
285484e2
JG		 2943/*
2944 * r600 cs checking helper
2945 */
2946unsigned r600_mip_minify(unsigned size, unsigned level);
2947bool r600_fmt_is_valid_color(u32 format);
2948bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2949int r600_fmt_get_blocksize(u32 format);
2950int r600_fmt_get_nblocksx(u32 format, u32 w);
2951int r600_fmt_get_nblocksy(u32 format, u32 h);
2952
3574dda4
DV		 2953/*
2954 * r600 functions used by radeon_encoder.c
2955 */
1b688d08
RM		 2956struct radeon_hdmi_acr {
2957 u32 clock;
2958
2959 int n_32khz;
2960 int cts_32khz;
2961
2962 int n_44_1khz;
2963 int cts_44_1khz;
2964
2965 int n_48khz;
2966 int cts_48khz;
2967
2968};
2969
e55d3e6c
RM		 2970extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2971
416a2bd2
AD		 2972extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2973 u32 tiling_pipe_num,
2974 u32 max_rb_num,
2975 u32 total_max_rb_num,
2976 u32 enabled_rb_mask);
fe251e2f 2977
e55d3e6c
RM		 2978/*
2979 * evergreen functions used by radeon_encoder.c
2980 */
2981
0af62b01 2982extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2983extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2984
c4917074
AD		 2985/* radeon_acpi.c */
2986#if defined(CONFIG_ACPI)
2987extern int radeon_acpi_init(struct radeon_device *rdev);
2988extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2989extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2990extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2991 u8 perf_req, bool advertise);
dc50ba7f 2992extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2993#else
2994static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2995static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2996#endif
d7a2952f 2997
c38f34b5
IH		 2998int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2999 struct radeon_cs_packet *pkt,
3000 unsigned idx);
9ffb7a6d 3001bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 3002void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3003 struct radeon_cs_packet *pkt);
e9716993
IH		 3004int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3005 struct radeon_cs_reloc **cs_reloc,
3006 int nomm);
40592a17
IH		 3007int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3008 uint32_t *vline_start_end,
3009 uint32_t *vline_status);
c38f34b5 3010
4c788679
JG		 3011#include "radeon_object.h"
3012
771fe6b9 3013#endif
Linux 6.x block layer and io_uring tree(s)