Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
771fe6b9 JG |
63 | #include <asm/atomic.h> |
64 | #include <linux/wait.h> | |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
147666fb | 72 | #include <ttm/ttm_execbuf_util.h> |
4c788679 | 73 | |
c2142715 | 74 | #include "radeon_family.h" |
771fe6b9 JG |
75 | #include "radeon_mode.h" |
76 | #include "radeon_reg.h" | |
771fe6b9 JG |
77 | |
78 | /* | |
79 | * Modules parameters. | |
80 | */ | |
81 | extern int radeon_no_wb; | |
82 | extern int radeon_modeset; | |
83 | extern int radeon_dynclks; | |
84 | extern int radeon_r4xx_atom; | |
85 | extern int radeon_agpmode; | |
86 | extern int radeon_vram_limit; | |
87 | extern int radeon_gart_size; | |
88 | extern int radeon_benchmarking; | |
ecc0b326 | 89 | extern int radeon_testing; |
771fe6b9 | 90 | extern int radeon_connector_table; |
4ce001ab | 91 | extern int radeon_tv; |
dafc3bd5 | 92 | extern int radeon_audio; |
f46c0120 | 93 | extern int radeon_disp_priority; |
e2b0a8e1 | 94 | extern int radeon_hw_i2c; |
771fe6b9 JG |
95 | |
96 | /* | |
97 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
98 | * symbol; | |
99 | */ | |
100 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | |
225758d8 | 101 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
e821767b | 102 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
771fe6b9 JG |
103 | #define RADEON_IB_POOL_SIZE 16 |
104 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 | |
105 | #define RADEONFB_CONN_LIMIT 4 | |
f657c2a7 | 106 | #define RADEON_BIOS_NUM_SCRATCH 8 |
771fe6b9 | 107 | |
771fe6b9 JG |
108 | /* |
109 | * Errata workarounds. | |
110 | */ | |
111 | enum radeon_pll_errata { | |
112 | CHIP_ERRATA_R300_CG = 0x00000001, | |
113 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
114 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
115 | }; | |
116 | ||
117 | ||
118 | struct radeon_device; | |
119 | ||
120 | ||
121 | /* | |
122 | * BIOS. | |
123 | */ | |
6a9ee8af DA |
124 | #define ATRM_BIOS_PAGE 4096 |
125 | ||
8edb381d | 126 | #if defined(CONFIG_VGA_SWITCHEROO) |
6a9ee8af DA |
127 | bool radeon_atrm_supported(struct pci_dev *pdev); |
128 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); | |
8edb381d DA |
129 | #else |
130 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) | |
131 | { | |
132 | return false; | |
133 | } | |
134 | ||
135 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ | |
136 | return -EINVAL; | |
137 | } | |
138 | #endif | |
771fe6b9 JG |
139 | bool radeon_get_bios(struct radeon_device *rdev); |
140 | ||
3ce0a23d | 141 | |
771fe6b9 | 142 | /* |
3ce0a23d | 143 | * Dummy page |
771fe6b9 | 144 | */ |
3ce0a23d JG |
145 | struct radeon_dummy_page { |
146 | struct page *page; | |
147 | dma_addr_t addr; | |
148 | }; | |
149 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
150 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
151 | ||
771fe6b9 | 152 | |
3ce0a23d JG |
153 | /* |
154 | * Clocks | |
155 | */ | |
771fe6b9 JG |
156 | struct radeon_clock { |
157 | struct radeon_pll p1pll; | |
158 | struct radeon_pll p2pll; | |
bcc1c2a1 | 159 | struct radeon_pll dcpll; |
771fe6b9 JG |
160 | struct radeon_pll spll; |
161 | struct radeon_pll mpll; | |
162 | /* 10 Khz units */ | |
163 | uint32_t default_mclk; | |
164 | uint32_t default_sclk; | |
bcc1c2a1 AD |
165 | uint32_t default_dispclk; |
166 | uint32_t dp_extclk; | |
771fe6b9 JG |
167 | }; |
168 | ||
7433874e RM |
169 | /* |
170 | * Power management | |
171 | */ | |
172 | int radeon_pm_init(struct radeon_device *rdev); | |
29fb52ca | 173 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 174 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
ce8f5370 AD |
175 | void radeon_pm_suspend(struct radeon_device *rdev); |
176 | void radeon_pm_resume(struct radeon_device *rdev); | |
56278a8e AD |
177 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
178 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
7ac9aa5a | 179 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level); |
f892034a | 180 | void rs690_pm_info(struct radeon_device *rdev); |
21a8122a AD |
181 | extern u32 rv6xx_get_temp(struct radeon_device *rdev); |
182 | extern u32 rv770_get_temp(struct radeon_device *rdev); | |
183 | extern u32 evergreen_get_temp(struct radeon_device *rdev); | |
e33df25f | 184 | extern u32 sumo_get_temp(struct radeon_device *rdev); |
3ce0a23d | 185 | |
771fe6b9 JG |
186 | /* |
187 | * Fences. | |
188 | */ | |
189 | struct radeon_fence_driver { | |
190 | uint32_t scratch_reg; | |
191 | atomic_t seq; | |
192 | uint32_t last_seq; | |
225758d8 JG |
193 | unsigned long last_jiffies; |
194 | unsigned long last_timeout; | |
771fe6b9 JG |
195 | wait_queue_head_t queue; |
196 | rwlock_t lock; | |
197 | struct list_head created; | |
198 | struct list_head emited; | |
199 | struct list_head signaled; | |
0a0c7596 | 200 | bool initialized; |
771fe6b9 JG |
201 | }; |
202 | ||
203 | struct radeon_fence { | |
204 | struct radeon_device *rdev; | |
205 | struct kref kref; | |
206 | struct list_head list; | |
207 | /* protected by radeon_fence.lock */ | |
208 | uint32_t seq; | |
771fe6b9 JG |
209 | bool emited; |
210 | bool signaled; | |
211 | }; | |
212 | ||
213 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
214 | void radeon_fence_driver_fini(struct radeon_device *rdev); | |
215 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); | |
216 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); | |
217 | void radeon_fence_process(struct radeon_device *rdev); | |
218 | bool radeon_fence_signaled(struct radeon_fence *fence); | |
219 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
220 | int radeon_fence_wait_next(struct radeon_device *rdev); | |
221 | int radeon_fence_wait_last(struct radeon_device *rdev); | |
222 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); | |
223 | void radeon_fence_unref(struct radeon_fence **fence); | |
224 | ||
e024e110 DA |
225 | /* |
226 | * Tiling registers | |
227 | */ | |
228 | struct radeon_surface_reg { | |
4c788679 | 229 | struct radeon_bo *bo; |
e024e110 DA |
230 | }; |
231 | ||
232 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
233 | |
234 | /* | |
4c788679 | 235 | * TTM. |
771fe6b9 | 236 | */ |
4c788679 JG |
237 | struct radeon_mman { |
238 | struct ttm_bo_global_ref bo_global_ref; | |
ba4420c2 | 239 | struct drm_global_reference mem_global_ref; |
4c788679 | 240 | struct ttm_bo_device bdev; |
0a0c7596 JG |
241 | bool mem_global_referenced; |
242 | bool initialized; | |
4c788679 JG |
243 | }; |
244 | ||
245 | struct radeon_bo { | |
246 | /* Protected by gem.mutex */ | |
247 | struct list_head list; | |
248 | /* Protected by tbo.reserved */ | |
312ea8da JG |
249 | u32 placements[3]; |
250 | struct ttm_placement placement; | |
4c788679 JG |
251 | struct ttm_buffer_object tbo; |
252 | struct ttm_bo_kmap_obj kmap; | |
253 | unsigned pin_count; | |
254 | void *kptr; | |
255 | u32 tiling_flags; | |
256 | u32 pitch; | |
257 | int surface_reg; | |
258 | /* Constant after initialization */ | |
259 | struct radeon_device *rdev; | |
260 | struct drm_gem_object *gobj; | |
261 | }; | |
771fe6b9 | 262 | |
4c788679 | 263 | struct radeon_bo_list { |
147666fb | 264 | struct ttm_validate_buffer tv; |
4c788679 | 265 | struct radeon_bo *bo; |
771fe6b9 JG |
266 | uint64_t gpu_offset; |
267 | unsigned rdomain; | |
268 | unsigned wdomain; | |
4c788679 | 269 | u32 tiling_flags; |
771fe6b9 JG |
270 | }; |
271 | ||
771fe6b9 JG |
272 | /* |
273 | * GEM objects. | |
274 | */ | |
275 | struct radeon_gem { | |
4c788679 | 276 | struct mutex mutex; |
771fe6b9 JG |
277 | struct list_head objects; |
278 | }; | |
279 | ||
280 | int radeon_gem_init(struct radeon_device *rdev); | |
281 | void radeon_gem_fini(struct radeon_device *rdev); | |
282 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
283 | int alignment, int initial_domain, |
284 | bool discardable, bool kernel, | |
285 | struct drm_gem_object **obj); | |
771fe6b9 JG |
286 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
287 | uint64_t *gpu_addr); | |
288 | void radeon_gem_object_unpin(struct drm_gem_object *obj); | |
289 | ||
290 | ||
291 | /* | |
292 | * GART structures, functions & helpers | |
293 | */ | |
294 | struct radeon_mc; | |
295 | ||
296 | struct radeon_gart_table_ram { | |
297 | volatile uint32_t *ptr; | |
298 | }; | |
299 | ||
300 | struct radeon_gart_table_vram { | |
4c788679 | 301 | struct radeon_bo *robj; |
771fe6b9 JG |
302 | volatile uint32_t *ptr; |
303 | }; | |
304 | ||
305 | union radeon_gart_table { | |
306 | struct radeon_gart_table_ram ram; | |
307 | struct radeon_gart_table_vram vram; | |
308 | }; | |
309 | ||
a77f1718 | 310 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 311 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
a77f1718 | 312 | |
771fe6b9 JG |
313 | struct radeon_gart { |
314 | dma_addr_t table_addr; | |
315 | unsigned num_gpu_pages; | |
316 | unsigned num_cpu_pages; | |
317 | unsigned table_size; | |
318 | union radeon_gart_table table; | |
319 | struct page **pages; | |
320 | dma_addr_t *pages_addr; | |
321 | bool ready; | |
322 | }; | |
323 | ||
324 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
325 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
326 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
327 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
328 | int radeon_gart_init(struct radeon_device *rdev); | |
329 | void radeon_gart_fini(struct radeon_device *rdev); | |
330 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
331 | int pages); | |
332 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
333 | int pages, struct page **pagelist); | |
334 | ||
335 | ||
336 | /* | |
337 | * GPU MC structures, functions & helpers | |
338 | */ | |
339 | struct radeon_mc { | |
340 | resource_size_t aper_size; | |
341 | resource_size_t aper_base; | |
342 | resource_size_t agp_base; | |
7a50f01a DA |
343 | /* for some chips with <= 32MB we need to lie |
344 | * about vram size near mc fb location */ | |
3ce0a23d | 345 | u64 mc_vram_size; |
d594e46a | 346 | u64 visible_vram_size; |
c919b371 | 347 | u64 active_vram_size; |
3ce0a23d JG |
348 | u64 gtt_size; |
349 | u64 gtt_start; | |
350 | u64 gtt_end; | |
3ce0a23d JG |
351 | u64 vram_start; |
352 | u64 vram_end; | |
771fe6b9 | 353 | unsigned vram_width; |
3ce0a23d | 354 | u64 real_vram_size; |
771fe6b9 JG |
355 | int vram_mtrr; |
356 | bool vram_is_ddr; | |
d594e46a | 357 | bool igp_sideport_enabled; |
8d369bb1 | 358 | u64 gtt_base_align; |
771fe6b9 JG |
359 | }; |
360 | ||
06b6476d AD |
361 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
362 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
363 | |
364 | /* | |
365 | * GPU scratch registers structures, functions & helpers | |
366 | */ | |
367 | struct radeon_scratch { | |
368 | unsigned num_reg; | |
724c80e1 | 369 | uint32_t reg_base; |
771fe6b9 JG |
370 | bool free[32]; |
371 | uint32_t reg[32]; | |
372 | }; | |
373 | ||
374 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
375 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
376 | ||
377 | ||
378 | /* | |
379 | * IRQS. | |
380 | */ | |
6f34be50 AD |
381 | |
382 | struct radeon_unpin_work { | |
383 | struct work_struct work; | |
384 | struct radeon_device *rdev; | |
385 | int crtc_id; | |
386 | struct radeon_fence *fence; | |
387 | struct drm_pending_vblank_event *event; | |
388 | struct radeon_bo *old_rbo; | |
389 | u64 new_crtc_base; | |
390 | }; | |
391 | ||
392 | struct r500_irq_stat_regs { | |
393 | u32 disp_int; | |
394 | }; | |
395 | ||
396 | struct r600_irq_stat_regs { | |
397 | u32 disp_int; | |
398 | u32 disp_int_cont; | |
399 | u32 disp_int_cont2; | |
400 | u32 d1grph_int; | |
401 | u32 d2grph_int; | |
402 | }; | |
403 | ||
404 | struct evergreen_irq_stat_regs { | |
405 | u32 disp_int; | |
406 | u32 disp_int_cont; | |
407 | u32 disp_int_cont2; | |
408 | u32 disp_int_cont3; | |
409 | u32 disp_int_cont4; | |
410 | u32 disp_int_cont5; | |
411 | u32 d1grph_int; | |
412 | u32 d2grph_int; | |
413 | u32 d3grph_int; | |
414 | u32 d4grph_int; | |
415 | u32 d5grph_int; | |
416 | u32 d6grph_int; | |
417 | }; | |
418 | ||
419 | union radeon_irq_stat_regs { | |
420 | struct r500_irq_stat_regs r500; | |
421 | struct r600_irq_stat_regs r600; | |
422 | struct evergreen_irq_stat_regs evergreen; | |
423 | }; | |
424 | ||
771fe6b9 JG |
425 | struct radeon_irq { |
426 | bool installed; | |
427 | bool sw_int; | |
428 | /* FIXME: use a define max crtc rather than hardcode it */ | |
45f9a39b | 429 | bool crtc_vblank_int[6]; |
6f34be50 | 430 | bool pflip[6]; |
73a6d3fc | 431 | wait_queue_head_t vblank_queue; |
b500f680 AD |
432 | /* FIXME: use defines for max hpd/dacs */ |
433 | bool hpd[6]; | |
2031f77c AD |
434 | bool gui_idle; |
435 | bool gui_idle_acked; | |
436 | wait_queue_head_t idle_queue; | |
f2594933 CK |
437 | /* FIXME: use defines for max HDMI blocks */ |
438 | bool hdmi[2]; | |
1614f8b1 DA |
439 | spinlock_t sw_lock; |
440 | int sw_refcount; | |
6f34be50 AD |
441 | union radeon_irq_stat_regs stat_regs; |
442 | spinlock_t pflip_lock[6]; | |
443 | int pflip_refcount[6]; | |
771fe6b9 JG |
444 | }; |
445 | ||
446 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
447 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1614f8b1 DA |
448 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
449 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); | |
6f34be50 AD |
450 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
451 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); | |
771fe6b9 JG |
452 | |
453 | /* | |
454 | * CP & ring. | |
455 | */ | |
456 | struct radeon_ib { | |
457 | struct list_head list; | |
e821767b | 458 | unsigned idx; |
771fe6b9 JG |
459 | uint64_t gpu_addr; |
460 | struct radeon_fence *fence; | |
e821767b | 461 | uint32_t *ptr; |
771fe6b9 | 462 | uint32_t length_dw; |
e821767b | 463 | bool free; |
771fe6b9 JG |
464 | }; |
465 | ||
ecb114a1 DA |
466 | /* |
467 | * locking - | |
468 | * mutex protects scheduled_ibs, ready, alloc_bm | |
469 | */ | |
771fe6b9 JG |
470 | struct radeon_ib_pool { |
471 | struct mutex mutex; | |
4c788679 | 472 | struct radeon_bo *robj; |
9f93ed39 | 473 | struct list_head bogus_ib; |
771fe6b9 JG |
474 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
475 | bool ready; | |
e821767b | 476 | unsigned head_id; |
771fe6b9 JG |
477 | }; |
478 | ||
479 | struct radeon_cp { | |
4c788679 | 480 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
481 | volatile uint32_t *ring; |
482 | unsigned rptr; | |
483 | unsigned wptr; | |
484 | unsigned wptr_old; | |
485 | unsigned ring_size; | |
486 | unsigned ring_free_dw; | |
487 | int count_dw; | |
488 | uint64_t gpu_addr; | |
489 | uint32_t align_mask; | |
490 | uint32_t ptr_mask; | |
491 | struct mutex mutex; | |
492 | bool ready; | |
493 | }; | |
494 | ||
d8f60cfc AD |
495 | /* |
496 | * R6xx+ IH ring | |
497 | */ | |
498 | struct r600_ih { | |
4c788679 | 499 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
500 | volatile uint32_t *ring; |
501 | unsigned rptr; | |
502 | unsigned wptr; | |
503 | unsigned wptr_old; | |
504 | unsigned ring_size; | |
505 | uint64_t gpu_addr; | |
d8f60cfc AD |
506 | uint32_t ptr_mask; |
507 | spinlock_t lock; | |
508 | bool enabled; | |
509 | }; | |
510 | ||
3ce0a23d | 511 | struct r600_blit { |
ff82f052 | 512 | struct mutex mutex; |
4c788679 | 513 | struct radeon_bo *shader_obj; |
3ce0a23d JG |
514 | u64 shader_gpu_addr; |
515 | u32 vs_offset, ps_offset; | |
516 | u32 state_offset; | |
517 | u32 state_len; | |
518 | u32 vb_used, vb_total; | |
519 | struct radeon_ib *vb_ib; | |
520 | }; | |
521 | ||
771fe6b9 JG |
522 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
523 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); | |
524 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); | |
525 | int radeon_ib_pool_init(struct radeon_device *rdev); | |
526 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
527 | int radeon_ib_test(struct radeon_device *rdev); | |
9f93ed39 | 528 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
771fe6b9 JG |
529 | /* Ring access between begin & end cannot sleep */ |
530 | void radeon_ring_free_size(struct radeon_device *rdev); | |
91700f3c | 531 | int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw); |
771fe6b9 | 532 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
91700f3c | 533 | void radeon_ring_commit(struct radeon_device *rdev); |
771fe6b9 JG |
534 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
535 | void radeon_ring_unlock_undo(struct radeon_device *rdev); | |
536 | int radeon_ring_test(struct radeon_device *rdev); | |
537 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
538 | void radeon_ring_fini(struct radeon_device *rdev); | |
539 | ||
540 | ||
541 | /* | |
542 | * CS. | |
543 | */ | |
544 | struct radeon_cs_reloc { | |
545 | struct drm_gem_object *gobj; | |
4c788679 JG |
546 | struct radeon_bo *robj; |
547 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
548 | uint32_t handle; |
549 | uint32_t flags; | |
550 | }; | |
551 | ||
552 | struct radeon_cs_chunk { | |
553 | uint32_t chunk_id; | |
554 | uint32_t length_dw; | |
513bcb46 DA |
555 | int kpage_idx[2]; |
556 | uint32_t *kpage[2]; | |
771fe6b9 | 557 | uint32_t *kdata; |
513bcb46 DA |
558 | void __user *user_ptr; |
559 | int last_copied_page; | |
560 | int last_page_index; | |
771fe6b9 JG |
561 | }; |
562 | ||
563 | struct radeon_cs_parser { | |
c8c15ff1 | 564 | struct device *dev; |
771fe6b9 JG |
565 | struct radeon_device *rdev; |
566 | struct drm_file *filp; | |
567 | /* chunks */ | |
568 | unsigned nchunks; | |
569 | struct radeon_cs_chunk *chunks; | |
570 | uint64_t *chunks_array; | |
571 | /* IB */ | |
572 | unsigned idx; | |
573 | /* relocations */ | |
574 | unsigned nrelocs; | |
575 | struct radeon_cs_reloc *relocs; | |
576 | struct radeon_cs_reloc **relocs_ptr; | |
577 | struct list_head validated; | |
578 | /* indices of various chunks */ | |
579 | int chunk_ib_idx; | |
580 | int chunk_relocs_idx; | |
581 | struct radeon_ib *ib; | |
582 | void *track; | |
3ce0a23d | 583 | unsigned family; |
513bcb46 | 584 | int parser_error; |
771fe6b9 JG |
585 | }; |
586 | ||
513bcb46 DA |
587 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
588 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); | |
589 | ||
590 | ||
591 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | |
592 | { | |
593 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
594 | u32 pg_idx, pg_offset; | |
595 | u32 idx_value = 0; | |
596 | int new_page; | |
597 | ||
598 | pg_idx = (idx * 4) / PAGE_SIZE; | |
599 | pg_offset = (idx * 4) % PAGE_SIZE; | |
600 | ||
601 | if (ibc->kpage_idx[0] == pg_idx) | |
602 | return ibc->kpage[0][pg_offset/4]; | |
603 | if (ibc->kpage_idx[1] == pg_idx) | |
604 | return ibc->kpage[1][pg_offset/4]; | |
605 | ||
606 | new_page = radeon_cs_update_pages(p, pg_idx); | |
607 | if (new_page < 0) { | |
608 | p->parser_error = new_page; | |
609 | return 0; | |
610 | } | |
611 | ||
612 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
613 | return idx_value; | |
614 | } | |
615 | ||
771fe6b9 JG |
616 | struct radeon_cs_packet { |
617 | unsigned idx; | |
618 | unsigned type; | |
619 | unsigned reg; | |
620 | unsigned opcode; | |
621 | int count; | |
622 | unsigned one_reg_wr; | |
623 | }; | |
624 | ||
625 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
626 | struct radeon_cs_packet *pkt, | |
627 | unsigned idx, unsigned reg); | |
628 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
629 | struct radeon_cs_packet *pkt); | |
630 | ||
631 | ||
632 | /* | |
633 | * AGP | |
634 | */ | |
635 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 636 | void radeon_agp_resume(struct radeon_device *rdev); |
10b06122 | 637 | void radeon_agp_suspend(struct radeon_device *rdev); |
771fe6b9 JG |
638 | void radeon_agp_fini(struct radeon_device *rdev); |
639 | ||
640 | ||
641 | /* | |
642 | * Writeback | |
643 | */ | |
644 | struct radeon_wb { | |
4c788679 | 645 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
646 | volatile uint32_t *wb; |
647 | uint64_t gpu_addr; | |
724c80e1 | 648 | bool enabled; |
d0f8a854 | 649 | bool use_event; |
771fe6b9 JG |
650 | }; |
651 | ||
724c80e1 AD |
652 | #define RADEON_WB_SCRATCH_OFFSET 0 |
653 | #define RADEON_WB_CP_RPTR_OFFSET 1024 | |
654 | #define R600_WB_IH_WPTR_OFFSET 2048 | |
d0f8a854 | 655 | #define R600_WB_EVENT_OFFSET 3072 |
724c80e1 | 656 | |
c93bb85b JG |
657 | /** |
658 | * struct radeon_pm - power management datas | |
659 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
660 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
661 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
662 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
663 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
664 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
665 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
666 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
667 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
668 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) | |
669 | * @needed_bandwidth: current bandwidth needs | |
670 | * | |
671 | * It keeps track of various data needed to take powermanagement decision. | |
672 | * Bandwith need is used to determine minimun clock of the GPU and memory. | |
673 | * Equation between gpu/memory clock and available bandwidth is hw dependent | |
674 | * (type of memory, bus size, efficiency, ...) | |
675 | */ | |
ce8f5370 AD |
676 | |
677 | enum radeon_pm_method { | |
678 | PM_METHOD_PROFILE, | |
679 | PM_METHOD_DYNPM, | |
680 | }; | |
681 | ||
682 | enum radeon_dynpm_state { | |
683 | DYNPM_STATE_DISABLED, | |
684 | DYNPM_STATE_MINIMUM, | |
685 | DYNPM_STATE_PAUSED, | |
3f53eb6f RW |
686 | DYNPM_STATE_ACTIVE, |
687 | DYNPM_STATE_SUSPENDED, | |
c913e23a | 688 | }; |
ce8f5370 AD |
689 | enum radeon_dynpm_action { |
690 | DYNPM_ACTION_NONE, | |
691 | DYNPM_ACTION_MINIMUM, | |
692 | DYNPM_ACTION_DOWNCLOCK, | |
693 | DYNPM_ACTION_UPCLOCK, | |
694 | DYNPM_ACTION_DEFAULT | |
c913e23a | 695 | }; |
56278a8e AD |
696 | |
697 | enum radeon_voltage_type { | |
698 | VOLTAGE_NONE = 0, | |
699 | VOLTAGE_GPIO, | |
700 | VOLTAGE_VDDC, | |
701 | VOLTAGE_SW | |
702 | }; | |
703 | ||
0ec0e74f AD |
704 | enum radeon_pm_state_type { |
705 | POWER_STATE_TYPE_DEFAULT, | |
706 | POWER_STATE_TYPE_POWERSAVE, | |
707 | POWER_STATE_TYPE_BATTERY, | |
708 | POWER_STATE_TYPE_BALANCED, | |
709 | POWER_STATE_TYPE_PERFORMANCE, | |
710 | }; | |
711 | ||
ce8f5370 AD |
712 | enum radeon_pm_profile_type { |
713 | PM_PROFILE_DEFAULT, | |
714 | PM_PROFILE_AUTO, | |
715 | PM_PROFILE_LOW, | |
c9e75b21 | 716 | PM_PROFILE_MID, |
ce8f5370 AD |
717 | PM_PROFILE_HIGH, |
718 | }; | |
719 | ||
720 | #define PM_PROFILE_DEFAULT_IDX 0 | |
721 | #define PM_PROFILE_LOW_SH_IDX 1 | |
c9e75b21 AD |
722 | #define PM_PROFILE_MID_SH_IDX 2 |
723 | #define PM_PROFILE_HIGH_SH_IDX 3 | |
724 | #define PM_PROFILE_LOW_MH_IDX 4 | |
725 | #define PM_PROFILE_MID_MH_IDX 5 | |
726 | #define PM_PROFILE_HIGH_MH_IDX 6 | |
727 | #define PM_PROFILE_MAX 7 | |
ce8f5370 AD |
728 | |
729 | struct radeon_pm_profile { | |
730 | int dpms_off_ps_idx; | |
731 | int dpms_on_ps_idx; | |
732 | int dpms_off_cm_idx; | |
733 | int dpms_on_cm_idx; | |
516d0e46 AD |
734 | }; |
735 | ||
21a8122a AD |
736 | enum radeon_int_thermal_type { |
737 | THERMAL_TYPE_NONE, | |
738 | THERMAL_TYPE_RV6XX, | |
739 | THERMAL_TYPE_RV770, | |
740 | THERMAL_TYPE_EVERGREEN, | |
e33df25f | 741 | THERMAL_TYPE_SUMO, |
21a8122a AD |
742 | }; |
743 | ||
56278a8e AD |
744 | struct radeon_voltage { |
745 | enum radeon_voltage_type type; | |
746 | /* gpio voltage */ | |
747 | struct radeon_gpio_rec gpio; | |
748 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
749 | bool active_high; /* voltage drop is active when bit is high */ | |
750 | /* VDDC voltage */ | |
751 | u8 vddc_id; /* index into vddc voltage table */ | |
752 | u8 vddci_id; /* index into vddci voltage table */ | |
753 | bool vddci_enabled; | |
754 | /* r6xx+ sw */ | |
755 | u32 voltage; | |
756 | }; | |
757 | ||
d7311171 AD |
758 | /* clock mode flags */ |
759 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) | |
760 | ||
56278a8e AD |
761 | struct radeon_pm_clock_info { |
762 | /* memory clock */ | |
763 | u32 mclk; | |
764 | /* engine clock */ | |
765 | u32 sclk; | |
766 | /* voltage info */ | |
767 | struct radeon_voltage voltage; | |
d7311171 | 768 | /* standardized clock flags */ |
56278a8e AD |
769 | u32 flags; |
770 | }; | |
771 | ||
a48b9b4e | 772 | /* state flags */ |
d7311171 | 773 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
a48b9b4e | 774 | |
56278a8e | 775 | struct radeon_power_state { |
0ec0e74f | 776 | enum radeon_pm_state_type type; |
56278a8e AD |
777 | /* XXX: use a define for num clock modes */ |
778 | struct radeon_pm_clock_info clock_info[8]; | |
779 | /* number of valid clock modes in this power state */ | |
780 | int num_clock_modes; | |
56278a8e | 781 | struct radeon_pm_clock_info *default_clock_mode; |
a48b9b4e AD |
782 | /* standardized state flags */ |
783 | u32 flags; | |
79daedc9 AD |
784 | u32 misc; /* vbios specific flags */ |
785 | u32 misc2; /* vbios specific flags */ | |
786 | int pcie_lanes; /* pcie lanes */ | |
56278a8e AD |
787 | }; |
788 | ||
27459324 RM |
789 | /* |
790 | * Some modes are overclocked by very low value, accept them | |
791 | */ | |
792 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
793 | ||
c93bb85b | 794 | struct radeon_pm { |
c913e23a | 795 | struct mutex mutex; |
a48b9b4e AD |
796 | u32 active_crtcs; |
797 | int active_crtc_count; | |
c913e23a | 798 | int req_vblank; |
839461d3 | 799 | bool vblank_sync; |
2031f77c | 800 | bool gui_idle; |
c93bb85b JG |
801 | fixed20_12 max_bandwidth; |
802 | fixed20_12 igp_sideport_mclk; | |
803 | fixed20_12 igp_system_mclk; | |
804 | fixed20_12 igp_ht_link_clk; | |
805 | fixed20_12 igp_ht_link_width; | |
806 | fixed20_12 k8_bandwidth; | |
807 | fixed20_12 sideport_bandwidth; | |
808 | fixed20_12 ht_bandwidth; | |
809 | fixed20_12 core_bandwidth; | |
810 | fixed20_12 sclk; | |
f47299c5 | 811 | fixed20_12 mclk; |
c93bb85b | 812 | fixed20_12 needed_bandwidth; |
56278a8e AD |
813 | /* XXX: use a define for num power modes */ |
814 | struct radeon_power_state power_state[8]; | |
815 | /* number of valid power states */ | |
816 | int num_power_states; | |
a48b9b4e AD |
817 | int current_power_state_index; |
818 | int current_clock_mode_index; | |
819 | int requested_power_state_index; | |
820 | int requested_clock_mode_index; | |
821 | int default_power_state_index; | |
822 | u32 current_sclk; | |
823 | u32 current_mclk; | |
4d60173f | 824 | u32 current_vddc; |
29fb52ca | 825 | struct radeon_i2c_chan *i2c_bus; |
ce8f5370 AD |
826 | /* selected pm method */ |
827 | enum radeon_pm_method pm_method; | |
828 | /* dynpm power management */ | |
829 | struct delayed_work dynpm_idle_work; | |
830 | enum radeon_dynpm_state dynpm_state; | |
831 | enum radeon_dynpm_action dynpm_planned_action; | |
832 | unsigned long dynpm_action_timeout; | |
833 | bool dynpm_can_upclock; | |
834 | bool dynpm_can_downclock; | |
835 | /* profile-based power management */ | |
836 | enum radeon_pm_profile_type profile; | |
837 | int profile_index; | |
838 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; | |
21a8122a AD |
839 | /* internal thermal controller on rv6xx+ */ |
840 | enum radeon_int_thermal_type int_thermal_type; | |
841 | struct device *int_hwmon_dev; | |
c93bb85b JG |
842 | }; |
843 | ||
771fe6b9 JG |
844 | |
845 | /* | |
846 | * Benchmarking | |
847 | */ | |
848 | void radeon_benchmark(struct radeon_device *rdev); | |
849 | ||
850 | ||
ecc0b326 MD |
851 | /* |
852 | * Testing | |
853 | */ | |
854 | void radeon_test_moves(struct radeon_device *rdev); | |
855 | ||
856 | ||
771fe6b9 JG |
857 | /* |
858 | * Debugfs | |
859 | */ | |
860 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
861 | struct drm_info_list *files, | |
862 | unsigned nfiles); | |
863 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 JG |
864 | |
865 | ||
866 | /* | |
867 | * ASIC specific functions. | |
868 | */ | |
869 | struct radeon_asic { | |
068a117c | 870 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
871 | void (*fini)(struct radeon_device *rdev); |
872 | int (*resume)(struct radeon_device *rdev); | |
873 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 874 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
225758d8 | 875 | bool (*gpu_is_lockup)(struct radeon_device *rdev); |
a2d07b74 | 876 | int (*asic_reset)(struct radeon_device *rdev); |
771fe6b9 JG |
877 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
878 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
879 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); | |
880 | void (*cp_fini)(struct radeon_device *rdev); | |
881 | void (*cp_disable)(struct radeon_device *rdev); | |
3ce0a23d | 882 | void (*cp_commit)(struct radeon_device *rdev); |
771fe6b9 | 883 | void (*ring_start)(struct radeon_device *rdev); |
3ce0a23d JG |
884 | int (*ring_test)(struct radeon_device *rdev); |
885 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
771fe6b9 JG |
886 | int (*irq_set)(struct radeon_device *rdev); |
887 | int (*irq_process)(struct radeon_device *rdev); | |
7ed220d7 | 888 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
889 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
890 | int (*cs_parse)(struct radeon_cs_parser *p); | |
891 | int (*copy_blit)(struct radeon_device *rdev, | |
892 | uint64_t src_offset, | |
893 | uint64_t dst_offset, | |
894 | unsigned num_pages, | |
895 | struct radeon_fence *fence); | |
896 | int (*copy_dma)(struct radeon_device *rdev, | |
897 | uint64_t src_offset, | |
898 | uint64_t dst_offset, | |
899 | unsigned num_pages, | |
900 | struct radeon_fence *fence); | |
901 | int (*copy)(struct radeon_device *rdev, | |
902 | uint64_t src_offset, | |
903 | uint64_t dst_offset, | |
904 | unsigned num_pages, | |
905 | struct radeon_fence *fence); | |
7433874e | 906 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
771fe6b9 | 907 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
7433874e | 908 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
771fe6b9 | 909 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
c836a412 | 910 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
771fe6b9 JG |
911 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
912 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
e024e110 DA |
913 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
914 | uint32_t tiling_flags, uint32_t pitch, | |
915 | uint32_t offset, uint32_t obj_size); | |
9479c54f | 916 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
c93bb85b | 917 | void (*bandwidth_update)(struct radeon_device *rdev); |
429770b3 AD |
918 | void (*hpd_init)(struct radeon_device *rdev); |
919 | void (*hpd_fini)(struct radeon_device *rdev); | |
920 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
921 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
062b389c JG |
922 | /* ioctl hw specific callback. Some hw might want to perform special |
923 | * operation on specific ioctl. For instance on wait idle some hw | |
924 | * might want to perform and HDP flush through MMIO as it seems that | |
925 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
926 | * through ring. | |
927 | */ | |
928 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
def9ba9c | 929 | bool (*gui_idle)(struct radeon_device *rdev); |
ce8f5370 | 930 | /* power management */ |
49e02b73 AD |
931 | void (*pm_misc)(struct radeon_device *rdev); |
932 | void (*pm_prepare)(struct radeon_device *rdev); | |
933 | void (*pm_finish)(struct radeon_device *rdev); | |
ce8f5370 AD |
934 | void (*pm_init_profile)(struct radeon_device *rdev); |
935 | void (*pm_get_dynpm_state)(struct radeon_device *rdev); | |
6f34be50 AD |
936 | /* pageflipping */ |
937 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); | |
938 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
939 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); | |
771fe6b9 JG |
940 | }; |
941 | ||
21f9a437 JG |
942 | /* |
943 | * Asic structures | |
944 | */ | |
225758d8 JG |
945 | struct r100_gpu_lockup { |
946 | unsigned long last_jiffies; | |
947 | u32 last_cp_rptr; | |
948 | }; | |
949 | ||
551ebd83 | 950 | struct r100_asic { |
225758d8 JG |
951 | const unsigned *reg_safe_bm; |
952 | unsigned reg_safe_bm_size; | |
953 | u32 hdp_cntl; | |
954 | struct r100_gpu_lockup lockup; | |
551ebd83 DA |
955 | }; |
956 | ||
21f9a437 | 957 | struct r300_asic { |
225758d8 JG |
958 | const unsigned *reg_safe_bm; |
959 | unsigned reg_safe_bm_size; | |
960 | u32 resync_scratch; | |
961 | u32 hdp_cntl; | |
962 | struct r100_gpu_lockup lockup; | |
21f9a437 JG |
963 | }; |
964 | ||
965 | struct r600_asic { | |
225758d8 JG |
966 | unsigned max_pipes; |
967 | unsigned max_tile_pipes; | |
968 | unsigned max_simds; | |
969 | unsigned max_backends; | |
970 | unsigned max_gprs; | |
971 | unsigned max_threads; | |
972 | unsigned max_stack_entries; | |
973 | unsigned max_hw_contexts; | |
974 | unsigned max_gs_threads; | |
975 | unsigned sx_max_export_size; | |
976 | unsigned sx_max_export_pos_size; | |
977 | unsigned sx_max_export_smx_size; | |
978 | unsigned sq_num_cf_insts; | |
979 | unsigned tiling_nbanks; | |
980 | unsigned tiling_npipes; | |
981 | unsigned tiling_group_size; | |
e7aeeba6 | 982 | unsigned tile_config; |
225758d8 | 983 | struct r100_gpu_lockup lockup; |
21f9a437 JG |
984 | }; |
985 | ||
986 | struct rv770_asic { | |
225758d8 JG |
987 | unsigned max_pipes; |
988 | unsigned max_tile_pipes; | |
989 | unsigned max_simds; | |
990 | unsigned max_backends; | |
991 | unsigned max_gprs; | |
992 | unsigned max_threads; | |
993 | unsigned max_stack_entries; | |
994 | unsigned max_hw_contexts; | |
995 | unsigned max_gs_threads; | |
996 | unsigned sx_max_export_size; | |
997 | unsigned sx_max_export_pos_size; | |
998 | unsigned sx_max_export_smx_size; | |
999 | unsigned sq_num_cf_insts; | |
1000 | unsigned sx_num_of_sets; | |
1001 | unsigned sc_prim_fifo_size; | |
1002 | unsigned sc_hiz_tile_fifo_size; | |
1003 | unsigned sc_earlyz_tile_fifo_fize; | |
1004 | unsigned tiling_nbanks; | |
1005 | unsigned tiling_npipes; | |
1006 | unsigned tiling_group_size; | |
e7aeeba6 | 1007 | unsigned tile_config; |
225758d8 | 1008 | struct r100_gpu_lockup lockup; |
21f9a437 JG |
1009 | }; |
1010 | ||
32fcdbf4 AD |
1011 | struct evergreen_asic { |
1012 | unsigned num_ses; | |
1013 | unsigned max_pipes; | |
1014 | unsigned max_tile_pipes; | |
1015 | unsigned max_simds; | |
1016 | unsigned max_backends; | |
1017 | unsigned max_gprs; | |
1018 | unsigned max_threads; | |
1019 | unsigned max_stack_entries; | |
1020 | unsigned max_hw_contexts; | |
1021 | unsigned max_gs_threads; | |
1022 | unsigned sx_max_export_size; | |
1023 | unsigned sx_max_export_pos_size; | |
1024 | unsigned sx_max_export_smx_size; | |
1025 | unsigned sq_num_cf_insts; | |
1026 | unsigned sx_num_of_sets; | |
1027 | unsigned sc_prim_fifo_size; | |
1028 | unsigned sc_hiz_tile_fifo_size; | |
1029 | unsigned sc_earlyz_tile_fifo_size; | |
1030 | unsigned tiling_nbanks; | |
1031 | unsigned tiling_npipes; | |
1032 | unsigned tiling_group_size; | |
e7aeeba6 | 1033 | unsigned tile_config; |
32fcdbf4 AD |
1034 | }; |
1035 | ||
068a117c JG |
1036 | union radeon_asic_config { |
1037 | struct r300_asic r300; | |
551ebd83 | 1038 | struct r100_asic r100; |
3ce0a23d JG |
1039 | struct r600_asic r600; |
1040 | struct rv770_asic rv770; | |
32fcdbf4 | 1041 | struct evergreen_asic evergreen; |
068a117c JG |
1042 | }; |
1043 | ||
0a10c851 DV |
1044 | /* |
1045 | * asic initizalization from radeon_asic.c | |
1046 | */ | |
1047 | void radeon_agp_disable(struct radeon_device *rdev); | |
1048 | int radeon_asic_init(struct radeon_device *rdev); | |
1049 | ||
771fe6b9 JG |
1050 | |
1051 | /* | |
1052 | * IOCTL. | |
1053 | */ | |
1054 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
1055 | struct drm_file *filp); | |
1056 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
1057 | struct drm_file *filp); | |
1058 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
1059 | struct drm_file *file_priv); | |
1060 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1061 | struct drm_file *file_priv); | |
1062 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1063 | struct drm_file *file_priv); | |
1064 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1065 | struct drm_file *file_priv); | |
1066 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1067 | struct drm_file *filp); | |
1068 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1069 | struct drm_file *filp); | |
1070 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1071 | struct drm_file *filp); | |
1072 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1073 | struct drm_file *filp); | |
1074 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
e024e110 DA |
1075 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
1076 | struct drm_file *filp); | |
1077 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
1078 | struct drm_file *filp); | |
771fe6b9 | 1079 | |
87cbf8f2 AD |
1080 | /* VRAM scratch page for HDP bug */ |
1081 | struct r700_vram_scratch { | |
1082 | struct radeon_bo *robj; | |
1083 | volatile uint32_t *ptr; | |
1084 | }; | |
771fe6b9 JG |
1085 | |
1086 | /* | |
1087 | * Core structure, functions and helpers. | |
1088 | */ | |
1089 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
1090 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
1091 | ||
1092 | struct radeon_device { | |
9f022ddf | 1093 | struct device *dev; |
771fe6b9 JG |
1094 | struct drm_device *ddev; |
1095 | struct pci_dev *pdev; | |
1096 | /* ASIC */ | |
068a117c | 1097 | union radeon_asic_config config; |
771fe6b9 JG |
1098 | enum radeon_family family; |
1099 | unsigned long flags; | |
1100 | int usec_timeout; | |
1101 | enum radeon_pll_errata pll_errata; | |
1102 | int num_gb_pipes; | |
f779b3e5 | 1103 | int num_z_pipes; |
771fe6b9 JG |
1104 | int disp_priority; |
1105 | /* BIOS */ | |
1106 | uint8_t *bios; | |
1107 | bool is_atom_bios; | |
1108 | uint16_t bios_header_start; | |
4c788679 | 1109 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 1110 | /* Register mmio */ |
4c9bc75c DA |
1111 | resource_size_t rmmio_base; |
1112 | resource_size_t rmmio_size; | |
771fe6b9 | 1113 | void *rmmio; |
771fe6b9 JG |
1114 | radeon_rreg_t mc_rreg; |
1115 | radeon_wreg_t mc_wreg; | |
1116 | radeon_rreg_t pll_rreg; | |
1117 | radeon_wreg_t pll_wreg; | |
de1b2898 | 1118 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
1119 | radeon_rreg_t pciep_rreg; |
1120 | radeon_wreg_t pciep_wreg; | |
351a52a2 AD |
1121 | /* io port */ |
1122 | void __iomem *rio_mem; | |
1123 | resource_size_t rio_mem_size; | |
771fe6b9 JG |
1124 | struct radeon_clock clock; |
1125 | struct radeon_mc mc; | |
1126 | struct radeon_gart gart; | |
1127 | struct radeon_mode_info mode_info; | |
1128 | struct radeon_scratch scratch; | |
1129 | struct radeon_mman mman; | |
1130 | struct radeon_fence_driver fence_drv; | |
1131 | struct radeon_cp cp; | |
1132 | struct radeon_ib_pool ib_pool; | |
1133 | struct radeon_irq irq; | |
1134 | struct radeon_asic *asic; | |
1135 | struct radeon_gem gem; | |
c93bb85b | 1136 | struct radeon_pm pm; |
f657c2a7 | 1137 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 JG |
1138 | struct mutex cs_mutex; |
1139 | struct radeon_wb wb; | |
3ce0a23d | 1140 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
1141 | bool gpu_lockup; |
1142 | bool shutdown; | |
1143 | bool suspend; | |
ad49f501 | 1144 | bool need_dma32; |
733289c2 | 1145 | bool accel_working; |
e024e110 | 1146 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
1147 | const struct firmware *me_fw; /* all family ME firmware */ |
1148 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 1149 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
3ce0a23d | 1150 | struct r600_blit r600_blit; |
87cbf8f2 | 1151 | struct r700_vram_scratch vram_scratch; |
3e5cb98d | 1152 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 1153 | struct r600_ih ih; /* r6/700 interrupt ring */ |
d4877cf2 AD |
1154 | struct workqueue_struct *wq; |
1155 | struct work_struct hotplug_work; | |
18917b60 | 1156 | int num_crtc; /* number of crtcs */ |
40bacf16 | 1157 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
5876dd24 | 1158 | struct mutex vram_mutex; |
dafc3bd5 CK |
1159 | |
1160 | /* audio stuff */ | |
7eea7e9e | 1161 | bool audio_enabled; |
dafc3bd5 CK |
1162 | struct timer_list audio_timer; |
1163 | int audio_channels; | |
1164 | int audio_rate; | |
1165 | int audio_bits_per_sample; | |
1166 | uint8_t audio_status_bits; | |
1167 | uint8_t audio_category_code; | |
6a9ee8af DA |
1168 | |
1169 | bool powered_down; | |
ce8f5370 | 1170 | struct notifier_block acpi_nb; |
ab9e1f59 DA |
1171 | /* only one userspace can use Hyperz features at a time */ |
1172 | struct drm_file *hyperz_filp; | |
f376b94f AD |
1173 | /* i2c buses */ |
1174 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; | |
771fe6b9 JG |
1175 | }; |
1176 | ||
1177 | int radeon_device_init(struct radeon_device *rdev, | |
1178 | struct drm_device *ddev, | |
1179 | struct pci_dev *pdev, | |
1180 | uint32_t flags); | |
1181 | void radeon_device_fini(struct radeon_device *rdev); | |
1182 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
1183 | ||
3ce0a23d JG |
1184 | /* r600 blit */ |
1185 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); | |
1186 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); | |
1187 | void r600_kms_blit_copy(struct radeon_device *rdev, | |
1188 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
1189 | int size_bytes); | |
d7ccd8fc AD |
1190 | /* evergreen blit */ |
1191 | int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); | |
1192 | void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); | |
1193 | void evergreen_kms_blit_copy(struct radeon_device *rdev, | |
1194 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
1195 | int size_bytes); | |
3ce0a23d | 1196 | |
de1b2898 DA |
1197 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
1198 | { | |
07bec2df | 1199 | if (reg < rdev->rmmio_size) |
de1b2898 DA |
1200 | return readl(((void __iomem *)rdev->rmmio) + reg); |
1201 | else { | |
1202 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
1203 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
1204 | } | |
1205 | } | |
1206 | ||
1207 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1208 | { | |
07bec2df | 1209 | if (reg < rdev->rmmio_size) |
de1b2898 DA |
1210 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
1211 | else { | |
1212 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
1213 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
1214 | } | |
1215 | } | |
1216 | ||
351a52a2 AD |
1217 | static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) |
1218 | { | |
1219 | if (reg < rdev->rio_mem_size) | |
1220 | return ioread32(rdev->rio_mem + reg); | |
1221 | else { | |
1222 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); | |
1223 | return ioread32(rdev->rio_mem + RADEON_MM_DATA); | |
1224 | } | |
1225 | } | |
1226 | ||
1227 | static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
1228 | { | |
1229 | if (reg < rdev->rio_mem_size) | |
1230 | iowrite32(v, rdev->rio_mem + reg); | |
1231 | else { | |
1232 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); | |
1233 | iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); | |
1234 | } | |
1235 | } | |
1236 | ||
4c788679 JG |
1237 | /* |
1238 | * Cast helper | |
1239 | */ | |
1240 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
1241 | |
1242 | /* | |
1243 | * Registers read & write functions. | |
1244 | */ | |
1245 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) | |
1246 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) | |
de1b2898 | 1247 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
3ce0a23d | 1248 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
de1b2898 | 1249 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
771fe6b9 JG |
1250 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1251 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1252 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
1253 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
1254 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
1255 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
1256 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1257 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
aa5120d2 RM |
1258 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1259 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
1260 | #define WREG32_P(reg, val, mask) \ |
1261 | do { \ | |
1262 | uint32_t tmp_ = RREG32(reg); \ | |
1263 | tmp_ &= (mask); \ | |
1264 | tmp_ |= ((val) & ~(mask)); \ | |
1265 | WREG32(reg, tmp_); \ | |
1266 | } while (0) | |
1267 | #define WREG32_PLL_P(reg, val, mask) \ | |
1268 | do { \ | |
1269 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1270 | tmp_ &= (mask); \ | |
1271 | tmp_ |= ((val) & ~(mask)); \ | |
1272 | WREG32_PLL(reg, tmp_); \ | |
1273 | } while (0) | |
3ce0a23d | 1274 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
351a52a2 AD |
1275 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1276 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) | |
771fe6b9 | 1277 | |
de1b2898 DA |
1278 | /* |
1279 | * Indirect registers accessor | |
1280 | */ | |
1281 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
1282 | { | |
1283 | uint32_t r; | |
1284 | ||
1285 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1286 | r = RREG32(RADEON_PCIE_DATA); | |
1287 | return r; | |
1288 | } | |
1289 | ||
1290 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1291 | { | |
1292 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1293 | WREG32(RADEON_PCIE_DATA, (v)); | |
1294 | } | |
1295 | ||
771fe6b9 JG |
1296 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1297 | ||
1298 | ||
1299 | /* | |
1300 | * ASICs helpers. | |
1301 | */ | |
b995e433 DA |
1302 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1303 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
1304 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1305 | (rdev->family == CHIP_RV200) || \ | |
1306 | (rdev->family == CHIP_RS100) || \ | |
1307 | (rdev->family == CHIP_RS200) || \ | |
1308 | (rdev->family == CHIP_RV250) || \ | |
1309 | (rdev->family == CHIP_RV280) || \ | |
1310 | (rdev->family == CHIP_RS300)) | |
1311 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
1312 | (rdev->family == CHIP_RV350) || \ | |
1313 | (rdev->family == CHIP_R350) || \ | |
1314 | (rdev->family == CHIP_RV380) || \ | |
1315 | (rdev->family == CHIP_R420) || \ | |
1316 | (rdev->family == CHIP_R423) || \ | |
1317 | (rdev->family == CHIP_RV410) || \ | |
1318 | (rdev->family == CHIP_RS400) || \ | |
1319 | (rdev->family == CHIP_RS480)) | |
1320 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) | |
99999aaa AD |
1321 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
1322 | (rdev->family == CHIP_RS690) || \ | |
1323 | (rdev->family == CHIP_RS740) || \ | |
1324 | (rdev->family >= CHIP_R600)) | |
771fe6b9 JG |
1325 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1326 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 1327 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
2f062fda | 1328 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM)) |
771fe6b9 JG |
1329 | |
1330 | /* | |
1331 | * BIOS helpers. | |
1332 | */ | |
1333 | #define RBIOS8(i) (rdev->bios[i]) | |
1334 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1335 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1336 | ||
1337 | int radeon_combios_init(struct radeon_device *rdev); | |
1338 | void radeon_combios_fini(struct radeon_device *rdev); | |
1339 | int radeon_atombios_init(struct radeon_device *rdev); | |
1340 | void radeon_atombios_fini(struct radeon_device *rdev); | |
1341 | ||
1342 | ||
1343 | /* | |
1344 | * RING helpers. | |
1345 | */ | |
771fe6b9 JG |
1346 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
1347 | { | |
1348 | #if DRM_DEBUG_CODE | |
1349 | if (rdev->cp.count_dw <= 0) { | |
1350 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); | |
1351 | } | |
1352 | #endif | |
1353 | rdev->cp.ring[rdev->cp.wptr++] = v; | |
1354 | rdev->cp.wptr &= rdev->cp.ptr_mask; | |
1355 | rdev->cp.count_dw--; | |
1356 | rdev->cp.ring_free_dw--; | |
1357 | } | |
1358 | ||
1359 | ||
1360 | /* | |
1361 | * ASICs macro. | |
1362 | */ | |
068a117c | 1363 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
1364 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1365 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
1366 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
771fe6b9 | 1367 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
28d52043 | 1368 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
225758d8 | 1369 | #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) |
a2d07b74 | 1370 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
771fe6b9 JG |
1371 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1372 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) | |
3ce0a23d | 1373 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
771fe6b9 | 1374 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
3ce0a23d JG |
1375 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
1376 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) | |
771fe6b9 JG |
1377 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1378 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) | |
7ed220d7 | 1379 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
771fe6b9 JG |
1380 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
1381 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) | |
1382 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) | |
1383 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) | |
7433874e | 1384 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
771fe6b9 | 1385 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
7433874e | 1386 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
93e7de7b | 1387 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
c836a412 | 1388 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
771fe6b9 JG |
1389 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1390 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) | |
e024e110 DA |
1391 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1392 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) | |
c93bb85b | 1393 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
429770b3 AD |
1394 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1395 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) | |
1396 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) | |
1397 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) | |
def9ba9c | 1398 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
a424816f AD |
1399 | #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) |
1400 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) | |
1401 | #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) | |
ce8f5370 AD |
1402 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) |
1403 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) | |
6f34be50 AD |
1404 | #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc)) |
1405 | #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base)) | |
1406 | #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc)) | |
771fe6b9 | 1407 | |
6cf8a3f5 | 1408 | /* Common functions */ |
700a0cc0 | 1409 | /* AGP */ |
90aca4d2 | 1410 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
700a0cc0 | 1411 | extern void radeon_agp_disable(struct radeon_device *rdev); |
4aac0473 | 1412 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
82568565 | 1413 | extern void radeon_gart_restore(struct radeon_device *rdev); |
21f9a437 JG |
1414 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1415 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 1416 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 1417 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 1418 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 1419 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 | 1420 | extern void radeon_scratch_init(struct radeon_device *rdev); |
724c80e1 AD |
1421 | extern void radeon_wb_fini(struct radeon_device *rdev); |
1422 | extern int radeon_wb_init(struct radeon_device *rdev); | |
1423 | extern void radeon_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1424 | extern void radeon_surface_init(struct radeon_device *rdev); |
1425 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1426 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1427 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 1428 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 1429 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
d594e46a JG |
1430 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1431 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
6a9ee8af DA |
1432 | extern int radeon_resume_kms(struct drm_device *dev); |
1433 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
6cf8a3f5 | 1434 | |
a18d7ea1 | 1435 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
225758d8 JG |
1436 | extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp); |
1437 | extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp); | |
9f022ddf | 1438 | |
d4550907 JG |
1439 | /* rv200,rv250,rv280 */ |
1440 | extern void r200_set_safe_registers(struct radeon_device *rdev); | |
9f022ddf JG |
1441 | |
1442 | /* r300,r350,rv350,rv370,rv380 */ | |
1443 | extern void r300_set_reg_safe(struct radeon_device *rdev); | |
1444 | extern void r300_mc_program(struct radeon_device *rdev); | |
d594e46a | 1445 | extern void r300_mc_init(struct radeon_device *rdev); |
ca6ffc64 JG |
1446 | extern void r300_clock_startup(struct radeon_device *rdev); |
1447 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
4aac0473 JG |
1448 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1449 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
1450 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
9f022ddf | 1451 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
a18d7ea1 | 1452 | |
905b6822 | 1453 | /* r420,r423,rv410 */ |
21f9a437 JG |
1454 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1455 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
9f022ddf | 1456 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
d39c3b89 | 1457 | extern void r420_pipes_init(struct radeon_device *rdev); |
905b6822 | 1458 | |
21f9a437 | 1459 | /* rv515 */ |
d39c3b89 JG |
1460 | struct rv515_mc_save { |
1461 | u32 d1vga_control; | |
1462 | u32 d2vga_control; | |
1463 | u32 vga_render_control; | |
1464 | u32 vga_hdp_control; | |
1465 | u32 d1crtc_control; | |
1466 | u32 d2crtc_control; | |
1467 | }; | |
21f9a437 | 1468 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
d39c3b89 JG |
1469 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1470 | extern void rv515_set_safe_registers(struct radeon_device *rdev); | |
f0ed1f65 JG |
1471 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
1472 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
1473 | extern void rv515_clock_startup(struct radeon_device *rdev); | |
1474 | extern void rv515_debugfs(struct radeon_device *rdev); | |
1475 | extern int rv515_suspend(struct radeon_device *rdev); | |
21f9a437 | 1476 | |
3bc68535 JG |
1477 | /* rs400 */ |
1478 | extern int rs400_gart_init(struct radeon_device *rdev); | |
1479 | extern int rs400_gart_enable(struct radeon_device *rdev); | |
1480 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); | |
1481 | extern void rs400_gart_disable(struct radeon_device *rdev); | |
1482 | extern void rs400_gart_fini(struct radeon_device *rdev); | |
1483 | ||
1484 | /* rs600 */ | |
1485 | extern void rs600_set_safe_registers(struct radeon_device *rdev); | |
ac447df4 JG |
1486 | extern int rs600_irq_set(struct radeon_device *rdev); |
1487 | extern void rs600_irq_disable(struct radeon_device *rdev); | |
3bc68535 | 1488 | |
21f9a437 JG |
1489 | /* rs690, rs740 */ |
1490 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, | |
1491 | struct drm_display_mode *mode1, | |
1492 | struct drm_display_mode *mode2); | |
1493 | ||
1494 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ | |
1495 | extern bool r600_card_posted(struct radeon_device *rdev); | |
1496 | extern void r600_cp_stop(struct radeon_device *rdev); | |
fe251e2f | 1497 | extern int r600_cp_start(struct radeon_device *rdev); |
21f9a437 JG |
1498 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); |
1499 | extern int r600_cp_resume(struct radeon_device *rdev); | |
655efd3d | 1500 | extern void r600_cp_fini(struct radeon_device *rdev); |
21f9a437 | 1501 | extern int r600_count_pipe_bits(uint32_t val); |
21f9a437 | 1502 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); |
4aac0473 | 1503 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
21f9a437 JG |
1504 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1505 | extern int r600_ib_test(struct radeon_device *rdev); | |
1506 | extern int r600_ring_test(struct radeon_device *rdev); | |
21f9a437 JG |
1507 | extern void r600_scratch_init(struct radeon_device *rdev); |
1508 | extern int r600_blit_init(struct radeon_device *rdev); | |
1509 | extern void r600_blit_fini(struct radeon_device *rdev); | |
d8f60cfc | 1510 | extern int r600_init_microcode(struct radeon_device *rdev); |
a2d07b74 | 1511 | extern int r600_asic_reset(struct radeon_device *rdev); |
d8f60cfc AD |
1512 | /* r600 irq */ |
1513 | extern int r600_irq_init(struct radeon_device *rdev); | |
1514 | extern void r600_irq_fini(struct radeon_device *rdev); | |
1515 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
1516 | extern int r600_irq_set(struct radeon_device *rdev); | |
0c45249f | 1517 | extern void r600_irq_suspend(struct radeon_device *rdev); |
45f9a39b AD |
1518 | extern void r600_disable_interrupts(struct radeon_device *rdev); |
1519 | extern void r600_rlc_stop(struct radeon_device *rdev); | |
0c45249f | 1520 | /* r600 audio */ |
dafc3bd5 CK |
1521 | extern int r600_audio_init(struct radeon_device *rdev); |
1522 | extern int r600_audio_tmds_index(struct drm_encoder *encoder); | |
1523 | extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); | |
58bd0863 CK |
1524 | extern int r600_audio_channels(struct radeon_device *rdev); |
1525 | extern int r600_audio_bits_per_sample(struct radeon_device *rdev); | |
1526 | extern int r600_audio_rate(struct radeon_device *rdev); | |
1527 | extern uint8_t r600_audio_status_bits(struct radeon_device *rdev); | |
1528 | extern uint8_t r600_audio_category_code(struct radeon_device *rdev); | |
f2594933 | 1529 | extern void r600_audio_schedule_polling(struct radeon_device *rdev); |
58bd0863 CK |
1530 | extern void r600_audio_enable_polling(struct drm_encoder *encoder); |
1531 | extern void r600_audio_disable_polling(struct drm_encoder *encoder); | |
dafc3bd5 CK |
1532 | extern void r600_audio_fini(struct radeon_device *rdev); |
1533 | extern void r600_hdmi_init(struct drm_encoder *encoder); | |
2cd6218c RM |
1534 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
1535 | extern void r600_hdmi_disable(struct drm_encoder *encoder); | |
dafc3bd5 CK |
1536 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
1537 | extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); | |
58bd0863 | 1538 | extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); |
dafc3bd5 | 1539 | |
0ef0c1f7 | 1540 | extern void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
fe251e2f AD |
1541 | extern void r700_cp_stop(struct radeon_device *rdev); |
1542 | extern void r700_cp_fini(struct radeon_device *rdev); | |
0ca2ab52 AD |
1543 | extern void evergreen_disable_interrupt_state(struct radeon_device *rdev); |
1544 | extern int evergreen_irq_set(struct radeon_device *rdev); | |
d7ccd8fc AD |
1545 | extern int evergreen_blit_init(struct radeon_device *rdev); |
1546 | extern void evergreen_blit_fini(struct radeon_device *rdev); | |
fe251e2f | 1547 | |
d7a2952f AM |
1548 | /* radeon_acpi.c */ |
1549 | #if defined(CONFIG_ACPI) | |
1550 | extern int radeon_acpi_init(struct radeon_device *rdev); | |
1551 | #else | |
1552 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } | |
1553 | #endif | |
1554 | ||
bcc1c2a1 AD |
1555 | /* evergreen */ |
1556 | struct evergreen_mc_save { | |
1557 | u32 vga_control[6]; | |
1558 | u32 vga_render_control; | |
1559 | u32 vga_hdp_control; | |
1560 | u32 crtc_control[6]; | |
1561 | }; | |
1562 | ||
4c788679 JG |
1563 | #include "radeon_object.h" |
1564 | ||
771fe6b9 | 1565 | #endif |