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drm/radeon: make vm_block_size a module parameter
[linux-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
363eb0b4 102extern int radeon_hard_reset;
c1c44132 103extern int radeon_vm_size;
4510fb98 104extern int radeon_vm_block_size;
771fe6b9
JG		 105
106/*
107 * Copy from radeon_drv.h so we don't have to include both and have conflicting
108 * symbol;
109 */
bb635567
JG		 110#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
111#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 112/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 113#define RADEON_IB_POOL_SIZE 16
114#define RADEON_DEBUGFS_MAX_COMPONENTS 32
115#define RADEONFB_CONN_LIMIT 4
116#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 117
bb635567
JG		 118/* fence seq are set to this number when signaled */
119#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 120
121/* internal ring indices */
122/* r1xx+ has gfx CP ring */
d93f7937 123#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 124
125/* cayman has 2 compute CP rings */
d93f7937
CK		 126#define CAYMAN_RING_TYPE_CP1_INDEX 1
127#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 128
4d75658b
AD		 129/* R600+ has an async dma ring */
130#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 131/* cayman add a second async dma ring */
132#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 133
f2ba57b5 134/* R600+ */
d93f7937
CK		 135#define R600_RING_TYPE_UVD_INDEX 5
136
137/* TN+ */
138#define TN_RING_TYPE_VCE1_INDEX 6
139#define TN_RING_TYPE_VCE2_INDEX 7
140
141/* max number of rings */
142#define RADEON_NUM_RINGS 8
f2ba57b5 143
1c61eae4
CK		 144/* number of hw syncs before falling back on blocking */
145#define RADEON_NUM_SYNCS 4
f2ba57b5 146
8f53492f
CK		 147/* number of hw syncs before falling back on blocking */
148#define RADEON_NUM_SYNCS 4
149
721604a1 150/* hardcode those limit for now */
ca19f21e 151#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 152#define RADEON_VA_RESERVED_SIZE (8 << 20)
153#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 154
1a0041b8
AD		 155/* hard reset data */
156#define RADEON_ASIC_RESET_DATA 0x39d5e86b
157
ec46c76d
AD		 158/* reset flags */
159#define RADEON_RESET_GFX (1 << 0)
160#define RADEON_RESET_COMPUTE (1 << 1)
161#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 162#define RADEON_RESET_CP (1 << 3)
163#define RADEON_RESET_GRBM (1 << 4)
164#define RADEON_RESET_DMA1 (1 << 5)
165#define RADEON_RESET_RLC (1 << 6)
166#define RADEON_RESET_SEM (1 << 7)
167#define RADEON_RESET_IH (1 << 8)
168#define RADEON_RESET_VMC (1 << 9)
169#define RADEON_RESET_MC (1 << 10)
170#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 171
22c775ce
AD		 172/* CG block flags */
173#define RADEON_CG_BLOCK_GFX (1 << 0)
174#define RADEON_CG_BLOCK_MC (1 << 1)
175#define RADEON_CG_BLOCK_SDMA (1 << 2)
176#define RADEON_CG_BLOCK_UVD (1 << 3)
177#define RADEON_CG_BLOCK_VCE (1 << 4)
178#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 179#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 180
64d8a728
AD		 181/* CG flags */
182#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
183#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
184#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
185#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
186#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
187#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
188#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
189#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
190#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
191#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
192#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
193#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
194#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
195#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
196#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
197#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
198#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
199
200/* PG flags */
2b19d17f 201#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 202#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
203#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
204#define RADEON_PG_SUPPORT_UVD (1 << 3)
205#define RADEON_PG_SUPPORT_VCE (1 << 4)
206#define RADEON_PG_SUPPORT_CP (1 << 5)
207#define RADEON_PG_SUPPORT_GDS (1 << 6)
208#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
209#define RADEON_PG_SUPPORT_SDMA (1 << 8)
210#define RADEON_PG_SUPPORT_ACP (1 << 9)
211#define RADEON_PG_SUPPORT_SAMU (1 << 10)
212
9e05fa1d
AD		 213/* max cursor sizes (in pixels) */
214#define CURSOR_WIDTH 64
215#define CURSOR_HEIGHT 64
216
217#define CIK_CURSOR_WIDTH 128
218#define CIK_CURSOR_HEIGHT 128
219
771fe6b9
JG		 220/*
221 * Errata workarounds.
222 */
223enum radeon_pll_errata {
224 CHIP_ERRATA_R300_CG = 0x00000001,
225 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
226 CHIP_ERRATA_PLL_DELAY = 0x00000004
227};
228
229
230struct radeon_device;
231
232
233/*
234 * BIOS.
235 */
236bool radeon_get_bios(struct radeon_device *rdev);
237
238/*
3ce0a23d 239 * Dummy page
771fe6b9 240 */
3ce0a23d
JG		 241struct radeon_dummy_page {
242 struct page *page;
243 dma_addr_t addr;
244};
245int radeon_dummy_page_init(struct radeon_device *rdev);
246void radeon_dummy_page_fini(struct radeon_device *rdev);
247
771fe6b9 248
3ce0a23d
JG		 249/*
250 * Clocks
251 */
771fe6b9
JG		 252struct radeon_clock {
253 struct radeon_pll p1pll;
254 struct radeon_pll p2pll;
bcc1c2a1 255 struct radeon_pll dcpll;
771fe6b9
JG		 256 struct radeon_pll spll;
257 struct radeon_pll mpll;
258 /* 10 Khz units */
259 uint32_t default_mclk;
260 uint32_t default_sclk;
bcc1c2a1 261 uint32_t default_dispclk;
4489cd62 262 uint32_t current_dispclk;
bcc1c2a1 263 uint32_t dp_extclk;
b20f9bef 264 uint32_t max_pixel_clock;
771fe6b9
JG		 265};
266
7433874e
RM		 267/*
268 * Power management
269 */
270int radeon_pm_init(struct radeon_device *rdev);
914a8987 271int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 272void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 273void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 274void radeon_pm_suspend(struct radeon_device *rdev);
275void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 276void radeon_combios_get_power_modes(struct radeon_device *rdev);
277void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 278int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
279 u8 clock_type,
280 u32 clock,
281 bool strobe_mode,
282 struct atom_clock_dividers *dividers);
eaa778af
AD		 283int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
284 u32 clock,
285 bool strobe_mode,
286 struct atom_mpll_param *mpll_param);
8a83ec5e 287void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 288int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
289 u16 voltage_level, u8 voltage_type,
290 u32 *gpio_value, u32 *gpio_mask);
291void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
292 u32 eng_clock, u32 mem_clock);
293int radeon_atom_get_voltage_step(struct radeon_device *rdev,
294 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 295int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
296 u16 voltage_id, u16 *voltage);
beb79f40
AD		 297int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
298 u16 *voltage,
299 u16 leakage_idx);
cc8dbbb4
AD		 300int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
301 u16 *leakage_id);
302int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
303 u16 *vddc, u16 *vddci,
304 u16 virtual_voltage_id,
305 u16 vbios_voltage_id);
ae5b0abb
AD		 306int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
307 u8 voltage_type,
308 u16 nominal_voltage,
309 u16 *true_voltage);
310int radeon_atom_get_min_voltage(struct radeon_device *rdev,
311 u8 voltage_type, u16 *min_voltage);
312int radeon_atom_get_max_voltage(struct radeon_device *rdev,
313 u8 voltage_type, u16 *max_voltage);
314int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 315 u8 voltage_type, u8 voltage_mode,
ae5b0abb 316 struct atom_voltage_table *voltage_table);
58653abd
AD		 317bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
318 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 319void radeon_atom_update_memory_dll(struct radeon_device *rdev,
320 u32 mem_clock);
321void radeon_atom_set_ac_timing(struct radeon_device *rdev,
322 u32 mem_clock);
323int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
324 u8 module_index,
325 struct atom_mc_reg_table *reg_table);
326int radeon_atom_get_memory_info(struct radeon_device *rdev,
327 u8 module_index, struct atom_memory_info *mem_info);
328int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
329 bool gddr5, u8 module_index,
330 struct atom_memory_clock_range_table *mclk_range_table);
331int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
332 u16 voltage_id, u16 *voltage);
f892034a 333void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 334extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
335 unsigned *bankh, unsigned *mtaspect,
336 unsigned *tile_split);
3ce0a23d 337
771fe6b9
JG		 338/*
339 * Fences.
340 */
341struct radeon_fence_driver {
342 uint32_t scratch_reg;
30eb77f4
JG		 343 uint64_t gpu_addr;
344 volatile uint32_t *cpu_addr;
68e250b7
CK		 345 /* sync_seq is protected by ring emission lock */
346 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 347 atomic64_t last_seq;
0a0c7596 348 bool initialized;
771fe6b9
JG		 349};
350
351struct radeon_fence {
352 struct radeon_device *rdev;
353 struct kref kref;
771fe6b9 354 /* protected by radeon_fence.lock */
bb635567 355 uint64_t seq;
7465280c 356 /* RB, DMA, etc. */
bb635567 357 unsigned ring;
771fe6b9
JG		 358};
359
30eb77f4
JG		 360int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
361int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 362void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 363void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 364int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 365void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 366bool radeon_fence_signaled(struct radeon_fence *fence);
367int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 368int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
369int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 370int radeon_fence_wait_any(struct radeon_device *rdev,
371 struct radeon_fence **fences,
372 bool intr);
771fe6b9
JG		 373struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
374void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 375unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 376bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
377void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
378static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
379 struct radeon_fence *b)
380{
381 if (!a) {
382 return b;
383 }
384
385 if (!b) {
386 return a;
387 }
388
389 BUG_ON(a->ring != b->ring);
390
391 if (a->seq > b->seq) {
392 return a;
393 } else {
394 return b;
395 }
396}
771fe6b9 397
ee60e29f
CK		 398static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
399 struct radeon_fence *b)
400{
401 if (!a) {
402 return false;
403 }
404
405 if (!b) {
406 return true;
407 }
408
409 BUG_ON(a->ring != b->ring);
410
411 return a->seq < b->seq;
412}
413
e024e110
DA		 414/*
415 * Tiling registers
416 */
417struct radeon_surface_reg {
4c788679 418 struct radeon_bo *bo;
e024e110
DA		 419};
420
421#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 422
423/*
4c788679 424 * TTM.
771fe6b9 425 */
4c788679
JG		 426struct radeon_mman {
427 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 428 struct drm_global_reference mem_global_ref;
4c788679 429 struct ttm_bo_device bdev;
0a0c7596
JG		 430 bool mem_global_referenced;
431 bool initialized;
2014b569
CK		 432
433#if defined(CONFIG_DEBUG_FS)
434 struct dentry *vram;
dd66d20e 435 struct dentry *gtt;
2014b569 436#endif
4c788679
JG		 437};
438
721604a1
JG		 439/* bo virtual address in a specific vm */
440struct radeon_bo_va {
e971bd5e 441 /* protected by bo being reserved */
721604a1 442 struct list_head bo_list;
721604a1
JG		 443 uint64_t soffset;
444 uint64_t eoffset;
445 uint32_t flags;
446 bool valid;
e971bd5e
CK		 447 unsigned ref_count;
448
449 /* protected by vm mutex */
450 struct list_head vm_list;
451
452 /* constant after initialization */
453 struct radeon_vm *vm;
454 struct radeon_bo *bo;
721604a1
JG		 455};
456
4c788679
JG		 457struct radeon_bo {
458 /* Protected by gem.mutex */
459 struct list_head list;
460 /* Protected by tbo.reserved */
bda72d58 461 u32 initial_domain;
312ea8da
JG		 462 u32 placements[3];
463 struct ttm_placement placement;
4c788679
JG		 464 struct ttm_buffer_object tbo;
465 struct ttm_bo_kmap_obj kmap;
466 unsigned pin_count;
467 void *kptr;
468 u32 tiling_flags;
469 u32 pitch;
470 int surface_reg;
721604a1
JG		 471 /* list of all virtual address to which this bo
472 * is associated to
473 */
474 struct list_head va;
4c788679
JG		 475 /* Constant after initialization */
476 struct radeon_device *rdev;
441921d5 477 struct drm_gem_object gem_base;
63bc620b 478
409851f4
JG		 479 struct ttm_bo_kmap_obj dma_buf_vmap;
480 pid_t pid;
4c788679 481};
7e4d15d9 482#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 483
409851f4
JG		 484int radeon_gem_debugfs_init(struct radeon_device *rdev);
485
b15ba512
JG		 486/* sub-allocation manager, it has to be protected by another lock.
487 * By conception this is an helper for other part of the driver
488 * like the indirect buffer or semaphore, which both have their
489 * locking.
490 *
491 * Principe is simple, we keep a list of sub allocation in offset
492 * order (first entry has offset == 0, last entry has the highest
493 * offset).
494 *
495 * When allocating new object we first check if there is room at
496 * the end total_size - (last_object_offset + last_object_size) >=
497 * alloc_size. If so we allocate new object there.
498 *
499 * When there is not enough room at the end, we start waiting for
500 * each sub object until we reach object_offset+object_size >=
501 * alloc_size, this object then become the sub object we return.
502 *
503 * Alignment can't be bigger than page size.
504 *
505 * Hole are not considered for allocation to keep things simple.
506 * Assumption is that there won't be hole (all object on same
507 * alignment).
508 */
509struct radeon_sa_manager {
bfb38d35 510 wait_queue_head_t wq;
b15ba512 511 struct radeon_bo *bo;
c3b7fe8b
CK		 512 struct list_head *hole;
513 struct list_head flist[RADEON_NUM_RINGS];
514 struct list_head olist;
b15ba512
JG		 515 unsigned size;
516 uint64_t gpu_addr;
517 void *cpu_ptr;
518 uint32_t domain;
6c4f978b 519 uint32_t align;
b15ba512
JG		 520};
521
522struct radeon_sa_bo;
523
524/* sub-allocation buffer */
525struct radeon_sa_bo {
c3b7fe8b
CK		 526 struct list_head olist;
527 struct list_head flist;
b15ba512 528 struct radeon_sa_manager *manager;
e6661a96
CK		 529 unsigned soffset;
530 unsigned eoffset;
557017a0 531 struct radeon_fence *fence;
b15ba512
JG		 532};
533
771fe6b9
JG		 534/*
535 * GEM objects.
536 */
537struct radeon_gem {
4c788679 538 struct mutex mutex;
771fe6b9
JG		 539 struct list_head objects;
540};
541
542int radeon_gem_init(struct radeon_device *rdev);
543void radeon_gem_fini(struct radeon_device *rdev);
544int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 545 int alignment, int initial_domain,
546 bool discardable, bool kernel,
547 struct drm_gem_object **obj);
771fe6b9 548
ff72145b
DA		 549int radeon_mode_dumb_create(struct drm_file *file_priv,
550 struct drm_device *dev,
551 struct drm_mode_create_dumb *args);
552int radeon_mode_dumb_mmap(struct drm_file *filp,
553 struct drm_device *dev,
554 uint32_t handle, uint64_t *offset_p);
771fe6b9 555
c1341e52
JG		 556/*
557 * Semaphores.
558 */
c1341e52 559struct radeon_semaphore {
a8c05940
JG		 560 struct radeon_sa_bo *sa_bo;
561 signed waiters;
c1341e52 562 uint64_t gpu_addr;
1654b817 563 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 564};
565
c1341e52
JG		 566int radeon_semaphore_create(struct radeon_device *rdev,
567 struct radeon_semaphore **semaphore);
1654b817 568bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 569 struct radeon_semaphore *semaphore);
1654b817 570bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 571 struct radeon_semaphore *semaphore);
1654b817
CK		 572void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
573 struct radeon_fence *fence);
8f676c4c
CK		 574int radeon_semaphore_sync_rings(struct radeon_device *rdev,
575 struct radeon_semaphore *semaphore,
1654b817 576 int waiting_ring);
c1341e52 577void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 578 struct radeon_semaphore **semaphore,
a8c05940 579 struct radeon_fence *fence);
c1341e52 580
771fe6b9
JG		 581/*
582 * GART structures, functions & helpers
583 */
584struct radeon_mc;
585
a77f1718 586#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 587#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 588#define RADEON_GPU_PAGE_SHIFT 12
721604a1 589#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 590
771fe6b9
JG		 591struct radeon_gart {
592 dma_addr_t table_addr;
c9a1be96
JG		 593 struct radeon_bo *robj;
594 void *ptr;
771fe6b9
JG		 595 unsigned num_gpu_pages;
596 unsigned num_cpu_pages;
597 unsigned table_size;
771fe6b9
JG		 598 struct page **pages;
599 dma_addr_t *pages_addr;
600 bool ready;
601};
602
603int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
604void radeon_gart_table_ram_free(struct radeon_device *rdev);
605int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
606void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 607int radeon_gart_table_vram_pin(struct radeon_device *rdev);
608void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 609int radeon_gart_init(struct radeon_device *rdev);
610void radeon_gart_fini(struct radeon_device *rdev);
611void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
612 int pages);
613int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 614 int pages, struct page **pagelist,
615 dma_addr_t *dma_addr);
c9a1be96 616void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 617
618
619/*
620 * GPU MC structures, functions & helpers
621 */
622struct radeon_mc {
623 resource_size_t aper_size;
624 resource_size_t aper_base;
625 resource_size_t agp_base;
7a50f01a
DA		 626 /* for some chips with <= 32MB we need to lie
627 * about vram size near mc fb location */
3ce0a23d 628 u64 mc_vram_size;
d594e46a 629 u64 visible_vram_size;
3ce0a23d
JG		 630 u64 gtt_size;
631 u64 gtt_start;
632 u64 gtt_end;
3ce0a23d
JG		 633 u64 vram_start;
634 u64 vram_end;
771fe6b9 635 unsigned vram_width;
3ce0a23d 636 u64 real_vram_size;
771fe6b9
JG		 637 int vram_mtrr;
638 bool vram_is_ddr;
d594e46a 639 bool igp_sideport_enabled;
8d369bb1 640 u64 gtt_base_align;
9ed8b1f9 641 u64 mc_mask;
771fe6b9
JG		 642};
643
06b6476d
AD		 644bool radeon_combios_sideport_present(struct radeon_device *rdev);
645bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 646
647/*
648 * GPU scratch registers structures, functions & helpers
649 */
650struct radeon_scratch {
651 unsigned num_reg;
724c80e1 652 uint32_t reg_base;
771fe6b9
JG		 653 bool free[32];
654 uint32_t reg[32];
655};
656
657int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
658void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
659
75efdee1
AD		 660/*
661 * GPU doorbell structures, functions & helpers
662 */
d5754ab8
AL		 663#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
664
75efdee1 665struct radeon_doorbell {
75efdee1 666 /* doorbell mmio */
d5754ab8
AL		 667 resource_size_t base;
668 resource_size_t size;
669 u32 __iomem *ptr;
670 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
671 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 672};
673
674int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
675void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 676
677/*
678 * IRQS.
679 */
6f34be50 680
fa7f517c
CK		 681struct radeon_flip_work {
682 struct work_struct flip_work;
683 struct work_struct unpin_work;
684 struct radeon_device *rdev;
685 int crtc_id;
686 struct drm_framebuffer *fb;
6f34be50 687 struct drm_pending_vblank_event *event;
fa7f517c
CK		 688 struct radeon_bo *old_rbo;
689 struct radeon_bo *new_rbo;
690 struct radeon_fence *fence;
6f34be50
AD		 691};
692
693struct r500_irq_stat_regs {
694 u32 disp_int;
f122c610 695 u32 hdmi0_status;
6f34be50
AD		 696};
697
698struct r600_irq_stat_regs {
699 u32 disp_int;
700 u32 disp_int_cont;
701 u32 disp_int_cont2;
702 u32 d1grph_int;
703 u32 d2grph_int;
f122c610
AD		 704 u32 hdmi0_status;
705 u32 hdmi1_status;
6f34be50
AD		 706};
707
708struct evergreen_irq_stat_regs {
709 u32 disp_int;
710 u32 disp_int_cont;
711 u32 disp_int_cont2;
712 u32 disp_int_cont3;
713 u32 disp_int_cont4;
714 u32 disp_int_cont5;
715 u32 d1grph_int;
716 u32 d2grph_int;
717 u32 d3grph_int;
718 u32 d4grph_int;
719 u32 d5grph_int;
720 u32 d6grph_int;
f122c610
AD		 721 u32 afmt_status1;
722 u32 afmt_status2;
723 u32 afmt_status3;
724 u32 afmt_status4;
725 u32 afmt_status5;
726 u32 afmt_status6;
6f34be50
AD		 727};
728
a59781bb
AD		 729struct cik_irq_stat_regs {
730 u32 disp_int;
731 u32 disp_int_cont;
732 u32 disp_int_cont2;
733 u32 disp_int_cont3;
734 u32 disp_int_cont4;
735 u32 disp_int_cont5;
736 u32 disp_int_cont6;
f5d636d2
CK		 737 u32 d1grph_int;
738 u32 d2grph_int;
739 u32 d3grph_int;
740 u32 d4grph_int;
741 u32 d5grph_int;
742 u32 d6grph_int;
a59781bb
AD		 743};
744
6f34be50
AD		 745union radeon_irq_stat_regs {
746 struct r500_irq_stat_regs r500;
747 struct r600_irq_stat_regs r600;
748 struct evergreen_irq_stat_regs evergreen;
a59781bb 749 struct cik_irq_stat_regs cik;
6f34be50
AD		 750};
751
be0949f5 752#define RADEON_MAX_HPD_PINS 7
54bd5206 753#define RADEON_MAX_CRTCS 6
b530602f 754#define RADEON_MAX_AFMT_BLOCKS 7
54bd5206 755
771fe6b9 756struct radeon_irq {
fb98257a
CK		 757 bool installed;
758 spinlock_t lock;
736fc37f 759 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 760 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 761 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 762 wait_queue_head_t vblank_queue;
763 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 764 bool afmt[RADEON_MAX_AFMT_BLOCKS];
765 union radeon_irq_stat_regs stat_regs;
4a6369e9 766 bool dpm_thermal;
771fe6b9
JG		 767};
768
769int radeon_irq_kms_init(struct radeon_device *rdev);
770void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 771void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
772void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 773void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
774void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 775void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
776void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
777void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
778void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 779
780/*
e32eb50d 781 * CP & rings.
771fe6b9 782 */
7465280c 783
771fe6b9 784struct radeon_ib {
68470ae7
JG		 785 struct radeon_sa_bo *sa_bo;
786 uint32_t length_dw;
787 uint64_t gpu_addr;
788 uint32_t *ptr;
876dc9f3 789 int ring;
68470ae7 790 struct radeon_fence *fence;
4bf3dd92 791 struct radeon_vm *vm;
68470ae7
JG		 792 bool is_const_ib;
793 struct radeon_semaphore *semaphore;
771fe6b9
JG		 794};
795
e32eb50d 796struct radeon_ring {
4c788679 797 struct radeon_bo *ring_obj;
771fe6b9 798 volatile uint32_t *ring;
5596a9db 799 unsigned rptr_offs;
45df6803 800 unsigned rptr_save_reg;
89d35807
AD		 801 u64 next_rptr_gpu_addr;
802 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 803 unsigned wptr;
804 unsigned wptr_old;
805 unsigned ring_size;
806 unsigned ring_free_dw;
807 int count_dw;
aee4aa73
CK		 808 atomic_t last_rptr;
809 atomic64_t last_activity;
771fe6b9
JG		 810 uint64_t gpu_addr;
811 uint32_t align_mask;
812 uint32_t ptr_mask;
771fe6b9 813 bool ready;
78c5560a 814 u32 nop;
8b25ed34 815 u32 idx;
5f0839c1
JG		 816 u64 last_semaphore_signal_addr;
817 u64 last_semaphore_wait_addr;
963e81f9
AD		 818 /* for CIK queues */
819 u32 me;
820 u32 pipe;
821 u32 queue;
822 struct radeon_bo *mqd_obj;
d5754ab8 823 u32 doorbell_index;
963e81f9
AD		 824 unsigned wptr_offs;
825};
826
827struct radeon_mec {
828 struct radeon_bo *hpd_eop_obj;
829 u64 hpd_eop_gpu_addr;
830 u32 num_pipe;
831 u32 num_mec;
832 u32 num_queue;
771fe6b9
JG		 833};
834
721604a1
JG		 835/*
836 * VM
837 */
ee60e29f 838
fa87e62d 839/* maximum number of VMIDs */
ee60e29f
CK		 840#define RADEON_NUM_VM 16
841
fa87e62d 842/* number of entries in page table */
4510fb98 843#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 844
1c01103c
AD		 845/* PTBs (Page Table Blocks) need to be aligned to 32K */
846#define RADEON_VM_PTB_ALIGN_SIZE 32768
847#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
848#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
849
24c16439
CK		 850#define R600_PTE_VALID (1 << 0)
851#define R600_PTE_SYSTEM (1 << 1)
852#define R600_PTE_SNOOPED (1 << 2)
853#define R600_PTE_READABLE (1 << 5)
854#define R600_PTE_WRITEABLE (1 << 6)
855
ec3dbbcb
CK		 856/* PTE (Page Table Entry) fragment field for different page sizes */
857#define R600_PTE_FRAG_4KB (0 << 7)
858#define R600_PTE_FRAG_64KB (4 << 7)
859#define R600_PTE_FRAG_256KB (6 << 7)
860
0e97703c
CK		 861/* flags used for GART page table entries on R600+ */
862#define R600_PTE_GART ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \
863 | R600_PTE_READABLE | R600_PTE_WRITEABLE)
864
6d2f2944
CK		 865struct radeon_vm_pt {
866 struct radeon_bo *bo;
867 uint64_t addr;
868};
869
721604a1 870struct radeon_vm {
721604a1 871 struct list_head va;
ee60e29f 872 unsigned id;
90a51a32
CK		 873
874 /* contains the page directory */
6d2f2944 875 struct radeon_bo *page_directory;
90a51a32 876 uint64_t pd_gpu_addr;
6d2f2944 877 unsigned max_pde_used;
90a51a32
CK		 878
879 /* array of page tables, one for each page directory entry */
6d2f2944 880 struct radeon_vm_pt *page_tables;
90a51a32 881
721604a1
JG		 882 struct mutex mutex;
883 /* last fence for cs using this vm */
884 struct radeon_fence *fence;
9b40e5d8
CK		 885 /* last flush or NULL if we still need to flush */
886 struct radeon_fence *last_flush;
593b2635
CK		 887 /* last use of vmid */
888 struct radeon_fence *last_id_use;
721604a1
JG		 889};
890
721604a1 891struct radeon_vm_manager {
ee60e29f 892 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 893 uint32_t max_pfn;
721604a1
JG		 894 /* number of VMIDs */
895 unsigned nvm;
896 /* vram base address for page table entry */
897 u64 vram_base_offset;
67e915e4
AD		 898 /* is vm enabled? */
899 bool enabled;
721604a1
JG		 900};
901
902/*
903 * file private structure
904 */
905struct radeon_fpriv {
906 struct radeon_vm vm;
907};
908
d8f60cfc
AD		 909/*
910 * R6xx+ IH ring
911 */
912struct r600_ih {
4c788679 913 struct radeon_bo *ring_obj;
d8f60cfc
AD		 914 volatile uint32_t *ring;
915 unsigned rptr;
d8f60cfc
AD		 916 unsigned ring_size;
917 uint64_t gpu_addr;
d8f60cfc 918 uint32_t ptr_mask;
c20dc369 919 atomic_t lock;
d8f60cfc
AD		 920 bool enabled;
921};
922
347e7592 923/*
2948f5e6 924 * RLC stuff
347e7592 925 */
2948f5e6
AD		 926#include "clearstate_defs.h"
927
928struct radeon_rlc {
347e7592
AD		 929 /* for power gating */
930 struct radeon_bo *save_restore_obj;
931 uint64_t save_restore_gpu_addr;
2948f5e6 932 volatile uint32_t *sr_ptr;
1fd11777 933 const u32 *reg_list;
2948f5e6 934 u32 reg_list_size;
347e7592
AD		 935 /* for clear state */
936 struct radeon_bo *clear_state_obj;
937 uint64_t clear_state_gpu_addr;
2948f5e6 938 volatile uint32_t *cs_ptr;
1fd11777 939 const struct cs_section_def *cs_data;
22c775ce
AD		 940 u32 clear_state_size;
941 /* for cp tables */
942 struct radeon_bo *cp_table_obj;
943 uint64_t cp_table_gpu_addr;
944 volatile uint32_t *cp_table_ptr;
945 u32 cp_table_size;
347e7592
AD		 946};
947
69e130a6 948int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 949 struct radeon_ib *ib, struct radeon_vm *vm,
950 unsigned size);
f2e39221 951void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 952int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
953 struct radeon_ib *const_ib);
771fe6b9
JG		 954int radeon_ib_pool_init(struct radeon_device *rdev);
955void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 956int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 957/* Ring access between begin & end cannot sleep */
89d35807
AD		 958bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
959 struct radeon_ring *ring);
e32eb50d
CK		 960void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
961int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
962int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
963void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
964void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 965void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 966void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
967int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 968void radeon_ring_lockup_update(struct radeon_device *rdev,
969 struct radeon_ring *ring);
069211e5 970bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 971unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
972 uint32_t **data);
973int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
974 unsigned size, uint32_t *data);
e32eb50d 975int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 976 unsigned rptr_offs, u32 nop);
e32eb50d 977void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 978
979
4d75658b
AD		 980/* r600 async dma */
981void r600_dma_stop(struct radeon_device *rdev);
982int r600_dma_resume(struct radeon_device *rdev);
983void r600_dma_fini(struct radeon_device *rdev);
984
8c5fd7ef
AD		 985void cayman_dma_stop(struct radeon_device *rdev);
986int cayman_dma_resume(struct radeon_device *rdev);
987void cayman_dma_fini(struct radeon_device *rdev);
988
771fe6b9
JG		 989/*
990 * CS.
991 */
992struct radeon_cs_reloc {
993 struct drm_gem_object *gobj;
4c788679 994 struct radeon_bo *robj;
df0af440
CK		 995 struct ttm_validate_buffer tv;
996 uint64_t gpu_offset;
ce6758c8
CK		 997 unsigned prefered_domains;
998 unsigned allowed_domains;
df0af440 999 uint32_t tiling_flags;
771fe6b9 1000 uint32_t handle;
771fe6b9
JG		 1001};
1002
1003struct radeon_cs_chunk {
1004 uint32_t chunk_id;
1005 uint32_t length_dw;
1006 uint32_t *kdata;
721604a1 1007 void __user *user_ptr;
771fe6b9
JG		 1008};
1009
1010struct radeon_cs_parser {
c8c15ff1 1011 struct device *dev;
771fe6b9
JG		 1012 struct radeon_device *rdev;
1013 struct drm_file *filp;
1014 /* chunks */
1015 unsigned nchunks;
1016 struct radeon_cs_chunk *chunks;
1017 uint64_t *chunks_array;
1018 /* IB */
1019 unsigned idx;
1020 /* relocations */
1021 unsigned nrelocs;
1022 struct radeon_cs_reloc *relocs;
1023 struct radeon_cs_reloc **relocs_ptr;
df0af440 1024 struct radeon_cs_reloc *vm_bos;
771fe6b9 1025 struct list_head validated;
cf4ccd01 1026 unsigned dma_reloc_idx;
771fe6b9
JG		 1027 /* indices of various chunks */
1028 int chunk_ib_idx;
1029 int chunk_relocs_idx;
721604a1 1030 int chunk_flags_idx;
dfcf5f36 1031 int chunk_const_ib_idx;
f2e39221
JG		 1032 struct radeon_ib ib;
1033 struct radeon_ib const_ib;
771fe6b9 1034 void *track;
3ce0a23d 1035 unsigned family;
e70f224c 1036 int parser_error;
721604a1
JG		 1037 u32 cs_flags;
1038 u32 ring;
1039 s32 priority;
ecff665f 1040 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1041};
1042
28a326c5
ML		 1043static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1044{
1045 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1046
1047 if (ibc->kdata)
1048 return ibc->kdata[idx];
1049 return p->ib.ptr[idx];
1050}
1051
513bcb46 1052
771fe6b9
JG		 1053struct radeon_cs_packet {
1054 unsigned idx;
1055 unsigned type;
1056 unsigned reg;
1057 unsigned opcode;
1058 int count;
1059 unsigned one_reg_wr;
1060};
1061
1062typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1063 struct radeon_cs_packet *pkt,
1064 unsigned idx, unsigned reg);
1065typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1066 struct radeon_cs_packet *pkt);
1067
1068
1069/*
1070 * AGP
1071 */
1072int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1073void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1074void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1075void radeon_agp_fini(struct radeon_device *rdev);
1076
1077
1078/*
1079 * Writeback
1080 */
1081struct radeon_wb {
4c788679 1082 struct radeon_bo *wb_obj;
771fe6b9
JG		 1083 volatile uint32_t *wb;
1084 uint64_t gpu_addr;
724c80e1 1085 bool enabled;
d0f8a854 1086 bool use_event;
771fe6b9
JG		 1087};
1088
724c80e1 1089#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1090#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1091#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1092#define RADEON_WB_CP1_RPTR_OFFSET 1280
1093#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1094#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1095#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1096#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1097#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1098#define CIK_WB_CP1_WPTR_OFFSET 3328
1099#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1100
c93bb85b
JG		 1101/**
1102 * struct radeon_pm - power management datas
1103 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1104 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1105 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1106 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1107 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1108 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1109 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1110 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1111 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1112 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1113 * @needed_bandwidth: current bandwidth needs
1114 *
1115 * It keeps track of various data needed to take powermanagement decision.
25985edc 1116 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1117 * Equation between gpu/memory clock and available bandwidth is hw dependent
1118 * (type of memory, bus size, efficiency, ...)
1119 */
ce8f5370
AD		 1120
1121enum radeon_pm_method {
1122 PM_METHOD_PROFILE,
1123 PM_METHOD_DYNPM,
da321c8a 1124 PM_METHOD_DPM,
ce8f5370
AD		 1125};
1126
1127enum radeon_dynpm_state {
1128 DYNPM_STATE_DISABLED,
1129 DYNPM_STATE_MINIMUM,
1130 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1131 DYNPM_STATE_ACTIVE,
1132 DYNPM_STATE_SUSPENDED,
c913e23a 1133};
ce8f5370
AD		 1134enum radeon_dynpm_action {
1135 DYNPM_ACTION_NONE,
1136 DYNPM_ACTION_MINIMUM,
1137 DYNPM_ACTION_DOWNCLOCK,
1138 DYNPM_ACTION_UPCLOCK,
1139 DYNPM_ACTION_DEFAULT
c913e23a 1140};
56278a8e
AD		 1141
1142enum radeon_voltage_type {
1143 VOLTAGE_NONE = 0,
1144 VOLTAGE_GPIO,
1145 VOLTAGE_VDDC,
1146 VOLTAGE_SW
1147};
1148
0ec0e74f 1149enum radeon_pm_state_type {
da321c8a 1150 /* not used for dpm */
0ec0e74f
AD		 1151 POWER_STATE_TYPE_DEFAULT,
1152 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1153 /* user selectable states */
0ec0e74f
AD		 1154 POWER_STATE_TYPE_BATTERY,
1155 POWER_STATE_TYPE_BALANCED,
1156 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1157 /* internal states */
1158 POWER_STATE_TYPE_INTERNAL_UVD,
1159 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1160 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1161 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1162 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1163 POWER_STATE_TYPE_INTERNAL_BOOT,
1164 POWER_STATE_TYPE_INTERNAL_THERMAL,
1165 POWER_STATE_TYPE_INTERNAL_ACPI,
1166 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1167 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1168};
1169
ce8f5370
AD		 1170enum radeon_pm_profile_type {
1171 PM_PROFILE_DEFAULT,
1172 PM_PROFILE_AUTO,
1173 PM_PROFILE_LOW,
c9e75b21 1174 PM_PROFILE_MID,
ce8f5370
AD		 1175 PM_PROFILE_HIGH,
1176};
1177
1178#define PM_PROFILE_DEFAULT_IDX 0
1179#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1180#define PM_PROFILE_MID_SH_IDX 2
1181#define PM_PROFILE_HIGH_SH_IDX 3
1182#define PM_PROFILE_LOW_MH_IDX 4
1183#define PM_PROFILE_MID_MH_IDX 5
1184#define PM_PROFILE_HIGH_MH_IDX 6
1185#define PM_PROFILE_MAX 7
ce8f5370
AD		 1186
1187struct radeon_pm_profile {
1188 int dpms_off_ps_idx;
1189 int dpms_on_ps_idx;
1190 int dpms_off_cm_idx;
1191 int dpms_on_cm_idx;
516d0e46
AD		 1192};
1193
21a8122a
AD		 1194enum radeon_int_thermal_type {
1195 THERMAL_TYPE_NONE,
da321c8a
AD		 1196 THERMAL_TYPE_EXTERNAL,
1197 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1198 THERMAL_TYPE_RV6XX,
1199 THERMAL_TYPE_RV770,
da321c8a 1200 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1201 THERMAL_TYPE_EVERGREEN,
e33df25f 1202 THERMAL_TYPE_SUMO,
4fddba1f 1203 THERMAL_TYPE_NI,
14607d08 1204 THERMAL_TYPE_SI,
da321c8a 1205 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1206 THERMAL_TYPE_CI,
16fbe00d 1207 THERMAL_TYPE_KV,
21a8122a
AD		 1208};
1209
56278a8e
AD		 1210struct radeon_voltage {
1211 enum radeon_voltage_type type;
1212 /* gpio voltage */
1213 struct radeon_gpio_rec gpio;
1214 u32 delay; /* delay in usec from voltage drop to sclk change */
1215 bool active_high; /* voltage drop is active when bit is high */
1216 /* VDDC voltage */
1217 u8 vddc_id; /* index into vddc voltage table */
1218 u8 vddci_id; /* index into vddci voltage table */
1219 bool vddci_enabled;
1220 /* r6xx+ sw */
2feea49a
AD		 1221 u16 voltage;
1222 /* evergreen+ vddci */
1223 u16 vddci;
56278a8e
AD		 1224};
1225
d7311171
AD		 1226/* clock mode flags */
1227#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1228
56278a8e
AD		 1229struct radeon_pm_clock_info {
1230 /* memory clock */
1231 u32 mclk;
1232 /* engine clock */
1233 u32 sclk;
1234 /* voltage info */
1235 struct radeon_voltage voltage;
d7311171 1236 /* standardized clock flags */
56278a8e
AD		 1237 u32 flags;
1238};
1239
a48b9b4e 1240/* state flags */
d7311171 1241#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1242
56278a8e 1243struct radeon_power_state {
0ec0e74f 1244 enum radeon_pm_state_type type;
8f3f1c9a 1245 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1246 /* number of valid clock modes in this power state */
1247 int num_clock_modes;
56278a8e 1248 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1249 /* standardized state flags */
1250 u32 flags;
79daedc9
AD		 1251 u32 misc; /* vbios specific flags */
1252 u32 misc2; /* vbios specific flags */
1253 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1254};
1255
27459324
RM		 1256/*
1257 * Some modes are overclocked by very low value, accept them
1258 */
1259#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1260
2e9d4c05
AD		 1261enum radeon_dpm_auto_throttle_src {
1262 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1263 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1264};
1265
1266enum radeon_dpm_event_src {
1267 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1268 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1269 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1270 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1271 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1272};
1273
58bd2a88
AD		 1274#define RADEON_MAX_VCE_LEVELS 6
1275
b62d628b
AD		 1276enum radeon_vce_level {
1277 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1278 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1279 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1280 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1281 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1282 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1283};
1284
da321c8a
AD		 1285struct radeon_ps {
1286 u32 caps; /* vbios flags */
1287 u32 class; /* vbios flags */
1288 u32 class2; /* vbios flags */
1289 /* UVD clocks */
1290 u32 vclk;
1291 u32 dclk;
c4453e66
AD		 1292 /* VCE clocks */
1293 u32 evclk;
1294 u32 ecclk;
b62d628b
AD		 1295 bool vce_active;
1296 enum radeon_vce_level vce_level;
da321c8a
AD		 1297 /* asic priv */
1298 void *ps_priv;
1299};
1300
1301struct radeon_dpm_thermal {
1302 /* thermal interrupt work */
1303 struct work_struct work;
1304 /* low temperature threshold */
1305 int min_temp;
1306 /* high temperature threshold */
1307 int max_temp;
1308 /* was interrupt low to high or high to low */
1309 bool high_to_low;
1310};
1311
d22b7e40
AD		 1312enum radeon_clk_action
1313{
1314 RADEON_SCLK_UP = 1,
1315 RADEON_SCLK_DOWN
1316};
1317
1318struct radeon_blacklist_clocks
1319{
1320 u32 sclk;
1321 u32 mclk;
1322 enum radeon_clk_action action;
1323};
1324
61b7d601
AD		 1325struct radeon_clock_and_voltage_limits {
1326 u32 sclk;
1327 u32 mclk;
cdf6e805
AD		 1328 u16 vddc;
1329 u16 vddci;
61b7d601
AD		 1330};
1331
1332struct radeon_clock_array {
1333 u32 count;
1334 u32 *values;
1335};
1336
1337struct radeon_clock_voltage_dependency_entry {
1338 u32 clk;
1339 u16 v;
1340};
1341
1342struct radeon_clock_voltage_dependency_table {
1343 u32 count;
1344 struct radeon_clock_voltage_dependency_entry *entries;
1345};
1346
ef976ec4
AD		 1347union radeon_cac_leakage_entry {
1348 struct {
1349 u16 vddc;
1350 u32 leakage;
1351 };
1352 struct {
1353 u16 vddc1;
1354 u16 vddc2;
1355 u16 vddc3;
1356 };
61b7d601
AD		 1357};
1358
1359struct radeon_cac_leakage_table {
1360 u32 count;
ef976ec4 1361 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1362};
1363
929ee7a8
AD		 1364struct radeon_phase_shedding_limits_entry {
1365 u16 voltage;
1366 u32 sclk;
1367 u32 mclk;
1368};
1369
1370struct radeon_phase_shedding_limits_table {
1371 u32 count;
1372 struct radeon_phase_shedding_limits_entry *entries;
1373};
1374
84a9d9ee
AD		 1375struct radeon_uvd_clock_voltage_dependency_entry {
1376 u32 vclk;
1377 u32 dclk;
1378 u16 v;
1379};
1380
1381struct radeon_uvd_clock_voltage_dependency_table {
1382 u8 count;
1383 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1384};
1385
d29f013b
AD		 1386struct radeon_vce_clock_voltage_dependency_entry {
1387 u32 ecclk;
1388 u32 evclk;
1389 u16 v;
1390};
1391
1392struct radeon_vce_clock_voltage_dependency_table {
1393 u8 count;
1394 struct radeon_vce_clock_voltage_dependency_entry *entries;
1395};
1396
a5cb318e
AD		 1397struct radeon_ppm_table {
1398 u8 ppm_design;
1399 u16 cpu_core_number;
1400 u32 platform_tdp;
1401 u32 small_ac_platform_tdp;
1402 u32 platform_tdc;
1403 u32 small_ac_platform_tdc;
1404 u32 apu_tdp;
1405 u32 dgpu_tdp;
1406 u32 dgpu_ulv_power;
1407 u32 tj_max;
1408};
1409
58cb7632
AD		 1410struct radeon_cac_tdp_table {
1411 u16 tdp;
1412 u16 configurable_tdp;
1413 u16 tdc;
1414 u16 battery_power_limit;
1415 u16 small_power_limit;
1416 u16 low_cac_leakage;
1417 u16 high_cac_leakage;
1418 u16 maximum_power_delivery_limit;
1419};
1420
61b7d601
AD		 1421struct radeon_dpm_dynamic_state {
1422 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1423 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1424 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1425 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1426 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1427 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1428 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1429 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1430 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1431 struct radeon_clock_array valid_sclk_values;
1432 struct radeon_clock_array valid_mclk_values;
1433 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1434 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1435 u32 mclk_sclk_ratio;
1436 u32 sclk_mclk_delta;
1437 u16 vddc_vddci_delta;
1438 u16 min_vddc_for_pcie_gen2;
1439 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1440 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1441 struct radeon_ppm_table *ppm_table;
58cb7632 1442 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1443};
1444
1445struct radeon_dpm_fan {
1446 u16 t_min;
1447 u16 t_med;
1448 u16 t_high;
1449 u16 pwm_min;
1450 u16 pwm_med;
1451 u16 pwm_high;
1452 u8 t_hyst;
1453 u32 cycle_delay;
1454 u16 t_max;
1455 bool ucode_fan_control;
1456};
1457
32ce4652
AD		 1458enum radeon_pcie_gen {
1459 RADEON_PCIE_GEN1 = 0,
1460 RADEON_PCIE_GEN2 = 1,
1461 RADEON_PCIE_GEN3 = 2,
1462 RADEON_PCIE_GEN_INVALID = 0xffff
1463};
1464
70d01a5e
AD		 1465enum radeon_dpm_forced_level {
1466 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1467 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1468 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1469};
1470
58bd2a88
AD		 1471struct radeon_vce_state {
1472 /* vce clocks */
1473 u32 evclk;
1474 u32 ecclk;
1475 /* gpu clocks */
1476 u32 sclk;
1477 u32 mclk;
1478 u8 clk_idx;
1479 u8 pstate;
1480};
1481
da321c8a
AD		 1482struct radeon_dpm {
1483 struct radeon_ps *ps;
1484 /* number of valid power states */
1485 int num_ps;
1486 /* current power state that is active */
1487 struct radeon_ps *current_ps;
1488 /* requested power state */
1489 struct radeon_ps *requested_ps;
1490 /* boot up power state */
1491 struct radeon_ps *boot_ps;
1492 /* default uvd power state */
1493 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1494 /* vce requirements */
1495 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1496 enum radeon_vce_level vce_level;
da321c8a
AD		 1497 enum radeon_pm_state_type state;
1498 enum radeon_pm_state_type user_state;
1499 u32 platform_caps;
1500 u32 voltage_response_time;
1501 u32 backbias_response_time;
1502 void *priv;
1503 u32 new_active_crtcs;
1504 int new_active_crtc_count;
1505 u32 current_active_crtcs;
1506 int current_active_crtc_count;
61b7d601
AD		 1507 struct radeon_dpm_dynamic_state dyn_state;
1508 struct radeon_dpm_fan fan;
1509 u32 tdp_limit;
1510 u32 near_tdp_limit;
a9e61410 1511 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1512 u32 sq_ramping_threshold;
1513 u32 cac_leakage;
1514 u16 tdp_od_limit;
1515 u32 tdp_adjustment;
1516 u16 load_line_slope;
1517 bool power_control;
5ca302f7 1518 bool ac_power;
da321c8a
AD		 1519 /* special states active */
1520 bool thermal_active;
8a227555 1521 bool uvd_active;
b62d628b 1522 bool vce_active;
da321c8a
AD		 1523 /* thermal handling */
1524 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1525 /* forced levels */
1526 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1527 /* track UVD streams */
1528 unsigned sd;
1529 unsigned hd;
da321c8a
AD		 1530};
1531
ce3537d5 1532void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1533void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1534
c93bb85b 1535struct radeon_pm {
c913e23a 1536 struct mutex mutex;
db7fce39
CK		 1537 /* write locked while reprogramming mclk */
1538 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1539 u32 active_crtcs;
1540 int active_crtc_count;
c913e23a 1541 int req_vblank;
839461d3 1542 bool vblank_sync;
c93bb85b
JG		 1543 fixed20_12 max_bandwidth;
1544 fixed20_12 igp_sideport_mclk;
1545 fixed20_12 igp_system_mclk;
1546 fixed20_12 igp_ht_link_clk;
1547 fixed20_12 igp_ht_link_width;
1548 fixed20_12 k8_bandwidth;
1549 fixed20_12 sideport_bandwidth;
1550 fixed20_12 ht_bandwidth;
1551 fixed20_12 core_bandwidth;
1552 fixed20_12 sclk;
f47299c5 1553 fixed20_12 mclk;
c93bb85b 1554 fixed20_12 needed_bandwidth;
0975b162 1555 struct radeon_power_state *power_state;
56278a8e
AD		 1556 /* number of valid power states */
1557 int num_power_states;
a48b9b4e
AD		 1558 int current_power_state_index;
1559 int current_clock_mode_index;
1560 int requested_power_state_index;
1561 int requested_clock_mode_index;
1562 int default_power_state_index;
1563 u32 current_sclk;
1564 u32 current_mclk;
2feea49a
AD		 1565 u16 current_vddc;
1566 u16 current_vddci;
9ace9f7b
AD		 1567 u32 default_sclk;
1568 u32 default_mclk;
2feea49a
AD		 1569 u16 default_vddc;
1570 u16 default_vddci;
29fb52ca 1571 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1572 /* selected pm method */
1573 enum radeon_pm_method pm_method;
1574 /* dynpm power management */
1575 struct delayed_work dynpm_idle_work;
1576 enum radeon_dynpm_state dynpm_state;
1577 enum radeon_dynpm_action dynpm_planned_action;
1578 unsigned long dynpm_action_timeout;
1579 bool dynpm_can_upclock;
1580 bool dynpm_can_downclock;
1581 /* profile-based power management */
1582 enum radeon_pm_profile_type profile;
1583 int profile_index;
1584 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1585 /* internal thermal controller on rv6xx+ */
1586 enum radeon_int_thermal_type int_thermal_type;
1587 struct device *int_hwmon_dev;
da321c8a
AD		 1588 /* dpm */
1589 bool dpm_enabled;
1590 struct radeon_dpm dpm;
c93bb85b
JG		 1591};
1592
a4c9e2ee
AD		 1593int radeon_pm_get_type_index(struct radeon_device *rdev,
1594 enum radeon_pm_state_type ps_type,
1595 int instance);
f2ba57b5
CK		 1596/*
1597 * UVD
1598 */
1599#define RADEON_MAX_UVD_HANDLES 10
1600#define RADEON_UVD_STACK_SIZE (1024*1024)
1601#define RADEON_UVD_HEAP_SIZE (1024*1024)
1602
1603struct radeon_uvd {
1604 struct radeon_bo *vcpu_bo;
1605 void *cpu_addr;
1606 uint64_t gpu_addr;
9cc2e0e9 1607 void *saved_bo;
f2ba57b5
CK		 1608 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1609 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1610 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1611 struct delayed_work idle_work;
f2ba57b5
CK		 1612};
1613
1614int radeon_uvd_init(struct radeon_device *rdev);
1615void radeon_uvd_fini(struct radeon_device *rdev);
1616int radeon_uvd_suspend(struct radeon_device *rdev);
1617int radeon_uvd_resume(struct radeon_device *rdev);
1618int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1619 uint32_t handle, struct radeon_fence **fence);
1620int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1621 uint32_t handle, struct radeon_fence **fence);
1622void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1623void radeon_uvd_free_handles(struct radeon_device *rdev,
1624 struct drm_file *filp);
1625int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1626void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1627int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1628 unsigned vclk, unsigned dclk,
1629 unsigned vco_min, unsigned vco_max,
1630 unsigned fb_factor, unsigned fb_mask,
1631 unsigned pd_min, unsigned pd_max,
1632 unsigned pd_even,
1633 unsigned *optimal_fb_div,
1634 unsigned *optimal_vclk_div,
1635 unsigned *optimal_dclk_div);
1636int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1637 unsigned cg_upll_func_cntl);
771fe6b9 1638
d93f7937
CK		 1639/*
1640 * VCE
1641 */
1642#define RADEON_MAX_VCE_HANDLES 16
1643#define RADEON_VCE_STACK_SIZE (1024*1024)
1644#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1645
1646struct radeon_vce {
1647 struct radeon_bo *vcpu_bo;
d93f7937 1648 uint64_t gpu_addr;
98ccc291
CK		 1649 unsigned fw_version;
1650 unsigned fb_version;
d93f7937
CK		 1651 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1652 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1653 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1654 struct delayed_work idle_work;
d93f7937
CK		 1655};
1656
1657int radeon_vce_init(struct radeon_device *rdev);
1658void radeon_vce_fini(struct radeon_device *rdev);
1659int radeon_vce_suspend(struct radeon_device *rdev);
1660int radeon_vce_resume(struct radeon_device *rdev);
1661int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1662 uint32_t handle, struct radeon_fence **fence);
1663int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1664 uint32_t handle, struct radeon_fence **fence);
1665void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1666void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1667int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1668int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1669bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1670 struct radeon_ring *ring,
1671 struct radeon_semaphore *semaphore,
1672 bool emit_wait);
1673void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1674void radeon_vce_fence_emit(struct radeon_device *rdev,
1675 struct radeon_fence *fence);
1676int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1677int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1678
b530602f 1679struct r600_audio_pin {
a92553ab
RM		 1680 int channels;
1681 int rate;
1682 int bits_per_sample;
1683 u8 status_bits;
1684 u8 category_code;
b530602f
AD		 1685 u32 offset;
1686 bool connected;
1687 u32 id;
1688};
1689
1690struct r600_audio {
1691 bool enabled;
1692 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1693 int num_pins;
a92553ab
RM		 1694};
1695
771fe6b9
JG		 1696/*
1697 * Benchmarking
1698 */
638dd7db 1699void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1700
1701
ecc0b326
MD		 1702/*
1703 * Testing
1704 */
1705void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1706void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1707 struct radeon_ring *cpA,
1708 struct radeon_ring *cpB);
60a7e396 1709void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1710
1711
771fe6b9
JG		 1712/*
1713 * Debugfs
1714 */
4d8bf9ae
CK		 1715struct radeon_debugfs {
1716 struct drm_info_list *files;
1717 unsigned num_files;
1718};
1719
771fe6b9
JG		 1720int radeon_debugfs_add_files(struct radeon_device *rdev,
1721 struct drm_info_list *files,
1722 unsigned nfiles);
1723int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1724
76a0df85
CK		 1725/*
1726 * ASIC ring specific functions.
1727 */
1728struct radeon_asic_ring {
1729 /* ring read/write ptr handling */
1730 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1731 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1732 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1733
1734 /* validating and patching of IBs */
1735 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1736 int (*cs_parse)(struct radeon_cs_parser *p);
1737
1738 /* command emmit functions */
1739 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1740 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1654b817 1741 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1742 struct radeon_semaphore *semaphore, bool emit_wait);
1743 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1744
1745 /* testing functions */
1746 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1747 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1748 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1749
1750 /* deprecated */
1751 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1752};
771fe6b9
JG		 1753
1754/*
1755 * ASIC specific functions.
1756 */
1757struct radeon_asic {
068a117c 1758 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1759 void (*fini)(struct radeon_device *rdev);
1760 int (*resume)(struct radeon_device *rdev);
1761 int (*suspend)(struct radeon_device *rdev);
28d52043 1762 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1763 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1764 /* ioctl hw specific callback. Some hw might want to perform special
1765 * operation on specific ioctl. For instance on wait idle some hw
1766 * might want to perform and HDP flush through MMIO as it seems that
1767 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1768 * through ring.
1769 */
1770 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1771 /* check if 3D engine is idle */
1772 bool (*gui_idle)(struct radeon_device *rdev);
1773 /* wait for mc_idle */
1774 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1775 /* get the reference clock */
1776 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1777 /* get the gpu clock counter */
1778 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1779 /* gart */
c5b3b850
AD		 1780 struct {
1781 void (*tlb_flush)(struct radeon_device *rdev);
7f90fc96
CK		 1782 void (*set_page)(struct radeon_device *rdev, unsigned i,
1783 uint64_t addr);
c5b3b850 1784 } gart;
05b07147
CK		 1785 struct {
1786 int (*init)(struct radeon_device *rdev);
1787 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1788 void (*set_page)(struct radeon_device *rdev,
1789 struct radeon_ib *ib,
1790 uint64_t pe,
dce34bfd
CK		 1791 uint64_t addr, unsigned count,
1792 uint32_t incr, uint32_t flags);
05b07147 1793 } vm;
54e88e06 1794 /* ring specific callbacks */
76a0df85 1795 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1796 /* irqs */
b35ea4ab
AD		 1797 struct {
1798 int (*set)(struct radeon_device *rdev);
1799 int (*process)(struct radeon_device *rdev);
1800 } irq;
54e88e06 1801 /* displays */
c79a49ca
AD		 1802 struct {
1803 /* display watermarks */
1804 void (*bandwidth_update)(struct radeon_device *rdev);
1805 /* get frame count */
1806 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1807 /* wait for vblank */
1808 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1809 /* set backlight level */
1810 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1811 /* get backlight level */
1812 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1813 /* audio callbacks */
1814 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1815 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1816 } display;
54e88e06 1817 /* copy functions for bo handling */
27cd7769
AD		 1818 struct {
1819 int (*blit)(struct radeon_device *rdev,
1820 uint64_t src_offset,
1821 uint64_t dst_offset,
1822 unsigned num_gpu_pages,
876dc9f3 1823 struct radeon_fence **fence);
27cd7769
AD		 1824 u32 blit_ring_index;
1825 int (*dma)(struct radeon_device *rdev,
1826 uint64_t src_offset,
1827 uint64_t dst_offset,
1828 unsigned num_gpu_pages,
876dc9f3 1829 struct radeon_fence **fence);
27cd7769
AD		 1830 u32 dma_ring_index;
1831 /* method used for bo copy */
1832 int (*copy)(struct radeon_device *rdev,
1833 uint64_t src_offset,
1834 uint64_t dst_offset,
1835 unsigned num_gpu_pages,
876dc9f3 1836 struct radeon_fence **fence);
27cd7769
AD		 1837 /* ring used for bo copies */
1838 u32 copy_ring_index;
1839 } copy;
54e88e06 1840 /* surfaces */
9e6f3d02
AD		 1841 struct {
1842 int (*set_reg)(struct radeon_device *rdev, int reg,
1843 uint32_t tiling_flags, uint32_t pitch,
1844 uint32_t offset, uint32_t obj_size);
1845 void (*clear_reg)(struct radeon_device *rdev, int reg);
1846 } surface;
54e88e06 1847 /* hotplug detect */
901ea57d
AD		 1848 struct {
1849 void (*init)(struct radeon_device *rdev);
1850 void (*fini)(struct radeon_device *rdev);
1851 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1852 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1853 } hpd;
da321c8a 1854 /* static power management */
a02fa397
AD		 1855 struct {
1856 void (*misc)(struct radeon_device *rdev);
1857 void (*prepare)(struct radeon_device *rdev);
1858 void (*finish)(struct radeon_device *rdev);
1859 void (*init_profile)(struct radeon_device *rdev);
1860 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1861 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1862 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1863 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1864 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1865 int (*get_pcie_lanes)(struct radeon_device *rdev);
1866 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1867 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1868 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1869 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1870 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1871 } pm;
da321c8a
AD		 1872 /* dynamic power management */
1873 struct {
1874 int (*init)(struct radeon_device *rdev);
1875 void (*setup_asic)(struct radeon_device *rdev);
1876 int (*enable)(struct radeon_device *rdev);
914a8987 1877 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1878 void (*disable)(struct radeon_device *rdev);
84dd1928 1879 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1880 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1881 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1882 void (*display_configuration_changed)(struct radeon_device *rdev);
1883 void (*fini)(struct radeon_device *rdev);
1884 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1885 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1886 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1887 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1888 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1889 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1890 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1891 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1892 } dpm;
6f34be50 1893 /* pageflipping */
0f9e006c 1894 struct {
157fa14d
CK		 1895 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1896 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 1897 } pflip;
771fe6b9
JG		 1898};
1899
21f9a437
JG		 1900/*
1901 * Asic structures
1902 */
551ebd83 1903struct r100_asic {
225758d8
JG		 1904 const unsigned *reg_safe_bm;
1905 unsigned reg_safe_bm_size;
1906 u32 hdp_cntl;
551ebd83
DA		 1907};
1908
21f9a437 1909struct r300_asic {
225758d8
JG		 1910 const unsigned *reg_safe_bm;
1911 unsigned reg_safe_bm_size;
1912 u32 resync_scratch;
1913 u32 hdp_cntl;
21f9a437
JG		 1914};
1915
1916struct r600_asic {
225758d8
JG		 1917 unsigned max_pipes;
1918 unsigned max_tile_pipes;
1919 unsigned max_simds;
1920 unsigned max_backends;
1921 unsigned max_gprs;
1922 unsigned max_threads;
1923 unsigned max_stack_entries;
1924 unsigned max_hw_contexts;
1925 unsigned max_gs_threads;
1926 unsigned sx_max_export_size;
1927 unsigned sx_max_export_pos_size;
1928 unsigned sx_max_export_smx_size;
1929 unsigned sq_num_cf_insts;
1930 unsigned tiling_nbanks;
1931 unsigned tiling_npipes;
1932 unsigned tiling_group_size;
e7aeeba6 1933 unsigned tile_config;
e55b9422 1934 unsigned backend_map;
21f9a437
JG		 1935};
1936
1937struct rv770_asic {
225758d8
JG		 1938 unsigned max_pipes;
1939 unsigned max_tile_pipes;
1940 unsigned max_simds;
1941 unsigned max_backends;
1942 unsigned max_gprs;
1943 unsigned max_threads;
1944 unsigned max_stack_entries;
1945 unsigned max_hw_contexts;
1946 unsigned max_gs_threads;
1947 unsigned sx_max_export_size;
1948 unsigned sx_max_export_pos_size;
1949 unsigned sx_max_export_smx_size;
1950 unsigned sq_num_cf_insts;
1951 unsigned sx_num_of_sets;
1952 unsigned sc_prim_fifo_size;
1953 unsigned sc_hiz_tile_fifo_size;
1954 unsigned sc_earlyz_tile_fifo_fize;
1955 unsigned tiling_nbanks;
1956 unsigned tiling_npipes;
1957 unsigned tiling_group_size;
e7aeeba6 1958 unsigned tile_config;
e55b9422 1959 unsigned backend_map;
21f9a437
JG		 1960};
1961
32fcdbf4
AD		 1962struct evergreen_asic {
1963 unsigned num_ses;
1964 unsigned max_pipes;
1965 unsigned max_tile_pipes;
1966 unsigned max_simds;
1967 unsigned max_backends;
1968 unsigned max_gprs;
1969 unsigned max_threads;
1970 unsigned max_stack_entries;
1971 unsigned max_hw_contexts;
1972 unsigned max_gs_threads;
1973 unsigned sx_max_export_size;
1974 unsigned sx_max_export_pos_size;
1975 unsigned sx_max_export_smx_size;
1976 unsigned sq_num_cf_insts;
1977 unsigned sx_num_of_sets;
1978 unsigned sc_prim_fifo_size;
1979 unsigned sc_hiz_tile_fifo_size;
1980 unsigned sc_earlyz_tile_fifo_size;
1981 unsigned tiling_nbanks;
1982 unsigned tiling_npipes;
1983 unsigned tiling_group_size;
e7aeeba6 1984 unsigned tile_config;
e55b9422 1985 unsigned backend_map;
32fcdbf4
AD		 1986};
1987
fecf1d07
AD		 1988struct cayman_asic {
1989 unsigned max_shader_engines;
1990 unsigned max_pipes_per_simd;
1991 unsigned max_tile_pipes;
1992 unsigned max_simds_per_se;
1993 unsigned max_backends_per_se;
1994 unsigned max_texture_channel_caches;
1995 unsigned max_gprs;
1996 unsigned max_threads;
1997 unsigned max_gs_threads;
1998 unsigned max_stack_entries;
1999 unsigned sx_num_of_sets;
2000 unsigned sx_max_export_size;
2001 unsigned sx_max_export_pos_size;
2002 unsigned sx_max_export_smx_size;
2003 unsigned max_hw_contexts;
2004 unsigned sq_num_cf_insts;
2005 unsigned sc_prim_fifo_size;
2006 unsigned sc_hiz_tile_fifo_size;
2007 unsigned sc_earlyz_tile_fifo_size;
2008
2009 unsigned num_shader_engines;
2010 unsigned num_shader_pipes_per_simd;
2011 unsigned num_tile_pipes;
2012 unsigned num_simds_per_se;
2013 unsigned num_backends_per_se;
2014 unsigned backend_disable_mask_per_asic;
2015 unsigned backend_map;
2016 unsigned num_texture_channel_caches;
2017 unsigned mem_max_burst_length_bytes;
2018 unsigned mem_row_size_in_kb;
2019 unsigned shader_engine_tile_size;
2020 unsigned num_gpus;
2021 unsigned multi_gpu_tile_size;
2022
2023 unsigned tile_config;
fecf1d07
AD		 2024};
2025
0a96d72b
AD		 2026struct si_asic {
2027 unsigned max_shader_engines;
0a96d72b 2028 unsigned max_tile_pipes;
1a8ca750
AD		 2029 unsigned max_cu_per_sh;
2030 unsigned max_sh_per_se;
0a96d72b
AD		 2031 unsigned max_backends_per_se;
2032 unsigned max_texture_channel_caches;
2033 unsigned max_gprs;
2034 unsigned max_gs_threads;
2035 unsigned max_hw_contexts;
2036 unsigned sc_prim_fifo_size_frontend;
2037 unsigned sc_prim_fifo_size_backend;
2038 unsigned sc_hiz_tile_fifo_size;
2039 unsigned sc_earlyz_tile_fifo_size;
2040
0a96d72b 2041 unsigned num_tile_pipes;
439a1cff 2042 unsigned backend_enable_mask;
0a96d72b
AD		 2043 unsigned backend_disable_mask_per_asic;
2044 unsigned backend_map;
2045 unsigned num_texture_channel_caches;
2046 unsigned mem_max_burst_length_bytes;
2047 unsigned mem_row_size_in_kb;
2048 unsigned shader_engine_tile_size;
2049 unsigned num_gpus;
2050 unsigned multi_gpu_tile_size;
2051
2052 unsigned tile_config;
64d7b8be 2053 uint32_t tile_mode_array[32];
0a96d72b
AD		 2054};
2055
8cc1a532
AD		 2056struct cik_asic {
2057 unsigned max_shader_engines;
2058 unsigned max_tile_pipes;
2059 unsigned max_cu_per_sh;
2060 unsigned max_sh_per_se;
2061 unsigned max_backends_per_se;
2062 unsigned max_texture_channel_caches;
2063 unsigned max_gprs;
2064 unsigned max_gs_threads;
2065 unsigned max_hw_contexts;
2066 unsigned sc_prim_fifo_size_frontend;
2067 unsigned sc_prim_fifo_size_backend;
2068 unsigned sc_hiz_tile_fifo_size;
2069 unsigned sc_earlyz_tile_fifo_size;
2070
2071 unsigned num_tile_pipes;
439a1cff 2072 unsigned backend_enable_mask;
8cc1a532
AD		 2073 unsigned backend_disable_mask_per_asic;
2074 unsigned backend_map;
2075 unsigned num_texture_channel_caches;
2076 unsigned mem_max_burst_length_bytes;
2077 unsigned mem_row_size_in_kb;
2078 unsigned shader_engine_tile_size;
2079 unsigned num_gpus;
2080 unsigned multi_gpu_tile_size;
2081
2082 unsigned tile_config;
39aee490 2083 uint32_t tile_mode_array[32];
32f79a8a 2084 uint32_t macrotile_mode_array[16];
8cc1a532
AD		 2085};
2086
068a117c
JG		 2087union radeon_asic_config {
2088 struct r300_asic r300;
551ebd83 2089 struct r100_asic r100;
3ce0a23d
JG		 2090 struct r600_asic r600;
2091 struct rv770_asic rv770;
32fcdbf4 2092 struct evergreen_asic evergreen;
fecf1d07 2093 struct cayman_asic cayman;
0a96d72b 2094 struct si_asic si;
8cc1a532 2095 struct cik_asic cik;
068a117c
JG		 2096};
2097
0a10c851
DV		 2098/*
2099 * asic initizalization from radeon_asic.c
2100 */
2101void radeon_agp_disable(struct radeon_device *rdev);
2102int radeon_asic_init(struct radeon_device *rdev);
2103
771fe6b9
JG		 2104
2105/*
2106 * IOCTL.
2107 */
2108int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2109 struct drm_file *filp);
2110int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2111 struct drm_file *filp);
2112int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2113 struct drm_file *file_priv);
2114int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2115 struct drm_file *file_priv);
2116int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2117 struct drm_file *file_priv);
2118int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2119 struct drm_file *file_priv);
2120int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2121 struct drm_file *filp);
2122int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2123 struct drm_file *filp);
2124int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2125 struct drm_file *filp);
2126int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2127 struct drm_file *filp);
721604a1
JG		 2128int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2129 struct drm_file *filp);
bda72d58
MO		 2130int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2131 struct drm_file *filp);
771fe6b9 2132int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2133int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2134 struct drm_file *filp);
2135int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2136 struct drm_file *filp);
771fe6b9 2137
16cdf04d
AD		 2138/* VRAM scratch page for HDP bug, default vram page */
2139struct r600_vram_scratch {
87cbf8f2
AD		 2140 struct radeon_bo *robj;
2141 volatile uint32_t *ptr;
16cdf04d 2142 u64 gpu_addr;
87cbf8f2 2143};
771fe6b9 2144
fd64ca8a
LT		 2145/*
2146 * ACPI
2147 */
2148struct radeon_atif_notification_cfg {
2149 bool enabled;
2150 int command_code;
2151};
2152
2153struct radeon_atif_notifications {
2154 bool display_switch;
2155 bool expansion_mode_change;
2156 bool thermal_state;
2157 bool forced_power_state;
2158 bool system_power_state;
2159 bool display_conf_change;
2160 bool px_gfx_switch;
2161 bool brightness_change;
2162 bool dgpu_display_event;
2163};
2164
2165struct radeon_atif_functions {
2166 bool system_params;
2167 bool sbios_requests;
2168 bool select_active_disp;
2169 bool lid_state;
2170 bool get_tv_standard;
2171 bool set_tv_standard;
2172 bool get_panel_expansion_mode;
2173 bool set_panel_expansion_mode;
2174 bool temperature_change;
2175 bool graphics_device_types;
2176};
2177
2178struct radeon_atif {
2179 struct radeon_atif_notifications notifications;
2180 struct radeon_atif_functions functions;
2181 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2182 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2183};
7a1619b9 2184
e3a15920
AD		 2185struct radeon_atcs_functions {
2186 bool get_ext_state;
2187 bool pcie_perf_req;
2188 bool pcie_dev_rdy;
2189 bool pcie_bus_width;
2190};
2191
2192struct radeon_atcs {
2193 struct radeon_atcs_functions functions;
2194};
2195
771fe6b9
JG		 2196/*
2197 * Core structure, functions and helpers.
2198 */
2199typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2200typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2201
2202struct radeon_device {
9f022ddf 2203 struct device *dev;
771fe6b9
JG		 2204 struct drm_device *ddev;
2205 struct pci_dev *pdev;
dee53e7f 2206 struct rw_semaphore exclusive_lock;
771fe6b9 2207 /* ASIC */
068a117c 2208 union radeon_asic_config config;
771fe6b9
JG		 2209 enum radeon_family family;
2210 unsigned long flags;
2211 int usec_timeout;
2212 enum radeon_pll_errata pll_errata;
2213 int num_gb_pipes;
f779b3e5 2214 int num_z_pipes;
771fe6b9
JG		 2215 int disp_priority;
2216 /* BIOS */
2217 uint8_t *bios;
2218 bool is_atom_bios;
2219 uint16_t bios_header_start;
4c788679 2220 struct radeon_bo *stollen_vga_memory;
771fe6b9 2221 /* Register mmio */
4c9bc75c
DA		 2222 resource_size_t rmmio_base;
2223 resource_size_t rmmio_size;
2c385151
DV		 2224 /* protects concurrent MM_INDEX/DATA based register access */
2225 spinlock_t mmio_idx_lock;
fe78118c
AD		 2226 /* protects concurrent SMC based register access */
2227 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2228 /* protects concurrent PLL register access */
2229 spinlock_t pll_idx_lock;
2230 /* protects concurrent MC register access */
2231 spinlock_t mc_idx_lock;
2232 /* protects concurrent PCIE register access */
2233 spinlock_t pcie_idx_lock;
2234 /* protects concurrent PCIE_PORT register access */
2235 spinlock_t pciep_idx_lock;
2236 /* protects concurrent PIF register access */
2237 spinlock_t pif_idx_lock;
2238 /* protects concurrent CG register access */
2239 spinlock_t cg_idx_lock;
2240 /* protects concurrent UVD register access */
2241 spinlock_t uvd_idx_lock;
2242 /* protects concurrent RCU register access */
2243 spinlock_t rcu_idx_lock;
2244 /* protects concurrent DIDT register access */
2245 spinlock_t didt_idx_lock;
2246 /* protects concurrent ENDPOINT (audio) register access */
2247 spinlock_t end_idx_lock;
a0533fbf 2248 void __iomem *rmmio;
771fe6b9
JG		 2249 radeon_rreg_t mc_rreg;
2250 radeon_wreg_t mc_wreg;
2251 radeon_rreg_t pll_rreg;
2252 radeon_wreg_t pll_wreg;
de1b2898 2253 uint32_t pcie_reg_mask;
771fe6b9
JG		 2254 radeon_rreg_t pciep_rreg;
2255 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2256 /* io port */
2257 void __iomem *rio_mem;
2258 resource_size_t rio_mem_size;
771fe6b9
JG		 2259 struct radeon_clock clock;
2260 struct radeon_mc mc;
2261 struct radeon_gart gart;
2262 struct radeon_mode_info mode_info;
2263 struct radeon_scratch scratch;
75efdee1 2264 struct radeon_doorbell doorbell;
771fe6b9 2265 struct radeon_mman mman;
7465280c 2266 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2267 wait_queue_head_t fence_queue;
d6999bc7 2268 struct mutex ring_lock;
e32eb50d 2269 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2270 bool ib_pool_ready;
2271 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2272 struct radeon_irq irq;
2273 struct radeon_asic *asic;
2274 struct radeon_gem gem;
c93bb85b 2275 struct radeon_pm pm;
f2ba57b5 2276 struct radeon_uvd uvd;
d93f7937 2277 struct radeon_vce vce;
f657c2a7 2278 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2279 struct radeon_wb wb;
3ce0a23d 2280 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2281 bool shutdown;
2282 bool suspend;
ad49f501 2283 bool need_dma32;
733289c2 2284 bool accel_working;
a0a53aa8 2285 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2286 bool needs_reset;
e024e110 2287 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2288 const struct firmware *me_fw; /* all family ME firmware */
2289 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2290 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2291 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2292 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2293 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2294 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2295 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2296 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2297 const struct firmware *vce_fw; /* VCE firmware */
16cdf04d 2298 struct r600_vram_scratch vram_scratch;
3e5cb98d 2299 int msi_enabled; /* msi enabled */
d8f60cfc 2300 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2301 struct radeon_rlc rlc;
963e81f9 2302 struct radeon_mec mec;
d4877cf2 2303 struct work_struct hotplug_work;
f122c610 2304 struct work_struct audio_work;
8f61b34c 2305 struct work_struct reset_work;
18917b60 2306 int num_crtc; /* number of crtcs */
40bacf16 2307 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2308 bool has_uvd;
b530602f 2309 struct r600_audio audio; /* audio stuff */
ce8f5370 2310 struct notifier_block acpi_nb;
9eba4a93 2311 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2312 struct drm_file *hyperz_filp;
9eba4a93 2313 struct drm_file *cmask_filp;
f376b94f
AD		 2314 /* i2c buses */
2315 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2316 /* debugfs */
2317 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2318 unsigned debugfs_count;
721604a1
JG		 2319 /* virtual memory */
2320 struct radeon_vm_manager vm_manager;
6759a0a7 2321 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2322 /* memory stats */
2323 atomic64_t vram_usage;
2324 atomic64_t gtt_usage;
2325 atomic64_t num_bytes_moved;
fd64ca8a
LT		 2326 /* ACPI interface */
2327 struct radeon_atif atif;
e3a15920 2328 struct radeon_atcs atcs;
f61d5b46
AD		 2329 /* srbm instance registers */
2330 struct mutex srbm_mutex;
64d8a728
AD		 2331 /* clock, powergating flags */
2332 u32 cg_flags;
2333 u32 pg_flags;
10ebc0bc
DA		 2334
2335 struct dev_pm_domain vga_pm_domain;
2336 bool have_disp_power_ref;
771fe6b9
JG		 2337};
2338
90c4cde9 2339bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2340int radeon_device_init(struct radeon_device *rdev,
2341 struct drm_device *ddev,
2342 struct pci_dev *pdev,
2343 uint32_t flags);
2344void radeon_device_fini(struct radeon_device *rdev);
2345int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2346
2ef9bdfe
DV		 2347uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2348 bool always_indirect);
2349void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2350 bool always_indirect);
6fcbef7a
AK		 2351u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2352void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2353
d5754ab8
AL		 2354u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2355void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2356
4c788679
JG		 2357/*
2358 * Cast helper
2359 */
2360#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2361
2362/*
2363 * Registers read & write functions.
2364 */
a0533fbf
BH		 2365#define RREG8(reg) readb((rdev->rmmio) + (reg))
2366#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2367#define RREG16(reg) readw((rdev->rmmio) + (reg))
2368#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2369#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2370#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2371#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2372#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2373#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2374#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2375#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2376#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2377#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2378#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2379#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2380#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2381#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2382#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2383#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2384#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2385#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2386#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2387#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2388#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2389#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2390#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2391#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2392#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2393#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2394#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2395#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2396#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2397#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2398#define WREG32_P(reg, val, mask) \
2399 do { \
2400 uint32_t tmp_ = RREG32(reg); \
2401 tmp_ &= (mask); \
2402 tmp_ |= ((val) & ~(mask)); \
2403 WREG32(reg, tmp_); \
2404 } while (0)
d5169fc4 2405#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2406#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2407#define WREG32_PLL_P(reg, val, mask) \
2408 do { \
2409 uint32_t tmp_ = RREG32_PLL(reg); \
2410 tmp_ &= (mask); \
2411 tmp_ |= ((val) & ~(mask)); \
2412 WREG32_PLL(reg, tmp_); \
2413 } while (0)
2ef9bdfe 2414#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2415#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2416#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2417
d5754ab8
AL		 2418#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2419#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2420
de1b2898
DA		 2421/*
2422 * Indirect registers accessor
2423 */
2424static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2425{
0a5b7b0b 2426 unsigned long flags;
de1b2898
DA		 2427 uint32_t r;
2428
0a5b7b0b 2429 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2430 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2431 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2432 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2433 return r;
2434}
2435
2436static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2437{
0a5b7b0b
AD		 2438 unsigned long flags;
2439
2440 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2441 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2442 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2443 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2444}
2445
1d5d0c34
AD		 2446static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2447{
fe78118c 2448 unsigned long flags;
1d5d0c34
AD		 2449 u32 r;
2450
fe78118c 2451 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2452 WREG32(TN_SMC_IND_INDEX_0, (reg));
2453 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2454 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2455 return r;
2456}
2457
2458static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2459{
fe78118c
AD		 2460 unsigned long flags;
2461
2462 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2463 WREG32(TN_SMC_IND_INDEX_0, (reg));
2464 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2465 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2466}
2467
ff82bbc4
AD		 2468static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2469{
0a5b7b0b 2470 unsigned long flags;
ff82bbc4
AD		 2471 u32 r;
2472
0a5b7b0b 2473 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2474 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2475 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2476 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2477 return r;
2478}
2479
2480static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2481{
0a5b7b0b
AD		 2482 unsigned long flags;
2483
2484 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2485 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2486 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2487 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2488}
2489
46f9564a
AD		 2490static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2491{
0a5b7b0b 2492 unsigned long flags;
46f9564a
AD		 2493 u32 r;
2494
0a5b7b0b 2495 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2496 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2497 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2498 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2499 return r;
2500}
2501
2502static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2503{
0a5b7b0b
AD		 2504 unsigned long flags;
2505
2506 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2507 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2508 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2509 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2510}
2511
792edd69
AD		 2512static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2513{
0a5b7b0b 2514 unsigned long flags;
792edd69
AD		 2515 u32 r;
2516
0a5b7b0b 2517 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2518 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2519 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2520 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2521 return r;
2522}
2523
2524static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2525{
0a5b7b0b
AD		 2526 unsigned long flags;
2527
2528 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2529 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2530 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2531 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2532}
2533
2534static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2535{
0a5b7b0b 2536 unsigned long flags;
792edd69
AD		 2537 u32 r;
2538
0a5b7b0b 2539 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2540 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2541 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2542 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2543 return r;
2544}
2545
2546static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2547{
0a5b7b0b
AD		 2548 unsigned long flags;
2549
2550 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2551 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2552 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2553 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2554}
2555
93656cdd
AD		 2556static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2557{
0a5b7b0b 2558 unsigned long flags;
93656cdd
AD		 2559 u32 r;
2560
0a5b7b0b 2561 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2562 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2563 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2564 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2565 return r;
2566}
2567
2568static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2569{
0a5b7b0b
AD		 2570 unsigned long flags;
2571
2572 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2573 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2574 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2575 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2576}
2577
1d58234d
AD		 2578
2579static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2580{
0a5b7b0b 2581 unsigned long flags;
1d58234d
AD		 2582 u32 r;
2583
0a5b7b0b 2584 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2585 WREG32(CIK_DIDT_IND_INDEX, (reg));
2586 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2587 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2588 return r;
2589}
2590
2591static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2592{
0a5b7b0b
AD		 2593 unsigned long flags;
2594
2595 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2596 WREG32(CIK_DIDT_IND_INDEX, (reg));
2597 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2598 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2599}
2600
771fe6b9
JG		 2601void r100_pll_errata_after_index(struct radeon_device *rdev);
2602
2603
2604/*
2605 * ASICs helpers.
2606 */
b995e433
DA		 2607#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2608 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2609#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2610 (rdev->family == CHIP_RV200) || \
2611 (rdev->family == CHIP_RS100) || \
2612 (rdev->family == CHIP_RS200) || \
2613 (rdev->family == CHIP_RV250) || \
2614 (rdev->family == CHIP_RV280) || \
2615 (rdev->family == CHIP_RS300))
2616#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2617 (rdev->family == CHIP_RV350) || \
2618 (rdev->family == CHIP_R350) || \
2619 (rdev->family == CHIP_RV380) || \
2620 (rdev->family == CHIP_R420) || \
2621 (rdev->family == CHIP_R423) || \
2622 (rdev->family == CHIP_RV410) || \
2623 (rdev->family == CHIP_RS400) || \
2624 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2625#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2626 (rdev->ddev->pdev->device == 0x9443) || \
2627 (rdev->ddev->pdev->device == 0x944B) || \
2628 (rdev->ddev->pdev->device == 0x9506) || \
2629 (rdev->ddev->pdev->device == 0x9509) || \
2630 (rdev->ddev->pdev->device == 0x950F) || \
2631 (rdev->ddev->pdev->device == 0x689C) || \
2632 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2633#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2634#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2635 (rdev->family == CHIP_RS690) || \
2636 (rdev->family == CHIP_RS740) || \
2637 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2638#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2639#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2640#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2641#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2642 (rdev->flags & RADEON_IS_IGP))
1fe18305 2643#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2644#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2645#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2646 (rdev->flags & RADEON_IS_IGP))
624d3524 2647#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2648#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2649#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2650#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2651#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2652#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2653 (rdev->family == CHIP_MULLINS))
771fe6b9 2654
dc50ba7f
AD		 2655#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2656 (rdev->ddev->pdev->device == 0x6850) || \
2657 (rdev->ddev->pdev->device == 0x6858) || \
2658 (rdev->ddev->pdev->device == 0x6859) || \
2659 (rdev->ddev->pdev->device == 0x6840) || \
2660 (rdev->ddev->pdev->device == 0x6841) || \
2661 (rdev->ddev->pdev->device == 0x6842) || \
2662 (rdev->ddev->pdev->device == 0x6843))
2663
771fe6b9
JG		 2664/*
2665 * BIOS helpers.
2666 */
2667#define RBIOS8(i) (rdev->bios[i])
2668#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2669#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2670
2671int radeon_combios_init(struct radeon_device *rdev);
2672void radeon_combios_fini(struct radeon_device *rdev);
2673int radeon_atombios_init(struct radeon_device *rdev);
2674void radeon_atombios_fini(struct radeon_device *rdev);
2675
2676
2677/*
2678 * RING helpers.
2679 */
ce580fab 2680#if DRM_DEBUG_CODE == 0
e32eb50d 2681static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2682{
e32eb50d
CK		 2683 ring->ring[ring->wptr++] = v;
2684 ring->wptr &= ring->ptr_mask;
2685 ring->count_dw--;
2686 ring->ring_free_dw--;
771fe6b9 2687}
ce580fab
AK		 2688#else
2689/* With debugging this is just too big to inline */
e32eb50d 2690void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2691#endif
771fe6b9
JG		 2692
2693/*
2694 * ASICs macro.
2695 */
068a117c 2696#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2697#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2698#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2699#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2700#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2701#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2702#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2703#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2704#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2705#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2706#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2707#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2708#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2709#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2710#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2711#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2712#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2713#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2714#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2715#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2716#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2717#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2718#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2719#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2720#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2721#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2722#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2723#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2724#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2725#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2726#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2727#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2728#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2729#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2730#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2731#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2732#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2733#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2734#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2735#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2736#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2737#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2738#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2739#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2740#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2741#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2742#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2743#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2744#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2745#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2746#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2747#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2748#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2749#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2750#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2751#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2752#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2753#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2754#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2755#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2756#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2757#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2758#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2759#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2760#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2761#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2762#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2763#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2764#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2765#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2766#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2767#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2768#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2769#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2770#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2771#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2772#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2773#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2774#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2775#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2776#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2777#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2778#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2779#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2780
6cf8a3f5 2781/* Common functions */
700a0cc0 2782/* AGP */
90aca4d2 2783extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2784extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2785extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2786extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2787extern int radeon_modeset_init(struct radeon_device *rdev);
2788extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2789extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2790extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2791extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2792extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2793extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2794extern void radeon_wb_fini(struct radeon_device *rdev);
2795extern int radeon_wb_init(struct radeon_device *rdev);
2796extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2797extern void radeon_surface_init(struct radeon_device *rdev);
2798extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2799extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2800extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2801extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2802extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2803extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2804extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2805extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2806extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2807extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2808extern void radeon_program_register_sequence(struct radeon_device *rdev,
2809 const u32 *registers,
2810 const u32 array_size);
6cf8a3f5 2811
721604a1
JG		 2812/*
2813 * vm
2814 */
2815int radeon_vm_manager_init(struct radeon_device *rdev);
2816void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2817int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2818void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
df0af440
CK		 2819struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2820 struct radeon_vm *vm,
2821 struct list_head *head);
ee60e29f
CK		 2822struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2823 struct radeon_vm *vm, int ring);
fa688343
CK		 2824void radeon_vm_flush(struct radeon_device *rdev,
2825 struct radeon_vm *vm,
2826 int ring);
ee60e29f
CK		 2827void radeon_vm_fence(struct radeon_device *rdev,
2828 struct radeon_vm *vm,
2829 struct radeon_fence *fence);
dce34bfd 2830uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2831int radeon_vm_update_page_directory(struct radeon_device *rdev,
2832 struct radeon_vm *vm);
9c57a6bd
CK		 2833int radeon_vm_bo_update(struct radeon_device *rdev,
2834 struct radeon_vm *vm,
2835 struct radeon_bo *bo,
2836 struct ttm_mem_reg *mem);
721604a1
JG		 2837void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2838 struct radeon_bo *bo);
421ca7ab
CK		 2839struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2840 struct radeon_bo *bo);
e971bd5e
CK		 2841struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2842 struct radeon_vm *vm,
2843 struct radeon_bo *bo);
2844int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2845 struct radeon_bo_va *bo_va,
2846 uint64_t offset,
2847 uint32_t flags);
721604a1 2848int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2849 struct radeon_bo_va *bo_va);
721604a1 2850
f122c610
AD		 2851/* audio */
2852void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2853struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2854struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2855void r600_audio_enable(struct radeon_device *rdev,
2856 struct r600_audio_pin *pin,
2857 bool enable);
2858void dce6_audio_enable(struct radeon_device *rdev,
2859 struct r600_audio_pin *pin,
2860 bool enable);
721604a1 2861
16cdf04d
AD		 2862/*
2863 * R600 vram scratch functions
2864 */
2865int r600_vram_scratch_init(struct radeon_device *rdev);
2866void r600_vram_scratch_fini(struct radeon_device *rdev);
2867
285484e2
JG		 2868/*
2869 * r600 cs checking helper
2870 */
2871unsigned r600_mip_minify(unsigned size, unsigned level);
2872bool r600_fmt_is_valid_color(u32 format);
2873bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2874int r600_fmt_get_blocksize(u32 format);
2875int r600_fmt_get_nblocksx(u32 format, u32 w);
2876int r600_fmt_get_nblocksy(u32 format, u32 h);
2877
3574dda4
DV		 2878/*
2879 * r600 functions used by radeon_encoder.c
2880 */
1b688d08
RM		 2881struct radeon_hdmi_acr {
2882 u32 clock;
2883
2884 int n_32khz;
2885 int cts_32khz;
2886
2887 int n_44_1khz;
2888 int cts_44_1khz;
2889
2890 int n_48khz;
2891 int cts_48khz;
2892
2893};
2894
e55d3e6c
RM		 2895extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2896
416a2bd2
AD		 2897extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2898 u32 tiling_pipe_num,
2899 u32 max_rb_num,
2900 u32 total_max_rb_num,
2901 u32 enabled_rb_mask);
fe251e2f 2902
e55d3e6c
RM		 2903/*
2904 * evergreen functions used by radeon_encoder.c
2905 */
2906
0af62b01 2907extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2908extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2909
c4917074
AD		 2910/* radeon_acpi.c */
2911#if defined(CONFIG_ACPI)
2912extern int radeon_acpi_init(struct radeon_device *rdev);
2913extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2914extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2915extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2916 u8 perf_req, bool advertise);
dc50ba7f 2917extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2918#else
2919static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2920static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2921#endif
d7a2952f 2922
c38f34b5
IH		 2923int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2924 struct radeon_cs_packet *pkt,
2925 unsigned idx);
9ffb7a6d 2926bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2927void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2928 struct radeon_cs_packet *pkt);
e9716993
IH		 2929int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2930 struct radeon_cs_reloc **cs_reloc,
2931 int nomm);
40592a17
IH		 2932int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2933 uint32_t *vline_start_end,
2934 uint32_t *vline_status);
c38f34b5 2935
4c788679
JG		 2936#include "radeon_object.h"
2937
771fe6b9 2938#endif
Linux 6.x block layer and io_uring tree(s)