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drm/radeon: convert SI,CIK to use sumo_rlc functions
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
771fe6b9
JG		 101
102/*
103 * Copy from radeon_drv.h so we don't have to include both and have conflicting
104 * symbol;
105 */
bb635567
JG		 106#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 108/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 109#define RADEON_IB_POOL_SIZE 16
110#define RADEON_DEBUGFS_MAX_COMPONENTS 32
111#define RADEONFB_CONN_LIMIT 4
112#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 113
1b37078b 114/* max number of rings */
f2ba57b5 115#define RADEON_NUM_RINGS 6
bb635567
JG		 116
117/* fence seq are set to this number when signaled */
118#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 119
120/* internal ring indices */
121/* r1xx+ has gfx CP ring */
f2ba57b5 122#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 123
124/* cayman has 2 compute CP rings */
f2ba57b5
CK		 125#define CAYMAN_RING_TYPE_CP1_INDEX 1
126#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 127
4d75658b
AD		 128/* R600+ has an async dma ring */
129#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 130/* cayman add a second async dma ring */
131#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 132
f2ba57b5
CK		 133/* R600+ */
134#define R600_RING_TYPE_UVD_INDEX 5
135
721604a1 136/* hardcode those limit for now */
ca19f21e 137#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 138#define RADEON_VA_RESERVED_SIZE (8 << 20)
139#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 140
ec46c76d
AD		 141/* reset flags */
142#define RADEON_RESET_GFX (1 << 0)
143#define RADEON_RESET_COMPUTE (1 << 1)
144#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 145#define RADEON_RESET_CP (1 << 3)
146#define RADEON_RESET_GRBM (1 << 4)
147#define RADEON_RESET_DMA1 (1 << 5)
148#define RADEON_RESET_RLC (1 << 6)
149#define RADEON_RESET_SEM (1 << 7)
150#define RADEON_RESET_IH (1 << 8)
151#define RADEON_RESET_VMC (1 << 9)
152#define RADEON_RESET_MC (1 << 10)
153#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 154
9e05fa1d
AD		 155/* max cursor sizes (in pixels) */
156#define CURSOR_WIDTH 64
157#define CURSOR_HEIGHT 64
158
159#define CIK_CURSOR_WIDTH 128
160#define CIK_CURSOR_HEIGHT 128
161
771fe6b9
JG		 162/*
163 * Errata workarounds.
164 */
165enum radeon_pll_errata {
166 CHIP_ERRATA_R300_CG = 0x00000001,
167 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
168 CHIP_ERRATA_PLL_DELAY = 0x00000004
169};
170
171
172struct radeon_device;
173
174
175/*
176 * BIOS.
177 */
178bool radeon_get_bios(struct radeon_device *rdev);
179
180/*
3ce0a23d 181 * Dummy page
771fe6b9 182 */
3ce0a23d
JG		 183struct radeon_dummy_page {
184 struct page *page;
185 dma_addr_t addr;
186};
187int radeon_dummy_page_init(struct radeon_device *rdev);
188void radeon_dummy_page_fini(struct radeon_device *rdev);
189
771fe6b9 190
3ce0a23d
JG		 191/*
192 * Clocks
193 */
771fe6b9
JG		 194struct radeon_clock {
195 struct radeon_pll p1pll;
196 struct radeon_pll p2pll;
bcc1c2a1 197 struct radeon_pll dcpll;
771fe6b9
JG		 198 struct radeon_pll spll;
199 struct radeon_pll mpll;
200 /* 10 Khz units */
201 uint32_t default_mclk;
202 uint32_t default_sclk;
bcc1c2a1 203 uint32_t default_dispclk;
4489cd62 204 uint32_t current_dispclk;
bcc1c2a1 205 uint32_t dp_extclk;
b20f9bef 206 uint32_t max_pixel_clock;
771fe6b9
JG		 207};
208
7433874e
RM		 209/*
210 * Power management
211 */
212int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 213void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 214void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 215void radeon_pm_suspend(struct radeon_device *rdev);
216void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 217void radeon_combios_get_power_modes(struct radeon_device *rdev);
218void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 219int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
220 u8 clock_type,
221 u32 clock,
222 bool strobe_mode,
223 struct atom_clock_dividers *dividers);
eaa778af
AD		 224int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
225 u32 clock,
226 bool strobe_mode,
227 struct atom_mpll_param *mpll_param);
8a83ec5e 228void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 229int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
230 u16 voltage_level, u8 voltage_type,
231 u32 *gpio_value, u32 *gpio_mask);
232void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
233 u32 eng_clock, u32 mem_clock);
234int radeon_atom_get_voltage_step(struct radeon_device *rdev,
235 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 236int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
237 u16 voltage_id, u16 *voltage);
beb79f40
AD		 238int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
239 u16 *voltage,
240 u16 leakage_idx);
ae5b0abb
AD		 241int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
242 u8 voltage_type,
243 u16 nominal_voltage,
244 u16 *true_voltage);
245int radeon_atom_get_min_voltage(struct radeon_device *rdev,
246 u8 voltage_type, u16 *min_voltage);
247int radeon_atom_get_max_voltage(struct radeon_device *rdev,
248 u8 voltage_type, u16 *max_voltage);
249int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 250 u8 voltage_type, u8 voltage_mode,
ae5b0abb 251 struct atom_voltage_table *voltage_table);
58653abd
AD		 252bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
253 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 254void radeon_atom_update_memory_dll(struct radeon_device *rdev,
255 u32 mem_clock);
256void radeon_atom_set_ac_timing(struct radeon_device *rdev,
257 u32 mem_clock);
258int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
259 u8 module_index,
260 struct atom_mc_reg_table *reg_table);
261int radeon_atom_get_memory_info(struct radeon_device *rdev,
262 u8 module_index, struct atom_memory_info *mem_info);
263int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
264 bool gddr5, u8 module_index,
265 struct atom_memory_clock_range_table *mclk_range_table);
266int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
267 u16 voltage_id, u16 *voltage);
f892034a 268void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 269extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
270 unsigned *bankh, unsigned *mtaspect,
271 unsigned *tile_split);
3ce0a23d 272
771fe6b9
JG		 273/*
274 * Fences.
275 */
276struct radeon_fence_driver {
277 uint32_t scratch_reg;
30eb77f4
JG		 278 uint64_t gpu_addr;
279 volatile uint32_t *cpu_addr;
68e250b7
CK		 280 /* sync_seq is protected by ring emission lock */
281 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 282 atomic64_t last_seq;
36abacae 283 unsigned long last_activity;
0a0c7596 284 bool initialized;
771fe6b9
JG		 285};
286
287struct radeon_fence {
288 struct radeon_device *rdev;
289 struct kref kref;
771fe6b9 290 /* protected by radeon_fence.lock */
bb635567 291 uint64_t seq;
7465280c 292 /* RB, DMA, etc. */
bb635567 293 unsigned ring;
771fe6b9
JG		 294};
295
30eb77f4
JG		 296int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
297int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 298void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 299void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 300int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 301void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 302bool radeon_fence_signaled(struct radeon_fence *fence);
303int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
8a47cc9e 304int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 305int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 306int radeon_fence_wait_any(struct radeon_device *rdev,
307 struct radeon_fence **fences,
308 bool intr);
771fe6b9
JG		 309struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
310void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 311unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 312bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
313void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
314static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
315 struct radeon_fence *b)
316{
317 if (!a) {
318 return b;
319 }
320
321 if (!b) {
322 return a;
323 }
324
325 BUG_ON(a->ring != b->ring);
326
327 if (a->seq > b->seq) {
328 return a;
329 } else {
330 return b;
331 }
332}
771fe6b9 333
ee60e29f
CK		 334static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
335 struct radeon_fence *b)
336{
337 if (!a) {
338 return false;
339 }
340
341 if (!b) {
342 return true;
343 }
344
345 BUG_ON(a->ring != b->ring);
346
347 return a->seq < b->seq;
348}
349
e024e110
DA		 350/*
351 * Tiling registers
352 */
353struct radeon_surface_reg {
4c788679 354 struct radeon_bo *bo;
e024e110
DA		 355};
356
357#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 358
359/*
4c788679 360 * TTM.
771fe6b9 361 */
4c788679
JG		 362struct radeon_mman {
363 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 364 struct drm_global_reference mem_global_ref;
4c788679 365 struct ttm_bo_device bdev;
0a0c7596
JG		 366 bool mem_global_referenced;
367 bool initialized;
4c788679
JG		 368};
369
721604a1
JG		 370/* bo virtual address in a specific vm */
371struct radeon_bo_va {
e971bd5e 372 /* protected by bo being reserved */
721604a1 373 struct list_head bo_list;
721604a1
JG		 374 uint64_t soffset;
375 uint64_t eoffset;
376 uint32_t flags;
377 bool valid;
e971bd5e
CK		 378 unsigned ref_count;
379
380 /* protected by vm mutex */
381 struct list_head vm_list;
382
383 /* constant after initialization */
384 struct radeon_vm *vm;
385 struct radeon_bo *bo;
721604a1
JG		 386};
387
4c788679
JG		 388struct radeon_bo {
389 /* Protected by gem.mutex */
390 struct list_head list;
391 /* Protected by tbo.reserved */
312ea8da
JG		 392 u32 placements[3];
393 struct ttm_placement placement;
4c788679
JG		 394 struct ttm_buffer_object tbo;
395 struct ttm_bo_kmap_obj kmap;
396 unsigned pin_count;
397 void *kptr;
398 u32 tiling_flags;
399 u32 pitch;
400 int surface_reg;
721604a1
JG		 401 /* list of all virtual address to which this bo
402 * is associated to
403 */
404 struct list_head va;
4c788679
JG		 405 /* Constant after initialization */
406 struct radeon_device *rdev;
441921d5 407 struct drm_gem_object gem_base;
63bc620b 408
409851f4
JG		 409 struct ttm_bo_kmap_obj dma_buf_vmap;
410 pid_t pid;
4c788679 411};
7e4d15d9 412#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 413
4c788679 414struct radeon_bo_list {
147666fb 415 struct ttm_validate_buffer tv;
4c788679 416 struct radeon_bo *bo;
771fe6b9 417 uint64_t gpu_offset;
4474f3a9
CK		 418 bool written;
419 unsigned domain;
420 unsigned alt_domain;
4c788679 421 u32 tiling_flags;
771fe6b9
JG		 422};
423
409851f4
JG		 424int radeon_gem_debugfs_init(struct radeon_device *rdev);
425
b15ba512
JG		 426/* sub-allocation manager, it has to be protected by another lock.
427 * By conception this is an helper for other part of the driver
428 * like the indirect buffer or semaphore, which both have their
429 * locking.
430 *
431 * Principe is simple, we keep a list of sub allocation in offset
432 * order (first entry has offset == 0, last entry has the highest
433 * offset).
434 *
435 * When allocating new object we first check if there is room at
436 * the end total_size - (last_object_offset + last_object_size) >=
437 * alloc_size. If so we allocate new object there.
438 *
439 * When there is not enough room at the end, we start waiting for
440 * each sub object until we reach object_offset+object_size >=
441 * alloc_size, this object then become the sub object we return.
442 *
443 * Alignment can't be bigger than page size.
444 *
445 * Hole are not considered for allocation to keep things simple.
446 * Assumption is that there won't be hole (all object on same
447 * alignment).
448 */
449struct radeon_sa_manager {
bfb38d35 450 wait_queue_head_t wq;
b15ba512 451 struct radeon_bo *bo;
c3b7fe8b
CK		 452 struct list_head *hole;
453 struct list_head flist[RADEON_NUM_RINGS];
454 struct list_head olist;
b15ba512
JG		 455 unsigned size;
456 uint64_t gpu_addr;
457 void *cpu_ptr;
458 uint32_t domain;
6c4f978b 459 uint32_t align;
b15ba512
JG		 460};
461
462struct radeon_sa_bo;
463
464/* sub-allocation buffer */
465struct radeon_sa_bo {
c3b7fe8b
CK		 466 struct list_head olist;
467 struct list_head flist;
b15ba512 468 struct radeon_sa_manager *manager;
e6661a96
CK		 469 unsigned soffset;
470 unsigned eoffset;
557017a0 471 struct radeon_fence *fence;
b15ba512
JG		 472};
473
771fe6b9
JG		 474/*
475 * GEM objects.
476 */
477struct radeon_gem {
4c788679 478 struct mutex mutex;
771fe6b9
JG		 479 struct list_head objects;
480};
481
482int radeon_gem_init(struct radeon_device *rdev);
483void radeon_gem_fini(struct radeon_device *rdev);
484int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 485 int alignment, int initial_domain,
486 bool discardable, bool kernel,
487 struct drm_gem_object **obj);
771fe6b9 488
ff72145b
DA		 489int radeon_mode_dumb_create(struct drm_file *file_priv,
490 struct drm_device *dev,
491 struct drm_mode_create_dumb *args);
492int radeon_mode_dumb_mmap(struct drm_file *filp,
493 struct drm_device *dev,
494 uint32_t handle, uint64_t *offset_p);
495int radeon_mode_dumb_destroy(struct drm_file *file_priv,
496 struct drm_device *dev,
497 uint32_t handle);
771fe6b9 498
c1341e52
JG		 499/*
500 * Semaphores.
501 */
c1341e52
JG		 502/* everything here is constant */
503struct radeon_semaphore {
a8c05940
JG		 504 struct radeon_sa_bo *sa_bo;
505 signed waiters;
c1341e52 506 uint64_t gpu_addr;
c1341e52
JG		 507};
508
c1341e52
JG		 509int radeon_semaphore_create(struct radeon_device *rdev,
510 struct radeon_semaphore **semaphore);
511void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
512 struct radeon_semaphore *semaphore);
513void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
514 struct radeon_semaphore *semaphore);
8f676c4c
CK		 515int radeon_semaphore_sync_rings(struct radeon_device *rdev,
516 struct radeon_semaphore *semaphore,
220907d9 517 int signaler, int waiter);
c1341e52 518void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 519 struct radeon_semaphore **semaphore,
a8c05940 520 struct radeon_fence *fence);
c1341e52 521
771fe6b9
JG		 522/*
523 * GART structures, functions & helpers
524 */
525struct radeon_mc;
526
a77f1718 527#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 528#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 529#define RADEON_GPU_PAGE_SHIFT 12
721604a1 530#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 531
771fe6b9
JG		 532struct radeon_gart {
533 dma_addr_t table_addr;
c9a1be96
JG		 534 struct radeon_bo *robj;
535 void *ptr;
771fe6b9
JG		 536 unsigned num_gpu_pages;
537 unsigned num_cpu_pages;
538 unsigned table_size;
771fe6b9
JG		 539 struct page **pages;
540 dma_addr_t *pages_addr;
541 bool ready;
542};
543
544int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
545void radeon_gart_table_ram_free(struct radeon_device *rdev);
546int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
547void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 548int radeon_gart_table_vram_pin(struct radeon_device *rdev);
549void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 550int radeon_gart_init(struct radeon_device *rdev);
551void radeon_gart_fini(struct radeon_device *rdev);
552void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
553 int pages);
554int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 555 int pages, struct page **pagelist,
556 dma_addr_t *dma_addr);
c9a1be96 557void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 558
559
560/*
561 * GPU MC structures, functions & helpers
562 */
563struct radeon_mc {
564 resource_size_t aper_size;
565 resource_size_t aper_base;
566 resource_size_t agp_base;
7a50f01a
DA		 567 /* for some chips with <= 32MB we need to lie
568 * about vram size near mc fb location */
3ce0a23d 569 u64 mc_vram_size;
d594e46a 570 u64 visible_vram_size;
3ce0a23d
JG		 571 u64 gtt_size;
572 u64 gtt_start;
573 u64 gtt_end;
3ce0a23d
JG		 574 u64 vram_start;
575 u64 vram_end;
771fe6b9 576 unsigned vram_width;
3ce0a23d 577 u64 real_vram_size;
771fe6b9
JG		 578 int vram_mtrr;
579 bool vram_is_ddr;
d594e46a 580 bool igp_sideport_enabled;
8d369bb1 581 u64 gtt_base_align;
9ed8b1f9 582 u64 mc_mask;
771fe6b9
JG		 583};
584
06b6476d
AD		 585bool radeon_combios_sideport_present(struct radeon_device *rdev);
586bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 587
588/*
589 * GPU scratch registers structures, functions & helpers
590 */
591struct radeon_scratch {
592 unsigned num_reg;
724c80e1 593 uint32_t reg_base;
771fe6b9
JG		 594 bool free[32];
595 uint32_t reg[32];
596};
597
598int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
599void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
600
75efdee1
AD		 601/*
602 * GPU doorbell structures, functions & helpers
603 */
604struct radeon_doorbell {
605 u32 num_pages;
606 bool free[1024];
607 /* doorbell mmio */
608 resource_size_t base;
609 resource_size_t size;
610 void __iomem *ptr;
611};
612
613int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
614void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 615
616/*
617 * IRQS.
618 */
6f34be50
AD		 619
620struct radeon_unpin_work {
621 struct work_struct work;
622 struct radeon_device *rdev;
623 int crtc_id;
624 struct radeon_fence *fence;
625 struct drm_pending_vblank_event *event;
626 struct radeon_bo *old_rbo;
627 u64 new_crtc_base;
628};
629
630struct r500_irq_stat_regs {
631 u32 disp_int;
f122c610 632 u32 hdmi0_status;
6f34be50
AD		 633};
634
635struct r600_irq_stat_regs {
636 u32 disp_int;
637 u32 disp_int_cont;
638 u32 disp_int_cont2;
639 u32 d1grph_int;
640 u32 d2grph_int;
f122c610
AD		 641 u32 hdmi0_status;
642 u32 hdmi1_status;
6f34be50
AD		 643};
644
645struct evergreen_irq_stat_regs {
646 u32 disp_int;
647 u32 disp_int_cont;
648 u32 disp_int_cont2;
649 u32 disp_int_cont3;
650 u32 disp_int_cont4;
651 u32 disp_int_cont5;
652 u32 d1grph_int;
653 u32 d2grph_int;
654 u32 d3grph_int;
655 u32 d4grph_int;
656 u32 d5grph_int;
657 u32 d6grph_int;
f122c610
AD		 658 u32 afmt_status1;
659 u32 afmt_status2;
660 u32 afmt_status3;
661 u32 afmt_status4;
662 u32 afmt_status5;
663 u32 afmt_status6;
6f34be50
AD		 664};
665
a59781bb
AD		 666struct cik_irq_stat_regs {
667 u32 disp_int;
668 u32 disp_int_cont;
669 u32 disp_int_cont2;
670 u32 disp_int_cont3;
671 u32 disp_int_cont4;
672 u32 disp_int_cont5;
673 u32 disp_int_cont6;
674};
675
6f34be50
AD		 676union radeon_irq_stat_regs {
677 struct r500_irq_stat_regs r500;
678 struct r600_irq_stat_regs r600;
679 struct evergreen_irq_stat_regs evergreen;
a59781bb 680 struct cik_irq_stat_regs cik;
6f34be50
AD		 681};
682
54bd5206
IH		 683#define RADEON_MAX_HPD_PINS 6
684#define RADEON_MAX_CRTCS 6
f122c610 685#define RADEON_MAX_AFMT_BLOCKS 6
54bd5206 686
771fe6b9 687struct radeon_irq {
fb98257a
CK		 688 bool installed;
689 spinlock_t lock;
736fc37f 690 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 691 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 692 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 693 wait_queue_head_t vblank_queue;
694 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 695 bool afmt[RADEON_MAX_AFMT_BLOCKS];
696 union radeon_irq_stat_regs stat_regs;
4a6369e9 697 bool dpm_thermal;
771fe6b9
JG		 698};
699
700int radeon_irq_kms_init(struct radeon_device *rdev);
701void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 702void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
703void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 704void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
705void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 706void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
707void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
708void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
709void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 710
711/*
e32eb50d 712 * CP & rings.
771fe6b9 713 */
7465280c 714
771fe6b9 715struct radeon_ib {
68470ae7
JG		 716 struct radeon_sa_bo *sa_bo;
717 uint32_t length_dw;
718 uint64_t gpu_addr;
719 uint32_t *ptr;
876dc9f3 720 int ring;
68470ae7 721 struct radeon_fence *fence;
4bf3dd92 722 struct radeon_vm *vm;
68470ae7 723 bool is_const_ib;
220907d9 724 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
68470ae7 725 struct radeon_semaphore *semaphore;
771fe6b9
JG		 726};
727
e32eb50d 728struct radeon_ring {
4c788679 729 struct radeon_bo *ring_obj;
771fe6b9
JG		 730 volatile uint32_t *ring;
731 unsigned rptr;
5596a9db
CK		 732 unsigned rptr_offs;
733 unsigned rptr_reg;
45df6803 734 unsigned rptr_save_reg;
89d35807
AD		 735 u64 next_rptr_gpu_addr;
736 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 737 unsigned wptr;
738 unsigned wptr_old;
5596a9db 739 unsigned wptr_reg;
771fe6b9
JG		 740 unsigned ring_size;
741 unsigned ring_free_dw;
742 int count_dw;
069211e5
CK		 743 unsigned long last_activity;
744 unsigned last_rptr;
771fe6b9
JG		 745 uint64_t gpu_addr;
746 uint32_t align_mask;
747 uint32_t ptr_mask;
771fe6b9 748 bool ready;
78c5560a
AD		 749 u32 ptr_reg_shift;
750 u32 ptr_reg_mask;
751 u32 nop;
8b25ed34 752 u32 idx;
5f0839c1
JG		 753 u64 last_semaphore_signal_addr;
754 u64 last_semaphore_wait_addr;
963e81f9
AD		 755 /* for CIK queues */
756 u32 me;
757 u32 pipe;
758 u32 queue;
759 struct radeon_bo *mqd_obj;
760 u32 doorbell_page_num;
761 u32 doorbell_offset;
762 unsigned wptr_offs;
763};
764
765struct radeon_mec {
766 struct radeon_bo *hpd_eop_obj;
767 u64 hpd_eop_gpu_addr;
768 u32 num_pipe;
769 u32 num_mec;
770 u32 num_queue;
771fe6b9
JG		 771};
772
721604a1
JG		 773/*
774 * VM
775 */
ee60e29f 776
fa87e62d 777/* maximum number of VMIDs */
ee60e29f
CK		 778#define RADEON_NUM_VM 16
779
fa87e62d
DC		 780/* defines number of bits in page table versus page directory,
781 * a page is 4KB so we have 12 bits offset, 9 bits in the page
782 * table and the remaining 19 bits are in the page directory */
783#define RADEON_VM_BLOCK_SIZE 9
784
785/* number of entries in page table */
786#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
787
1c01103c
AD		 788/* PTBs (Page Table Blocks) need to be aligned to 32K */
789#define RADEON_VM_PTB_ALIGN_SIZE 32768
790#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
791#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
792
721604a1
JG		 793struct radeon_vm {
794 struct list_head list;
795 struct list_head va;
ee60e29f 796 unsigned id;
90a51a32
CK		 797
798 /* contains the page directory */
799 struct radeon_sa_bo *page_directory;
800 uint64_t pd_gpu_addr;
801
802 /* array of page tables, one for each page directory entry */
803 struct radeon_sa_bo **page_tables;
804
721604a1
JG		 805 struct mutex mutex;
806 /* last fence for cs using this vm */
807 struct radeon_fence *fence;
9b40e5d8
CK		 808 /* last flush or NULL if we still need to flush */
809 struct radeon_fence *last_flush;
721604a1
JG		 810};
811
721604a1 812struct radeon_vm_manager {
36ff39c4 813 struct mutex lock;
721604a1 814 struct list_head lru_vm;
ee60e29f 815 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 816 struct radeon_sa_manager sa_manager;
817 uint32_t max_pfn;
721604a1
JG		 818 /* number of VMIDs */
819 unsigned nvm;
820 /* vram base address for page table entry */
821 u64 vram_base_offset;
67e915e4
AD		 822 /* is vm enabled? */
823 bool enabled;
721604a1
JG		 824};
825
826/*
827 * file private structure
828 */
829struct radeon_fpriv {
830 struct radeon_vm vm;
831};
832
d8f60cfc
AD		 833/*
834 * R6xx+ IH ring
835 */
836struct r600_ih {
4c788679 837 struct radeon_bo *ring_obj;
d8f60cfc
AD		 838 volatile uint32_t *ring;
839 unsigned rptr;
d8f60cfc
AD		 840 unsigned ring_size;
841 uint64_t gpu_addr;
d8f60cfc 842 uint32_t ptr_mask;
c20dc369 843 atomic_t lock;
d8f60cfc
AD		 844 bool enabled;
845};
846
347e7592 847/*
2948f5e6 848 * RLC stuff
347e7592 849 */
2948f5e6
AD		 850#include "clearstate_defs.h"
851
852struct radeon_rlc {
347e7592
AD		 853 /* for power gating */
854 struct radeon_bo *save_restore_obj;
855 uint64_t save_restore_gpu_addr;
2948f5e6 856 volatile uint32_t *sr_ptr;
1fd11777 857 const u32 *reg_list;
2948f5e6 858 u32 reg_list_size;
347e7592
AD		 859 /* for clear state */
860 struct radeon_bo *clear_state_obj;
861 uint64_t clear_state_gpu_addr;
2948f5e6 862 volatile uint32_t *cs_ptr;
1fd11777 863 const struct cs_section_def *cs_data;
347e7592
AD		 864};
865
69e130a6 866int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 867 struct radeon_ib *ib, struct radeon_vm *vm,
868 unsigned size);
f2e39221 869void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
43f1214a 870void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
4ef72566
CK		 871int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
872 struct radeon_ib *const_ib);
771fe6b9
JG		 873int radeon_ib_pool_init(struct radeon_device *rdev);
874void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 875int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 876/* Ring access between begin & end cannot sleep */
89d35807
AD		 877bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
878 struct radeon_ring *ring);
e32eb50d
CK		 879void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
880int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
881int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
882void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
883void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 884void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 885void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
886int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 887void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 888void radeon_ring_lockup_update(struct radeon_ring *ring);
889bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 890unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
891 uint32_t **data);
892int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
893 unsigned size, uint32_t *data);
e32eb50d 894int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
78c5560a
AD		 895 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
896 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
e32eb50d 897void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 898
899
4d75658b
AD		 900/* r600 async dma */
901void r600_dma_stop(struct radeon_device *rdev);
902int r600_dma_resume(struct radeon_device *rdev);
903void r600_dma_fini(struct radeon_device *rdev);
904
8c5fd7ef
AD		 905void cayman_dma_stop(struct radeon_device *rdev);
906int cayman_dma_resume(struct radeon_device *rdev);
907void cayman_dma_fini(struct radeon_device *rdev);
908
771fe6b9
JG		 909/*
910 * CS.
911 */
912struct radeon_cs_reloc {
913 struct drm_gem_object *gobj;
4c788679
JG		 914 struct radeon_bo *robj;
915 struct radeon_bo_list lobj;
771fe6b9
JG		 916 uint32_t handle;
917 uint32_t flags;
918};
919
920struct radeon_cs_chunk {
921 uint32_t chunk_id;
922 uint32_t length_dw;
721604a1
JG		 923 int kpage_idx[2];
924 uint32_t *kpage[2];
771fe6b9 925 uint32_t *kdata;
721604a1
JG		 926 void __user *user_ptr;
927 int last_copied_page;
928 int last_page_index;
771fe6b9
JG		 929};
930
931struct radeon_cs_parser {
c8c15ff1 932 struct device *dev;
771fe6b9
JG		 933 struct radeon_device *rdev;
934 struct drm_file *filp;
935 /* chunks */
936 unsigned nchunks;
937 struct radeon_cs_chunk *chunks;
938 uint64_t *chunks_array;
939 /* IB */
940 unsigned idx;
941 /* relocations */
942 unsigned nrelocs;
943 struct radeon_cs_reloc *relocs;
944 struct radeon_cs_reloc **relocs_ptr;
945 struct list_head validated;
cf4ccd01 946 unsigned dma_reloc_idx;
771fe6b9
JG		 947 /* indices of various chunks */
948 int chunk_ib_idx;
949 int chunk_relocs_idx;
721604a1 950 int chunk_flags_idx;
dfcf5f36 951 int chunk_const_ib_idx;
f2e39221
JG		 952 struct radeon_ib ib;
953 struct radeon_ib const_ib;
771fe6b9 954 void *track;
3ce0a23d 955 unsigned family;
e70f224c 956 int parser_error;
721604a1
JG		 957 u32 cs_flags;
958 u32 ring;
959 s32 priority;
ecff665f 960 struct ww_acquire_ctx ticket;
771fe6b9
JG		 961};
962
513bcb46 963extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
ce580fab 964extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
513bcb46 965
771fe6b9
JG		 966struct radeon_cs_packet {
967 unsigned idx;
968 unsigned type;
969 unsigned reg;
970 unsigned opcode;
971 int count;
972 unsigned one_reg_wr;
973};
974
975typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
976 struct radeon_cs_packet *pkt,
977 unsigned idx, unsigned reg);
978typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
979 struct radeon_cs_packet *pkt);
980
981
982/*
983 * AGP
984 */
985int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 986void radeon_agp_resume(struct radeon_device *rdev);
10b06122 987void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 988void radeon_agp_fini(struct radeon_device *rdev);
989
990
991/*
992 * Writeback
993 */
994struct radeon_wb {
4c788679 995 struct radeon_bo *wb_obj;
771fe6b9
JG		 996 volatile uint32_t *wb;
997 uint64_t gpu_addr;
724c80e1 998 bool enabled;
d0f8a854 999 bool use_event;
771fe6b9
JG		 1000};
1001
724c80e1 1002#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1003#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1004#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1005#define RADEON_WB_CP1_RPTR_OFFSET 1280
1006#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1007#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1008#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1009#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
f2ba57b5 1010#define R600_WB_UVD_RPTR_OFFSET 2560
d0f8a854 1011#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1012#define CIK_WB_CP1_WPTR_OFFSET 3328
1013#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1014
c93bb85b
JG		 1015/**
1016 * struct radeon_pm - power management datas
1017 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1018 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1019 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1020 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1021 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1022 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1023 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1024 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1025 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1026 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1027 * @needed_bandwidth: current bandwidth needs
1028 *
1029 * It keeps track of various data needed to take powermanagement decision.
25985edc 1030 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1031 * Equation between gpu/memory clock and available bandwidth is hw dependent
1032 * (type of memory, bus size, efficiency, ...)
1033 */
ce8f5370
AD		 1034
1035enum radeon_pm_method {
1036 PM_METHOD_PROFILE,
1037 PM_METHOD_DYNPM,
da321c8a 1038 PM_METHOD_DPM,
ce8f5370
AD		 1039};
1040
1041enum radeon_dynpm_state {
1042 DYNPM_STATE_DISABLED,
1043 DYNPM_STATE_MINIMUM,
1044 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1045 DYNPM_STATE_ACTIVE,
1046 DYNPM_STATE_SUSPENDED,
c913e23a 1047};
ce8f5370
AD		 1048enum radeon_dynpm_action {
1049 DYNPM_ACTION_NONE,
1050 DYNPM_ACTION_MINIMUM,
1051 DYNPM_ACTION_DOWNCLOCK,
1052 DYNPM_ACTION_UPCLOCK,
1053 DYNPM_ACTION_DEFAULT
c913e23a 1054};
56278a8e
AD		 1055
1056enum radeon_voltage_type {
1057 VOLTAGE_NONE = 0,
1058 VOLTAGE_GPIO,
1059 VOLTAGE_VDDC,
1060 VOLTAGE_SW
1061};
1062
0ec0e74f 1063enum radeon_pm_state_type {
da321c8a 1064 /* not used for dpm */
0ec0e74f
AD		 1065 POWER_STATE_TYPE_DEFAULT,
1066 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1067 /* user selectable states */
0ec0e74f
AD		 1068 POWER_STATE_TYPE_BATTERY,
1069 POWER_STATE_TYPE_BALANCED,
1070 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1071 /* internal states */
1072 POWER_STATE_TYPE_INTERNAL_UVD,
1073 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1074 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1075 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1076 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1077 POWER_STATE_TYPE_INTERNAL_BOOT,
1078 POWER_STATE_TYPE_INTERNAL_THERMAL,
1079 POWER_STATE_TYPE_INTERNAL_ACPI,
1080 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1081 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1082};
1083
ce8f5370
AD		 1084enum radeon_pm_profile_type {
1085 PM_PROFILE_DEFAULT,
1086 PM_PROFILE_AUTO,
1087 PM_PROFILE_LOW,
c9e75b21 1088 PM_PROFILE_MID,
ce8f5370
AD		 1089 PM_PROFILE_HIGH,
1090};
1091
1092#define PM_PROFILE_DEFAULT_IDX 0
1093#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1094#define PM_PROFILE_MID_SH_IDX 2
1095#define PM_PROFILE_HIGH_SH_IDX 3
1096#define PM_PROFILE_LOW_MH_IDX 4
1097#define PM_PROFILE_MID_MH_IDX 5
1098#define PM_PROFILE_HIGH_MH_IDX 6
1099#define PM_PROFILE_MAX 7
ce8f5370
AD		 1100
1101struct radeon_pm_profile {
1102 int dpms_off_ps_idx;
1103 int dpms_on_ps_idx;
1104 int dpms_off_cm_idx;
1105 int dpms_on_cm_idx;
516d0e46
AD		 1106};
1107
21a8122a
AD		 1108enum radeon_int_thermal_type {
1109 THERMAL_TYPE_NONE,
da321c8a
AD		 1110 THERMAL_TYPE_EXTERNAL,
1111 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1112 THERMAL_TYPE_RV6XX,
1113 THERMAL_TYPE_RV770,
da321c8a 1114 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1115 THERMAL_TYPE_EVERGREEN,
e33df25f 1116 THERMAL_TYPE_SUMO,
4fddba1f 1117 THERMAL_TYPE_NI,
14607d08 1118 THERMAL_TYPE_SI,
da321c8a 1119 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1120 THERMAL_TYPE_CI,
21a8122a
AD		 1121};
1122
56278a8e
AD		 1123struct radeon_voltage {
1124 enum radeon_voltage_type type;
1125 /* gpio voltage */
1126 struct radeon_gpio_rec gpio;
1127 u32 delay; /* delay in usec from voltage drop to sclk change */
1128 bool active_high; /* voltage drop is active when bit is high */
1129 /* VDDC voltage */
1130 u8 vddc_id; /* index into vddc voltage table */
1131 u8 vddci_id; /* index into vddci voltage table */
1132 bool vddci_enabled;
1133 /* r6xx+ sw */
2feea49a
AD		 1134 u16 voltage;
1135 /* evergreen+ vddci */
1136 u16 vddci;
56278a8e
AD		 1137};
1138
d7311171
AD		 1139/* clock mode flags */
1140#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1141
56278a8e
AD		 1142struct radeon_pm_clock_info {
1143 /* memory clock */
1144 u32 mclk;
1145 /* engine clock */
1146 u32 sclk;
1147 /* voltage info */
1148 struct radeon_voltage voltage;
d7311171 1149 /* standardized clock flags */
56278a8e
AD		 1150 u32 flags;
1151};
1152
a48b9b4e 1153/* state flags */
d7311171 1154#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1155
56278a8e 1156struct radeon_power_state {
0ec0e74f 1157 enum radeon_pm_state_type type;
8f3f1c9a 1158 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1159 /* number of valid clock modes in this power state */
1160 int num_clock_modes;
56278a8e 1161 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1162 /* standardized state flags */
1163 u32 flags;
79daedc9
AD		 1164 u32 misc; /* vbios specific flags */
1165 u32 misc2; /* vbios specific flags */
1166 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1167};
1168
27459324
RM		 1169/*
1170 * Some modes are overclocked by very low value, accept them
1171 */
1172#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1173
2e9d4c05
AD		 1174enum radeon_dpm_auto_throttle_src {
1175 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1176 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1177};
1178
1179enum radeon_dpm_event_src {
1180 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1181 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1182 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1183 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1184 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1185};
1186
da321c8a
AD		 1187struct radeon_ps {
1188 u32 caps; /* vbios flags */
1189 u32 class; /* vbios flags */
1190 u32 class2; /* vbios flags */
1191 /* UVD clocks */
1192 u32 vclk;
1193 u32 dclk;
1194 /* asic priv */
1195 void *ps_priv;
1196};
1197
1198struct radeon_dpm_thermal {
1199 /* thermal interrupt work */
1200 struct work_struct work;
1201 /* low temperature threshold */
1202 int min_temp;
1203 /* high temperature threshold */
1204 int max_temp;
1205 /* was interrupt low to high or high to low */
1206 bool high_to_low;
1207};
1208
d22b7e40
AD		 1209enum radeon_clk_action
1210{
1211 RADEON_SCLK_UP = 1,
1212 RADEON_SCLK_DOWN
1213};
1214
1215struct radeon_blacklist_clocks
1216{
1217 u32 sclk;
1218 u32 mclk;
1219 enum radeon_clk_action action;
1220};
1221
61b7d601
AD		 1222struct radeon_clock_and_voltage_limits {
1223 u32 sclk;
1224 u32 mclk;
1225 u32 vddc;
1226 u32 vddci;
1227};
1228
1229struct radeon_clock_array {
1230 u32 count;
1231 u32 *values;
1232};
1233
1234struct radeon_clock_voltage_dependency_entry {
1235 u32 clk;
1236 u16 v;
1237};
1238
1239struct radeon_clock_voltage_dependency_table {
1240 u32 count;
1241 struct radeon_clock_voltage_dependency_entry *entries;
1242};
1243
1244struct radeon_cac_leakage_entry {
1245 u16 vddc;
1246 u32 leakage;
1247};
1248
1249struct radeon_cac_leakage_table {
1250 u32 count;
1251 struct radeon_cac_leakage_entry *entries;
1252};
1253
929ee7a8
AD		 1254struct radeon_phase_shedding_limits_entry {
1255 u16 voltage;
1256 u32 sclk;
1257 u32 mclk;
1258};
1259
1260struct radeon_phase_shedding_limits_table {
1261 u32 count;
1262 struct radeon_phase_shedding_limits_entry *entries;
1263};
1264
a5cb318e
AD		 1265struct radeon_ppm_table {
1266 u8 ppm_design;
1267 u16 cpu_core_number;
1268 u32 platform_tdp;
1269 u32 small_ac_platform_tdp;
1270 u32 platform_tdc;
1271 u32 small_ac_platform_tdc;
1272 u32 apu_tdp;
1273 u32 dgpu_tdp;
1274 u32 dgpu_ulv_power;
1275 u32 tj_max;
1276};
1277
61b7d601
AD		 1278struct radeon_dpm_dynamic_state {
1279 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1280 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1281 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
4489cd62 1282 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
61b7d601
AD		 1283 struct radeon_clock_array valid_sclk_values;
1284 struct radeon_clock_array valid_mclk_values;
1285 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1286 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1287 u32 mclk_sclk_ratio;
1288 u32 sclk_mclk_delta;
1289 u16 vddc_vddci_delta;
1290 u16 min_vddc_for_pcie_gen2;
1291 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1292 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1293 struct radeon_ppm_table *ppm_table;
61b7d601
AD		 1294};
1295
1296struct radeon_dpm_fan {
1297 u16 t_min;
1298 u16 t_med;
1299 u16 t_high;
1300 u16 pwm_min;
1301 u16 pwm_med;
1302 u16 pwm_high;
1303 u8 t_hyst;
1304 u32 cycle_delay;
1305 u16 t_max;
1306 bool ucode_fan_control;
1307};
1308
32ce4652
AD		 1309enum radeon_pcie_gen {
1310 RADEON_PCIE_GEN1 = 0,
1311 RADEON_PCIE_GEN2 = 1,
1312 RADEON_PCIE_GEN3 = 2,
1313 RADEON_PCIE_GEN_INVALID = 0xffff
1314};
1315
70d01a5e
AD		 1316enum radeon_dpm_forced_level {
1317 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1318 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1319 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1320};
1321
da321c8a
AD		 1322struct radeon_dpm {
1323 struct radeon_ps *ps;
1324 /* number of valid power states */
1325 int num_ps;
1326 /* current power state that is active */
1327 struct radeon_ps *current_ps;
1328 /* requested power state */
1329 struct radeon_ps *requested_ps;
1330 /* boot up power state */
1331 struct radeon_ps *boot_ps;
1332 /* default uvd power state */
1333 struct radeon_ps *uvd_ps;
1334 enum radeon_pm_state_type state;
1335 enum radeon_pm_state_type user_state;
1336 u32 platform_caps;
1337 u32 voltage_response_time;
1338 u32 backbias_response_time;
1339 void *priv;
1340 u32 new_active_crtcs;
1341 int new_active_crtc_count;
1342 u32 current_active_crtcs;
1343 int current_active_crtc_count;
61b7d601
AD		 1344 struct radeon_dpm_dynamic_state dyn_state;
1345 struct radeon_dpm_fan fan;
1346 u32 tdp_limit;
1347 u32 near_tdp_limit;
a9e61410 1348 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1349 u32 sq_ramping_threshold;
1350 u32 cac_leakage;
1351 u16 tdp_od_limit;
1352 u32 tdp_adjustment;
1353 u16 load_line_slope;
1354 bool power_control;
5ca302f7 1355 bool ac_power;
da321c8a
AD		 1356 /* special states active */
1357 bool thermal_active;
8a227555 1358 bool uvd_active;
da321c8a
AD		 1359 /* thermal handling */
1360 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1361 /* forced levels */
1362 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1363 /* track UVD streams */
1364 unsigned sd;
1365 unsigned hd;
da321c8a
AD		 1366};
1367
ce3537d5 1368void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
da321c8a 1369
c93bb85b 1370struct radeon_pm {
c913e23a 1371 struct mutex mutex;
db7fce39
CK		 1372 /* write locked while reprogramming mclk */
1373 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1374 u32 active_crtcs;
1375 int active_crtc_count;
c913e23a 1376 int req_vblank;
839461d3 1377 bool vblank_sync;
c93bb85b
JG		 1378 fixed20_12 max_bandwidth;
1379 fixed20_12 igp_sideport_mclk;
1380 fixed20_12 igp_system_mclk;
1381 fixed20_12 igp_ht_link_clk;
1382 fixed20_12 igp_ht_link_width;
1383 fixed20_12 k8_bandwidth;
1384 fixed20_12 sideport_bandwidth;
1385 fixed20_12 ht_bandwidth;
1386 fixed20_12 core_bandwidth;
1387 fixed20_12 sclk;
f47299c5 1388 fixed20_12 mclk;
c93bb85b 1389 fixed20_12 needed_bandwidth;
0975b162 1390 struct radeon_power_state *power_state;
56278a8e
AD		 1391 /* number of valid power states */
1392 int num_power_states;
a48b9b4e
AD		 1393 int current_power_state_index;
1394 int current_clock_mode_index;
1395 int requested_power_state_index;
1396 int requested_clock_mode_index;
1397 int default_power_state_index;
1398 u32 current_sclk;
1399 u32 current_mclk;
2feea49a
AD		 1400 u16 current_vddc;
1401 u16 current_vddci;
9ace9f7b
AD		 1402 u32 default_sclk;
1403 u32 default_mclk;
2feea49a
AD		 1404 u16 default_vddc;
1405 u16 default_vddci;
29fb52ca 1406 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1407 /* selected pm method */
1408 enum radeon_pm_method pm_method;
1409 /* dynpm power management */
1410 struct delayed_work dynpm_idle_work;
1411 enum radeon_dynpm_state dynpm_state;
1412 enum radeon_dynpm_action dynpm_planned_action;
1413 unsigned long dynpm_action_timeout;
1414 bool dynpm_can_upclock;
1415 bool dynpm_can_downclock;
1416 /* profile-based power management */
1417 enum radeon_pm_profile_type profile;
1418 int profile_index;
1419 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1420 /* internal thermal controller on rv6xx+ */
1421 enum radeon_int_thermal_type int_thermal_type;
1422 struct device *int_hwmon_dev;
da321c8a
AD		 1423 /* dpm */
1424 bool dpm_enabled;
1425 struct radeon_dpm dpm;
c93bb85b
JG		 1426};
1427
a4c9e2ee
AD		 1428int radeon_pm_get_type_index(struct radeon_device *rdev,
1429 enum radeon_pm_state_type ps_type,
1430 int instance);
f2ba57b5
CK		 1431/*
1432 * UVD
1433 */
1434#define RADEON_MAX_UVD_HANDLES 10
1435#define RADEON_UVD_STACK_SIZE (1024*1024)
1436#define RADEON_UVD_HEAP_SIZE (1024*1024)
1437
1438struct radeon_uvd {
1439 struct radeon_bo *vcpu_bo;
1440 void *cpu_addr;
1441 uint64_t gpu_addr;
9cc2e0e9 1442 void *saved_bo;
f2ba57b5
CK		 1443 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1444 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1445 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1446 struct delayed_work idle_work;
f2ba57b5
CK		 1447};
1448
1449int radeon_uvd_init(struct radeon_device *rdev);
1450void radeon_uvd_fini(struct radeon_device *rdev);
1451int radeon_uvd_suspend(struct radeon_device *rdev);
1452int radeon_uvd_resume(struct radeon_device *rdev);
1453int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1454 uint32_t handle, struct radeon_fence **fence);
1455int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1456 uint32_t handle, struct radeon_fence **fence);
1457void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1458void radeon_uvd_free_handles(struct radeon_device *rdev,
1459 struct drm_file *filp);
1460int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1461void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1462int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1463 unsigned vclk, unsigned dclk,
1464 unsigned vco_min, unsigned vco_max,
1465 unsigned fb_factor, unsigned fb_mask,
1466 unsigned pd_min, unsigned pd_max,
1467 unsigned pd_even,
1468 unsigned *optimal_fb_div,
1469 unsigned *optimal_vclk_div,
1470 unsigned *optimal_dclk_div);
1471int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1472 unsigned cg_upll_func_cntl);
771fe6b9 1473
a92553ab 1474struct r600_audio {
a92553ab
RM		 1475 int channels;
1476 int rate;
1477 int bits_per_sample;
1478 u8 status_bits;
1479 u8 category_code;
1480};
1481
771fe6b9
JG		 1482/*
1483 * Benchmarking
1484 */
638dd7db 1485void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1486
1487
ecc0b326
MD		 1488/*
1489 * Testing
1490 */
1491void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1492void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1493 struct radeon_ring *cpA,
1494 struct radeon_ring *cpB);
60a7e396 1495void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1496
1497
771fe6b9
JG		 1498/*
1499 * Debugfs
1500 */
4d8bf9ae
CK		 1501struct radeon_debugfs {
1502 struct drm_info_list *files;
1503 unsigned num_files;
1504};
1505
771fe6b9
JG		 1506int radeon_debugfs_add_files(struct radeon_device *rdev,
1507 struct drm_info_list *files,
1508 unsigned nfiles);
1509int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9
JG		 1510
1511
1512/*
1513 * ASIC specific functions.
1514 */
1515struct radeon_asic {
068a117c 1516 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1517 void (*fini)(struct radeon_device *rdev);
1518 int (*resume)(struct radeon_device *rdev);
1519 int (*suspend)(struct radeon_device *rdev);
28d52043 1520 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1521 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1522 /* ioctl hw specific callback. Some hw might want to perform special
1523 * operation on specific ioctl. For instance on wait idle some hw
1524 * might want to perform and HDP flush through MMIO as it seems that
1525 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1526 * through ring.
1527 */
1528 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1529 /* check if 3D engine is idle */
1530 bool (*gui_idle)(struct radeon_device *rdev);
1531 /* wait for mc_idle */
1532 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1533 /* get the reference clock */
1534 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1535 /* get the gpu clock counter */
1536 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1537 /* gart */
c5b3b850
AD		 1538 struct {
1539 void (*tlb_flush)(struct radeon_device *rdev);
1540 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1541 } gart;
05b07147
CK		 1542 struct {
1543 int (*init)(struct radeon_device *rdev);
1544 void (*fini)(struct radeon_device *rdev);
2a6f1abb
CK		 1545
1546 u32 pt_ring_index;
43f1214a
AD		 1547 void (*set_page)(struct radeon_device *rdev,
1548 struct radeon_ib *ib,
1549 uint64_t pe,
dce34bfd
CK		 1550 uint64_t addr, unsigned count,
1551 uint32_t incr, uint32_t flags);
05b07147 1552 } vm;
54e88e06 1553 /* ring specific callbacks */
4c87bc26
CK		 1554 struct {
1555 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
721604a1 1556 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
4c87bc26 1557 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
e32eb50d 1558 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
4c87bc26 1559 struct radeon_semaphore *semaphore, bool emit_wait);
eb0c19c5 1560 int (*cs_parse)(struct radeon_cs_parser *p);
f712812e
AD		 1561 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1562 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1563 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
312c4a8c 1564 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
498522b4 1565 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
f93bdefe
AD		 1566
1567 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1568 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1569 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
4c87bc26 1570 } ring[RADEON_NUM_RINGS];
54e88e06 1571 /* irqs */
b35ea4ab
AD		 1572 struct {
1573 int (*set)(struct radeon_device *rdev);
1574 int (*process)(struct radeon_device *rdev);
1575 } irq;
54e88e06 1576 /* displays */
c79a49ca
AD		 1577 struct {
1578 /* display watermarks */
1579 void (*bandwidth_update)(struct radeon_device *rdev);
1580 /* get frame count */
1581 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1582 /* wait for vblank */
1583 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1584 /* set backlight level */
1585 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1586 /* get backlight level */
1587 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1588 /* audio callbacks */
1589 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1590 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1591 } display;
54e88e06 1592 /* copy functions for bo handling */
27cd7769
AD		 1593 struct {
1594 int (*blit)(struct radeon_device *rdev,
1595 uint64_t src_offset,
1596 uint64_t dst_offset,
1597 unsigned num_gpu_pages,
876dc9f3 1598 struct radeon_fence **fence);
27cd7769
AD		 1599 u32 blit_ring_index;
1600 int (*dma)(struct radeon_device *rdev,
1601 uint64_t src_offset,
1602 uint64_t dst_offset,
1603 unsigned num_gpu_pages,
876dc9f3 1604 struct radeon_fence **fence);
27cd7769
AD		 1605 u32 dma_ring_index;
1606 /* method used for bo copy */
1607 int (*copy)(struct radeon_device *rdev,
1608 uint64_t src_offset,
1609 uint64_t dst_offset,
1610 unsigned num_gpu_pages,
876dc9f3 1611 struct radeon_fence **fence);
27cd7769
AD		 1612 /* ring used for bo copies */
1613 u32 copy_ring_index;
1614 } copy;
54e88e06 1615 /* surfaces */
9e6f3d02
AD		 1616 struct {
1617 int (*set_reg)(struct radeon_device *rdev, int reg,
1618 uint32_t tiling_flags, uint32_t pitch,
1619 uint32_t offset, uint32_t obj_size);
1620 void (*clear_reg)(struct radeon_device *rdev, int reg);
1621 } surface;
54e88e06 1622 /* hotplug detect */
901ea57d
AD		 1623 struct {
1624 void (*init)(struct radeon_device *rdev);
1625 void (*fini)(struct radeon_device *rdev);
1626 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1627 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1628 } hpd;
da321c8a 1629 /* static power management */
a02fa397
AD		 1630 struct {
1631 void (*misc)(struct radeon_device *rdev);
1632 void (*prepare)(struct radeon_device *rdev);
1633 void (*finish)(struct radeon_device *rdev);
1634 void (*init_profile)(struct radeon_device *rdev);
1635 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1636 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1637 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1638 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1639 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1640 int (*get_pcie_lanes)(struct radeon_device *rdev);
1641 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1642 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1643 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1644 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1645 } pm;
da321c8a
AD		 1646 /* dynamic power management */
1647 struct {
1648 int (*init)(struct radeon_device *rdev);
1649 void (*setup_asic)(struct radeon_device *rdev);
1650 int (*enable)(struct radeon_device *rdev);
1651 void (*disable)(struct radeon_device *rdev);
84dd1928 1652 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1653 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1654 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1655 void (*display_configuration_changed)(struct radeon_device *rdev);
1656 void (*fini)(struct radeon_device *rdev);
1657 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1658 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1659 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1660 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1661 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1662 bool (*vblank_too_short)(struct radeon_device *rdev);
da321c8a 1663 } dpm;
6f34be50 1664 /* pageflipping */
0f9e006c
AD		 1665 struct {
1666 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1667 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1668 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1669 } pflip;
771fe6b9
JG		 1670};
1671
21f9a437
JG		 1672/*
1673 * Asic structures
1674 */
551ebd83 1675struct r100_asic {
225758d8
JG		 1676 const unsigned *reg_safe_bm;
1677 unsigned reg_safe_bm_size;
1678 u32 hdp_cntl;
551ebd83
DA		 1679};
1680
21f9a437 1681struct r300_asic {
225758d8
JG		 1682 const unsigned *reg_safe_bm;
1683 unsigned reg_safe_bm_size;
1684 u32 resync_scratch;
1685 u32 hdp_cntl;
21f9a437
JG		 1686};
1687
1688struct r600_asic {
225758d8
JG		 1689 unsigned max_pipes;
1690 unsigned max_tile_pipes;
1691 unsigned max_simds;
1692 unsigned max_backends;
1693 unsigned max_gprs;
1694 unsigned max_threads;
1695 unsigned max_stack_entries;
1696 unsigned max_hw_contexts;
1697 unsigned max_gs_threads;
1698 unsigned sx_max_export_size;
1699 unsigned sx_max_export_pos_size;
1700 unsigned sx_max_export_smx_size;
1701 unsigned sq_num_cf_insts;
1702 unsigned tiling_nbanks;
1703 unsigned tiling_npipes;
1704 unsigned tiling_group_size;
e7aeeba6 1705 unsigned tile_config;
e55b9422 1706 unsigned backend_map;
21f9a437
JG		 1707};
1708
1709struct rv770_asic {
225758d8
JG		 1710 unsigned max_pipes;
1711 unsigned max_tile_pipes;
1712 unsigned max_simds;
1713 unsigned max_backends;
1714 unsigned max_gprs;
1715 unsigned max_threads;
1716 unsigned max_stack_entries;
1717 unsigned max_hw_contexts;
1718 unsigned max_gs_threads;
1719 unsigned sx_max_export_size;
1720 unsigned sx_max_export_pos_size;
1721 unsigned sx_max_export_smx_size;
1722 unsigned sq_num_cf_insts;
1723 unsigned sx_num_of_sets;
1724 unsigned sc_prim_fifo_size;
1725 unsigned sc_hiz_tile_fifo_size;
1726 unsigned sc_earlyz_tile_fifo_fize;
1727 unsigned tiling_nbanks;
1728 unsigned tiling_npipes;
1729 unsigned tiling_group_size;
e7aeeba6 1730 unsigned tile_config;
e55b9422 1731 unsigned backend_map;
21f9a437
JG		 1732};
1733
32fcdbf4
AD		 1734struct evergreen_asic {
1735 unsigned num_ses;
1736 unsigned max_pipes;
1737 unsigned max_tile_pipes;
1738 unsigned max_simds;
1739 unsigned max_backends;
1740 unsigned max_gprs;
1741 unsigned max_threads;
1742 unsigned max_stack_entries;
1743 unsigned max_hw_contexts;
1744 unsigned max_gs_threads;
1745 unsigned sx_max_export_size;
1746 unsigned sx_max_export_pos_size;
1747 unsigned sx_max_export_smx_size;
1748 unsigned sq_num_cf_insts;
1749 unsigned sx_num_of_sets;
1750 unsigned sc_prim_fifo_size;
1751 unsigned sc_hiz_tile_fifo_size;
1752 unsigned sc_earlyz_tile_fifo_size;
1753 unsigned tiling_nbanks;
1754 unsigned tiling_npipes;
1755 unsigned tiling_group_size;
e7aeeba6 1756 unsigned tile_config;
e55b9422 1757 unsigned backend_map;
32fcdbf4
AD		 1758};
1759
fecf1d07
AD		 1760struct cayman_asic {
1761 unsigned max_shader_engines;
1762 unsigned max_pipes_per_simd;
1763 unsigned max_tile_pipes;
1764 unsigned max_simds_per_se;
1765 unsigned max_backends_per_se;
1766 unsigned max_texture_channel_caches;
1767 unsigned max_gprs;
1768 unsigned max_threads;
1769 unsigned max_gs_threads;
1770 unsigned max_stack_entries;
1771 unsigned sx_num_of_sets;
1772 unsigned sx_max_export_size;
1773 unsigned sx_max_export_pos_size;
1774 unsigned sx_max_export_smx_size;
1775 unsigned max_hw_contexts;
1776 unsigned sq_num_cf_insts;
1777 unsigned sc_prim_fifo_size;
1778 unsigned sc_hiz_tile_fifo_size;
1779 unsigned sc_earlyz_tile_fifo_size;
1780
1781 unsigned num_shader_engines;
1782 unsigned num_shader_pipes_per_simd;
1783 unsigned num_tile_pipes;
1784 unsigned num_simds_per_se;
1785 unsigned num_backends_per_se;
1786 unsigned backend_disable_mask_per_asic;
1787 unsigned backend_map;
1788 unsigned num_texture_channel_caches;
1789 unsigned mem_max_burst_length_bytes;
1790 unsigned mem_row_size_in_kb;
1791 unsigned shader_engine_tile_size;
1792 unsigned num_gpus;
1793 unsigned multi_gpu_tile_size;
1794
1795 unsigned tile_config;
fecf1d07
AD		 1796};
1797
0a96d72b
AD		 1798struct si_asic {
1799 unsigned max_shader_engines;
0a96d72b 1800 unsigned max_tile_pipes;
1a8ca750
AD		 1801 unsigned max_cu_per_sh;
1802 unsigned max_sh_per_se;
0a96d72b
AD		 1803 unsigned max_backends_per_se;
1804 unsigned max_texture_channel_caches;
1805 unsigned max_gprs;
1806 unsigned max_gs_threads;
1807 unsigned max_hw_contexts;
1808 unsigned sc_prim_fifo_size_frontend;
1809 unsigned sc_prim_fifo_size_backend;
1810 unsigned sc_hiz_tile_fifo_size;
1811 unsigned sc_earlyz_tile_fifo_size;
1812
0a96d72b
AD		 1813 unsigned num_tile_pipes;
1814 unsigned num_backends_per_se;
1815 unsigned backend_disable_mask_per_asic;
1816 unsigned backend_map;
1817 unsigned num_texture_channel_caches;
1818 unsigned mem_max_burst_length_bytes;
1819 unsigned mem_row_size_in_kb;
1820 unsigned shader_engine_tile_size;
1821 unsigned num_gpus;
1822 unsigned multi_gpu_tile_size;
1823
1824 unsigned tile_config;
64d7b8be 1825 uint32_t tile_mode_array[32];
0a96d72b
AD		 1826};
1827
8cc1a532
AD		 1828struct cik_asic {
1829 unsigned max_shader_engines;
1830 unsigned max_tile_pipes;
1831 unsigned max_cu_per_sh;
1832 unsigned max_sh_per_se;
1833 unsigned max_backends_per_se;
1834 unsigned max_texture_channel_caches;
1835 unsigned max_gprs;
1836 unsigned max_gs_threads;
1837 unsigned max_hw_contexts;
1838 unsigned sc_prim_fifo_size_frontend;
1839 unsigned sc_prim_fifo_size_backend;
1840 unsigned sc_hiz_tile_fifo_size;
1841 unsigned sc_earlyz_tile_fifo_size;
1842
1843 unsigned num_tile_pipes;
1844 unsigned num_backends_per_se;
1845 unsigned backend_disable_mask_per_asic;
1846 unsigned backend_map;
1847 unsigned num_texture_channel_caches;
1848 unsigned mem_max_burst_length_bytes;
1849 unsigned mem_row_size_in_kb;
1850 unsigned shader_engine_tile_size;
1851 unsigned num_gpus;
1852 unsigned multi_gpu_tile_size;
1853
1854 unsigned tile_config;
39aee490 1855 uint32_t tile_mode_array[32];
8cc1a532
AD		 1856};
1857
068a117c
JG		 1858union radeon_asic_config {
1859 struct r300_asic r300;
551ebd83 1860 struct r100_asic r100;
3ce0a23d
JG		 1861 struct r600_asic r600;
1862 struct rv770_asic rv770;
32fcdbf4 1863 struct evergreen_asic evergreen;
fecf1d07 1864 struct cayman_asic cayman;
0a96d72b 1865 struct si_asic si;
8cc1a532 1866 struct cik_asic cik;
068a117c
JG		 1867};
1868
0a10c851
DV		 1869/*
1870 * asic initizalization from radeon_asic.c
1871 */
1872void radeon_agp_disable(struct radeon_device *rdev);
1873int radeon_asic_init(struct radeon_device *rdev);
1874
771fe6b9
JG		 1875
1876/*
1877 * IOCTL.
1878 */
1879int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1880 struct drm_file *filp);
1881int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1882 struct drm_file *filp);
1883int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1884 struct drm_file *file_priv);
1885int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1886 struct drm_file *file_priv);
1887int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1888 struct drm_file *file_priv);
1889int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1890 struct drm_file *file_priv);
1891int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1892 struct drm_file *filp);
1893int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1894 struct drm_file *filp);
1895int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1896 struct drm_file *filp);
1897int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1898 struct drm_file *filp);
721604a1
JG		 1899int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1900 struct drm_file *filp);
771fe6b9 1901int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1902int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1903 struct drm_file *filp);
1904int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1905 struct drm_file *filp);
771fe6b9 1906
16cdf04d
AD		 1907/* VRAM scratch page for HDP bug, default vram page */
1908struct r600_vram_scratch {
87cbf8f2
AD		 1909 struct radeon_bo *robj;
1910 volatile uint32_t *ptr;
16cdf04d 1911 u64 gpu_addr;
87cbf8f2 1912};
771fe6b9 1913
fd64ca8a
LT		 1914/*
1915 * ACPI
1916 */
1917struct radeon_atif_notification_cfg {
1918 bool enabled;
1919 int command_code;
1920};
1921
1922struct radeon_atif_notifications {
1923 bool display_switch;
1924 bool expansion_mode_change;
1925 bool thermal_state;
1926 bool forced_power_state;
1927 bool system_power_state;
1928 bool display_conf_change;
1929 bool px_gfx_switch;
1930 bool brightness_change;
1931 bool dgpu_display_event;
1932};
1933
1934struct radeon_atif_functions {
1935 bool system_params;
1936 bool sbios_requests;
1937 bool select_active_disp;
1938 bool lid_state;
1939 bool get_tv_standard;
1940 bool set_tv_standard;
1941 bool get_panel_expansion_mode;
1942 bool set_panel_expansion_mode;
1943 bool temperature_change;
1944 bool graphics_device_types;
1945};
1946
1947struct radeon_atif {
1948 struct radeon_atif_notifications notifications;
1949 struct radeon_atif_functions functions;
1950 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 1951 struct radeon_encoder *encoder_for_bl;
fd64ca8a 1952};
7a1619b9 1953
e3a15920
AD		 1954struct radeon_atcs_functions {
1955 bool get_ext_state;
1956 bool pcie_perf_req;
1957 bool pcie_dev_rdy;
1958 bool pcie_bus_width;
1959};
1960
1961struct radeon_atcs {
1962 struct radeon_atcs_functions functions;
1963};
1964
771fe6b9
JG		 1965/*
1966 * Core structure, functions and helpers.
1967 */
1968typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1969typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1970
1971struct radeon_device {
9f022ddf 1972 struct device *dev;
771fe6b9
JG		 1973 struct drm_device *ddev;
1974 struct pci_dev *pdev;
dee53e7f 1975 struct rw_semaphore exclusive_lock;
771fe6b9 1976 /* ASIC */
068a117c 1977 union radeon_asic_config config;
771fe6b9
JG		 1978 enum radeon_family family;
1979 unsigned long flags;
1980 int usec_timeout;
1981 enum radeon_pll_errata pll_errata;
1982 int num_gb_pipes;
f779b3e5 1983 int num_z_pipes;
771fe6b9
JG		 1984 int disp_priority;
1985 /* BIOS */
1986 uint8_t *bios;
1987 bool is_atom_bios;
1988 uint16_t bios_header_start;
4c788679 1989 struct radeon_bo *stollen_vga_memory;
771fe6b9 1990 /* Register mmio */
4c9bc75c
DA		 1991 resource_size_t rmmio_base;
1992 resource_size_t rmmio_size;
2c385151
DV		 1993 /* protects concurrent MM_INDEX/DATA based register access */
1994 spinlock_t mmio_idx_lock;
a0533fbf 1995 void __iomem *rmmio;
771fe6b9
JG		 1996 radeon_rreg_t mc_rreg;
1997 radeon_wreg_t mc_wreg;
1998 radeon_rreg_t pll_rreg;
1999 radeon_wreg_t pll_wreg;
de1b2898 2000 uint32_t pcie_reg_mask;
771fe6b9
JG		 2001 radeon_rreg_t pciep_rreg;
2002 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2003 /* io port */
2004 void __iomem *rio_mem;
2005 resource_size_t rio_mem_size;
771fe6b9
JG		 2006 struct radeon_clock clock;
2007 struct radeon_mc mc;
2008 struct radeon_gart gart;
2009 struct radeon_mode_info mode_info;
2010 struct radeon_scratch scratch;
75efdee1 2011 struct radeon_doorbell doorbell;
771fe6b9 2012 struct radeon_mman mman;
7465280c 2013 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2014 wait_queue_head_t fence_queue;
d6999bc7 2015 struct mutex ring_lock;
e32eb50d 2016 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2017 bool ib_pool_ready;
2018 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2019 struct radeon_irq irq;
2020 struct radeon_asic *asic;
2021 struct radeon_gem gem;
c93bb85b 2022 struct radeon_pm pm;
f2ba57b5 2023 struct radeon_uvd uvd;
f657c2a7 2024 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2025 struct radeon_wb wb;
3ce0a23d 2026 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2027 bool shutdown;
2028 bool suspend;
ad49f501 2029 bool need_dma32;
733289c2 2030 bool accel_working;
a0a53aa8 2031 bool fastfb_working; /* IGP feature*/
e024e110 2032 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2033 const struct firmware *me_fw; /* all family ME firmware */
2034 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2035 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2036 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2037 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2038 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2039 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2040 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2041 const struct firmware *uvd_fw; /* UVD firmware */
16cdf04d 2042 struct r600_vram_scratch vram_scratch;
3e5cb98d 2043 int msi_enabled; /* msi enabled */
d8f60cfc 2044 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2045 struct radeon_rlc rlc;
963e81f9 2046 struct radeon_mec mec;
d4877cf2 2047 struct work_struct hotplug_work;
f122c610 2048 struct work_struct audio_work;
8f61b34c 2049 struct work_struct reset_work;
18917b60 2050 int num_crtc; /* number of crtcs */
40bacf16 2051 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
3299de95 2052 bool audio_enabled;
948bee3f 2053 bool has_uvd;
3299de95 2054 struct r600_audio audio_status; /* audio stuff */
ce8f5370 2055 struct notifier_block acpi_nb;
9eba4a93 2056 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2057 struct drm_file *hyperz_filp;
9eba4a93 2058 struct drm_file *cmask_filp;
f376b94f
AD		 2059 /* i2c buses */
2060 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2061 /* debugfs */
2062 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2063 unsigned debugfs_count;
721604a1
JG		 2064 /* virtual memory */
2065 struct radeon_vm_manager vm_manager;
6759a0a7 2066 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2067 /* ACPI interface */
2068 struct radeon_atif atif;
e3a15920 2069 struct radeon_atcs atcs;
f61d5b46
AD		 2070 /* srbm instance registers */
2071 struct mutex srbm_mutex;
771fe6b9
JG		 2072};
2073
2074int radeon_device_init(struct radeon_device *rdev,
2075 struct drm_device *ddev,
2076 struct pci_dev *pdev,
2077 uint32_t flags);
2078void radeon_device_fini(struct radeon_device *rdev);
2079int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2080
2ef9bdfe
DV		 2081uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2082 bool always_indirect);
2083void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2084 bool always_indirect);
6fcbef7a
AK		 2085u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2086void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2087
75efdee1
AD		 2088u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2089void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2090
4c788679
JG		 2091/*
2092 * Cast helper
2093 */
2094#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2095
2096/*
2097 * Registers read & write functions.
2098 */
a0533fbf
BH		 2099#define RREG8(reg) readb((rdev->rmmio) + (reg))
2100#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2101#define RREG16(reg) readw((rdev->rmmio) + (reg))
2102#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2103#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2104#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2105#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2106#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2107#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2108#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2109#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2110#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2111#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2112#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2113#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2114#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2115#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2116#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2117#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2118#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2119#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2120#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2121#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2122#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2123#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2124#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2125#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2126#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2127#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2128#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2129#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
771fe6b9
JG		 2130#define WREG32_P(reg, val, mask) \
2131 do { \
2132 uint32_t tmp_ = RREG32(reg); \
2133 tmp_ &= (mask); \
2134 tmp_ |= ((val) & ~(mask)); \
2135 WREG32(reg, tmp_); \
2136 } while (0)
d5169fc4 2137#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2138#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2139#define WREG32_PLL_P(reg, val, mask) \
2140 do { \
2141 uint32_t tmp_ = RREG32_PLL(reg); \
2142 tmp_ &= (mask); \
2143 tmp_ |= ((val) & ~(mask)); \
2144 WREG32_PLL(reg, tmp_); \
2145 } while (0)
2ef9bdfe 2146#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2147#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2148#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2149
75efdee1
AD		 2150#define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2151#define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2152
de1b2898
DA		 2153/*
2154 * Indirect registers accessor
2155 */
2156static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2157{
2158 uint32_t r;
2159
2160 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2161 r = RREG32(RADEON_PCIE_DATA);
2162 return r;
2163}
2164
2165static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2166{
2167 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2168 WREG32(RADEON_PCIE_DATA, (v));
2169}
2170
1d5d0c34
AD		 2171static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2172{
2173 u32 r;
2174
2175 WREG32(TN_SMC_IND_INDEX_0, (reg));
2176 r = RREG32(TN_SMC_IND_DATA_0);
2177 return r;
2178}
2179
2180static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2181{
2182 WREG32(TN_SMC_IND_INDEX_0, (reg));
2183 WREG32(TN_SMC_IND_DATA_0, (v));
2184}
2185
ff82bbc4
AD		 2186static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2187{
2188 u32 r;
2189
2190 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2191 r = RREG32(R600_RCU_DATA);
2192 return r;
2193}
2194
2195static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2196{
2197 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2198 WREG32(R600_RCU_DATA, (v));
2199}
2200
46f9564a
AD		 2201static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2202{
2203 u32 r;
2204
2205 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2206 r = RREG32(EVERGREEN_CG_IND_DATA);
2207 return r;
2208}
2209
2210static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2211{
2212 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2213 WREG32(EVERGREEN_CG_IND_DATA, (v));
2214}
2215
792edd69
AD		 2216static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2217{
2218 u32 r;
2219
2220 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2221 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2222 return r;
2223}
2224
2225static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2226{
2227 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2228 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2229}
2230
2231static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2232{
2233 u32 r;
2234
2235 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2236 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2237 return r;
2238}
2239
2240static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2241{
2242 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2243 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2244}
2245
93656cdd
AD		 2246static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2247{
2248 u32 r;
2249
2250 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2251 r = RREG32(R600_UVD_CTX_DATA);
2252 return r;
2253}
2254
2255static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2256{
2257 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2258 WREG32(R600_UVD_CTX_DATA, (v));
2259}
2260
771fe6b9
JG		 2261void r100_pll_errata_after_index(struct radeon_device *rdev);
2262
2263
2264/*
2265 * ASICs helpers.
2266 */
b995e433
DA		 2267#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2268 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2269#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2270 (rdev->family == CHIP_RV200) || \
2271 (rdev->family == CHIP_RS100) || \
2272 (rdev->family == CHIP_RS200) || \
2273 (rdev->family == CHIP_RV250) || \
2274 (rdev->family == CHIP_RV280) || \
2275 (rdev->family == CHIP_RS300))
2276#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2277 (rdev->family == CHIP_RV350) || \
2278 (rdev->family == CHIP_R350) || \
2279 (rdev->family == CHIP_RV380) || \
2280 (rdev->family == CHIP_R420) || \
2281 (rdev->family == CHIP_R423) || \
2282 (rdev->family == CHIP_RV410) || \
2283 (rdev->family == CHIP_RS400) || \
2284 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2285#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2286 (rdev->ddev->pdev->device == 0x9443) || \
2287 (rdev->ddev->pdev->device == 0x944B) || \
2288 (rdev->ddev->pdev->device == 0x9506) || \
2289 (rdev->ddev->pdev->device == 0x9509) || \
2290 (rdev->ddev->pdev->device == 0x950F) || \
2291 (rdev->ddev->pdev->device == 0x689C) || \
2292 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2293#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2294#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2295 (rdev->family == CHIP_RS690) || \
2296 (rdev->family == CHIP_RS740) || \
2297 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2298#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2299#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2300#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2301#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2302 (rdev->flags & RADEON_IS_IGP))
1fe18305 2303#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2304#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2305#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2306 (rdev->flags & RADEON_IS_IGP))
624d3524 2307#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2308#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2309#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2310
dc50ba7f
AD		 2311#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2312 (rdev->ddev->pdev->device == 0x6850) || \
2313 (rdev->ddev->pdev->device == 0x6858) || \
2314 (rdev->ddev->pdev->device == 0x6859) || \
2315 (rdev->ddev->pdev->device == 0x6840) || \
2316 (rdev->ddev->pdev->device == 0x6841) || \
2317 (rdev->ddev->pdev->device == 0x6842) || \
2318 (rdev->ddev->pdev->device == 0x6843))
2319
771fe6b9
JG		 2320/*
2321 * BIOS helpers.
2322 */
2323#define RBIOS8(i) (rdev->bios[i])
2324#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2325#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2326
2327int radeon_combios_init(struct radeon_device *rdev);
2328void radeon_combios_fini(struct radeon_device *rdev);
2329int radeon_atombios_init(struct radeon_device *rdev);
2330void radeon_atombios_fini(struct radeon_device *rdev);
2331
2332
2333/*
2334 * RING helpers.
2335 */
ce580fab 2336#if DRM_DEBUG_CODE == 0
e32eb50d 2337static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2338{
e32eb50d
CK		 2339 ring->ring[ring->wptr++] = v;
2340 ring->wptr &= ring->ptr_mask;
2341 ring->count_dw--;
2342 ring->ring_free_dw--;
771fe6b9 2343}
ce580fab
AK		 2344#else
2345/* With debugging this is just too big to inline */
e32eb50d 2346void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2347#endif
771fe6b9
JG		 2348
2349/*
2350 * ASICs macro.
2351 */
068a117c 2352#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2353#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2354#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2355#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
eb0c19c5 2356#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
28d52043 2357#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2358#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2359#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2360#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2361#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2362#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2363#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
f712812e
AD		 2364#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2365#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2366#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
4c87bc26 2367#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
721604a1 2368#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
312c4a8c 2369#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
498522b4 2370#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
f93bdefe
AD		 2371#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2372#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2373#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
b35ea4ab
AD		 2374#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2375#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2376#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2377#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2378#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2379#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2380#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
4c87bc26
CK		 2381#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2382#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2383#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2384#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2385#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2386#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2387#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2388#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2389#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2390#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2391#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2392#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2393#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2394#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2395#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2396#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2397#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2398#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2399#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2400#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2401#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2402#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2403#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2404#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2405#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2406#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2407#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2408#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2409#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2410#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2411#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2412#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2413#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2414#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2415#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2416#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2417#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2418#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2419#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2420#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2421#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2422#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2423#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2424#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2425#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2426#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2427#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2428#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2429#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2430#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2431#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2432#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
771fe6b9 2433
6cf8a3f5 2434/* Common functions */
700a0cc0 2435/* AGP */
90aca4d2 2436extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2437extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2438extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2439extern int radeon_modeset_init(struct radeon_device *rdev);
2440extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2441extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2442extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2443extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2444extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2445extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2446extern void radeon_wb_fini(struct radeon_device *rdev);
2447extern int radeon_wb_init(struct radeon_device *rdev);
2448extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2449extern void radeon_surface_init(struct radeon_device *rdev);
2450extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2451extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2452extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2453extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2454extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2455extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2456extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 2457extern int radeon_resume_kms(struct drm_device *dev);
2458extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
53595338 2459extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2460extern void radeon_program_register_sequence(struct radeon_device *rdev,
2461 const u32 *registers,
2462 const u32 array_size);
6cf8a3f5 2463
721604a1
JG		 2464/*
2465 * vm
2466 */
2467int radeon_vm_manager_init(struct radeon_device *rdev);
2468void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2469void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2470void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2471int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2472void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2473struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2474 struct radeon_vm *vm, int ring);
2475void radeon_vm_fence(struct radeon_device *rdev,
2476 struct radeon_vm *vm,
2477 struct radeon_fence *fence);
dce34bfd 2478uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
721604a1
JG		 2479int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2480 struct radeon_vm *vm,
2481 struct radeon_bo *bo,
2482 struct ttm_mem_reg *mem);
2483void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2484 struct radeon_bo *bo);
421ca7ab
CK		 2485struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2486 struct radeon_bo *bo);
e971bd5e
CK		 2487struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2488 struct radeon_vm *vm,
2489 struct radeon_bo *bo);
2490int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2491 struct radeon_bo_va *bo_va,
2492 uint64_t offset,
2493 uint32_t flags);
721604a1 2494int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2495 struct radeon_bo_va *bo_va);
721604a1 2496
f122c610
AD		 2497/* audio */
2498void r600_audio_update_hdmi(struct work_struct *work);
721604a1 2499
16cdf04d
AD		 2500/*
2501 * R600 vram scratch functions
2502 */
2503int r600_vram_scratch_init(struct radeon_device *rdev);
2504void r600_vram_scratch_fini(struct radeon_device *rdev);
2505
285484e2
JG		 2506/*
2507 * r600 cs checking helper
2508 */
2509unsigned r600_mip_minify(unsigned size, unsigned level);
2510bool r600_fmt_is_valid_color(u32 format);
2511bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2512int r600_fmt_get_blocksize(u32 format);
2513int r600_fmt_get_nblocksx(u32 format, u32 w);
2514int r600_fmt_get_nblocksy(u32 format, u32 h);
2515
3574dda4
DV		 2516/*
2517 * r600 functions used by radeon_encoder.c
2518 */
1b688d08
RM		 2519struct radeon_hdmi_acr {
2520 u32 clock;
2521
2522 int n_32khz;
2523 int cts_32khz;
2524
2525 int n_44_1khz;
2526 int cts_44_1khz;
2527
2528 int n_48khz;
2529 int cts_48khz;
2530
2531};
2532
e55d3e6c
RM		 2533extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2534
416a2bd2
AD		 2535extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2536 u32 tiling_pipe_num,
2537 u32 max_rb_num,
2538 u32 total_max_rb_num,
2539 u32 enabled_rb_mask);
fe251e2f 2540
e55d3e6c
RM		 2541/*
2542 * evergreen functions used by radeon_encoder.c
2543 */
2544
0af62b01 2545extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2546extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2547
c4917074
AD		 2548/* radeon_acpi.c */
2549#if defined(CONFIG_ACPI)
2550extern int radeon_acpi_init(struct radeon_device *rdev);
2551extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2552extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2553extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2554 u8 perf_req, bool advertise);
dc50ba7f 2555extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2556#else
2557static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2558static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2559#endif
d7a2952f 2560
c38f34b5
IH		 2561int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2562 struct radeon_cs_packet *pkt,
2563 unsigned idx);
9ffb7a6d 2564bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2565void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2566 struct radeon_cs_packet *pkt);
e9716993
IH		 2567int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2568 struct radeon_cs_reloc **cs_reloc,
2569 int nomm);
40592a17
IH		 2570int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2571 uint32_t *vline_start_end,
2572 uint32_t *vline_status);
c38f34b5 2573
4c788679
JG		 2574#include "radeon_object.h"
2575
771fe6b9 2576#endif
Linux 6.x block layer and io_uring tree(s)