Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
60063497 | 63 | #include <linux/atomic.h> |
771fe6b9 JG |
64 | #include <linux/wait.h> |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
147666fb | 72 | #include <ttm/ttm_execbuf_util.h> |
4c788679 | 73 | |
c2142715 | 74 | #include "radeon_family.h" |
771fe6b9 JG |
75 | #include "radeon_mode.h" |
76 | #include "radeon_reg.h" | |
771fe6b9 JG |
77 | |
78 | /* | |
79 | * Modules parameters. | |
80 | */ | |
81 | extern int radeon_no_wb; | |
82 | extern int radeon_modeset; | |
83 | extern int radeon_dynclks; | |
84 | extern int radeon_r4xx_atom; | |
85 | extern int radeon_agpmode; | |
86 | extern int radeon_vram_limit; | |
87 | extern int radeon_gart_size; | |
88 | extern int radeon_benchmarking; | |
ecc0b326 | 89 | extern int radeon_testing; |
771fe6b9 | 90 | extern int radeon_connector_table; |
4ce001ab | 91 | extern int radeon_tv; |
dafc3bd5 | 92 | extern int radeon_audio; |
f46c0120 | 93 | extern int radeon_disp_priority; |
e2b0a8e1 | 94 | extern int radeon_hw_i2c; |
d42dd579 | 95 | extern int radeon_pcie_gen2; |
a18cee15 | 96 | extern int radeon_msi; |
3368ff0c | 97 | extern int radeon_lockup_timeout; |
a0a53aa8 | 98 | extern int radeon_fastfb; |
da321c8a | 99 | extern int radeon_dpm; |
1294d4a3 | 100 | extern int radeon_aspm; |
10ebc0bc | 101 | extern int radeon_runtime_pm; |
363eb0b4 | 102 | extern int radeon_hard_reset; |
771fe6b9 JG |
103 | |
104 | /* | |
105 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
106 | * symbol; | |
107 | */ | |
bb635567 JG |
108 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
109 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
e821767b | 110 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
bb635567 JG |
111 | #define RADEON_IB_POOL_SIZE 16 |
112 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 | |
113 | #define RADEONFB_CONN_LIMIT 4 | |
114 | #define RADEON_BIOS_NUM_SCRATCH 8 | |
771fe6b9 | 115 | |
bb635567 JG |
116 | /* fence seq are set to this number when signaled */ |
117 | #define RADEON_FENCE_SIGNALED_SEQ 0LL | |
1b37078b AD |
118 | |
119 | /* internal ring indices */ | |
120 | /* r1xx+ has gfx CP ring */ | |
d93f7937 | 121 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
1b37078b AD |
122 | |
123 | /* cayman has 2 compute CP rings */ | |
d93f7937 CK |
124 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
125 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 | |
1b37078b | 126 | |
4d75658b AD |
127 | /* R600+ has an async dma ring */ |
128 | #define R600_RING_TYPE_DMA_INDEX 3 | |
f60cbd11 AD |
129 | /* cayman add a second async dma ring */ |
130 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 | |
4d75658b | 131 | |
f2ba57b5 | 132 | /* R600+ */ |
d93f7937 CK |
133 | #define R600_RING_TYPE_UVD_INDEX 5 |
134 | ||
135 | /* TN+ */ | |
136 | #define TN_RING_TYPE_VCE1_INDEX 6 | |
137 | #define TN_RING_TYPE_VCE2_INDEX 7 | |
138 | ||
139 | /* max number of rings */ | |
140 | #define RADEON_NUM_RINGS 8 | |
f2ba57b5 | 141 | |
1c61eae4 CK |
142 | /* number of hw syncs before falling back on blocking */ |
143 | #define RADEON_NUM_SYNCS 4 | |
f2ba57b5 | 144 | |
8f53492f CK |
145 | /* number of hw syncs before falling back on blocking */ |
146 | #define RADEON_NUM_SYNCS 4 | |
147 | ||
721604a1 | 148 | /* hardcode those limit for now */ |
ca19f21e | 149 | #define RADEON_VA_IB_OFFSET (1 << 20) |
bb635567 JG |
150 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
151 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) | |
721604a1 | 152 | |
1a0041b8 AD |
153 | /* hard reset data */ |
154 | #define RADEON_ASIC_RESET_DATA 0x39d5e86b | |
155 | ||
ec46c76d AD |
156 | /* reset flags */ |
157 | #define RADEON_RESET_GFX (1 << 0) | |
158 | #define RADEON_RESET_COMPUTE (1 << 1) | |
159 | #define RADEON_RESET_DMA (1 << 2) | |
9ff0744c AD |
160 | #define RADEON_RESET_CP (1 << 3) |
161 | #define RADEON_RESET_GRBM (1 << 4) | |
162 | #define RADEON_RESET_DMA1 (1 << 5) | |
163 | #define RADEON_RESET_RLC (1 << 6) | |
164 | #define RADEON_RESET_SEM (1 << 7) | |
165 | #define RADEON_RESET_IH (1 << 8) | |
166 | #define RADEON_RESET_VMC (1 << 9) | |
167 | #define RADEON_RESET_MC (1 << 10) | |
168 | #define RADEON_RESET_DISPLAY (1 << 11) | |
ec46c76d | 169 | |
22c775ce AD |
170 | /* CG block flags */ |
171 | #define RADEON_CG_BLOCK_GFX (1 << 0) | |
172 | #define RADEON_CG_BLOCK_MC (1 << 1) | |
173 | #define RADEON_CG_BLOCK_SDMA (1 << 2) | |
174 | #define RADEON_CG_BLOCK_UVD (1 << 3) | |
175 | #define RADEON_CG_BLOCK_VCE (1 << 4) | |
176 | #define RADEON_CG_BLOCK_HDP (1 << 5) | |
e16866ec | 177 | #define RADEON_CG_BLOCK_BIF (1 << 6) |
22c775ce | 178 | |
64d8a728 AD |
179 | /* CG flags */ |
180 | #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) | |
181 | #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) | |
182 | #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) | |
183 | #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) | |
184 | #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) | |
185 | #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) | |
186 | #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) | |
187 | #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) | |
188 | #define RADEON_CG_SUPPORT_MC_LS (1 << 8) | |
189 | #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) | |
190 | #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) | |
191 | #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) | |
192 | #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) | |
193 | #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) | |
194 | #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) | |
195 | #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) | |
196 | #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) | |
197 | ||
198 | /* PG flags */ | |
2b19d17f | 199 | #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) |
64d8a728 AD |
200 | #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) |
201 | #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) | |
202 | #define RADEON_PG_SUPPORT_UVD (1 << 3) | |
203 | #define RADEON_PG_SUPPORT_VCE (1 << 4) | |
204 | #define RADEON_PG_SUPPORT_CP (1 << 5) | |
205 | #define RADEON_PG_SUPPORT_GDS (1 << 6) | |
206 | #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) | |
207 | #define RADEON_PG_SUPPORT_SDMA (1 << 8) | |
208 | #define RADEON_PG_SUPPORT_ACP (1 << 9) | |
209 | #define RADEON_PG_SUPPORT_SAMU (1 << 10) | |
210 | ||
9e05fa1d AD |
211 | /* max cursor sizes (in pixels) */ |
212 | #define CURSOR_WIDTH 64 | |
213 | #define CURSOR_HEIGHT 64 | |
214 | ||
215 | #define CIK_CURSOR_WIDTH 128 | |
216 | #define CIK_CURSOR_HEIGHT 128 | |
217 | ||
771fe6b9 JG |
218 | /* |
219 | * Errata workarounds. | |
220 | */ | |
221 | enum radeon_pll_errata { | |
222 | CHIP_ERRATA_R300_CG = 0x00000001, | |
223 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
224 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
225 | }; | |
226 | ||
227 | ||
228 | struct radeon_device; | |
229 | ||
230 | ||
231 | /* | |
232 | * BIOS. | |
233 | */ | |
234 | bool radeon_get_bios(struct radeon_device *rdev); | |
235 | ||
236 | /* | |
3ce0a23d | 237 | * Dummy page |
771fe6b9 | 238 | */ |
3ce0a23d JG |
239 | struct radeon_dummy_page { |
240 | struct page *page; | |
241 | dma_addr_t addr; | |
242 | }; | |
243 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
244 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
245 | ||
771fe6b9 | 246 | |
3ce0a23d JG |
247 | /* |
248 | * Clocks | |
249 | */ | |
771fe6b9 JG |
250 | struct radeon_clock { |
251 | struct radeon_pll p1pll; | |
252 | struct radeon_pll p2pll; | |
bcc1c2a1 | 253 | struct radeon_pll dcpll; |
771fe6b9 JG |
254 | struct radeon_pll spll; |
255 | struct radeon_pll mpll; | |
256 | /* 10 Khz units */ | |
257 | uint32_t default_mclk; | |
258 | uint32_t default_sclk; | |
bcc1c2a1 | 259 | uint32_t default_dispclk; |
4489cd62 | 260 | uint32_t current_dispclk; |
bcc1c2a1 | 261 | uint32_t dp_extclk; |
b20f9bef | 262 | uint32_t max_pixel_clock; |
771fe6b9 JG |
263 | }; |
264 | ||
7433874e RM |
265 | /* |
266 | * Power management | |
267 | */ | |
268 | int radeon_pm_init(struct radeon_device *rdev); | |
914a8987 | 269 | int radeon_pm_late_init(struct radeon_device *rdev); |
29fb52ca | 270 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 271 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
ce8f5370 AD |
272 | void radeon_pm_suspend(struct radeon_device *rdev); |
273 | void radeon_pm_resume(struct radeon_device *rdev); | |
56278a8e AD |
274 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
275 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
7062ab67 CK |
276 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
277 | u8 clock_type, | |
278 | u32 clock, | |
279 | bool strobe_mode, | |
280 | struct atom_clock_dividers *dividers); | |
eaa778af AD |
281 | int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, |
282 | u32 clock, | |
283 | bool strobe_mode, | |
284 | struct atom_mpll_param *mpll_param); | |
8a83ec5e | 285 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
ae5b0abb AD |
286 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
287 | u16 voltage_level, u8 voltage_type, | |
288 | u32 *gpio_value, u32 *gpio_mask); | |
289 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, | |
290 | u32 eng_clock, u32 mem_clock); | |
291 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, | |
292 | u8 voltage_type, u16 *voltage_step); | |
4a6369e9 AD |
293 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, |
294 | u16 voltage_id, u16 *voltage); | |
beb79f40 AD |
295 | int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, |
296 | u16 *voltage, | |
297 | u16 leakage_idx); | |
cc8dbbb4 AD |
298 | int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, |
299 | u16 *leakage_id); | |
300 | int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, | |
301 | u16 *vddc, u16 *vddci, | |
302 | u16 virtual_voltage_id, | |
303 | u16 vbios_voltage_id); | |
ae5b0abb AD |
304 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, |
305 | u8 voltage_type, | |
306 | u16 nominal_voltage, | |
307 | u16 *true_voltage); | |
308 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, | |
309 | u8 voltage_type, u16 *min_voltage); | |
310 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, | |
311 | u8 voltage_type, u16 *max_voltage); | |
312 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, | |
65171944 | 313 | u8 voltage_type, u8 voltage_mode, |
ae5b0abb | 314 | struct atom_voltage_table *voltage_table); |
58653abd AD |
315 | bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, |
316 | u8 voltage_type, u8 voltage_mode); | |
ae5b0abb AD |
317 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, |
318 | u32 mem_clock); | |
319 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, | |
320 | u32 mem_clock); | |
321 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, | |
322 | u8 module_index, | |
323 | struct atom_mc_reg_table *reg_table); | |
324 | int radeon_atom_get_memory_info(struct radeon_device *rdev, | |
325 | u8 module_index, struct atom_memory_info *mem_info); | |
326 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, | |
327 | bool gddr5, u8 module_index, | |
328 | struct atom_memory_clock_range_table *mclk_range_table); | |
329 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, | |
330 | u16 voltage_id, u16 *voltage); | |
f892034a | 331 | void rs690_pm_info(struct radeon_device *rdev); |
285484e2 JG |
332 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
333 | unsigned *bankh, unsigned *mtaspect, | |
334 | unsigned *tile_split); | |
3ce0a23d | 335 | |
771fe6b9 JG |
336 | /* |
337 | * Fences. | |
338 | */ | |
339 | struct radeon_fence_driver { | |
340 | uint32_t scratch_reg; | |
30eb77f4 JG |
341 | uint64_t gpu_addr; |
342 | volatile uint32_t *cpu_addr; | |
68e250b7 CK |
343 | /* sync_seq is protected by ring emission lock */ |
344 | uint64_t sync_seq[RADEON_NUM_RINGS]; | |
bb635567 | 345 | atomic64_t last_seq; |
0a0c7596 | 346 | bool initialized; |
771fe6b9 JG |
347 | }; |
348 | ||
349 | struct radeon_fence { | |
350 | struct radeon_device *rdev; | |
351 | struct kref kref; | |
771fe6b9 | 352 | /* protected by radeon_fence.lock */ |
bb635567 | 353 | uint64_t seq; |
7465280c | 354 | /* RB, DMA, etc. */ |
bb635567 | 355 | unsigned ring; |
771fe6b9 JG |
356 | }; |
357 | ||
30eb77f4 JG |
358 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
359 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
771fe6b9 | 360 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
76903b96 | 361 | void radeon_fence_driver_force_completion(struct radeon_device *rdev); |
876dc9f3 | 362 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
7465280c | 363 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
771fe6b9 JG |
364 | bool radeon_fence_signaled(struct radeon_fence *fence); |
365 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
37615527 CK |
366 | int radeon_fence_wait_next(struct radeon_device *rdev, int ring); |
367 | int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); | |
0085c950 JG |
368 | int radeon_fence_wait_any(struct radeon_device *rdev, |
369 | struct radeon_fence **fences, | |
370 | bool intr); | |
771fe6b9 JG |
371 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
372 | void radeon_fence_unref(struct radeon_fence **fence); | |
3b7a2b24 | 373 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
68e250b7 CK |
374 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
375 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); | |
376 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, | |
377 | struct radeon_fence *b) | |
378 | { | |
379 | if (!a) { | |
380 | return b; | |
381 | } | |
382 | ||
383 | if (!b) { | |
384 | return a; | |
385 | } | |
386 | ||
387 | BUG_ON(a->ring != b->ring); | |
388 | ||
389 | if (a->seq > b->seq) { | |
390 | return a; | |
391 | } else { | |
392 | return b; | |
393 | } | |
394 | } | |
771fe6b9 | 395 | |
ee60e29f CK |
396 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
397 | struct radeon_fence *b) | |
398 | { | |
399 | if (!a) { | |
400 | return false; | |
401 | } | |
402 | ||
403 | if (!b) { | |
404 | return true; | |
405 | } | |
406 | ||
407 | BUG_ON(a->ring != b->ring); | |
408 | ||
409 | return a->seq < b->seq; | |
410 | } | |
411 | ||
e024e110 DA |
412 | /* |
413 | * Tiling registers | |
414 | */ | |
415 | struct radeon_surface_reg { | |
4c788679 | 416 | struct radeon_bo *bo; |
e024e110 DA |
417 | }; |
418 | ||
419 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
420 | |
421 | /* | |
4c788679 | 422 | * TTM. |
771fe6b9 | 423 | */ |
4c788679 JG |
424 | struct radeon_mman { |
425 | struct ttm_bo_global_ref bo_global_ref; | |
ba4420c2 | 426 | struct drm_global_reference mem_global_ref; |
4c788679 | 427 | struct ttm_bo_device bdev; |
0a0c7596 JG |
428 | bool mem_global_referenced; |
429 | bool initialized; | |
2014b569 CK |
430 | |
431 | #if defined(CONFIG_DEBUG_FS) | |
432 | struct dentry *vram; | |
dd66d20e | 433 | struct dentry *gtt; |
2014b569 | 434 | #endif |
4c788679 JG |
435 | }; |
436 | ||
721604a1 JG |
437 | /* bo virtual address in a specific vm */ |
438 | struct radeon_bo_va { | |
e971bd5e | 439 | /* protected by bo being reserved */ |
721604a1 | 440 | struct list_head bo_list; |
721604a1 JG |
441 | uint64_t soffset; |
442 | uint64_t eoffset; | |
443 | uint32_t flags; | |
444 | bool valid; | |
e971bd5e CK |
445 | unsigned ref_count; |
446 | ||
447 | /* protected by vm mutex */ | |
448 | struct list_head vm_list; | |
449 | ||
450 | /* constant after initialization */ | |
451 | struct radeon_vm *vm; | |
452 | struct radeon_bo *bo; | |
721604a1 JG |
453 | }; |
454 | ||
4c788679 JG |
455 | struct radeon_bo { |
456 | /* Protected by gem.mutex */ | |
457 | struct list_head list; | |
458 | /* Protected by tbo.reserved */ | |
bda72d58 | 459 | u32 initial_domain; |
312ea8da JG |
460 | u32 placements[3]; |
461 | struct ttm_placement placement; | |
4c788679 JG |
462 | struct ttm_buffer_object tbo; |
463 | struct ttm_bo_kmap_obj kmap; | |
464 | unsigned pin_count; | |
465 | void *kptr; | |
466 | u32 tiling_flags; | |
467 | u32 pitch; | |
468 | int surface_reg; | |
721604a1 JG |
469 | /* list of all virtual address to which this bo |
470 | * is associated to | |
471 | */ | |
472 | struct list_head va; | |
4c788679 JG |
473 | /* Constant after initialization */ |
474 | struct radeon_device *rdev; | |
441921d5 | 475 | struct drm_gem_object gem_base; |
63bc620b | 476 | |
409851f4 JG |
477 | struct ttm_bo_kmap_obj dma_buf_vmap; |
478 | pid_t pid; | |
4c788679 | 479 | }; |
7e4d15d9 | 480 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
771fe6b9 | 481 | |
409851f4 JG |
482 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
483 | ||
b15ba512 JG |
484 | /* sub-allocation manager, it has to be protected by another lock. |
485 | * By conception this is an helper for other part of the driver | |
486 | * like the indirect buffer or semaphore, which both have their | |
487 | * locking. | |
488 | * | |
489 | * Principe is simple, we keep a list of sub allocation in offset | |
490 | * order (first entry has offset == 0, last entry has the highest | |
491 | * offset). | |
492 | * | |
493 | * When allocating new object we first check if there is room at | |
494 | * the end total_size - (last_object_offset + last_object_size) >= | |
495 | * alloc_size. If so we allocate new object there. | |
496 | * | |
497 | * When there is not enough room at the end, we start waiting for | |
498 | * each sub object until we reach object_offset+object_size >= | |
499 | * alloc_size, this object then become the sub object we return. | |
500 | * | |
501 | * Alignment can't be bigger than page size. | |
502 | * | |
503 | * Hole are not considered for allocation to keep things simple. | |
504 | * Assumption is that there won't be hole (all object on same | |
505 | * alignment). | |
506 | */ | |
507 | struct radeon_sa_manager { | |
bfb38d35 | 508 | wait_queue_head_t wq; |
b15ba512 | 509 | struct radeon_bo *bo; |
c3b7fe8b CK |
510 | struct list_head *hole; |
511 | struct list_head flist[RADEON_NUM_RINGS]; | |
512 | struct list_head olist; | |
b15ba512 JG |
513 | unsigned size; |
514 | uint64_t gpu_addr; | |
515 | void *cpu_ptr; | |
516 | uint32_t domain; | |
6c4f978b | 517 | uint32_t align; |
b15ba512 JG |
518 | }; |
519 | ||
520 | struct radeon_sa_bo; | |
521 | ||
522 | /* sub-allocation buffer */ | |
523 | struct radeon_sa_bo { | |
c3b7fe8b CK |
524 | struct list_head olist; |
525 | struct list_head flist; | |
b15ba512 | 526 | struct radeon_sa_manager *manager; |
e6661a96 CK |
527 | unsigned soffset; |
528 | unsigned eoffset; | |
557017a0 | 529 | struct radeon_fence *fence; |
b15ba512 JG |
530 | }; |
531 | ||
771fe6b9 JG |
532 | /* |
533 | * GEM objects. | |
534 | */ | |
535 | struct radeon_gem { | |
4c788679 | 536 | struct mutex mutex; |
771fe6b9 JG |
537 | struct list_head objects; |
538 | }; | |
539 | ||
540 | int radeon_gem_init(struct radeon_device *rdev); | |
541 | void radeon_gem_fini(struct radeon_device *rdev); | |
542 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
543 | int alignment, int initial_domain, |
544 | bool discardable, bool kernel, | |
545 | struct drm_gem_object **obj); | |
771fe6b9 | 546 | |
ff72145b DA |
547 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
548 | struct drm_device *dev, | |
549 | struct drm_mode_create_dumb *args); | |
550 | int radeon_mode_dumb_mmap(struct drm_file *filp, | |
551 | struct drm_device *dev, | |
552 | uint32_t handle, uint64_t *offset_p); | |
771fe6b9 | 553 | |
c1341e52 JG |
554 | /* |
555 | * Semaphores. | |
556 | */ | |
c1341e52 | 557 | struct radeon_semaphore { |
a8c05940 JG |
558 | struct radeon_sa_bo *sa_bo; |
559 | signed waiters; | |
c1341e52 | 560 | uint64_t gpu_addr; |
1654b817 | 561 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
c1341e52 JG |
562 | }; |
563 | ||
c1341e52 JG |
564 | int radeon_semaphore_create(struct radeon_device *rdev, |
565 | struct radeon_semaphore **semaphore); | |
1654b817 | 566 | bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
c1341e52 | 567 | struct radeon_semaphore *semaphore); |
1654b817 | 568 | bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
c1341e52 | 569 | struct radeon_semaphore *semaphore); |
1654b817 CK |
570 | void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore, |
571 | struct radeon_fence *fence); | |
8f676c4c CK |
572 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
573 | struct radeon_semaphore *semaphore, | |
1654b817 | 574 | int waiting_ring); |
c1341e52 | 575 | void radeon_semaphore_free(struct radeon_device *rdev, |
220907d9 | 576 | struct radeon_semaphore **semaphore, |
a8c05940 | 577 | struct radeon_fence *fence); |
c1341e52 | 578 | |
771fe6b9 JG |
579 | /* |
580 | * GART structures, functions & helpers | |
581 | */ | |
582 | struct radeon_mc; | |
583 | ||
a77f1718 | 584 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 585 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
003cefe0 | 586 | #define RADEON_GPU_PAGE_SHIFT 12 |
721604a1 | 587 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
a77f1718 | 588 | |
771fe6b9 JG |
589 | struct radeon_gart { |
590 | dma_addr_t table_addr; | |
c9a1be96 JG |
591 | struct radeon_bo *robj; |
592 | void *ptr; | |
771fe6b9 JG |
593 | unsigned num_gpu_pages; |
594 | unsigned num_cpu_pages; | |
595 | unsigned table_size; | |
771fe6b9 JG |
596 | struct page **pages; |
597 | dma_addr_t *pages_addr; | |
598 | bool ready; | |
599 | }; | |
600 | ||
601 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
602 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
603 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
604 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
c9a1be96 JG |
605 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
606 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); | |
771fe6b9 JG |
607 | int radeon_gart_init(struct radeon_device *rdev); |
608 | void radeon_gart_fini(struct radeon_device *rdev); | |
609 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
610 | int pages); | |
611 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
c39d3516 KRW |
612 | int pages, struct page **pagelist, |
613 | dma_addr_t *dma_addr); | |
c9a1be96 | 614 | void radeon_gart_restore(struct radeon_device *rdev); |
771fe6b9 JG |
615 | |
616 | ||
617 | /* | |
618 | * GPU MC structures, functions & helpers | |
619 | */ | |
620 | struct radeon_mc { | |
621 | resource_size_t aper_size; | |
622 | resource_size_t aper_base; | |
623 | resource_size_t agp_base; | |
7a50f01a DA |
624 | /* for some chips with <= 32MB we need to lie |
625 | * about vram size near mc fb location */ | |
3ce0a23d | 626 | u64 mc_vram_size; |
d594e46a | 627 | u64 visible_vram_size; |
3ce0a23d JG |
628 | u64 gtt_size; |
629 | u64 gtt_start; | |
630 | u64 gtt_end; | |
3ce0a23d JG |
631 | u64 vram_start; |
632 | u64 vram_end; | |
771fe6b9 | 633 | unsigned vram_width; |
3ce0a23d | 634 | u64 real_vram_size; |
771fe6b9 JG |
635 | int vram_mtrr; |
636 | bool vram_is_ddr; | |
d594e46a | 637 | bool igp_sideport_enabled; |
8d369bb1 | 638 | u64 gtt_base_align; |
9ed8b1f9 | 639 | u64 mc_mask; |
771fe6b9 JG |
640 | }; |
641 | ||
06b6476d AD |
642 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
643 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
644 | |
645 | /* | |
646 | * GPU scratch registers structures, functions & helpers | |
647 | */ | |
648 | struct radeon_scratch { | |
649 | unsigned num_reg; | |
724c80e1 | 650 | uint32_t reg_base; |
771fe6b9 JG |
651 | bool free[32]; |
652 | uint32_t reg[32]; | |
653 | }; | |
654 | ||
655 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
656 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
657 | ||
75efdee1 AD |
658 | /* |
659 | * GPU doorbell structures, functions & helpers | |
660 | */ | |
d5754ab8 AL |
661 | #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ |
662 | ||
75efdee1 | 663 | struct radeon_doorbell { |
75efdee1 | 664 | /* doorbell mmio */ |
d5754ab8 AL |
665 | resource_size_t base; |
666 | resource_size_t size; | |
667 | u32 __iomem *ptr; | |
668 | u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ | |
669 | unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; | |
75efdee1 AD |
670 | }; |
671 | ||
672 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); | |
673 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); | |
771fe6b9 JG |
674 | |
675 | /* | |
676 | * IRQS. | |
677 | */ | |
6f34be50 | 678 | |
1aab5514 CK |
679 | struct radeon_flip_work { |
680 | struct work_struct flip_work; | |
681 | struct work_struct unpin_work; | |
682 | struct radeon_device *rdev; | |
683 | int crtc_id; | |
684 | struct drm_framebuffer *fb; | |
6f34be50 | 685 | struct drm_pending_vblank_event *event; |
1aab5514 CK |
686 | struct radeon_bo *old_rbo; |
687 | struct radeon_bo *new_rbo; | |
688 | struct radeon_fence *fence; | |
6f34be50 AD |
689 | }; |
690 | ||
691 | struct r500_irq_stat_regs { | |
692 | u32 disp_int; | |
f122c610 | 693 | u32 hdmi0_status; |
6f34be50 AD |
694 | }; |
695 | ||
696 | struct r600_irq_stat_regs { | |
697 | u32 disp_int; | |
698 | u32 disp_int_cont; | |
699 | u32 disp_int_cont2; | |
700 | u32 d1grph_int; | |
701 | u32 d2grph_int; | |
f122c610 AD |
702 | u32 hdmi0_status; |
703 | u32 hdmi1_status; | |
6f34be50 AD |
704 | }; |
705 | ||
706 | struct evergreen_irq_stat_regs { | |
707 | u32 disp_int; | |
708 | u32 disp_int_cont; | |
709 | u32 disp_int_cont2; | |
710 | u32 disp_int_cont3; | |
711 | u32 disp_int_cont4; | |
712 | u32 disp_int_cont5; | |
713 | u32 d1grph_int; | |
714 | u32 d2grph_int; | |
715 | u32 d3grph_int; | |
716 | u32 d4grph_int; | |
717 | u32 d5grph_int; | |
718 | u32 d6grph_int; | |
f122c610 AD |
719 | u32 afmt_status1; |
720 | u32 afmt_status2; | |
721 | u32 afmt_status3; | |
722 | u32 afmt_status4; | |
723 | u32 afmt_status5; | |
724 | u32 afmt_status6; | |
6f34be50 AD |
725 | }; |
726 | ||
a59781bb AD |
727 | struct cik_irq_stat_regs { |
728 | u32 disp_int; | |
729 | u32 disp_int_cont; | |
730 | u32 disp_int_cont2; | |
731 | u32 disp_int_cont3; | |
732 | u32 disp_int_cont4; | |
733 | u32 disp_int_cont5; | |
734 | u32 disp_int_cont6; | |
735 | }; | |
736 | ||
6f34be50 AD |
737 | union radeon_irq_stat_regs { |
738 | struct r500_irq_stat_regs r500; | |
739 | struct r600_irq_stat_regs r600; | |
740 | struct evergreen_irq_stat_regs evergreen; | |
a59781bb | 741 | struct cik_irq_stat_regs cik; |
6f34be50 AD |
742 | }; |
743 | ||
be0949f5 | 744 | #define RADEON_MAX_HPD_PINS 7 |
54bd5206 | 745 | #define RADEON_MAX_CRTCS 6 |
b530602f | 746 | #define RADEON_MAX_AFMT_BLOCKS 7 |
54bd5206 | 747 | |
771fe6b9 | 748 | struct radeon_irq { |
fb98257a CK |
749 | bool installed; |
750 | spinlock_t lock; | |
736fc37f | 751 | atomic_t ring_int[RADEON_NUM_RINGS]; |
fb98257a | 752 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
736fc37f | 753 | atomic_t pflip[RADEON_MAX_CRTCS]; |
fb98257a CK |
754 | wait_queue_head_t vblank_queue; |
755 | bool hpd[RADEON_MAX_HPD_PINS]; | |
fb98257a CK |
756 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
757 | union radeon_irq_stat_regs stat_regs; | |
4a6369e9 | 758 | bool dpm_thermal; |
771fe6b9 JG |
759 | }; |
760 | ||
761 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
762 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1b37078b AD |
763 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
764 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); | |
6f34be50 AD |
765 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
766 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); | |
fb98257a CK |
767 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
768 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); | |
769 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
770 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
771fe6b9 JG |
771 | |
772 | /* | |
e32eb50d | 773 | * CP & rings. |
771fe6b9 | 774 | */ |
7465280c | 775 | |
771fe6b9 | 776 | struct radeon_ib { |
68470ae7 JG |
777 | struct radeon_sa_bo *sa_bo; |
778 | uint32_t length_dw; | |
779 | uint64_t gpu_addr; | |
780 | uint32_t *ptr; | |
876dc9f3 | 781 | int ring; |
68470ae7 | 782 | struct radeon_fence *fence; |
4bf3dd92 | 783 | struct radeon_vm *vm; |
68470ae7 JG |
784 | bool is_const_ib; |
785 | struct radeon_semaphore *semaphore; | |
771fe6b9 JG |
786 | }; |
787 | ||
e32eb50d | 788 | struct radeon_ring { |
4c788679 | 789 | struct radeon_bo *ring_obj; |
771fe6b9 | 790 | volatile uint32_t *ring; |
5596a9db | 791 | unsigned rptr_offs; |
45df6803 | 792 | unsigned rptr_save_reg; |
89d35807 AD |
793 | u64 next_rptr_gpu_addr; |
794 | volatile u32 *next_rptr_cpu_addr; | |
771fe6b9 JG |
795 | unsigned wptr; |
796 | unsigned wptr_old; | |
797 | unsigned ring_size; | |
798 | unsigned ring_free_dw; | |
799 | int count_dw; | |
aee4aa73 CK |
800 | atomic_t last_rptr; |
801 | atomic64_t last_activity; | |
771fe6b9 JG |
802 | uint64_t gpu_addr; |
803 | uint32_t align_mask; | |
804 | uint32_t ptr_mask; | |
771fe6b9 | 805 | bool ready; |
78c5560a | 806 | u32 nop; |
8b25ed34 | 807 | u32 idx; |
5f0839c1 JG |
808 | u64 last_semaphore_signal_addr; |
809 | u64 last_semaphore_wait_addr; | |
963e81f9 AD |
810 | /* for CIK queues */ |
811 | u32 me; | |
812 | u32 pipe; | |
813 | u32 queue; | |
814 | struct radeon_bo *mqd_obj; | |
d5754ab8 | 815 | u32 doorbell_index; |
963e81f9 AD |
816 | unsigned wptr_offs; |
817 | }; | |
818 | ||
819 | struct radeon_mec { | |
820 | struct radeon_bo *hpd_eop_obj; | |
821 | u64 hpd_eop_gpu_addr; | |
822 | u32 num_pipe; | |
823 | u32 num_mec; | |
824 | u32 num_queue; | |
771fe6b9 JG |
825 | }; |
826 | ||
721604a1 JG |
827 | /* |
828 | * VM | |
829 | */ | |
ee60e29f | 830 | |
fa87e62d | 831 | /* maximum number of VMIDs */ |
ee60e29f CK |
832 | #define RADEON_NUM_VM 16 |
833 | ||
fa87e62d DC |
834 | /* defines number of bits in page table versus page directory, |
835 | * a page is 4KB so we have 12 bits offset, 9 bits in the page | |
836 | * table and the remaining 19 bits are in the page directory */ | |
837 | #define RADEON_VM_BLOCK_SIZE 9 | |
838 | ||
839 | /* number of entries in page table */ | |
840 | #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) | |
841 | ||
1c01103c AD |
842 | /* PTBs (Page Table Blocks) need to be aligned to 32K */ |
843 | #define RADEON_VM_PTB_ALIGN_SIZE 32768 | |
844 | #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) | |
845 | #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) | |
846 | ||
24c16439 CK |
847 | #define R600_PTE_VALID (1 << 0) |
848 | #define R600_PTE_SYSTEM (1 << 1) | |
849 | #define R600_PTE_SNOOPED (1 << 2) | |
850 | #define R600_PTE_READABLE (1 << 5) | |
851 | #define R600_PTE_WRITEABLE (1 << 6) | |
852 | ||
ec3dbbcb CK |
853 | /* PTE (Page Table Entry) fragment field for different page sizes */ |
854 | #define R600_PTE_FRAG_4KB (0 << 7) | |
855 | #define R600_PTE_FRAG_64KB (4 << 7) | |
856 | #define R600_PTE_FRAG_256KB (6 << 7) | |
857 | ||
6d2f2944 CK |
858 | struct radeon_vm_pt { |
859 | struct radeon_bo *bo; | |
860 | uint64_t addr; | |
861 | }; | |
862 | ||
721604a1 | 863 | struct radeon_vm { |
721604a1 | 864 | struct list_head va; |
ee60e29f | 865 | unsigned id; |
90a51a32 CK |
866 | |
867 | /* contains the page directory */ | |
6d2f2944 | 868 | struct radeon_bo *page_directory; |
90a51a32 | 869 | uint64_t pd_gpu_addr; |
6d2f2944 | 870 | unsigned max_pde_used; |
90a51a32 CK |
871 | |
872 | /* array of page tables, one for each page directory entry */ | |
6d2f2944 | 873 | struct radeon_vm_pt *page_tables; |
90a51a32 | 874 | |
721604a1 JG |
875 | struct mutex mutex; |
876 | /* last fence for cs using this vm */ | |
877 | struct radeon_fence *fence; | |
9b40e5d8 CK |
878 | /* last flush or NULL if we still need to flush */ |
879 | struct radeon_fence *last_flush; | |
593b2635 CK |
880 | /* last use of vmid */ |
881 | struct radeon_fence *last_id_use; | |
721604a1 JG |
882 | }; |
883 | ||
721604a1 | 884 | struct radeon_vm_manager { |
ee60e29f | 885 | struct radeon_fence *active[RADEON_NUM_VM]; |
721604a1 | 886 | uint32_t max_pfn; |
721604a1 JG |
887 | /* number of VMIDs */ |
888 | unsigned nvm; | |
889 | /* vram base address for page table entry */ | |
890 | u64 vram_base_offset; | |
67e915e4 AD |
891 | /* is vm enabled? */ |
892 | bool enabled; | |
721604a1 JG |
893 | }; |
894 | ||
895 | /* | |
896 | * file private structure | |
897 | */ | |
898 | struct radeon_fpriv { | |
899 | struct radeon_vm vm; | |
900 | }; | |
901 | ||
d8f60cfc AD |
902 | /* |
903 | * R6xx+ IH ring | |
904 | */ | |
905 | struct r600_ih { | |
4c788679 | 906 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
907 | volatile uint32_t *ring; |
908 | unsigned rptr; | |
d8f60cfc AD |
909 | unsigned ring_size; |
910 | uint64_t gpu_addr; | |
d8f60cfc | 911 | uint32_t ptr_mask; |
c20dc369 | 912 | atomic_t lock; |
d8f60cfc AD |
913 | bool enabled; |
914 | }; | |
915 | ||
347e7592 | 916 | /* |
2948f5e6 | 917 | * RLC stuff |
347e7592 | 918 | */ |
2948f5e6 AD |
919 | #include "clearstate_defs.h" |
920 | ||
921 | struct radeon_rlc { | |
347e7592 AD |
922 | /* for power gating */ |
923 | struct radeon_bo *save_restore_obj; | |
924 | uint64_t save_restore_gpu_addr; | |
2948f5e6 | 925 | volatile uint32_t *sr_ptr; |
1fd11777 | 926 | const u32 *reg_list; |
2948f5e6 | 927 | u32 reg_list_size; |
347e7592 AD |
928 | /* for clear state */ |
929 | struct radeon_bo *clear_state_obj; | |
930 | uint64_t clear_state_gpu_addr; | |
2948f5e6 | 931 | volatile uint32_t *cs_ptr; |
1fd11777 | 932 | const struct cs_section_def *cs_data; |
22c775ce AD |
933 | u32 clear_state_size; |
934 | /* for cp tables */ | |
935 | struct radeon_bo *cp_table_obj; | |
936 | uint64_t cp_table_gpu_addr; | |
937 | volatile uint32_t *cp_table_ptr; | |
938 | u32 cp_table_size; | |
347e7592 AD |
939 | }; |
940 | ||
69e130a6 | 941 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
942 | struct radeon_ib *ib, struct radeon_vm *vm, |
943 | unsigned size); | |
f2e39221 | 944 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
4ef72566 CK |
945 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
946 | struct radeon_ib *const_ib); | |
771fe6b9 JG |
947 | int radeon_ib_pool_init(struct radeon_device *rdev); |
948 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
7bd560e8 | 949 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
771fe6b9 | 950 | /* Ring access between begin & end cannot sleep */ |
89d35807 AD |
951 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
952 | struct radeon_ring *ring); | |
e32eb50d CK |
953 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
954 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
955 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
956 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
957 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
d6999bc7 | 958 | void radeon_ring_undo(struct radeon_ring *ring); |
e32eb50d CK |
959 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
960 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); | |
ff212f25 CK |
961 | void radeon_ring_lockup_update(struct radeon_device *rdev, |
962 | struct radeon_ring *ring); | |
069211e5 | 963 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
55d7c221 CK |
964 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
965 | uint32_t **data); | |
966 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
967 | unsigned size, uint32_t *data); | |
e32eb50d | 968 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
ea31bf69 | 969 | unsigned rptr_offs, u32 nop); |
e32eb50d | 970 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
771fe6b9 JG |
971 | |
972 | ||
4d75658b AD |
973 | /* r600 async dma */ |
974 | void r600_dma_stop(struct radeon_device *rdev); | |
975 | int r600_dma_resume(struct radeon_device *rdev); | |
976 | void r600_dma_fini(struct radeon_device *rdev); | |
977 | ||
8c5fd7ef AD |
978 | void cayman_dma_stop(struct radeon_device *rdev); |
979 | int cayman_dma_resume(struct radeon_device *rdev); | |
980 | void cayman_dma_fini(struct radeon_device *rdev); | |
981 | ||
771fe6b9 JG |
982 | /* |
983 | * CS. | |
984 | */ | |
985 | struct radeon_cs_reloc { | |
986 | struct drm_gem_object *gobj; | |
4c788679 | 987 | struct radeon_bo *robj; |
df0af440 CK |
988 | struct ttm_validate_buffer tv; |
989 | uint64_t gpu_offset; | |
990 | unsigned domain; | |
991 | unsigned alt_domain; | |
992 | uint32_t tiling_flags; | |
771fe6b9 | 993 | uint32_t handle; |
771fe6b9 JG |
994 | }; |
995 | ||
996 | struct radeon_cs_chunk { | |
997 | uint32_t chunk_id; | |
998 | uint32_t length_dw; | |
999 | uint32_t *kdata; | |
721604a1 | 1000 | void __user *user_ptr; |
771fe6b9 JG |
1001 | }; |
1002 | ||
1003 | struct radeon_cs_parser { | |
c8c15ff1 | 1004 | struct device *dev; |
771fe6b9 JG |
1005 | struct radeon_device *rdev; |
1006 | struct drm_file *filp; | |
1007 | /* chunks */ | |
1008 | unsigned nchunks; | |
1009 | struct radeon_cs_chunk *chunks; | |
1010 | uint64_t *chunks_array; | |
1011 | /* IB */ | |
1012 | unsigned idx; | |
1013 | /* relocations */ | |
1014 | unsigned nrelocs; | |
1015 | struct radeon_cs_reloc *relocs; | |
1016 | struct radeon_cs_reloc **relocs_ptr; | |
df0af440 | 1017 | struct radeon_cs_reloc *vm_bos; |
771fe6b9 | 1018 | struct list_head validated; |
cf4ccd01 | 1019 | unsigned dma_reloc_idx; |
771fe6b9 JG |
1020 | /* indices of various chunks */ |
1021 | int chunk_ib_idx; | |
1022 | int chunk_relocs_idx; | |
721604a1 | 1023 | int chunk_flags_idx; |
dfcf5f36 | 1024 | int chunk_const_ib_idx; |
f2e39221 JG |
1025 | struct radeon_ib ib; |
1026 | struct radeon_ib const_ib; | |
771fe6b9 | 1027 | void *track; |
3ce0a23d | 1028 | unsigned family; |
e70f224c | 1029 | int parser_error; |
721604a1 JG |
1030 | u32 cs_flags; |
1031 | u32 ring; | |
1032 | s32 priority; | |
ecff665f | 1033 | struct ww_acquire_ctx ticket; |
771fe6b9 JG |
1034 | }; |
1035 | ||
28a326c5 ML |
1036 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
1037 | { | |
1038 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
1039 | ||
1040 | if (ibc->kdata) | |
1041 | return ibc->kdata[idx]; | |
1042 | return p->ib.ptr[idx]; | |
1043 | } | |
1044 | ||
513bcb46 | 1045 | |
771fe6b9 JG |
1046 | struct radeon_cs_packet { |
1047 | unsigned idx; | |
1048 | unsigned type; | |
1049 | unsigned reg; | |
1050 | unsigned opcode; | |
1051 | int count; | |
1052 | unsigned one_reg_wr; | |
1053 | }; | |
1054 | ||
1055 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
1056 | struct radeon_cs_packet *pkt, | |
1057 | unsigned idx, unsigned reg); | |
1058 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
1059 | struct radeon_cs_packet *pkt); | |
1060 | ||
1061 | ||
1062 | /* | |
1063 | * AGP | |
1064 | */ | |
1065 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 1066 | void radeon_agp_resume(struct radeon_device *rdev); |
10b06122 | 1067 | void radeon_agp_suspend(struct radeon_device *rdev); |
771fe6b9 JG |
1068 | void radeon_agp_fini(struct radeon_device *rdev); |
1069 | ||
1070 | ||
1071 | /* | |
1072 | * Writeback | |
1073 | */ | |
1074 | struct radeon_wb { | |
4c788679 | 1075 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
1076 | volatile uint32_t *wb; |
1077 | uint64_t gpu_addr; | |
724c80e1 | 1078 | bool enabled; |
d0f8a854 | 1079 | bool use_event; |
771fe6b9 JG |
1080 | }; |
1081 | ||
724c80e1 | 1082 | #define RADEON_WB_SCRATCH_OFFSET 0 |
89d35807 | 1083 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
724c80e1 | 1084 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
0c88a02e AD |
1085 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
1086 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 | |
4d75658b | 1087 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
724c80e1 | 1088 | #define R600_WB_IH_WPTR_OFFSET 2048 |
f60cbd11 | 1089 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
d0f8a854 | 1090 | #define R600_WB_EVENT_OFFSET 3072 |
963e81f9 AD |
1091 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
1092 | #define CIK_WB_CP2_WPTR_OFFSET 3584 | |
724c80e1 | 1093 | |
c93bb85b JG |
1094 | /** |
1095 | * struct radeon_pm - power management datas | |
1096 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
1097 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
1098 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
1099 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
1100 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
1101 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
1102 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
1103 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
1104 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
25985edc | 1105 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
c93bb85b JG |
1106 | * @needed_bandwidth: current bandwidth needs |
1107 | * | |
1108 | * It keeps track of various data needed to take powermanagement decision. | |
25985edc | 1109 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
c93bb85b JG |
1110 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
1111 | * (type of memory, bus size, efficiency, ...) | |
1112 | */ | |
ce8f5370 AD |
1113 | |
1114 | enum radeon_pm_method { | |
1115 | PM_METHOD_PROFILE, | |
1116 | PM_METHOD_DYNPM, | |
da321c8a | 1117 | PM_METHOD_DPM, |
ce8f5370 AD |
1118 | }; |
1119 | ||
1120 | enum radeon_dynpm_state { | |
1121 | DYNPM_STATE_DISABLED, | |
1122 | DYNPM_STATE_MINIMUM, | |
1123 | DYNPM_STATE_PAUSED, | |
3f53eb6f RW |
1124 | DYNPM_STATE_ACTIVE, |
1125 | DYNPM_STATE_SUSPENDED, | |
c913e23a | 1126 | }; |
ce8f5370 AD |
1127 | enum radeon_dynpm_action { |
1128 | DYNPM_ACTION_NONE, | |
1129 | DYNPM_ACTION_MINIMUM, | |
1130 | DYNPM_ACTION_DOWNCLOCK, | |
1131 | DYNPM_ACTION_UPCLOCK, | |
1132 | DYNPM_ACTION_DEFAULT | |
c913e23a | 1133 | }; |
56278a8e AD |
1134 | |
1135 | enum radeon_voltage_type { | |
1136 | VOLTAGE_NONE = 0, | |
1137 | VOLTAGE_GPIO, | |
1138 | VOLTAGE_VDDC, | |
1139 | VOLTAGE_SW | |
1140 | }; | |
1141 | ||
0ec0e74f | 1142 | enum radeon_pm_state_type { |
da321c8a | 1143 | /* not used for dpm */ |
0ec0e74f AD |
1144 | POWER_STATE_TYPE_DEFAULT, |
1145 | POWER_STATE_TYPE_POWERSAVE, | |
da321c8a | 1146 | /* user selectable states */ |
0ec0e74f AD |
1147 | POWER_STATE_TYPE_BATTERY, |
1148 | POWER_STATE_TYPE_BALANCED, | |
1149 | POWER_STATE_TYPE_PERFORMANCE, | |
da321c8a AD |
1150 | /* internal states */ |
1151 | POWER_STATE_TYPE_INTERNAL_UVD, | |
1152 | POWER_STATE_TYPE_INTERNAL_UVD_SD, | |
1153 | POWER_STATE_TYPE_INTERNAL_UVD_HD, | |
1154 | POWER_STATE_TYPE_INTERNAL_UVD_HD2, | |
1155 | POWER_STATE_TYPE_INTERNAL_UVD_MVC, | |
1156 | POWER_STATE_TYPE_INTERNAL_BOOT, | |
1157 | POWER_STATE_TYPE_INTERNAL_THERMAL, | |
1158 | POWER_STATE_TYPE_INTERNAL_ACPI, | |
1159 | POWER_STATE_TYPE_INTERNAL_ULV, | |
edcaa5b1 | 1160 | POWER_STATE_TYPE_INTERNAL_3DPERF, |
0ec0e74f AD |
1161 | }; |
1162 | ||
ce8f5370 AD |
1163 | enum radeon_pm_profile_type { |
1164 | PM_PROFILE_DEFAULT, | |
1165 | PM_PROFILE_AUTO, | |
1166 | PM_PROFILE_LOW, | |
c9e75b21 | 1167 | PM_PROFILE_MID, |
ce8f5370 AD |
1168 | PM_PROFILE_HIGH, |
1169 | }; | |
1170 | ||
1171 | #define PM_PROFILE_DEFAULT_IDX 0 | |
1172 | #define PM_PROFILE_LOW_SH_IDX 1 | |
c9e75b21 AD |
1173 | #define PM_PROFILE_MID_SH_IDX 2 |
1174 | #define PM_PROFILE_HIGH_SH_IDX 3 | |
1175 | #define PM_PROFILE_LOW_MH_IDX 4 | |
1176 | #define PM_PROFILE_MID_MH_IDX 5 | |
1177 | #define PM_PROFILE_HIGH_MH_IDX 6 | |
1178 | #define PM_PROFILE_MAX 7 | |
ce8f5370 AD |
1179 | |
1180 | struct radeon_pm_profile { | |
1181 | int dpms_off_ps_idx; | |
1182 | int dpms_on_ps_idx; | |
1183 | int dpms_off_cm_idx; | |
1184 | int dpms_on_cm_idx; | |
516d0e46 AD |
1185 | }; |
1186 | ||
21a8122a AD |
1187 | enum radeon_int_thermal_type { |
1188 | THERMAL_TYPE_NONE, | |
da321c8a AD |
1189 | THERMAL_TYPE_EXTERNAL, |
1190 | THERMAL_TYPE_EXTERNAL_GPIO, | |
21a8122a AD |
1191 | THERMAL_TYPE_RV6XX, |
1192 | THERMAL_TYPE_RV770, | |
da321c8a | 1193 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, |
21a8122a | 1194 | THERMAL_TYPE_EVERGREEN, |
e33df25f | 1195 | THERMAL_TYPE_SUMO, |
4fddba1f | 1196 | THERMAL_TYPE_NI, |
14607d08 | 1197 | THERMAL_TYPE_SI, |
da321c8a | 1198 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, |
51150207 | 1199 | THERMAL_TYPE_CI, |
16fbe00d | 1200 | THERMAL_TYPE_KV, |
21a8122a AD |
1201 | }; |
1202 | ||
56278a8e AD |
1203 | struct radeon_voltage { |
1204 | enum radeon_voltage_type type; | |
1205 | /* gpio voltage */ | |
1206 | struct radeon_gpio_rec gpio; | |
1207 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
1208 | bool active_high; /* voltage drop is active when bit is high */ | |
1209 | /* VDDC voltage */ | |
1210 | u8 vddc_id; /* index into vddc voltage table */ | |
1211 | u8 vddci_id; /* index into vddci voltage table */ | |
1212 | bool vddci_enabled; | |
1213 | /* r6xx+ sw */ | |
2feea49a AD |
1214 | u16 voltage; |
1215 | /* evergreen+ vddci */ | |
1216 | u16 vddci; | |
56278a8e AD |
1217 | }; |
1218 | ||
d7311171 AD |
1219 | /* clock mode flags */ |
1220 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) | |
1221 | ||
56278a8e AD |
1222 | struct radeon_pm_clock_info { |
1223 | /* memory clock */ | |
1224 | u32 mclk; | |
1225 | /* engine clock */ | |
1226 | u32 sclk; | |
1227 | /* voltage info */ | |
1228 | struct radeon_voltage voltage; | |
d7311171 | 1229 | /* standardized clock flags */ |
56278a8e AD |
1230 | u32 flags; |
1231 | }; | |
1232 | ||
a48b9b4e | 1233 | /* state flags */ |
d7311171 | 1234 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
a48b9b4e | 1235 | |
56278a8e | 1236 | struct radeon_power_state { |
0ec0e74f | 1237 | enum radeon_pm_state_type type; |
8f3f1c9a | 1238 | struct radeon_pm_clock_info *clock_info; |
56278a8e AD |
1239 | /* number of valid clock modes in this power state */ |
1240 | int num_clock_modes; | |
56278a8e | 1241 | struct radeon_pm_clock_info *default_clock_mode; |
a48b9b4e AD |
1242 | /* standardized state flags */ |
1243 | u32 flags; | |
79daedc9 AD |
1244 | u32 misc; /* vbios specific flags */ |
1245 | u32 misc2; /* vbios specific flags */ | |
1246 | int pcie_lanes; /* pcie lanes */ | |
56278a8e AD |
1247 | }; |
1248 | ||
27459324 RM |
1249 | /* |
1250 | * Some modes are overclocked by very low value, accept them | |
1251 | */ | |
1252 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
1253 | ||
2e9d4c05 AD |
1254 | enum radeon_dpm_auto_throttle_src { |
1255 | RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, | |
1256 | RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL | |
1257 | }; | |
1258 | ||
1259 | enum radeon_dpm_event_src { | |
1260 | RADEON_DPM_EVENT_SRC_ANALOG = 0, | |
1261 | RADEON_DPM_EVENT_SRC_EXTERNAL = 1, | |
1262 | RADEON_DPM_EVENT_SRC_DIGITAL = 2, | |
1263 | RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, | |
1264 | RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 | |
1265 | }; | |
1266 | ||
58bd2a88 AD |
1267 | #define RADEON_MAX_VCE_LEVELS 6 |
1268 | ||
b62d628b AD |
1269 | enum radeon_vce_level { |
1270 | RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ | |
1271 | RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ | |
1272 | RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ | |
1273 | RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ | |
1274 | RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ | |
1275 | RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ | |
1276 | }; | |
1277 | ||
da321c8a AD |
1278 | struct radeon_ps { |
1279 | u32 caps; /* vbios flags */ | |
1280 | u32 class; /* vbios flags */ | |
1281 | u32 class2; /* vbios flags */ | |
1282 | /* UVD clocks */ | |
1283 | u32 vclk; | |
1284 | u32 dclk; | |
c4453e66 AD |
1285 | /* VCE clocks */ |
1286 | u32 evclk; | |
1287 | u32 ecclk; | |
b62d628b AD |
1288 | bool vce_active; |
1289 | enum radeon_vce_level vce_level; | |
da321c8a AD |
1290 | /* asic priv */ |
1291 | void *ps_priv; | |
1292 | }; | |
1293 | ||
1294 | struct radeon_dpm_thermal { | |
1295 | /* thermal interrupt work */ | |
1296 | struct work_struct work; | |
1297 | /* low temperature threshold */ | |
1298 | int min_temp; | |
1299 | /* high temperature threshold */ | |
1300 | int max_temp; | |
1301 | /* was interrupt low to high or high to low */ | |
1302 | bool high_to_low; | |
1303 | }; | |
1304 | ||
d22b7e40 AD |
1305 | enum radeon_clk_action |
1306 | { | |
1307 | RADEON_SCLK_UP = 1, | |
1308 | RADEON_SCLK_DOWN | |
1309 | }; | |
1310 | ||
1311 | struct radeon_blacklist_clocks | |
1312 | { | |
1313 | u32 sclk; | |
1314 | u32 mclk; | |
1315 | enum radeon_clk_action action; | |
1316 | }; | |
1317 | ||
61b7d601 AD |
1318 | struct radeon_clock_and_voltage_limits { |
1319 | u32 sclk; | |
1320 | u32 mclk; | |
cdf6e805 AD |
1321 | u16 vddc; |
1322 | u16 vddci; | |
61b7d601 AD |
1323 | }; |
1324 | ||
1325 | struct radeon_clock_array { | |
1326 | u32 count; | |
1327 | u32 *values; | |
1328 | }; | |
1329 | ||
1330 | struct radeon_clock_voltage_dependency_entry { | |
1331 | u32 clk; | |
1332 | u16 v; | |
1333 | }; | |
1334 | ||
1335 | struct radeon_clock_voltage_dependency_table { | |
1336 | u32 count; | |
1337 | struct radeon_clock_voltage_dependency_entry *entries; | |
1338 | }; | |
1339 | ||
ef976ec4 AD |
1340 | union radeon_cac_leakage_entry { |
1341 | struct { | |
1342 | u16 vddc; | |
1343 | u32 leakage; | |
1344 | }; | |
1345 | struct { | |
1346 | u16 vddc1; | |
1347 | u16 vddc2; | |
1348 | u16 vddc3; | |
1349 | }; | |
61b7d601 AD |
1350 | }; |
1351 | ||
1352 | struct radeon_cac_leakage_table { | |
1353 | u32 count; | |
ef976ec4 | 1354 | union radeon_cac_leakage_entry *entries; |
61b7d601 AD |
1355 | }; |
1356 | ||
929ee7a8 AD |
1357 | struct radeon_phase_shedding_limits_entry { |
1358 | u16 voltage; | |
1359 | u32 sclk; | |
1360 | u32 mclk; | |
1361 | }; | |
1362 | ||
1363 | struct radeon_phase_shedding_limits_table { | |
1364 | u32 count; | |
1365 | struct radeon_phase_shedding_limits_entry *entries; | |
1366 | }; | |
1367 | ||
84a9d9ee AD |
1368 | struct radeon_uvd_clock_voltage_dependency_entry { |
1369 | u32 vclk; | |
1370 | u32 dclk; | |
1371 | u16 v; | |
1372 | }; | |
1373 | ||
1374 | struct radeon_uvd_clock_voltage_dependency_table { | |
1375 | u8 count; | |
1376 | struct radeon_uvd_clock_voltage_dependency_entry *entries; | |
1377 | }; | |
1378 | ||
d29f013b AD |
1379 | struct radeon_vce_clock_voltage_dependency_entry { |
1380 | u32 ecclk; | |
1381 | u32 evclk; | |
1382 | u16 v; | |
1383 | }; | |
1384 | ||
1385 | struct radeon_vce_clock_voltage_dependency_table { | |
1386 | u8 count; | |
1387 | struct radeon_vce_clock_voltage_dependency_entry *entries; | |
1388 | }; | |
1389 | ||
a5cb318e AD |
1390 | struct radeon_ppm_table { |
1391 | u8 ppm_design; | |
1392 | u16 cpu_core_number; | |
1393 | u32 platform_tdp; | |
1394 | u32 small_ac_platform_tdp; | |
1395 | u32 platform_tdc; | |
1396 | u32 small_ac_platform_tdc; | |
1397 | u32 apu_tdp; | |
1398 | u32 dgpu_tdp; | |
1399 | u32 dgpu_ulv_power; | |
1400 | u32 tj_max; | |
1401 | }; | |
1402 | ||
58cb7632 AD |
1403 | struct radeon_cac_tdp_table { |
1404 | u16 tdp; | |
1405 | u16 configurable_tdp; | |
1406 | u16 tdc; | |
1407 | u16 battery_power_limit; | |
1408 | u16 small_power_limit; | |
1409 | u16 low_cac_leakage; | |
1410 | u16 high_cac_leakage; | |
1411 | u16 maximum_power_delivery_limit; | |
1412 | }; | |
1413 | ||
61b7d601 AD |
1414 | struct radeon_dpm_dynamic_state { |
1415 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; | |
1416 | struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; | |
1417 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; | |
dd621a22 | 1418 | struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; |
4489cd62 | 1419 | struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; |
84a9d9ee | 1420 | struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; |
d29f013b | 1421 | struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; |
94a914f5 AD |
1422 | struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; |
1423 | struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; | |
61b7d601 AD |
1424 | struct radeon_clock_array valid_sclk_values; |
1425 | struct radeon_clock_array valid_mclk_values; | |
1426 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; | |
1427 | struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; | |
1428 | u32 mclk_sclk_ratio; | |
1429 | u32 sclk_mclk_delta; | |
1430 | u16 vddc_vddci_delta; | |
1431 | u16 min_vddc_for_pcie_gen2; | |
1432 | struct radeon_cac_leakage_table cac_leakage_table; | |
929ee7a8 | 1433 | struct radeon_phase_shedding_limits_table phase_shedding_limits_table; |
a5cb318e | 1434 | struct radeon_ppm_table *ppm_table; |
58cb7632 | 1435 | struct radeon_cac_tdp_table *cac_tdp_table; |
61b7d601 AD |
1436 | }; |
1437 | ||
1438 | struct radeon_dpm_fan { | |
1439 | u16 t_min; | |
1440 | u16 t_med; | |
1441 | u16 t_high; | |
1442 | u16 pwm_min; | |
1443 | u16 pwm_med; | |
1444 | u16 pwm_high; | |
1445 | u8 t_hyst; | |
1446 | u32 cycle_delay; | |
1447 | u16 t_max; | |
1448 | bool ucode_fan_control; | |
1449 | }; | |
1450 | ||
32ce4652 AD |
1451 | enum radeon_pcie_gen { |
1452 | RADEON_PCIE_GEN1 = 0, | |
1453 | RADEON_PCIE_GEN2 = 1, | |
1454 | RADEON_PCIE_GEN3 = 2, | |
1455 | RADEON_PCIE_GEN_INVALID = 0xffff | |
1456 | }; | |
1457 | ||
70d01a5e AD |
1458 | enum radeon_dpm_forced_level { |
1459 | RADEON_DPM_FORCED_LEVEL_AUTO = 0, | |
1460 | RADEON_DPM_FORCED_LEVEL_LOW = 1, | |
1461 | RADEON_DPM_FORCED_LEVEL_HIGH = 2, | |
1462 | }; | |
1463 | ||
58bd2a88 AD |
1464 | struct radeon_vce_state { |
1465 | /* vce clocks */ | |
1466 | u32 evclk; | |
1467 | u32 ecclk; | |
1468 | /* gpu clocks */ | |
1469 | u32 sclk; | |
1470 | u32 mclk; | |
1471 | u8 clk_idx; | |
1472 | u8 pstate; | |
1473 | }; | |
1474 | ||
da321c8a AD |
1475 | struct radeon_dpm { |
1476 | struct radeon_ps *ps; | |
1477 | /* number of valid power states */ | |
1478 | int num_ps; | |
1479 | /* current power state that is active */ | |
1480 | struct radeon_ps *current_ps; | |
1481 | /* requested power state */ | |
1482 | struct radeon_ps *requested_ps; | |
1483 | /* boot up power state */ | |
1484 | struct radeon_ps *boot_ps; | |
1485 | /* default uvd power state */ | |
1486 | struct radeon_ps *uvd_ps; | |
58bd2a88 AD |
1487 | /* vce requirements */ |
1488 | struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; | |
1489 | enum radeon_vce_level vce_level; | |
da321c8a AD |
1490 | enum radeon_pm_state_type state; |
1491 | enum radeon_pm_state_type user_state; | |
1492 | u32 platform_caps; | |
1493 | u32 voltage_response_time; | |
1494 | u32 backbias_response_time; | |
1495 | void *priv; | |
1496 | u32 new_active_crtcs; | |
1497 | int new_active_crtc_count; | |
1498 | u32 current_active_crtcs; | |
1499 | int current_active_crtc_count; | |
61b7d601 AD |
1500 | struct radeon_dpm_dynamic_state dyn_state; |
1501 | struct radeon_dpm_fan fan; | |
1502 | u32 tdp_limit; | |
1503 | u32 near_tdp_limit; | |
a9e61410 | 1504 | u32 near_tdp_limit_adjusted; |
61b7d601 AD |
1505 | u32 sq_ramping_threshold; |
1506 | u32 cac_leakage; | |
1507 | u16 tdp_od_limit; | |
1508 | u32 tdp_adjustment; | |
1509 | u16 load_line_slope; | |
1510 | bool power_control; | |
5ca302f7 | 1511 | bool ac_power; |
da321c8a AD |
1512 | /* special states active */ |
1513 | bool thermal_active; | |
8a227555 | 1514 | bool uvd_active; |
b62d628b | 1515 | bool vce_active; |
da321c8a AD |
1516 | /* thermal handling */ |
1517 | struct radeon_dpm_thermal thermal; | |
70d01a5e AD |
1518 | /* forced levels */ |
1519 | enum radeon_dpm_forced_level forced_level; | |
ce3537d5 AD |
1520 | /* track UVD streams */ |
1521 | unsigned sd; | |
1522 | unsigned hd; | |
da321c8a AD |
1523 | }; |
1524 | ||
ce3537d5 | 1525 | void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); |
03afe6f6 | 1526 | void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); |
da321c8a | 1527 | |
c93bb85b | 1528 | struct radeon_pm { |
c913e23a | 1529 | struct mutex mutex; |
db7fce39 CK |
1530 | /* write locked while reprogramming mclk */ |
1531 | struct rw_semaphore mclk_lock; | |
a48b9b4e AD |
1532 | u32 active_crtcs; |
1533 | int active_crtc_count; | |
c913e23a | 1534 | int req_vblank; |
839461d3 | 1535 | bool vblank_sync; |
c93bb85b JG |
1536 | fixed20_12 max_bandwidth; |
1537 | fixed20_12 igp_sideport_mclk; | |
1538 | fixed20_12 igp_system_mclk; | |
1539 | fixed20_12 igp_ht_link_clk; | |
1540 | fixed20_12 igp_ht_link_width; | |
1541 | fixed20_12 k8_bandwidth; | |
1542 | fixed20_12 sideport_bandwidth; | |
1543 | fixed20_12 ht_bandwidth; | |
1544 | fixed20_12 core_bandwidth; | |
1545 | fixed20_12 sclk; | |
f47299c5 | 1546 | fixed20_12 mclk; |
c93bb85b | 1547 | fixed20_12 needed_bandwidth; |
0975b162 | 1548 | struct radeon_power_state *power_state; |
56278a8e AD |
1549 | /* number of valid power states */ |
1550 | int num_power_states; | |
a48b9b4e AD |
1551 | int current_power_state_index; |
1552 | int current_clock_mode_index; | |
1553 | int requested_power_state_index; | |
1554 | int requested_clock_mode_index; | |
1555 | int default_power_state_index; | |
1556 | u32 current_sclk; | |
1557 | u32 current_mclk; | |
2feea49a AD |
1558 | u16 current_vddc; |
1559 | u16 current_vddci; | |
9ace9f7b AD |
1560 | u32 default_sclk; |
1561 | u32 default_mclk; | |
2feea49a AD |
1562 | u16 default_vddc; |
1563 | u16 default_vddci; | |
29fb52ca | 1564 | struct radeon_i2c_chan *i2c_bus; |
ce8f5370 AD |
1565 | /* selected pm method */ |
1566 | enum radeon_pm_method pm_method; | |
1567 | /* dynpm power management */ | |
1568 | struct delayed_work dynpm_idle_work; | |
1569 | enum radeon_dynpm_state dynpm_state; | |
1570 | enum radeon_dynpm_action dynpm_planned_action; | |
1571 | unsigned long dynpm_action_timeout; | |
1572 | bool dynpm_can_upclock; | |
1573 | bool dynpm_can_downclock; | |
1574 | /* profile-based power management */ | |
1575 | enum radeon_pm_profile_type profile; | |
1576 | int profile_index; | |
1577 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; | |
21a8122a AD |
1578 | /* internal thermal controller on rv6xx+ */ |
1579 | enum radeon_int_thermal_type int_thermal_type; | |
1580 | struct device *int_hwmon_dev; | |
da321c8a AD |
1581 | /* dpm */ |
1582 | bool dpm_enabled; | |
1583 | struct radeon_dpm dpm; | |
c93bb85b JG |
1584 | }; |
1585 | ||
a4c9e2ee AD |
1586 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1587 | enum radeon_pm_state_type ps_type, | |
1588 | int instance); | |
f2ba57b5 CK |
1589 | /* |
1590 | * UVD | |
1591 | */ | |
1592 | #define RADEON_MAX_UVD_HANDLES 10 | |
1593 | #define RADEON_UVD_STACK_SIZE (1024*1024) | |
1594 | #define RADEON_UVD_HEAP_SIZE (1024*1024) | |
1595 | ||
1596 | struct radeon_uvd { | |
1597 | struct radeon_bo *vcpu_bo; | |
1598 | void *cpu_addr; | |
1599 | uint64_t gpu_addr; | |
9cc2e0e9 | 1600 | void *saved_bo; |
f2ba57b5 CK |
1601 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; |
1602 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; | |
85a129ca | 1603 | unsigned img_size[RADEON_MAX_UVD_HANDLES]; |
55b51c88 | 1604 | struct delayed_work idle_work; |
f2ba57b5 CK |
1605 | }; |
1606 | ||
1607 | int radeon_uvd_init(struct radeon_device *rdev); | |
1608 | void radeon_uvd_fini(struct radeon_device *rdev); | |
1609 | int radeon_uvd_suspend(struct radeon_device *rdev); | |
1610 | int radeon_uvd_resume(struct radeon_device *rdev); | |
1611 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, | |
1612 | uint32_t handle, struct radeon_fence **fence); | |
1613 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, | |
1614 | uint32_t handle, struct radeon_fence **fence); | |
1615 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); | |
1616 | void radeon_uvd_free_handles(struct radeon_device *rdev, | |
1617 | struct drm_file *filp); | |
1618 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); | |
55b51c88 | 1619 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
facd112d CK |
1620 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
1621 | unsigned vclk, unsigned dclk, | |
1622 | unsigned vco_min, unsigned vco_max, | |
1623 | unsigned fb_factor, unsigned fb_mask, | |
1624 | unsigned pd_min, unsigned pd_max, | |
1625 | unsigned pd_even, | |
1626 | unsigned *optimal_fb_div, | |
1627 | unsigned *optimal_vclk_div, | |
1628 | unsigned *optimal_dclk_div); | |
1629 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, | |
1630 | unsigned cg_upll_func_cntl); | |
771fe6b9 | 1631 | |
d93f7937 CK |
1632 | /* |
1633 | * VCE | |
1634 | */ | |
1635 | #define RADEON_MAX_VCE_HANDLES 16 | |
1636 | #define RADEON_VCE_STACK_SIZE (1024*1024) | |
1637 | #define RADEON_VCE_HEAP_SIZE (4*1024*1024) | |
1638 | ||
1639 | struct radeon_vce { | |
1640 | struct radeon_bo *vcpu_bo; | |
d93f7937 | 1641 | uint64_t gpu_addr; |
98ccc291 CK |
1642 | unsigned fw_version; |
1643 | unsigned fb_version; | |
d93f7937 CK |
1644 | atomic_t handles[RADEON_MAX_VCE_HANDLES]; |
1645 | struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; | |
03afe6f6 | 1646 | struct delayed_work idle_work; |
d93f7937 CK |
1647 | }; |
1648 | ||
1649 | int radeon_vce_init(struct radeon_device *rdev); | |
1650 | void radeon_vce_fini(struct radeon_device *rdev); | |
1651 | int radeon_vce_suspend(struct radeon_device *rdev); | |
1652 | int radeon_vce_resume(struct radeon_device *rdev); | |
1653 | int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, | |
1654 | uint32_t handle, struct radeon_fence **fence); | |
1655 | int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, | |
1656 | uint32_t handle, struct radeon_fence **fence); | |
1657 | void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); | |
03afe6f6 | 1658 | void radeon_vce_note_usage(struct radeon_device *rdev); |
d93f7937 CK |
1659 | int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi); |
1660 | int radeon_vce_cs_parse(struct radeon_cs_parser *p); | |
1661 | bool radeon_vce_semaphore_emit(struct radeon_device *rdev, | |
1662 | struct radeon_ring *ring, | |
1663 | struct radeon_semaphore *semaphore, | |
1664 | bool emit_wait); | |
1665 | void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | |
1666 | void radeon_vce_fence_emit(struct radeon_device *rdev, | |
1667 | struct radeon_fence *fence); | |
1668 | int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
1669 | int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); | |
1670 | ||
b530602f | 1671 | struct r600_audio_pin { |
a92553ab RM |
1672 | int channels; |
1673 | int rate; | |
1674 | int bits_per_sample; | |
1675 | u8 status_bits; | |
1676 | u8 category_code; | |
b530602f AD |
1677 | u32 offset; |
1678 | bool connected; | |
1679 | u32 id; | |
1680 | }; | |
1681 | ||
1682 | struct r600_audio { | |
1683 | bool enabled; | |
1684 | struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; | |
1685 | int num_pins; | |
a92553ab RM |
1686 | }; |
1687 | ||
771fe6b9 JG |
1688 | /* |
1689 | * Benchmarking | |
1690 | */ | |
638dd7db | 1691 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
771fe6b9 JG |
1692 | |
1693 | ||
ecc0b326 MD |
1694 | /* |
1695 | * Testing | |
1696 | */ | |
1697 | void radeon_test_moves(struct radeon_device *rdev); | |
60a7e396 | 1698 | void radeon_test_ring_sync(struct radeon_device *rdev, |
e32eb50d CK |
1699 | struct radeon_ring *cpA, |
1700 | struct radeon_ring *cpB); | |
60a7e396 | 1701 | void radeon_test_syncing(struct radeon_device *rdev); |
ecc0b326 MD |
1702 | |
1703 | ||
771fe6b9 JG |
1704 | /* |
1705 | * Debugfs | |
1706 | */ | |
4d8bf9ae CK |
1707 | struct radeon_debugfs { |
1708 | struct drm_info_list *files; | |
1709 | unsigned num_files; | |
1710 | }; | |
1711 | ||
771fe6b9 JG |
1712 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1713 | struct drm_info_list *files, | |
1714 | unsigned nfiles); | |
1715 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 | 1716 | |
76a0df85 CK |
1717 | /* |
1718 | * ASIC ring specific functions. | |
1719 | */ | |
1720 | struct radeon_asic_ring { | |
1721 | /* ring read/write ptr handling */ | |
1722 | u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); | |
1723 | u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); | |
1724 | void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); | |
1725 | ||
1726 | /* validating and patching of IBs */ | |
1727 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); | |
1728 | int (*cs_parse)(struct radeon_cs_parser *p); | |
1729 | ||
1730 | /* command emmit functions */ | |
1731 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
1732 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); | |
1654b817 | 1733 | bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
76a0df85 CK |
1734 | struct radeon_semaphore *semaphore, bool emit_wait); |
1735 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); | |
1736 | ||
1737 | /* testing functions */ | |
1738 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1739 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1740 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1741 | ||
1742 | /* deprecated */ | |
1743 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1744 | }; | |
771fe6b9 JG |
1745 | |
1746 | /* | |
1747 | * ASIC specific functions. | |
1748 | */ | |
1749 | struct radeon_asic { | |
068a117c | 1750 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
1751 | void (*fini)(struct radeon_device *rdev); |
1752 | int (*resume)(struct radeon_device *rdev); | |
1753 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 1754 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
a2d07b74 | 1755 | int (*asic_reset)(struct radeon_device *rdev); |
54e88e06 AD |
1756 | /* ioctl hw specific callback. Some hw might want to perform special |
1757 | * operation on specific ioctl. For instance on wait idle some hw | |
1758 | * might want to perform and HDP flush through MMIO as it seems that | |
1759 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
1760 | * through ring. | |
1761 | */ | |
1762 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
1763 | /* check if 3D engine is idle */ | |
1764 | bool (*gui_idle)(struct radeon_device *rdev); | |
1765 | /* wait for mc_idle */ | |
1766 | int (*mc_wait_for_idle)(struct radeon_device *rdev); | |
454d2e2a AD |
1767 | /* get the reference clock */ |
1768 | u32 (*get_xclk)(struct radeon_device *rdev); | |
d0418894 AD |
1769 | /* get the gpu clock counter */ |
1770 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); | |
54e88e06 | 1771 | /* gart */ |
c5b3b850 AD |
1772 | struct { |
1773 | void (*tlb_flush)(struct radeon_device *rdev); | |
1774 | int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
1775 | } gart; | |
05b07147 CK |
1776 | struct { |
1777 | int (*init)(struct radeon_device *rdev); | |
1778 | void (*fini)(struct radeon_device *rdev); | |
43f1214a AD |
1779 | void (*set_page)(struct radeon_device *rdev, |
1780 | struct radeon_ib *ib, | |
1781 | uint64_t pe, | |
dce34bfd CK |
1782 | uint64_t addr, unsigned count, |
1783 | uint32_t incr, uint32_t flags); | |
05b07147 | 1784 | } vm; |
54e88e06 | 1785 | /* ring specific callbacks */ |
76a0df85 | 1786 | struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; |
54e88e06 | 1787 | /* irqs */ |
b35ea4ab AD |
1788 | struct { |
1789 | int (*set)(struct radeon_device *rdev); | |
1790 | int (*process)(struct radeon_device *rdev); | |
1791 | } irq; | |
54e88e06 | 1792 | /* displays */ |
c79a49ca AD |
1793 | struct { |
1794 | /* display watermarks */ | |
1795 | void (*bandwidth_update)(struct radeon_device *rdev); | |
1796 | /* get frame count */ | |
1797 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); | |
1798 | /* wait for vblank */ | |
1799 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); | |
37e9b6a6 AD |
1800 | /* set backlight level */ |
1801 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); | |
6d92f81d AD |
1802 | /* get backlight level */ |
1803 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); | |
a973bea1 AD |
1804 | /* audio callbacks */ |
1805 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); | |
1806 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
c79a49ca | 1807 | } display; |
54e88e06 | 1808 | /* copy functions for bo handling */ |
27cd7769 AD |
1809 | struct { |
1810 | int (*blit)(struct radeon_device *rdev, | |
1811 | uint64_t src_offset, | |
1812 | uint64_t dst_offset, | |
1813 | unsigned num_gpu_pages, | |
876dc9f3 | 1814 | struct radeon_fence **fence); |
27cd7769 AD |
1815 | u32 blit_ring_index; |
1816 | int (*dma)(struct radeon_device *rdev, | |
1817 | uint64_t src_offset, | |
1818 | uint64_t dst_offset, | |
1819 | unsigned num_gpu_pages, | |
876dc9f3 | 1820 | struct radeon_fence **fence); |
27cd7769 AD |
1821 | u32 dma_ring_index; |
1822 | /* method used for bo copy */ | |
1823 | int (*copy)(struct radeon_device *rdev, | |
1824 | uint64_t src_offset, | |
1825 | uint64_t dst_offset, | |
1826 | unsigned num_gpu_pages, | |
876dc9f3 | 1827 | struct radeon_fence **fence); |
27cd7769 AD |
1828 | /* ring used for bo copies */ |
1829 | u32 copy_ring_index; | |
1830 | } copy; | |
54e88e06 | 1831 | /* surfaces */ |
9e6f3d02 AD |
1832 | struct { |
1833 | int (*set_reg)(struct radeon_device *rdev, int reg, | |
1834 | uint32_t tiling_flags, uint32_t pitch, | |
1835 | uint32_t offset, uint32_t obj_size); | |
1836 | void (*clear_reg)(struct radeon_device *rdev, int reg); | |
1837 | } surface; | |
54e88e06 | 1838 | /* hotplug detect */ |
901ea57d AD |
1839 | struct { |
1840 | void (*init)(struct radeon_device *rdev); | |
1841 | void (*fini)(struct radeon_device *rdev); | |
1842 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1843 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1844 | } hpd; | |
da321c8a | 1845 | /* static power management */ |
a02fa397 AD |
1846 | struct { |
1847 | void (*misc)(struct radeon_device *rdev); | |
1848 | void (*prepare)(struct radeon_device *rdev); | |
1849 | void (*finish)(struct radeon_device *rdev); | |
1850 | void (*init_profile)(struct radeon_device *rdev); | |
1851 | void (*get_dynpm_state)(struct radeon_device *rdev); | |
798bcf73 AD |
1852 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1853 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); | |
1854 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); | |
1855 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); | |
1856 | int (*get_pcie_lanes)(struct radeon_device *rdev); | |
1857 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); | |
1858 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
73afc70d | 1859 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
b59b7333 | 1860 | int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); |
6bd1c385 | 1861 | int (*get_temperature)(struct radeon_device *rdev); |
a02fa397 | 1862 | } pm; |
da321c8a AD |
1863 | /* dynamic power management */ |
1864 | struct { | |
1865 | int (*init)(struct radeon_device *rdev); | |
1866 | void (*setup_asic)(struct radeon_device *rdev); | |
1867 | int (*enable)(struct radeon_device *rdev); | |
914a8987 | 1868 | int (*late_enable)(struct radeon_device *rdev); |
da321c8a | 1869 | void (*disable)(struct radeon_device *rdev); |
84dd1928 | 1870 | int (*pre_set_power_state)(struct radeon_device *rdev); |
da321c8a | 1871 | int (*set_power_state)(struct radeon_device *rdev); |
84dd1928 | 1872 | void (*post_set_power_state)(struct radeon_device *rdev); |
da321c8a AD |
1873 | void (*display_configuration_changed)(struct radeon_device *rdev); |
1874 | void (*fini)(struct radeon_device *rdev); | |
1875 | u32 (*get_sclk)(struct radeon_device *rdev, bool low); | |
1876 | u32 (*get_mclk)(struct radeon_device *rdev, bool low); | |
1877 | void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); | |
1316b792 | 1878 | void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); |
70d01a5e | 1879 | int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); |
48783069 | 1880 | bool (*vblank_too_short)(struct radeon_device *rdev); |
9e9d9762 | 1881 | void (*powergate_uvd)(struct radeon_device *rdev, bool gate); |
1c71bda0 | 1882 | void (*enable_bapm)(struct radeon_device *rdev, bool enable); |
da321c8a | 1883 | } dpm; |
6f34be50 | 1884 | /* pageflipping */ |
0f9e006c | 1885 | struct { |
157fa14d CK |
1886 | void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
1887 | bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); | |
0f9e006c | 1888 | } pflip; |
771fe6b9 JG |
1889 | }; |
1890 | ||
21f9a437 JG |
1891 | /* |
1892 | * Asic structures | |
1893 | */ | |
551ebd83 | 1894 | struct r100_asic { |
225758d8 JG |
1895 | const unsigned *reg_safe_bm; |
1896 | unsigned reg_safe_bm_size; | |
1897 | u32 hdp_cntl; | |
551ebd83 DA |
1898 | }; |
1899 | ||
21f9a437 | 1900 | struct r300_asic { |
225758d8 JG |
1901 | const unsigned *reg_safe_bm; |
1902 | unsigned reg_safe_bm_size; | |
1903 | u32 resync_scratch; | |
1904 | u32 hdp_cntl; | |
21f9a437 JG |
1905 | }; |
1906 | ||
1907 | struct r600_asic { | |
225758d8 JG |
1908 | unsigned max_pipes; |
1909 | unsigned max_tile_pipes; | |
1910 | unsigned max_simds; | |
1911 | unsigned max_backends; | |
1912 | unsigned max_gprs; | |
1913 | unsigned max_threads; | |
1914 | unsigned max_stack_entries; | |
1915 | unsigned max_hw_contexts; | |
1916 | unsigned max_gs_threads; | |
1917 | unsigned sx_max_export_size; | |
1918 | unsigned sx_max_export_pos_size; | |
1919 | unsigned sx_max_export_smx_size; | |
1920 | unsigned sq_num_cf_insts; | |
1921 | unsigned tiling_nbanks; | |
1922 | unsigned tiling_npipes; | |
1923 | unsigned tiling_group_size; | |
e7aeeba6 | 1924 | unsigned tile_config; |
e55b9422 | 1925 | unsigned backend_map; |
21f9a437 JG |
1926 | }; |
1927 | ||
1928 | struct rv770_asic { | |
225758d8 JG |
1929 | unsigned max_pipes; |
1930 | unsigned max_tile_pipes; | |
1931 | unsigned max_simds; | |
1932 | unsigned max_backends; | |
1933 | unsigned max_gprs; | |
1934 | unsigned max_threads; | |
1935 | unsigned max_stack_entries; | |
1936 | unsigned max_hw_contexts; | |
1937 | unsigned max_gs_threads; | |
1938 | unsigned sx_max_export_size; | |
1939 | unsigned sx_max_export_pos_size; | |
1940 | unsigned sx_max_export_smx_size; | |
1941 | unsigned sq_num_cf_insts; | |
1942 | unsigned sx_num_of_sets; | |
1943 | unsigned sc_prim_fifo_size; | |
1944 | unsigned sc_hiz_tile_fifo_size; | |
1945 | unsigned sc_earlyz_tile_fifo_fize; | |
1946 | unsigned tiling_nbanks; | |
1947 | unsigned tiling_npipes; | |
1948 | unsigned tiling_group_size; | |
e7aeeba6 | 1949 | unsigned tile_config; |
e55b9422 | 1950 | unsigned backend_map; |
21f9a437 JG |
1951 | }; |
1952 | ||
32fcdbf4 AD |
1953 | struct evergreen_asic { |
1954 | unsigned num_ses; | |
1955 | unsigned max_pipes; | |
1956 | unsigned max_tile_pipes; | |
1957 | unsigned max_simds; | |
1958 | unsigned max_backends; | |
1959 | unsigned max_gprs; | |
1960 | unsigned max_threads; | |
1961 | unsigned max_stack_entries; | |
1962 | unsigned max_hw_contexts; | |
1963 | unsigned max_gs_threads; | |
1964 | unsigned sx_max_export_size; | |
1965 | unsigned sx_max_export_pos_size; | |
1966 | unsigned sx_max_export_smx_size; | |
1967 | unsigned sq_num_cf_insts; | |
1968 | unsigned sx_num_of_sets; | |
1969 | unsigned sc_prim_fifo_size; | |
1970 | unsigned sc_hiz_tile_fifo_size; | |
1971 | unsigned sc_earlyz_tile_fifo_size; | |
1972 | unsigned tiling_nbanks; | |
1973 | unsigned tiling_npipes; | |
1974 | unsigned tiling_group_size; | |
e7aeeba6 | 1975 | unsigned tile_config; |
e55b9422 | 1976 | unsigned backend_map; |
32fcdbf4 AD |
1977 | }; |
1978 | ||
fecf1d07 AD |
1979 | struct cayman_asic { |
1980 | unsigned max_shader_engines; | |
1981 | unsigned max_pipes_per_simd; | |
1982 | unsigned max_tile_pipes; | |
1983 | unsigned max_simds_per_se; | |
1984 | unsigned max_backends_per_se; | |
1985 | unsigned max_texture_channel_caches; | |
1986 | unsigned max_gprs; | |
1987 | unsigned max_threads; | |
1988 | unsigned max_gs_threads; | |
1989 | unsigned max_stack_entries; | |
1990 | unsigned sx_num_of_sets; | |
1991 | unsigned sx_max_export_size; | |
1992 | unsigned sx_max_export_pos_size; | |
1993 | unsigned sx_max_export_smx_size; | |
1994 | unsigned max_hw_contexts; | |
1995 | unsigned sq_num_cf_insts; | |
1996 | unsigned sc_prim_fifo_size; | |
1997 | unsigned sc_hiz_tile_fifo_size; | |
1998 | unsigned sc_earlyz_tile_fifo_size; | |
1999 | ||
2000 | unsigned num_shader_engines; | |
2001 | unsigned num_shader_pipes_per_simd; | |
2002 | unsigned num_tile_pipes; | |
2003 | unsigned num_simds_per_se; | |
2004 | unsigned num_backends_per_se; | |
2005 | unsigned backend_disable_mask_per_asic; | |
2006 | unsigned backend_map; | |
2007 | unsigned num_texture_channel_caches; | |
2008 | unsigned mem_max_burst_length_bytes; | |
2009 | unsigned mem_row_size_in_kb; | |
2010 | unsigned shader_engine_tile_size; | |
2011 | unsigned num_gpus; | |
2012 | unsigned multi_gpu_tile_size; | |
2013 | ||
2014 | unsigned tile_config; | |
fecf1d07 AD |
2015 | }; |
2016 | ||
0a96d72b AD |
2017 | struct si_asic { |
2018 | unsigned max_shader_engines; | |
0a96d72b | 2019 | unsigned max_tile_pipes; |
1a8ca750 AD |
2020 | unsigned max_cu_per_sh; |
2021 | unsigned max_sh_per_se; | |
0a96d72b AD |
2022 | unsigned max_backends_per_se; |
2023 | unsigned max_texture_channel_caches; | |
2024 | unsigned max_gprs; | |
2025 | unsigned max_gs_threads; | |
2026 | unsigned max_hw_contexts; | |
2027 | unsigned sc_prim_fifo_size_frontend; | |
2028 | unsigned sc_prim_fifo_size_backend; | |
2029 | unsigned sc_hiz_tile_fifo_size; | |
2030 | unsigned sc_earlyz_tile_fifo_size; | |
2031 | ||
0a96d72b | 2032 | unsigned num_tile_pipes; |
439a1cff | 2033 | unsigned backend_enable_mask; |
0a96d72b AD |
2034 | unsigned backend_disable_mask_per_asic; |
2035 | unsigned backend_map; | |
2036 | unsigned num_texture_channel_caches; | |
2037 | unsigned mem_max_burst_length_bytes; | |
2038 | unsigned mem_row_size_in_kb; | |
2039 | unsigned shader_engine_tile_size; | |
2040 | unsigned num_gpus; | |
2041 | unsigned multi_gpu_tile_size; | |
2042 | ||
2043 | unsigned tile_config; | |
64d7b8be | 2044 | uint32_t tile_mode_array[32]; |
0a96d72b AD |
2045 | }; |
2046 | ||
8cc1a532 AD |
2047 | struct cik_asic { |
2048 | unsigned max_shader_engines; | |
2049 | unsigned max_tile_pipes; | |
2050 | unsigned max_cu_per_sh; | |
2051 | unsigned max_sh_per_se; | |
2052 | unsigned max_backends_per_se; | |
2053 | unsigned max_texture_channel_caches; | |
2054 | unsigned max_gprs; | |
2055 | unsigned max_gs_threads; | |
2056 | unsigned max_hw_contexts; | |
2057 | unsigned sc_prim_fifo_size_frontend; | |
2058 | unsigned sc_prim_fifo_size_backend; | |
2059 | unsigned sc_hiz_tile_fifo_size; | |
2060 | unsigned sc_earlyz_tile_fifo_size; | |
2061 | ||
2062 | unsigned num_tile_pipes; | |
439a1cff | 2063 | unsigned backend_enable_mask; |
8cc1a532 AD |
2064 | unsigned backend_disable_mask_per_asic; |
2065 | unsigned backend_map; | |
2066 | unsigned num_texture_channel_caches; | |
2067 | unsigned mem_max_burst_length_bytes; | |
2068 | unsigned mem_row_size_in_kb; | |
2069 | unsigned shader_engine_tile_size; | |
2070 | unsigned num_gpus; | |
2071 | unsigned multi_gpu_tile_size; | |
2072 | ||
2073 | unsigned tile_config; | |
39aee490 | 2074 | uint32_t tile_mode_array[32]; |
32f79a8a | 2075 | uint32_t macrotile_mode_array[16]; |
8cc1a532 AD |
2076 | }; |
2077 | ||
068a117c JG |
2078 | union radeon_asic_config { |
2079 | struct r300_asic r300; | |
551ebd83 | 2080 | struct r100_asic r100; |
3ce0a23d JG |
2081 | struct r600_asic r600; |
2082 | struct rv770_asic rv770; | |
32fcdbf4 | 2083 | struct evergreen_asic evergreen; |
fecf1d07 | 2084 | struct cayman_asic cayman; |
0a96d72b | 2085 | struct si_asic si; |
8cc1a532 | 2086 | struct cik_asic cik; |
068a117c JG |
2087 | }; |
2088 | ||
0a10c851 DV |
2089 | /* |
2090 | * asic initizalization from radeon_asic.c | |
2091 | */ | |
2092 | void radeon_agp_disable(struct radeon_device *rdev); | |
2093 | int radeon_asic_init(struct radeon_device *rdev); | |
2094 | ||
771fe6b9 JG |
2095 | |
2096 | /* | |
2097 | * IOCTL. | |
2098 | */ | |
2099 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
2100 | struct drm_file *filp); | |
2101 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
2102 | struct drm_file *filp); | |
2103 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
2104 | struct drm_file *file_priv); | |
2105 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
2106 | struct drm_file *file_priv); | |
2107 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2108 | struct drm_file *file_priv); | |
2109 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2110 | struct drm_file *file_priv); | |
2111 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
2112 | struct drm_file *filp); | |
2113 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2114 | struct drm_file *filp); | |
2115 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
2116 | struct drm_file *filp); | |
2117 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
2118 | struct drm_file *filp); | |
721604a1 JG |
2119 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
2120 | struct drm_file *filp); | |
bda72d58 MO |
2121 | int radeon_gem_op_ioctl(struct drm_device *dev, void *data, |
2122 | struct drm_file *filp); | |
771fe6b9 | 2123 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
e024e110 DA |
2124 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
2125 | struct drm_file *filp); | |
2126 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
2127 | struct drm_file *filp); | |
771fe6b9 | 2128 | |
16cdf04d AD |
2129 | /* VRAM scratch page for HDP bug, default vram page */ |
2130 | struct r600_vram_scratch { | |
87cbf8f2 AD |
2131 | struct radeon_bo *robj; |
2132 | volatile uint32_t *ptr; | |
16cdf04d | 2133 | u64 gpu_addr; |
87cbf8f2 | 2134 | }; |
771fe6b9 | 2135 | |
fd64ca8a LT |
2136 | /* |
2137 | * ACPI | |
2138 | */ | |
2139 | struct radeon_atif_notification_cfg { | |
2140 | bool enabled; | |
2141 | int command_code; | |
2142 | }; | |
2143 | ||
2144 | struct radeon_atif_notifications { | |
2145 | bool display_switch; | |
2146 | bool expansion_mode_change; | |
2147 | bool thermal_state; | |
2148 | bool forced_power_state; | |
2149 | bool system_power_state; | |
2150 | bool display_conf_change; | |
2151 | bool px_gfx_switch; | |
2152 | bool brightness_change; | |
2153 | bool dgpu_display_event; | |
2154 | }; | |
2155 | ||
2156 | struct radeon_atif_functions { | |
2157 | bool system_params; | |
2158 | bool sbios_requests; | |
2159 | bool select_active_disp; | |
2160 | bool lid_state; | |
2161 | bool get_tv_standard; | |
2162 | bool set_tv_standard; | |
2163 | bool get_panel_expansion_mode; | |
2164 | bool set_panel_expansion_mode; | |
2165 | bool temperature_change; | |
2166 | bool graphics_device_types; | |
2167 | }; | |
2168 | ||
2169 | struct radeon_atif { | |
2170 | struct radeon_atif_notifications notifications; | |
2171 | struct radeon_atif_functions functions; | |
2172 | struct radeon_atif_notification_cfg notification_cfg; | |
37e9b6a6 | 2173 | struct radeon_encoder *encoder_for_bl; |
fd64ca8a | 2174 | }; |
7a1619b9 | 2175 | |
e3a15920 AD |
2176 | struct radeon_atcs_functions { |
2177 | bool get_ext_state; | |
2178 | bool pcie_perf_req; | |
2179 | bool pcie_dev_rdy; | |
2180 | bool pcie_bus_width; | |
2181 | }; | |
2182 | ||
2183 | struct radeon_atcs { | |
2184 | struct radeon_atcs_functions functions; | |
2185 | }; | |
2186 | ||
771fe6b9 JG |
2187 | /* |
2188 | * Core structure, functions and helpers. | |
2189 | */ | |
2190 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
2191 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
2192 | ||
2193 | struct radeon_device { | |
9f022ddf | 2194 | struct device *dev; |
771fe6b9 JG |
2195 | struct drm_device *ddev; |
2196 | struct pci_dev *pdev; | |
dee53e7f | 2197 | struct rw_semaphore exclusive_lock; |
771fe6b9 | 2198 | /* ASIC */ |
068a117c | 2199 | union radeon_asic_config config; |
771fe6b9 JG |
2200 | enum radeon_family family; |
2201 | unsigned long flags; | |
2202 | int usec_timeout; | |
2203 | enum radeon_pll_errata pll_errata; | |
2204 | int num_gb_pipes; | |
f779b3e5 | 2205 | int num_z_pipes; |
771fe6b9 JG |
2206 | int disp_priority; |
2207 | /* BIOS */ | |
2208 | uint8_t *bios; | |
2209 | bool is_atom_bios; | |
2210 | uint16_t bios_header_start; | |
4c788679 | 2211 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 2212 | /* Register mmio */ |
4c9bc75c DA |
2213 | resource_size_t rmmio_base; |
2214 | resource_size_t rmmio_size; | |
2c385151 DV |
2215 | /* protects concurrent MM_INDEX/DATA based register access */ |
2216 | spinlock_t mmio_idx_lock; | |
fe78118c AD |
2217 | /* protects concurrent SMC based register access */ |
2218 | spinlock_t smc_idx_lock; | |
0a5b7b0b AD |
2219 | /* protects concurrent PLL register access */ |
2220 | spinlock_t pll_idx_lock; | |
2221 | /* protects concurrent MC register access */ | |
2222 | spinlock_t mc_idx_lock; | |
2223 | /* protects concurrent PCIE register access */ | |
2224 | spinlock_t pcie_idx_lock; | |
2225 | /* protects concurrent PCIE_PORT register access */ | |
2226 | spinlock_t pciep_idx_lock; | |
2227 | /* protects concurrent PIF register access */ | |
2228 | spinlock_t pif_idx_lock; | |
2229 | /* protects concurrent CG register access */ | |
2230 | spinlock_t cg_idx_lock; | |
2231 | /* protects concurrent UVD register access */ | |
2232 | spinlock_t uvd_idx_lock; | |
2233 | /* protects concurrent RCU register access */ | |
2234 | spinlock_t rcu_idx_lock; | |
2235 | /* protects concurrent DIDT register access */ | |
2236 | spinlock_t didt_idx_lock; | |
2237 | /* protects concurrent ENDPOINT (audio) register access */ | |
2238 | spinlock_t end_idx_lock; | |
a0533fbf | 2239 | void __iomem *rmmio; |
771fe6b9 JG |
2240 | radeon_rreg_t mc_rreg; |
2241 | radeon_wreg_t mc_wreg; | |
2242 | radeon_rreg_t pll_rreg; | |
2243 | radeon_wreg_t pll_wreg; | |
de1b2898 | 2244 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
2245 | radeon_rreg_t pciep_rreg; |
2246 | radeon_wreg_t pciep_wreg; | |
351a52a2 AD |
2247 | /* io port */ |
2248 | void __iomem *rio_mem; | |
2249 | resource_size_t rio_mem_size; | |
771fe6b9 JG |
2250 | struct radeon_clock clock; |
2251 | struct radeon_mc mc; | |
2252 | struct radeon_gart gart; | |
2253 | struct radeon_mode_info mode_info; | |
2254 | struct radeon_scratch scratch; | |
75efdee1 | 2255 | struct radeon_doorbell doorbell; |
771fe6b9 | 2256 | struct radeon_mman mman; |
7465280c | 2257 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
0085c950 | 2258 | wait_queue_head_t fence_queue; |
d6999bc7 | 2259 | struct mutex ring_lock; |
e32eb50d | 2260 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
c507f7ef JG |
2261 | bool ib_pool_ready; |
2262 | struct radeon_sa_manager ring_tmp_bo; | |
771fe6b9 JG |
2263 | struct radeon_irq irq; |
2264 | struct radeon_asic *asic; | |
2265 | struct radeon_gem gem; | |
c93bb85b | 2266 | struct radeon_pm pm; |
f2ba57b5 | 2267 | struct radeon_uvd uvd; |
d93f7937 | 2268 | struct radeon_vce vce; |
f657c2a7 | 2269 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 | 2270 | struct radeon_wb wb; |
3ce0a23d | 2271 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
2272 | bool shutdown; |
2273 | bool suspend; | |
ad49f501 | 2274 | bool need_dma32; |
733289c2 | 2275 | bool accel_working; |
a0a53aa8 | 2276 | bool fastfb_working; /* IGP feature*/ |
f9eaf9ae | 2277 | bool needs_reset; |
e024e110 | 2278 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
2279 | const struct firmware *me_fw; /* all family ME firmware */ |
2280 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 2281 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
0af62b01 | 2282 | const struct firmware *mc_fw; /* NI MC firmware */ |
0f0de06c | 2283 | const struct firmware *ce_fw; /* SI CE firmware */ |
02c81327 | 2284 | const struct firmware *mec_fw; /* CIK MEC firmware */ |
21a93e13 | 2285 | const struct firmware *sdma_fw; /* CIK SDMA firmware */ |
66229b20 | 2286 | const struct firmware *smc_fw; /* SMC firmware */ |
4ad9c1c7 | 2287 | const struct firmware *uvd_fw; /* UVD firmware */ |
d93f7937 | 2288 | const struct firmware *vce_fw; /* VCE firmware */ |
16cdf04d | 2289 | struct r600_vram_scratch vram_scratch; |
3e5cb98d | 2290 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 2291 | struct r600_ih ih; /* r6/700 interrupt ring */ |
2948f5e6 | 2292 | struct radeon_rlc rlc; |
963e81f9 | 2293 | struct radeon_mec mec; |
d4877cf2 | 2294 | struct work_struct hotplug_work; |
f122c610 | 2295 | struct work_struct audio_work; |
8f61b34c | 2296 | struct work_struct reset_work; |
18917b60 | 2297 | int num_crtc; /* number of crtcs */ |
40bacf16 | 2298 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
948bee3f | 2299 | bool has_uvd; |
b530602f | 2300 | struct r600_audio audio; /* audio stuff */ |
ce8f5370 | 2301 | struct notifier_block acpi_nb; |
9eba4a93 | 2302 | /* only one userspace can use Hyperz features or CMASK at a time */ |
ab9e1f59 | 2303 | struct drm_file *hyperz_filp; |
9eba4a93 | 2304 | struct drm_file *cmask_filp; |
f376b94f AD |
2305 | /* i2c buses */ |
2306 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; | |
4d8bf9ae CK |
2307 | /* debugfs */ |
2308 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; | |
2309 | unsigned debugfs_count; | |
721604a1 JG |
2310 | /* virtual memory */ |
2311 | struct radeon_vm_manager vm_manager; | |
6759a0a7 | 2312 | struct mutex gpu_clock_mutex; |
67e8e3f9 MO |
2313 | /* memory stats */ |
2314 | atomic64_t vram_usage; | |
2315 | atomic64_t gtt_usage; | |
2316 | atomic64_t num_bytes_moved; | |
fd64ca8a LT |
2317 | /* ACPI interface */ |
2318 | struct radeon_atif atif; | |
e3a15920 | 2319 | struct radeon_atcs atcs; |
f61d5b46 AD |
2320 | /* srbm instance registers */ |
2321 | struct mutex srbm_mutex; | |
64d8a728 AD |
2322 | /* clock, powergating flags */ |
2323 | u32 cg_flags; | |
2324 | u32 pg_flags; | |
10ebc0bc DA |
2325 | |
2326 | struct dev_pm_domain vga_pm_domain; | |
2327 | bool have_disp_power_ref; | |
771fe6b9 JG |
2328 | }; |
2329 | ||
90c4cde9 | 2330 | bool radeon_is_px(struct drm_device *dev); |
771fe6b9 JG |
2331 | int radeon_device_init(struct radeon_device *rdev, |
2332 | struct drm_device *ddev, | |
2333 | struct pci_dev *pdev, | |
2334 | uint32_t flags); | |
2335 | void radeon_device_fini(struct radeon_device *rdev); | |
2336 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
2337 | ||
2ef9bdfe DV |
2338 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
2339 | bool always_indirect); | |
2340 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, | |
2341 | bool always_indirect); | |
6fcbef7a AK |
2342 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
2343 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
351a52a2 | 2344 | |
d5754ab8 AL |
2345 | u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); |
2346 | void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); | |
75efdee1 | 2347 | |
4c788679 JG |
2348 | /* |
2349 | * Cast helper | |
2350 | */ | |
2351 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
2352 | |
2353 | /* | |
2354 | * Registers read & write functions. | |
2355 | */ | |
a0533fbf BH |
2356 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
2357 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) | |
2358 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) | |
2359 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) | |
2ef9bdfe DV |
2360 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
2361 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) | |
2362 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) | |
2363 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) | |
2364 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) | |
771fe6b9 JG |
2365 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
2366 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
2367 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
2368 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
2369 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
2370 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
2371 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
2372 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
492d2b61 AD |
2373 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
2374 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
1d5d0c34 AD |
2375 | #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) |
2376 | #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) | |
ff82bbc4 AD |
2377 | #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) |
2378 | #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) | |
46f9564a AD |
2379 | #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) |
2380 | #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) | |
792edd69 AD |
2381 | #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) |
2382 | #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) | |
2383 | #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) | |
2384 | #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) | |
93656cdd AD |
2385 | #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) |
2386 | #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) | |
1d58234d AD |
2387 | #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) |
2388 | #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
2389 | #define WREG32_P(reg, val, mask) \ |
2390 | do { \ | |
2391 | uint32_t tmp_ = RREG32(reg); \ | |
2392 | tmp_ &= (mask); \ | |
2393 | tmp_ |= ((val) & ~(mask)); \ | |
2394 | WREG32(reg, tmp_); \ | |
2395 | } while (0) | |
d5169fc4 | 2396 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
d43a93c8 | 2397 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
771fe6b9 JG |
2398 | #define WREG32_PLL_P(reg, val, mask) \ |
2399 | do { \ | |
2400 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
2401 | tmp_ &= (mask); \ | |
2402 | tmp_ |= ((val) & ~(mask)); \ | |
2403 | WREG32_PLL(reg, tmp_); \ | |
2404 | } while (0) | |
2ef9bdfe | 2405 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
351a52a2 AD |
2406 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
2407 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) | |
771fe6b9 | 2408 | |
d5754ab8 AL |
2409 | #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) |
2410 | #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) | |
75efdee1 | 2411 | |
de1b2898 DA |
2412 | /* |
2413 | * Indirect registers accessor | |
2414 | */ | |
2415 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
2416 | { | |
0a5b7b0b | 2417 | unsigned long flags; |
de1b2898 DA |
2418 | uint32_t r; |
2419 | ||
0a5b7b0b | 2420 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); |
de1b2898 DA |
2421 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
2422 | r = RREG32(RADEON_PCIE_DATA); | |
0a5b7b0b | 2423 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
de1b2898 DA |
2424 | return r; |
2425 | } | |
2426 | ||
2427 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
2428 | { | |
0a5b7b0b AD |
2429 | unsigned long flags; |
2430 | ||
2431 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); | |
de1b2898 DA |
2432 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
2433 | WREG32(RADEON_PCIE_DATA, (v)); | |
0a5b7b0b | 2434 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); |
de1b2898 DA |
2435 | } |
2436 | ||
1d5d0c34 AD |
2437 | static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) |
2438 | { | |
fe78118c | 2439 | unsigned long flags; |
1d5d0c34 AD |
2440 | u32 r; |
2441 | ||
fe78118c | 2442 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); |
1d5d0c34 AD |
2443 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
2444 | r = RREG32(TN_SMC_IND_DATA_0); | |
fe78118c | 2445 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
1d5d0c34 AD |
2446 | return r; |
2447 | } | |
2448 | ||
2449 | static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2450 | { | |
fe78118c AD |
2451 | unsigned long flags; |
2452 | ||
2453 | spin_lock_irqsave(&rdev->smc_idx_lock, flags); | |
1d5d0c34 AD |
2454 | WREG32(TN_SMC_IND_INDEX_0, (reg)); |
2455 | WREG32(TN_SMC_IND_DATA_0, (v)); | |
fe78118c | 2456 | spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); |
1d5d0c34 AD |
2457 | } |
2458 | ||
ff82bbc4 AD |
2459 | static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) |
2460 | { | |
0a5b7b0b | 2461 | unsigned long flags; |
ff82bbc4 AD |
2462 | u32 r; |
2463 | ||
0a5b7b0b | 2464 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); |
ff82bbc4 AD |
2465 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
2466 | r = RREG32(R600_RCU_DATA); | |
0a5b7b0b | 2467 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
ff82bbc4 AD |
2468 | return r; |
2469 | } | |
2470 | ||
2471 | static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2472 | { | |
0a5b7b0b AD |
2473 | unsigned long flags; |
2474 | ||
2475 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); | |
ff82bbc4 AD |
2476 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); |
2477 | WREG32(R600_RCU_DATA, (v)); | |
0a5b7b0b | 2478 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); |
ff82bbc4 AD |
2479 | } |
2480 | ||
46f9564a AD |
2481 | static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) |
2482 | { | |
0a5b7b0b | 2483 | unsigned long flags; |
46f9564a AD |
2484 | u32 r; |
2485 | ||
0a5b7b0b | 2486 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); |
46f9564a AD |
2487 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
2488 | r = RREG32(EVERGREEN_CG_IND_DATA); | |
0a5b7b0b | 2489 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
46f9564a AD |
2490 | return r; |
2491 | } | |
2492 | ||
2493 | static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2494 | { | |
0a5b7b0b AD |
2495 | unsigned long flags; |
2496 | ||
2497 | spin_lock_irqsave(&rdev->cg_idx_lock, flags); | |
46f9564a AD |
2498 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); |
2499 | WREG32(EVERGREEN_CG_IND_DATA, (v)); | |
0a5b7b0b | 2500 | spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); |
46f9564a AD |
2501 | } |
2502 | ||
792edd69 AD |
2503 | static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) |
2504 | { | |
0a5b7b0b | 2505 | unsigned long flags; |
792edd69 AD |
2506 | u32 r; |
2507 | ||
0a5b7b0b | 2508 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2509 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
2510 | r = RREG32(EVERGREEN_PIF_PHY0_DATA); | |
0a5b7b0b | 2511 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2512 | return r; |
2513 | } | |
2514 | ||
2515 | static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2516 | { | |
0a5b7b0b AD |
2517 | unsigned long flags; |
2518 | ||
2519 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); | |
792edd69 AD |
2520 | WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); |
2521 | WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); | |
0a5b7b0b | 2522 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2523 | } |
2524 | ||
2525 | static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) | |
2526 | { | |
0a5b7b0b | 2527 | unsigned long flags; |
792edd69 AD |
2528 | u32 r; |
2529 | ||
0a5b7b0b | 2530 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2531 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
2532 | r = RREG32(EVERGREEN_PIF_PHY1_DATA); | |
0a5b7b0b | 2533 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2534 | return r; |
2535 | } | |
2536 | ||
2537 | static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2538 | { | |
0a5b7b0b AD |
2539 | unsigned long flags; |
2540 | ||
2541 | spin_lock_irqsave(&rdev->pif_idx_lock, flags); | |
792edd69 AD |
2542 | WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); |
2543 | WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); | |
0a5b7b0b | 2544 | spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); |
792edd69 AD |
2545 | } |
2546 | ||
93656cdd AD |
2547 | static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) |
2548 | { | |
0a5b7b0b | 2549 | unsigned long flags; |
93656cdd AD |
2550 | u32 r; |
2551 | ||
0a5b7b0b | 2552 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); |
93656cdd AD |
2553 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
2554 | r = RREG32(R600_UVD_CTX_DATA); | |
0a5b7b0b | 2555 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
93656cdd AD |
2556 | return r; |
2557 | } | |
2558 | ||
2559 | static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2560 | { | |
0a5b7b0b AD |
2561 | unsigned long flags; |
2562 | ||
2563 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); | |
93656cdd AD |
2564 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); |
2565 | WREG32(R600_UVD_CTX_DATA, (v)); | |
0a5b7b0b | 2566 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); |
93656cdd AD |
2567 | } |
2568 | ||
1d58234d AD |
2569 | |
2570 | static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) | |
2571 | { | |
0a5b7b0b | 2572 | unsigned long flags; |
1d58234d AD |
2573 | u32 r; |
2574 | ||
0a5b7b0b | 2575 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); |
1d58234d AD |
2576 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
2577 | r = RREG32(CIK_DIDT_IND_DATA); | |
0a5b7b0b | 2578 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
1d58234d AD |
2579 | return r; |
2580 | } | |
2581 | ||
2582 | static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2583 | { | |
0a5b7b0b AD |
2584 | unsigned long flags; |
2585 | ||
2586 | spin_lock_irqsave(&rdev->didt_idx_lock, flags); | |
1d58234d AD |
2587 | WREG32(CIK_DIDT_IND_INDEX, (reg)); |
2588 | WREG32(CIK_DIDT_IND_DATA, (v)); | |
0a5b7b0b | 2589 | spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); |
1d58234d AD |
2590 | } |
2591 | ||
771fe6b9 JG |
2592 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
2593 | ||
2594 | ||
2595 | /* | |
2596 | * ASICs helpers. | |
2597 | */ | |
b995e433 DA |
2598 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
2599 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
2600 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
2601 | (rdev->family == CHIP_RV200) || \ | |
2602 | (rdev->family == CHIP_RS100) || \ | |
2603 | (rdev->family == CHIP_RS200) || \ | |
2604 | (rdev->family == CHIP_RV250) || \ | |
2605 | (rdev->family == CHIP_RV280) || \ | |
2606 | (rdev->family == CHIP_RS300)) | |
2607 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
2608 | (rdev->family == CHIP_RV350) || \ | |
2609 | (rdev->family == CHIP_R350) || \ | |
2610 | (rdev->family == CHIP_RV380) || \ | |
2611 | (rdev->family == CHIP_R420) || \ | |
2612 | (rdev->family == CHIP_R423) || \ | |
2613 | (rdev->family == CHIP_RV410) || \ | |
2614 | (rdev->family == CHIP_RS400) || \ | |
2615 | (rdev->family == CHIP_RS480)) | |
3313e3d4 AD |
2616 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
2617 | (rdev->ddev->pdev->device == 0x9443) || \ | |
2618 | (rdev->ddev->pdev->device == 0x944B) || \ | |
2619 | (rdev->ddev->pdev->device == 0x9506) || \ | |
2620 | (rdev->ddev->pdev->device == 0x9509) || \ | |
2621 | (rdev->ddev->pdev->device == 0x950F) || \ | |
2622 | (rdev->ddev->pdev->device == 0x689C) || \ | |
2623 | (rdev->ddev->pdev->device == 0x689D)) | |
771fe6b9 | 2624 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
99999aaa AD |
2625 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
2626 | (rdev->family == CHIP_RS690) || \ | |
2627 | (rdev->family == CHIP_RS740) || \ | |
2628 | (rdev->family >= CHIP_R600)) | |
771fe6b9 JG |
2629 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
2630 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 2631 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
633b9164 AD |
2632 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
2633 | (rdev->flags & RADEON_IS_IGP)) | |
1fe18305 | 2634 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
8848f759 AD |
2635 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
2636 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ | |
2637 | (rdev->flags & RADEON_IS_IGP)) | |
624d3524 | 2638 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
b5d9d726 | 2639 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
e282917c | 2640 | #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) |
be0949f5 AD |
2641 | #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) |
2642 | #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) | |
2643 | #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI)) | |
771fe6b9 | 2644 | |
dc50ba7f AD |
2645 | #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ |
2646 | (rdev->ddev->pdev->device == 0x6850) || \ | |
2647 | (rdev->ddev->pdev->device == 0x6858) || \ | |
2648 | (rdev->ddev->pdev->device == 0x6859) || \ | |
2649 | (rdev->ddev->pdev->device == 0x6840) || \ | |
2650 | (rdev->ddev->pdev->device == 0x6841) || \ | |
2651 | (rdev->ddev->pdev->device == 0x6842) || \ | |
2652 | (rdev->ddev->pdev->device == 0x6843)) | |
2653 | ||
771fe6b9 JG |
2654 | /* |
2655 | * BIOS helpers. | |
2656 | */ | |
2657 | #define RBIOS8(i) (rdev->bios[i]) | |
2658 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
2659 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
2660 | ||
2661 | int radeon_combios_init(struct radeon_device *rdev); | |
2662 | void radeon_combios_fini(struct radeon_device *rdev); | |
2663 | int radeon_atombios_init(struct radeon_device *rdev); | |
2664 | void radeon_atombios_fini(struct radeon_device *rdev); | |
2665 | ||
2666 | ||
2667 | /* | |
2668 | * RING helpers. | |
2669 | */ | |
ce580fab | 2670 | #if DRM_DEBUG_CODE == 0 |
e32eb50d | 2671 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
771fe6b9 | 2672 | { |
e32eb50d CK |
2673 | ring->ring[ring->wptr++] = v; |
2674 | ring->wptr &= ring->ptr_mask; | |
2675 | ring->count_dw--; | |
2676 | ring->ring_free_dw--; | |
771fe6b9 | 2677 | } |
ce580fab AK |
2678 | #else |
2679 | /* With debugging this is just too big to inline */ | |
e32eb50d | 2680 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
ce580fab | 2681 | #endif |
771fe6b9 JG |
2682 | |
2683 | /* | |
2684 | * ASICs macro. | |
2685 | */ | |
068a117c | 2686 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
2687 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
2688 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
2689 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
76a0df85 | 2690 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) |
28d52043 | 2691 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
a2d07b74 | 2692 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
c5b3b850 AD |
2693 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
2694 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) | |
05b07147 CK |
2695 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
2696 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) | |
43f1214a | 2697 | #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
76a0df85 CK |
2698 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) |
2699 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) | |
2700 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) | |
2701 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) | |
2702 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) | |
2703 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) | |
2704 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) | |
2705 | #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) | |
2706 | #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) | |
2707 | #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) | |
b35ea4ab AD |
2708 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
2709 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) | |
c79a49ca | 2710 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
37e9b6a6 | 2711 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
6d92f81d | 2712 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
a973bea1 AD |
2713 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
2714 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) | |
76a0df85 CK |
2715 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) |
2716 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) | |
27cd7769 AD |
2717 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
2718 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) | |
2719 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) | |
2720 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index | |
2721 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index | |
2722 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index | |
798bcf73 AD |
2723 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
2724 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) | |
2725 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) | |
2726 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) | |
2727 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) | |
2728 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) | |
2729 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) | |
73afc70d | 2730 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
b59b7333 | 2731 | #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) |
6bd1c385 | 2732 | #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) |
9e6f3d02 AD |
2733 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
2734 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) | |
c79a49ca | 2735 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
901ea57d AD |
2736 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
2737 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) | |
2738 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) | |
2739 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) | |
def9ba9c | 2740 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
a02fa397 AD |
2741 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
2742 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) | |
2743 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) | |
2744 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) | |
2745 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) | |
69b62ad8 | 2746 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
157fa14d | 2747 | #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) |
69b62ad8 AD |
2748 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
2749 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) | |
454d2e2a | 2750 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
d0418894 | 2751 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
da321c8a AD |
2752 | #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) |
2753 | #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) | |
2754 | #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) | |
914a8987 | 2755 | #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) |
da321c8a | 2756 | #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) |
84dd1928 | 2757 | #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) |
da321c8a | 2758 | #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) |
84dd1928 | 2759 | #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) |
da321c8a AD |
2760 | #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) |
2761 | #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) | |
2762 | #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) | |
2763 | #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) | |
2764 | #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) | |
1316b792 | 2765 | #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) |
70d01a5e | 2766 | #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) |
48783069 | 2767 | #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) |
9e9d9762 | 2768 | #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) |
1c71bda0 | 2769 | #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) |
771fe6b9 | 2770 | |
6cf8a3f5 | 2771 | /* Common functions */ |
700a0cc0 | 2772 | /* AGP */ |
90aca4d2 | 2773 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
1a0041b8 | 2774 | extern void radeon_pci_config_reset(struct radeon_device *rdev); |
410a3418 | 2775 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
700a0cc0 | 2776 | extern void radeon_agp_disable(struct radeon_device *rdev); |
21f9a437 JG |
2777 | extern int radeon_modeset_init(struct radeon_device *rdev); |
2778 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 2779 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 2780 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 2781 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 2782 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 | 2783 | extern void radeon_scratch_init(struct radeon_device *rdev); |
724c80e1 AD |
2784 | extern void radeon_wb_fini(struct radeon_device *rdev); |
2785 | extern int radeon_wb_init(struct radeon_device *rdev); | |
2786 | extern void radeon_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
2787 | extern void radeon_surface_init(struct radeon_device *rdev); |
2788 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 2789 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 2790 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 2791 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 2792 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
d594e46a JG |
2793 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
2794 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
10ebc0bc DA |
2795 | extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); |
2796 | extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); | |
53595338 | 2797 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
2e1b65f9 AD |
2798 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
2799 | const u32 *registers, | |
2800 | const u32 array_size); | |
6cf8a3f5 | 2801 | |
721604a1 JG |
2802 | /* |
2803 | * vm | |
2804 | */ | |
2805 | int radeon_vm_manager_init(struct radeon_device *rdev); | |
2806 | void radeon_vm_manager_fini(struct radeon_device *rdev); | |
6d2f2944 | 2807 | int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
721604a1 | 2808 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
df0af440 CK |
2809 | struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, |
2810 | struct radeon_vm *vm, | |
2811 | struct list_head *head); | |
ee60e29f CK |
2812 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
2813 | struct radeon_vm *vm, int ring); | |
fa688343 CK |
2814 | void radeon_vm_flush(struct radeon_device *rdev, |
2815 | struct radeon_vm *vm, | |
2816 | int ring); | |
ee60e29f CK |
2817 | void radeon_vm_fence(struct radeon_device *rdev, |
2818 | struct radeon_vm *vm, | |
2819 | struct radeon_fence *fence); | |
dce34bfd | 2820 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
6d2f2944 CK |
2821 | int radeon_vm_update_page_directory(struct radeon_device *rdev, |
2822 | struct radeon_vm *vm); | |
9c57a6bd CK |
2823 | int radeon_vm_bo_update(struct radeon_device *rdev, |
2824 | struct radeon_vm *vm, | |
2825 | struct radeon_bo *bo, | |
2826 | struct ttm_mem_reg *mem); | |
721604a1 JG |
2827 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
2828 | struct radeon_bo *bo); | |
421ca7ab CK |
2829 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
2830 | struct radeon_bo *bo); | |
e971bd5e CK |
2831 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
2832 | struct radeon_vm *vm, | |
2833 | struct radeon_bo *bo); | |
2834 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, | |
2835 | struct radeon_bo_va *bo_va, | |
2836 | uint64_t offset, | |
2837 | uint32_t flags); | |
721604a1 | 2838 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
e971bd5e | 2839 | struct radeon_bo_va *bo_va); |
721604a1 | 2840 | |
f122c610 AD |
2841 | /* audio */ |
2842 | void r600_audio_update_hdmi(struct work_struct *work); | |
b530602f AD |
2843 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); |
2844 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); | |
832eafaf AD |
2845 | void r600_audio_enable(struct radeon_device *rdev, |
2846 | struct r600_audio_pin *pin, | |
2847 | bool enable); | |
2848 | void dce6_audio_enable(struct radeon_device *rdev, | |
2849 | struct r600_audio_pin *pin, | |
2850 | bool enable); | |
721604a1 | 2851 | |
16cdf04d AD |
2852 | /* |
2853 | * R600 vram scratch functions | |
2854 | */ | |
2855 | int r600_vram_scratch_init(struct radeon_device *rdev); | |
2856 | void r600_vram_scratch_fini(struct radeon_device *rdev); | |
2857 | ||
285484e2 JG |
2858 | /* |
2859 | * r600 cs checking helper | |
2860 | */ | |
2861 | unsigned r600_mip_minify(unsigned size, unsigned level); | |
2862 | bool r600_fmt_is_valid_color(u32 format); | |
2863 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); | |
2864 | int r600_fmt_get_blocksize(u32 format); | |
2865 | int r600_fmt_get_nblocksx(u32 format, u32 w); | |
2866 | int r600_fmt_get_nblocksy(u32 format, u32 h); | |
2867 | ||
3574dda4 DV |
2868 | /* |
2869 | * r600 functions used by radeon_encoder.c | |
2870 | */ | |
1b688d08 RM |
2871 | struct radeon_hdmi_acr { |
2872 | u32 clock; | |
2873 | ||
2874 | int n_32khz; | |
2875 | int cts_32khz; | |
2876 | ||
2877 | int n_44_1khz; | |
2878 | int cts_44_1khz; | |
2879 | ||
2880 | int n_48khz; | |
2881 | int cts_48khz; | |
2882 | ||
2883 | }; | |
2884 | ||
e55d3e6c RM |
2885 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
2886 | ||
416a2bd2 AD |
2887 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
2888 | u32 tiling_pipe_num, | |
2889 | u32 max_rb_num, | |
2890 | u32 total_max_rb_num, | |
2891 | u32 enabled_rb_mask); | |
fe251e2f | 2892 | |
e55d3e6c RM |
2893 | /* |
2894 | * evergreen functions used by radeon_encoder.c | |
2895 | */ | |
2896 | ||
0af62b01 | 2897 | extern int ni_init_microcode(struct radeon_device *rdev); |
755d819e | 2898 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
0af62b01 | 2899 | |
c4917074 AD |
2900 | /* radeon_acpi.c */ |
2901 | #if defined(CONFIG_ACPI) | |
2902 | extern int radeon_acpi_init(struct radeon_device *rdev); | |
2903 | extern void radeon_acpi_fini(struct radeon_device *rdev); | |
dc50ba7f AD |
2904 | extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); |
2905 | extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, | |
e37e6a0e | 2906 | u8 perf_req, bool advertise); |
dc50ba7f | 2907 | extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); |
c4917074 AD |
2908 | #else |
2909 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } | |
2910 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } | |
2911 | #endif | |
d7a2952f | 2912 | |
c38f34b5 IH |
2913 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
2914 | struct radeon_cs_packet *pkt, | |
2915 | unsigned idx); | |
9ffb7a6d | 2916 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
c3ad63af IH |
2917 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
2918 | struct radeon_cs_packet *pkt); | |
e9716993 IH |
2919 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
2920 | struct radeon_cs_reloc **cs_reloc, | |
2921 | int nomm); | |
40592a17 IH |
2922 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
2923 | uint32_t *vline_start_end, | |
2924 | uint32_t *vline_status); | |
c38f34b5 | 2925 | |
4c788679 JG |
2926 | #include "radeon_object.h" |
2927 | ||
771fe6b9 | 2928 | #endif |