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[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
771fe6b9
JG		 102
103/*
104 * Copy from radeon_drv.h so we don't have to include both and have conflicting
105 * symbol;
106 */
bb635567
JG		 107#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
108#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 109/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 110#define RADEON_IB_POOL_SIZE 16
111#define RADEON_DEBUGFS_MAX_COMPONENTS 32
112#define RADEONFB_CONN_LIMIT 4
113#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 114
1b37078b 115/* max number of rings */
f2ba57b5 116#define RADEON_NUM_RINGS 6
bb635567
JG		 117
118/* fence seq are set to this number when signaled */
119#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 120
121/* internal ring indices */
122/* r1xx+ has gfx CP ring */
f2ba57b5 123#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 124
125/* cayman has 2 compute CP rings */
f2ba57b5
CK		 126#define CAYMAN_RING_TYPE_CP1_INDEX 1
127#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 128
4d75658b
AD		 129/* R600+ has an async dma ring */
130#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 131/* cayman add a second async dma ring */
132#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 133
f2ba57b5
CK		 134/* R600+ */
135#define R600_RING_TYPE_UVD_INDEX 5
136
721604a1 137/* hardcode those limit for now */
ca19f21e 138#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 139#define RADEON_VA_RESERVED_SIZE (8 << 20)
140#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 141
ec46c76d
AD		 142/* reset flags */
143#define RADEON_RESET_GFX (1 << 0)
144#define RADEON_RESET_COMPUTE (1 << 1)
145#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 146#define RADEON_RESET_CP (1 << 3)
147#define RADEON_RESET_GRBM (1 << 4)
148#define RADEON_RESET_DMA1 (1 << 5)
149#define RADEON_RESET_RLC (1 << 6)
150#define RADEON_RESET_SEM (1 << 7)
151#define RADEON_RESET_IH (1 << 8)
152#define RADEON_RESET_VMC (1 << 9)
153#define RADEON_RESET_MC (1 << 10)
154#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 155
22c775ce
AD		 156/* CG block flags */
157#define RADEON_CG_BLOCK_GFX (1 << 0)
158#define RADEON_CG_BLOCK_MC (1 << 1)
159#define RADEON_CG_BLOCK_SDMA (1 << 2)
160#define RADEON_CG_BLOCK_UVD (1 << 3)
161#define RADEON_CG_BLOCK_VCE (1 << 4)
162#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 163#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 164
64d8a728
AD		 165/* CG flags */
166#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
167#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
168#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
169#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
170#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
171#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
172#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
173#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
174#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
175#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
176#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
177#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
178#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
179#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
180#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
181#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
182#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
183
184/* PG flags */
2b19d17f 185#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 186#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
187#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
188#define RADEON_PG_SUPPORT_UVD (1 << 3)
189#define RADEON_PG_SUPPORT_VCE (1 << 4)
190#define RADEON_PG_SUPPORT_CP (1 << 5)
191#define RADEON_PG_SUPPORT_GDS (1 << 6)
192#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
193#define RADEON_PG_SUPPORT_SDMA (1 << 8)
194#define RADEON_PG_SUPPORT_ACP (1 << 9)
195#define RADEON_PG_SUPPORT_SAMU (1 << 10)
196
9e05fa1d
AD		 197/* max cursor sizes (in pixels) */
198#define CURSOR_WIDTH 64
199#define CURSOR_HEIGHT 64
200
201#define CIK_CURSOR_WIDTH 128
202#define CIK_CURSOR_HEIGHT 128
203
771fe6b9
JG		 204/*
205 * Errata workarounds.
206 */
207enum radeon_pll_errata {
208 CHIP_ERRATA_R300_CG = 0x00000001,
209 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
210 CHIP_ERRATA_PLL_DELAY = 0x00000004
211};
212
213
214struct radeon_device;
215
216
217/*
218 * BIOS.
219 */
220bool radeon_get_bios(struct radeon_device *rdev);
221
222/*
3ce0a23d 223 * Dummy page
771fe6b9 224 */
3ce0a23d
JG		 225struct radeon_dummy_page {
226 struct page *page;
227 dma_addr_t addr;
228};
229int radeon_dummy_page_init(struct radeon_device *rdev);
230void radeon_dummy_page_fini(struct radeon_device *rdev);
231
771fe6b9 232
3ce0a23d
JG		 233/*
234 * Clocks
235 */
771fe6b9
JG		 236struct radeon_clock {
237 struct radeon_pll p1pll;
238 struct radeon_pll p2pll;
bcc1c2a1 239 struct radeon_pll dcpll;
771fe6b9
JG		 240 struct radeon_pll spll;
241 struct radeon_pll mpll;
242 /* 10 Khz units */
243 uint32_t default_mclk;
244 uint32_t default_sclk;
bcc1c2a1 245 uint32_t default_dispclk;
4489cd62 246 uint32_t current_dispclk;
bcc1c2a1 247 uint32_t dp_extclk;
b20f9bef 248 uint32_t max_pixel_clock;
771fe6b9
JG		 249};
250
7433874e
RM		 251/*
252 * Power management
253 */
254int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 255void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 256void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 257void radeon_pm_suspend(struct radeon_device *rdev);
258void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 259void radeon_combios_get_power_modes(struct radeon_device *rdev);
260void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 261int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
262 u8 clock_type,
263 u32 clock,
264 bool strobe_mode,
265 struct atom_clock_dividers *dividers);
eaa778af
AD		 266int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
267 u32 clock,
268 bool strobe_mode,
269 struct atom_mpll_param *mpll_param);
8a83ec5e 270void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 271int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
272 u16 voltage_level, u8 voltage_type,
273 u32 *gpio_value, u32 *gpio_mask);
274void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
275 u32 eng_clock, u32 mem_clock);
276int radeon_atom_get_voltage_step(struct radeon_device *rdev,
277 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 278int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
279 u16 voltage_id, u16 *voltage);
beb79f40
AD		 280int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
281 u16 *voltage,
282 u16 leakage_idx);
cc8dbbb4
AD		 283int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
284 u16 *leakage_id);
285int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
286 u16 *vddc, u16 *vddci,
287 u16 virtual_voltage_id,
288 u16 vbios_voltage_id);
ae5b0abb
AD		 289int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
290 u8 voltage_type,
291 u16 nominal_voltage,
292 u16 *true_voltage);
293int radeon_atom_get_min_voltage(struct radeon_device *rdev,
294 u8 voltage_type, u16 *min_voltage);
295int radeon_atom_get_max_voltage(struct radeon_device *rdev,
296 u8 voltage_type, u16 *max_voltage);
297int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 298 u8 voltage_type, u8 voltage_mode,
ae5b0abb 299 struct atom_voltage_table *voltage_table);
58653abd
AD		 300bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
301 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 302void radeon_atom_update_memory_dll(struct radeon_device *rdev,
303 u32 mem_clock);
304void radeon_atom_set_ac_timing(struct radeon_device *rdev,
305 u32 mem_clock);
306int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
307 u8 module_index,
308 struct atom_mc_reg_table *reg_table);
309int radeon_atom_get_memory_info(struct radeon_device *rdev,
310 u8 module_index, struct atom_memory_info *mem_info);
311int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
312 bool gddr5, u8 module_index,
313 struct atom_memory_clock_range_table *mclk_range_table);
314int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
315 u16 voltage_id, u16 *voltage);
f892034a 316void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 317extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
318 unsigned *bankh, unsigned *mtaspect,
319 unsigned *tile_split);
3ce0a23d 320
771fe6b9
JG		 321/*
322 * Fences.
323 */
324struct radeon_fence_driver {
325 uint32_t scratch_reg;
30eb77f4
JG		 326 uint64_t gpu_addr;
327 volatile uint32_t *cpu_addr;
68e250b7
CK		 328 /* sync_seq is protected by ring emission lock */
329 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 330 atomic64_t last_seq;
0a0c7596 331 bool initialized;
771fe6b9
JG		 332};
333
334struct radeon_fence {
335 struct radeon_device *rdev;
336 struct kref kref;
771fe6b9 337 /* protected by radeon_fence.lock */
bb635567 338 uint64_t seq;
7465280c 339 /* RB, DMA, etc. */
bb635567 340 unsigned ring;
771fe6b9
JG		 341};
342
30eb77f4
JG		 343int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
344int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 345void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 346void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 347int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 348void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 349bool radeon_fence_signaled(struct radeon_fence *fence);
350int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
1654b817 351int radeon_fence_wait_locked(struct radeon_fence *fence);
8a47cc9e 352int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 353int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 354int radeon_fence_wait_any(struct radeon_device *rdev,
355 struct radeon_fence **fences,
356 bool intr);
771fe6b9
JG		 357struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
358void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 359unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 360bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
361void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
362static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
363 struct radeon_fence *b)
364{
365 if (!a) {
366 return b;
367 }
368
369 if (!b) {
370 return a;
371 }
372
373 BUG_ON(a->ring != b->ring);
374
375 if (a->seq > b->seq) {
376 return a;
377 } else {
378 return b;
379 }
380}
771fe6b9 381
ee60e29f
CK		 382static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
383 struct radeon_fence *b)
384{
385 if (!a) {
386 return false;
387 }
388
389 if (!b) {
390 return true;
391 }
392
393 BUG_ON(a->ring != b->ring);
394
395 return a->seq < b->seq;
396}
397
e024e110
DA		 398/*
399 * Tiling registers
400 */
401struct radeon_surface_reg {
4c788679 402 struct radeon_bo *bo;
e024e110
DA		 403};
404
405#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 406
407/*
4c788679 408 * TTM.
771fe6b9 409 */
4c788679
JG		 410struct radeon_mman {
411 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 412 struct drm_global_reference mem_global_ref;
4c788679 413 struct ttm_bo_device bdev;
0a0c7596
JG		 414 bool mem_global_referenced;
415 bool initialized;
4c788679
JG		 416};
417
721604a1
JG		 418/* bo virtual address in a specific vm */
419struct radeon_bo_va {
e971bd5e 420 /* protected by bo being reserved */
721604a1 421 struct list_head bo_list;
721604a1
JG		 422 uint64_t soffset;
423 uint64_t eoffset;
424 uint32_t flags;
425 bool valid;
e971bd5e
CK		 426 unsigned ref_count;
427
428 /* protected by vm mutex */
429 struct list_head vm_list;
430
431 /* constant after initialization */
432 struct radeon_vm *vm;
433 struct radeon_bo *bo;
721604a1
JG		 434};
435
4c788679
JG		 436struct radeon_bo {
437 /* Protected by gem.mutex */
438 struct list_head list;
439 /* Protected by tbo.reserved */
312ea8da
JG		 440 u32 placements[3];
441 struct ttm_placement placement;
4c788679
JG		 442 struct ttm_buffer_object tbo;
443 struct ttm_bo_kmap_obj kmap;
444 unsigned pin_count;
445 void *kptr;
446 u32 tiling_flags;
447 u32 pitch;
448 int surface_reg;
721604a1
JG		 449 /* list of all virtual address to which this bo
450 * is associated to
451 */
452 struct list_head va;
4c788679
JG		 453 /* Constant after initialization */
454 struct radeon_device *rdev;
441921d5 455 struct drm_gem_object gem_base;
63bc620b 456
409851f4
JG		 457 struct ttm_bo_kmap_obj dma_buf_vmap;
458 pid_t pid;
4c788679 459};
7e4d15d9 460#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 461
4c788679 462struct radeon_bo_list {
147666fb 463 struct ttm_validate_buffer tv;
4c788679 464 struct radeon_bo *bo;
771fe6b9 465 uint64_t gpu_offset;
4474f3a9
CK		 466 bool written;
467 unsigned domain;
468 unsigned alt_domain;
4c788679 469 u32 tiling_flags;
771fe6b9
JG		 470};
471
409851f4
JG		 472int radeon_gem_debugfs_init(struct radeon_device *rdev);
473
b15ba512
JG		 474/* sub-allocation manager, it has to be protected by another lock.
475 * By conception this is an helper for other part of the driver
476 * like the indirect buffer or semaphore, which both have their
477 * locking.
478 *
479 * Principe is simple, we keep a list of sub allocation in offset
480 * order (first entry has offset == 0, last entry has the highest
481 * offset).
482 *
483 * When allocating new object we first check if there is room at
484 * the end total_size - (last_object_offset + last_object_size) >=
485 * alloc_size. If so we allocate new object there.
486 *
487 * When there is not enough room at the end, we start waiting for
488 * each sub object until we reach object_offset+object_size >=
489 * alloc_size, this object then become the sub object we return.
490 *
491 * Alignment can't be bigger than page size.
492 *
493 * Hole are not considered for allocation to keep things simple.
494 * Assumption is that there won't be hole (all object on same
495 * alignment).
496 */
497struct radeon_sa_manager {
bfb38d35 498 wait_queue_head_t wq;
b15ba512 499 struct radeon_bo *bo;
c3b7fe8b
CK		 500 struct list_head *hole;
501 struct list_head flist[RADEON_NUM_RINGS];
502 struct list_head olist;
b15ba512
JG		 503 unsigned size;
504 uint64_t gpu_addr;
505 void *cpu_ptr;
506 uint32_t domain;
6c4f978b 507 uint32_t align;
b15ba512
JG		 508};
509
510struct radeon_sa_bo;
511
512/* sub-allocation buffer */
513struct radeon_sa_bo {
c3b7fe8b
CK		 514 struct list_head olist;
515 struct list_head flist;
b15ba512 516 struct radeon_sa_manager *manager;
e6661a96
CK		 517 unsigned soffset;
518 unsigned eoffset;
557017a0 519 struct radeon_fence *fence;
b15ba512
JG		 520};
521
771fe6b9
JG		 522/*
523 * GEM objects.
524 */
525struct radeon_gem {
4c788679 526 struct mutex mutex;
771fe6b9
JG		 527 struct list_head objects;
528};
529
530int radeon_gem_init(struct radeon_device *rdev);
531void radeon_gem_fini(struct radeon_device *rdev);
532int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 533 int alignment, int initial_domain,
534 bool discardable, bool kernel,
535 struct drm_gem_object **obj);
771fe6b9 536
ff72145b
DA		 537int radeon_mode_dumb_create(struct drm_file *file_priv,
538 struct drm_device *dev,
539 struct drm_mode_create_dumb *args);
540int radeon_mode_dumb_mmap(struct drm_file *filp,
541 struct drm_device *dev,
542 uint32_t handle, uint64_t *offset_p);
771fe6b9 543
c1341e52
JG		 544/*
545 * Semaphores.
546 */
c1341e52
JG		 547/* everything here is constant */
548struct radeon_semaphore {
a8c05940
JG		 549 struct radeon_sa_bo *sa_bo;
550 signed waiters;
c1341e52 551 uint64_t gpu_addr;
1654b817 552 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 553};
554
c1341e52
JG		 555int radeon_semaphore_create(struct radeon_device *rdev,
556 struct radeon_semaphore **semaphore);
1654b817 557bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 558 struct radeon_semaphore *semaphore);
1654b817 559bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 560 struct radeon_semaphore *semaphore);
1654b817
CK		 561void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
562 struct radeon_fence *fence);
8f676c4c
CK		 563int radeon_semaphore_sync_rings(struct radeon_device *rdev,
564 struct radeon_semaphore *semaphore,
1654b817 565 int waiting_ring);
c1341e52 566void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 567 struct radeon_semaphore **semaphore,
a8c05940 568 struct radeon_fence *fence);
c1341e52 569
771fe6b9
JG		 570/*
571 * GART structures, functions & helpers
572 */
573struct radeon_mc;
574
a77f1718 575#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 576#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 577#define RADEON_GPU_PAGE_SHIFT 12
721604a1 578#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 579
771fe6b9
JG		 580struct radeon_gart {
581 dma_addr_t table_addr;
c9a1be96
JG		 582 struct radeon_bo *robj;
583 void *ptr;
771fe6b9
JG		 584 unsigned num_gpu_pages;
585 unsigned num_cpu_pages;
586 unsigned table_size;
771fe6b9
JG		 587 struct page **pages;
588 dma_addr_t *pages_addr;
589 bool ready;
590};
591
592int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
593void radeon_gart_table_ram_free(struct radeon_device *rdev);
594int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
595void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 596int radeon_gart_table_vram_pin(struct radeon_device *rdev);
597void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 598int radeon_gart_init(struct radeon_device *rdev);
599void radeon_gart_fini(struct radeon_device *rdev);
600void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
601 int pages);
602int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 603 int pages, struct page **pagelist,
604 dma_addr_t *dma_addr);
c9a1be96 605void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 606
607
608/*
609 * GPU MC structures, functions & helpers
610 */
611struct radeon_mc {
612 resource_size_t aper_size;
613 resource_size_t aper_base;
614 resource_size_t agp_base;
7a50f01a
DA		 615 /* for some chips with <= 32MB we need to lie
616 * about vram size near mc fb location */
3ce0a23d 617 u64 mc_vram_size;
d594e46a 618 u64 visible_vram_size;
3ce0a23d
JG		 619 u64 gtt_size;
620 u64 gtt_start;
621 u64 gtt_end;
3ce0a23d
JG		 622 u64 vram_start;
623 u64 vram_end;
771fe6b9 624 unsigned vram_width;
3ce0a23d 625 u64 real_vram_size;
771fe6b9
JG		 626 int vram_mtrr;
627 bool vram_is_ddr;
d594e46a 628 bool igp_sideport_enabled;
8d369bb1 629 u64 gtt_base_align;
9ed8b1f9 630 u64 mc_mask;
771fe6b9
JG		 631};
632
06b6476d
AD		 633bool radeon_combios_sideport_present(struct radeon_device *rdev);
634bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 635
636/*
637 * GPU scratch registers structures, functions & helpers
638 */
639struct radeon_scratch {
640 unsigned num_reg;
724c80e1 641 uint32_t reg_base;
771fe6b9
JG		 642 bool free[32];
643 uint32_t reg[32];
644};
645
646int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
647void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
648
75efdee1
AD		 649/*
650 * GPU doorbell structures, functions & helpers
651 */
d5754ab8
AL		 652#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
653
75efdee1 654struct radeon_doorbell {
75efdee1 655 /* doorbell mmio */
d5754ab8
AL		 656 resource_size_t base;
657 resource_size_t size;
658 u32 __iomem *ptr;
659 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
660 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 661};
662
663int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
664void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 665
666/*
667 * IRQS.
668 */
6f34be50
AD		 669
670struct radeon_unpin_work {
671 struct work_struct work;
672 struct radeon_device *rdev;
673 int crtc_id;
674 struct radeon_fence *fence;
675 struct drm_pending_vblank_event *event;
676 struct radeon_bo *old_rbo;
677 u64 new_crtc_base;
678};
679
680struct r500_irq_stat_regs {
681 u32 disp_int;
f122c610 682 u32 hdmi0_status;
6f34be50
AD		 683};
684
685struct r600_irq_stat_regs {
686 u32 disp_int;
687 u32 disp_int_cont;
688 u32 disp_int_cont2;
689 u32 d1grph_int;
690 u32 d2grph_int;
f122c610
AD		 691 u32 hdmi0_status;
692 u32 hdmi1_status;
6f34be50
AD		 693};
694
695struct evergreen_irq_stat_regs {
696 u32 disp_int;
697 u32 disp_int_cont;
698 u32 disp_int_cont2;
699 u32 disp_int_cont3;
700 u32 disp_int_cont4;
701 u32 disp_int_cont5;
702 u32 d1grph_int;
703 u32 d2grph_int;
704 u32 d3grph_int;
705 u32 d4grph_int;
706 u32 d5grph_int;
707 u32 d6grph_int;
f122c610
AD		 708 u32 afmt_status1;
709 u32 afmt_status2;
710 u32 afmt_status3;
711 u32 afmt_status4;
712 u32 afmt_status5;
713 u32 afmt_status6;
6f34be50
AD		 714};
715
a59781bb
AD		 716struct cik_irq_stat_regs {
717 u32 disp_int;
718 u32 disp_int_cont;
719 u32 disp_int_cont2;
720 u32 disp_int_cont3;
721 u32 disp_int_cont4;
722 u32 disp_int_cont5;
723 u32 disp_int_cont6;
724};
725
6f34be50
AD		 726union radeon_irq_stat_regs {
727 struct r500_irq_stat_regs r500;
728 struct r600_irq_stat_regs r600;
729 struct evergreen_irq_stat_regs evergreen;
a59781bb 730 struct cik_irq_stat_regs cik;
6f34be50
AD		 731};
732
54bd5206
IH		 733#define RADEON_MAX_HPD_PINS 6
734#define RADEON_MAX_CRTCS 6
b530602f 735#define RADEON_MAX_AFMT_BLOCKS 7
54bd5206 736
771fe6b9 737struct radeon_irq {
fb98257a
CK		 738 bool installed;
739 spinlock_t lock;
736fc37f 740 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 741 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 742 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 743 wait_queue_head_t vblank_queue;
744 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 745 bool afmt[RADEON_MAX_AFMT_BLOCKS];
746 union radeon_irq_stat_regs stat_regs;
4a6369e9 747 bool dpm_thermal;
771fe6b9
JG		 748};
749
750int radeon_irq_kms_init(struct radeon_device *rdev);
751void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 752void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
753void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 754void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
755void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 756void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
757void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
758void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
759void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 760
761/*
e32eb50d 762 * CP & rings.
771fe6b9 763 */
7465280c 764
771fe6b9 765struct radeon_ib {
68470ae7
JG		 766 struct radeon_sa_bo *sa_bo;
767 uint32_t length_dw;
768 uint64_t gpu_addr;
769 uint32_t *ptr;
876dc9f3 770 int ring;
68470ae7 771 struct radeon_fence *fence;
4bf3dd92 772 struct radeon_vm *vm;
68470ae7
JG		 773 bool is_const_ib;
774 struct radeon_semaphore *semaphore;
771fe6b9
JG		 775};
776
e32eb50d 777struct radeon_ring {
4c788679 778 struct radeon_bo *ring_obj;
771fe6b9
JG		 779 volatile uint32_t *ring;
780 unsigned rptr;
5596a9db
CK		 781 unsigned rptr_offs;
782 unsigned rptr_reg;
45df6803 783 unsigned rptr_save_reg;
89d35807
AD		 784 u64 next_rptr_gpu_addr;
785 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 786 unsigned wptr;
787 unsigned wptr_old;
5596a9db 788 unsigned wptr_reg;
771fe6b9
JG		 789 unsigned ring_size;
790 unsigned ring_free_dw;
791 int count_dw;
069211e5
CK		 792 unsigned long last_activity;
793 unsigned last_rptr;
771fe6b9
JG		 794 uint64_t gpu_addr;
795 uint32_t align_mask;
796 uint32_t ptr_mask;
771fe6b9 797 bool ready;
78c5560a 798 u32 nop;
8b25ed34 799 u32 idx;
5f0839c1
JG		 800 u64 last_semaphore_signal_addr;
801 u64 last_semaphore_wait_addr;
963e81f9
AD		 802 /* for CIK queues */
803 u32 me;
804 u32 pipe;
805 u32 queue;
806 struct radeon_bo *mqd_obj;
d5754ab8 807 u32 doorbell_index;
963e81f9
AD		 808 unsigned wptr_offs;
809};
810
811struct radeon_mec {
812 struct radeon_bo *hpd_eop_obj;
813 u64 hpd_eop_gpu_addr;
814 u32 num_pipe;
815 u32 num_mec;
816 u32 num_queue;
771fe6b9
JG		 817};
818
721604a1
JG		 819/*
820 * VM
821 */
ee60e29f 822
fa87e62d 823/* maximum number of VMIDs */
ee60e29f
CK		 824#define RADEON_NUM_VM 16
825
fa87e62d
DC		 826/* defines number of bits in page table versus page directory,
827 * a page is 4KB so we have 12 bits offset, 9 bits in the page
828 * table and the remaining 19 bits are in the page directory */
829#define RADEON_VM_BLOCK_SIZE 9
830
831/* number of entries in page table */
832#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
833
1c01103c
AD		 834/* PTBs (Page Table Blocks) need to be aligned to 32K */
835#define RADEON_VM_PTB_ALIGN_SIZE 32768
836#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
837#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
838
24c16439
CK		 839#define R600_PTE_VALID (1 << 0)
840#define R600_PTE_SYSTEM (1 << 1)
841#define R600_PTE_SNOOPED (1 << 2)
842#define R600_PTE_READABLE (1 << 5)
843#define R600_PTE_WRITEABLE (1 << 6)
844
721604a1
JG		 845struct radeon_vm {
846 struct list_head list;
847 struct list_head va;
ee60e29f 848 unsigned id;
90a51a32
CK		 849
850 /* contains the page directory */
851 struct radeon_sa_bo *page_directory;
852 uint64_t pd_gpu_addr;
853
854 /* array of page tables, one for each page directory entry */
855 struct radeon_sa_bo **page_tables;
856
721604a1
JG		 857 struct mutex mutex;
858 /* last fence for cs using this vm */
859 struct radeon_fence *fence;
9b40e5d8
CK		 860 /* last flush or NULL if we still need to flush */
861 struct radeon_fence *last_flush;
721604a1
JG		 862};
863
721604a1 864struct radeon_vm_manager {
36ff39c4 865 struct mutex lock;
721604a1 866 struct list_head lru_vm;
ee60e29f 867 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 868 struct radeon_sa_manager sa_manager;
869 uint32_t max_pfn;
721604a1
JG		 870 /* number of VMIDs */
871 unsigned nvm;
872 /* vram base address for page table entry */
873 u64 vram_base_offset;
67e915e4
AD		 874 /* is vm enabled? */
875 bool enabled;
721604a1
JG		 876};
877
878/*
879 * file private structure
880 */
881struct radeon_fpriv {
882 struct radeon_vm vm;
883};
884
d8f60cfc
AD		 885/*
886 * R6xx+ IH ring
887 */
888struct r600_ih {
4c788679 889 struct radeon_bo *ring_obj;
d8f60cfc
AD		 890 volatile uint32_t *ring;
891 unsigned rptr;
d8f60cfc
AD		 892 unsigned ring_size;
893 uint64_t gpu_addr;
d8f60cfc 894 uint32_t ptr_mask;
c20dc369 895 atomic_t lock;
d8f60cfc
AD		 896 bool enabled;
897};
898
347e7592 899/*
2948f5e6 900 * RLC stuff
347e7592 901 */
2948f5e6
AD		 902#include "clearstate_defs.h"
903
904struct radeon_rlc {
347e7592
AD		 905 /* for power gating */
906 struct radeon_bo *save_restore_obj;
907 uint64_t save_restore_gpu_addr;
2948f5e6 908 volatile uint32_t *sr_ptr;
1fd11777 909 const u32 *reg_list;
2948f5e6 910 u32 reg_list_size;
347e7592
AD		 911 /* for clear state */
912 struct radeon_bo *clear_state_obj;
913 uint64_t clear_state_gpu_addr;
2948f5e6 914 volatile uint32_t *cs_ptr;
1fd11777 915 const struct cs_section_def *cs_data;
22c775ce
AD		 916 u32 clear_state_size;
917 /* for cp tables */
918 struct radeon_bo *cp_table_obj;
919 uint64_t cp_table_gpu_addr;
920 volatile uint32_t *cp_table_ptr;
921 u32 cp_table_size;
347e7592
AD		 922};
923
69e130a6 924int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 925 struct radeon_ib *ib, struct radeon_vm *vm,
926 unsigned size);
f2e39221 927void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 928int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
929 struct radeon_ib *const_ib);
771fe6b9
JG		 930int radeon_ib_pool_init(struct radeon_device *rdev);
931void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 932int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 933/* Ring access between begin & end cannot sleep */
89d35807
AD		 934bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
935 struct radeon_ring *ring);
e32eb50d
CK		 936void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
937int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
938int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
939void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
940void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 941void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 942void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
943int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 944void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 945void radeon_ring_lockup_update(struct radeon_ring *ring);
946bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 947unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
948 uint32_t **data);
949int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
950 unsigned size, uint32_t *data);
e32eb50d 951int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
2e1e6dad 952 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
e32eb50d 953void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 954
955
4d75658b
AD		 956/* r600 async dma */
957void r600_dma_stop(struct radeon_device *rdev);
958int r600_dma_resume(struct radeon_device *rdev);
959void r600_dma_fini(struct radeon_device *rdev);
960
8c5fd7ef
AD		 961void cayman_dma_stop(struct radeon_device *rdev);
962int cayman_dma_resume(struct radeon_device *rdev);
963void cayman_dma_fini(struct radeon_device *rdev);
964
771fe6b9
JG		 965/*
966 * CS.
967 */
968struct radeon_cs_reloc {
969 struct drm_gem_object *gobj;
4c788679
JG		 970 struct radeon_bo *robj;
971 struct radeon_bo_list lobj;
771fe6b9
JG		 972 uint32_t handle;
973 uint32_t flags;
974};
975
976struct radeon_cs_chunk {
977 uint32_t chunk_id;
978 uint32_t length_dw;
979 uint32_t *kdata;
721604a1 980 void __user *user_ptr;
771fe6b9
JG		 981};
982
983struct radeon_cs_parser {
c8c15ff1 984 struct device *dev;
771fe6b9
JG		 985 struct radeon_device *rdev;
986 struct drm_file *filp;
987 /* chunks */
988 unsigned nchunks;
989 struct radeon_cs_chunk *chunks;
990 uint64_t *chunks_array;
991 /* IB */
992 unsigned idx;
993 /* relocations */
994 unsigned nrelocs;
995 struct radeon_cs_reloc *relocs;
996 struct radeon_cs_reloc **relocs_ptr;
997 struct list_head validated;
cf4ccd01 998 unsigned dma_reloc_idx;
771fe6b9
JG		 999 /* indices of various chunks */
1000 int chunk_ib_idx;
1001 int chunk_relocs_idx;
721604a1 1002 int chunk_flags_idx;
dfcf5f36 1003 int chunk_const_ib_idx;
f2e39221
JG		 1004 struct radeon_ib ib;
1005 struct radeon_ib const_ib;
771fe6b9 1006 void *track;
3ce0a23d 1007 unsigned family;
e70f224c 1008 int parser_error;
721604a1
JG		 1009 u32 cs_flags;
1010 u32 ring;
1011 s32 priority;
ecff665f 1012 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1013};
1014
28a326c5
ML		 1015static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1016{
1017 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1018
1019 if (ibc->kdata)
1020 return ibc->kdata[idx];
1021 return p->ib.ptr[idx];
1022}
1023
513bcb46 1024
771fe6b9
JG		 1025struct radeon_cs_packet {
1026 unsigned idx;
1027 unsigned type;
1028 unsigned reg;
1029 unsigned opcode;
1030 int count;
1031 unsigned one_reg_wr;
1032};
1033
1034typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1035 struct radeon_cs_packet *pkt,
1036 unsigned idx, unsigned reg);
1037typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1038 struct radeon_cs_packet *pkt);
1039
1040
1041/*
1042 * AGP
1043 */
1044int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1045void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1046void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1047void radeon_agp_fini(struct radeon_device *rdev);
1048
1049
1050/*
1051 * Writeback
1052 */
1053struct radeon_wb {
4c788679 1054 struct radeon_bo *wb_obj;
771fe6b9
JG		 1055 volatile uint32_t *wb;
1056 uint64_t gpu_addr;
724c80e1 1057 bool enabled;
d0f8a854 1058 bool use_event;
771fe6b9
JG		 1059};
1060
724c80e1 1061#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1062#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1063#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1064#define RADEON_WB_CP1_RPTR_OFFSET 1280
1065#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1066#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1067#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1068#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1069#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1070#define CIK_WB_CP1_WPTR_OFFSET 3328
1071#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1072
c93bb85b
JG		 1073/**
1074 * struct radeon_pm - power management datas
1075 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1076 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1077 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1078 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1079 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1080 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1081 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1082 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1083 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1084 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1085 * @needed_bandwidth: current bandwidth needs
1086 *
1087 * It keeps track of various data needed to take powermanagement decision.
25985edc 1088 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1089 * Equation between gpu/memory clock and available bandwidth is hw dependent
1090 * (type of memory, bus size, efficiency, ...)
1091 */
ce8f5370
AD		 1092
1093enum radeon_pm_method {
1094 PM_METHOD_PROFILE,
1095 PM_METHOD_DYNPM,
da321c8a 1096 PM_METHOD_DPM,
ce8f5370
AD		 1097};
1098
1099enum radeon_dynpm_state {
1100 DYNPM_STATE_DISABLED,
1101 DYNPM_STATE_MINIMUM,
1102 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1103 DYNPM_STATE_ACTIVE,
1104 DYNPM_STATE_SUSPENDED,
c913e23a 1105};
ce8f5370
AD		 1106enum radeon_dynpm_action {
1107 DYNPM_ACTION_NONE,
1108 DYNPM_ACTION_MINIMUM,
1109 DYNPM_ACTION_DOWNCLOCK,
1110 DYNPM_ACTION_UPCLOCK,
1111 DYNPM_ACTION_DEFAULT
c913e23a 1112};
56278a8e
AD		 1113
1114enum radeon_voltage_type {
1115 VOLTAGE_NONE = 0,
1116 VOLTAGE_GPIO,
1117 VOLTAGE_VDDC,
1118 VOLTAGE_SW
1119};
1120
0ec0e74f 1121enum radeon_pm_state_type {
da321c8a 1122 /* not used for dpm */
0ec0e74f
AD		 1123 POWER_STATE_TYPE_DEFAULT,
1124 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1125 /* user selectable states */
0ec0e74f
AD		 1126 POWER_STATE_TYPE_BATTERY,
1127 POWER_STATE_TYPE_BALANCED,
1128 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1129 /* internal states */
1130 POWER_STATE_TYPE_INTERNAL_UVD,
1131 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1132 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1133 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1134 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1135 POWER_STATE_TYPE_INTERNAL_BOOT,
1136 POWER_STATE_TYPE_INTERNAL_THERMAL,
1137 POWER_STATE_TYPE_INTERNAL_ACPI,
1138 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1139 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1140};
1141
ce8f5370
AD		 1142enum radeon_pm_profile_type {
1143 PM_PROFILE_DEFAULT,
1144 PM_PROFILE_AUTO,
1145 PM_PROFILE_LOW,
c9e75b21 1146 PM_PROFILE_MID,
ce8f5370
AD		 1147 PM_PROFILE_HIGH,
1148};
1149
1150#define PM_PROFILE_DEFAULT_IDX 0
1151#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1152#define PM_PROFILE_MID_SH_IDX 2
1153#define PM_PROFILE_HIGH_SH_IDX 3
1154#define PM_PROFILE_LOW_MH_IDX 4
1155#define PM_PROFILE_MID_MH_IDX 5
1156#define PM_PROFILE_HIGH_MH_IDX 6
1157#define PM_PROFILE_MAX 7
ce8f5370
AD		 1158
1159struct radeon_pm_profile {
1160 int dpms_off_ps_idx;
1161 int dpms_on_ps_idx;
1162 int dpms_off_cm_idx;
1163 int dpms_on_cm_idx;
516d0e46
AD		 1164};
1165
21a8122a
AD		 1166enum radeon_int_thermal_type {
1167 THERMAL_TYPE_NONE,
da321c8a
AD		 1168 THERMAL_TYPE_EXTERNAL,
1169 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1170 THERMAL_TYPE_RV6XX,
1171 THERMAL_TYPE_RV770,
da321c8a 1172 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1173 THERMAL_TYPE_EVERGREEN,
e33df25f 1174 THERMAL_TYPE_SUMO,
4fddba1f 1175 THERMAL_TYPE_NI,
14607d08 1176 THERMAL_TYPE_SI,
da321c8a 1177 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1178 THERMAL_TYPE_CI,
16fbe00d 1179 THERMAL_TYPE_KV,
21a8122a
AD		 1180};
1181
56278a8e
AD		 1182struct radeon_voltage {
1183 enum radeon_voltage_type type;
1184 /* gpio voltage */
1185 struct radeon_gpio_rec gpio;
1186 u32 delay; /* delay in usec from voltage drop to sclk change */
1187 bool active_high; /* voltage drop is active when bit is high */
1188 /* VDDC voltage */
1189 u8 vddc_id; /* index into vddc voltage table */
1190 u8 vddci_id; /* index into vddci voltage table */
1191 bool vddci_enabled;
1192 /* r6xx+ sw */
2feea49a
AD		 1193 u16 voltage;
1194 /* evergreen+ vddci */
1195 u16 vddci;
56278a8e
AD		 1196};
1197
d7311171
AD		 1198/* clock mode flags */
1199#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1200
56278a8e
AD		 1201struct radeon_pm_clock_info {
1202 /* memory clock */
1203 u32 mclk;
1204 /* engine clock */
1205 u32 sclk;
1206 /* voltage info */
1207 struct radeon_voltage voltage;
d7311171 1208 /* standardized clock flags */
56278a8e
AD		 1209 u32 flags;
1210};
1211
a48b9b4e 1212/* state flags */
d7311171 1213#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1214
56278a8e 1215struct radeon_power_state {
0ec0e74f 1216 enum radeon_pm_state_type type;
8f3f1c9a 1217 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1218 /* number of valid clock modes in this power state */
1219 int num_clock_modes;
56278a8e 1220 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1221 /* standardized state flags */
1222 u32 flags;
79daedc9
AD		 1223 u32 misc; /* vbios specific flags */
1224 u32 misc2; /* vbios specific flags */
1225 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1226};
1227
27459324
RM		 1228/*
1229 * Some modes are overclocked by very low value, accept them
1230 */
1231#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1232
2e9d4c05
AD		 1233enum radeon_dpm_auto_throttle_src {
1234 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1235 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1236};
1237
1238enum radeon_dpm_event_src {
1239 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1240 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1241 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1242 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1243 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1244};
1245
da321c8a
AD		 1246struct radeon_ps {
1247 u32 caps; /* vbios flags */
1248 u32 class; /* vbios flags */
1249 u32 class2; /* vbios flags */
1250 /* UVD clocks */
1251 u32 vclk;
1252 u32 dclk;
c4453e66
AD		 1253 /* VCE clocks */
1254 u32 evclk;
1255 u32 ecclk;
da321c8a
AD		 1256 /* asic priv */
1257 void *ps_priv;
1258};
1259
1260struct radeon_dpm_thermal {
1261 /* thermal interrupt work */
1262 struct work_struct work;
1263 /* low temperature threshold */
1264 int min_temp;
1265 /* high temperature threshold */
1266 int max_temp;
1267 /* was interrupt low to high or high to low */
1268 bool high_to_low;
1269};
1270
d22b7e40
AD		 1271enum radeon_clk_action
1272{
1273 RADEON_SCLK_UP = 1,
1274 RADEON_SCLK_DOWN
1275};
1276
1277struct radeon_blacklist_clocks
1278{
1279 u32 sclk;
1280 u32 mclk;
1281 enum radeon_clk_action action;
1282};
1283
61b7d601
AD		 1284struct radeon_clock_and_voltage_limits {
1285 u32 sclk;
1286 u32 mclk;
cdf6e805
AD		 1287 u16 vddc;
1288 u16 vddci;
61b7d601
AD		 1289};
1290
1291struct radeon_clock_array {
1292 u32 count;
1293 u32 *values;
1294};
1295
1296struct radeon_clock_voltage_dependency_entry {
1297 u32 clk;
1298 u16 v;
1299};
1300
1301struct radeon_clock_voltage_dependency_table {
1302 u32 count;
1303 struct radeon_clock_voltage_dependency_entry *entries;
1304};
1305
ef976ec4
AD		 1306union radeon_cac_leakage_entry {
1307 struct {
1308 u16 vddc;
1309 u32 leakage;
1310 };
1311 struct {
1312 u16 vddc1;
1313 u16 vddc2;
1314 u16 vddc3;
1315 };
61b7d601
AD		 1316};
1317
1318struct radeon_cac_leakage_table {
1319 u32 count;
ef976ec4 1320 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1321};
1322
929ee7a8
AD		 1323struct radeon_phase_shedding_limits_entry {
1324 u16 voltage;
1325 u32 sclk;
1326 u32 mclk;
1327};
1328
1329struct radeon_phase_shedding_limits_table {
1330 u32 count;
1331 struct radeon_phase_shedding_limits_entry *entries;
1332};
1333
84a9d9ee
AD		 1334struct radeon_uvd_clock_voltage_dependency_entry {
1335 u32 vclk;
1336 u32 dclk;
1337 u16 v;
1338};
1339
1340struct radeon_uvd_clock_voltage_dependency_table {
1341 u8 count;
1342 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1343};
1344
d29f013b
AD		 1345struct radeon_vce_clock_voltage_dependency_entry {
1346 u32 ecclk;
1347 u32 evclk;
1348 u16 v;
1349};
1350
1351struct radeon_vce_clock_voltage_dependency_table {
1352 u8 count;
1353 struct radeon_vce_clock_voltage_dependency_entry *entries;
1354};
1355
a5cb318e
AD		 1356struct radeon_ppm_table {
1357 u8 ppm_design;
1358 u16 cpu_core_number;
1359 u32 platform_tdp;
1360 u32 small_ac_platform_tdp;
1361 u32 platform_tdc;
1362 u32 small_ac_platform_tdc;
1363 u32 apu_tdp;
1364 u32 dgpu_tdp;
1365 u32 dgpu_ulv_power;
1366 u32 tj_max;
1367};
1368
58cb7632
AD		 1369struct radeon_cac_tdp_table {
1370 u16 tdp;
1371 u16 configurable_tdp;
1372 u16 tdc;
1373 u16 battery_power_limit;
1374 u16 small_power_limit;
1375 u16 low_cac_leakage;
1376 u16 high_cac_leakage;
1377 u16 maximum_power_delivery_limit;
1378};
1379
61b7d601
AD		 1380struct radeon_dpm_dynamic_state {
1381 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1382 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1383 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1384 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1385 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1386 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1387 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1388 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1389 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1390 struct radeon_clock_array valid_sclk_values;
1391 struct radeon_clock_array valid_mclk_values;
1392 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1393 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1394 u32 mclk_sclk_ratio;
1395 u32 sclk_mclk_delta;
1396 u16 vddc_vddci_delta;
1397 u16 min_vddc_for_pcie_gen2;
1398 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1399 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1400 struct radeon_ppm_table *ppm_table;
58cb7632 1401 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1402};
1403
1404struct radeon_dpm_fan {
1405 u16 t_min;
1406 u16 t_med;
1407 u16 t_high;
1408 u16 pwm_min;
1409 u16 pwm_med;
1410 u16 pwm_high;
1411 u8 t_hyst;
1412 u32 cycle_delay;
1413 u16 t_max;
1414 bool ucode_fan_control;
1415};
1416
32ce4652
AD		 1417enum radeon_pcie_gen {
1418 RADEON_PCIE_GEN1 = 0,
1419 RADEON_PCIE_GEN2 = 1,
1420 RADEON_PCIE_GEN3 = 2,
1421 RADEON_PCIE_GEN_INVALID = 0xffff
1422};
1423
70d01a5e
AD		 1424enum radeon_dpm_forced_level {
1425 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1426 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1427 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1428};
1429
da321c8a
AD		 1430struct radeon_dpm {
1431 struct radeon_ps *ps;
1432 /* number of valid power states */
1433 int num_ps;
1434 /* current power state that is active */
1435 struct radeon_ps *current_ps;
1436 /* requested power state */
1437 struct radeon_ps *requested_ps;
1438 /* boot up power state */
1439 struct radeon_ps *boot_ps;
1440 /* default uvd power state */
1441 struct radeon_ps *uvd_ps;
1442 enum radeon_pm_state_type state;
1443 enum radeon_pm_state_type user_state;
1444 u32 platform_caps;
1445 u32 voltage_response_time;
1446 u32 backbias_response_time;
1447 void *priv;
1448 u32 new_active_crtcs;
1449 int new_active_crtc_count;
1450 u32 current_active_crtcs;
1451 int current_active_crtc_count;
61b7d601
AD		 1452 struct radeon_dpm_dynamic_state dyn_state;
1453 struct radeon_dpm_fan fan;
1454 u32 tdp_limit;
1455 u32 near_tdp_limit;
a9e61410 1456 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1457 u32 sq_ramping_threshold;
1458 u32 cac_leakage;
1459 u16 tdp_od_limit;
1460 u32 tdp_adjustment;
1461 u16 load_line_slope;
1462 bool power_control;
5ca302f7 1463 bool ac_power;
da321c8a
AD		 1464 /* special states active */
1465 bool thermal_active;
8a227555 1466 bool uvd_active;
da321c8a
AD		 1467 /* thermal handling */
1468 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1469 /* forced levels */
1470 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1471 /* track UVD streams */
1472 unsigned sd;
1473 unsigned hd;
da321c8a
AD		 1474};
1475
ce3537d5 1476void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
da321c8a 1477
c93bb85b 1478struct radeon_pm {
c913e23a 1479 struct mutex mutex;
db7fce39
CK		 1480 /* write locked while reprogramming mclk */
1481 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1482 u32 active_crtcs;
1483 int active_crtc_count;
c913e23a 1484 int req_vblank;
839461d3 1485 bool vblank_sync;
c93bb85b
JG		 1486 fixed20_12 max_bandwidth;
1487 fixed20_12 igp_sideport_mclk;
1488 fixed20_12 igp_system_mclk;
1489 fixed20_12 igp_ht_link_clk;
1490 fixed20_12 igp_ht_link_width;
1491 fixed20_12 k8_bandwidth;
1492 fixed20_12 sideport_bandwidth;
1493 fixed20_12 ht_bandwidth;
1494 fixed20_12 core_bandwidth;
1495 fixed20_12 sclk;
f47299c5 1496 fixed20_12 mclk;
c93bb85b 1497 fixed20_12 needed_bandwidth;
0975b162 1498 struct radeon_power_state *power_state;
56278a8e
AD		 1499 /* number of valid power states */
1500 int num_power_states;
a48b9b4e
AD		 1501 int current_power_state_index;
1502 int current_clock_mode_index;
1503 int requested_power_state_index;
1504 int requested_clock_mode_index;
1505 int default_power_state_index;
1506 u32 current_sclk;
1507 u32 current_mclk;
2feea49a
AD		 1508 u16 current_vddc;
1509 u16 current_vddci;
9ace9f7b
AD		 1510 u32 default_sclk;
1511 u32 default_mclk;
2feea49a
AD		 1512 u16 default_vddc;
1513 u16 default_vddci;
29fb52ca 1514 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1515 /* selected pm method */
1516 enum radeon_pm_method pm_method;
1517 /* dynpm power management */
1518 struct delayed_work dynpm_idle_work;
1519 enum radeon_dynpm_state dynpm_state;
1520 enum radeon_dynpm_action dynpm_planned_action;
1521 unsigned long dynpm_action_timeout;
1522 bool dynpm_can_upclock;
1523 bool dynpm_can_downclock;
1524 /* profile-based power management */
1525 enum radeon_pm_profile_type profile;
1526 int profile_index;
1527 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1528 /* internal thermal controller on rv6xx+ */
1529 enum radeon_int_thermal_type int_thermal_type;
1530 struct device *int_hwmon_dev;
da321c8a
AD		 1531 /* dpm */
1532 bool dpm_enabled;
1533 struct radeon_dpm dpm;
c93bb85b
JG		 1534};
1535
a4c9e2ee
AD		 1536int radeon_pm_get_type_index(struct radeon_device *rdev,
1537 enum radeon_pm_state_type ps_type,
1538 int instance);
f2ba57b5
CK		 1539/*
1540 * UVD
1541 */
1542#define RADEON_MAX_UVD_HANDLES 10
1543#define RADEON_UVD_STACK_SIZE (1024*1024)
1544#define RADEON_UVD_HEAP_SIZE (1024*1024)
1545
1546struct radeon_uvd {
1547 struct radeon_bo *vcpu_bo;
1548 void *cpu_addr;
1549 uint64_t gpu_addr;
9cc2e0e9 1550 void *saved_bo;
f2ba57b5
CK		 1551 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1552 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1553 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1554 struct delayed_work idle_work;
f2ba57b5
CK		 1555};
1556
1557int radeon_uvd_init(struct radeon_device *rdev);
1558void radeon_uvd_fini(struct radeon_device *rdev);
1559int radeon_uvd_suspend(struct radeon_device *rdev);
1560int radeon_uvd_resume(struct radeon_device *rdev);
1561int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1562 uint32_t handle, struct radeon_fence **fence);
1563int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1564 uint32_t handle, struct radeon_fence **fence);
1565void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1566void radeon_uvd_free_handles(struct radeon_device *rdev,
1567 struct drm_file *filp);
1568int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1569void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1570int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1571 unsigned vclk, unsigned dclk,
1572 unsigned vco_min, unsigned vco_max,
1573 unsigned fb_factor, unsigned fb_mask,
1574 unsigned pd_min, unsigned pd_max,
1575 unsigned pd_even,
1576 unsigned *optimal_fb_div,
1577 unsigned *optimal_vclk_div,
1578 unsigned *optimal_dclk_div);
1579int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1580 unsigned cg_upll_func_cntl);
771fe6b9 1581
b530602f 1582struct r600_audio_pin {
a92553ab
RM		 1583 int channels;
1584 int rate;
1585 int bits_per_sample;
1586 u8 status_bits;
1587 u8 category_code;
b530602f
AD		 1588 u32 offset;
1589 bool connected;
1590 u32 id;
1591};
1592
1593struct r600_audio {
1594 bool enabled;
1595 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1596 int num_pins;
a92553ab
RM		 1597};
1598
771fe6b9
JG		 1599/*
1600 * Benchmarking
1601 */
638dd7db 1602void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1603
1604
ecc0b326
MD		 1605/*
1606 * Testing
1607 */
1608void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1609void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1610 struct radeon_ring *cpA,
1611 struct radeon_ring *cpB);
60a7e396 1612void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1613
1614
771fe6b9
JG		 1615/*
1616 * Debugfs
1617 */
4d8bf9ae
CK		 1618struct radeon_debugfs {
1619 struct drm_info_list *files;
1620 unsigned num_files;
1621};
1622
771fe6b9
JG		 1623int radeon_debugfs_add_files(struct radeon_device *rdev,
1624 struct drm_info_list *files,
1625 unsigned nfiles);
1626int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1627
76a0df85
CK		 1628/*
1629 * ASIC ring specific functions.
1630 */
1631struct radeon_asic_ring {
1632 /* ring read/write ptr handling */
1633 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1634 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1635 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1636
1637 /* validating and patching of IBs */
1638 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1639 int (*cs_parse)(struct radeon_cs_parser *p);
1640
1641 /* command emmit functions */
1642 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1643 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1654b817 1644 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1645 struct radeon_semaphore *semaphore, bool emit_wait);
1646 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1647
1648 /* testing functions */
1649 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1650 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1651 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1652
1653 /* deprecated */
1654 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1655};
771fe6b9
JG		 1656
1657/*
1658 * ASIC specific functions.
1659 */
1660struct radeon_asic {
068a117c 1661 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1662 void (*fini)(struct radeon_device *rdev);
1663 int (*resume)(struct radeon_device *rdev);
1664 int (*suspend)(struct radeon_device *rdev);
28d52043 1665 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1666 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1667 /* ioctl hw specific callback. Some hw might want to perform special
1668 * operation on specific ioctl. For instance on wait idle some hw
1669 * might want to perform and HDP flush through MMIO as it seems that
1670 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1671 * through ring.
1672 */
1673 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1674 /* check if 3D engine is idle */
1675 bool (*gui_idle)(struct radeon_device *rdev);
1676 /* wait for mc_idle */
1677 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1678 /* get the reference clock */
1679 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1680 /* get the gpu clock counter */
1681 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1682 /* gart */
c5b3b850
AD		 1683 struct {
1684 void (*tlb_flush)(struct radeon_device *rdev);
1685 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1686 } gart;
05b07147
CK		 1687 struct {
1688 int (*init)(struct radeon_device *rdev);
1689 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1690 void (*set_page)(struct radeon_device *rdev,
1691 struct radeon_ib *ib,
1692 uint64_t pe,
dce34bfd
CK		 1693 uint64_t addr, unsigned count,
1694 uint32_t incr, uint32_t flags);
05b07147 1695 } vm;
54e88e06 1696 /* ring specific callbacks */
76a0df85 1697 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1698 /* irqs */
b35ea4ab
AD		 1699 struct {
1700 int (*set)(struct radeon_device *rdev);
1701 int (*process)(struct radeon_device *rdev);
1702 } irq;
54e88e06 1703 /* displays */
c79a49ca
AD		 1704 struct {
1705 /* display watermarks */
1706 void (*bandwidth_update)(struct radeon_device *rdev);
1707 /* get frame count */
1708 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1709 /* wait for vblank */
1710 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1711 /* set backlight level */
1712 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1713 /* get backlight level */
1714 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1715 /* audio callbacks */
1716 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1717 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1718 } display;
54e88e06 1719 /* copy functions for bo handling */
27cd7769
AD		 1720 struct {
1721 int (*blit)(struct radeon_device *rdev,
1722 uint64_t src_offset,
1723 uint64_t dst_offset,
1724 unsigned num_gpu_pages,
876dc9f3 1725 struct radeon_fence **fence);
27cd7769
AD		 1726 u32 blit_ring_index;
1727 int (*dma)(struct radeon_device *rdev,
1728 uint64_t src_offset,
1729 uint64_t dst_offset,
1730 unsigned num_gpu_pages,
876dc9f3 1731 struct radeon_fence **fence);
27cd7769
AD		 1732 u32 dma_ring_index;
1733 /* method used for bo copy */
1734 int (*copy)(struct radeon_device *rdev,
1735 uint64_t src_offset,
1736 uint64_t dst_offset,
1737 unsigned num_gpu_pages,
876dc9f3 1738 struct radeon_fence **fence);
27cd7769
AD		 1739 /* ring used for bo copies */
1740 u32 copy_ring_index;
1741 } copy;
54e88e06 1742 /* surfaces */
9e6f3d02
AD		 1743 struct {
1744 int (*set_reg)(struct radeon_device *rdev, int reg,
1745 uint32_t tiling_flags, uint32_t pitch,
1746 uint32_t offset, uint32_t obj_size);
1747 void (*clear_reg)(struct radeon_device *rdev, int reg);
1748 } surface;
54e88e06 1749 /* hotplug detect */
901ea57d
AD		 1750 struct {
1751 void (*init)(struct radeon_device *rdev);
1752 void (*fini)(struct radeon_device *rdev);
1753 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1754 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1755 } hpd;
da321c8a 1756 /* static power management */
a02fa397
AD		 1757 struct {
1758 void (*misc)(struct radeon_device *rdev);
1759 void (*prepare)(struct radeon_device *rdev);
1760 void (*finish)(struct radeon_device *rdev);
1761 void (*init_profile)(struct radeon_device *rdev);
1762 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1763 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1764 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1765 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1766 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1767 int (*get_pcie_lanes)(struct radeon_device *rdev);
1768 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1769 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1770 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1771 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1772 } pm;
da321c8a
AD		 1773 /* dynamic power management */
1774 struct {
1775 int (*init)(struct radeon_device *rdev);
1776 void (*setup_asic)(struct radeon_device *rdev);
1777 int (*enable)(struct radeon_device *rdev);
1778 void (*disable)(struct radeon_device *rdev);
84dd1928 1779 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1780 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1781 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1782 void (*display_configuration_changed)(struct radeon_device *rdev);
1783 void (*fini)(struct radeon_device *rdev);
1784 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1785 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1786 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1787 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1788 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1789 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1790 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1791 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1792 } dpm;
6f34be50 1793 /* pageflipping */
0f9e006c
AD		 1794 struct {
1795 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1796 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1797 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1798 } pflip;
771fe6b9
JG		 1799};
1800
21f9a437
JG		 1801/*
1802 * Asic structures
1803 */
551ebd83 1804struct r100_asic {
225758d8
JG		 1805 const unsigned *reg_safe_bm;
1806 unsigned reg_safe_bm_size;
1807 u32 hdp_cntl;
551ebd83
DA		 1808};
1809
21f9a437 1810struct r300_asic {
225758d8
JG		 1811 const unsigned *reg_safe_bm;
1812 unsigned reg_safe_bm_size;
1813 u32 resync_scratch;
1814 u32 hdp_cntl;
21f9a437
JG		 1815};
1816
1817struct r600_asic {
225758d8
JG		 1818 unsigned max_pipes;
1819 unsigned max_tile_pipes;
1820 unsigned max_simds;
1821 unsigned max_backends;
1822 unsigned max_gprs;
1823 unsigned max_threads;
1824 unsigned max_stack_entries;
1825 unsigned max_hw_contexts;
1826 unsigned max_gs_threads;
1827 unsigned sx_max_export_size;
1828 unsigned sx_max_export_pos_size;
1829 unsigned sx_max_export_smx_size;
1830 unsigned sq_num_cf_insts;
1831 unsigned tiling_nbanks;
1832 unsigned tiling_npipes;
1833 unsigned tiling_group_size;
e7aeeba6 1834 unsigned tile_config;
e55b9422 1835 unsigned backend_map;
21f9a437
JG		 1836};
1837
1838struct rv770_asic {
225758d8
JG		 1839 unsigned max_pipes;
1840 unsigned max_tile_pipes;
1841 unsigned max_simds;
1842 unsigned max_backends;
1843 unsigned max_gprs;
1844 unsigned max_threads;
1845 unsigned max_stack_entries;
1846 unsigned max_hw_contexts;
1847 unsigned max_gs_threads;
1848 unsigned sx_max_export_size;
1849 unsigned sx_max_export_pos_size;
1850 unsigned sx_max_export_smx_size;
1851 unsigned sq_num_cf_insts;
1852 unsigned sx_num_of_sets;
1853 unsigned sc_prim_fifo_size;
1854 unsigned sc_hiz_tile_fifo_size;
1855 unsigned sc_earlyz_tile_fifo_fize;
1856 unsigned tiling_nbanks;
1857 unsigned tiling_npipes;
1858 unsigned tiling_group_size;
e7aeeba6 1859 unsigned tile_config;
e55b9422 1860 unsigned backend_map;
21f9a437
JG		 1861};
1862
32fcdbf4
AD		 1863struct evergreen_asic {
1864 unsigned num_ses;
1865 unsigned max_pipes;
1866 unsigned max_tile_pipes;
1867 unsigned max_simds;
1868 unsigned max_backends;
1869 unsigned max_gprs;
1870 unsigned max_threads;
1871 unsigned max_stack_entries;
1872 unsigned max_hw_contexts;
1873 unsigned max_gs_threads;
1874 unsigned sx_max_export_size;
1875 unsigned sx_max_export_pos_size;
1876 unsigned sx_max_export_smx_size;
1877 unsigned sq_num_cf_insts;
1878 unsigned sx_num_of_sets;
1879 unsigned sc_prim_fifo_size;
1880 unsigned sc_hiz_tile_fifo_size;
1881 unsigned sc_earlyz_tile_fifo_size;
1882 unsigned tiling_nbanks;
1883 unsigned tiling_npipes;
1884 unsigned tiling_group_size;
e7aeeba6 1885 unsigned tile_config;
e55b9422 1886 unsigned backend_map;
32fcdbf4
AD		 1887};
1888
fecf1d07
AD		 1889struct cayman_asic {
1890 unsigned max_shader_engines;
1891 unsigned max_pipes_per_simd;
1892 unsigned max_tile_pipes;
1893 unsigned max_simds_per_se;
1894 unsigned max_backends_per_se;
1895 unsigned max_texture_channel_caches;
1896 unsigned max_gprs;
1897 unsigned max_threads;
1898 unsigned max_gs_threads;
1899 unsigned max_stack_entries;
1900 unsigned sx_num_of_sets;
1901 unsigned sx_max_export_size;
1902 unsigned sx_max_export_pos_size;
1903 unsigned sx_max_export_smx_size;
1904 unsigned max_hw_contexts;
1905 unsigned sq_num_cf_insts;
1906 unsigned sc_prim_fifo_size;
1907 unsigned sc_hiz_tile_fifo_size;
1908 unsigned sc_earlyz_tile_fifo_size;
1909
1910 unsigned num_shader_engines;
1911 unsigned num_shader_pipes_per_simd;
1912 unsigned num_tile_pipes;
1913 unsigned num_simds_per_se;
1914 unsigned num_backends_per_se;
1915 unsigned backend_disable_mask_per_asic;
1916 unsigned backend_map;
1917 unsigned num_texture_channel_caches;
1918 unsigned mem_max_burst_length_bytes;
1919 unsigned mem_row_size_in_kb;
1920 unsigned shader_engine_tile_size;
1921 unsigned num_gpus;
1922 unsigned multi_gpu_tile_size;
1923
1924 unsigned tile_config;
fecf1d07
AD		 1925};
1926
0a96d72b
AD		 1927struct si_asic {
1928 unsigned max_shader_engines;
0a96d72b 1929 unsigned max_tile_pipes;
1a8ca750
AD		 1930 unsigned max_cu_per_sh;
1931 unsigned max_sh_per_se;
0a96d72b
AD		 1932 unsigned max_backends_per_se;
1933 unsigned max_texture_channel_caches;
1934 unsigned max_gprs;
1935 unsigned max_gs_threads;
1936 unsigned max_hw_contexts;
1937 unsigned sc_prim_fifo_size_frontend;
1938 unsigned sc_prim_fifo_size_backend;
1939 unsigned sc_hiz_tile_fifo_size;
1940 unsigned sc_earlyz_tile_fifo_size;
1941
0a96d72b 1942 unsigned num_tile_pipes;
439a1cff 1943 unsigned backend_enable_mask;
0a96d72b
AD		 1944 unsigned backend_disable_mask_per_asic;
1945 unsigned backend_map;
1946 unsigned num_texture_channel_caches;
1947 unsigned mem_max_burst_length_bytes;
1948 unsigned mem_row_size_in_kb;
1949 unsigned shader_engine_tile_size;
1950 unsigned num_gpus;
1951 unsigned multi_gpu_tile_size;
1952
1953 unsigned tile_config;
64d7b8be 1954 uint32_t tile_mode_array[32];
0a96d72b
AD		 1955};
1956
8cc1a532
AD		 1957struct cik_asic {
1958 unsigned max_shader_engines;
1959 unsigned max_tile_pipes;
1960 unsigned max_cu_per_sh;
1961 unsigned max_sh_per_se;
1962 unsigned max_backends_per_se;
1963 unsigned max_texture_channel_caches;
1964 unsigned max_gprs;
1965 unsigned max_gs_threads;
1966 unsigned max_hw_contexts;
1967 unsigned sc_prim_fifo_size_frontend;
1968 unsigned sc_prim_fifo_size_backend;
1969 unsigned sc_hiz_tile_fifo_size;
1970 unsigned sc_earlyz_tile_fifo_size;
1971
1972 unsigned num_tile_pipes;
439a1cff 1973 unsigned backend_enable_mask;
8cc1a532
AD		 1974 unsigned backend_disable_mask_per_asic;
1975 unsigned backend_map;
1976 unsigned num_texture_channel_caches;
1977 unsigned mem_max_burst_length_bytes;
1978 unsigned mem_row_size_in_kb;
1979 unsigned shader_engine_tile_size;
1980 unsigned num_gpus;
1981 unsigned multi_gpu_tile_size;
1982
1983 unsigned tile_config;
39aee490 1984 uint32_t tile_mode_array[32];
32f79a8a 1985 uint32_t macrotile_mode_array[16];
8cc1a532
AD		 1986};
1987
068a117c
JG		 1988union radeon_asic_config {
1989 struct r300_asic r300;
551ebd83 1990 struct r100_asic r100;
3ce0a23d
JG		 1991 struct r600_asic r600;
1992 struct rv770_asic rv770;
32fcdbf4 1993 struct evergreen_asic evergreen;
fecf1d07 1994 struct cayman_asic cayman;
0a96d72b 1995 struct si_asic si;
8cc1a532 1996 struct cik_asic cik;
068a117c
JG		 1997};
1998
0a10c851
DV		 1999/*
2000 * asic initizalization from radeon_asic.c
2001 */
2002void radeon_agp_disable(struct radeon_device *rdev);
2003int radeon_asic_init(struct radeon_device *rdev);
2004
771fe6b9
JG		 2005
2006/*
2007 * IOCTL.
2008 */
2009int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2010 struct drm_file *filp);
2011int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2012 struct drm_file *filp);
2013int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2014 struct drm_file *file_priv);
2015int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2016 struct drm_file *file_priv);
2017int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2018 struct drm_file *file_priv);
2019int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2020 struct drm_file *file_priv);
2021int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2022 struct drm_file *filp);
2023int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2024 struct drm_file *filp);
2025int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2026 struct drm_file *filp);
2027int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2028 struct drm_file *filp);
721604a1
JG		 2029int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2030 struct drm_file *filp);
771fe6b9 2031int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2032int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2033 struct drm_file *filp);
2034int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2035 struct drm_file *filp);
771fe6b9 2036
16cdf04d
AD		 2037/* VRAM scratch page for HDP bug, default vram page */
2038struct r600_vram_scratch {
87cbf8f2
AD		 2039 struct radeon_bo *robj;
2040 volatile uint32_t *ptr;
16cdf04d 2041 u64 gpu_addr;
87cbf8f2 2042};
771fe6b9 2043
fd64ca8a
LT		 2044/*
2045 * ACPI
2046 */
2047struct radeon_atif_notification_cfg {
2048 bool enabled;
2049 int command_code;
2050};
2051
2052struct radeon_atif_notifications {
2053 bool display_switch;
2054 bool expansion_mode_change;
2055 bool thermal_state;
2056 bool forced_power_state;
2057 bool system_power_state;
2058 bool display_conf_change;
2059 bool px_gfx_switch;
2060 bool brightness_change;
2061 bool dgpu_display_event;
2062};
2063
2064struct radeon_atif_functions {
2065 bool system_params;
2066 bool sbios_requests;
2067 bool select_active_disp;
2068 bool lid_state;
2069 bool get_tv_standard;
2070 bool set_tv_standard;
2071 bool get_panel_expansion_mode;
2072 bool set_panel_expansion_mode;
2073 bool temperature_change;
2074 bool graphics_device_types;
2075};
2076
2077struct radeon_atif {
2078 struct radeon_atif_notifications notifications;
2079 struct radeon_atif_functions functions;
2080 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2081 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2082};
7a1619b9 2083
e3a15920
AD		 2084struct radeon_atcs_functions {
2085 bool get_ext_state;
2086 bool pcie_perf_req;
2087 bool pcie_dev_rdy;
2088 bool pcie_bus_width;
2089};
2090
2091struct radeon_atcs {
2092 struct radeon_atcs_functions functions;
2093};
2094
771fe6b9
JG		 2095/*
2096 * Core structure, functions and helpers.
2097 */
2098typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2099typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2100
2101struct radeon_device {
9f022ddf 2102 struct device *dev;
771fe6b9
JG		 2103 struct drm_device *ddev;
2104 struct pci_dev *pdev;
dee53e7f 2105 struct rw_semaphore exclusive_lock;
771fe6b9 2106 /* ASIC */
068a117c 2107 union radeon_asic_config config;
771fe6b9
JG		 2108 enum radeon_family family;
2109 unsigned long flags;
2110 int usec_timeout;
2111 enum radeon_pll_errata pll_errata;
2112 int num_gb_pipes;
f779b3e5 2113 int num_z_pipes;
771fe6b9
JG		 2114 int disp_priority;
2115 /* BIOS */
2116 uint8_t *bios;
2117 bool is_atom_bios;
2118 uint16_t bios_header_start;
4c788679 2119 struct radeon_bo *stollen_vga_memory;
771fe6b9 2120 /* Register mmio */
4c9bc75c
DA		 2121 resource_size_t rmmio_base;
2122 resource_size_t rmmio_size;
2c385151
DV		 2123 /* protects concurrent MM_INDEX/DATA based register access */
2124 spinlock_t mmio_idx_lock;
fe78118c
AD		 2125 /* protects concurrent SMC based register access */
2126 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2127 /* protects concurrent PLL register access */
2128 spinlock_t pll_idx_lock;
2129 /* protects concurrent MC register access */
2130 spinlock_t mc_idx_lock;
2131 /* protects concurrent PCIE register access */
2132 spinlock_t pcie_idx_lock;
2133 /* protects concurrent PCIE_PORT register access */
2134 spinlock_t pciep_idx_lock;
2135 /* protects concurrent PIF register access */
2136 spinlock_t pif_idx_lock;
2137 /* protects concurrent CG register access */
2138 spinlock_t cg_idx_lock;
2139 /* protects concurrent UVD register access */
2140 spinlock_t uvd_idx_lock;
2141 /* protects concurrent RCU register access */
2142 spinlock_t rcu_idx_lock;
2143 /* protects concurrent DIDT register access */
2144 spinlock_t didt_idx_lock;
2145 /* protects concurrent ENDPOINT (audio) register access */
2146 spinlock_t end_idx_lock;
a0533fbf 2147 void __iomem *rmmio;
771fe6b9
JG		 2148 radeon_rreg_t mc_rreg;
2149 radeon_wreg_t mc_wreg;
2150 radeon_rreg_t pll_rreg;
2151 radeon_wreg_t pll_wreg;
de1b2898 2152 uint32_t pcie_reg_mask;
771fe6b9
JG		 2153 radeon_rreg_t pciep_rreg;
2154 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2155 /* io port */
2156 void __iomem *rio_mem;
2157 resource_size_t rio_mem_size;
771fe6b9
JG		 2158 struct radeon_clock clock;
2159 struct radeon_mc mc;
2160 struct radeon_gart gart;
2161 struct radeon_mode_info mode_info;
2162 struct radeon_scratch scratch;
75efdee1 2163 struct radeon_doorbell doorbell;
771fe6b9 2164 struct radeon_mman mman;
7465280c 2165 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2166 wait_queue_head_t fence_queue;
d6999bc7 2167 struct mutex ring_lock;
e32eb50d 2168 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2169 bool ib_pool_ready;
2170 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2171 struct radeon_irq irq;
2172 struct radeon_asic *asic;
2173 struct radeon_gem gem;
c93bb85b 2174 struct radeon_pm pm;
f2ba57b5 2175 struct radeon_uvd uvd;
f657c2a7 2176 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2177 struct radeon_wb wb;
3ce0a23d 2178 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2179 bool shutdown;
2180 bool suspend;
ad49f501 2181 bool need_dma32;
733289c2 2182 bool accel_working;
a0a53aa8 2183 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2184 bool needs_reset;
e024e110 2185 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2186 const struct firmware *me_fw; /* all family ME firmware */
2187 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2188 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2189 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2190 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2191 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2192 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2193 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2194 const struct firmware *uvd_fw; /* UVD firmware */
16cdf04d 2195 struct r600_vram_scratch vram_scratch;
3e5cb98d 2196 int msi_enabled; /* msi enabled */
d8f60cfc 2197 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2198 struct radeon_rlc rlc;
963e81f9 2199 struct radeon_mec mec;
d4877cf2 2200 struct work_struct hotplug_work;
f122c610 2201 struct work_struct audio_work;
8f61b34c 2202 struct work_struct reset_work;
18917b60 2203 int num_crtc; /* number of crtcs */
40bacf16 2204 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2205 bool has_uvd;
b530602f 2206 struct r600_audio audio; /* audio stuff */
ce8f5370 2207 struct notifier_block acpi_nb;
9eba4a93 2208 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2209 struct drm_file *hyperz_filp;
9eba4a93 2210 struct drm_file *cmask_filp;
f376b94f
AD		 2211 /* i2c buses */
2212 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2213 /* debugfs */
2214 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2215 unsigned debugfs_count;
721604a1
JG		 2216 /* virtual memory */
2217 struct radeon_vm_manager vm_manager;
6759a0a7 2218 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2219 /* ACPI interface */
2220 struct radeon_atif atif;
e3a15920 2221 struct radeon_atcs atcs;
f61d5b46
AD		 2222 /* srbm instance registers */
2223 struct mutex srbm_mutex;
64d8a728
AD		 2224 /* clock, powergating flags */
2225 u32 cg_flags;
2226 u32 pg_flags;
10ebc0bc
DA		 2227
2228 struct dev_pm_domain vga_pm_domain;
2229 bool have_disp_power_ref;
771fe6b9
JG		 2230};
2231
2232int radeon_device_init(struct radeon_device *rdev,
2233 struct drm_device *ddev,
2234 struct pci_dev *pdev,
2235 uint32_t flags);
2236void radeon_device_fini(struct radeon_device *rdev);
2237int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2238
2ef9bdfe
DV		 2239uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2240 bool always_indirect);
2241void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2242 bool always_indirect);
6fcbef7a
AK		 2243u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2244void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2245
d5754ab8
AL		 2246u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2247void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2248
4c788679
JG		 2249/*
2250 * Cast helper
2251 */
2252#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2253
2254/*
2255 * Registers read & write functions.
2256 */
a0533fbf
BH		 2257#define RREG8(reg) readb((rdev->rmmio) + (reg))
2258#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2259#define RREG16(reg) readw((rdev->rmmio) + (reg))
2260#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2261#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2262#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2263#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2264#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2265#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2266#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2267#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2268#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2269#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2270#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2271#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2272#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2273#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2274#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2275#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2276#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2277#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2278#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2279#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2280#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2281#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2282#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2283#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2284#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2285#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2286#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2287#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2288#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2289#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2290#define WREG32_P(reg, val, mask) \
2291 do { \
2292 uint32_t tmp_ = RREG32(reg); \
2293 tmp_ &= (mask); \
2294 tmp_ |= ((val) & ~(mask)); \
2295 WREG32(reg, tmp_); \
2296 } while (0)
d5169fc4 2297#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2298#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2299#define WREG32_PLL_P(reg, val, mask) \
2300 do { \
2301 uint32_t tmp_ = RREG32_PLL(reg); \
2302 tmp_ &= (mask); \
2303 tmp_ |= ((val) & ~(mask)); \
2304 WREG32_PLL(reg, tmp_); \
2305 } while (0)
2ef9bdfe 2306#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2307#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2308#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2309
d5754ab8
AL		 2310#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2311#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2312
de1b2898
DA		 2313/*
2314 * Indirect registers accessor
2315 */
2316static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2317{
0a5b7b0b 2318 unsigned long flags;
de1b2898
DA		 2319 uint32_t r;
2320
0a5b7b0b 2321 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2322 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2323 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2324 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2325 return r;
2326}
2327
2328static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2329{
0a5b7b0b
AD		 2330 unsigned long flags;
2331
2332 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2333 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2334 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2335 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2336}
2337
1d5d0c34
AD		 2338static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2339{
fe78118c 2340 unsigned long flags;
1d5d0c34
AD		 2341 u32 r;
2342
fe78118c 2343 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2344 WREG32(TN_SMC_IND_INDEX_0, (reg));
2345 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2346 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2347 return r;
2348}
2349
2350static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2351{
fe78118c
AD		 2352 unsigned long flags;
2353
2354 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2355 WREG32(TN_SMC_IND_INDEX_0, (reg));
2356 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2357 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2358}
2359
ff82bbc4
AD		 2360static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2361{
0a5b7b0b 2362 unsigned long flags;
ff82bbc4
AD		 2363 u32 r;
2364
0a5b7b0b 2365 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2366 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2367 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2368 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2369 return r;
2370}
2371
2372static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2373{
0a5b7b0b
AD		 2374 unsigned long flags;
2375
2376 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2377 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2378 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2379 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2380}
2381
46f9564a
AD		 2382static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2383{
0a5b7b0b 2384 unsigned long flags;
46f9564a
AD		 2385 u32 r;
2386
0a5b7b0b 2387 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2388 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2389 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2390 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2391 return r;
2392}
2393
2394static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2395{
0a5b7b0b
AD		 2396 unsigned long flags;
2397
2398 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2399 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2400 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2401 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2402}
2403
792edd69
AD		 2404static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2405{
0a5b7b0b 2406 unsigned long flags;
792edd69
AD		 2407 u32 r;
2408
0a5b7b0b 2409 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2410 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2411 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2412 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2413 return r;
2414}
2415
2416static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2417{
0a5b7b0b
AD		 2418 unsigned long flags;
2419
2420 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2421 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2422 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2423 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2424}
2425
2426static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2427{
0a5b7b0b 2428 unsigned long flags;
792edd69
AD		 2429 u32 r;
2430
0a5b7b0b 2431 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2432 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2433 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2434 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2435 return r;
2436}
2437
2438static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2439{
0a5b7b0b
AD		 2440 unsigned long flags;
2441
2442 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2443 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2444 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2445 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2446}
2447
93656cdd
AD		 2448static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2449{
0a5b7b0b 2450 unsigned long flags;
93656cdd
AD		 2451 u32 r;
2452
0a5b7b0b 2453 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2454 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2455 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2456 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2457 return r;
2458}
2459
2460static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2461{
0a5b7b0b
AD		 2462 unsigned long flags;
2463
2464 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2465 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2466 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2467 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2468}
2469
1d58234d
AD		 2470
2471static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2472{
0a5b7b0b 2473 unsigned long flags;
1d58234d
AD		 2474 u32 r;
2475
0a5b7b0b 2476 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2477 WREG32(CIK_DIDT_IND_INDEX, (reg));
2478 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2479 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2480 return r;
2481}
2482
2483static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2484{
0a5b7b0b
AD		 2485 unsigned long flags;
2486
2487 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2488 WREG32(CIK_DIDT_IND_INDEX, (reg));
2489 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2490 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2491}
2492
771fe6b9
JG		 2493void r100_pll_errata_after_index(struct radeon_device *rdev);
2494
2495
2496/*
2497 * ASICs helpers.
2498 */
b995e433
DA		 2499#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2500 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2501#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2502 (rdev->family == CHIP_RV200) || \
2503 (rdev->family == CHIP_RS100) || \
2504 (rdev->family == CHIP_RS200) || \
2505 (rdev->family == CHIP_RV250) || \
2506 (rdev->family == CHIP_RV280) || \
2507 (rdev->family == CHIP_RS300))
2508#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2509 (rdev->family == CHIP_RV350) || \
2510 (rdev->family == CHIP_R350) || \
2511 (rdev->family == CHIP_RV380) || \
2512 (rdev->family == CHIP_R420) || \
2513 (rdev->family == CHIP_R423) || \
2514 (rdev->family == CHIP_RV410) || \
2515 (rdev->family == CHIP_RS400) || \
2516 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2517#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2518 (rdev->ddev->pdev->device == 0x9443) || \
2519 (rdev->ddev->pdev->device == 0x944B) || \
2520 (rdev->ddev->pdev->device == 0x9506) || \
2521 (rdev->ddev->pdev->device == 0x9509) || \
2522 (rdev->ddev->pdev->device == 0x950F) || \
2523 (rdev->ddev->pdev->device == 0x689C) || \
2524 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2525#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2526#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2527 (rdev->family == CHIP_RS690) || \
2528 (rdev->family == CHIP_RS740) || \
2529 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2530#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2531#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2532#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2533#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2534 (rdev->flags & RADEON_IS_IGP))
1fe18305 2535#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2536#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2537#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2538 (rdev->flags & RADEON_IS_IGP))
624d3524 2539#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2540#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2541#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2542
dc50ba7f
AD		 2543#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2544 (rdev->ddev->pdev->device == 0x6850) || \
2545 (rdev->ddev->pdev->device == 0x6858) || \
2546 (rdev->ddev->pdev->device == 0x6859) || \
2547 (rdev->ddev->pdev->device == 0x6840) || \
2548 (rdev->ddev->pdev->device == 0x6841) || \
2549 (rdev->ddev->pdev->device == 0x6842) || \
2550 (rdev->ddev->pdev->device == 0x6843))
2551
771fe6b9
JG		 2552/*
2553 * BIOS helpers.
2554 */
2555#define RBIOS8(i) (rdev->bios[i])
2556#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2557#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2558
2559int radeon_combios_init(struct radeon_device *rdev);
2560void radeon_combios_fini(struct radeon_device *rdev);
2561int radeon_atombios_init(struct radeon_device *rdev);
2562void radeon_atombios_fini(struct radeon_device *rdev);
2563
2564
2565/*
2566 * RING helpers.
2567 */
ce580fab 2568#if DRM_DEBUG_CODE == 0
e32eb50d 2569static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2570{
e32eb50d
CK		 2571 ring->ring[ring->wptr++] = v;
2572 ring->wptr &= ring->ptr_mask;
2573 ring->count_dw--;
2574 ring->ring_free_dw--;
771fe6b9 2575}
ce580fab
AK		 2576#else
2577/* With debugging this is just too big to inline */
e32eb50d 2578void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2579#endif
771fe6b9
JG		 2580
2581/*
2582 * ASICs macro.
2583 */
068a117c 2584#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2585#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2586#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2587#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2588#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2589#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2590#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2591#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2592#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2593#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2594#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2595#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2596#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2597#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2598#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2599#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2600#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2601#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2602#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2603#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2604#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2605#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2606#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2607#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2608#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2609#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2610#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2611#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2612#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2613#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2614#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2615#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2616#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2617#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2618#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2619#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2620#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2621#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2622#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2623#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2624#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2625#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2626#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2627#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2628#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2629#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2630#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2631#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2632#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2633#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2634#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2635#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2636#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2637#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2638#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2639#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2640#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2641#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2642#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2643#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2644#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2645#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2646#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2647#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2648#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2649#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2650#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2651#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2652#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2653#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2654#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2655#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2656#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2657#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2658#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2659#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2660#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2661#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2662#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2663#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2664#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2665#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2666#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2667
6cf8a3f5 2668/* Common functions */
700a0cc0 2669/* AGP */
90aca4d2 2670extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2671extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2672extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2673extern int radeon_modeset_init(struct radeon_device *rdev);
2674extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2675extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2676extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2677extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2678extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2679extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2680extern void radeon_wb_fini(struct radeon_device *rdev);
2681extern int radeon_wb_init(struct radeon_device *rdev);
2682extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2683extern void radeon_surface_init(struct radeon_device *rdev);
2684extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2685extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2686extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2687extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2688extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2689extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2690extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2691extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2692extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2693extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2694extern void radeon_program_register_sequence(struct radeon_device *rdev,
2695 const u32 *registers,
2696 const u32 array_size);
6cf8a3f5 2697
721604a1
JG		 2698/*
2699 * vm
2700 */
2701int radeon_vm_manager_init(struct radeon_device *rdev);
2702void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2703void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2704void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2705int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2706void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2707struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2708 struct radeon_vm *vm, int ring);
2709void radeon_vm_fence(struct radeon_device *rdev,
2710 struct radeon_vm *vm,
2711 struct radeon_fence *fence);
dce34bfd 2712uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
9c57a6bd
CK		 2713int radeon_vm_bo_update(struct radeon_device *rdev,
2714 struct radeon_vm *vm,
2715 struct radeon_bo *bo,
2716 struct ttm_mem_reg *mem);
721604a1
JG		 2717void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2718 struct radeon_bo *bo);
421ca7ab
CK		 2719struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2720 struct radeon_bo *bo);
e971bd5e
CK		 2721struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2722 struct radeon_vm *vm,
2723 struct radeon_bo *bo);
2724int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2725 struct radeon_bo_va *bo_va,
2726 uint64_t offset,
2727 uint32_t flags);
721604a1 2728int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2729 struct radeon_bo_va *bo_va);
721604a1 2730
f122c610
AD		 2731/* audio */
2732void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2733struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2734struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
721604a1 2735
16cdf04d
AD		 2736/*
2737 * R600 vram scratch functions
2738 */
2739int r600_vram_scratch_init(struct radeon_device *rdev);
2740void r600_vram_scratch_fini(struct radeon_device *rdev);
2741
285484e2
JG		 2742/*
2743 * r600 cs checking helper
2744 */
2745unsigned r600_mip_minify(unsigned size, unsigned level);
2746bool r600_fmt_is_valid_color(u32 format);
2747bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2748int r600_fmt_get_blocksize(u32 format);
2749int r600_fmt_get_nblocksx(u32 format, u32 w);
2750int r600_fmt_get_nblocksy(u32 format, u32 h);
2751
3574dda4
DV		 2752/*
2753 * r600 functions used by radeon_encoder.c
2754 */
1b688d08
RM		 2755struct radeon_hdmi_acr {
2756 u32 clock;
2757
2758 int n_32khz;
2759 int cts_32khz;
2760
2761 int n_44_1khz;
2762 int cts_44_1khz;
2763
2764 int n_48khz;
2765 int cts_48khz;
2766
2767};
2768
e55d3e6c
RM		 2769extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2770
416a2bd2
AD		 2771extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2772 u32 tiling_pipe_num,
2773 u32 max_rb_num,
2774 u32 total_max_rb_num,
2775 u32 enabled_rb_mask);
fe251e2f 2776
e55d3e6c
RM		 2777/*
2778 * evergreen functions used by radeon_encoder.c
2779 */
2780
0af62b01 2781extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2782extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2783
c4917074
AD		 2784/* radeon_acpi.c */
2785#if defined(CONFIG_ACPI)
2786extern int radeon_acpi_init(struct radeon_device *rdev);
2787extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2788extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2789extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2790 u8 perf_req, bool advertise);
dc50ba7f 2791extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2792#else
2793static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2794static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2795#endif
d7a2952f 2796
c38f34b5
IH		 2797int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2798 struct radeon_cs_packet *pkt,
2799 unsigned idx);
9ffb7a6d 2800bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2801void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2802 struct radeon_cs_packet *pkt);
e9716993
IH		 2803int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2804 struct radeon_cs_reloc **cs_reloc,
2805 int nomm);
40592a17
IH		 2806int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2807 uint32_t *vline_start_end,
2808 uint32_t *vline_status);
c38f34b5 2809
4c788679
JG		 2810#include "radeon_object.h"
2811
771fe6b9 2812#endif
Linux 6.x block layer and io_uring tree(s)