projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/msm: Remove CRTC .mode_set and .mode_set_base helpers
[linux-2.6-block.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
0aea5e4a 67#include <linux/interval_tree.h>
341cb9e4 68#include <linux/hashtable.h>
954605ca 69#include <linux/fence.h>
771fe6b9 70
4c788679
JG		 71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
147666fb 75#include <ttm/ttm_execbuf_util.h>
4c788679 76
d9fc9413
DV		 77#include <drm/drm_gem.h>
78
c2142715 79#include "radeon_family.h"
771fe6b9
JG		 80#include "radeon_mode.h"
81#include "radeon_reg.h"
771fe6b9
JG		 82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
ecc0b326 94extern int radeon_testing;
771fe6b9 95extern int radeon_connector_table;
4ce001ab 96extern int radeon_tv;
dafc3bd5 97extern int radeon_audio;
f46c0120 98extern int radeon_disp_priority;
e2b0a8e1 99extern int radeon_hw_i2c;
d42dd579 100extern int radeon_pcie_gen2;
a18cee15 101extern int radeon_msi;
3368ff0c 102extern int radeon_lockup_timeout;
a0a53aa8 103extern int radeon_fastfb;
da321c8a 104extern int radeon_dpm;
1294d4a3 105extern int radeon_aspm;
10ebc0bc 106extern int radeon_runtime_pm;
363eb0b4 107extern int radeon_hard_reset;
c1c44132 108extern int radeon_vm_size;
4510fb98 109extern int radeon_vm_block_size;
a624f429 110extern int radeon_deep_color;
39dc5454 111extern int radeon_use_pflipirq;
6e909f74 112extern int radeon_bapm;
bc13018b 113extern int radeon_backlight;
771fe6b9
JG		 114
115/*
116 * Copy from radeon_drv.h so we don't have to include both and have conflicting
117 * symbol;
118 */
bb635567
JG		 119#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
120#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 121/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 122#define RADEON_IB_POOL_SIZE 16
123#define RADEON_DEBUGFS_MAX_COMPONENTS 32
124#define RADEONFB_CONN_LIMIT 4
125#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 126
1b37078b
AD		 127/* internal ring indices */
128/* r1xx+ has gfx CP ring */
d93f7937 129#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 130
131/* cayman has 2 compute CP rings */
d93f7937
CK		 132#define CAYMAN_RING_TYPE_CP1_INDEX 1
133#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 134
4d75658b
AD		 135/* R600+ has an async dma ring */
136#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 137/* cayman add a second async dma ring */
138#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 139
f2ba57b5 140/* R600+ */
d93f7937
CK		 141#define R600_RING_TYPE_UVD_INDEX 5
142
143/* TN+ */
144#define TN_RING_TYPE_VCE1_INDEX 6
145#define TN_RING_TYPE_VCE2_INDEX 7
146
147/* max number of rings */
148#define RADEON_NUM_RINGS 8
f2ba57b5 149
1c61eae4
CK		 150/* number of hw syncs before falling back on blocking */
151#define RADEON_NUM_SYNCS 4
f2ba57b5 152
721604a1 153/* hardcode those limit for now */
ca19f21e 154#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 155#define RADEON_VA_RESERVED_SIZE (8 << 20)
156#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 157
1a0041b8
AD		 158/* hard reset data */
159#define RADEON_ASIC_RESET_DATA 0x39d5e86b
160
ec46c76d
AD		 161/* reset flags */
162#define RADEON_RESET_GFX (1 << 0)
163#define RADEON_RESET_COMPUTE (1 << 1)
164#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 165#define RADEON_RESET_CP (1 << 3)
166#define RADEON_RESET_GRBM (1 << 4)
167#define RADEON_RESET_DMA1 (1 << 5)
168#define RADEON_RESET_RLC (1 << 6)
169#define RADEON_RESET_SEM (1 << 7)
170#define RADEON_RESET_IH (1 << 8)
171#define RADEON_RESET_VMC (1 << 9)
172#define RADEON_RESET_MC (1 << 10)
173#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 174
22c775ce
AD		 175/* CG block flags */
176#define RADEON_CG_BLOCK_GFX (1 << 0)
177#define RADEON_CG_BLOCK_MC (1 << 1)
178#define RADEON_CG_BLOCK_SDMA (1 << 2)
179#define RADEON_CG_BLOCK_UVD (1 << 3)
180#define RADEON_CG_BLOCK_VCE (1 << 4)
181#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 182#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 183
64d8a728
AD		 184/* CG flags */
185#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
186#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
187#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
188#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
189#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
190#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
191#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
192#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
193#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
194#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
195#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
196#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
197#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
198#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
199#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
200#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
201#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
202
203/* PG flags */
2b19d17f 204#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 205#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
206#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
207#define RADEON_PG_SUPPORT_UVD (1 << 3)
208#define RADEON_PG_SUPPORT_VCE (1 << 4)
209#define RADEON_PG_SUPPORT_CP (1 << 5)
210#define RADEON_PG_SUPPORT_GDS (1 << 6)
211#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
212#define RADEON_PG_SUPPORT_SDMA (1 << 8)
213#define RADEON_PG_SUPPORT_ACP (1 << 9)
214#define RADEON_PG_SUPPORT_SAMU (1 << 10)
215
9e05fa1d
AD		 216/* max cursor sizes (in pixels) */
217#define CURSOR_WIDTH 64
218#define CURSOR_HEIGHT 64
219
220#define CIK_CURSOR_WIDTH 128
221#define CIK_CURSOR_HEIGHT 128
222
771fe6b9
JG		 223/*
224 * Errata workarounds.
225 */
226enum radeon_pll_errata {
227 CHIP_ERRATA_R300_CG = 0x00000001,
228 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
229 CHIP_ERRATA_PLL_DELAY = 0x00000004
230};
231
232
233struct radeon_device;
234
235
236/*
237 * BIOS.
238 */
239bool radeon_get_bios(struct radeon_device *rdev);
240
241/*
3ce0a23d 242 * Dummy page
771fe6b9 243 */
3ce0a23d 244struct radeon_dummy_page {
cb658906 245 uint64_t entry;
3ce0a23d
JG		 246 struct page *page;
247 dma_addr_t addr;
248};
249int radeon_dummy_page_init(struct radeon_device *rdev);
250void radeon_dummy_page_fini(struct radeon_device *rdev);
251
771fe6b9 252
3ce0a23d
JG		 253/*
254 * Clocks
255 */
771fe6b9
JG		 256struct radeon_clock {
257 struct radeon_pll p1pll;
258 struct radeon_pll p2pll;
bcc1c2a1 259 struct radeon_pll dcpll;
771fe6b9
JG		 260 struct radeon_pll spll;
261 struct radeon_pll mpll;
262 /* 10 Khz units */
263 uint32_t default_mclk;
264 uint32_t default_sclk;
bcc1c2a1 265 uint32_t default_dispclk;
4489cd62 266 uint32_t current_dispclk;
bcc1c2a1 267 uint32_t dp_extclk;
b20f9bef 268 uint32_t max_pixel_clock;
771fe6b9
JG		 269};
270
7433874e
RM		 271/*
272 * Power management
273 */
274int radeon_pm_init(struct radeon_device *rdev);
914a8987 275int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 276void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 277void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 278void radeon_pm_suspend(struct radeon_device *rdev);
279void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 280void radeon_combios_get_power_modes(struct radeon_device *rdev);
281void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 282int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
283 u8 clock_type,
284 u32 clock,
285 bool strobe_mode,
286 struct atom_clock_dividers *dividers);
eaa778af
AD		 287int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
288 u32 clock,
289 bool strobe_mode,
290 struct atom_mpll_param *mpll_param);
8a83ec5e 291void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 292int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
293 u16 voltage_level, u8 voltage_type,
294 u32 *gpio_value, u32 *gpio_mask);
295void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
296 u32 eng_clock, u32 mem_clock);
297int radeon_atom_get_voltage_step(struct radeon_device *rdev,
298 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 299int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
300 u16 voltage_id, u16 *voltage);
beb79f40
AD		 301int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
302 u16 *voltage,
303 u16 leakage_idx);
cc8dbbb4
AD		 304int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
305 u16 *leakage_id);
306int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
307 u16 *vddc, u16 *vddci,
308 u16 virtual_voltage_id,
309 u16 vbios_voltage_id);
e9f274b2
AD		 310int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
311 u16 virtual_voltage_id,
312 u16 *voltage);
ae5b0abb
AD		 313int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
314 u8 voltage_type,
315 u16 nominal_voltage,
316 u16 *true_voltage);
317int radeon_atom_get_min_voltage(struct radeon_device *rdev,
318 u8 voltage_type, u16 *min_voltage);
319int radeon_atom_get_max_voltage(struct radeon_device *rdev,
320 u8 voltage_type, u16 *max_voltage);
321int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 322 u8 voltage_type, u8 voltage_mode,
ae5b0abb 323 struct atom_voltage_table *voltage_table);
58653abd
AD		 324bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
325 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 326int radeon_atom_get_svi2_info(struct radeon_device *rdev,
327 u8 voltage_type,
328 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 329void radeon_atom_update_memory_dll(struct radeon_device *rdev,
330 u32 mem_clock);
331void radeon_atom_set_ac_timing(struct radeon_device *rdev,
332 u32 mem_clock);
333int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
334 u8 module_index,
335 struct atom_mc_reg_table *reg_table);
336int radeon_atom_get_memory_info(struct radeon_device *rdev,
337 u8 module_index, struct atom_memory_info *mem_info);
338int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
339 bool gddr5, u8 module_index,
340 struct atom_memory_clock_range_table *mclk_range_table);
341int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
342 u16 voltage_id, u16 *voltage);
f892034a 343void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 344extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
345 unsigned *bankh, unsigned *mtaspect,
346 unsigned *tile_split);
3ce0a23d 347
771fe6b9
JG		 348/*
349 * Fences.
350 */
351struct radeon_fence_driver {
0bfa4b41 352 struct radeon_device *rdev;
771fe6b9 353 uint32_t scratch_reg;
30eb77f4
JG		 354 uint64_t gpu_addr;
355 volatile uint32_t *cpu_addr;
68e250b7
CK		 356 /* sync_seq is protected by ring emission lock */
357 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 358 atomic64_t last_seq;
954605ca 359 bool initialized, delayed_irq;
0bfa4b41 360 struct delayed_work lockup_work;
771fe6b9
JG		 361};
362
363struct radeon_fence {
ad1a58a4 364 struct fence base;
954605ca 365
ad1a58a4
CK		 366 struct radeon_device *rdev;
367 uint64_t seq;
7465280c 368 /* RB, DMA, etc. */
ad1a58a4
CK		 369 unsigned ring;
370 bool is_vm_update;
954605ca 371
ad1a58a4 372 wait_queue_t fence_wake;
771fe6b9
JG		 373};
374
30eb77f4
JG		 375int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
376int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 377void radeon_fence_driver_fini(struct radeon_device *rdev);
eb98c709 378void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
876dc9f3 379int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 380void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 381bool radeon_fence_signaled(struct radeon_fence *fence);
382int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 383int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
384int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 385int radeon_fence_wait_any(struct radeon_device *rdev,
386 struct radeon_fence **fences,
387 bool intr);
771fe6b9
JG		 388struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
389void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 390unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 391bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
392void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
393static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
394 struct radeon_fence *b)
395{
396 if (!a) {
397 return b;
398 }
399
400 if (!b) {
401 return a;
402 }
403
404 BUG_ON(a->ring != b->ring);
405
406 if (a->seq > b->seq) {
407 return a;
408 } else {
409 return b;
410 }
411}
771fe6b9 412
ee60e29f
CK		 413static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
414 struct radeon_fence *b)
415{
416 if (!a) {
417 return false;
418 }
419
420 if (!b) {
421 return true;
422 }
423
424 BUG_ON(a->ring != b->ring);
425
426 return a->seq < b->seq;
427}
428
e024e110
DA		 429/*
430 * Tiling registers
431 */
432struct radeon_surface_reg {
4c788679 433 struct radeon_bo *bo;
e024e110
DA		 434};
435
436#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 437
438/*
4c788679 439 * TTM.
771fe6b9 440 */
4c788679
JG		 441struct radeon_mman {
442 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 443 struct drm_global_reference mem_global_ref;
4c788679 444 struct ttm_bo_device bdev;
0a0c7596
JG		 445 bool mem_global_referenced;
446 bool initialized;
2014b569
CK		 447
448#if defined(CONFIG_DEBUG_FS)
449 struct dentry *vram;
dd66d20e 450 struct dentry *gtt;
2014b569 451#endif
4c788679
JG		 452};
453
1d0c0942
CK		 454struct radeon_bo_list {
455 struct radeon_bo *robj;
456 struct ttm_validate_buffer tv;
457 uint64_t gpu_offset;
458 unsigned prefered_domains;
459 unsigned allowed_domains;
460 uint32_t tiling_flags;
461};
462
721604a1
JG		 463/* bo virtual address in a specific vm */
464struct radeon_bo_va {
e971bd5e 465 /* protected by bo being reserved */
721604a1 466 struct list_head bo_list;
721604a1 467 uint32_t flags;
e31ad969 468 uint64_t addr;
94214635 469 struct radeon_fence *last_pt_update;
e971bd5e
CK		 470 unsigned ref_count;
471
472 /* protected by vm mutex */
0aea5e4a 473 struct interval_tree_node it;
036bf46a 474 struct list_head vm_status;
e971bd5e
CK		 475
476 /* constant after initialization */
477 struct radeon_vm *vm;
478 struct radeon_bo *bo;
721604a1
JG		 479};
480
4c788679
JG		 481struct radeon_bo {
482 /* Protected by gem.mutex */
483 struct list_head list;
484 /* Protected by tbo.reserved */
bda72d58 485 u32 initial_domain;
c9da4a4b 486 struct ttm_place placements[4];
312ea8da 487 struct ttm_placement placement;
4c788679
JG		 488 struct ttm_buffer_object tbo;
489 struct ttm_bo_kmap_obj kmap;
02376d82 490 u32 flags;
4c788679
JG		 491 unsigned pin_count;
492 void *kptr;
493 u32 tiling_flags;
494 u32 pitch;
495 int surface_reg;
721604a1
JG		 496 /* list of all virtual address to which this bo
497 * is associated to
498 */
499 struct list_head va;
4c788679
JG		 500 /* Constant after initialization */
501 struct radeon_device *rdev;
441921d5 502 struct drm_gem_object gem_base;
63bc620b 503
409851f4
JG		 504 struct ttm_bo_kmap_obj dma_buf_vmap;
505 pid_t pid;
341cb9e4
CK		 506
507 struct radeon_mn *mn;
508 struct interval_tree_node mn_it;
4c788679 509};
7e4d15d9 510#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 511
409851f4
JG		 512int radeon_gem_debugfs_init(struct radeon_device *rdev);
513
b15ba512
JG		 514/* sub-allocation manager, it has to be protected by another lock.
515 * By conception this is an helper for other part of the driver
516 * like the indirect buffer or semaphore, which both have their
517 * locking.
518 *
519 * Principe is simple, we keep a list of sub allocation in offset
520 * order (first entry has offset == 0, last entry has the highest
521 * offset).
522 *
523 * When allocating new object we first check if there is room at
524 * the end total_size - (last_object_offset + last_object_size) >=
525 * alloc_size. If so we allocate new object there.
526 *
527 * When there is not enough room at the end, we start waiting for
528 * each sub object until we reach object_offset+object_size >=
529 * alloc_size, this object then become the sub object we return.
530 *
531 * Alignment can't be bigger than page size.
532 *
533 * Hole are not considered for allocation to keep things simple.
534 * Assumption is that there won't be hole (all object on same
535 * alignment).
536 */
537struct radeon_sa_manager {
bfb38d35 538 wait_queue_head_t wq;
b15ba512 539 struct radeon_bo *bo;
c3b7fe8b
CK		 540 struct list_head *hole;
541 struct list_head flist[RADEON_NUM_RINGS];
542 struct list_head olist;
b15ba512
JG		 543 unsigned size;
544 uint64_t gpu_addr;
545 void *cpu_ptr;
546 uint32_t domain;
6c4f978b 547 uint32_t align;
b15ba512
JG		 548};
549
550struct radeon_sa_bo;
551
552/* sub-allocation buffer */
553struct radeon_sa_bo {
c3b7fe8b
CK		 554 struct list_head olist;
555 struct list_head flist;
b15ba512 556 struct radeon_sa_manager *manager;
e6661a96
CK		 557 unsigned soffset;
558 unsigned eoffset;
557017a0 559 struct radeon_fence *fence;
b15ba512
JG		 560};
561
771fe6b9
JG		 562/*
563 * GEM objects.
564 */
565struct radeon_gem {
4c788679 566 struct mutex mutex;
771fe6b9
JG		 567 struct list_head objects;
568};
569
570int radeon_gem_init(struct radeon_device *rdev);
571void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 572int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 573 int alignment, int initial_domain,
ed5cb43f 574 u32 flags, bool kernel,
4c788679 575 struct drm_gem_object **obj);
771fe6b9 576
ff72145b
DA		 577int radeon_mode_dumb_create(struct drm_file *file_priv,
578 struct drm_device *dev,
579 struct drm_mode_create_dumb *args);
580int radeon_mode_dumb_mmap(struct drm_file *filp,
581 struct drm_device *dev,
582 uint32_t handle, uint64_t *offset_p);
771fe6b9 583
c1341e52
JG		 584/*
585 * Semaphores.
586 */
c1341e52 587struct radeon_semaphore {
975700d2
CK		 588 struct radeon_sa_bo *sa_bo;
589 signed waiters;
590 uint64_t gpu_addr;
c1341e52
JG		 591};
592
c1341e52
JG		 593int radeon_semaphore_create(struct radeon_device *rdev,
594 struct radeon_semaphore **semaphore);
1654b817 595bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 596 struct radeon_semaphore *semaphore);
1654b817 597bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52
JG		 598 struct radeon_semaphore *semaphore);
599void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 600 struct radeon_semaphore **semaphore,
a8c05940 601 struct radeon_fence *fence);
c1341e52 602
975700d2
CK		 603/*
604 * Synchronization
605 */
606struct radeon_sync {
607 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
608 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
ad1a58a4 609 struct radeon_fence *last_vm_update;
975700d2
CK		 610};
611
612void radeon_sync_create(struct radeon_sync *sync);
613void radeon_sync_fence(struct radeon_sync *sync,
614 struct radeon_fence *fence);
615int radeon_sync_resv(struct radeon_device *rdev,
616 struct radeon_sync *sync,
617 struct reservation_object *resv,
618 bool shared);
619int radeon_sync_rings(struct radeon_device *rdev,
620 struct radeon_sync *sync,
621 int waiting_ring);
622void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
623 struct radeon_fence *fence);
624
771fe6b9
JG		 625/*
626 * GART structures, functions & helpers
627 */
628struct radeon_mc;
629
a77f1718 630#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 631#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 632#define RADEON_GPU_PAGE_SHIFT 12
721604a1 633#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 634
77497f27
MD		 635#define RADEON_GART_PAGE_DUMMY 0
636#define RADEON_GART_PAGE_VALID (1 << 0)
637#define RADEON_GART_PAGE_READ (1 << 1)
638#define RADEON_GART_PAGE_WRITE (1 << 2)
639#define RADEON_GART_PAGE_SNOOP (1 << 3)
640
771fe6b9
JG		 641struct radeon_gart {
642 dma_addr_t table_addr;
c9a1be96
JG		 643 struct radeon_bo *robj;
644 void *ptr;
771fe6b9
JG		 645 unsigned num_gpu_pages;
646 unsigned num_cpu_pages;
647 unsigned table_size;
771fe6b9 648 struct page **pages;
cb658906 649 uint64_t *pages_entry;
771fe6b9
JG		 650 bool ready;
651};
652
653int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
654void radeon_gart_table_ram_free(struct radeon_device *rdev);
655int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
656void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 657int radeon_gart_table_vram_pin(struct radeon_device *rdev);
658void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 659int radeon_gart_init(struct radeon_device *rdev);
660void radeon_gart_fini(struct radeon_device *rdev);
661void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
662 int pages);
663int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 664 int pages, struct page **pagelist,
77497f27 665 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 666
667
668/*
669 * GPU MC structures, functions & helpers
670 */
671struct radeon_mc {
672 resource_size_t aper_size;
673 resource_size_t aper_base;
674 resource_size_t agp_base;
7a50f01a
DA		 675 /* for some chips with <= 32MB we need to lie
676 * about vram size near mc fb location */
3ce0a23d 677 u64 mc_vram_size;
d594e46a 678 u64 visible_vram_size;
3ce0a23d
JG		 679 u64 gtt_size;
680 u64 gtt_start;
681 u64 gtt_end;
3ce0a23d
JG		 682 u64 vram_start;
683 u64 vram_end;
771fe6b9 684 unsigned vram_width;
3ce0a23d 685 u64 real_vram_size;
771fe6b9
JG		 686 int vram_mtrr;
687 bool vram_is_ddr;
d594e46a 688 bool igp_sideport_enabled;
8d369bb1 689 u64 gtt_base_align;
9ed8b1f9 690 u64 mc_mask;
771fe6b9
JG		 691};
692
06b6476d
AD		 693bool radeon_combios_sideport_present(struct radeon_device *rdev);
694bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 695
696/*
697 * GPU scratch registers structures, functions & helpers
698 */
699struct radeon_scratch {
700 unsigned num_reg;
724c80e1 701 uint32_t reg_base;
771fe6b9
JG		 702 bool free[32];
703 uint32_t reg[32];
704};
705
706int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
707void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
708
75efdee1
AD		 709/*
710 * GPU doorbell structures, functions & helpers
711 */
d5754ab8
AL		 712#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
713
75efdee1 714struct radeon_doorbell {
75efdee1 715 /* doorbell mmio */
d5754ab8
AL		 716 resource_size_t base;
717 resource_size_t size;
718 u32 __iomem *ptr;
719 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
720 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 721};
722
723int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
724void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
ebff8453
OG		 725void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
726 phys_addr_t *aperture_base,
727 size_t *aperture_size,
728 size_t *start_offset);
771fe6b9
JG		 729
730/*
731 * IRQS.
732 */
6f34be50 733
fa7f517c
CK		 734struct radeon_flip_work {
735 struct work_struct flip_work;
736 struct work_struct unpin_work;
737 struct radeon_device *rdev;
738 int crtc_id;
c60381bd 739 uint64_t base;
6f34be50 740 struct drm_pending_vblank_event *event;
fa7f517c 741 struct radeon_bo *old_rbo;
a0e84764 742 struct fence *fence;
6f34be50
AD		 743};
744
745struct r500_irq_stat_regs {
746 u32 disp_int;
f122c610 747 u32 hdmi0_status;
6f34be50
AD		 748};
749
750struct r600_irq_stat_regs {
751 u32 disp_int;
752 u32 disp_int_cont;
753 u32 disp_int_cont2;
754 u32 d1grph_int;
755 u32 d2grph_int;
f122c610
AD		 756 u32 hdmi0_status;
757 u32 hdmi1_status;
6f34be50
AD		 758};
759
760struct evergreen_irq_stat_regs {
761 u32 disp_int;
762 u32 disp_int_cont;
763 u32 disp_int_cont2;
764 u32 disp_int_cont3;
765 u32 disp_int_cont4;
766 u32 disp_int_cont5;
767 u32 d1grph_int;
768 u32 d2grph_int;
769 u32 d3grph_int;
770 u32 d4grph_int;
771 u32 d5grph_int;
772 u32 d6grph_int;
f122c610
AD		 773 u32 afmt_status1;
774 u32 afmt_status2;
775 u32 afmt_status3;
776 u32 afmt_status4;
777 u32 afmt_status5;
778 u32 afmt_status6;
6f34be50
AD		 779};
780
a59781bb
AD		 781struct cik_irq_stat_regs {
782 u32 disp_int;
783 u32 disp_int_cont;
784 u32 disp_int_cont2;
785 u32 disp_int_cont3;
786 u32 disp_int_cont4;
787 u32 disp_int_cont5;
788 u32 disp_int_cont6;
f5d636d2
CK		 789 u32 d1grph_int;
790 u32 d2grph_int;
791 u32 d3grph_int;
792 u32 d4grph_int;
793 u32 d5grph_int;
794 u32 d6grph_int;
a59781bb
AD		 795};
796
6f34be50
AD		 797union radeon_irq_stat_regs {
798 struct r500_irq_stat_regs r500;
799 struct r600_irq_stat_regs r600;
800 struct evergreen_irq_stat_regs evergreen;
a59781bb 801 struct cik_irq_stat_regs cik;
6f34be50
AD		 802};
803
771fe6b9 804struct radeon_irq {
fb98257a
CK		 805 bool installed;
806 spinlock_t lock;
736fc37f 807 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 808 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 809 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 810 wait_queue_head_t vblank_queue;
811 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 812 bool afmt[RADEON_MAX_AFMT_BLOCKS];
813 union radeon_irq_stat_regs stat_regs;
4a6369e9 814 bool dpm_thermal;
771fe6b9
JG		 815};
816
817int radeon_irq_kms_init(struct radeon_device *rdev);
818void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b 819void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
954605ca 820bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
1b37078b 821void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 822void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
823void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 824void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
825void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
826void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
827void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 828
829/*
e32eb50d 830 * CP & rings.
771fe6b9 831 */
7465280c 832
771fe6b9 833struct radeon_ib {
68470ae7
JG		 834 struct radeon_sa_bo *sa_bo;
835 uint32_t length_dw;
836 uint64_t gpu_addr;
837 uint32_t *ptr;
876dc9f3 838 int ring;
68470ae7 839 struct radeon_fence *fence;
4bf3dd92 840 struct radeon_vm *vm;
68470ae7 841 bool is_const_ib;
975700d2 842 struct radeon_sync sync;
771fe6b9
JG		 843};
844
e32eb50d 845struct radeon_ring {
4c788679 846 struct radeon_bo *ring_obj;
771fe6b9 847 volatile uint32_t *ring;
5596a9db 848 unsigned rptr_offs;
45df6803 849 unsigned rptr_save_reg;
89d35807
AD		 850 u64 next_rptr_gpu_addr;
851 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 852 unsigned wptr;
853 unsigned wptr_old;
854 unsigned ring_size;
855 unsigned ring_free_dw;
856 int count_dw;
aee4aa73
CK		 857 atomic_t last_rptr;
858 atomic64_t last_activity;
771fe6b9
JG		 859 uint64_t gpu_addr;
860 uint32_t align_mask;
861 uint32_t ptr_mask;
771fe6b9 862 bool ready;
78c5560a 863 u32 nop;
8b25ed34 864 u32 idx;
5f0839c1
JG		 865 u64 last_semaphore_signal_addr;
866 u64 last_semaphore_wait_addr;
963e81f9
AD		 867 /* for CIK queues */
868 u32 me;
869 u32 pipe;
870 u32 queue;
871 struct radeon_bo *mqd_obj;
d5754ab8 872 u32 doorbell_index;
963e81f9
AD		 873 unsigned wptr_offs;
874};
875
876struct radeon_mec {
877 struct radeon_bo *hpd_eop_obj;
878 u64 hpd_eop_gpu_addr;
879 u32 num_pipe;
880 u32 num_mec;
881 u32 num_queue;
771fe6b9
JG		 882};
883
721604a1
JG		 884/*
885 * VM
886 */
ee60e29f 887
fa87e62d 888/* maximum number of VMIDs */
ee60e29f
CK		 889#define RADEON_NUM_VM 16
890
fa87e62d 891/* number of entries in page table */
4510fb98 892#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 893
1c01103c
AD		 894/* PTBs (Page Table Blocks) need to be aligned to 32K */
895#define RADEON_VM_PTB_ALIGN_SIZE 32768
896#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
897#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
898
24c16439
CK		 899#define R600_PTE_VALID (1 << 0)
900#define R600_PTE_SYSTEM (1 << 1)
901#define R600_PTE_SNOOPED (1 << 2)
902#define R600_PTE_READABLE (1 << 5)
903#define R600_PTE_WRITEABLE (1 << 6)
904
ec3dbbcb
CK		 905/* PTE (Page Table Entry) fragment field for different page sizes */
906#define R600_PTE_FRAG_4KB (0 << 7)
907#define R600_PTE_FRAG_64KB (4 << 7)
908#define R600_PTE_FRAG_256KB (6 << 7)
909
33fa9fe3
CK		 910/* flags needed to be set so we can copy directly from the GART table */
911#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
912 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 913
6d2f2944
CK		 914struct radeon_vm_pt {
915 struct radeon_bo *bo;
916 uint64_t addr;
917};
918
7c42bc1a
CK		 919struct radeon_vm_id {
920 unsigned id;
921 uint64_t pd_gpu_addr;
922 /* last flushed PD/PT update */
923 struct radeon_fence *flushed_updates;
924 /* last use of vmid */
925 struct radeon_fence *last_id_use;
926};
927
721604a1 928struct radeon_vm {
94214635
CK		 929 struct mutex mutex;
930
7c42bc1a 931 struct rb_root va;
90a51a32 932
f7a3db75
CK		 933 /* protecting invalidated and freed */
934 spinlock_t status_lock;
935
e31ad969 936 /* BOs moved, but not yet updated in the PT */
7c42bc1a 937 struct list_head invalidated;
e31ad969 938
036bf46a 939 /* BOs freed, but not yet updated in the PT */
7c42bc1a 940 struct list_head freed;
036bf46a 941
90a51a32 942 /* contains the page directory */
7c42bc1a
CK		 943 struct radeon_bo *page_directory;
944 unsigned max_pde_used;
90a51a32
CK		 945
946 /* array of page tables, one for each page directory entry */
7c42bc1a 947 struct radeon_vm_pt *page_tables;
90a51a32 948
7c42bc1a 949 struct radeon_bo_va *ib_bo_va;
cc9e67e3 950
7c42bc1a
CK		 951 /* for id and flush management per ring */
952 struct radeon_vm_id ids[RADEON_NUM_RINGS];
721604a1
JG		 953};
954
721604a1 955struct radeon_vm_manager {
ee60e29f 956 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 957 uint32_t max_pfn;
721604a1
JG		 958 /* number of VMIDs */
959 unsigned nvm;
960 /* vram base address for page table entry */
961 u64 vram_base_offset;
67e915e4
AD		 962 /* is vm enabled? */
963 bool enabled;
054e01d6
CK		 964 /* for hw to save the PD addr on suspend/resume */
965 uint32_t saved_table_addr[RADEON_NUM_VM];
721604a1
JG		 966};
967
968/*
969 * file private structure
970 */
971struct radeon_fpriv {
972 struct radeon_vm vm;
973};
974
d8f60cfc
AD		 975/*
976 * R6xx+ IH ring
977 */
978struct r600_ih {
4c788679 979 struct radeon_bo *ring_obj;
d8f60cfc
AD		 980 volatile uint32_t *ring;
981 unsigned rptr;
d8f60cfc
AD		 982 unsigned ring_size;
983 uint64_t gpu_addr;
d8f60cfc 984 uint32_t ptr_mask;
c20dc369 985 atomic_t lock;
d8f60cfc
AD		 986 bool enabled;
987};
988
347e7592 989/*
2948f5e6 990 * RLC stuff
347e7592 991 */
2948f5e6
AD		 992#include "clearstate_defs.h"
993
994struct radeon_rlc {
347e7592
AD		 995 /* for power gating */
996 struct radeon_bo *save_restore_obj;
997 uint64_t save_restore_gpu_addr;
2948f5e6 998 volatile uint32_t *sr_ptr;
1fd11777 999 const u32 *reg_list;
2948f5e6 1000 u32 reg_list_size;
347e7592
AD		 1001 /* for clear state */
1002 struct radeon_bo *clear_state_obj;
1003 uint64_t clear_state_gpu_addr;
2948f5e6 1004 volatile uint32_t *cs_ptr;
1fd11777 1005 const struct cs_section_def *cs_data;
22c775ce
AD		 1006 u32 clear_state_size;
1007 /* for cp tables */
1008 struct radeon_bo *cp_table_obj;
1009 uint64_t cp_table_gpu_addr;
1010 volatile uint32_t *cp_table_ptr;
1011 u32 cp_table_size;
347e7592
AD		 1012};
1013
69e130a6 1014int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 1015 struct radeon_ib *ib, struct radeon_vm *vm,
1016 unsigned size);
f2e39221 1017void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566 1018int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1538a9e0 1019 struct radeon_ib *const_ib, bool hdp_flush);
771fe6b9
JG		 1020int radeon_ib_pool_init(struct radeon_device *rdev);
1021void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 1022int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 1023/* Ring access between begin & end cannot sleep */
89d35807
AD		 1024bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1025 struct radeon_ring *ring);
e32eb50d
CK		 1026void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1027int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1028int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1538a9e0
MD		 1029void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1030 bool hdp_flush);
1031void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1032 bool hdp_flush);
d6999bc7 1033void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 1034void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1035int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 1036void radeon_ring_lockup_update(struct radeon_device *rdev,
1037 struct radeon_ring *ring);
069211e5 1038bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 1039unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1040 uint32_t **data);
1041int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1042 unsigned size, uint32_t *data);
e32eb50d 1043int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 1044 unsigned rptr_offs, u32 nop);
e32eb50d 1045void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 1046
1047
4d75658b
AD		 1048/* r600 async dma */
1049void r600_dma_stop(struct radeon_device *rdev);
1050int r600_dma_resume(struct radeon_device *rdev);
1051void r600_dma_fini(struct radeon_device *rdev);
1052
8c5fd7ef
AD		 1053void cayman_dma_stop(struct radeon_device *rdev);
1054int cayman_dma_resume(struct radeon_device *rdev);
1055void cayman_dma_fini(struct radeon_device *rdev);
1056
771fe6b9
JG		 1057/*
1058 * CS.
1059 */
771fe6b9 1060struct radeon_cs_chunk {
771fe6b9
JG		 1061 uint32_t length_dw;
1062 uint32_t *kdata;
721604a1 1063 void __user *user_ptr;
771fe6b9
JG		 1064};
1065
1066struct radeon_cs_parser {
c8c15ff1 1067 struct device *dev;
771fe6b9
JG		 1068 struct radeon_device *rdev;
1069 struct drm_file *filp;
1070 /* chunks */
1071 unsigned nchunks;
1072 struct radeon_cs_chunk *chunks;
1073 uint64_t *chunks_array;
1074 /* IB */
1075 unsigned idx;
1076 /* relocations */
1077 unsigned nrelocs;
1d0c0942 1078 struct radeon_bo_list *relocs;
1d0c0942 1079 struct radeon_bo_list *vm_bos;
771fe6b9 1080 struct list_head validated;
cf4ccd01 1081 unsigned dma_reloc_idx;
771fe6b9 1082 /* indices of various chunks */
6d2d13dd
CK		 1083 struct radeon_cs_chunk *chunk_ib;
1084 struct radeon_cs_chunk *chunk_relocs;
1085 struct radeon_cs_chunk *chunk_flags;
1086 struct radeon_cs_chunk *chunk_const_ib;
f2e39221
JG		 1087 struct radeon_ib ib;
1088 struct radeon_ib const_ib;
771fe6b9 1089 void *track;
3ce0a23d 1090 unsigned family;
e70f224c 1091 int parser_error;
721604a1
JG		 1092 u32 cs_flags;
1093 u32 ring;
1094 s32 priority;
ecff665f 1095 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1096};
1097
28a326c5
ML		 1098static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1099{
6d2d13dd 1100 struct radeon_cs_chunk *ibc = p->chunk_ib;
28a326c5
ML		 1101
1102 if (ibc->kdata)
1103 return ibc->kdata[idx];
1104 return p->ib.ptr[idx];
1105}
1106
513bcb46 1107
771fe6b9
JG		 1108struct radeon_cs_packet {
1109 unsigned idx;
1110 unsigned type;
1111 unsigned reg;
1112 unsigned opcode;
1113 int count;
1114 unsigned one_reg_wr;
1115};
1116
1117typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1118 struct radeon_cs_packet *pkt,
1119 unsigned idx, unsigned reg);
1120typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1121 struct radeon_cs_packet *pkt);
1122
1123
1124/*
1125 * AGP
1126 */
1127int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1128void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1129void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1130void radeon_agp_fini(struct radeon_device *rdev);
1131
1132
1133/*
1134 * Writeback
1135 */
1136struct radeon_wb {
4c788679 1137 struct radeon_bo *wb_obj;
771fe6b9
JG		 1138 volatile uint32_t *wb;
1139 uint64_t gpu_addr;
724c80e1 1140 bool enabled;
d0f8a854 1141 bool use_event;
771fe6b9
JG		 1142};
1143
724c80e1 1144#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1145#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1146#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1147#define RADEON_WB_CP1_RPTR_OFFSET 1280
1148#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1149#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1150#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1151#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1152#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1153#define CIK_WB_CP1_WPTR_OFFSET 3328
1154#define CIK_WB_CP2_WPTR_OFFSET 3584
adfed2b0
AD		 1155#define R600_WB_DMA_RING_TEST_OFFSET 3588
1156#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
724c80e1 1157
c93bb85b
JG		 1158/**
1159 * struct radeon_pm - power management datas
1160 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1161 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1162 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1163 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1164 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1165 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1166 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1167 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1168 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1169 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1170 * @needed_bandwidth: current bandwidth needs
1171 *
1172 * It keeps track of various data needed to take powermanagement decision.
25985edc 1173 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1174 * Equation between gpu/memory clock and available bandwidth is hw dependent
1175 * (type of memory, bus size, efficiency, ...)
1176 */
ce8f5370
AD		 1177
1178enum radeon_pm_method {
1179 PM_METHOD_PROFILE,
1180 PM_METHOD_DYNPM,
da321c8a 1181 PM_METHOD_DPM,
ce8f5370
AD		 1182};
1183
1184enum radeon_dynpm_state {
1185 DYNPM_STATE_DISABLED,
1186 DYNPM_STATE_MINIMUM,
1187 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1188 DYNPM_STATE_ACTIVE,
1189 DYNPM_STATE_SUSPENDED,
c913e23a 1190};
ce8f5370
AD		 1191enum radeon_dynpm_action {
1192 DYNPM_ACTION_NONE,
1193 DYNPM_ACTION_MINIMUM,
1194 DYNPM_ACTION_DOWNCLOCK,
1195 DYNPM_ACTION_UPCLOCK,
1196 DYNPM_ACTION_DEFAULT
c913e23a 1197};
56278a8e
AD		 1198
1199enum radeon_voltage_type {
1200 VOLTAGE_NONE = 0,
1201 VOLTAGE_GPIO,
1202 VOLTAGE_VDDC,
1203 VOLTAGE_SW
1204};
1205
0ec0e74f 1206enum radeon_pm_state_type {
da321c8a 1207 /* not used for dpm */
0ec0e74f
AD		 1208 POWER_STATE_TYPE_DEFAULT,
1209 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1210 /* user selectable states */
0ec0e74f
AD		 1211 POWER_STATE_TYPE_BATTERY,
1212 POWER_STATE_TYPE_BALANCED,
1213 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1214 /* internal states */
1215 POWER_STATE_TYPE_INTERNAL_UVD,
1216 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1217 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1218 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1219 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1220 POWER_STATE_TYPE_INTERNAL_BOOT,
1221 POWER_STATE_TYPE_INTERNAL_THERMAL,
1222 POWER_STATE_TYPE_INTERNAL_ACPI,
1223 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1224 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1225};
1226
ce8f5370
AD		 1227enum radeon_pm_profile_type {
1228 PM_PROFILE_DEFAULT,
1229 PM_PROFILE_AUTO,
1230 PM_PROFILE_LOW,
c9e75b21 1231 PM_PROFILE_MID,
ce8f5370
AD		 1232 PM_PROFILE_HIGH,
1233};
1234
1235#define PM_PROFILE_DEFAULT_IDX 0
1236#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1237#define PM_PROFILE_MID_SH_IDX 2
1238#define PM_PROFILE_HIGH_SH_IDX 3
1239#define PM_PROFILE_LOW_MH_IDX 4
1240#define PM_PROFILE_MID_MH_IDX 5
1241#define PM_PROFILE_HIGH_MH_IDX 6
1242#define PM_PROFILE_MAX 7
ce8f5370
AD		 1243
1244struct radeon_pm_profile {
1245 int dpms_off_ps_idx;
1246 int dpms_on_ps_idx;
1247 int dpms_off_cm_idx;
1248 int dpms_on_cm_idx;
516d0e46
AD		 1249};
1250
21a8122a
AD		 1251enum radeon_int_thermal_type {
1252 THERMAL_TYPE_NONE,
da321c8a
AD		 1253 THERMAL_TYPE_EXTERNAL,
1254 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1255 THERMAL_TYPE_RV6XX,
1256 THERMAL_TYPE_RV770,
da321c8a 1257 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1258 THERMAL_TYPE_EVERGREEN,
e33df25f 1259 THERMAL_TYPE_SUMO,
4fddba1f 1260 THERMAL_TYPE_NI,
14607d08 1261 THERMAL_TYPE_SI,
da321c8a 1262 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1263 THERMAL_TYPE_CI,
16fbe00d 1264 THERMAL_TYPE_KV,
21a8122a
AD		 1265};
1266
56278a8e
AD		 1267struct radeon_voltage {
1268 enum radeon_voltage_type type;
1269 /* gpio voltage */
1270 struct radeon_gpio_rec gpio;
1271 u32 delay; /* delay in usec from voltage drop to sclk change */
1272 bool active_high; /* voltage drop is active when bit is high */
1273 /* VDDC voltage */
1274 u8 vddc_id; /* index into vddc voltage table */
1275 u8 vddci_id; /* index into vddci voltage table */
1276 bool vddci_enabled;
1277 /* r6xx+ sw */
2feea49a
AD		 1278 u16 voltage;
1279 /* evergreen+ vddci */
1280 u16 vddci;
56278a8e
AD		 1281};
1282
d7311171
AD		 1283/* clock mode flags */
1284#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1285
56278a8e
AD		 1286struct radeon_pm_clock_info {
1287 /* memory clock */
1288 u32 mclk;
1289 /* engine clock */
1290 u32 sclk;
1291 /* voltage info */
1292 struct radeon_voltage voltage;
d7311171 1293 /* standardized clock flags */
56278a8e
AD		 1294 u32 flags;
1295};
1296
a48b9b4e 1297/* state flags */
d7311171 1298#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1299
56278a8e 1300struct radeon_power_state {
0ec0e74f 1301 enum radeon_pm_state_type type;
8f3f1c9a 1302 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1303 /* number of valid clock modes in this power state */
1304 int num_clock_modes;
56278a8e 1305 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1306 /* standardized state flags */
1307 u32 flags;
79daedc9
AD		 1308 u32 misc; /* vbios specific flags */
1309 u32 misc2; /* vbios specific flags */
1310 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1311};
1312
27459324
RM		 1313/*
1314 * Some modes are overclocked by very low value, accept them
1315 */
1316#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1317
2e9d4c05
AD		 1318enum radeon_dpm_auto_throttle_src {
1319 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1320 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1321};
1322
1323enum radeon_dpm_event_src {
1324 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1325 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1326 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1327 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1328 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1329};
1330
58bd2a88
AD		 1331#define RADEON_MAX_VCE_LEVELS 6
1332
b62d628b
AD		 1333enum radeon_vce_level {
1334 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1335 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1336 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1337 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1338 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1339 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1340};
1341
da321c8a
AD		 1342struct radeon_ps {
1343 u32 caps; /* vbios flags */
1344 u32 class; /* vbios flags */
1345 u32 class2; /* vbios flags */
1346 /* UVD clocks */
1347 u32 vclk;
1348 u32 dclk;
c4453e66
AD		 1349 /* VCE clocks */
1350 u32 evclk;
1351 u32 ecclk;
b62d628b
AD		 1352 bool vce_active;
1353 enum radeon_vce_level vce_level;
da321c8a
AD		 1354 /* asic priv */
1355 void *ps_priv;
1356};
1357
1358struct radeon_dpm_thermal {
1359 /* thermal interrupt work */
1360 struct work_struct work;
1361 /* low temperature threshold */
1362 int min_temp;
1363 /* high temperature threshold */
1364 int max_temp;
1365 /* was interrupt low to high or high to low */
1366 bool high_to_low;
1367};
1368
d22b7e40
AD		 1369enum radeon_clk_action
1370{
1371 RADEON_SCLK_UP = 1,
1372 RADEON_SCLK_DOWN
1373};
1374
1375struct radeon_blacklist_clocks
1376{
1377 u32 sclk;
1378 u32 mclk;
1379 enum radeon_clk_action action;
1380};
1381
61b7d601
AD		 1382struct radeon_clock_and_voltage_limits {
1383 u32 sclk;
1384 u32 mclk;
cdf6e805
AD		 1385 u16 vddc;
1386 u16 vddci;
61b7d601
AD		 1387};
1388
1389struct radeon_clock_array {
1390 u32 count;
1391 u32 *values;
1392};
1393
1394struct radeon_clock_voltage_dependency_entry {
1395 u32 clk;
1396 u16 v;
1397};
1398
1399struct radeon_clock_voltage_dependency_table {
1400 u32 count;
1401 struct radeon_clock_voltage_dependency_entry *entries;
1402};
1403
ef976ec4
AD		 1404union radeon_cac_leakage_entry {
1405 struct {
1406 u16 vddc;
1407 u32 leakage;
1408 };
1409 struct {
1410 u16 vddc1;
1411 u16 vddc2;
1412 u16 vddc3;
1413 };
61b7d601
AD		 1414};
1415
1416struct radeon_cac_leakage_table {
1417 u32 count;
ef976ec4 1418 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1419};
1420
929ee7a8
AD		 1421struct radeon_phase_shedding_limits_entry {
1422 u16 voltage;
1423 u32 sclk;
1424 u32 mclk;
1425};
1426
1427struct radeon_phase_shedding_limits_table {
1428 u32 count;
1429 struct radeon_phase_shedding_limits_entry *entries;
1430};
1431
84a9d9ee
AD		 1432struct radeon_uvd_clock_voltage_dependency_entry {
1433 u32 vclk;
1434 u32 dclk;
1435 u16 v;
1436};
1437
1438struct radeon_uvd_clock_voltage_dependency_table {
1439 u8 count;
1440 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1441};
1442
d29f013b
AD		 1443struct radeon_vce_clock_voltage_dependency_entry {
1444 u32 ecclk;
1445 u32 evclk;
1446 u16 v;
1447};
1448
1449struct radeon_vce_clock_voltage_dependency_table {
1450 u8 count;
1451 struct radeon_vce_clock_voltage_dependency_entry *entries;
1452};
1453
a5cb318e
AD		 1454struct radeon_ppm_table {
1455 u8 ppm_design;
1456 u16 cpu_core_number;
1457 u32 platform_tdp;
1458 u32 small_ac_platform_tdp;
1459 u32 platform_tdc;
1460 u32 small_ac_platform_tdc;
1461 u32 apu_tdp;
1462 u32 dgpu_tdp;
1463 u32 dgpu_ulv_power;
1464 u32 tj_max;
1465};
1466
58cb7632
AD		 1467struct radeon_cac_tdp_table {
1468 u16 tdp;
1469 u16 configurable_tdp;
1470 u16 tdc;
1471 u16 battery_power_limit;
1472 u16 small_power_limit;
1473 u16 low_cac_leakage;
1474 u16 high_cac_leakage;
1475 u16 maximum_power_delivery_limit;
1476};
1477
61b7d601
AD		 1478struct radeon_dpm_dynamic_state {
1479 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1480 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1481 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1482 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1483 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1484 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1485 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1486 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1487 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1488 struct radeon_clock_array valid_sclk_values;
1489 struct radeon_clock_array valid_mclk_values;
1490 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1491 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1492 u32 mclk_sclk_ratio;
1493 u32 sclk_mclk_delta;
1494 u16 vddc_vddci_delta;
1495 u16 min_vddc_for_pcie_gen2;
1496 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1497 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1498 struct radeon_ppm_table *ppm_table;
58cb7632 1499 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1500};
1501
1502struct radeon_dpm_fan {
1503 u16 t_min;
1504 u16 t_med;
1505 u16 t_high;
1506 u16 pwm_min;
1507 u16 pwm_med;
1508 u16 pwm_high;
1509 u8 t_hyst;
1510 u32 cycle_delay;
1511 u16 t_max;
e03cea36
AD		 1512 u8 control_mode;
1513 u16 default_max_fan_pwm;
1514 u16 default_fan_output_sensitivity;
1515 u16 fan_output_sensitivity;
61b7d601
AD		 1516 bool ucode_fan_control;
1517};
1518
32ce4652
AD		 1519enum radeon_pcie_gen {
1520 RADEON_PCIE_GEN1 = 0,
1521 RADEON_PCIE_GEN2 = 1,
1522 RADEON_PCIE_GEN3 = 2,
1523 RADEON_PCIE_GEN_INVALID = 0xffff
1524};
1525
70d01a5e
AD		 1526enum radeon_dpm_forced_level {
1527 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1528 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1529 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1530};
1531
58bd2a88
AD		 1532struct radeon_vce_state {
1533 /* vce clocks */
1534 u32 evclk;
1535 u32 ecclk;
1536 /* gpu clocks */
1537 u32 sclk;
1538 u32 mclk;
1539 u8 clk_idx;
1540 u8 pstate;
1541};
1542
da321c8a
AD		 1543struct radeon_dpm {
1544 struct radeon_ps *ps;
1545 /* number of valid power states */
1546 int num_ps;
1547 /* current power state that is active */
1548 struct radeon_ps *current_ps;
1549 /* requested power state */
1550 struct radeon_ps *requested_ps;
1551 /* boot up power state */
1552 struct radeon_ps *boot_ps;
1553 /* default uvd power state */
1554 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1555 /* vce requirements */
1556 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1557 enum radeon_vce_level vce_level;
da321c8a
AD		 1558 enum radeon_pm_state_type state;
1559 enum radeon_pm_state_type user_state;
1560 u32 platform_caps;
1561 u32 voltage_response_time;
1562 u32 backbias_response_time;
1563 void *priv;
1564 u32 new_active_crtcs;
1565 int new_active_crtc_count;
1566 u32 current_active_crtcs;
1567 int current_active_crtc_count;
61b7d601
AD		 1568 struct radeon_dpm_dynamic_state dyn_state;
1569 struct radeon_dpm_fan fan;
1570 u32 tdp_limit;
1571 u32 near_tdp_limit;
a9e61410 1572 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1573 u32 sq_ramping_threshold;
1574 u32 cac_leakage;
1575 u16 tdp_od_limit;
1576 u32 tdp_adjustment;
1577 u16 load_line_slope;
1578 bool power_control;
5ca302f7 1579 bool ac_power;
da321c8a
AD		 1580 /* special states active */
1581 bool thermal_active;
8a227555 1582 bool uvd_active;
b62d628b 1583 bool vce_active;
da321c8a
AD		 1584 /* thermal handling */
1585 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1586 /* forced levels */
1587 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1588 /* track UVD streams */
1589 unsigned sd;
1590 unsigned hd;
da321c8a
AD		 1591};
1592
ce3537d5 1593void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1594void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1595
c93bb85b 1596struct radeon_pm {
c913e23a 1597 struct mutex mutex;
db7fce39
CK		 1598 /* write locked while reprogramming mclk */
1599 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1600 u32 active_crtcs;
1601 int active_crtc_count;
c913e23a 1602 int req_vblank;
839461d3 1603 bool vblank_sync;
c93bb85b
JG		 1604 fixed20_12 max_bandwidth;
1605 fixed20_12 igp_sideport_mclk;
1606 fixed20_12 igp_system_mclk;
1607 fixed20_12 igp_ht_link_clk;
1608 fixed20_12 igp_ht_link_width;
1609 fixed20_12 k8_bandwidth;
1610 fixed20_12 sideport_bandwidth;
1611 fixed20_12 ht_bandwidth;
1612 fixed20_12 core_bandwidth;
1613 fixed20_12 sclk;
f47299c5 1614 fixed20_12 mclk;
c93bb85b 1615 fixed20_12 needed_bandwidth;
0975b162 1616 struct radeon_power_state *power_state;
56278a8e
AD		 1617 /* number of valid power states */
1618 int num_power_states;
a48b9b4e
AD		 1619 int current_power_state_index;
1620 int current_clock_mode_index;
1621 int requested_power_state_index;
1622 int requested_clock_mode_index;
1623 int default_power_state_index;
1624 u32 current_sclk;
1625 u32 current_mclk;
2feea49a
AD		 1626 u16 current_vddc;
1627 u16 current_vddci;
9ace9f7b
AD		 1628 u32 default_sclk;
1629 u32 default_mclk;
2feea49a
AD		 1630 u16 default_vddc;
1631 u16 default_vddci;
29fb52ca 1632 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1633 /* selected pm method */
1634 enum radeon_pm_method pm_method;
1635 /* dynpm power management */
1636 struct delayed_work dynpm_idle_work;
1637 enum radeon_dynpm_state dynpm_state;
1638 enum radeon_dynpm_action dynpm_planned_action;
1639 unsigned long dynpm_action_timeout;
1640 bool dynpm_can_upclock;
1641 bool dynpm_can_downclock;
1642 /* profile-based power management */
1643 enum radeon_pm_profile_type profile;
1644 int profile_index;
1645 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1646 /* internal thermal controller on rv6xx+ */
1647 enum radeon_int_thermal_type int_thermal_type;
1648 struct device *int_hwmon_dev;
9b92d1ec
AD		 1649 /* fan control parameters */
1650 bool no_fan;
1651 u8 fan_pulses_per_revolution;
1652 u8 fan_min_rpm;
1653 u8 fan_max_rpm;
da321c8a
AD		 1654 /* dpm */
1655 bool dpm_enabled;
1656 struct radeon_dpm dpm;
c93bb85b
JG		 1657};
1658
a4c9e2ee
AD		 1659int radeon_pm_get_type_index(struct radeon_device *rdev,
1660 enum radeon_pm_state_type ps_type,
1661 int instance);
f2ba57b5
CK		 1662/*
1663 * UVD
1664 */
1665#define RADEON_MAX_UVD_HANDLES 10
1666#define RADEON_UVD_STACK_SIZE (1024*1024)
1667#define RADEON_UVD_HEAP_SIZE (1024*1024)
1668
1669struct radeon_uvd {
1670 struct radeon_bo *vcpu_bo;
1671 void *cpu_addr;
1672 uint64_t gpu_addr;
9cc2e0e9 1673 void *saved_bo;
f2ba57b5
CK		 1674 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1675 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1676 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1677 struct delayed_work idle_work;
f2ba57b5
CK		 1678};
1679
1680int radeon_uvd_init(struct radeon_device *rdev);
1681void radeon_uvd_fini(struct radeon_device *rdev);
1682int radeon_uvd_suspend(struct radeon_device *rdev);
1683int radeon_uvd_resume(struct radeon_device *rdev);
1684int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1685 uint32_t handle, struct radeon_fence **fence);
1686int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1687 uint32_t handle, struct radeon_fence **fence);
3852752c
CK		 1688void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1689 uint32_t allowed_domains);
f2ba57b5
CK		 1690void radeon_uvd_free_handles(struct radeon_device *rdev,
1691 struct drm_file *filp);
1692int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1693void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1694int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1695 unsigned vclk, unsigned dclk,
1696 unsigned vco_min, unsigned vco_max,
1697 unsigned fb_factor, unsigned fb_mask,
1698 unsigned pd_min, unsigned pd_max,
1699 unsigned pd_even,
1700 unsigned *optimal_fb_div,
1701 unsigned *optimal_vclk_div,
1702 unsigned *optimal_dclk_div);
1703int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1704 unsigned cg_upll_func_cntl);
771fe6b9 1705
d93f7937
CK		 1706/*
1707 * VCE
1708 */
1709#define RADEON_MAX_VCE_HANDLES 16
1710#define RADEON_VCE_STACK_SIZE (1024*1024)
1711#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1712
1713struct radeon_vce {
1714 struct radeon_bo *vcpu_bo;
d93f7937 1715 uint64_t gpu_addr;
98ccc291
CK		 1716 unsigned fw_version;
1717 unsigned fb_version;
d93f7937
CK		 1718 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1719 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1720 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1721 struct delayed_work idle_work;
d93f7937
CK		 1722};
1723
1724int radeon_vce_init(struct radeon_device *rdev);
1725void radeon_vce_fini(struct radeon_device *rdev);
1726int radeon_vce_suspend(struct radeon_device *rdev);
1727int radeon_vce_resume(struct radeon_device *rdev);
1728int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1729 uint32_t handle, struct radeon_fence **fence);
1730int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1731 uint32_t handle, struct radeon_fence **fence);
1732void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1733void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1734int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1735int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1736bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1737 struct radeon_ring *ring,
1738 struct radeon_semaphore *semaphore,
1739 bool emit_wait);
1740void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1741void radeon_vce_fence_emit(struct radeon_device *rdev,
1742 struct radeon_fence *fence);
1743int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1744int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1745
b530602f 1746struct r600_audio_pin {
a92553ab
RM		 1747 int channels;
1748 int rate;
1749 int bits_per_sample;
1750 u8 status_bits;
1751 u8 category_code;
b530602f
AD		 1752 u32 offset;
1753 bool connected;
1754 u32 id;
1755};
1756
1757struct r600_audio {
1758 bool enabled;
1759 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1760 int num_pins;
1a626b68
SG		 1761 struct radeon_audio_funcs *hdmi_funcs;
1762 struct radeon_audio_funcs *dp_funcs;
1763 struct radeon_audio_basic_funcs *funcs;
a92553ab
RM		 1764};
1765
771fe6b9
JG		 1766/*
1767 * Benchmarking
1768 */
638dd7db 1769void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1770
1771
ecc0b326
MD		 1772/*
1773 * Testing
1774 */
1775void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1776void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1777 struct radeon_ring *cpA,
1778 struct radeon_ring *cpB);
60a7e396 1779void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326 1780
341cb9e4
CK		 1781/*
1782 * MMU Notifier
1783 */
5a1aa4b4 1784#if defined(CONFIG_MMU_NOTIFIER)
341cb9e4
CK		 1785int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1786void radeon_mn_unregister(struct radeon_bo *bo);
5a1aa4b4
RC		 1787#else
1788static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1789{
1790 return -ENODEV;
1791}
1792static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1793#endif
ecc0b326 1794
771fe6b9
JG		 1795/*
1796 * Debugfs
1797 */
4d8bf9ae
CK		 1798struct radeon_debugfs {
1799 struct drm_info_list *files;
1800 unsigned num_files;
1801};
1802
771fe6b9
JG		 1803int radeon_debugfs_add_files(struct radeon_device *rdev,
1804 struct drm_info_list *files,
1805 unsigned nfiles);
1806int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1807
76a0df85
CK		 1808/*
1809 * ASIC ring specific functions.
1810 */
1811struct radeon_asic_ring {
1812 /* ring read/write ptr handling */
1813 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1814 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1815 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1816
1817 /* validating and patching of IBs */
1818 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1819 int (*cs_parse)(struct radeon_cs_parser *p);
1820
1821 /* command emmit functions */
1822 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1823 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1824 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1825 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85 1826 struct radeon_semaphore *semaphore, bool emit_wait);
faffaf62
CK		 1827 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1828 unsigned vm_id, uint64_t pd_addr);
76a0df85
CK		 1829
1830 /* testing functions */
1831 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1832 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1833 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1834
1835 /* deprecated */
1836 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1837};
771fe6b9
JG		 1838
1839/*
1840 * ASIC specific functions.
1841 */
1842struct radeon_asic {
068a117c 1843 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1844 void (*fini)(struct radeon_device *rdev);
1845 int (*resume)(struct radeon_device *rdev);
1846 int (*suspend)(struct radeon_device *rdev);
28d52043 1847 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1848 int (*asic_reset)(struct radeon_device *rdev);
124764f1
MD		 1849 /* Flush the HDP cache via MMIO */
1850 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1851 /* check if 3D engine is idle */
1852 bool (*gui_idle)(struct radeon_device *rdev);
1853 /* wait for mc_idle */
1854 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1855 /* get the reference clock */
1856 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1857 /* get the gpu clock counter */
1858 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1859 /* gart */
c5b3b850
AD		 1860 struct {
1861 void (*tlb_flush)(struct radeon_device *rdev);
cb658906 1862 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
7f90fc96 1863 void (*set_page)(struct radeon_device *rdev, unsigned i,
cb658906 1864 uint64_t entry);
c5b3b850 1865 } gart;
05b07147
CK		 1866 struct {
1867 int (*init)(struct radeon_device *rdev);
1868 void (*fini)(struct radeon_device *rdev);
03f62abd
CK		 1869 void (*copy_pages)(struct radeon_device *rdev,
1870 struct radeon_ib *ib,
1871 uint64_t pe, uint64_t src,
1872 unsigned count);
1873 void (*write_pages)(struct radeon_device *rdev,
1874 struct radeon_ib *ib,
1875 uint64_t pe,
1876 uint64_t addr, unsigned count,
1877 uint32_t incr, uint32_t flags);
1878 void (*set_pages)(struct radeon_device *rdev,
1879 struct radeon_ib *ib,
1880 uint64_t pe,
1881 uint64_t addr, unsigned count,
1882 uint32_t incr, uint32_t flags);
1883 void (*pad_ib)(struct radeon_ib *ib);
05b07147 1884 } vm;
54e88e06 1885 /* ring specific callbacks */
76a0df85 1886 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1887 /* irqs */
b35ea4ab
AD		 1888 struct {
1889 int (*set)(struct radeon_device *rdev);
1890 int (*process)(struct radeon_device *rdev);
1891 } irq;
54e88e06 1892 /* displays */
c79a49ca
AD		 1893 struct {
1894 /* display watermarks */
1895 void (*bandwidth_update)(struct radeon_device *rdev);
1896 /* get frame count */
1897 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1898 /* wait for vblank */
1899 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1900 /* set backlight level */
1901 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1902 /* get backlight level */
1903 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1904 /* audio callbacks */
1905 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1906 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1907 } display;
54e88e06 1908 /* copy functions for bo handling */
27cd7769 1909 struct {
57d20a43
CK		 1910 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1911 uint64_t src_offset,
1912 uint64_t dst_offset,
1913 unsigned num_gpu_pages,
1914 struct reservation_object *resv);
27cd7769 1915 u32 blit_ring_index;
57d20a43
CK		 1916 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1917 uint64_t src_offset,
1918 uint64_t dst_offset,
1919 unsigned num_gpu_pages,
1920 struct reservation_object *resv);
27cd7769
AD		 1921 u32 dma_ring_index;
1922 /* method used for bo copy */
57d20a43
CK		 1923 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1924 uint64_t src_offset,
1925 uint64_t dst_offset,
1926 unsigned num_gpu_pages,
1927 struct reservation_object *resv);
27cd7769
AD		 1928 /* ring used for bo copies */
1929 u32 copy_ring_index;
1930 } copy;
54e88e06 1931 /* surfaces */
9e6f3d02
AD		 1932 struct {
1933 int (*set_reg)(struct radeon_device *rdev, int reg,
1934 uint32_t tiling_flags, uint32_t pitch,
1935 uint32_t offset, uint32_t obj_size);
1936 void (*clear_reg)(struct radeon_device *rdev, int reg);
1937 } surface;
54e88e06 1938 /* hotplug detect */
901ea57d
AD		 1939 struct {
1940 void (*init)(struct radeon_device *rdev);
1941 void (*fini)(struct radeon_device *rdev);
1942 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1943 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1944 } hpd;
da321c8a 1945 /* static power management */
a02fa397
AD		 1946 struct {
1947 void (*misc)(struct radeon_device *rdev);
1948 void (*prepare)(struct radeon_device *rdev);
1949 void (*finish)(struct radeon_device *rdev);
1950 void (*init_profile)(struct radeon_device *rdev);
1951 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1952 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1953 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1954 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1955 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1956 int (*get_pcie_lanes)(struct radeon_device *rdev);
1957 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1958 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1959 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1960 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1961 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1962 } pm;
da321c8a
AD		 1963 /* dynamic power management */
1964 struct {
1965 int (*init)(struct radeon_device *rdev);
1966 void (*setup_asic)(struct radeon_device *rdev);
1967 int (*enable)(struct radeon_device *rdev);
914a8987 1968 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1969 void (*disable)(struct radeon_device *rdev);
84dd1928 1970 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1971 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1972 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1973 void (*display_configuration_changed)(struct radeon_device *rdev);
1974 void (*fini)(struct radeon_device *rdev);
1975 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1976 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1977 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1978 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1979 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1980 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1981 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1982 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
a35a4b2b
OC		 1983 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1984 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1985 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1986 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
da321c8a 1987 } dpm;
6f34be50 1988 /* pageflipping */
0f9e006c 1989 struct {
157fa14d
CK		 1990 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1991 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 1992 } pflip;
771fe6b9
JG		 1993};
1994
21f9a437
JG		 1995/*
1996 * Asic structures
1997 */
551ebd83 1998struct r100_asic {
225758d8
JG		 1999 const unsigned *reg_safe_bm;
2000 unsigned reg_safe_bm_size;
2001 u32 hdp_cntl;
551ebd83
DA		 2002};
2003
21f9a437 2004struct r300_asic {
225758d8
JG		 2005 const unsigned *reg_safe_bm;
2006 unsigned reg_safe_bm_size;
2007 u32 resync_scratch;
2008 u32 hdp_cntl;
21f9a437
JG		 2009};
2010
2011struct r600_asic {
225758d8
JG		 2012 unsigned max_pipes;
2013 unsigned max_tile_pipes;
2014 unsigned max_simds;
2015 unsigned max_backends;
2016 unsigned max_gprs;
2017 unsigned max_threads;
2018 unsigned max_stack_entries;
2019 unsigned max_hw_contexts;
2020 unsigned max_gs_threads;
2021 unsigned sx_max_export_size;
2022 unsigned sx_max_export_pos_size;
2023 unsigned sx_max_export_smx_size;
2024 unsigned sq_num_cf_insts;
2025 unsigned tiling_nbanks;
2026 unsigned tiling_npipes;
2027 unsigned tiling_group_size;
e7aeeba6 2028 unsigned tile_config;
e55b9422 2029 unsigned backend_map;
65fcf668 2030 unsigned active_simds;
21f9a437
JG		 2031};
2032
2033struct rv770_asic {
225758d8
JG		 2034 unsigned max_pipes;
2035 unsigned max_tile_pipes;
2036 unsigned max_simds;
2037 unsigned max_backends;
2038 unsigned max_gprs;
2039 unsigned max_threads;
2040 unsigned max_stack_entries;
2041 unsigned max_hw_contexts;
2042 unsigned max_gs_threads;
2043 unsigned sx_max_export_size;
2044 unsigned sx_max_export_pos_size;
2045 unsigned sx_max_export_smx_size;
2046 unsigned sq_num_cf_insts;
2047 unsigned sx_num_of_sets;
2048 unsigned sc_prim_fifo_size;
2049 unsigned sc_hiz_tile_fifo_size;
2050 unsigned sc_earlyz_tile_fifo_fize;
2051 unsigned tiling_nbanks;
2052 unsigned tiling_npipes;
2053 unsigned tiling_group_size;
e7aeeba6 2054 unsigned tile_config;
e55b9422 2055 unsigned backend_map;
65fcf668 2056 unsigned active_simds;
21f9a437
JG		 2057};
2058
32fcdbf4
AD		 2059struct evergreen_asic {
2060 unsigned num_ses;
2061 unsigned max_pipes;
2062 unsigned max_tile_pipes;
2063 unsigned max_simds;
2064 unsigned max_backends;
2065 unsigned max_gprs;
2066 unsigned max_threads;
2067 unsigned max_stack_entries;
2068 unsigned max_hw_contexts;
2069 unsigned max_gs_threads;
2070 unsigned sx_max_export_size;
2071 unsigned sx_max_export_pos_size;
2072 unsigned sx_max_export_smx_size;
2073 unsigned sq_num_cf_insts;
2074 unsigned sx_num_of_sets;
2075 unsigned sc_prim_fifo_size;
2076 unsigned sc_hiz_tile_fifo_size;
2077 unsigned sc_earlyz_tile_fifo_size;
2078 unsigned tiling_nbanks;
2079 unsigned tiling_npipes;
2080 unsigned tiling_group_size;
e7aeeba6 2081 unsigned tile_config;
e55b9422 2082 unsigned backend_map;
65fcf668 2083 unsigned active_simds;
32fcdbf4
AD		 2084};
2085
fecf1d07
AD		 2086struct cayman_asic {
2087 unsigned max_shader_engines;
2088 unsigned max_pipes_per_simd;
2089 unsigned max_tile_pipes;
2090 unsigned max_simds_per_se;
2091 unsigned max_backends_per_se;
2092 unsigned max_texture_channel_caches;
2093 unsigned max_gprs;
2094 unsigned max_threads;
2095 unsigned max_gs_threads;
2096 unsigned max_stack_entries;
2097 unsigned sx_num_of_sets;
2098 unsigned sx_max_export_size;
2099 unsigned sx_max_export_pos_size;
2100 unsigned sx_max_export_smx_size;
2101 unsigned max_hw_contexts;
2102 unsigned sq_num_cf_insts;
2103 unsigned sc_prim_fifo_size;
2104 unsigned sc_hiz_tile_fifo_size;
2105 unsigned sc_earlyz_tile_fifo_size;
2106
2107 unsigned num_shader_engines;
2108 unsigned num_shader_pipes_per_simd;
2109 unsigned num_tile_pipes;
2110 unsigned num_simds_per_se;
2111 unsigned num_backends_per_se;
2112 unsigned backend_disable_mask_per_asic;
2113 unsigned backend_map;
2114 unsigned num_texture_channel_caches;
2115 unsigned mem_max_burst_length_bytes;
2116 unsigned mem_row_size_in_kb;
2117 unsigned shader_engine_tile_size;
2118 unsigned num_gpus;
2119 unsigned multi_gpu_tile_size;
2120
2121 unsigned tile_config;
65fcf668 2122 unsigned active_simds;
fecf1d07
AD		 2123};
2124
0a96d72b
AD		 2125struct si_asic {
2126 unsigned max_shader_engines;
0a96d72b 2127 unsigned max_tile_pipes;
1a8ca750
AD		 2128 unsigned max_cu_per_sh;
2129 unsigned max_sh_per_se;
0a96d72b
AD		 2130 unsigned max_backends_per_se;
2131 unsigned max_texture_channel_caches;
2132 unsigned max_gprs;
2133 unsigned max_gs_threads;
2134 unsigned max_hw_contexts;
2135 unsigned sc_prim_fifo_size_frontend;
2136 unsigned sc_prim_fifo_size_backend;
2137 unsigned sc_hiz_tile_fifo_size;
2138 unsigned sc_earlyz_tile_fifo_size;
2139
0a96d72b 2140 unsigned num_tile_pipes;
439a1cff 2141 unsigned backend_enable_mask;
0a96d72b
AD		 2142 unsigned backend_disable_mask_per_asic;
2143 unsigned backend_map;
2144 unsigned num_texture_channel_caches;
2145 unsigned mem_max_burst_length_bytes;
2146 unsigned mem_row_size_in_kb;
2147 unsigned shader_engine_tile_size;
2148 unsigned num_gpus;
2149 unsigned multi_gpu_tile_size;
2150
2151 unsigned tile_config;
64d7b8be 2152 uint32_t tile_mode_array[32];
65fcf668 2153 uint32_t active_cus;
0a96d72b
AD		 2154};
2155
8cc1a532
AD		 2156struct cik_asic {
2157 unsigned max_shader_engines;
2158 unsigned max_tile_pipes;
2159 unsigned max_cu_per_sh;
2160 unsigned max_sh_per_se;
2161 unsigned max_backends_per_se;
2162 unsigned max_texture_channel_caches;
2163 unsigned max_gprs;
2164 unsigned max_gs_threads;
2165 unsigned max_hw_contexts;
2166 unsigned sc_prim_fifo_size_frontend;
2167 unsigned sc_prim_fifo_size_backend;
2168 unsigned sc_hiz_tile_fifo_size;
2169 unsigned sc_earlyz_tile_fifo_size;
2170
2171 unsigned num_tile_pipes;
439a1cff 2172 unsigned backend_enable_mask;
8cc1a532
AD		 2173 unsigned backend_disable_mask_per_asic;
2174 unsigned backend_map;
2175 unsigned num_texture_channel_caches;
2176 unsigned mem_max_burst_length_bytes;
2177 unsigned mem_row_size_in_kb;
2178 unsigned shader_engine_tile_size;
2179 unsigned num_gpus;
2180 unsigned multi_gpu_tile_size;
2181
2182 unsigned tile_config;
39aee490 2183 uint32_t tile_mode_array[32];
32f79a8a 2184 uint32_t macrotile_mode_array[16];
65fcf668 2185 uint32_t active_cus;
8cc1a532
AD		 2186};
2187
068a117c
JG		 2188union radeon_asic_config {
2189 struct r300_asic r300;
551ebd83 2190 struct r100_asic r100;
3ce0a23d
JG		 2191 struct r600_asic r600;
2192 struct rv770_asic rv770;
32fcdbf4 2193 struct evergreen_asic evergreen;
fecf1d07 2194 struct cayman_asic cayman;
0a96d72b 2195 struct si_asic si;
8cc1a532 2196 struct cik_asic cik;
068a117c
JG		 2197};
2198
0a10c851
DV		 2199/*
2200 * asic initizalization from radeon_asic.c
2201 */
2202void radeon_agp_disable(struct radeon_device *rdev);
2203int radeon_asic_init(struct radeon_device *rdev);
2204
771fe6b9
JG		 2205
2206/*
2207 * IOCTL.
2208 */
2209int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2210 struct drm_file *filp);
2211int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2212 struct drm_file *filp);
f72a113a
CK		 2213int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2214 struct drm_file *filp);
771fe6b9
JG		 2215int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2216 struct drm_file *file_priv);
2217int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2218 struct drm_file *file_priv);
2219int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2220 struct drm_file *file_priv);
2221int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2222 struct drm_file *file_priv);
2223int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2224 struct drm_file *filp);
2225int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2226 struct drm_file *filp);
2227int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2228 struct drm_file *filp);
2229int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2230 struct drm_file *filp);
721604a1
JG		 2231int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2232 struct drm_file *filp);
bda72d58
MO		 2233int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2234 struct drm_file *filp);
771fe6b9 2235int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2236int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2237 struct drm_file *filp);
2238int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2239 struct drm_file *filp);
771fe6b9 2240
16cdf04d
AD		 2241/* VRAM scratch page for HDP bug, default vram page */
2242struct r600_vram_scratch {
87cbf8f2
AD		 2243 struct radeon_bo *robj;
2244 volatile uint32_t *ptr;
16cdf04d 2245 u64 gpu_addr;
87cbf8f2 2246};
771fe6b9 2247
fd64ca8a
LT		 2248/*
2249 * ACPI
2250 */
2251struct radeon_atif_notification_cfg {
2252 bool enabled;
2253 int command_code;
2254};
2255
2256struct radeon_atif_notifications {
2257 bool display_switch;
2258 bool expansion_mode_change;
2259 bool thermal_state;
2260 bool forced_power_state;
2261 bool system_power_state;
2262 bool display_conf_change;
2263 bool px_gfx_switch;
2264 bool brightness_change;
2265 bool dgpu_display_event;
2266};
2267
2268struct radeon_atif_functions {
2269 bool system_params;
2270 bool sbios_requests;
2271 bool select_active_disp;
2272 bool lid_state;
2273 bool get_tv_standard;
2274 bool set_tv_standard;
2275 bool get_panel_expansion_mode;
2276 bool set_panel_expansion_mode;
2277 bool temperature_change;
2278 bool graphics_device_types;
2279};
2280
2281struct radeon_atif {
2282 struct radeon_atif_notifications notifications;
2283 struct radeon_atif_functions functions;
2284 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2285 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2286};
7a1619b9 2287
e3a15920
AD		 2288struct radeon_atcs_functions {
2289 bool get_ext_state;
2290 bool pcie_perf_req;
2291 bool pcie_dev_rdy;
2292 bool pcie_bus_width;
2293};
2294
2295struct radeon_atcs {
2296 struct radeon_atcs_functions functions;
2297};
2298
771fe6b9
JG		 2299/*
2300 * Core structure, functions and helpers.
2301 */
2302typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2303typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2304
2305struct radeon_device {
9f022ddf 2306 struct device *dev;
771fe6b9
JG		 2307 struct drm_device *ddev;
2308 struct pci_dev *pdev;
dee53e7f 2309 struct rw_semaphore exclusive_lock;
771fe6b9 2310 /* ASIC */
068a117c 2311 union radeon_asic_config config;
771fe6b9
JG		 2312 enum radeon_family family;
2313 unsigned long flags;
2314 int usec_timeout;
2315 enum radeon_pll_errata pll_errata;
2316 int num_gb_pipes;
f779b3e5 2317 int num_z_pipes;
771fe6b9
JG		 2318 int disp_priority;
2319 /* BIOS */
2320 uint8_t *bios;
2321 bool is_atom_bios;
2322 uint16_t bios_header_start;
4c788679 2323 struct radeon_bo *stollen_vga_memory;
771fe6b9 2324 /* Register mmio */
4c9bc75c
DA		 2325 resource_size_t rmmio_base;
2326 resource_size_t rmmio_size;
2c385151
DV		 2327 /* protects concurrent MM_INDEX/DATA based register access */
2328 spinlock_t mmio_idx_lock;
fe78118c
AD		 2329 /* protects concurrent SMC based register access */
2330 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2331 /* protects concurrent PLL register access */
2332 spinlock_t pll_idx_lock;
2333 /* protects concurrent MC register access */
2334 spinlock_t mc_idx_lock;
2335 /* protects concurrent PCIE register access */
2336 spinlock_t pcie_idx_lock;
2337 /* protects concurrent PCIE_PORT register access */
2338 spinlock_t pciep_idx_lock;
2339 /* protects concurrent PIF register access */
2340 spinlock_t pif_idx_lock;
2341 /* protects concurrent CG register access */
2342 spinlock_t cg_idx_lock;
2343 /* protects concurrent UVD register access */
2344 spinlock_t uvd_idx_lock;
2345 /* protects concurrent RCU register access */
2346 spinlock_t rcu_idx_lock;
2347 /* protects concurrent DIDT register access */
2348 spinlock_t didt_idx_lock;
2349 /* protects concurrent ENDPOINT (audio) register access */
2350 spinlock_t end_idx_lock;
a0533fbf 2351 void __iomem *rmmio;
771fe6b9
JG		 2352 radeon_rreg_t mc_rreg;
2353 radeon_wreg_t mc_wreg;
2354 radeon_rreg_t pll_rreg;
2355 radeon_wreg_t pll_wreg;
de1b2898 2356 uint32_t pcie_reg_mask;
771fe6b9
JG		 2357 radeon_rreg_t pciep_rreg;
2358 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2359 /* io port */
2360 void __iomem *rio_mem;
2361 resource_size_t rio_mem_size;
771fe6b9
JG		 2362 struct radeon_clock clock;
2363 struct radeon_mc mc;
2364 struct radeon_gart gart;
2365 struct radeon_mode_info mode_info;
2366 struct radeon_scratch scratch;
75efdee1 2367 struct radeon_doorbell doorbell;
771fe6b9 2368 struct radeon_mman mman;
7465280c 2369 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2370 wait_queue_head_t fence_queue;
954605ca 2371 unsigned fence_context;
d6999bc7 2372 struct mutex ring_lock;
e32eb50d 2373 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2374 bool ib_pool_ready;
2375 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2376 struct radeon_irq irq;
2377 struct radeon_asic *asic;
2378 struct radeon_gem gem;
c93bb85b 2379 struct radeon_pm pm;
f2ba57b5 2380 struct radeon_uvd uvd;
d93f7937 2381 struct radeon_vce vce;
f657c2a7 2382 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2383 struct radeon_wb wb;
3ce0a23d 2384 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2385 bool shutdown;
2386 bool suspend;
ad49f501 2387 bool need_dma32;
733289c2 2388 bool accel_working;
a0a53aa8 2389 bool fastfb_working; /* IGP feature*/
9bb39ff4 2390 bool needs_reset, in_reset;
e024e110 2391 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2392 const struct firmware *me_fw; /* all family ME firmware */
2393 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2394 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2395 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2396 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2397 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2398 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2399 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2400 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2401 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2402 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2403 bool new_fw;
16cdf04d 2404 struct r600_vram_scratch vram_scratch;
3e5cb98d 2405 int msi_enabled; /* msi enabled */
d8f60cfc 2406 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2407 struct radeon_rlc rlc;
963e81f9 2408 struct radeon_mec mec;
d4877cf2 2409 struct work_struct hotplug_work;
f122c610 2410 struct work_struct audio_work;
18917b60 2411 int num_crtc; /* number of crtcs */
40bacf16 2412 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2413 bool has_uvd;
b530602f 2414 struct r600_audio audio; /* audio stuff */
ce8f5370 2415 struct notifier_block acpi_nb;
9eba4a93 2416 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2417 struct drm_file *hyperz_filp;
9eba4a93 2418 struct drm_file *cmask_filp;
f376b94f
AD		 2419 /* i2c buses */
2420 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2421 /* debugfs */
2422 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2423 unsigned debugfs_count;
721604a1
JG		 2424 /* virtual memory */
2425 struct radeon_vm_manager vm_manager;
6759a0a7 2426 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2427 /* memory stats */
2428 atomic64_t vram_usage;
2429 atomic64_t gtt_usage;
2430 atomic64_t num_bytes_moved;
fd64ca8a
LT		 2431 /* ACPI interface */
2432 struct radeon_atif atif;
e3a15920 2433 struct radeon_atcs atcs;
f61d5b46
AD		 2434 /* srbm instance registers */
2435 struct mutex srbm_mutex;
1c0a4625
OG		 2436 /* GRBM index mutex. Protects concurrents access to GRBM index */
2437 struct mutex grbm_idx_mutex;
64d8a728
AD		 2438 /* clock, powergating flags */
2439 u32 cg_flags;
2440 u32 pg_flags;
10ebc0bc
DA		 2441
2442 struct dev_pm_domain vga_pm_domain;
2443 bool have_disp_power_ref;
4807c5a8 2444 u32 px_quirk_flags;
71ecc97e
AD		 2445
2446 /* tracking pinned memory */
2447 u64 vram_pin_size;
2448 u64 gart_pin_size;
341cb9e4 2449
e28740ec
OG		 2450 /* amdkfd interface */
2451 struct kfd_dev *kfd;
2452 struct radeon_sa_manager kfd_bo;
2453
341cb9e4
CK		 2454 struct mutex mn_lock;
2455 DECLARE_HASHTABLE(mn_hash, 7);
771fe6b9
JG		 2456};
2457
90c4cde9 2458bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2459int radeon_device_init(struct radeon_device *rdev,
2460 struct drm_device *ddev,
2461 struct pci_dev *pdev,
2462 uint32_t flags);
2463void radeon_device_fini(struct radeon_device *rdev);
2464int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2465
59bc1d89
LK		 2466#define RADEON_MIN_MMIO_SIZE 0x10000
2467
2468static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2469 bool always_indirect)
2470{
2471 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2472 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2473 return readl(((void __iomem *)rdev->rmmio) + reg);
2474 else {
2475 unsigned long flags;
2476 uint32_t ret;
2477
2478 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2479 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2480 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2481 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2482
2483 return ret;
2484 }
2485}
2486
2487static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2488 bool always_indirect)
2489{
2490 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2491 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2492 else {
2493 unsigned long flags;
2494
2495 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2496 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2497 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2498 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2499 }
2500}
2501
6fcbef7a
AK		 2502u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2503void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2504
d5754ab8
AL		 2505u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2506void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2507
4c788679
JG		 2508/*
2509 * Cast helper
2510 */
954605ca
ML		 2511extern const struct fence_ops radeon_fence_ops;
2512
2513static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2514{
2515 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2516
2517 if (__f->base.ops == &radeon_fence_ops)
2518 return __f;
2519
2520 return NULL;
2521}
771fe6b9
JG		 2522
2523/*
2524 * Registers read & write functions.
2525 */
a0533fbf
BH		 2526#define RREG8(reg) readb((rdev->rmmio) + (reg))
2527#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2528#define RREG16(reg) readw((rdev->rmmio) + (reg))
2529#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2530#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2531#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2532#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2533#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2534#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2535#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2536#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2537#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2538#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2539#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2540#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2541#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2542#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2543#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2544#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2545#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2546#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2547#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2548#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2549#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2550#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2551#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2552#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2553#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2554#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2555#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2556#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2557#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2558#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2559#define WREG32_P(reg, val, mask) \
2560 do { \
2561 uint32_t tmp_ = RREG32(reg); \
2562 tmp_ &= (mask); \
2563 tmp_ |= ((val) & ~(mask)); \
2564 WREG32(reg, tmp_); \
2565 } while (0)
d5169fc4 2566#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2567#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2568#define WREG32_PLL_P(reg, val, mask) \
2569 do { \
2570 uint32_t tmp_ = RREG32_PLL(reg); \
2571 tmp_ &= (mask); \
2572 tmp_ |= ((val) & ~(mask)); \
2573 WREG32_PLL(reg, tmp_); \
2574 } while (0)
2ef9bdfe 2575#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2576#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2577#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2578
d5754ab8
AL		 2579#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2580#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2581
de1b2898
DA		 2582/*
2583 * Indirect registers accessor
2584 */
2585static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2586{
0a5b7b0b 2587 unsigned long flags;
de1b2898
DA		 2588 uint32_t r;
2589
0a5b7b0b 2590 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2591 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2592 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2593 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2594 return r;
2595}
2596
2597static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2598{
0a5b7b0b
AD		 2599 unsigned long flags;
2600
2601 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2602 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2603 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2604 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2605}
2606
1d5d0c34
AD		 2607static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2608{
fe78118c 2609 unsigned long flags;
1d5d0c34
AD		 2610 u32 r;
2611
fe78118c 2612 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2613 WREG32(TN_SMC_IND_INDEX_0, (reg));
2614 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2615 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2616 return r;
2617}
2618
2619static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2620{
fe78118c
AD		 2621 unsigned long flags;
2622
2623 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2624 WREG32(TN_SMC_IND_INDEX_0, (reg));
2625 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2626 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2627}
2628
ff82bbc4
AD		 2629static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2630{
0a5b7b0b 2631 unsigned long flags;
ff82bbc4
AD		 2632 u32 r;
2633
0a5b7b0b 2634 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2635 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2636 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2637 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2638 return r;
2639}
2640
2641static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2642{
0a5b7b0b
AD		 2643 unsigned long flags;
2644
2645 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2646 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2647 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2648 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2649}
2650
46f9564a
AD		 2651static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2652{
0a5b7b0b 2653 unsigned long flags;
46f9564a
AD		 2654 u32 r;
2655
0a5b7b0b 2656 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2657 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2658 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2659 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2660 return r;
2661}
2662
2663static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2664{
0a5b7b0b
AD		 2665 unsigned long flags;
2666
2667 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2668 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2669 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2670 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2671}
2672
792edd69
AD		 2673static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2674{
0a5b7b0b 2675 unsigned long flags;
792edd69
AD		 2676 u32 r;
2677
0a5b7b0b 2678 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2679 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2680 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2681 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2682 return r;
2683}
2684
2685static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2686{
0a5b7b0b
AD		 2687 unsigned long flags;
2688
2689 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2690 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2691 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2692 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2693}
2694
2695static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2696{
0a5b7b0b 2697 unsigned long flags;
792edd69
AD		 2698 u32 r;
2699
0a5b7b0b 2700 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2701 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2702 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2703 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2704 return r;
2705}
2706
2707static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2708{
0a5b7b0b
AD		 2709 unsigned long flags;
2710
2711 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2712 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2713 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2714 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2715}
2716
93656cdd
AD		 2717static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2718{
0a5b7b0b 2719 unsigned long flags;
93656cdd
AD		 2720 u32 r;
2721
0a5b7b0b 2722 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2723 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2724 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2725 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2726 return r;
2727}
2728
2729static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2730{
0a5b7b0b
AD		 2731 unsigned long flags;
2732
2733 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2734 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2735 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2736 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2737}
2738
1d58234d
AD		 2739
2740static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2741{
0a5b7b0b 2742 unsigned long flags;
1d58234d
AD		 2743 u32 r;
2744
0a5b7b0b 2745 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2746 WREG32(CIK_DIDT_IND_INDEX, (reg));
2747 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2748 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2749 return r;
2750}
2751
2752static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2753{
0a5b7b0b
AD		 2754 unsigned long flags;
2755
2756 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2757 WREG32(CIK_DIDT_IND_INDEX, (reg));
2758 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2759 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2760}
2761
771fe6b9
JG		 2762void r100_pll_errata_after_index(struct radeon_device *rdev);
2763
2764
2765/*
2766 * ASICs helpers.
2767 */
b995e433
DA		 2768#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2769 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2770#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2771 (rdev->family == CHIP_RV200) || \
2772 (rdev->family == CHIP_RS100) || \
2773 (rdev->family == CHIP_RS200) || \
2774 (rdev->family == CHIP_RV250) || \
2775 (rdev->family == CHIP_RV280) || \
2776 (rdev->family == CHIP_RS300))
2777#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2778 (rdev->family == CHIP_RV350) || \
2779 (rdev->family == CHIP_R350) || \
2780 (rdev->family == CHIP_RV380) || \
2781 (rdev->family == CHIP_R420) || \
2782 (rdev->family == CHIP_R423) || \
2783 (rdev->family == CHIP_RV410) || \
2784 (rdev->family == CHIP_RS400) || \
2785 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2786#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2787 (rdev->ddev->pdev->device == 0x9443) || \
2788 (rdev->ddev->pdev->device == 0x944B) || \
2789 (rdev->ddev->pdev->device == 0x9506) || \
2790 (rdev->ddev->pdev->device == 0x9509) || \
2791 (rdev->ddev->pdev->device == 0x950F) || \
2792 (rdev->ddev->pdev->device == 0x689C) || \
2793 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2794#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2795#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2796 (rdev->family == CHIP_RS690) || \
2797 (rdev->family == CHIP_RS740) || \
2798 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2799#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2800#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2801#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2802#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2803 (rdev->flags & RADEON_IS_IGP))
1fe18305 2804#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2805#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2806#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2807 (rdev->flags & RADEON_IS_IGP))
624d3524 2808#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2809#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2810#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2811#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2812#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2813#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2814 (rdev->family == CHIP_MULLINS))
771fe6b9 2815
dc50ba7f
AD		 2816#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2817 (rdev->ddev->pdev->device == 0x6850) || \
2818 (rdev->ddev->pdev->device == 0x6858) || \
2819 (rdev->ddev->pdev->device == 0x6859) || \
2820 (rdev->ddev->pdev->device == 0x6840) || \
2821 (rdev->ddev->pdev->device == 0x6841) || \
2822 (rdev->ddev->pdev->device == 0x6842) || \
2823 (rdev->ddev->pdev->device == 0x6843))
2824
771fe6b9
JG		 2825/*
2826 * BIOS helpers.
2827 */
2828#define RBIOS8(i) (rdev->bios[i])
2829#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2830#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2831
2832int radeon_combios_init(struct radeon_device *rdev);
2833void radeon_combios_fini(struct radeon_device *rdev);
2834int radeon_atombios_init(struct radeon_device *rdev);
2835void radeon_atombios_fini(struct radeon_device *rdev);
2836
2837
2838/*
2839 * RING helpers.
2840 */
edf0ac7c
DH		 2841
2842/**
2843 * radeon_ring_write - write a value to the ring
2844 *
2845 * @ring: radeon_ring structure holding ring information
2846 * @v: dword (dw) value to write
2847 *
2848 * Write a value to the requested ring buffer (all asics).
2849 */
e32eb50d 2850static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2851{
edf0ac7c
DH		 2852 if (ring->count_dw <= 0)
2853 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2854
e32eb50d
CK		 2855 ring->ring[ring->wptr++] = v;
2856 ring->wptr &= ring->ptr_mask;
2857 ring->count_dw--;
2858 ring->ring_free_dw--;
771fe6b9 2859}
771fe6b9
JG		 2860
2861/*
2862 * ASICs macro.
2863 */
068a117c 2864#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2865#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2866#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2867#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2868#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2869#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2870#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850 2871#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
cb658906
MD		 2872#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2873#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
05b07147
CK		 2874#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2875#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
03f62abd
CK		 2876#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2877#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2878#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2879#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
76a0df85
CK		 2880#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2881#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2882#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2883#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2884#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2885#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
faffaf62 2886#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
76a0df85
CK		 2887#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2888#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2889#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2890#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2891#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2892#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2893#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2894#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2895#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2896#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2897#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2898#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
57d20a43
CK		 2899#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2900#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2901#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
27cd7769
AD		 2902#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2903#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2904#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2905#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2906#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2907#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2908#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2909#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2910#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2911#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2912#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2913#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2914#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2915#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2916#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2917#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2918#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2919#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2920#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2921#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2922#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2923#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2924#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2925#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2926#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2927#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2928#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2929#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2930#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2931#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2932#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2933#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2934#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2935#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2936#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2937#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2938#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2939#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2940#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2941#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2942#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2943#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2944#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2945#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2946#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2947#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2948#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2949#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2950#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2951#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2952
6cf8a3f5 2953/* Common functions */
700a0cc0 2954/* AGP */
90aca4d2 2955extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2956extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2957extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2958extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2959extern int radeon_modeset_init(struct radeon_device *rdev);
2960extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2961extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2962extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2963extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2964extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2965extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2966extern void radeon_wb_fini(struct radeon_device *rdev);
2967extern int radeon_wb_init(struct radeon_device *rdev);
2968extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2969extern void radeon_surface_init(struct radeon_device *rdev);
2970extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2971extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2972extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2973extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2974extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
f72a113a
CK		 2975extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2976 uint32_t flags);
2977extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2978extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
d594e46a
JG		 2979extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2980extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2981extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2982extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2983extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2984extern void radeon_program_register_sequence(struct radeon_device *rdev,
2985 const u32 *registers,
2986 const u32 array_size);
6cf8a3f5 2987
721604a1
JG		 2988/*
2989 * vm
2990 */
2991int radeon_vm_manager_init(struct radeon_device *rdev);
2992void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2993int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2994void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1d0c0942 2995struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
df0af440
CK		 2996 struct radeon_vm *vm,
2997 struct list_head *head);
ee60e29f
CK		 2998struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2999 struct radeon_vm *vm, int ring);
fa688343
CK		 3000void radeon_vm_flush(struct radeon_device *rdev,
3001 struct radeon_vm *vm,
ad1a58a4 3002 int ring, struct radeon_fence *fence);
ee60e29f
CK		 3003void radeon_vm_fence(struct radeon_device *rdev,
3004 struct radeon_vm *vm,
3005 struct radeon_fence *fence);
dce34bfd 3006uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 3007int radeon_vm_update_page_directory(struct radeon_device *rdev,
3008 struct radeon_vm *vm);
036bf46a
CK		 3009int radeon_vm_clear_freed(struct radeon_device *rdev,
3010 struct radeon_vm *vm);
e31ad969
CK		 3011int radeon_vm_clear_invalids(struct radeon_device *rdev,
3012 struct radeon_vm *vm);
9c57a6bd 3013int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 3014 struct radeon_bo_va *bo_va,
9c57a6bd 3015 struct ttm_mem_reg *mem);
721604a1
JG		 3016void radeon_vm_bo_invalidate(struct radeon_device *rdev,
3017 struct radeon_bo *bo);
421ca7ab
CK		 3018struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
3019 struct radeon_bo *bo);
e971bd5e
CK		 3020struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
3021 struct radeon_vm *vm,
3022 struct radeon_bo *bo);
3023int radeon_vm_bo_set_addr(struct radeon_device *rdev,
3024 struct radeon_bo_va *bo_va,
3025 uint64_t offset,
3026 uint32_t flags);
036bf46a
CK		 3027void radeon_vm_bo_rmv(struct radeon_device *rdev,
3028 struct radeon_bo_va *bo_va);
721604a1 3029
f122c610
AD		 3030/* audio */
3031void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 3032struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
3033struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 3034void r600_audio_enable(struct radeon_device *rdev,
3035 struct r600_audio_pin *pin,
d3d8c141 3036 u8 enable_mask);
832eafaf
AD		 3037void dce6_audio_enable(struct radeon_device *rdev,
3038 struct r600_audio_pin *pin,
d3d8c141 3039 u8 enable_mask);
721604a1 3040
16cdf04d
AD		 3041/*
3042 * R600 vram scratch functions
3043 */
3044int r600_vram_scratch_init(struct radeon_device *rdev);
3045void r600_vram_scratch_fini(struct radeon_device *rdev);
3046
285484e2
JG		 3047/*
3048 * r600 cs checking helper
3049 */
3050unsigned r600_mip_minify(unsigned size, unsigned level);
3051bool r600_fmt_is_valid_color(u32 format);
3052bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
3053int r600_fmt_get_blocksize(u32 format);
3054int r600_fmt_get_nblocksx(u32 format, u32 w);
3055int r600_fmt_get_nblocksy(u32 format, u32 h);
3056
3574dda4
DV		 3057/*
3058 * r600 functions used by radeon_encoder.c
3059 */
1b688d08
RM		 3060struct radeon_hdmi_acr {
3061 u32 clock;
3062
3063 int n_32khz;
3064 int cts_32khz;
3065
3066 int n_44_1khz;
3067 int cts_44_1khz;
3068
3069 int n_48khz;
3070 int cts_48khz;
3071
3072};
3073
e55d3e6c
RM		 3074extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3075
416a2bd2
AD		 3076extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3077 u32 tiling_pipe_num,
3078 u32 max_rb_num,
3079 u32 total_max_rb_num,
3080 u32 enabled_rb_mask);
fe251e2f 3081
e55d3e6c
RM		 3082/*
3083 * evergreen functions used by radeon_encoder.c
3084 */
3085
0af62b01 3086extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 3087extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 3088
c4917074
AD		 3089/* radeon_acpi.c */
3090#if defined(CONFIG_ACPI)
3091extern int radeon_acpi_init(struct radeon_device *rdev);
3092extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 3093extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3094extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 3095 u8 perf_req, bool advertise);
dc50ba7f 3096extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 3097#else
3098static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3099static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3100#endif
d7a2952f 3101
c38f34b5
IH		 3102int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3103 struct radeon_cs_packet *pkt,
3104 unsigned idx);
9ffb7a6d 3105bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 3106void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3107 struct radeon_cs_packet *pkt);
e9716993 3108int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
1d0c0942 3109 struct radeon_bo_list **cs_reloc,
e9716993 3110 int nomm);
40592a17
IH		 3111int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3112 uint32_t *vline_start_end,
3113 uint32_t *vline_status);
c38f34b5 3114
4c788679
JG		 3115#include "radeon_object.h"
3116
771fe6b9 3117#endif
Linux 6.x block layer and io_uring tree(s)