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radeon/audio: consolidate audio_init() functions
[linux-2.6-block.git] / drivers / gpu / drm / radeon / r600_hdmi.c
CommitLineData
dafc3bd5
CK		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 */
e3b2e034 26#include <linux/hdmi.h>
a2098250 27#include <linux/gcd.h>
760285e7
DH		 28#include <drm/drmP.h>
29#include <drm/radeon_drm.h>
dafc3bd5 30#include "radeon.h"
3574dda4 31#include "radeon_asic.h"
c6543a6e 32#include "r600d.h"
dafc3bd5
CK		 33#include "atom.h"
34
35/*
36 * HDMI color format
37 */
38enum r600_hdmi_color_format {
39 RGB = 0,
40 YCC_422 = 1,
41 YCC_444 = 2
42};
43
44/*
45 * IEC60958 status bits
46 */
47enum r600_hdmi_iec_status_bits {
48 AUDIO_STATUS_DIG_ENABLE = 0x01,
3fe373d9
RM		 49 AUDIO_STATUS_V = 0x02,
50 AUDIO_STATUS_VCFG = 0x04,
dafc3bd5
CK		 51 AUDIO_STATUS_EMPHASIS = 0x08,
52 AUDIO_STATUS_COPYRIGHT = 0x10,
53 AUDIO_STATUS_NONAUDIO = 0x20,
54 AUDIO_STATUS_PROFESSIONAL = 0x40,
3fe373d9 55 AUDIO_STATUS_LEVEL = 0x80
dafc3bd5
CK		 56};
57
1109ca09 58static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
dafc3bd5
CK		 59 /* 32kHz 44.1kHz 48kHz */
60 /* Clock N CTS N CTS N CTS */
3e71985f 61 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
dafc3bd5
CK		 62 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
63 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
64 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
65 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
66 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
3e71985f 67 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
dafc3bd5 68 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
3e71985f 69 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
dafc3bd5 70 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
dafc3bd5
CK		 71};
72
72156676
AD		 73static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
74{
75 struct r600_audio_pin status;
76 uint32_t value;
77
78 value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
79
80 /* number of channels */
81 status.channels = (value & 0x7) + 1;
82
83 /* bits per sample */
84 switch ((value & 0xF0) >> 4) {
85 case 0x0:
86 status.bits_per_sample = 8;
87 break;
88 case 0x1:
89 status.bits_per_sample = 16;
90 break;
91 case 0x2:
92 status.bits_per_sample = 20;
93 break;
94 case 0x3:
95 status.bits_per_sample = 24;
96 break;
97 case 0x4:
98 status.bits_per_sample = 32;
99 break;
100 default:
101 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
102 (int)value);
103 status.bits_per_sample = 16;
104 }
105
106 /* current sampling rate in HZ */
107 if (value & 0x4000)
108 status.rate = 44100;
109 else
110 status.rate = 48000;
111 status.rate *= ((value >> 11) & 0x7) + 1;
112 status.rate /= ((value >> 8) & 0x7) + 1;
113
114 value = RREG32(R600_AUDIO_STATUS_BITS);
115
116 /* iec 60958 status bits */
117 status.status_bits = value & 0xff;
118
119 /* iec 60958 category code */
120 status.category_code = (value >> 8) & 0xff;
121
122 return status;
123}
124
125/*
126 * update all hdmi interfaces with current audio parameters
127 */
128void r600_audio_update_hdmi(struct work_struct *work)
129{
130 struct radeon_device *rdev = container_of(work, struct radeon_device,
131 audio_work);
132 struct drm_device *dev = rdev->ddev;
133 struct r600_audio_pin audio_status = r600_audio_status(rdev);
134 struct drm_encoder *encoder;
135 bool changed = false;
136
137 if (rdev->audio.pin[0].channels != audio_status.channels ||
138 rdev->audio.pin[0].rate != audio_status.rate ||
139 rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
140 rdev->audio.pin[0].status_bits != audio_status.status_bits ||
141 rdev->audio.pin[0].category_code != audio_status.category_code) {
142 rdev->audio.pin[0] = audio_status;
143 changed = true;
144 }
145
146 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
147 if (!radeon_encoder_is_digital(encoder))
148 continue;
149 if (changed || r600_hdmi_buffer_status_changed(encoder))
150 r600_hdmi_update_audio_settings(encoder);
151 }
152}
153
154/* enable the audio stream */
155void r600_audio_enable(struct radeon_device *rdev,
156 struct r600_audio_pin *pin,
d3d8c141 157 u8 enable_mask)
72156676 158{
d3d8c141 159 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
72156676
AD		 160
161 if (!pin)
162 return;
163
d3d8c141
AD		 164 if (enable_mask) {
165 tmp |= AUDIO_ENABLED;
166 if (enable_mask & 1)
167 tmp |= PIN0_AUDIO_ENABLED;
168 if (enable_mask & 2)
169 tmp |= PIN1_AUDIO_ENABLED;
170 if (enable_mask & 4)
171 tmp |= PIN2_AUDIO_ENABLED;
172 if (enable_mask & 8)
173 tmp |= PIN3_AUDIO_ENABLED;
72156676 174 } else {
d3d8c141
AD		 175 tmp &= ~(AUDIO_ENABLED |
176 PIN0_AUDIO_ENABLED |
177 PIN1_AUDIO_ENABLED |
178 PIN2_AUDIO_ENABLED |
179 PIN3_AUDIO_ENABLED);
72156676 180 }
d3d8c141
AD		 181
182 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
72156676
AD		 183}
184
72156676
AD		 185/*
186 * release the audio timer
187 * TODO: How to do this correctly on SMP systems?
188 */
189void r600_audio_fini(struct radeon_device *rdev)
190{
191 if (!rdev->audio.enabled)
192 return;
193
d3d8c141 194 r600_audio_enable(rdev, &rdev->audio.pin[0], 0);
72156676
AD		 195
196 rdev->audio.enabled = false;
197}
198
199struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
200{
201 /* only one pin on 6xx-NI */
202 return &rdev->audio.pin[0];
203}
204
dafc3bd5 205/*
a2098250 206 * calculate CTS and N values if they are not found in the table
dafc3bd5 207 */
a2098250 208static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
dafc3bd5 209{
a2098250
PO		 210 int n, cts;
211 unsigned long div, mul;
212
213 /* Safe, but overly large values */
214 n = 128 * freq;
215 cts = clock * 1000;
216
217 /* Smallest valid fraction */
218 div = gcd(n, cts);
219
220 n /= div;
221 cts /= div;
222
223 /*
224 * The optimal N is 128*freq/1000. Calculate the closest larger
225 * value that doesn't truncate any bits.
226 */
227 mul = ((128*freq/1000) + (n-1))/n;
228
229 n *= mul;
230 cts *= mul;
231
232 /* Check that we are in spec (not always possible) */
233 if (n < (128*freq/1500))
234 printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
235 if (n > (128*freq/300))
236 printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");
237
238 *N = n;
239 *CTS = cts;
240
241 DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
242 *N, *CTS, freq);
dafc3bd5
CK		 243}
244
1b688d08
RM		 245struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
246{
247 struct radeon_hdmi_acr res;
248 u8 i;
249
a2098250
PO		 250 /* Precalculated values for common clocks */
251 for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) {
252 if (r600_hdmi_predefined_acr[i].clock == clock)
253 return r600_hdmi_predefined_acr[i];
254 }
1b688d08 255
a2098250
PO		 256 /* And odd clocks get manually calculated */
257 r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
258 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
259 r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
1b688d08
RM		 260
261 return res;
262}
263
dafc3bd5
CK		 264/*
265 * update the N and CTS parameters for a given pixel clock rate
266 */
8f33a156 267void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
dafc3bd5
CK		 268{
269 struct drm_device *dev = encoder->dev;
270 struct radeon_device *rdev = dev->dev_private;
1b688d08 271 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
cfcbd6d3
RM		 272 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
273 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
274 uint32_t offset = dig->afmt->offset;
dafc3bd5 275
68706337
RM		 276 WREG32_P(HDMI0_ACR_32_0 + offset,
277 HDMI0_ACR_CTS_32(acr.cts_32khz),
278 ~HDMI0_ACR_CTS_32_MASK);
279 WREG32_P(HDMI0_ACR_32_1 + offset,
280 HDMI0_ACR_N_32(acr.n_32khz),
281 ~HDMI0_ACR_N_32_MASK);
282
283 WREG32_P(HDMI0_ACR_44_0 + offset,
284 HDMI0_ACR_CTS_44(acr.cts_44_1khz),
285 ~HDMI0_ACR_CTS_44_MASK);
286 WREG32_P(HDMI0_ACR_44_1 + offset,
287 HDMI0_ACR_N_44(acr.n_44_1khz),
288 ~HDMI0_ACR_N_44_MASK);
289
290 WREG32_P(HDMI0_ACR_48_0 + offset,
291 HDMI0_ACR_CTS_48(acr.cts_48khz),
292 ~HDMI0_ACR_CTS_48_MASK);
293 WREG32_P(HDMI0_ACR_48_1 + offset,
294 HDMI0_ACR_N_48(acr.n_48khz),
295 ~HDMI0_ACR_N_48_MASK);
dafc3bd5
CK		 296}
297
dafc3bd5
CK		 298/*
299 * build a HDMI Video Info Frame
300 */
8f33a156
RM		 301void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
302 size_t size)
dafc3bd5
CK		 303{
304 struct drm_device *dev = encoder->dev;
305 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 306 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
307 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
308 uint32_t offset = dig->afmt->offset;
e3b2e034 309 uint8_t *frame = buffer + 3;
f100380e 310 uint8_t *header = buffer;
dafc3bd5 311
c6543a6e 312 WREG32(HDMI0_AVI_INFO0 + offset,
dafc3bd5 313 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
c6543a6e 314 WREG32(HDMI0_AVI_INFO1 + offset,
dafc3bd5 315 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
c6543a6e 316 WREG32(HDMI0_AVI_INFO2 + offset,
dafc3bd5 317 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
c6543a6e 318 WREG32(HDMI0_AVI_INFO3 + offset,
f100380e 319 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
dafc3bd5
CK		 320}
321
322/*
323 * build a Audio Info Frame
324 */
e3b2e034
TR		 325static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
326 const void *buffer, size_t size)
dafc3bd5
CK		 327{
328 struct drm_device *dev = encoder->dev;
329 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 330 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
331 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
332 uint32_t offset = dig->afmt->offset;
e3b2e034 333 const u8 *frame = buffer + 3;
dafc3bd5 334
c6543a6e 335 WREG32(HDMI0_AUDIO_INFO0 + offset,
dafc3bd5 336 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
c6543a6e 337 WREG32(HDMI0_AUDIO_INFO1 + offset,
dafc3bd5
CK		 338 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
339}
340
341/*
342 * test if audio buffer is filled enough to start playing
343 */
cfcbd6d3 344static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
dafc3bd5
CK		 345{
346 struct drm_device *dev = encoder->dev;
347 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 348 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
349 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
350 uint32_t offset = dig->afmt->offset;
dafc3bd5 351
c6543a6e 352 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
dafc3bd5
CK		 353}
354
355/*
356 * have buffer status changed since last call?
357 */
358int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
359{
360 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 361 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
dafc3bd5
CK		 362 int status, result;
363
cfcbd6d3 364 if (!dig->afmt || !dig->afmt->enabled)
dafc3bd5
CK		 365 return 0;
366
367 status = r600_hdmi_is_audio_buffer_filled(encoder);
cfcbd6d3
RM		 368 result = dig->afmt->last_buffer_filled_status != status;
369 dig->afmt->last_buffer_filled_status = status;
dafc3bd5
CK		 370
371 return result;
372}
373
374/*
375 * write the audio workaround status to the hardware
376 */
8f33a156 377void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
dafc3bd5
CK		 378{
379 struct drm_device *dev = encoder->dev;
380 struct radeon_device *rdev = dev->dev_private;
381 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3
RM		 382 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
383 uint32_t offset = dig->afmt->offset;
384 bool hdmi_audio_workaround = false; /* FIXME */
385 u32 value;
386
387 if (!hdmi_audio_workaround ||
388 r600_hdmi_is_audio_buffer_filled(encoder))
389 value = 0; /* disable workaround */
390 else
391 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
392 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
393 value, ~HDMI0_AUDIO_TEST_EN);
dafc3bd5
CK		 394}
395
8f33a156 396void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
b1f6f47e
AD		 397{
398 struct drm_device *dev = encoder->dev;
399 struct radeon_device *rdev = dev->dev_private;
400 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
401 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
731da21b 402 u32 base_rate = 24000;
1518dd8e
AD		 403 u32 max_ratio = clock / base_rate;
404 u32 dto_phase;
405 u32 dto_modulo = clock;
406 u32 wallclock_ratio;
407 u32 dto_cntl;
b1f6f47e
AD		 408
409 if (!dig || !dig->afmt)
410 return;
411
1518dd8e
AD		 412 if (max_ratio >= 8) {
413 dto_phase = 192 * 1000;
414 wallclock_ratio = 3;
415 } else if (max_ratio >= 4) {
416 dto_phase = 96 * 1000;
417 wallclock_ratio = 2;
418 } else if (max_ratio >= 2) {
419 dto_phase = 48 * 1000;
420 wallclock_ratio = 1;
421 } else {
422 dto_phase = 24 * 1000;
423 wallclock_ratio = 0;
424 }
425
b1f6f47e
AD		 426 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
427 * doesn't matter which one you use. Just use the first one.
428 */
b1f6f47e
AD		 429 /* XXX two dtos; generally use dto0 for hdmi */
430 /* Express [24MHz / target pixel clock] as an exact rational
431 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
432 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
433 */
58d327da 434 if (ASIC_IS_DCE32(rdev)) {
e1accbf0 435 if (dig->dig_encoder == 0) {
1518dd8e
AD		 436 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
437 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
438 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
439 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
440 WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
e1accbf0
AD		 441 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
442 } else {
1518dd8e
AD		 443 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
444 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
445 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
446 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
447 WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
e1accbf0
AD		 448 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
449 }
55d4e020 450 } else {
58d327da 451 /* according to the reg specs, this should DCE3.2 only, but in
55d4e020 452 * practice it seems to cover DCE2.0/3.0/3.1 as well.
58d327da
AD		 453 */
454 if (dig->dig_encoder == 0) {
455 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
456 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
457 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
458 } else {
459 WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);
460 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
461 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
462 }
1586505a 463 }
b1f6f47e 464}
dafc3bd5
CK		 465
466/*
467 * update the info frames with the data from the current display mode
468 */
469void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
470{
471 struct drm_device *dev = encoder->dev;
472 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 473 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
474 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
e3b2e034
TR		 475 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
476 struct hdmi_avi_infoframe frame;
cfcbd6d3 477 uint32_t offset;
2e93cac9 478 uint32_t acr_ctl;
e3b2e034 479 ssize_t err;
dafc3bd5 480
c2b4cacf
AD		 481 if (!dig || !dig->afmt)
482 return;
483
cfcbd6d3
RM		 484 /* Silent, r600_hdmi_enable will raise WARN for us */
485 if (!dig->afmt->enabled)
dafc3bd5 486 return;
cfcbd6d3 487 offset = dig->afmt->offset;
dafc3bd5 488
832eafaf
AD		 489 /* disable audio prior to setting up hw */
490 dig->afmt->pin = r600_audio_get_pin(rdev);
d3d8c141 491 r600_audio_enable(rdev, dig->afmt->pin, 0xf);
832eafaf 492
b1f6f47e 493 r600_audio_set_dto(encoder, mode->clock);
dafc3bd5 494
68706337
RM		 495 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
496 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
497 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
498 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
499 HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */
500 ~(HDMI0_AUDIO_SAMPLE_SEND |
501 HDMI0_AUDIO_DELAY_EN_MASK |
502 HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
503 HDMI0_60958_CS_UPDATE));
0ffae60c 504
2e93cac9
RM		 505 /* DCE 3.0 uses register that's normally for CRC_CONTROL */
506 acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
507 HDMI0_ACR_PACKET_CONTROL;
68706337
RM		 508 WREG32_P(acr_ctl + offset,
509 HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
510 HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
511 ~(HDMI0_ACR_SOURCE |
512 HDMI0_ACR_AUTO_SEND));
513
514 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
515 HDMI0_NULL_SEND | /* send null packets when required */
516 HDMI0_GC_SEND | /* send general control packets */
517 HDMI0_GC_CONT); /* send general control packets every frame */
518
519 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
520 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
521 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
522 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
523 HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
524
525 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
526 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
527 HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */
528 ~(HDMI0_AVI_INFO_LINE_MASK |
529 HDMI0_AUDIO_INFO_LINE_MASK));
530
531 WREG32_AND(HDMI0_GC + offset,
532 ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */
dafc3bd5 533
e3b2e034
TR		 534 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
535 if (err < 0) {
536 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
537 return;
538 }
dafc3bd5 539
e3b2e034
TR		 540 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
541 if (err < 0) {
542 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
543 return;
544 }
545
546 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
68706337
RM		 547
548 /* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */
549
550 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
551 ~(HDMI0_GENERIC0_SEND |
552 HDMI0_GENERIC0_CONT |
553 HDMI0_GENERIC0_UPDATE |
554 HDMI0_GENERIC1_SEND |
555 HDMI0_GENERIC1_CONT |
556 HDMI0_GENERIC0_LINE_MASK |
557 HDMI0_GENERIC1_LINE_MASK));
558
1c3439f2
RM		 559 r600_hdmi_update_ACR(encoder, mode->clock);
560
68706337
RM		 561 WREG32_P(HDMI0_60958_0 + offset,
562 HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
563 ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
564 HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
565
566 WREG32_P(HDMI0_60958_1 + offset,
567 HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
568 ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
569
25985edc 570 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
c6543a6e
RM		 571 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
572 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
573 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
574 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
dafc3bd5 575
832eafaf 576 /* enable audio after to setting up hw */
d3d8c141 577 r600_audio_enable(rdev, dig->afmt->pin, 0xf);
dafc3bd5
CK		 578}
579
8e4d9f81
RM		 580/**
581 * r600_hdmi_update_audio_settings - Update audio infoframe
582 *
583 * @encoder: drm encoder
584 *
585 * Gets info about current audio stream and updates audio infoframe.
dafc3bd5 586 */
58bd0863 587void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
dafc3bd5
CK		 588{
589 struct drm_device *dev = encoder->dev;
590 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 591 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
592 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
b530602f 593 struct r600_audio_pin audio = r600_audio_status(rdev);
e3b2e034
TR		 594 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
595 struct hdmi_audio_infoframe frame;
cfcbd6d3 596 uint32_t offset;
8e4d9f81 597 uint32_t value;
e3b2e034 598 ssize_t err;
dafc3bd5 599
cfcbd6d3 600 if (!dig->afmt || !dig->afmt->enabled)
dafc3bd5 601 return;
cfcbd6d3 602 offset = dig->afmt->offset;
dafc3bd5
CK		 603
604 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
605 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
3299de95 606 audio.channels, audio.rate, audio.bits_per_sample);
dafc3bd5 607 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
3299de95 608 (int)audio.status_bits, (int)audio.category_code);
dafc3bd5 609
e3b2e034
TR		 610 err = hdmi_audio_infoframe_init(&frame);
611 if (err < 0) {
612 DRM_ERROR("failed to setup audio infoframe\n");
613 return;
614 }
615
616 frame.channels = audio.channels;
617
618 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
619 if (err < 0) {
620 DRM_ERROR("failed to pack audio infoframe\n");
621 return;
622 }
dafc3bd5 623
8e4d9f81
RM		 624 value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
625 if (value & HDMI0_AUDIO_TEST_EN)
626 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
627 value & ~HDMI0_AUDIO_TEST_EN);
628
629 WREG32_OR(HDMI0_CONTROL + offset,
630 HDMI0_ERROR_ACK);
631
632 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
633 ~HDMI0_AUDIO_INFO_SOURCE);
634
e3b2e034 635 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
8e4d9f81
RM		 636
637 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
638 HDMI0_AUDIO_INFO_CONT |
639 HDMI0_AUDIO_INFO_UPDATE);
dafc3bd5
CK		 640}
641
dafc3bd5 642/*
2cd6218c 643 * enable the HDMI engine
dafc3bd5 644 */
a973bea1 645void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
dafc3bd5 646{
2cd6218c
RM		 647 struct drm_device *dev = encoder->dev;
648 struct radeon_device *rdev = dev->dev_private;
dafc3bd5 649 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 650 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
a973bea1 651 u32 hdmi = HDMI0_ERROR_ACK;
16823d16 652
c2b4cacf
AD		 653 if (!dig || !dig->afmt)
654 return;
655
cfcbd6d3 656 /* Silent, r600_hdmi_enable will raise WARN for us */
a973bea1
AD		 657 if (enable && dig->afmt->enabled)
658 return;
659 if (!enable && !dig->afmt->enabled)
cfcbd6d3 660 return;
64fb4fb0 661
4adb34ef
AD		 662 if (!enable && dig->afmt->pin) {
663 r600_audio_enable(rdev, dig->afmt->pin, 0);
664 dig->afmt->pin = NULL;
665 }
666
64fb4fb0 667 /* Older chipsets require setting HDMI and routing manually */
a973bea1
AD		 668 if (!ASIC_IS_DCE3(rdev)) {
669 if (enable)
670 hdmi |= HDMI0_ENABLE;
5715f67c
RM		 671 switch (radeon_encoder->encoder_id) {
672 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
a973bea1
AD		 673 if (enable) {
674 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
675 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
676 } else {
677 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
678 }
5715f67c
RM		 679 break;
680 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
a973bea1
AD		 681 if (enable) {
682 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
683 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
684 } else {
685 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
686 }
64fb4fb0
RM		 687 break;
688 case ENCODER_OBJECT_ID_INTERNAL_DDI:
a973bea1
AD		 689 if (enable) {
690 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
691 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
692 } else {
693 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
694 }
64fb4fb0
RM		 695 break;
696 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
a973bea1
AD		 697 if (enable)
698 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
5715f67c
RM		 699 break;
700 default:
64fb4fb0
RM		 701 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
702 radeon_encoder->encoder_id);
5715f67c
RM		 703 break;
704 }
a973bea1 705 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
5715f67c 706 }
2cd6218c 707
f122c610 708 if (rdev->irq.installed) {
f2594933 709 /* if irq is available use it */
9054ae1c 710 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
a973bea1 711 if (enable)
9054ae1c 712 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
a973bea1
AD		 713 else
714 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
f2594933 715 }
58bd0863 716
a973bea1 717 dig->afmt->enabled = enable;
cfcbd6d3 718
a973bea1
AD		 719 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
720 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
2cd6218c 721}
dafc3bd5 722
Linux 6.x block layer and io_uring tree(s)