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drm/radeon: ATOM Endian fix for atombios_crtc_program_pll()
[linux-2.6-block.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
771fe6b9 32#include "drmP.h"
3ce0a23d 33#include "radeon_drm.h"
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
771fe6b9 40
3ce0a23d
JG		 41#define PFP_UCODE_SIZE 576
42#define PM4_UCODE_SIZE 1792
d8f60cfc 43#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 44#define R700_PFP_UCODE_SIZE 848
45#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 46#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 47#define EVERGREEN_PFP_UCODE_SIZE 1120
48#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 49#define EVERGREEN_RLC_UCODE_SIZE 768
12727809 50#define CAYMAN_RLC_UCODE_SIZE 1024
3ce0a23d
JG		 51
52/* Firmware Names */
53MODULE_FIRMWARE("radeon/R600_pfp.bin");
54MODULE_FIRMWARE("radeon/R600_me.bin");
55MODULE_FIRMWARE("radeon/RV610_pfp.bin");
56MODULE_FIRMWARE("radeon/RV610_me.bin");
57MODULE_FIRMWARE("radeon/RV630_pfp.bin");
58MODULE_FIRMWARE("radeon/RV630_me.bin");
59MODULE_FIRMWARE("radeon/RV620_pfp.bin");
60MODULE_FIRMWARE("radeon/RV620_me.bin");
61MODULE_FIRMWARE("radeon/RV635_pfp.bin");
62MODULE_FIRMWARE("radeon/RV635_me.bin");
63MODULE_FIRMWARE("radeon/RV670_pfp.bin");
64MODULE_FIRMWARE("radeon/RV670_me.bin");
65MODULE_FIRMWARE("radeon/RS780_pfp.bin");
66MODULE_FIRMWARE("radeon/RS780_me.bin");
67MODULE_FIRMWARE("radeon/RV770_pfp.bin");
68MODULE_FIRMWARE("radeon/RV770_me.bin");
69MODULE_FIRMWARE("radeon/RV730_pfp.bin");
70MODULE_FIRMWARE("radeon/RV730_me.bin");
71MODULE_FIRMWARE("radeon/RV710_pfp.bin");
72MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 73MODULE_FIRMWARE("radeon/R600_rlc.bin");
74MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 75MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
76MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 77MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 78MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
79MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 80MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 81MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
82MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 83MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 84MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 85MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 86MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
439bd6cd
AD		 87MODULE_FIRMWARE("radeon/PALM_pfp.bin");
88MODULE_FIRMWARE("radeon/PALM_me.bin");
89MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
d5c5a72f
AD		 90MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
91MODULE_FIRMWARE("radeon/SUMO_me.bin");
92MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
93MODULE_FIRMWARE("radeon/SUMO2_me.bin");
3ce0a23d
JG		 94
95int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 96
1a029b76 97/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 98int r600_mc_wait_for_idle(struct radeon_device *rdev);
99void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 100void r600_fini(struct radeon_device *rdev);
45f9a39b 101void r600_irq_disable(struct radeon_device *rdev);
9e46a48d 102static void r600_pcie_gen2_enable(struct radeon_device *rdev);
771fe6b9 103
21a8122a 104/* get temperature in millidegrees */
20d391d7 105int rv6xx_get_temp(struct radeon_device *rdev)
21a8122a
AD		 106{
107 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
108 ASIC_T_SHIFT;
20d391d7 109 int actual_temp = temp & 0xff;
21a8122a 110
20d391d7
AD		 111 if (temp & 0x100)
112 actual_temp -= 256;
113
114 return actual_temp * 1000;
21a8122a
AD		 115}
116
ce8f5370 117void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 118{
119 int i;
120
ce8f5370
AD		 121 rdev->pm.dynpm_can_upclock = true;
122 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 123
124 /* power state array is low to high, default is first */
125 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
126 int min_power_state_index = 0;
127
128 if (rdev->pm.num_power_states > 2)
129 min_power_state_index = 1;
130
ce8f5370
AD		 131 switch (rdev->pm.dynpm_planned_action) {
132 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 133 rdev->pm.requested_power_state_index = min_power_state_index;
134 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 135 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 136 break;
ce8f5370 137 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 138 if (rdev->pm.current_power_state_index == min_power_state_index) {
139 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 140 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 141 } else {
142 if (rdev->pm.active_crtc_count > 1) {
143 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 144 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 145 continue;
146 else if (i >= rdev->pm.current_power_state_index) {
147 rdev->pm.requested_power_state_index =
148 rdev->pm.current_power_state_index;
149 break;
150 } else {
151 rdev->pm.requested_power_state_index = i;
152 break;
153 }
154 }
773c3fa3
AD		 155 } else {
156 if (rdev->pm.current_power_state_index == 0)
157 rdev->pm.requested_power_state_index =
158 rdev->pm.num_power_states - 1;
159 else
160 rdev->pm.requested_power_state_index =
161 rdev->pm.current_power_state_index - 1;
162 }
a48b9b4e
AD		 163 }
164 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 165 /* don't use the power state if crtcs are active and no display flag is set */
166 if ((rdev->pm.active_crtc_count > 0) &&
167 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
168 clock_info[rdev->pm.requested_clock_mode_index].flags &
169 RADEON_PM_MODE_NO_DISPLAY)) {
170 rdev->pm.requested_power_state_index++;
171 }
a48b9b4e 172 break;
ce8f5370 173 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 174 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
175 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 176 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 177 } else {
178 if (rdev->pm.active_crtc_count > 1) {
179 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 180 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 181 continue;
182 else if (i <= rdev->pm.current_power_state_index) {
183 rdev->pm.requested_power_state_index =
184 rdev->pm.current_power_state_index;
185 break;
186 } else {
187 rdev->pm.requested_power_state_index = i;
188 break;
189 }
190 }
191 } else
192 rdev->pm.requested_power_state_index =
193 rdev->pm.current_power_state_index + 1;
194 }
195 rdev->pm.requested_clock_mode_index = 0;
196 break;
ce8f5370 197 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 198 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
199 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 200 rdev->pm.dynpm_can_upclock = false;
58e21dff 201 break;
ce8f5370 202 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 203 default:
204 DRM_ERROR("Requested mode for not defined action\n");
205 return;
206 }
207 } else {
208 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
209 /* for now just select the first power state and switch between clock modes */
210 /* power state array is low to high, default is first (0) */
211 if (rdev->pm.active_crtc_count > 1) {
212 rdev->pm.requested_power_state_index = -1;
213 /* start at 1 as we don't want the default mode */
214 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 215 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 216 continue;
217 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
218 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
219 rdev->pm.requested_power_state_index = i;
220 break;
221 }
222 }
223 /* if nothing selected, grab the default state. */
224 if (rdev->pm.requested_power_state_index == -1)
225 rdev->pm.requested_power_state_index = 0;
226 } else
227 rdev->pm.requested_power_state_index = 1;
228
ce8f5370
AD		 229 switch (rdev->pm.dynpm_planned_action) {
230 case DYNPM_ACTION_MINIMUM:
a48b9b4e 231 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 232 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 233 break;
ce8f5370 234 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 235 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
236 if (rdev->pm.current_clock_mode_index == 0) {
237 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 238 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 239 } else
240 rdev->pm.requested_clock_mode_index =
241 rdev->pm.current_clock_mode_index - 1;
242 } else {
243 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 244 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 245 }
d7311171
AD		 246 /* don't use the power state if crtcs are active and no display flag is set */
247 if ((rdev->pm.active_crtc_count > 0) &&
248 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
249 clock_info[rdev->pm.requested_clock_mode_index].flags &
250 RADEON_PM_MODE_NO_DISPLAY)) {
251 rdev->pm.requested_clock_mode_index++;
252 }
a48b9b4e 253 break;
ce8f5370 254 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 255 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
256 if (rdev->pm.current_clock_mode_index ==
257 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
258 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 259 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 260 } else
261 rdev->pm.requested_clock_mode_index =
262 rdev->pm.current_clock_mode_index + 1;
263 } else {
264 rdev->pm.requested_clock_mode_index =
265 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 266 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 267 }
268 break;
ce8f5370 269 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 270 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
271 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 272 rdev->pm.dynpm_can_upclock = false;
58e21dff 273 break;
ce8f5370 274 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 275 default:
276 DRM_ERROR("Requested mode for not defined action\n");
277 return;
278 }
279 }
280
d9fdaafb 281 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 282 rdev->pm.power_state[rdev->pm.requested_power_state_index].
283 clock_info[rdev->pm.requested_clock_mode_index].sclk,
284 rdev->pm.power_state[rdev->pm.requested_power_state_index].
285 clock_info[rdev->pm.requested_clock_mode_index].mclk,
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].
287 pcie_lanes);
a48b9b4e
AD		 288}
289
ce8f5370
AD		 290static int r600_pm_get_type_index(struct radeon_device *rdev,
291 enum radeon_pm_state_type ps_type,
292 int instance)
bae6b562 293{
ce8f5370
AD		 294 int i;
295 int found_instance = -1;
bae6b562 296
ce8f5370
AD		 297 for (i = 0; i < rdev->pm.num_power_states; i++) {
298 if (rdev->pm.power_state[i].type == ps_type) {
299 found_instance++;
300 if (found_instance == instance)
301 return i;
a424816f 302 }
ce8f5370
AD		 303 }
304 /* return default if no match */
305 return rdev->pm.default_power_state_index;
306}
307
308void rs780_pm_init_profile(struct radeon_device *rdev)
309{
310 if (rdev->pm.num_power_states == 2) {
311 /* default */
312 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
314 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
316 /* low sh */
317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 321 /* mid sh */
322 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 326 /* high sh */
327 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
329 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
331 /* low mh */
332 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 336 /* mid mh */
337 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 341 /* high mh */
342 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
344 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
346 } else if (rdev->pm.num_power_states == 3) {
347 /* default */
348 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
349 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
350 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
351 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
352 /* low sh */
353 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
354 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
355 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
356 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 357 /* mid sh */
358 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
360 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 362 /* high sh */
363 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
364 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
365 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
366 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
367 /* low mh */
368 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
369 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
370 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 372 /* mid mh */
373 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
374 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
375 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 377 /* high mh */
378 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
379 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
380 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
382 } else {
383 /* default */
384 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
385 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
386 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
388 /* low sh */
389 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
390 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
391 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
392 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 393 /* mid sh */
394 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
395 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
396 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
397 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 398 /* high sh */
399 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
400 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
401 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
402 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
403 /* low mh */
404 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
405 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
406 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
407 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 408 /* mid mh */
409 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
410 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
411 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
412 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 413 /* high mh */
414 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
415 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
416 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
417 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
418 }
419}
bae6b562 420
ce8f5370
AD		 421void r600_pm_init_profile(struct radeon_device *rdev)
422{
423 if (rdev->family == CHIP_R600) {
424 /* XXX */
425 /* default */
426 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
427 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 429 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 430 /* low sh */
431 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
432 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 434 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 435 /* mid sh */
436 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
437 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
439 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 440 /* high sh */
441 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
442 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 444 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 445 /* low mh */
446 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
447 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
448 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 449 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 450 /* mid mh */
451 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
452 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
453 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
454 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 455 /* high mh */
456 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
457 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
458 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 459 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 460 } else {
461 if (rdev->pm.num_power_states < 4) {
462 /* default */
463 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
464 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
465 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
466 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
467 /* low sh */
4bff5171
AD		 468 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
469 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 470 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 471 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
472 /* mid sh */
473 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
474 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
475 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
476 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 477 /* high sh */
4bff5171
AD		 478 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
479 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 480 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
481 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
482 /* low mh */
4bff5171
AD		 483 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
484 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 485 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 486 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
487 /* low mh */
488 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
489 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
490 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
491 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 492 /* high mh */
4bff5171
AD		 493 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
494 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 495 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
496 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
497 } else {
498 /* default */
499 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
500 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
501 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
502 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
503 /* low sh */
4bff5171
AD		 504 if (rdev->flags & RADEON_IS_MOBILITY) {
505 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
506 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
507 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
508 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
509 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21 510 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 511 } else {
512 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
513 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
514 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
515 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
516 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 517 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
518 }
519 /* mid sh */
520 if (rdev->flags & RADEON_IS_MOBILITY) {
521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
522 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
523 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
524 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
525 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
526 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
527 } else {
528 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
529 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
530 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
531 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
532 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
533 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
4bff5171 534 }
ce8f5370 535 /* high sh */
4bff5171
AD		 536 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
537 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
538 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
539 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
ce8f5370
AD		 540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
541 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
542 /* low mh */
4bff5171
AD		 543 if (rdev->flags & RADEON_IS_MOBILITY) {
544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
545 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
546 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
547 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
548 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21 549 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
4bff5171
AD		 550 } else {
551 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
552 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
553 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
554 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
555 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 556 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
557 }
558 /* mid mh */
559 if (rdev->flags & RADEON_IS_MOBILITY) {
560 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
561 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
562 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
563 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
566 } else {
567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
568 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
569 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
570 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
571 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
572 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
4bff5171 573 }
ce8f5370 574 /* high mh */
4bff5171
AD		 575 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
576 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
577 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
578 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
ce8f5370
AD		 579 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
580 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
581 }
582 }
bae6b562
AD		 583}
584
49e02b73
AD		 585void r600_pm_misc(struct radeon_device *rdev)
586{
a081a9d6
RM		 587 int req_ps_idx = rdev->pm.requested_power_state_index;
588 int req_cm_idx = rdev->pm.requested_clock_mode_index;
589 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
590 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 591
4d60173f 592 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
a377e187
AD		 593 /* 0xff01 is a flag rather then an actual voltage */
594 if (voltage->voltage == 0xff01)
595 return;
4d60173f 596 if (voltage->voltage != rdev->pm.current_vddc) {
8a83ec5e 597 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 598 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 599 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 600 }
601 }
49e02b73
AD		 602}
603
def9ba9c
AD		 604bool r600_gui_idle(struct radeon_device *rdev)
605{
606 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
607 return false;
608 else
609 return true;
610}
611
e0df1ac5
AD		 612/* hpd for digital panel detect/disconnect */
613bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
614{
615 bool connected = false;
616
617 if (ASIC_IS_DCE3(rdev)) {
618 switch (hpd) {
619 case RADEON_HPD_1:
620 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
621 connected = true;
622 break;
623 case RADEON_HPD_2:
624 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
625 connected = true;
626 break;
627 case RADEON_HPD_3:
628 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
629 connected = true;
630 break;
631 case RADEON_HPD_4:
632 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
633 connected = true;
634 break;
635 /* DCE 3.2 */
636 case RADEON_HPD_5:
637 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
638 connected = true;
639 break;
640 case RADEON_HPD_6:
641 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
642 connected = true;
643 break;
644 default:
645 break;
646 }
647 } else {
648 switch (hpd) {
649 case RADEON_HPD_1:
650 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
651 connected = true;
652 break;
653 case RADEON_HPD_2:
654 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
655 connected = true;
656 break;
657 case RADEON_HPD_3:
658 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
659 connected = true;
660 break;
661 default:
662 break;
663 }
664 }
665 return connected;
666}
667
668void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 669 enum radeon_hpd_id hpd)
e0df1ac5
AD		 670{
671 u32 tmp;
672 bool connected = r600_hpd_sense(rdev, hpd);
673
674 if (ASIC_IS_DCE3(rdev)) {
675 switch (hpd) {
676 case RADEON_HPD_1:
677 tmp = RREG32(DC_HPD1_INT_CONTROL);
678 if (connected)
679 tmp &= ~DC_HPDx_INT_POLARITY;
680 else
681 tmp |= DC_HPDx_INT_POLARITY;
682 WREG32(DC_HPD1_INT_CONTROL, tmp);
683 break;
684 case RADEON_HPD_2:
685 tmp = RREG32(DC_HPD2_INT_CONTROL);
686 if (connected)
687 tmp &= ~DC_HPDx_INT_POLARITY;
688 else
689 tmp |= DC_HPDx_INT_POLARITY;
690 WREG32(DC_HPD2_INT_CONTROL, tmp);
691 break;
692 case RADEON_HPD_3:
693 tmp = RREG32(DC_HPD3_INT_CONTROL);
694 if (connected)
695 tmp &= ~DC_HPDx_INT_POLARITY;
696 else
697 tmp |= DC_HPDx_INT_POLARITY;
698 WREG32(DC_HPD3_INT_CONTROL, tmp);
699 break;
700 case RADEON_HPD_4:
701 tmp = RREG32(DC_HPD4_INT_CONTROL);
702 if (connected)
703 tmp &= ~DC_HPDx_INT_POLARITY;
704 else
705 tmp |= DC_HPDx_INT_POLARITY;
706 WREG32(DC_HPD4_INT_CONTROL, tmp);
707 break;
708 case RADEON_HPD_5:
709 tmp = RREG32(DC_HPD5_INT_CONTROL);
710 if (connected)
711 tmp &= ~DC_HPDx_INT_POLARITY;
712 else
713 tmp |= DC_HPDx_INT_POLARITY;
714 WREG32(DC_HPD5_INT_CONTROL, tmp);
715 break;
716 /* DCE 3.2 */
717 case RADEON_HPD_6:
718 tmp = RREG32(DC_HPD6_INT_CONTROL);
719 if (connected)
720 tmp &= ~DC_HPDx_INT_POLARITY;
721 else
722 tmp |= DC_HPDx_INT_POLARITY;
723 WREG32(DC_HPD6_INT_CONTROL, tmp);
724 break;
725 default:
726 break;
727 }
728 } else {
729 switch (hpd) {
730 case RADEON_HPD_1:
731 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
732 if (connected)
733 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
734 else
735 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
736 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
737 break;
738 case RADEON_HPD_2:
739 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
740 if (connected)
741 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
742 else
743 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
744 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
745 break;
746 case RADEON_HPD_3:
747 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
748 if (connected)
749 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
750 else
751 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
752 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
753 break;
754 default:
755 break;
756 }
757 }
758}
759
760void r600_hpd_init(struct radeon_device *rdev)
761{
762 struct drm_device *dev = rdev->ddev;
763 struct drm_connector *connector;
764
765 if (ASIC_IS_DCE3(rdev)) {
766 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
767 if (ASIC_IS_DCE32(rdev))
768 tmp |= DC_HPDx_EN;
769
770 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
771 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
772 switch (radeon_connector->hpd.hpd) {
773 case RADEON_HPD_1:
774 WREG32(DC_HPD1_CONTROL, tmp);
775 rdev->irq.hpd[0] = true;
776 break;
777 case RADEON_HPD_2:
778 WREG32(DC_HPD2_CONTROL, tmp);
779 rdev->irq.hpd[1] = true;
780 break;
781 case RADEON_HPD_3:
782 WREG32(DC_HPD3_CONTROL, tmp);
783 rdev->irq.hpd[2] = true;
784 break;
785 case RADEON_HPD_4:
786 WREG32(DC_HPD4_CONTROL, tmp);
787 rdev->irq.hpd[3] = true;
788 break;
789 /* DCE 3.2 */
790 case RADEON_HPD_5:
791 WREG32(DC_HPD5_CONTROL, tmp);
792 rdev->irq.hpd[4] = true;
793 break;
794 case RADEON_HPD_6:
795 WREG32(DC_HPD6_CONTROL, tmp);
796 rdev->irq.hpd[5] = true;
797 break;
798 default:
799 break;
800 }
801 }
802 } else {
803 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
804 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
805 switch (radeon_connector->hpd.hpd) {
806 case RADEON_HPD_1:
807 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
808 rdev->irq.hpd[0] = true;
809 break;
810 case RADEON_HPD_2:
811 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
812 rdev->irq.hpd[1] = true;
813 break;
814 case RADEON_HPD_3:
815 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
816 rdev->irq.hpd[2] = true;
817 break;
818 default:
819 break;
820 }
821 }
822 }
003e69f9
JG		 823 if (rdev->irq.installed)
824 r600_irq_set(rdev);
e0df1ac5
AD		 825}
826
827void r600_hpd_fini(struct radeon_device *rdev)
828{
829 struct drm_device *dev = rdev->ddev;
830 struct drm_connector *connector;
831
832 if (ASIC_IS_DCE3(rdev)) {
833 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
834 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
835 switch (radeon_connector->hpd.hpd) {
836 case RADEON_HPD_1:
837 WREG32(DC_HPD1_CONTROL, 0);
838 rdev->irq.hpd[0] = false;
839 break;
840 case RADEON_HPD_2:
841 WREG32(DC_HPD2_CONTROL, 0);
842 rdev->irq.hpd[1] = false;
843 break;
844 case RADEON_HPD_3:
845 WREG32(DC_HPD3_CONTROL, 0);
846 rdev->irq.hpd[2] = false;
847 break;
848 case RADEON_HPD_4:
849 WREG32(DC_HPD4_CONTROL, 0);
850 rdev->irq.hpd[3] = false;
851 break;
852 /* DCE 3.2 */
853 case RADEON_HPD_5:
854 WREG32(DC_HPD5_CONTROL, 0);
855 rdev->irq.hpd[4] = false;
856 break;
857 case RADEON_HPD_6:
858 WREG32(DC_HPD6_CONTROL, 0);
859 rdev->irq.hpd[5] = false;
860 break;
861 default:
862 break;
863 }
864 }
865 } else {
866 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
867 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
868 switch (radeon_connector->hpd.hpd) {
869 case RADEON_HPD_1:
870 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
871 rdev->irq.hpd[0] = false;
872 break;
873 case RADEON_HPD_2:
874 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
875 rdev->irq.hpd[1] = false;
876 break;
877 case RADEON_HPD_3:
878 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
879 rdev->irq.hpd[2] = false;
880 break;
881 default:
882 break;
883 }
884 }
885 }
886}
887
771fe6b9 888/*
3ce0a23d 889 * R600 PCIE GART
771fe6b9 890 */
3ce0a23d
JG		 891void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
892{
893 unsigned i;
894 u32 tmp;
895
2e98f10a 896 /* flush hdp cache so updates hit vram */
f3886f85
AD		 897 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
898 !(rdev->flags & RADEON_IS_AGP)) {
812d0469
AD		 899 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
900 u32 tmp;
901
902 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
903 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 904 * This seems to cause problems on some AGP cards. Just use the old
905 * method for them.
812d0469
AD		 906 */
907 WREG32(HDP_DEBUG1, 0);
908 tmp = readl((void __iomem *)ptr);
909 } else
910 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 911
3ce0a23d
JG		 912 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
913 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
914 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
915 for (i = 0; i < rdev->usec_timeout; i++) {
916 /* read MC_STATUS */
917 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
918 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
919 if (tmp == 2) {
920 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
921 return;
922 }
923 if (tmp) {
924 return;
925 }
926 udelay(1);
927 }
928}
929
4aac0473 930int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 931{
4aac0473 932 int r;
3ce0a23d 933
4aac0473 934 if (rdev->gart.table.vram.robj) {
fce7d61b 935 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 936 return 0;
937 }
3ce0a23d
JG		 938 /* Initialize common gart structure */
939 r = radeon_gart_init(rdev);
4aac0473 940 if (r)
3ce0a23d 941 return r;
3ce0a23d 942 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 943 return radeon_gart_table_vram_alloc(rdev);
944}
945
946int r600_pcie_gart_enable(struct radeon_device *rdev)
947{
948 u32 tmp;
949 int r, i;
950
951 if (rdev->gart.table.vram.robj == NULL) {
952 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
953 return -EINVAL;
771fe6b9 954 }
4aac0473
JG		 955 r = radeon_gart_table_vram_pin(rdev);
956 if (r)
957 return r;
82568565 958 radeon_gart_restore(rdev);
bc1a631e 959
3ce0a23d
JG		 960 /* Setup L2 cache */
961 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
962 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
963 EFFECTIVE_L2_QUEUE_SIZE(7));
964 WREG32(VM_L2_CNTL2, 0);
965 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
966 /* Setup TLB control */
967 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
968 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
969 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
970 ENABLE_WAIT_L2_QUERY;
971 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
972 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
973 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
974 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
980 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
981 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
982 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
983 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
984 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
985 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 986 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 987 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
988 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
989 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
990 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
991 (u32)(rdev->dummy_page.addr >> 12));
992 for (i = 1; i < 7; i++)
993 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 994
3ce0a23d
JG		 995 r600_pcie_gart_tlb_flush(rdev);
996 rdev->gart.ready = true;
771fe6b9
JG		 997 return 0;
998}
999
3ce0a23d 1000void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 1001{
3ce0a23d 1002 u32 tmp;
4c788679 1003 int i, r;
771fe6b9 1004
3ce0a23d
JG		 1005 /* Disable all tables */
1006 for (i = 0; i < 7; i++)
1007 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 1008
3ce0a23d
JG		 1009 /* Disable L2 cache */
1010 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1011 EFFECTIVE_L2_QUEUE_SIZE(7));
1012 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1013 /* Setup L1 TLB control */
1014 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1015 ENABLE_WAIT_L2_QUERY;
1016 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1017 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1018 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1019 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1020 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1021 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1022 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1023 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1024 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1025 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1026 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1027 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1028 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1029 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
4aac0473 1030 if (rdev->gart.table.vram.robj) {
4c788679
JG		 1031 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1032 if (likely(r == 0)) {
1033 radeon_bo_kunmap(rdev->gart.table.vram.robj);
1034 radeon_bo_unpin(rdev->gart.table.vram.robj);
1035 radeon_bo_unreserve(rdev->gart.table.vram.robj);
1036 }
4aac0473
JG		 1037 }
1038}
1039
1040void r600_pcie_gart_fini(struct radeon_device *rdev)
1041{
f9274562 1042 radeon_gart_fini(rdev);
4aac0473
JG		 1043 r600_pcie_gart_disable(rdev);
1044 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1045}
1046
1a029b76
JG		 1047void r600_agp_enable(struct radeon_device *rdev)
1048{
1049 u32 tmp;
1050 int i;
1051
1052 /* Setup L2 cache */
1053 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1054 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1055 EFFECTIVE_L2_QUEUE_SIZE(7));
1056 WREG32(VM_L2_CNTL2, 0);
1057 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1058 /* Setup TLB control */
1059 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1060 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1061 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1062 ENABLE_WAIT_L2_QUERY;
1063 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1064 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1065 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1066 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1067 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1068 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1069 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1070 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1071 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1072 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1073 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1074 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1075 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1076 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1077 for (i = 0; i < 7; i++)
1078 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1079}
1080
771fe6b9
JG		 1081int r600_mc_wait_for_idle(struct radeon_device *rdev)
1082{
3ce0a23d
JG		 1083 unsigned i;
1084 u32 tmp;
1085
1086 for (i = 0; i < rdev->usec_timeout; i++) {
1087 /* read MC_STATUS */
1088 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1089 if (!tmp)
1090 return 0;
1091 udelay(1);
1092 }
1093 return -1;
771fe6b9
JG		 1094}
1095
a3c1945a 1096static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1097{
a3c1945a 1098 struct rv515_mc_save save;
3ce0a23d
JG		 1099 u32 tmp;
1100 int i, j;
771fe6b9 1101
3ce0a23d
JG		 1102 /* Initialize HDP */
1103 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1104 WREG32((0x2c14 + j), 0x00000000);
1105 WREG32((0x2c18 + j), 0x00000000);
1106 WREG32((0x2c1c + j), 0x00000000);
1107 WREG32((0x2c20 + j), 0x00000000);
1108 WREG32((0x2c24 + j), 0x00000000);
1109 }
1110 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1111
a3c1945a 1112 rv515_mc_stop(rdev, &save);
3ce0a23d 1113 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1114 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1115 }
a3c1945a 1116 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1117 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1118 /* Update configuration */
1a029b76
JG		 1119 if (rdev->flags & RADEON_IS_AGP) {
1120 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1121 /* VRAM before AGP */
1122 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1123 rdev->mc.vram_start >> 12);
1124 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1125 rdev->mc.gtt_end >> 12);
1126 } else {
1127 /* VRAM after AGP */
1128 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1129 rdev->mc.gtt_start >> 12);
1130 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1131 rdev->mc.vram_end >> 12);
1132 }
1133 } else {
1134 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1135 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1136 }
3ce0a23d 1137 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1a029b76 1138 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1139 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1140 WREG32(MC_VM_FB_LOCATION, tmp);
1141 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1142 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1143 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1144 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1145 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1146 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1147 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1148 } else {
1149 WREG32(MC_VM_AGP_BASE, 0);
1150 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1151 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1152 }
3ce0a23d 1153 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1154 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1155 }
a3c1945a 1156 rv515_mc_resume(rdev, &save);
698443d9
DA		 1157 /* we need to own VRAM, so turn off the VGA renderer here
1158 * to stop it overwriting our objects */
d39c3b89 1159 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1160}
1161
d594e46a
JG		 1162/**
1163 * r600_vram_gtt_location - try to find VRAM & GTT location
1164 * @rdev: radeon device structure holding all necessary informations
1165 * @mc: memory controller structure holding memory informations
1166 *
1167 * Function will place try to place VRAM at same place as in CPU (PCI)
1168 * address space as some GPU seems to have issue when we reprogram at
1169 * different address space.
1170 *
1171 * If there is not enough space to fit the unvisible VRAM after the
1172 * aperture then we limit the VRAM size to the aperture.
1173 *
1174 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1175 * them to be in one from GPU point of view so that we can program GPU to
1176 * catch access outside them (weird GPU policy see ??).
1177 *
1178 * This function will never fails, worst case are limiting VRAM or GTT.
1179 *
1180 * Note: GTT start, end, size should be initialized before calling this
1181 * function on AGP platform.
1182 */
0ef0c1f7 1183static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
d594e46a
JG		 1184{
1185 u64 size_bf, size_af;
1186
1187 if (mc->mc_vram_size > 0xE0000000) {
1188 /* leave room for at least 512M GTT */
1189 dev_warn(rdev->dev, "limiting VRAM\n");
1190 mc->real_vram_size = 0xE0000000;
1191 mc->mc_vram_size = 0xE0000000;
1192 }
1193 if (rdev->flags & RADEON_IS_AGP) {
1194 size_bf = mc->gtt_start;
1195 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1196 if (size_bf > size_af) {
1197 if (mc->mc_vram_size > size_bf) {
1198 dev_warn(rdev->dev, "limiting VRAM\n");
1199 mc->real_vram_size = size_bf;
1200 mc->mc_vram_size = size_bf;
1201 }
1202 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1203 } else {
1204 if (mc->mc_vram_size > size_af) {
1205 dev_warn(rdev->dev, "limiting VRAM\n");
1206 mc->real_vram_size = size_af;
1207 mc->mc_vram_size = size_af;
1208 }
1209 mc->vram_start = mc->gtt_end;
1210 }
1211 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1212 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1213 mc->mc_vram_size >> 20, mc->vram_start,
1214 mc->vram_end, mc->real_vram_size >> 20);
1215 } else {
1216 u64 base = 0;
8961d52d
AD		 1217 if (rdev->flags & RADEON_IS_IGP) {
1218 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1219 base <<= 24;
1220 }
d594e46a 1221 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1222 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1223 radeon_gtt_location(rdev, mc);
1224 }
1225}
1226
3ce0a23d 1227int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1228{
3ce0a23d 1229 u32 tmp;
5885b7a9 1230 int chansize, numchan;
771fe6b9 1231
3ce0a23d 1232 /* Get VRAM informations */
771fe6b9 1233 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1234 tmp = RREG32(RAMCFG);
1235 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1236 chansize = 16;
3ce0a23d 1237 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1238 chansize = 64;
1239 } else {
1240 chansize = 32;
1241 }
5885b7a9
AD		 1242 tmp = RREG32(CHMAP);
1243 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1244 case 0:
1245 default:
1246 numchan = 1;
1247 break;
1248 case 1:
1249 numchan = 2;
1250 break;
1251 case 2:
1252 numchan = 4;
1253 break;
1254 case 3:
1255 numchan = 8;
1256 break;
771fe6b9 1257 }
5885b7a9 1258 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1259 /* Could aper size report 0 ? */
01d73a69
JC		 1260 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1261 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1262 /* Setup GPU memory space */
1263 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1264 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1265 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1266 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1267
f892034a
AD		 1268 if (rdev->flags & RADEON_IS_IGP) {
1269 rs690_pm_info(rdev);
06b6476d 1270 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f892034a 1271 }
f47299c5 1272 radeon_update_bandwidth_info(rdev);
3ce0a23d 1273 return 0;
771fe6b9
JG		 1274}
1275
3ce0a23d
JG		 1276/* We doesn't check that the GPU really needs a reset we simply do the
1277 * reset, it's up to the caller to determine if the GPU needs one. We
1278 * might add an helper function to check that.
1279 */
1280int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 1281{
a3c1945a 1282 struct rv515_mc_save save;
3ce0a23d
JG		 1283 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1284 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1285 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1286 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1287 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1288 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1289 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1290 S_008010_GUI_ACTIVE(1);
1291 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1292 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1293 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1294 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1295 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1296 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1297 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1298 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 1299 u32 tmp;
771fe6b9 1300
8d96fe93
AD		 1301 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1302 return 0;
1303
1a029b76
JG		 1304 dev_info(rdev->dev, "GPU softreset \n");
1305 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1306 RREG32(R_008010_GRBM_STATUS));
1307 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 1308 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 1309 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1310 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 1311 rv515_mc_stop(rdev, &save);
1312 if (r600_mc_wait_for_idle(rdev)) {
1313 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1314 }
3ce0a23d 1315 /* Disable CP parsing/prefetching */
90aca4d2 1316 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 1317 /* Check if any of the rendering block is busy and reset it */
1318 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1319 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 1320 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 1321 S_008020_SOFT_RESET_DB(1) |
1322 S_008020_SOFT_RESET_CB(1) |
1323 S_008020_SOFT_RESET_PA(1) |
1324 S_008020_SOFT_RESET_SC(1) |
1325 S_008020_SOFT_RESET_SMX(1) |
1326 S_008020_SOFT_RESET_SPI(1) |
1327 S_008020_SOFT_RESET_SX(1) |
1328 S_008020_SOFT_RESET_SH(1) |
1329 S_008020_SOFT_RESET_TC(1) |
1330 S_008020_SOFT_RESET_TA(1) |
1331 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1332 S_008020_SOFT_RESET_VGT(1);
1a029b76 1333 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1334 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1335 RREG32(R_008020_GRBM_SOFT_RESET);
1336 mdelay(15);
3ce0a23d 1337 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1338 }
1339 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1340 tmp = S_008020_SOFT_RESET_CP(1);
1341 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1342 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1343 RREG32(R_008020_GRBM_SOFT_RESET);
1344 mdelay(15);
3ce0a23d 1345 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 1346 /* Wait a little for things to settle down */
225758d8 1347 mdelay(1);
1a029b76
JG		 1348 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1349 RREG32(R_008010_GRBM_STATUS));
1350 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1351 RREG32(R_008014_GRBM_STATUS2));
1352 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1353 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 1354 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 1355 return 0;
1356}
1357
225758d8
JG		 1358bool r600_gpu_is_lockup(struct radeon_device *rdev)
1359{
1360 u32 srbm_status;
1361 u32 grbm_status;
1362 u32 grbm_status2;
e29ff729 1363 struct r100_gpu_lockup *lockup;
225758d8
JG		 1364 int r;
1365
e29ff729
AD		 1366 if (rdev->family >= CHIP_RV770)
1367 lockup = &rdev->config.rv770.lockup;
1368 else
1369 lockup = &rdev->config.r600.lockup;
1370
225758d8
JG		 1371 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1372 grbm_status = RREG32(R_008010_GRBM_STATUS);
1373 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1374 if (!G_008010_GUI_ACTIVE(grbm_status)) {
e29ff729 1375 r100_gpu_lockup_update(lockup, &rdev->cp);
225758d8
JG		 1376 return false;
1377 }
1378 /* force CP activities */
1379 r = radeon_ring_lock(rdev, 2);
1380 if (!r) {
1381 /* PACKET2 NOP */
1382 radeon_ring_write(rdev, 0x80000000);
1383 radeon_ring_write(rdev, 0x80000000);
1384 radeon_ring_unlock_commit(rdev);
1385 }
1386 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
e29ff729 1387 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
225758d8
JG		 1388}
1389
a2d07b74 1390int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 1391{
1392 return r600_gpu_soft_reset(rdev);
1393}
1394
1395static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1396 u32 num_backends,
1397 u32 backend_disable_mask)
1398{
1399 u32 backend_map = 0;
1400 u32 enabled_backends_mask;
1401 u32 enabled_backends_count;
1402 u32 cur_pipe;
1403 u32 swizzle_pipe[R6XX_MAX_PIPES];
1404 u32 cur_backend;
1405 u32 i;
1406
1407 if (num_tile_pipes > R6XX_MAX_PIPES)
1408 num_tile_pipes = R6XX_MAX_PIPES;
1409 if (num_tile_pipes < 1)
1410 num_tile_pipes = 1;
1411 if (num_backends > R6XX_MAX_BACKENDS)
1412 num_backends = R6XX_MAX_BACKENDS;
1413 if (num_backends < 1)
1414 num_backends = 1;
1415
1416 enabled_backends_mask = 0;
1417 enabled_backends_count = 0;
1418 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1419 if (((backend_disable_mask >> i) & 1) == 0) {
1420 enabled_backends_mask |= (1 << i);
1421 ++enabled_backends_count;
1422 }
1423 if (enabled_backends_count == num_backends)
1424 break;
1425 }
1426
1427 if (enabled_backends_count == 0) {
1428 enabled_backends_mask = 1;
1429 enabled_backends_count = 1;
1430 }
1431
1432 if (enabled_backends_count != num_backends)
1433 num_backends = enabled_backends_count;
1434
1435 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1436 switch (num_tile_pipes) {
1437 case 1:
1438 swizzle_pipe[0] = 0;
1439 break;
1440 case 2:
1441 swizzle_pipe[0] = 0;
1442 swizzle_pipe[1] = 1;
1443 break;
1444 case 3:
1445 swizzle_pipe[0] = 0;
1446 swizzle_pipe[1] = 1;
1447 swizzle_pipe[2] = 2;
1448 break;
1449 case 4:
1450 swizzle_pipe[0] = 0;
1451 swizzle_pipe[1] = 1;
1452 swizzle_pipe[2] = 2;
1453 swizzle_pipe[3] = 3;
1454 break;
1455 case 5:
1456 swizzle_pipe[0] = 0;
1457 swizzle_pipe[1] = 1;
1458 swizzle_pipe[2] = 2;
1459 swizzle_pipe[3] = 3;
1460 swizzle_pipe[4] = 4;
1461 break;
1462 case 6:
1463 swizzle_pipe[0] = 0;
1464 swizzle_pipe[1] = 2;
1465 swizzle_pipe[2] = 4;
1466 swizzle_pipe[3] = 5;
1467 swizzle_pipe[4] = 1;
1468 swizzle_pipe[5] = 3;
1469 break;
1470 case 7:
1471 swizzle_pipe[0] = 0;
1472 swizzle_pipe[1] = 2;
1473 swizzle_pipe[2] = 4;
1474 swizzle_pipe[3] = 6;
1475 swizzle_pipe[4] = 1;
1476 swizzle_pipe[5] = 3;
1477 swizzle_pipe[6] = 5;
1478 break;
1479 case 8:
1480 swizzle_pipe[0] = 0;
1481 swizzle_pipe[1] = 2;
1482 swizzle_pipe[2] = 4;
1483 swizzle_pipe[3] = 6;
1484 swizzle_pipe[4] = 1;
1485 swizzle_pipe[5] = 3;
1486 swizzle_pipe[6] = 5;
1487 swizzle_pipe[7] = 7;
1488 break;
1489 }
1490
1491 cur_backend = 0;
1492 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1493 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1494 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1495
1496 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1497
1498 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1499 }
1500
1501 return backend_map;
1502}
1503
1504int r600_count_pipe_bits(uint32_t val)
1505{
1506 int i, ret = 0;
1507
1508 for (i = 0; i < 32; i++) {
1509 ret += val & 1;
1510 val >>= 1;
1511 }
1512 return ret;
771fe6b9
JG		 1513}
1514
3ce0a23d
JG		 1515void r600_gpu_init(struct radeon_device *rdev)
1516{
1517 u32 tiling_config;
1518 u32 ramcfg;
d03f5d59
AD		 1519 u32 backend_map;
1520 u32 cc_rb_backend_disable;
1521 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1522 u32 tmp;
1523 int i, j;
1524 u32 sq_config;
1525 u32 sq_gpr_resource_mgmt_1 = 0;
1526 u32 sq_gpr_resource_mgmt_2 = 0;
1527 u32 sq_thread_resource_mgmt = 0;
1528 u32 sq_stack_resource_mgmt_1 = 0;
1529 u32 sq_stack_resource_mgmt_2 = 0;
1530
1531 /* FIXME: implement */
1532 switch (rdev->family) {
1533 case CHIP_R600:
1534 rdev->config.r600.max_pipes = 4;
1535 rdev->config.r600.max_tile_pipes = 8;
1536 rdev->config.r600.max_simds = 4;
1537 rdev->config.r600.max_backends = 4;
1538 rdev->config.r600.max_gprs = 256;
1539 rdev->config.r600.max_threads = 192;
1540 rdev->config.r600.max_stack_entries = 256;
1541 rdev->config.r600.max_hw_contexts = 8;
1542 rdev->config.r600.max_gs_threads = 16;
1543 rdev->config.r600.sx_max_export_size = 128;
1544 rdev->config.r600.sx_max_export_pos_size = 16;
1545 rdev->config.r600.sx_max_export_smx_size = 128;
1546 rdev->config.r600.sq_num_cf_insts = 2;
1547 break;
1548 case CHIP_RV630:
1549 case CHIP_RV635:
1550 rdev->config.r600.max_pipes = 2;
1551 rdev->config.r600.max_tile_pipes = 2;
1552 rdev->config.r600.max_simds = 3;
1553 rdev->config.r600.max_backends = 1;
1554 rdev->config.r600.max_gprs = 128;
1555 rdev->config.r600.max_threads = 192;
1556 rdev->config.r600.max_stack_entries = 128;
1557 rdev->config.r600.max_hw_contexts = 8;
1558 rdev->config.r600.max_gs_threads = 4;
1559 rdev->config.r600.sx_max_export_size = 128;
1560 rdev->config.r600.sx_max_export_pos_size = 16;
1561 rdev->config.r600.sx_max_export_smx_size = 128;
1562 rdev->config.r600.sq_num_cf_insts = 2;
1563 break;
1564 case CHIP_RV610:
1565 case CHIP_RV620:
1566 case CHIP_RS780:
1567 case CHIP_RS880:
1568 rdev->config.r600.max_pipes = 1;
1569 rdev->config.r600.max_tile_pipes = 1;
1570 rdev->config.r600.max_simds = 2;
1571 rdev->config.r600.max_backends = 1;
1572 rdev->config.r600.max_gprs = 128;
1573 rdev->config.r600.max_threads = 192;
1574 rdev->config.r600.max_stack_entries = 128;
1575 rdev->config.r600.max_hw_contexts = 4;
1576 rdev->config.r600.max_gs_threads = 4;
1577 rdev->config.r600.sx_max_export_size = 128;
1578 rdev->config.r600.sx_max_export_pos_size = 16;
1579 rdev->config.r600.sx_max_export_smx_size = 128;
1580 rdev->config.r600.sq_num_cf_insts = 1;
1581 break;
1582 case CHIP_RV670:
1583 rdev->config.r600.max_pipes = 4;
1584 rdev->config.r600.max_tile_pipes = 4;
1585 rdev->config.r600.max_simds = 4;
1586 rdev->config.r600.max_backends = 4;
1587 rdev->config.r600.max_gprs = 192;
1588 rdev->config.r600.max_threads = 192;
1589 rdev->config.r600.max_stack_entries = 256;
1590 rdev->config.r600.max_hw_contexts = 8;
1591 rdev->config.r600.max_gs_threads = 16;
1592 rdev->config.r600.sx_max_export_size = 128;
1593 rdev->config.r600.sx_max_export_pos_size = 16;
1594 rdev->config.r600.sx_max_export_smx_size = 128;
1595 rdev->config.r600.sq_num_cf_insts = 2;
1596 break;
1597 default:
1598 break;
1599 }
1600
1601 /* Initialize HDP */
1602 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1603 WREG32((0x2c14 + j), 0x00000000);
1604 WREG32((0x2c18 + j), 0x00000000);
1605 WREG32((0x2c1c + j), 0x00000000);
1606 WREG32((0x2c20 + j), 0x00000000);
1607 WREG32((0x2c24 + j), 0x00000000);
1608 }
1609
1610 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1611
1612 /* Setup tiling */
1613 tiling_config = 0;
1614 ramcfg = RREG32(RAMCFG);
1615 switch (rdev->config.r600.max_tile_pipes) {
1616 case 1:
1617 tiling_config |= PIPE_TILING(0);
1618 break;
1619 case 2:
1620 tiling_config |= PIPE_TILING(1);
1621 break;
1622 case 4:
1623 tiling_config |= PIPE_TILING(2);
1624 break;
1625 case 8:
1626 tiling_config |= PIPE_TILING(3);
1627 break;
1628 default:
1629 break;
1630 }
d03f5d59 1631 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1632 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 1633 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1
AD		 1634 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1635 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1636 rdev->config.r600.tiling_group_size = 512;
1637 else
1638 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1639 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1640 if (tmp > 3) {
1641 tiling_config |= ROW_TILING(3);
1642 tiling_config |= SAMPLE_SPLIT(3);
1643 } else {
1644 tiling_config |= ROW_TILING(tmp);
1645 tiling_config |= SAMPLE_SPLIT(tmp);
1646 }
1647 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1648
1649 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1650 cc_rb_backend_disable |=
1651 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1652
1653 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1654 cc_gc_shader_pipe_config |=
1655 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1656 cc_gc_shader_pipe_config |=
1657 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1658
1659 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1660 (R6XX_MAX_BACKENDS -
1661 r600_count_pipe_bits((cc_rb_backend_disable &
1662 R6XX_MAX_BACKENDS_MASK) >> 16)),
1663 (cc_rb_backend_disable >> 16));
e7aeeba6 1664 rdev->config.r600.tile_config = tiling_config;
e55b9422 1665 rdev->config.r600.backend_map = backend_map;
d03f5d59 1666 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1667 WREG32(GB_TILING_CONFIG, tiling_config);
1668 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1669 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1670
3ce0a23d 1671 /* Setup pipes */
d03f5d59
AD		 1672 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1673 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1674 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1675
d03f5d59 1676 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1677 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1678 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1679
1680 /* Setup some CP states */
1681 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1682 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1683
1684 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1685 SYNC_WALKER | SYNC_ALIGNER));
1686 /* Setup various GPU states */
1687 if (rdev->family == CHIP_RV670)
1688 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1689
1690 tmp = RREG32(SX_DEBUG_1);
1691 tmp |= SMX_EVENT_RELEASE;
1692 if ((rdev->family > CHIP_R600))
1693 tmp |= ENABLE_NEW_SMX_ADDRESS;
1694 WREG32(SX_DEBUG_1, tmp);
1695
1696 if (((rdev->family) == CHIP_R600) ||
1697 ((rdev->family) == CHIP_RV630) ||
1698 ((rdev->family) == CHIP_RV610) ||
1699 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1700 ((rdev->family) == CHIP_RS780) ||
1701 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1702 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1703 } else {
1704 WREG32(DB_DEBUG, 0);
1705 }
1706 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1707 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1708
1709 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1710 WREG32(VGT_NUM_INSTANCES, 0);
1711
1712 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1713 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1714
1715 tmp = RREG32(SQ_MS_FIFO_SIZES);
1716 if (((rdev->family) == CHIP_RV610) ||
1717 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1718 ((rdev->family) == CHIP_RS780) ||
1719 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1720 tmp = (CACHE_FIFO_SIZE(0xa) |
1721 FETCH_FIFO_HIWATER(0xa) |
1722 DONE_FIFO_HIWATER(0xe0) |
1723 ALU_UPDATE_FIFO_HIWATER(0x8));
1724 } else if (((rdev->family) == CHIP_R600) ||
1725 ((rdev->family) == CHIP_RV630)) {
1726 tmp &= ~DONE_FIFO_HIWATER(0xff);
1727 tmp |= DONE_FIFO_HIWATER(0x4);
1728 }
1729 WREG32(SQ_MS_FIFO_SIZES, tmp);
1730
1731 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1732 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1733 */
1734 sq_config = RREG32(SQ_CONFIG);
1735 sq_config &= ~(PS_PRIO(3) |
1736 VS_PRIO(3) |
1737 GS_PRIO(3) |
1738 ES_PRIO(3));
1739 sq_config |= (DX9_CONSTS |
1740 VC_ENABLE |
1741 PS_PRIO(0) |
1742 VS_PRIO(1) |
1743 GS_PRIO(2) |
1744 ES_PRIO(3));
1745
1746 if ((rdev->family) == CHIP_R600) {
1747 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1748 NUM_VS_GPRS(124) |
1749 NUM_CLAUSE_TEMP_GPRS(4));
1750 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1751 NUM_ES_GPRS(0));
1752 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1753 NUM_VS_THREADS(48) |
1754 NUM_GS_THREADS(4) |
1755 NUM_ES_THREADS(4));
1756 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1757 NUM_VS_STACK_ENTRIES(128));
1758 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1759 NUM_ES_STACK_ENTRIES(0));
1760 } else if (((rdev->family) == CHIP_RV610) ||
1761 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1762 ((rdev->family) == CHIP_RS780) ||
1763 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1764 /* no vertex cache */
1765 sq_config &= ~VC_ENABLE;
1766
1767 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1768 NUM_VS_GPRS(44) |
1769 NUM_CLAUSE_TEMP_GPRS(2));
1770 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1771 NUM_ES_GPRS(17));
1772 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1773 NUM_VS_THREADS(78) |
1774 NUM_GS_THREADS(4) |
1775 NUM_ES_THREADS(31));
1776 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1777 NUM_VS_STACK_ENTRIES(40));
1778 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1779 NUM_ES_STACK_ENTRIES(16));
1780 } else if (((rdev->family) == CHIP_RV630) ||
1781 ((rdev->family) == CHIP_RV635)) {
1782 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1783 NUM_VS_GPRS(44) |
1784 NUM_CLAUSE_TEMP_GPRS(2));
1785 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1786 NUM_ES_GPRS(18));
1787 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1788 NUM_VS_THREADS(78) |
1789 NUM_GS_THREADS(4) |
1790 NUM_ES_THREADS(31));
1791 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1792 NUM_VS_STACK_ENTRIES(40));
1793 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1794 NUM_ES_STACK_ENTRIES(16));
1795 } else if ((rdev->family) == CHIP_RV670) {
1796 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1797 NUM_VS_GPRS(44) |
1798 NUM_CLAUSE_TEMP_GPRS(2));
1799 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1800 NUM_ES_GPRS(17));
1801 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1802 NUM_VS_THREADS(78) |
1803 NUM_GS_THREADS(4) |
1804 NUM_ES_THREADS(31));
1805 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1806 NUM_VS_STACK_ENTRIES(64));
1807 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1808 NUM_ES_STACK_ENTRIES(64));
1809 }
1810
1811 WREG32(SQ_CONFIG, sq_config);
1812 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1813 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1814 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1815 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1816 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1817
1818 if (((rdev->family) == CHIP_RV610) ||
1819 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1820 ((rdev->family) == CHIP_RS780) ||
1821 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1822 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1823 } else {
1824 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1825 }
1826
1827 /* More default values. 2D/3D driver should adjust as needed */
1828 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1829 S1_X(0x4) | S1_Y(0xc)));
1830 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1831 S1_X(0x2) | S1_Y(0x2) |
1832 S2_X(0xa) | S2_Y(0x6) |
1833 S3_X(0x6) | S3_Y(0xa)));
1834 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1835 S1_X(0x4) | S1_Y(0xc) |
1836 S2_X(0x1) | S2_Y(0x6) |
1837 S3_X(0xa) | S3_Y(0xe)));
1838 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1839 S5_X(0x0) | S5_Y(0x0) |
1840 S6_X(0xb) | S6_Y(0x4) |
1841 S7_X(0x7) | S7_Y(0x8)));
1842
1843 WREG32(VGT_STRMOUT_EN, 0);
1844 tmp = rdev->config.r600.max_pipes * 16;
1845 switch (rdev->family) {
1846 case CHIP_RV610:
3ce0a23d 1847 case CHIP_RV620:
ee59f2b4
AD		 1848 case CHIP_RS780:
1849 case CHIP_RS880:
3ce0a23d
JG		 1850 tmp += 32;
1851 break;
1852 case CHIP_RV670:
1853 tmp += 128;
1854 break;
1855 default:
1856 break;
1857 }
1858 if (tmp > 256) {
1859 tmp = 256;
1860 }
1861 WREG32(VGT_ES_PER_GS, 128);
1862 WREG32(VGT_GS_PER_ES, tmp);
1863 WREG32(VGT_GS_PER_VS, 2);
1864 WREG32(VGT_GS_VERTEX_REUSE, 16);
1865
1866 /* more default values. 2D/3D driver should adjust as needed */
1867 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1868 WREG32(VGT_STRMOUT_EN, 0);
1869 WREG32(SX_MISC, 0);
1870 WREG32(PA_SC_MODE_CNTL, 0);
1871 WREG32(PA_SC_AA_CONFIG, 0);
1872 WREG32(PA_SC_LINE_STIPPLE, 0);
1873 WREG32(SPI_INPUT_Z, 0);
1874 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1875 WREG32(CB_COLOR7_FRAG, 0);
1876
1877 /* Clear render buffer base addresses */
1878 WREG32(CB_COLOR0_BASE, 0);
1879 WREG32(CB_COLOR1_BASE, 0);
1880 WREG32(CB_COLOR2_BASE, 0);
1881 WREG32(CB_COLOR3_BASE, 0);
1882 WREG32(CB_COLOR4_BASE, 0);
1883 WREG32(CB_COLOR5_BASE, 0);
1884 WREG32(CB_COLOR6_BASE, 0);
1885 WREG32(CB_COLOR7_BASE, 0);
1886 WREG32(CB_COLOR7_FRAG, 0);
1887
1888 switch (rdev->family) {
1889 case CHIP_RV610:
3ce0a23d 1890 case CHIP_RV620:
ee59f2b4
AD		 1891 case CHIP_RS780:
1892 case CHIP_RS880:
3ce0a23d
JG		 1893 tmp = TC_L2_SIZE(8);
1894 break;
1895 case CHIP_RV630:
1896 case CHIP_RV635:
1897 tmp = TC_L2_SIZE(4);
1898 break;
1899 case CHIP_R600:
1900 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1901 break;
1902 default:
1903 tmp = TC_L2_SIZE(0);
1904 break;
1905 }
1906 WREG32(TC_CNTL, tmp);
1907
1908 tmp = RREG32(HDP_HOST_PATH_CNTL);
1909 WREG32(HDP_HOST_PATH_CNTL, tmp);
1910
1911 tmp = RREG32(ARB_POP);
1912 tmp |= ENABLE_TC128;
1913 WREG32(ARB_POP, tmp);
1914
1915 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1916 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1917 NUM_CLIP_SEQ(3)));
1918 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1919}
1920
1921
771fe6b9
JG		 1922/*
1923 * Indirect registers accessor
1924 */
3ce0a23d
JG		 1925u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1926{
1927 u32 r;
1928
1929 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1930 (void)RREG32(PCIE_PORT_INDEX);
1931 r = RREG32(PCIE_PORT_DATA);
1932 return r;
1933}
1934
1935void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1936{
1937 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1938 (void)RREG32(PCIE_PORT_INDEX);
1939 WREG32(PCIE_PORT_DATA, (v));
1940 (void)RREG32(PCIE_PORT_DATA);
1941}
1942
3ce0a23d
JG		 1943/*
1944 * CP & Ring
1945 */
1946void r600_cp_stop(struct radeon_device *rdev)
1947{
53595338 1948 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3ce0a23d 1949 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 1950 WREG32(SCRATCH_UMSK, 0);
3ce0a23d
JG		 1951}
1952
d8f60cfc 1953int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1954{
1955 struct platform_device *pdev;
1956 const char *chip_name;
d8f60cfc
AD		 1957 const char *rlc_chip_name;
1958 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1959 char fw_name[30];
1960 int err;
1961
1962 DRM_DEBUG("\n");
1963
1964 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1965 err = IS_ERR(pdev);
1966 if (err) {
1967 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1968 return -EINVAL;
1969 }
1970
1971 switch (rdev->family) {
d8f60cfc
AD		 1972 case CHIP_R600:
1973 chip_name = "R600";
1974 rlc_chip_name = "R600";
1975 break;
1976 case CHIP_RV610:
1977 chip_name = "RV610";
1978 rlc_chip_name = "R600";
1979 break;
1980 case CHIP_RV630:
1981 chip_name = "RV630";
1982 rlc_chip_name = "R600";
1983 break;
1984 case CHIP_RV620:
1985 chip_name = "RV620";
1986 rlc_chip_name = "R600";
1987 break;
1988 case CHIP_RV635:
1989 chip_name = "RV635";
1990 rlc_chip_name = "R600";
1991 break;
1992 case CHIP_RV670:
1993 chip_name = "RV670";
1994 rlc_chip_name = "R600";
1995 break;
3ce0a23d 1996 case CHIP_RS780:
d8f60cfc
AD		 1997 case CHIP_RS880:
1998 chip_name = "RS780";
1999 rlc_chip_name = "R600";
2000 break;
2001 case CHIP_RV770:
2002 chip_name = "RV770";
2003 rlc_chip_name = "R700";
2004 break;
3ce0a23d 2005 case CHIP_RV730:
d8f60cfc
AD		 2006 case CHIP_RV740:
2007 chip_name = "RV730";
2008 rlc_chip_name = "R700";
2009 break;
2010 case CHIP_RV710:
2011 chip_name = "RV710";
2012 rlc_chip_name = "R700";
2013 break;
fe251e2f
AD		 2014 case CHIP_CEDAR:
2015 chip_name = "CEDAR";
45f9a39b 2016 rlc_chip_name = "CEDAR";
fe251e2f
AD		 2017 break;
2018 case CHIP_REDWOOD:
2019 chip_name = "REDWOOD";
45f9a39b 2020 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 2021 break;
2022 case CHIP_JUNIPER:
2023 chip_name = "JUNIPER";
45f9a39b 2024 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 2025 break;
2026 case CHIP_CYPRESS:
2027 case CHIP_HEMLOCK:
2028 chip_name = "CYPRESS";
45f9a39b 2029 rlc_chip_name = "CYPRESS";
fe251e2f 2030 break;
439bd6cd
AD		 2031 case CHIP_PALM:
2032 chip_name = "PALM";
2033 rlc_chip_name = "SUMO";
2034 break;
d5c5a72f
AD		 2035 case CHIP_SUMO:
2036 chip_name = "SUMO";
2037 rlc_chip_name = "SUMO";
2038 break;
2039 case CHIP_SUMO2:
2040 chip_name = "SUMO2";
2041 rlc_chip_name = "SUMO";
2042 break;
3ce0a23d
JG		 2043 default: BUG();
2044 }
2045
fe251e2f
AD		 2046 if (rdev->family >= CHIP_CEDAR) {
2047 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2048 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2049 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2050 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2051 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2052 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2053 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2054 } else {
2055 pfp_req_size = PFP_UCODE_SIZE * 4;
2056 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 2057 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2058 }
2059
d8f60cfc 2060 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2061
2062 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2063 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2064 if (err)
2065 goto out;
2066 if (rdev->pfp_fw->size != pfp_req_size) {
2067 printk(KERN_ERR
2068 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2069 rdev->pfp_fw->size, fw_name);
2070 err = -EINVAL;
2071 goto out;
2072 }
2073
2074 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2075 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2076 if (err)
2077 goto out;
2078 if (rdev->me_fw->size != me_req_size) {
2079 printk(KERN_ERR
2080 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2081 rdev->me_fw->size, fw_name);
2082 err = -EINVAL;
2083 }
d8f60cfc
AD		 2084
2085 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2086 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2087 if (err)
2088 goto out;
2089 if (rdev->rlc_fw->size != rlc_req_size) {
2090 printk(KERN_ERR
2091 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2092 rdev->rlc_fw->size, fw_name);
2093 err = -EINVAL;
2094 }
2095
3ce0a23d
JG		 2096out:
2097 platform_device_unregister(pdev);
2098
2099 if (err) {
2100 if (err != -EINVAL)
2101 printk(KERN_ERR
2102 "r600_cp: Failed to load firmware \"%s\"\n",
2103 fw_name);
2104 release_firmware(rdev->pfp_fw);
2105 rdev->pfp_fw = NULL;
2106 release_firmware(rdev->me_fw);
2107 rdev->me_fw = NULL;
d8f60cfc
AD		 2108 release_firmware(rdev->rlc_fw);
2109 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2110 }
2111 return err;
2112}
2113
2114static int r600_cp_load_microcode(struct radeon_device *rdev)
2115{
2116 const __be32 *fw_data;
2117 int i;
2118
2119 if (!rdev->me_fw || !rdev->pfp_fw)
2120 return -EINVAL;
2121
2122 r600_cp_stop(rdev);
2123
4eace7fd
CC		 2124 WREG32(CP_RB_CNTL,
2125#ifdef __BIG_ENDIAN
2126 BUF_SWAP_32BIT |
2127#endif
2128 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3ce0a23d
JG		 2129
2130 /* Reset cp */
2131 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2132 RREG32(GRBM_SOFT_RESET);
2133 mdelay(15);
2134 WREG32(GRBM_SOFT_RESET, 0);
2135
2136 WREG32(CP_ME_RAM_WADDR, 0);
2137
2138 fw_data = (const __be32 *)rdev->me_fw->data;
2139 WREG32(CP_ME_RAM_WADDR, 0);
2140 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2141 WREG32(CP_ME_RAM_DATA,
2142 be32_to_cpup(fw_data++));
2143
2144 fw_data = (const __be32 *)rdev->pfp_fw->data;
2145 WREG32(CP_PFP_UCODE_ADDR, 0);
2146 for (i = 0; i < PFP_UCODE_SIZE; i++)
2147 WREG32(CP_PFP_UCODE_DATA,
2148 be32_to_cpup(fw_data++));
2149
2150 WREG32(CP_PFP_UCODE_ADDR, 0);
2151 WREG32(CP_ME_RAM_WADDR, 0);
2152 WREG32(CP_ME_RAM_RADDR, 0);
2153 return 0;
2154}
2155
2156int r600_cp_start(struct radeon_device *rdev)
2157{
2158 int r;
2159 uint32_t cp_me;
2160
2161 r = radeon_ring_lock(rdev, 7);
2162 if (r) {
2163 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2164 return r;
2165 }
2166 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2167 radeon_ring_write(rdev, 0x1);
7e7b41d2 2168 if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2169 radeon_ring_write(rdev, 0x0);
2170 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f
AD		 2171 } else {
2172 radeon_ring_write(rdev, 0x3);
2173 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d
JG		 2174 }
2175 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2176 radeon_ring_write(rdev, 0);
2177 radeon_ring_write(rdev, 0);
2178 radeon_ring_unlock_commit(rdev);
2179
2180 cp_me = 0xff;
2181 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2182 return 0;
2183}
2184
2185int r600_cp_resume(struct radeon_device *rdev)
2186{
2187 u32 tmp;
2188 u32 rb_bufsz;
2189 int r;
2190
2191 /* Reset cp */
2192 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2193 RREG32(GRBM_SOFT_RESET);
2194 mdelay(15);
2195 WREG32(GRBM_SOFT_RESET, 0);
2196
2197 /* Set ring buffer size */
2198 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
724c80e1 2199 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2200#ifdef __BIG_ENDIAN
d6f28938 2201 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2202#endif
d6f28938 2203 WREG32(CP_RB_CNTL, tmp);
3ce0a23d
JG		 2204 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2205
2206 /* Set the write pointer delay */
2207 WREG32(CP_RB_WPTR_DELAY, 0);
2208
2209 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2210 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2211 WREG32(CP_RB_RPTR_WR, 0);
2212 WREG32(CP_RB_WPTR, 0);
724c80e1
AD		 2213
2214 /* set the wb address whether it's enabled or not */
4eace7fd 2215 WREG32(CP_RB_RPTR_ADDR,
4eace7fd 2216 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 2217 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2218 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2219
2220 if (rdev->wb.enabled)
2221 WREG32(SCRATCH_UMSK, 0xff);
2222 else {
2223 tmp |= RB_NO_UPDATE;
2224 WREG32(SCRATCH_UMSK, 0);
2225 }
2226
3ce0a23d
JG		 2227 mdelay(1);
2228 WREG32(CP_RB_CNTL, tmp);
2229
2230 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2231 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2232
2233 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2234 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2235
2236 r600_cp_start(rdev);
2237 rdev->cp.ready = true;
2238 r = radeon_ring_test(rdev);
2239 if (r) {
2240 rdev->cp.ready = false;
2241 return r;
2242 }
2243 return 0;
2244}
2245
2246void r600_cp_commit(struct radeon_device *rdev)
2247{
2248 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2249 (void)RREG32(CP_RB_WPTR);
2250}
2251
2252void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2253{
2254 u32 rb_bufsz;
2255
2256 /* Align ring size */
2257 rb_bufsz = drm_order(ring_size / 8);
2258 ring_size = (1 << (rb_bufsz + 1)) * 4;
2259 rdev->cp.ring_size = ring_size;
2260 rdev->cp.align_mask = 16 - 1;
2261}
2262
655efd3d
JG		 2263void r600_cp_fini(struct radeon_device *rdev)
2264{
2265 r600_cp_stop(rdev);
2266 radeon_ring_fini(rdev);
2267}
2268
3ce0a23d
JG		 2269
2270/*
2271 * GPU scratch registers helpers function.
2272 */
2273void r600_scratch_init(struct radeon_device *rdev)
2274{
2275 int i;
2276
2277 rdev->scratch.num_reg = 7;
724c80e1 2278 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2279 for (i = 0; i < rdev->scratch.num_reg; i++) {
2280 rdev->scratch.free[i] = true;
724c80e1 2281 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2282 }
2283}
2284
2285int r600_ring_test(struct radeon_device *rdev)
2286{
2287 uint32_t scratch;
2288 uint32_t tmp = 0;
2289 unsigned i;
2290 int r;
2291
2292 r = radeon_scratch_get(rdev, &scratch);
2293 if (r) {
2294 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2295 return r;
2296 }
2297 WREG32(scratch, 0xCAFEDEAD);
2298 r = radeon_ring_lock(rdev, 3);
2299 if (r) {
2300 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2301 radeon_scratch_free(rdev, scratch);
2302 return r;
2303 }
2304 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2305 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2306 radeon_ring_write(rdev, 0xDEADBEEF);
2307 radeon_ring_unlock_commit(rdev);
2308 for (i = 0; i < rdev->usec_timeout; i++) {
2309 tmp = RREG32(scratch);
2310 if (tmp == 0xDEADBEEF)
2311 break;
2312 DRM_UDELAY(1);
2313 }
2314 if (i < rdev->usec_timeout) {
2315 DRM_INFO("ring test succeeded in %d usecs\n", i);
2316 } else {
2317 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2318 scratch, tmp);
2319 r = -EINVAL;
2320 }
2321 radeon_scratch_free(rdev, scratch);
2322 return r;
2323}
2324
3ce0a23d
JG		 2325void r600_fence_ring_emit(struct radeon_device *rdev,
2326 struct radeon_fence *fence)
2327{
d0f8a854
AD		 2328 if (rdev->wb.use_event) {
2329 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2330 (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2331 /* EVENT_WRITE_EOP - flush caches, send int */
2332 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2333 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2334 radeon_ring_write(rdev, addr & 0xffffffff);
2335 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2336 radeon_ring_write(rdev, fence->seq);
2337 radeon_ring_write(rdev, 0);
2338 } else {
2339 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2340 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2341 /* wait for 3D idle clean */
2342 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2343 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2344 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2345 /* Emit fence sequence & fire IRQ */
2346 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2347 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2348 radeon_ring_write(rdev, fence->seq);
2349 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2350 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2351 radeon_ring_write(rdev, RB_INT_STAT);
2352 }
3ce0a23d
JG		 2353}
2354
3ce0a23d
JG		 2355int r600_copy_blit(struct radeon_device *rdev,
2356 uint64_t src_offset, uint64_t dst_offset,
2357 unsigned num_pages, struct radeon_fence *fence)
2358{
ff82f052
JG		 2359 int r;
2360
2361 mutex_lock(&rdev->r600_blit.mutex);
2362 rdev->r600_blit.vb_ib = NULL;
2363 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2364 if (r) {
2365 if (rdev->r600_blit.vb_ib)
2366 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2367 mutex_unlock(&rdev->r600_blit.mutex);
2368 return r;
2369 }
a77f1718 2370 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3ce0a23d 2371 r600_blit_done_copy(rdev, fence);
ff82f052 2372 mutex_unlock(&rdev->r600_blit.mutex);
3ce0a23d
JG		 2373 return 0;
2374}
2375
3ce0a23d
JG		 2376int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2377 uint32_t tiling_flags, uint32_t pitch,
2378 uint32_t offset, uint32_t obj_size)
2379{
2380 /* FIXME: implement */
2381 return 0;
2382}
2383
2384void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2385{
2386 /* FIXME: implement */
2387}
2388
fc30b8ef 2389int r600_startup(struct radeon_device *rdev)
3ce0a23d
JG		 2390{
2391 int r;
2392
9e46a48d
AD		 2393 /* enable pcie gen2 link */
2394 r600_pcie_gen2_enable(rdev);
2395
779720a3
AD		 2396 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2397 r = r600_init_microcode(rdev);
2398 if (r) {
2399 DRM_ERROR("Failed to load firmware!\n");
2400 return r;
2401 }
2402 }
2403
a3c1945a 2404 r600_mc_program(rdev);
1a029b76
JG		 2405 if (rdev->flags & RADEON_IS_AGP) {
2406 r600_agp_enable(rdev);
2407 } else {
2408 r = r600_pcie_gart_enable(rdev);
2409 if (r)
2410 return r;
2411 }
3ce0a23d 2412 r600_gpu_init(rdev);
c38c7b64
JG		 2413 r = r600_blit_init(rdev);
2414 if (r) {
2415 r600_blit_fini(rdev);
2416 rdev->asic->copy = NULL;
2417 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2418 }
b70d6bb3 2419
724c80e1
AD		 2420 /* allocate wb buffer */
2421 r = radeon_wb_init(rdev);
2422 if (r)
2423 return r;
2424
d8f60cfc 2425 /* Enable IRQ */
d8f60cfc
AD		 2426 r = r600_irq_init(rdev);
2427 if (r) {
2428 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2429 radeon_irq_kms_fini(rdev);
2430 return r;
2431 }
2432 r600_irq_set(rdev);
2433
3ce0a23d
JG		 2434 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2435 if (r)
2436 return r;
2437 r = r600_cp_load_microcode(rdev);
2438 if (r)
2439 return r;
2440 r = r600_cp_resume(rdev);
2441 if (r)
2442 return r;
724c80e1 2443
3ce0a23d
JG		 2444 return 0;
2445}
2446
28d52043
DA		 2447void r600_vga_set_state(struct radeon_device *rdev, bool state)
2448{
2449 uint32_t temp;
2450
2451 temp = RREG32(CONFIG_CNTL);
2452 if (state == false) {
2453 temp &= ~(1<<0);
2454 temp |= (1<<1);
2455 } else {
2456 temp &= ~(1<<1);
2457 }
2458 WREG32(CONFIG_CNTL, temp);
2459}
2460
fc30b8ef
DA		 2461int r600_resume(struct radeon_device *rdev)
2462{
2463 int r;
2464
1a029b76
JG		 2465 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2466 * posting will perform necessary task to bring back GPU into good
2467 * shape.
2468 */
fc30b8ef 2469 /* post card */
e7d40b9a 2470 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 2471
2472 r = r600_startup(rdev);
2473 if (r) {
2474 DRM_ERROR("r600 startup failed on resume\n");
2475 return r;
2476 }
2477
62a8ea3f 2478 r = r600_ib_test(rdev);
fc30b8ef 2479 if (r) {
ec4f2ac4 2480 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
fc30b8ef
DA		 2481 return r;
2482 }
38fd2c6f
RM		 2483
2484 r = r600_audio_init(rdev);
2485 if (r) {
2486 DRM_ERROR("radeon: audio resume failed\n");
2487 return r;
2488 }
2489
fc30b8ef
DA		 2490 return r;
2491}
2492
3ce0a23d
JG		 2493int r600_suspend(struct radeon_device *rdev)
2494{
4c788679
JG		 2495 int r;
2496
38fd2c6f 2497 r600_audio_fini(rdev);
3ce0a23d
JG		 2498 /* FIXME: we should wait for ring to be empty */
2499 r600_cp_stop(rdev);
bc1a631e 2500 rdev->cp.ready = false;
0c45249f 2501 r600_irq_suspend(rdev);
724c80e1 2502 radeon_wb_disable(rdev);
4aac0473 2503 r600_pcie_gart_disable(rdev);
bc1a631e 2504 /* unpin shaders bo */
30d2d9a5
JG		 2505 if (rdev->r600_blit.shader_obj) {
2506 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2507 if (!r) {
2508 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2509 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2510 }
2511 }
3ce0a23d
JG		 2512 return 0;
2513}
2514
2515/* Plan is to move initialization in that function and use
2516 * helper function so that radeon_device_init pretty much
2517 * do nothing more than calling asic specific function. This
2518 * should also allow to remove a bunch of callback function
2519 * like vram_info.
2520 */
2521int r600_init(struct radeon_device *rdev)
771fe6b9 2522{
3ce0a23d 2523 int r;
771fe6b9 2524
3ce0a23d
JG		 2525 if (r600_debugfs_mc_info_init(rdev)) {
2526 DRM_ERROR("Failed to register debugfs file for mc !\n");
2527 }
2528 /* This don't do much */
2529 r = radeon_gem_init(rdev);
2530 if (r)
2531 return r;
2532 /* Read BIOS */
2533 if (!radeon_get_bios(rdev)) {
2534 if (ASIC_IS_AVIVO(rdev))
2535 return -EINVAL;
2536 }
2537 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2538 if (!rdev->is_atom_bios) {
2539 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2540 return -EINVAL;
e7d40b9a 2541 }
3ce0a23d
JG		 2542 r = radeon_atombios_init(rdev);
2543 if (r)
2544 return r;
2545 /* Post card if necessary */
fd909c37 2546 if (!radeon_card_posted(rdev)) {
72542d77
DA		 2547 if (!rdev->bios) {
2548 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2549 return -EINVAL;
2550 }
3ce0a23d
JG		 2551 DRM_INFO("GPU not posted. posting now...\n");
2552 atom_asic_init(rdev->mode_info.atom_context);
2553 }
2554 /* Initialize scratch registers */
2555 r600_scratch_init(rdev);
2556 /* Initialize surface registers */
2557 radeon_surface_init(rdev);
7433874e 2558 /* Initialize clocks */
5e6dde7e 2559 radeon_get_clock_info(rdev->ddev);
3ce0a23d
JG		 2560 /* Fence driver */
2561 r = radeon_fence_driver_init(rdev);
2562 if (r)
2563 return r;
700a0cc0
JG		 2564 if (rdev->flags & RADEON_IS_AGP) {
2565 r = radeon_agp_init(rdev);
2566 if (r)
2567 radeon_agp_disable(rdev);
2568 }
3ce0a23d 2569 r = r600_mc_init(rdev);
b574f251 2570 if (r)
3ce0a23d 2571 return r;
3ce0a23d 2572 /* Memory manager */
4c788679 2573 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2574 if (r)
2575 return r;
d8f60cfc
AD		 2576
2577 r = radeon_irq_kms_init(rdev);
2578 if (r)
2579 return r;
2580
3ce0a23d
JG		 2581 rdev->cp.ring_obj = NULL;
2582 r600_ring_init(rdev, 1024 * 1024);
2583
d8f60cfc
AD		 2584 rdev->ih.ring_obj = NULL;
2585 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2586
4aac0473
JG		 2587 r = r600_pcie_gart_init(rdev);
2588 if (r)
2589 return r;
2590
779720a3 2591 rdev->accel_working = true;
fc30b8ef 2592 r = r600_startup(rdev);
3ce0a23d 2593 if (r) {
655efd3d
JG		 2594 dev_err(rdev->dev, "disabling GPU acceleration\n");
2595 r600_cp_fini(rdev);
655efd3d 2596 r600_irq_fini(rdev);
724c80e1 2597 radeon_wb_fini(rdev);
655efd3d 2598 radeon_irq_kms_fini(rdev);
75c81298 2599 r600_pcie_gart_fini(rdev);
733289c2 2600 rdev->accel_working = false;
3ce0a23d 2601 }
733289c2
JG		 2602 if (rdev->accel_working) {
2603 r = radeon_ib_pool_init(rdev);
2604 if (r) {
db96380e 2605 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 2606 rdev->accel_working = false;
db96380e
JG		 2607 } else {
2608 r = r600_ib_test(rdev);
2609 if (r) {
2610 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2611 rdev->accel_working = false;
2612 }
733289c2 2613 }
3ce0a23d 2614 }
dafc3bd5
CK		 2615
2616 r = r600_audio_init(rdev);
2617 if (r)
2618 return r; /* TODO error handling */
3ce0a23d
JG		 2619 return 0;
2620}
2621
2622void r600_fini(struct radeon_device *rdev)
2623{
dafc3bd5 2624 r600_audio_fini(rdev);
3ce0a23d 2625 r600_blit_fini(rdev);
655efd3d 2626 r600_cp_fini(rdev);
d8f60cfc 2627 r600_irq_fini(rdev);
724c80e1 2628 radeon_wb_fini(rdev);
ccd6895d 2629 radeon_ib_pool_fini(rdev);
d8f60cfc 2630 radeon_irq_kms_fini(rdev);
4aac0473 2631 r600_pcie_gart_fini(rdev);
655efd3d 2632 radeon_agp_fini(rdev);
3ce0a23d
JG		 2633 radeon_gem_fini(rdev);
2634 radeon_fence_driver_fini(rdev);
4c788679 2635 radeon_bo_fini(rdev);
e7d40b9a 2636 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2637 kfree(rdev->bios);
2638 rdev->bios = NULL;
3ce0a23d
JG		 2639}
2640
2641
2642/*
2643 * CS stuff
2644 */
2645void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2646{
2647 /* FIXME: implement */
2648 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4eace7fd
CC		 2649 radeon_ring_write(rdev,
2650#ifdef __BIG_ENDIAN
2651 (2 << 0) |
2652#endif
2653 (ib->gpu_addr & 0xFFFFFFFC));
3ce0a23d
JG		 2654 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2655 radeon_ring_write(rdev, ib->length_dw);
2656}
2657
2658int r600_ib_test(struct radeon_device *rdev)
2659{
2660 struct radeon_ib *ib;
2661 uint32_t scratch;
2662 uint32_t tmp = 0;
2663 unsigned i;
2664 int r;
2665
2666 r = radeon_scratch_get(rdev, &scratch);
2667 if (r) {
2668 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2669 return r;
2670 }
2671 WREG32(scratch, 0xCAFEDEAD);
2672 r = radeon_ib_get(rdev, &ib);
2673 if (r) {
2674 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2675 return r;
2676 }
2677 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2678 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2679 ib->ptr[2] = 0xDEADBEEF;
2680 ib->ptr[3] = PACKET2(0);
2681 ib->ptr[4] = PACKET2(0);
2682 ib->ptr[5] = PACKET2(0);
2683 ib->ptr[6] = PACKET2(0);
2684 ib->ptr[7] = PACKET2(0);
2685 ib->ptr[8] = PACKET2(0);
2686 ib->ptr[9] = PACKET2(0);
2687 ib->ptr[10] = PACKET2(0);
2688 ib->ptr[11] = PACKET2(0);
2689 ib->ptr[12] = PACKET2(0);
2690 ib->ptr[13] = PACKET2(0);
2691 ib->ptr[14] = PACKET2(0);
2692 ib->ptr[15] = PACKET2(0);
2693 ib->length_dw = 16;
2694 r = radeon_ib_schedule(rdev, ib);
2695 if (r) {
2696 radeon_scratch_free(rdev, scratch);
2697 radeon_ib_free(rdev, &ib);
2698 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2699 return r;
2700 }
2701 r = radeon_fence_wait(ib->fence, false);
2702 if (r) {
2703 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2704 return r;
2705 }
2706 for (i = 0; i < rdev->usec_timeout; i++) {
2707 tmp = RREG32(scratch);
2708 if (tmp == 0xDEADBEEF)
2709 break;
2710 DRM_UDELAY(1);
2711 }
2712 if (i < rdev->usec_timeout) {
2713 DRM_INFO("ib test succeeded in %u usecs\n", i);
2714 } else {
4417d7f6 2715 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 2716 scratch, tmp);
2717 r = -EINVAL;
2718 }
2719 radeon_scratch_free(rdev, scratch);
2720 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2721 return r;
2722}
2723
d8f60cfc
AD		 2724/*
2725 * Interrupts
2726 *
2727 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2728 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2729 * writing to the ring and the GPU consuming, the GPU writes to the ring
2730 * and host consumes. As the host irq handler processes interrupts, it
2731 * increments the rptr. When the rptr catches up with the wptr, all the
2732 * current interrupts have been processed.
2733 */
2734
2735void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2736{
2737 u32 rb_bufsz;
2738
2739 /* Align ring size */
2740 rb_bufsz = drm_order(ring_size / 4);
2741 ring_size = (1 << rb_bufsz) * 4;
2742 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2743 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2744 rdev->ih.rptr = 0;
d8f60cfc
AD		 2745}
2746
0c45249f 2747static int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2748{
2749 int r;
2750
d8f60cfc
AD		 2751 /* Allocate ring buffer */
2752 if (rdev->ih.ring_obj == NULL) {
441921d5 2753 r = radeon_bo_create(rdev, rdev->ih.ring_size,
268b2510 2754 PAGE_SIZE, true,
4c788679
JG		 2755 RADEON_GEM_DOMAIN_GTT,
2756 &rdev->ih.ring_obj);
d8f60cfc
AD		 2757 if (r) {
2758 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2759 return r;
2760 }
4c788679
JG		 2761 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2762 if (unlikely(r != 0))
2763 return r;
2764 r = radeon_bo_pin(rdev->ih.ring_obj,
2765 RADEON_GEM_DOMAIN_GTT,
2766 &rdev->ih.gpu_addr);
d8f60cfc 2767 if (r) {
4c788679 2768 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2769 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2770 return r;
2771 }
4c788679
JG		 2772 r = radeon_bo_kmap(rdev->ih.ring_obj,
2773 (void **)&rdev->ih.ring);
2774 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2775 if (r) {
2776 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2777 return r;
2778 }
2779 }
d8f60cfc
AD		 2780 return 0;
2781}
2782
2783static void r600_ih_ring_fini(struct radeon_device *rdev)
2784{
4c788679 2785 int r;
d8f60cfc 2786 if (rdev->ih.ring_obj) {
4c788679
JG		 2787 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2788 if (likely(r == 0)) {
2789 radeon_bo_kunmap(rdev->ih.ring_obj);
2790 radeon_bo_unpin(rdev->ih.ring_obj);
2791 radeon_bo_unreserve(rdev->ih.ring_obj);
2792 }
2793 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2794 rdev->ih.ring = NULL;
2795 rdev->ih.ring_obj = NULL;
2796 }
2797}
2798
45f9a39b 2799void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2800{
2801
45f9a39b
AD		 2802 if ((rdev->family >= CHIP_RV770) &&
2803 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2804 /* r7xx asics need to soft reset RLC before halting */
2805 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2806 RREG32(SRBM_SOFT_RESET);
2807 udelay(15000);
2808 WREG32(SRBM_SOFT_RESET, 0);
2809 RREG32(SRBM_SOFT_RESET);
2810 }
2811
2812 WREG32(RLC_CNTL, 0);
2813}
2814
2815static void r600_rlc_start(struct radeon_device *rdev)
2816{
2817 WREG32(RLC_CNTL, RLC_ENABLE);
2818}
2819
2820static int r600_rlc_init(struct radeon_device *rdev)
2821{
2822 u32 i;
2823 const __be32 *fw_data;
2824
2825 if (!rdev->rlc_fw)
2826 return -EINVAL;
2827
2828 r600_rlc_stop(rdev);
2829
2830 WREG32(RLC_HB_BASE, 0);
2831 WREG32(RLC_HB_CNTL, 0);
2832 WREG32(RLC_HB_RPTR, 0);
2833 WREG32(RLC_HB_WPTR, 0);
12727809
AD		 2834 if (rdev->family <= CHIP_CAICOS) {
2835 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2836 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2837 }
d8f60cfc
AD		 2838 WREG32(RLC_MC_CNTL, 0);
2839 WREG32(RLC_UCODE_CNTL, 0);
2840
2841 fw_data = (const __be32 *)rdev->rlc_fw->data;
12727809
AD		 2842 if (rdev->family >= CHIP_CAYMAN) {
2843 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2844 WREG32(RLC_UCODE_ADDR, i);
2845 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2846 }
2847 } else if (rdev->family >= CHIP_CEDAR) {
45f9a39b
AD		 2848 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2849 WREG32(RLC_UCODE_ADDR, i);
2850 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2851 }
2852 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2853 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2854 WREG32(RLC_UCODE_ADDR, i);
2855 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2856 }
2857 } else {
2858 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2859 WREG32(RLC_UCODE_ADDR, i);
2860 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2861 }
2862 }
2863 WREG32(RLC_UCODE_ADDR, 0);
2864
2865 r600_rlc_start(rdev);
2866
2867 return 0;
2868}
2869
2870static void r600_enable_interrupts(struct radeon_device *rdev)
2871{
2872 u32 ih_cntl = RREG32(IH_CNTL);
2873 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2874
2875 ih_cntl |= ENABLE_INTR;
2876 ih_rb_cntl |= IH_RB_ENABLE;
2877 WREG32(IH_CNTL, ih_cntl);
2878 WREG32(IH_RB_CNTL, ih_rb_cntl);
2879 rdev->ih.enabled = true;
2880}
2881
45f9a39b 2882void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2883{
2884 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2885 u32 ih_cntl = RREG32(IH_CNTL);
2886
2887 ih_rb_cntl &= ~IH_RB_ENABLE;
2888 ih_cntl &= ~ENABLE_INTR;
2889 WREG32(IH_RB_CNTL, ih_rb_cntl);
2890 WREG32(IH_CNTL, ih_cntl);
2891 /* set rptr, wptr to 0 */
2892 WREG32(IH_RB_RPTR, 0);
2893 WREG32(IH_RB_WPTR, 0);
2894 rdev->ih.enabled = false;
2895 rdev->ih.wptr = 0;
2896 rdev->ih.rptr = 0;
2897}
2898
e0df1ac5
AD		 2899static void r600_disable_interrupt_state(struct radeon_device *rdev)
2900{
2901 u32 tmp;
2902
3555e53b 2903 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
e0df1ac5
AD		 2904 WREG32(GRBM_INT_CNTL, 0);
2905 WREG32(DxMODE_INT_MASK, 0);
6f34be50
AD		 2906 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2907 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
e0df1ac5
AD		 2908 if (ASIC_IS_DCE3(rdev)) {
2909 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2910 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2911 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2912 WREG32(DC_HPD1_INT_CONTROL, tmp);
2913 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2914 WREG32(DC_HPD2_INT_CONTROL, tmp);
2915 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2916 WREG32(DC_HPD3_INT_CONTROL, tmp);
2917 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2918 WREG32(DC_HPD4_INT_CONTROL, tmp);
2919 if (ASIC_IS_DCE32(rdev)) {
2920 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2921 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2922 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2923 WREG32(DC_HPD6_INT_CONTROL, tmp);
e0df1ac5
AD		 2924 }
2925 } else {
2926 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2927 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2928 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2929 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2930 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2931 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2932 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2933 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
e0df1ac5
AD		 2934 }
2935}
2936
d8f60cfc
AD		 2937int r600_irq_init(struct radeon_device *rdev)
2938{
2939 int ret = 0;
2940 int rb_bufsz;
2941 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2942
2943 /* allocate ring */
0c45249f 2944 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2945 if (ret)
2946 return ret;
2947
2948 /* disable irqs */
2949 r600_disable_interrupts(rdev);
2950
2951 /* init rlc */
2952 ret = r600_rlc_init(rdev);
2953 if (ret) {
2954 r600_ih_ring_fini(rdev);
2955 return ret;
2956 }
2957
2958 /* setup interrupt control */
2959 /* set dummy read address to ring address */
2960 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2961 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2962 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2963 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2964 */
2965 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2966 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2967 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2968 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2969
2970 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2971 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2972
2973 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2974 IH_WPTR_OVERFLOW_CLEAR |
2975 (rb_bufsz << 1));
724c80e1
AD		 2976
2977 if (rdev->wb.enabled)
2978 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2979
2980 /* set the writeback address whether it's enabled or not */
2981 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2982 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 2983
2984 WREG32(IH_RB_CNTL, ih_rb_cntl);
2985
2986 /* set rptr, wptr to 0 */
2987 WREG32(IH_RB_RPTR, 0);
2988 WREG32(IH_RB_WPTR, 0);
2989
2990 /* Default settings for IH_CNTL (disabled at first) */
2991 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2992 /* RPTR_REARM only works if msi's are enabled */
2993 if (rdev->msi_enabled)
2994 ih_cntl |= RPTR_REARM;
d8f60cfc
AD		 2995 WREG32(IH_CNTL, ih_cntl);
2996
2997 /* force the active interrupt state to all disabled */
45f9a39b
AD		 2998 if (rdev->family >= CHIP_CEDAR)
2999 evergreen_disable_interrupt_state(rdev);
3000 else
3001 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3002
3003 /* enable irqs */
3004 r600_enable_interrupts(rdev);
3005
3006 return ret;
3007}
3008
0c45249f 3009void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 3010{
45f9a39b 3011 r600_irq_disable(rdev);
d8f60cfc 3012 r600_rlc_stop(rdev);
0c45249f
JG		 3013}
3014
3015void r600_irq_fini(struct radeon_device *rdev)
3016{
3017 r600_irq_suspend(rdev);
d8f60cfc
AD		 3018 r600_ih_ring_fini(rdev);
3019}
3020
3021int r600_irq_set(struct radeon_device *rdev)
3022{
e0df1ac5
AD		 3023 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3024 u32 mode_int = 0;
3025 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3026 u32 grbm_int_cntl = 0;
f2594933 3027 u32 hdmi1, hdmi2;
6f34be50 3028 u32 d1grph = 0, d2grph = 0;
d8f60cfc 3029
003e69f9 3030 if (!rdev->irq.installed) {
fce7d61b 3031 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3032 return -EINVAL;
3033 }
d8f60cfc 3034 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3035 if (!rdev->ih.enabled) {
3036 r600_disable_interrupts(rdev);
3037 /* force the active interrupt state to all disabled */
3038 r600_disable_interrupt_state(rdev);
d8f60cfc 3039 return 0;
79c2bbc5 3040 }
d8f60cfc 3041
f2594933 3042 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5 3043 if (ASIC_IS_DCE3(rdev)) {
f2594933 3044 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3045 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3046 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3047 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3048 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3049 if (ASIC_IS_DCE32(rdev)) {
3050 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3051 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3052 }
3053 } else {
f2594933 3054 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3055 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3056 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3057 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3058 }
3059
d8f60cfc
AD		 3060 if (rdev->irq.sw_int) {
3061 DRM_DEBUG("r600_irq_set: sw int\n");
3062 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3063 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc 3064 }
6f34be50
AD		 3065 if (rdev->irq.crtc_vblank_int[0] ||
3066 rdev->irq.pflip[0]) {
d8f60cfc
AD		 3067 DRM_DEBUG("r600_irq_set: vblank 0\n");
3068 mode_int |= D1MODE_VBLANK_INT_MASK;
3069 }
6f34be50
AD		 3070 if (rdev->irq.crtc_vblank_int[1] ||
3071 rdev->irq.pflip[1]) {
d8f60cfc
AD		 3072 DRM_DEBUG("r600_irq_set: vblank 1\n");
3073 mode_int |= D2MODE_VBLANK_INT_MASK;
3074 }
e0df1ac5
AD		 3075 if (rdev->irq.hpd[0]) {
3076 DRM_DEBUG("r600_irq_set: hpd 1\n");
3077 hpd1 |= DC_HPDx_INT_EN;
3078 }
3079 if (rdev->irq.hpd[1]) {
3080 DRM_DEBUG("r600_irq_set: hpd 2\n");
3081 hpd2 |= DC_HPDx_INT_EN;
3082 }
3083 if (rdev->irq.hpd[2]) {
3084 DRM_DEBUG("r600_irq_set: hpd 3\n");
3085 hpd3 |= DC_HPDx_INT_EN;
3086 }
3087 if (rdev->irq.hpd[3]) {
3088 DRM_DEBUG("r600_irq_set: hpd 4\n");
3089 hpd4 |= DC_HPDx_INT_EN;
3090 }
3091 if (rdev->irq.hpd[4]) {
3092 DRM_DEBUG("r600_irq_set: hpd 5\n");
3093 hpd5 |= DC_HPDx_INT_EN;
3094 }
3095 if (rdev->irq.hpd[5]) {
3096 DRM_DEBUG("r600_irq_set: hpd 6\n");
3097 hpd6 |= DC_HPDx_INT_EN;
3098 }
f2594933
CK		 3099 if (rdev->irq.hdmi[0]) {
3100 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3101 hdmi1 |= R600_HDMI_INT_EN;
3102 }
3103 if (rdev->irq.hdmi[1]) {
3104 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3105 hdmi2 |= R600_HDMI_INT_EN;
3106 }
2031f77c
AD		 3107 if (rdev->irq.gui_idle) {
3108 DRM_DEBUG("gui idle\n");
3109 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3110 }
d8f60cfc
AD		 3111
3112 WREG32(CP_INT_CNTL, cp_int_cntl);
3113 WREG32(DxMODE_INT_MASK, mode_int);
6f34be50
AD		 3114 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3115 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
2031f77c 3116 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
f2594933 3117 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
e0df1ac5 3118 if (ASIC_IS_DCE3(rdev)) {
f2594933 3119 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3120 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3121 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3122 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3123 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3124 if (ASIC_IS_DCE32(rdev)) {
3125 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3126 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3127 }
3128 } else {
f2594933 3129 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3130 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3131 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3132 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3133 }
d8f60cfc
AD		 3134
3135 return 0;
3136}
3137
6f34be50 3138static inline void r600_irq_ack(struct radeon_device *rdev)
d8f60cfc 3139{
e0df1ac5
AD		 3140 u32 tmp;
3141
3142 if (ASIC_IS_DCE3(rdev)) {
6f34be50
AD		 3143 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3144 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3145 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
e0df1ac5 3146 } else {
6f34be50
AD		 3147 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3148 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3149 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3150 }
3151 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3152 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3153
3154 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3155 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3156 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3157 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3158 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3159 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3160 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3161 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3162 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3163 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3164 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3165 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3166 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
e0df1ac5
AD		 3167 if (ASIC_IS_DCE3(rdev)) {
3168 tmp = RREG32(DC_HPD1_INT_CONTROL);
3169 tmp |= DC_HPDx_INT_ACK;
3170 WREG32(DC_HPD1_INT_CONTROL, tmp);
3171 } else {
3172 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3173 tmp |= DC_HPDx_INT_ACK;
3174 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3175 }
3176 }
6f34be50 3177 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
e0df1ac5
AD		 3178 if (ASIC_IS_DCE3(rdev)) {
3179 tmp = RREG32(DC_HPD2_INT_CONTROL);
3180 tmp |= DC_HPDx_INT_ACK;
3181 WREG32(DC_HPD2_INT_CONTROL, tmp);
3182 } else {
3183 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3184 tmp |= DC_HPDx_INT_ACK;
3185 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3186 }
3187 }
6f34be50 3188 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
e0df1ac5
AD		 3189 if (ASIC_IS_DCE3(rdev)) {
3190 tmp = RREG32(DC_HPD3_INT_CONTROL);
3191 tmp |= DC_HPDx_INT_ACK;
3192 WREG32(DC_HPD3_INT_CONTROL, tmp);
3193 } else {
3194 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3195 tmp |= DC_HPDx_INT_ACK;
3196 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3197 }
3198 }
6f34be50 3199 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
e0df1ac5
AD		 3200 tmp = RREG32(DC_HPD4_INT_CONTROL);
3201 tmp |= DC_HPDx_INT_ACK;
3202 WREG32(DC_HPD4_INT_CONTROL, tmp);
3203 }
3204 if (ASIC_IS_DCE32(rdev)) {
6f34be50 3205 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
e0df1ac5
AD		 3206 tmp = RREG32(DC_HPD5_INT_CONTROL);
3207 tmp |= DC_HPDx_INT_ACK;
3208 WREG32(DC_HPD5_INT_CONTROL, tmp);
3209 }
6f34be50 3210 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
e0df1ac5
AD		 3211 tmp = RREG32(DC_HPD5_INT_CONTROL);
3212 tmp |= DC_HPDx_INT_ACK;
3213 WREG32(DC_HPD6_INT_CONTROL, tmp);
3214 }
3215 }
f2594933
CK		 3216 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3217 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3218 }
3219 if (ASIC_IS_DCE3(rdev)) {
3220 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3221 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3222 }
3223 } else {
3224 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3225 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3226 }
3227 }
d8f60cfc
AD		 3228}
3229
3230void r600_irq_disable(struct radeon_device *rdev)
3231{
d8f60cfc
AD		 3232 r600_disable_interrupts(rdev);
3233 /* Wait and acknowledge irq */
3234 mdelay(1);
6f34be50 3235 r600_irq_ack(rdev);
e0df1ac5 3236 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3237}
3238
3239static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3240{
3241 u32 wptr, tmp;
3ce0a23d 3242
724c80e1 3243 if (rdev->wb.enabled)
204ae24d 3244 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 3245 else
3246 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3247
d8f60cfc 3248 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3249 /* When a ring buffer overflow happen start parsing interrupt
3250 * from the last not overwritten vector (wptr + 16). Hopefully
3251 * this should allow us to catchup.
3252 */
3253 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3254 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3255 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3256 tmp = RREG32(IH_RB_CNTL);
3257 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3258 WREG32(IH_RB_CNTL, tmp);
3259 }
0c45249f 3260 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3261}
3ce0a23d 3262
d8f60cfc
AD		 3263/* r600 IV Ring
3264 * Each IV ring entry is 128 bits:
3265 * [7:0] - interrupt source id
3266 * [31:8] - reserved
3267 * [59:32] - interrupt source data
3268 * [127:60] - reserved
3269 *
3270 * The basic interrupt vector entries
3271 * are decoded as follows:
3272 * src_id src_data description
3273 * 1 0 D1 Vblank
3274 * 1 1 D1 Vline
3275 * 5 0 D2 Vblank
3276 * 5 1 D2 Vline
3277 * 19 0 FP Hot plug detection A
3278 * 19 1 FP Hot plug detection B
3279 * 19 2 DAC A auto-detection
3280 * 19 3 DAC B auto-detection
f2594933
CK		 3281 * 21 4 HDMI block A
3282 * 21 5 HDMI block B
d8f60cfc
AD		 3283 * 176 - CP_INT RB
3284 * 177 - CP_INT IB1
3285 * 178 - CP_INT IB2
3286 * 181 - EOP Interrupt
3287 * 233 - GUI Idle
3288 *
3289 * Note, these are based on r600 and may need to be
3290 * adjusted or added to on newer asics
3291 */
3292
3293int r600_irq_process(struct radeon_device *rdev)
3294{
682f1a54
DA		 3295 u32 wptr;
3296 u32 rptr;
d8f60cfc 3297 u32 src_id, src_data;
6f34be50 3298 u32 ring_index;
d8f60cfc 3299 unsigned long flags;
d4877cf2 3300 bool queue_hotplug = false;
d8f60cfc 3301
682f1a54 3302 if (!rdev->ih.enabled || rdev->shutdown)
79c2bbc5 3303 return IRQ_NONE;
d8f60cfc 3304
f6a56939
BH		 3305 /* No MSIs, need a dummy read to flush PCI DMAs */
3306 if (!rdev->msi_enabled)
3307 RREG32(IH_RB_WPTR);
3308
682f1a54
DA		 3309 wptr = r600_get_ih_wptr(rdev);
3310 rptr = rdev->ih.rptr;
3311 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3312
d8f60cfc
AD		 3313 spin_lock_irqsave(&rdev->ih.lock, flags);
3314
3315 if (rptr == wptr) {
3316 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3317 return IRQ_NONE;
3318 }
d8f60cfc
AD		 3319
3320restart_ih:
3321 /* display interrupts */
6f34be50 3322 r600_irq_ack(rdev);
d8f60cfc
AD		 3323
3324 rdev->ih.wptr = wptr;
3325 while (rptr != wptr) {
3326 /* wptr/rptr are in bytes! */
3327 ring_index = rptr / 4;
4eace7fd
CC		 3328 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3329 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
d8f60cfc
AD		 3330
3331 switch (src_id) {
3332 case 1: /* D1 vblank/vline */
3333 switch (src_data) {
3334 case 0: /* D1 vblank */
6f34be50 3335 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3336 if (rdev->irq.crtc_vblank_int[0]) {
3337 drm_handle_vblank(rdev->ddev, 0);
3338 rdev->pm.vblank_sync = true;
3339 wake_up(&rdev->irq.vblank_queue);
3340 }
3e4ea742
MK		 3341 if (rdev->irq.pflip[0])
3342 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3343 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
d8f60cfc
AD		 3344 DRM_DEBUG("IH: D1 vblank\n");
3345 }
3346 break;
3347 case 1: /* D1 vline */
6f34be50
AD		 3348 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3349 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
d8f60cfc
AD		 3350 DRM_DEBUG("IH: D1 vline\n");
3351 }
3352 break;
3353 default:
b042589c 3354 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3355 break;
3356 }
3357 break;
3358 case 5: /* D2 vblank/vline */
3359 switch (src_data) {
3360 case 0: /* D2 vblank */
6f34be50 3361 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3362 if (rdev->irq.crtc_vblank_int[1]) {
3363 drm_handle_vblank(rdev->ddev, 1);
3364 rdev->pm.vblank_sync = true;
3365 wake_up(&rdev->irq.vblank_queue);
3366 }
3e4ea742
MK		 3367 if (rdev->irq.pflip[1])
3368 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3369 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
d8f60cfc
AD		 3370 DRM_DEBUG("IH: D2 vblank\n");
3371 }
3372 break;
3373 case 1: /* D1 vline */
6f34be50
AD		 3374 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3375 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
d8f60cfc
AD		 3376 DRM_DEBUG("IH: D2 vline\n");
3377 }
3378 break;
3379 default:
b042589c 3380 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3381 break;
3382 }
3383 break;
e0df1ac5
AD		 3384 case 19: /* HPD/DAC hotplug */
3385 switch (src_data) {
3386 case 0:
6f34be50
AD		 3387 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3388 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3389 queue_hotplug = true;
3390 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3391 }
3392 break;
3393 case 1:
6f34be50
AD		 3394 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3395 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3396 queue_hotplug = true;
3397 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3398 }
3399 break;
3400 case 4:
6f34be50
AD		 3401 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3402 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3403 queue_hotplug = true;
3404 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3405 }
3406 break;
3407 case 5:
6f34be50
AD		 3408 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3409 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3410 queue_hotplug = true;
3411 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3412 }
3413 break;
3414 case 10:
6f34be50
AD		 3415 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3416 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3417 queue_hotplug = true;
3418 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3419 }
3420 break;
3421 case 12:
6f34be50
AD		 3422 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3423 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3424 queue_hotplug = true;
3425 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3426 }
3427 break;
3428 default:
b042589c 3429 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3430 break;
3431 }
3432 break;
f2594933
CK		 3433 case 21: /* HDMI */
3434 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3435 r600_audio_schedule_polling(rdev);
3436 break;
d8f60cfc
AD		 3437 case 176: /* CP_INT in ring buffer */
3438 case 177: /* CP_INT in IB1 */
3439 case 178: /* CP_INT in IB2 */
3440 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3441 radeon_fence_process(rdev);
3442 break;
3443 case 181: /* CP EOP event */
3444 DRM_DEBUG("IH: CP EOP\n");
d0f8a854 3445 radeon_fence_process(rdev);
d8f60cfc 3446 break;
2031f77c 3447 case 233: /* GUI IDLE */
303c805c 3448 DRM_DEBUG("IH: GUI idle\n");
2031f77c
AD		 3449 rdev->pm.gui_idle = true;
3450 wake_up(&rdev->irq.idle_queue);
3451 break;
d8f60cfc 3452 default:
b042589c 3453 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3454 break;
3455 }
3456
3457 /* wptr/rptr are in bytes! */
0c45249f
JG		 3458 rptr += 16;
3459 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 3460 }
3461 /* make sure wptr hasn't changed while processing */
3462 wptr = r600_get_ih_wptr(rdev);
3463 if (wptr != rdev->ih.wptr)
3464 goto restart_ih;
d4877cf2 3465 if (queue_hotplug)
32c87fca 3466 schedule_work(&rdev->hotplug_work);
d8f60cfc
AD		 3467 rdev->ih.rptr = rptr;
3468 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3469 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3470 return IRQ_HANDLED;
3471}
3ce0a23d
JG		 3472
3473/*
3474 * Debugfs info
3475 */
3476#if defined(CONFIG_DEBUG_FS)
3477
3478static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
771fe6b9 3479{
3ce0a23d
JG		 3480 struct drm_info_node *node = (struct drm_info_node *) m->private;
3481 struct drm_device *dev = node->minor->dev;
3482 struct radeon_device *rdev = dev->dev_private;
3ce0a23d
JG		 3483 unsigned count, i, j;
3484
3485 radeon_ring_free_size(rdev);
d6840766 3486 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3ce0a23d 3487 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
d6840766
RM		 3488 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3489 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3490 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3491 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3ce0a23d
JG		 3492 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3493 seq_printf(m, "%u dwords in ring\n", count);
d6840766 3494 i = rdev->cp.rptr;
3ce0a23d 3495 for (j = 0; j <= count; j++) {
3ce0a23d 3496 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
d6840766 3497 i = (i + 1) & rdev->cp.ptr_mask;
3ce0a23d
JG		 3498 }
3499 return 0;
3500}
3501
3502static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3503{
3504 struct drm_info_node *node = (struct drm_info_node *) m->private;
3505 struct drm_device *dev = node->minor->dev;
3506 struct radeon_device *rdev = dev->dev_private;
3507
3508 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3509 DREG32_SYS(m, rdev, VM_L2_STATUS);
3510 return 0;
3511}
3512
3513static struct drm_info_list r600_mc_info_list[] = {
3514 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3515 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3516};
3517#endif
3518
3519int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3520{
3521#if defined(CONFIG_DEBUG_FS)
3522 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3523#else
3524 return 0;
3525#endif
771fe6b9 3526}
062b389c
JG		 3527
3528/**
3529 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3530 * rdev: radeon device structure
3531 * bo: buffer object struct which userspace is waiting for idle
3532 *
3533 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3534 * through ring buffer, this leads to corruption in rendering, see
3535 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3536 * directly perform HDP flush by writing register through MMIO.
3537 */
3538void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3539{
812d0469 3540 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 3541 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3542 * This seems to cause problems on some AGP cards. Just use the old
3543 * method for them.
812d0469 3544 */
e488459a 3545 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 3546 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 3547 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 3548 u32 tmp;
3549
3550 WREG32(HDP_DEBUG1, 0);
3551 tmp = readl((void __iomem *)ptr);
3552 } else
3553 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 3554}
3313e3d4
AD		 3555
3556void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3557{
3558 u32 link_width_cntl, mask, target_reg;
3559
3560 if (rdev->flags & RADEON_IS_IGP)
3561 return;
3562
3563 if (!(rdev->flags & RADEON_IS_PCIE))
3564 return;
3565
3566 /* x2 cards have a special sequence */
3567 if (ASIC_IS_X2(rdev))
3568 return;
3569
3570 /* FIXME wait for idle */
3571
3572 switch (lanes) {
3573 case 0:
3574 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3575 break;
3576 case 1:
3577 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3578 break;
3579 case 2:
3580 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3581 break;
3582 case 4:
3583 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3584 break;
3585 case 8:
3586 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3587 break;
3588 case 12:
3589 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3590 break;
3591 case 16:
3592 default:
3593 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3594 break;
3595 }
3596
3597 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3598
3599 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3600 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3601 return;
3602
3603 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3604 return;
3605
3606 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3607 RADEON_PCIE_LC_RECONFIG_NOW |
3608 R600_PCIE_LC_RENEGOTIATE_EN |
3609 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3610 link_width_cntl |= mask;
3611
3612 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3613
3614 /* some northbridges can renegotiate the link rather than requiring
3615 * a complete re-config.
3616 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3617 */
3618 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3619 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3620 else
3621 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3622
3623 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3624 RADEON_PCIE_LC_RECONFIG_NOW));
3625
3626 if (rdev->family >= CHIP_RV770)
3627 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3628 else
3629 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3630
3631 /* wait for lane set to complete */
3632 link_width_cntl = RREG32(target_reg);
3633 while (link_width_cntl == 0xffffffff)
3634 link_width_cntl = RREG32(target_reg);
3635
3636}
3637
3638int r600_get_pcie_lanes(struct radeon_device *rdev)
3639{
3640 u32 link_width_cntl;
3641
3642 if (rdev->flags & RADEON_IS_IGP)
3643 return 0;
3644
3645 if (!(rdev->flags & RADEON_IS_PCIE))
3646 return 0;
3647
3648 /* x2 cards have a special sequence */
3649 if (ASIC_IS_X2(rdev))
3650 return 0;
3651
3652 /* FIXME wait for idle */
3653
3654 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3655
3656 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3657 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3658 return 0;
3659 case RADEON_PCIE_LC_LINK_WIDTH_X1:
3660 return 1;
3661 case RADEON_PCIE_LC_LINK_WIDTH_X2:
3662 return 2;
3663 case RADEON_PCIE_LC_LINK_WIDTH_X4:
3664 return 4;
3665 case RADEON_PCIE_LC_LINK_WIDTH_X8:
3666 return 8;
3667 case RADEON_PCIE_LC_LINK_WIDTH_X16:
3668 default:
3669 return 16;
3670 }
3671}
3672
9e46a48d
AD		 3673static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3674{
3675 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3676 u16 link_cntl2;
3677
d42dd579
AD		 3678 if (radeon_pcie_gen2 == 0)
3679 return;
3680
9e46a48d
AD		 3681 if (rdev->flags & RADEON_IS_IGP)
3682 return;
3683
3684 if (!(rdev->flags & RADEON_IS_PCIE))
3685 return;
3686
3687 /* x2 cards have a special sequence */
3688 if (ASIC_IS_X2(rdev))
3689 return;
3690
3691 /* only RV6xx+ chips are supported */
3692 if (rdev->family <= CHIP_R600)
3693 return;
3694
3695 /* 55 nm r6xx asics */
3696 if ((rdev->family == CHIP_RV670) ||
3697 (rdev->family == CHIP_RV620) ||
3698 (rdev->family == CHIP_RV635)) {
3699 /* advertise upconfig capability */
3700 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3701 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3702 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3703 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3704 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3705 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3706 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3707 LC_RECONFIG_ARC_MISSING_ESCAPE);
3708 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3709 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3710 } else {
3711 link_width_cntl |= LC_UPCONFIGURE_DIS;
3712 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3713 }
3714 }
3715
3716 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3717 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3718 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3719
3720 /* 55 nm r6xx asics */
3721 if ((rdev->family == CHIP_RV670) ||
3722 (rdev->family == CHIP_RV620) ||
3723 (rdev->family == CHIP_RV635)) {
3724 WREG32(MM_CFGREGS_CNTL, 0x8);
3725 link_cntl2 = RREG32(0x4088);
3726 WREG32(MM_CFGREGS_CNTL, 0);
3727 /* not supported yet */
3728 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3729 return;
3730 }
3731
3732 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3733 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3734 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3735 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3736 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3737 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3738
3739 tmp = RREG32(0x541c);
3740 WREG32(0x541c, tmp | 0x8);
3741 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3742 link_cntl2 = RREG16(0x4088);
3743 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3744 link_cntl2 |= 0x2;
3745 WREG16(0x4088, link_cntl2);
3746 WREG32(MM_CFGREGS_CNTL, 0);
3747
3748 if ((rdev->family == CHIP_RV670) ||
3749 (rdev->family == CHIP_RV620) ||
3750 (rdev->family == CHIP_RV635)) {
3751 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3752 training_cntl &= ~LC_POINT_7_PLUS_EN;
3753 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3754 } else {
3755 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3756 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3757 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3758 }
3759
3760 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3761 speed_cntl |= LC_GEN2_EN_STRAP;
3762 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3763
3764 } else {
3765 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3766 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3767 if (1)
3768 link_width_cntl |= LC_UPCONFIGURE_DIS;
3769 else
3770 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3771 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3772 }
3773}
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