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drm/radeon: remove unnecessary VM syncs
[linux-2.6-block.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
e0cd3608 31#include <linux/module.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
138e4e16 40#include "radeon_ucode.h"
3ce0a23d
JG		 41
42/* Firmware Names */
43MODULE_FIRMWARE("radeon/R600_pfp.bin");
44MODULE_FIRMWARE("radeon/R600_me.bin");
45MODULE_FIRMWARE("radeon/RV610_pfp.bin");
46MODULE_FIRMWARE("radeon/RV610_me.bin");
47MODULE_FIRMWARE("radeon/RV630_pfp.bin");
48MODULE_FIRMWARE("radeon/RV630_me.bin");
49MODULE_FIRMWARE("radeon/RV620_pfp.bin");
50MODULE_FIRMWARE("radeon/RV620_me.bin");
51MODULE_FIRMWARE("radeon/RV635_pfp.bin");
52MODULE_FIRMWARE("radeon/RV635_me.bin");
53MODULE_FIRMWARE("radeon/RV670_pfp.bin");
54MODULE_FIRMWARE("radeon/RV670_me.bin");
55MODULE_FIRMWARE("radeon/RS780_pfp.bin");
56MODULE_FIRMWARE("radeon/RS780_me.bin");
57MODULE_FIRMWARE("radeon/RV770_pfp.bin");
58MODULE_FIRMWARE("radeon/RV770_me.bin");
66229b20 59MODULE_FIRMWARE("radeon/RV770_smc.bin");
3ce0a23d
JG		 60MODULE_FIRMWARE("radeon/RV730_pfp.bin");
61MODULE_FIRMWARE("radeon/RV730_me.bin");
66229b20
AD		 62MODULE_FIRMWARE("radeon/RV730_smc.bin");
63MODULE_FIRMWARE("radeon/RV740_smc.bin");
3ce0a23d
JG		 64MODULE_FIRMWARE("radeon/RV710_pfp.bin");
65MODULE_FIRMWARE("radeon/RV710_me.bin");
66229b20 66MODULE_FIRMWARE("radeon/RV710_smc.bin");
d8f60cfc
AD		 67MODULE_FIRMWARE("radeon/R600_rlc.bin");
68MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 69MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
70MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 71MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
dc50ba7f 72MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
fe251e2f
AD		 73MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
74MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 75MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
dc50ba7f 76MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
78MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
dc50ba7f 80MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
a7433742 81MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 82MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 83MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
dc50ba7f 84MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
439bd6cd
AD		 85MODULE_FIRMWARE("radeon/PALM_pfp.bin");
86MODULE_FIRMWARE("radeon/PALM_me.bin");
87MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
d5c5a72f
AD		 88MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
89MODULE_FIRMWARE("radeon/SUMO_me.bin");
90MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
91MODULE_FIRMWARE("radeon/SUMO2_me.bin");
3ce0a23d 92
f13f7731
AD		 93static const u32 crtc_offsets[2] =
94{
95 0,
96 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
97};
98
3ce0a23d 99int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 100
1a029b76 101/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9 102int r600_mc_wait_for_idle(struct radeon_device *rdev);
1109ca09 103static void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 104void r600_fini(struct radeon_device *rdev);
45f9a39b 105void r600_irq_disable(struct radeon_device *rdev);
9e46a48d 106static void r600_pcie_gen2_enable(struct radeon_device *rdev);
2948f5e6 107extern int evergreen_rlc_resume(struct radeon_device *rdev);
de9ae744 108extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
771fe6b9 109
454d2e2a
AD		 110/**
111 * r600_get_xclk - get the xclk
112 *
113 * @rdev: radeon_device pointer
114 *
115 * Returns the reference clock used by the gfx engine
116 * (r6xx, IGPs, APUs).
117 */
118u32 r600_get_xclk(struct radeon_device *rdev)
119{
120 return rdev->clock.spll.reference_freq;
121}
122
1b9ba70a
AD		 123int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
124{
4a956a70
AD		 125 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0;
126 int r;
127
128 /* bypass vclk and dclk with bclk */
129 WREG32_P(CG_UPLL_FUNC_CNTL_2,
130 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
131 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
132
133 /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */
134 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(
135 UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK));
136
137 if (rdev->family >= CHIP_RS780)
138 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL,
139 ~UPLL_BYPASS_CNTL);
140
141 if (!vclk || !dclk) {
142 /* keep the Bypass mode, put PLL to sleep */
143 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
144 return 0;
145 }
146
147 if (rdev->clock.spll.reference_freq == 10000)
148 ref_div = 34;
149 else
150 ref_div = 4;
151
152 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
153 ref_div + 1, 0xFFF, 2, 30, ~0,
154 &fb_div, &vclk_div, &dclk_div);
155 if (r)
156 return r;
157
158 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780)
159 fb_div >>= 1;
160 else
161 fb_div |= 1;
162
163 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
164 if (r)
165 return r;
166
167 /* assert PLL_RESET */
168 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
169
170 /* For RS780 we have to choose ref clk */
171 if (rdev->family >= CHIP_RS780)
172 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,
173 ~UPLL_REFCLK_SRC_SEL_MASK);
174
175 /* set the required fb, ref and post divder values */
176 WREG32_P(CG_UPLL_FUNC_CNTL,
177 UPLL_FB_DIV(fb_div) |
178 UPLL_REF_DIV(ref_div),
179 ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK));
180 WREG32_P(CG_UPLL_FUNC_CNTL_2,
181 UPLL_SW_HILEN(vclk_div >> 1) |
182 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
183 UPLL_SW_HILEN2(dclk_div >> 1) |
184 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) |
185 UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK,
186 ~UPLL_SW_MASK);
187
188 /* give the PLL some time to settle */
189 mdelay(15);
190
191 /* deassert PLL_RESET */
192 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
193
194 mdelay(15);
195
196 /* deassert BYPASS EN */
197 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
198
199 if (rdev->family >= CHIP_RS780)
200 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL);
201
202 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
203 if (r)
204 return r;
205
206 /* switch VCLK and DCLK selection */
207 WREG32_P(CG_UPLL_FUNC_CNTL_2,
208 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
209 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
210
211 mdelay(100);
212
1b9ba70a
AD		 213 return 0;
214}
215
134b480f
AD		 216void dce3_program_fmt(struct drm_encoder *encoder)
217{
218 struct drm_device *dev = encoder->dev;
219 struct radeon_device *rdev = dev->dev_private;
220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
222 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
223 int bpc = 0;
224 u32 tmp = 0;
6214bb74 225 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
134b480f 226
6214bb74
AD		 227 if (connector) {
228 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
134b480f 229 bpc = radeon_get_monitor_bpc(connector);
6214bb74
AD		 230 dither = radeon_connector->dither;
231 }
134b480f
AD		 232
233 /* LVDS FMT is set up by atom */
234 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
235 return;
236
237 /* not needed for analog */
238 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
239 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
240 return;
241
242 if (bpc == 0)
243 return;
244
245 switch (bpc) {
246 case 6:
6214bb74 247 if (dither == RADEON_FMT_DITHER_ENABLE)
134b480f
AD		 248 /* XXX sort out optimal dither settings */
249 tmp |= FMT_SPATIAL_DITHER_EN;
250 else
251 tmp |= FMT_TRUNCATE_EN;
252 break;
253 case 8:
6214bb74 254 if (dither == RADEON_FMT_DITHER_ENABLE)
134b480f
AD		 255 /* XXX sort out optimal dither settings */
256 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
257 else
258 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
259 break;
260 case 10:
261 default:
262 /* not needed */
263 break;
264 }
265
266 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
267}
268
21a8122a 269/* get temperature in millidegrees */
20d391d7 270int rv6xx_get_temp(struct radeon_device *rdev)
21a8122a
AD		 271{
272 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
273 ASIC_T_SHIFT;
20d391d7 274 int actual_temp = temp & 0xff;
21a8122a 275
20d391d7
AD		 276 if (temp & 0x100)
277 actual_temp -= 256;
278
279 return actual_temp * 1000;
21a8122a
AD		 280}
281
ce8f5370 282void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 283{
284 int i;
285
ce8f5370
AD		 286 rdev->pm.dynpm_can_upclock = true;
287 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 288
289 /* power state array is low to high, default is first */
290 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
291 int min_power_state_index = 0;
292
293 if (rdev->pm.num_power_states > 2)
294 min_power_state_index = 1;
295
ce8f5370
AD		 296 switch (rdev->pm.dynpm_planned_action) {
297 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 298 rdev->pm.requested_power_state_index = min_power_state_index;
299 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 300 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 301 break;
ce8f5370 302 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 303 if (rdev->pm.current_power_state_index == min_power_state_index) {
304 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 305 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 306 } else {
307 if (rdev->pm.active_crtc_count > 1) {
308 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 309 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 310 continue;
311 else if (i >= rdev->pm.current_power_state_index) {
312 rdev->pm.requested_power_state_index =
313 rdev->pm.current_power_state_index;
314 break;
315 } else {
316 rdev->pm.requested_power_state_index = i;
317 break;
318 }
319 }
773c3fa3
AD		 320 } else {
321 if (rdev->pm.current_power_state_index == 0)
322 rdev->pm.requested_power_state_index =
323 rdev->pm.num_power_states - 1;
324 else
325 rdev->pm.requested_power_state_index =
326 rdev->pm.current_power_state_index - 1;
327 }
a48b9b4e
AD		 328 }
329 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 330 /* don't use the power state if crtcs are active and no display flag is set */
331 if ((rdev->pm.active_crtc_count > 0) &&
332 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
333 clock_info[rdev->pm.requested_clock_mode_index].flags &
334 RADEON_PM_MODE_NO_DISPLAY)) {
335 rdev->pm.requested_power_state_index++;
336 }
a48b9b4e 337 break;
ce8f5370 338 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 339 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
340 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 341 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 342 } else {
343 if (rdev->pm.active_crtc_count > 1) {
344 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 345 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 346 continue;
347 else if (i <= rdev->pm.current_power_state_index) {
348 rdev->pm.requested_power_state_index =
349 rdev->pm.current_power_state_index;
350 break;
351 } else {
352 rdev->pm.requested_power_state_index = i;
353 break;
354 }
355 }
356 } else
357 rdev->pm.requested_power_state_index =
358 rdev->pm.current_power_state_index + 1;
359 }
360 rdev->pm.requested_clock_mode_index = 0;
361 break;
ce8f5370 362 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 363 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
364 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 365 rdev->pm.dynpm_can_upclock = false;
58e21dff 366 break;
ce8f5370 367 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 368 default:
369 DRM_ERROR("Requested mode for not defined action\n");
370 return;
371 }
372 } else {
373 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
374 /* for now just select the first power state and switch between clock modes */
375 /* power state array is low to high, default is first (0) */
376 if (rdev->pm.active_crtc_count > 1) {
377 rdev->pm.requested_power_state_index = -1;
378 /* start at 1 as we don't want the default mode */
379 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 380 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 381 continue;
382 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
383 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
384 rdev->pm.requested_power_state_index = i;
385 break;
386 }
387 }
388 /* if nothing selected, grab the default state. */
389 if (rdev->pm.requested_power_state_index == -1)
390 rdev->pm.requested_power_state_index = 0;
391 } else
392 rdev->pm.requested_power_state_index = 1;
393
ce8f5370
AD		 394 switch (rdev->pm.dynpm_planned_action) {
395 case DYNPM_ACTION_MINIMUM:
a48b9b4e 396 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 397 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 398 break;
ce8f5370 399 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 400 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
401 if (rdev->pm.current_clock_mode_index == 0) {
402 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 403 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 404 } else
405 rdev->pm.requested_clock_mode_index =
406 rdev->pm.current_clock_mode_index - 1;
407 } else {
408 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 409 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 410 }
d7311171
AD		 411 /* don't use the power state if crtcs are active and no display flag is set */
412 if ((rdev->pm.active_crtc_count > 0) &&
413 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
414 clock_info[rdev->pm.requested_clock_mode_index].flags &
415 RADEON_PM_MODE_NO_DISPLAY)) {
416 rdev->pm.requested_clock_mode_index++;
417 }
a48b9b4e 418 break;
ce8f5370 419 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 420 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
421 if (rdev->pm.current_clock_mode_index ==
422 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
423 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 424 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 425 } else
426 rdev->pm.requested_clock_mode_index =
427 rdev->pm.current_clock_mode_index + 1;
428 } else {
429 rdev->pm.requested_clock_mode_index =
430 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 431 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 432 }
433 break;
ce8f5370 434 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 435 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
436 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 437 rdev->pm.dynpm_can_upclock = false;
58e21dff 438 break;
ce8f5370 439 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 440 default:
441 DRM_ERROR("Requested mode for not defined action\n");
442 return;
443 }
444 }
445
d9fdaafb 446 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 447 rdev->pm.power_state[rdev->pm.requested_power_state_index].
448 clock_info[rdev->pm.requested_clock_mode_index].sclk,
449 rdev->pm.power_state[rdev->pm.requested_power_state_index].
450 clock_info[rdev->pm.requested_clock_mode_index].mclk,
451 rdev->pm.power_state[rdev->pm.requested_power_state_index].
452 pcie_lanes);
a48b9b4e
AD		 453}
454
ce8f5370
AD		 455void rs780_pm_init_profile(struct radeon_device *rdev)
456{
457 if (rdev->pm.num_power_states == 2) {
458 /* default */
459 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
460 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
461 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
462 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
463 /* low sh */
464 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
465 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
466 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
467 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 468 /* mid sh */
469 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
470 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
471 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
472 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 473 /* high sh */
474 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
475 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
476 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
477 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
478 /* low mh */
479 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
480 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
481 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
482 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 483 /* mid mh */
484 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
485 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
486 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
487 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 488 /* high mh */
489 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
490 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
491 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
492 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
493 } else if (rdev->pm.num_power_states == 3) {
494 /* default */
495 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
496 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
497 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
498 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
499 /* low sh */
500 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
501 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
502 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
503 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 504 /* mid sh */
505 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
506 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
507 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
508 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 509 /* high sh */
510 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
511 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
512 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
513 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
514 /* low mh */
515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
518 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 519 /* mid mh */
520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
522 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
523 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 524 /* high mh */
525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
528 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
529 } else {
530 /* default */
531 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
532 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
533 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
534 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
535 /* low sh */
536 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
537 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
538 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
539 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 540 /* mid sh */
541 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
542 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
543 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
544 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 545 /* high sh */
546 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
547 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
548 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
549 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
550 /* low mh */
551 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
552 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
553 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
554 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 555 /* mid mh */
556 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
557 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
558 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
559 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 560 /* high mh */
561 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
562 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
563 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
564 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
565 }
566}
bae6b562 567
ce8f5370
AD		 568void r600_pm_init_profile(struct radeon_device *rdev)
569{
bbe26ffe
AD		 570 int idx;
571
ce8f5370
AD		 572 if (rdev->family == CHIP_R600) {
573 /* XXX */
574 /* default */
575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 579 /* low sh */
580 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 584 /* mid sh */
585 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 589 /* high sh */
590 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 594 /* low mh */
595 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 599 /* mid mh */
600 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 604 /* high mh */
605 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 609 } else {
610 if (rdev->pm.num_power_states < 4) {
611 /* default */
612 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
614 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
615 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
616 /* low sh */
4bff5171
AD		 617 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 619 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 620 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
621 /* mid sh */
622 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
624 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
625 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 626 /* high sh */
4bff5171
AD		 627 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 629 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
630 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
631 /* low mh */
4bff5171
AD		 632 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 634 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 635 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
636 /* low mh */
637 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
639 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
640 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 641 /* high mh */
4bff5171
AD		 642 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 644 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
645 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
646 } else {
647 /* default */
648 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
649 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
650 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
651 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
652 /* low sh */
bbe26ffe
AD		 653 if (rdev->flags & RADEON_IS_MOBILITY)
654 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
655 else
656 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
657 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
658 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
659 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
660 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21 661 /* mid sh */
bbe26ffe
AD		 662 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
663 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
664 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
665 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 666 /* high sh */
bbe26ffe
AD		 667 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
668 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
669 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 670 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
671 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
672 /* low mh */
bbe26ffe
AD		 673 if (rdev->flags & RADEON_IS_MOBILITY)
674 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
675 else
676 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
678 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
679 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
680 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21 681 /* mid mh */
bbe26ffe
AD		 682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
683 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
684 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
685 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 686 /* high mh */
bbe26ffe
AD		 687 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
688 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
689 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 690 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
691 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
692 }
693 }
bae6b562
AD		 694}
695
49e02b73
AD		 696void r600_pm_misc(struct radeon_device *rdev)
697{
a081a9d6
RM		 698 int req_ps_idx = rdev->pm.requested_power_state_index;
699 int req_cm_idx = rdev->pm.requested_clock_mode_index;
700 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
701 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 702
4d60173f 703 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
a377e187
AD		 704 /* 0xff01 is a flag rather then an actual voltage */
705 if (voltage->voltage == 0xff01)
706 return;
4d60173f 707 if (voltage->voltage != rdev->pm.current_vddc) {
8a83ec5e 708 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 709 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 710 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 711 }
712 }
49e02b73
AD		 713}
714
def9ba9c
AD		 715bool r600_gui_idle(struct radeon_device *rdev)
716{
717 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
718 return false;
719 else
720 return true;
721}
722
e0df1ac5
AD		 723/* hpd for digital panel detect/disconnect */
724bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
725{
726 bool connected = false;
727
728 if (ASIC_IS_DCE3(rdev)) {
729 switch (hpd) {
730 case RADEON_HPD_1:
731 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
732 connected = true;
733 break;
734 case RADEON_HPD_2:
735 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
736 connected = true;
737 break;
738 case RADEON_HPD_3:
739 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
740 connected = true;
741 break;
742 case RADEON_HPD_4:
743 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
744 connected = true;
745 break;
746 /* DCE 3.2 */
747 case RADEON_HPD_5:
748 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
749 connected = true;
750 break;
751 case RADEON_HPD_6:
752 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
753 connected = true;
754 break;
755 default:
756 break;
757 }
758 } else {
759 switch (hpd) {
760 case RADEON_HPD_1:
761 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
762 connected = true;
763 break;
764 case RADEON_HPD_2:
765 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
766 connected = true;
767 break;
768 case RADEON_HPD_3:
769 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
770 connected = true;
771 break;
772 default:
773 break;
774 }
775 }
776 return connected;
777}
778
779void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 780 enum radeon_hpd_id hpd)
e0df1ac5
AD		 781{
782 u32 tmp;
783 bool connected = r600_hpd_sense(rdev, hpd);
784
785 if (ASIC_IS_DCE3(rdev)) {
786 switch (hpd) {
787 case RADEON_HPD_1:
788 tmp = RREG32(DC_HPD1_INT_CONTROL);
789 if (connected)
790 tmp &= ~DC_HPDx_INT_POLARITY;
791 else
792 tmp |= DC_HPDx_INT_POLARITY;
793 WREG32(DC_HPD1_INT_CONTROL, tmp);
794 break;
795 case RADEON_HPD_2:
796 tmp = RREG32(DC_HPD2_INT_CONTROL);
797 if (connected)
798 tmp &= ~DC_HPDx_INT_POLARITY;
799 else
800 tmp |= DC_HPDx_INT_POLARITY;
801 WREG32(DC_HPD2_INT_CONTROL, tmp);
802 break;
803 case RADEON_HPD_3:
804 tmp = RREG32(DC_HPD3_INT_CONTROL);
805 if (connected)
806 tmp &= ~DC_HPDx_INT_POLARITY;
807 else
808 tmp |= DC_HPDx_INT_POLARITY;
809 WREG32(DC_HPD3_INT_CONTROL, tmp);
810 break;
811 case RADEON_HPD_4:
812 tmp = RREG32(DC_HPD4_INT_CONTROL);
813 if (connected)
814 tmp &= ~DC_HPDx_INT_POLARITY;
815 else
816 tmp |= DC_HPDx_INT_POLARITY;
817 WREG32(DC_HPD4_INT_CONTROL, tmp);
818 break;
819 case RADEON_HPD_5:
820 tmp = RREG32(DC_HPD5_INT_CONTROL);
821 if (connected)
822 tmp &= ~DC_HPDx_INT_POLARITY;
823 else
824 tmp |= DC_HPDx_INT_POLARITY;
825 WREG32(DC_HPD5_INT_CONTROL, tmp);
826 break;
827 /* DCE 3.2 */
828 case RADEON_HPD_6:
829 tmp = RREG32(DC_HPD6_INT_CONTROL);
830 if (connected)
831 tmp &= ~DC_HPDx_INT_POLARITY;
832 else
833 tmp |= DC_HPDx_INT_POLARITY;
834 WREG32(DC_HPD6_INT_CONTROL, tmp);
835 break;
836 default:
837 break;
838 }
839 } else {
840 switch (hpd) {
841 case RADEON_HPD_1:
842 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
843 if (connected)
844 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
845 else
846 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
847 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
848 break;
849 case RADEON_HPD_2:
850 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
851 if (connected)
852 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
853 else
854 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
855 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
856 break;
857 case RADEON_HPD_3:
858 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
859 if (connected)
860 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
861 else
862 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
863 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
864 break;
865 default:
866 break;
867 }
868 }
869}
870
871void r600_hpd_init(struct radeon_device *rdev)
872{
873 struct drm_device *dev = rdev->ddev;
874 struct drm_connector *connector;
fb98257a 875 unsigned enable = 0;
e0df1ac5 876
64912e99
AD		 877 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
878 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
879
455c89b9
JG		 880 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
881 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
882 /* don't try to enable hpd on eDP or LVDS avoid breaking the
883 * aux dp channel on imac and help (but not completely fix)
884 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
885 */
886 continue;
887 }
64912e99
AD		 888 if (ASIC_IS_DCE3(rdev)) {
889 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
890 if (ASIC_IS_DCE32(rdev))
891 tmp |= DC_HPDx_EN;
e0df1ac5 892
e0df1ac5
AD		 893 switch (radeon_connector->hpd.hpd) {
894 case RADEON_HPD_1:
895 WREG32(DC_HPD1_CONTROL, tmp);
e0df1ac5
AD		 896 break;
897 case RADEON_HPD_2:
898 WREG32(DC_HPD2_CONTROL, tmp);
e0df1ac5
AD		 899 break;
900 case RADEON_HPD_3:
901 WREG32(DC_HPD3_CONTROL, tmp);
e0df1ac5
AD		 902 break;
903 case RADEON_HPD_4:
904 WREG32(DC_HPD4_CONTROL, tmp);
e0df1ac5
AD		 905 break;
906 /* DCE 3.2 */
907 case RADEON_HPD_5:
908 WREG32(DC_HPD5_CONTROL, tmp);
e0df1ac5
AD		 909 break;
910 case RADEON_HPD_6:
911 WREG32(DC_HPD6_CONTROL, tmp);
e0df1ac5
AD		 912 break;
913 default:
914 break;
915 }
64912e99 916 } else {
e0df1ac5
AD		 917 switch (radeon_connector->hpd.hpd) {
918 case RADEON_HPD_1:
919 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 920 break;
921 case RADEON_HPD_2:
922 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 923 break;
924 case RADEON_HPD_3:
925 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 926 break;
927 default:
928 break;
929 }
930 }
fb98257a 931 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 932 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
e0df1ac5 933 }
fb98257a 934 radeon_irq_kms_enable_hpd(rdev, enable);
e0df1ac5
AD		 935}
936
937void r600_hpd_fini(struct radeon_device *rdev)
938{
939 struct drm_device *dev = rdev->ddev;
940 struct drm_connector *connector;
fb98257a 941 unsigned disable = 0;
e0df1ac5 942
fb98257a
CK		 943 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
944 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
945 if (ASIC_IS_DCE3(rdev)) {
e0df1ac5
AD		 946 switch (radeon_connector->hpd.hpd) {
947 case RADEON_HPD_1:
948 WREG32(DC_HPD1_CONTROL, 0);
e0df1ac5
AD		 949 break;
950 case RADEON_HPD_2:
951 WREG32(DC_HPD2_CONTROL, 0);
e0df1ac5
AD		 952 break;
953 case RADEON_HPD_3:
954 WREG32(DC_HPD3_CONTROL, 0);
e0df1ac5
AD		 955 break;
956 case RADEON_HPD_4:
957 WREG32(DC_HPD4_CONTROL, 0);
e0df1ac5
AD		 958 break;
959 /* DCE 3.2 */
960 case RADEON_HPD_5:
961 WREG32(DC_HPD5_CONTROL, 0);
e0df1ac5
AD		 962 break;
963 case RADEON_HPD_6:
964 WREG32(DC_HPD6_CONTROL, 0);
e0df1ac5
AD		 965 break;
966 default:
967 break;
968 }
fb98257a 969 } else {
e0df1ac5
AD		 970 switch (radeon_connector->hpd.hpd) {
971 case RADEON_HPD_1:
972 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
e0df1ac5
AD		 973 break;
974 case RADEON_HPD_2:
975 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
e0df1ac5
AD		 976 break;
977 case RADEON_HPD_3:
978 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
e0df1ac5
AD		 979 break;
980 default:
981 break;
982 }
983 }
fb98257a 984 disable |= 1 << radeon_connector->hpd.hpd;
e0df1ac5 985 }
fb98257a 986 radeon_irq_kms_disable_hpd(rdev, disable);
e0df1ac5
AD		 987}
988
771fe6b9 989/*
3ce0a23d 990 * R600 PCIE GART
771fe6b9 991 */
3ce0a23d
JG		 992void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
993{
994 unsigned i;
995 u32 tmp;
996
2e98f10a 997 /* flush hdp cache so updates hit vram */
f3886f85
AD		 998 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
999 !(rdev->flags & RADEON_IS_AGP)) {
c9a1be96 1000 void __iomem *ptr = (void *)rdev->gart.ptr;
812d0469
AD		 1001 u32 tmp;
1002
1003 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
1004 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 1005 * This seems to cause problems on some AGP cards. Just use the old
1006 * method for them.
812d0469
AD		 1007 */
1008 WREG32(HDP_DEBUG1, 0);
1009 tmp = readl((void __iomem *)ptr);
1010 } else
1011 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 1012
3ce0a23d
JG		 1013 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
1014 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
1015 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1016 for (i = 0; i < rdev->usec_timeout; i++) {
1017 /* read MC_STATUS */
1018 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1019 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1020 if (tmp == 2) {
1021 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1022 return;
1023 }
1024 if (tmp) {
1025 return;
1026 }
1027 udelay(1);
1028 }
1029}
1030
4aac0473 1031int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 1032{
4aac0473 1033 int r;
3ce0a23d 1034
c9a1be96 1035 if (rdev->gart.robj) {
fce7d61b 1036 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 1037 return 0;
1038 }
3ce0a23d
JG		 1039 /* Initialize common gart structure */
1040 r = radeon_gart_init(rdev);
4aac0473 1041 if (r)
3ce0a23d 1042 return r;
3ce0a23d 1043 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 1044 return radeon_gart_table_vram_alloc(rdev);
1045}
1046
1109ca09 1047static int r600_pcie_gart_enable(struct radeon_device *rdev)
4aac0473
JG		 1048{
1049 u32 tmp;
1050 int r, i;
1051
c9a1be96 1052 if (rdev->gart.robj == NULL) {
4aac0473
JG		 1053 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1054 return -EINVAL;
771fe6b9 1055 }
4aac0473
JG		 1056 r = radeon_gart_table_vram_pin(rdev);
1057 if (r)
1058 return r;
bc1a631e 1059
3ce0a23d
JG		 1060 /* Setup L2 cache */
1061 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1062 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1063 EFFECTIVE_L2_QUEUE_SIZE(7));
1064 WREG32(VM_L2_CNTL2, 0);
1065 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1066 /* Setup TLB control */
1067 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1068 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1069 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1070 ENABLE_WAIT_L2_QUERY;
1071 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1072 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1073 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1074 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1075 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1076 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1077 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1078 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1079 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1080 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1081 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1082 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
a8fba64a
CK		 1083 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1084 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
3ce0a23d
JG		 1085 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1086 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1087 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 1088 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 1089 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1090 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1091 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1092 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1093 (u32)(rdev->dummy_page.addr >> 12));
1094 for (i = 1; i < 7; i++)
1095 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 1096
3ce0a23d 1097 r600_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1098 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1099 (unsigned)(rdev->mc.gtt_size >> 20),
1100 (unsigned long long)rdev->gart.table_addr);
3ce0a23d 1101 rdev->gart.ready = true;
771fe6b9
JG		 1102 return 0;
1103}
1104
1109ca09 1105static void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 1106{
3ce0a23d 1107 u32 tmp;
c9a1be96 1108 int i;
771fe6b9 1109
3ce0a23d
JG		 1110 /* Disable all tables */
1111 for (i = 0; i < 7; i++)
1112 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 1113
3ce0a23d
JG		 1114 /* Disable L2 cache */
1115 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1116 EFFECTIVE_L2_QUEUE_SIZE(7));
1117 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1118 /* Setup L1 TLB control */
1119 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1120 ENABLE_WAIT_L2_QUERY;
1121 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1122 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1123 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1124 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1125 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1126 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1127 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1128 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1129 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1130 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1131 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1132 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1133 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1134 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
a8fba64a
CK		 1135 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
1136 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
c9a1be96 1137 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 1138}
1139
1109ca09 1140static void r600_pcie_gart_fini(struct radeon_device *rdev)
4aac0473 1141{
f9274562 1142 radeon_gart_fini(rdev);
4aac0473
JG		 1143 r600_pcie_gart_disable(rdev);
1144 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1145}
1146
1109ca09 1147static void r600_agp_enable(struct radeon_device *rdev)
1a029b76
JG		 1148{
1149 u32 tmp;
1150 int i;
1151
1152 /* Setup L2 cache */
1153 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1154 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1155 EFFECTIVE_L2_QUEUE_SIZE(7));
1156 WREG32(VM_L2_CNTL2, 0);
1157 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1158 /* Setup TLB control */
1159 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1160 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1161 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1162 ENABLE_WAIT_L2_QUERY;
1163 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1164 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1165 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1166 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1167 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1168 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1169 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1170 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1171 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1172 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1173 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1174 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1175 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1176 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1177 for (i = 0; i < 7; i++)
1178 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1179}
1180
771fe6b9
JG		 1181int r600_mc_wait_for_idle(struct radeon_device *rdev)
1182{
3ce0a23d
JG		 1183 unsigned i;
1184 u32 tmp;
1185
1186 for (i = 0; i < rdev->usec_timeout; i++) {
1187 /* read MC_STATUS */
1188 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1189 if (!tmp)
1190 return 0;
1191 udelay(1);
1192 }
1193 return -1;
771fe6b9
JG		 1194}
1195
65337e60
SL		 1196uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1197{
0a5b7b0b 1198 unsigned long flags;
65337e60
SL		 1199 uint32_t r;
1200
0a5b7b0b 1201 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
65337e60
SL		 1202 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1203 r = RREG32(R_0028FC_MC_DATA);
1204 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
0a5b7b0b 1205 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
65337e60
SL		 1206 return r;
1207}
1208
1209void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1210{
0a5b7b0b
AD		 1211 unsigned long flags;
1212
1213 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
65337e60
SL		 1214 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1215 S_0028F8_MC_IND_WR_EN(1));
1216 WREG32(R_0028FC_MC_DATA, v);
1217 WREG32(R_0028F8_MC_INDEX, 0x7F);
0a5b7b0b 1218 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
65337e60
SL		 1219}
1220
a3c1945a 1221static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1222{
a3c1945a 1223 struct rv515_mc_save save;
3ce0a23d
JG		 1224 u32 tmp;
1225 int i, j;
771fe6b9 1226
3ce0a23d
JG		 1227 /* Initialize HDP */
1228 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1229 WREG32((0x2c14 + j), 0x00000000);
1230 WREG32((0x2c18 + j), 0x00000000);
1231 WREG32((0x2c1c + j), 0x00000000);
1232 WREG32((0x2c20 + j), 0x00000000);
1233 WREG32((0x2c24 + j), 0x00000000);
1234 }
1235 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1236
a3c1945a 1237 rv515_mc_stop(rdev, &save);
3ce0a23d 1238 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1239 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1240 }
a3c1945a 1241 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1242 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1243 /* Update configuration */
1a029b76
JG		 1244 if (rdev->flags & RADEON_IS_AGP) {
1245 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1246 /* VRAM before AGP */
1247 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1248 rdev->mc.vram_start >> 12);
1249 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1250 rdev->mc.gtt_end >> 12);
1251 } else {
1252 /* VRAM after AGP */
1253 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1254 rdev->mc.gtt_start >> 12);
1255 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1256 rdev->mc.vram_end >> 12);
1257 }
1258 } else {
1259 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1260 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1261 }
16cdf04d 1262 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1a029b76 1263 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1264 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1265 WREG32(MC_VM_FB_LOCATION, tmp);
1266 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1267 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1268 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1269 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1270 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1271 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1272 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1273 } else {
1274 WREG32(MC_VM_AGP_BASE, 0);
1275 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1276 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1277 }
3ce0a23d 1278 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1279 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1280 }
a3c1945a 1281 rv515_mc_resume(rdev, &save);
698443d9
DA		 1282 /* we need to own VRAM, so turn off the VGA renderer here
1283 * to stop it overwriting our objects */
d39c3b89 1284 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1285}
1286
d594e46a
JG		 1287/**
1288 * r600_vram_gtt_location - try to find VRAM & GTT location
1289 * @rdev: radeon device structure holding all necessary informations
1290 * @mc: memory controller structure holding memory informations
1291 *
1292 * Function will place try to place VRAM at same place as in CPU (PCI)
1293 * address space as some GPU seems to have issue when we reprogram at
1294 * different address space.
1295 *
1296 * If there is not enough space to fit the unvisible VRAM after the
1297 * aperture then we limit the VRAM size to the aperture.
1298 *
1299 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1300 * them to be in one from GPU point of view so that we can program GPU to
1301 * catch access outside them (weird GPU policy see ??).
1302 *
1303 * This function will never fails, worst case are limiting VRAM or GTT.
1304 *
1305 * Note: GTT start, end, size should be initialized before calling this
1306 * function on AGP platform.
1307 */
0ef0c1f7 1308static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
d594e46a
JG		 1309{
1310 u64 size_bf, size_af;
1311
1312 if (mc->mc_vram_size > 0xE0000000) {
1313 /* leave room for at least 512M GTT */
1314 dev_warn(rdev->dev, "limiting VRAM\n");
1315 mc->real_vram_size = 0xE0000000;
1316 mc->mc_vram_size = 0xE0000000;
1317 }
1318 if (rdev->flags & RADEON_IS_AGP) {
1319 size_bf = mc->gtt_start;
9ed8b1f9 1320 size_af = mc->mc_mask - mc->gtt_end;
d594e46a
JG		 1321 if (size_bf > size_af) {
1322 if (mc->mc_vram_size > size_bf) {
1323 dev_warn(rdev->dev, "limiting VRAM\n");
1324 mc->real_vram_size = size_bf;
1325 mc->mc_vram_size = size_bf;
1326 }
1327 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1328 } else {
1329 if (mc->mc_vram_size > size_af) {
1330 dev_warn(rdev->dev, "limiting VRAM\n");
1331 mc->real_vram_size = size_af;
1332 mc->mc_vram_size = size_af;
1333 }
dfc6ae5b 1334 mc->vram_start = mc->gtt_end + 1;
d594e46a
JG		 1335 }
1336 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1337 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1338 mc->mc_vram_size >> 20, mc->vram_start,
1339 mc->vram_end, mc->real_vram_size >> 20);
1340 } else {
1341 u64 base = 0;
8961d52d
AD		 1342 if (rdev->flags & RADEON_IS_IGP) {
1343 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1344 base <<= 24;
1345 }
d594e46a 1346 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1347 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1348 radeon_gtt_location(rdev, mc);
1349 }
1350}
1351
1109ca09 1352static int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1353{
3ce0a23d 1354 u32 tmp;
5885b7a9 1355 int chansize, numchan;
65337e60
SL		 1356 uint32_t h_addr, l_addr;
1357 unsigned long long k8_addr;
771fe6b9 1358
3ce0a23d 1359 /* Get VRAM informations */
771fe6b9 1360 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1361 tmp = RREG32(RAMCFG);
1362 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1363 chansize = 16;
3ce0a23d 1364 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1365 chansize = 64;
1366 } else {
1367 chansize = 32;
1368 }
5885b7a9
AD		 1369 tmp = RREG32(CHMAP);
1370 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1371 case 0:
1372 default:
1373 numchan = 1;
1374 break;
1375 case 1:
1376 numchan = 2;
1377 break;
1378 case 2:
1379 numchan = 4;
1380 break;
1381 case 3:
1382 numchan = 8;
1383 break;
771fe6b9 1384 }
5885b7a9 1385 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1386 /* Could aper size report 0 ? */
01d73a69
JC		 1387 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1388 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1389 /* Setup GPU memory space */
1390 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1391 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1392 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1393 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1394
f892034a
AD		 1395 if (rdev->flags & RADEON_IS_IGP) {
1396 rs690_pm_info(rdev);
06b6476d 1397 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
65337e60
SL		 1398
1399 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1400 /* Use K8 direct mapping for fast fb access. */
1401 rdev->fastfb_working = false;
1402 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1403 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1404 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1405#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1406 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1407#endif
1408 {
1409 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1410 * memory is present.
1411 */
1412 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1413 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1414 (unsigned long long)rdev->mc.aper_base, k8_addr);
1415 rdev->mc.aper_base = (resource_size_t)k8_addr;
1416 rdev->fastfb_working = true;
1417 }
1418 }
1419 }
f892034a 1420 }
65337e60 1421
f47299c5 1422 radeon_update_bandwidth_info(rdev);
3ce0a23d 1423 return 0;
771fe6b9
JG		 1424}
1425
16cdf04d
AD		 1426int r600_vram_scratch_init(struct radeon_device *rdev)
1427{
1428 int r;
1429
1430 if (rdev->vram_scratch.robj == NULL) {
1431 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1432 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
831b6966 1433 0, NULL, NULL, &rdev->vram_scratch.robj);
16cdf04d
AD		 1434 if (r) {
1435 return r;
1436 }
1437 }
1438
1439 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1440 if (unlikely(r != 0))
1441 return r;
1442 r = radeon_bo_pin(rdev->vram_scratch.robj,
1443 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1444 if (r) {
1445 radeon_bo_unreserve(rdev->vram_scratch.robj);
1446 return r;
1447 }
1448 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1449 (void **)&rdev->vram_scratch.ptr);
1450 if (r)
1451 radeon_bo_unpin(rdev->vram_scratch.robj);
1452 radeon_bo_unreserve(rdev->vram_scratch.robj);
1453
1454 return r;
1455}
1456
1457void r600_vram_scratch_fini(struct radeon_device *rdev)
1458{
1459 int r;
1460
1461 if (rdev->vram_scratch.robj == NULL) {
1462 return;
1463 }
1464 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1465 if (likely(r == 0)) {
1466 radeon_bo_kunmap(rdev->vram_scratch.robj);
1467 radeon_bo_unpin(rdev->vram_scratch.robj);
1468 radeon_bo_unreserve(rdev->vram_scratch.robj);
1469 }
1470 radeon_bo_unref(&rdev->vram_scratch.robj);
1471}
1472
410a3418
AD		 1473void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1474{
1475 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1476
1477 if (hung)
1478 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1479 else
1480 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1481
1482 WREG32(R600_BIOS_3_SCRATCH, tmp);
1483}
1484
d3cb781e 1485static void r600_print_gpu_status_regs(struct radeon_device *rdev)
771fe6b9 1486{
64c56e8c 1487 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
d3cb781e 1488 RREG32(R_008010_GRBM_STATUS));
64c56e8c 1489 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
d3cb781e 1490 RREG32(R_008014_GRBM_STATUS2));
64c56e8c 1491 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
d3cb781e 1492 RREG32(R_000E50_SRBM_STATUS));
440a7cd8 1493 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
d3cb781e 1494 RREG32(CP_STALLED_STAT1));
440a7cd8 1495 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
d3cb781e 1496 RREG32(CP_STALLED_STAT2));
440a7cd8 1497 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
d3cb781e 1498 RREG32(CP_BUSY_STAT));
440a7cd8 1499 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
d3cb781e 1500 RREG32(CP_STAT));
71e3d157
AD		 1501 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1502 RREG32(DMA_STATUS_REG));
1503}
1504
f13f7731 1505static bool r600_is_display_hung(struct radeon_device *rdev)
71e3d157 1506{
f13f7731
AD		 1507 u32 crtc_hung = 0;
1508 u32 crtc_status[2];
1509 u32 i, j, tmp;
1510
1511 for (i = 0; i < rdev->num_crtc; i++) {
1512 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1513 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1514 crtc_hung |= (1 << i);
1515 }
1516 }
1517
1518 for (j = 0; j < 10; j++) {
1519 for (i = 0; i < rdev->num_crtc; i++) {
1520 if (crtc_hung & (1 << i)) {
1521 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1522 if (tmp != crtc_status[i])
1523 crtc_hung &= ~(1 << i);
1524 }
1525 }
1526 if (crtc_hung == 0)
1527 return false;
1528 udelay(100);
1529 }
1530
1531 return true;
1532}
1533
2483b4ea 1534u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
f13f7731
AD		 1535{
1536 u32 reset_mask = 0;
d3cb781e 1537 u32 tmp;
71e3d157 1538
f13f7731
AD		 1539 /* GRBM_STATUS */
1540 tmp = RREG32(R_008010_GRBM_STATUS);
1541 if (rdev->family >= CHIP_RV770) {
1542 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1543 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1544 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1545 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1546 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1547 reset_mask |= RADEON_RESET_GFX;
1548 } else {
1549 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1550 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1551 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1552 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1553 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1554 reset_mask |= RADEON_RESET_GFX;
1555 }
1556
1557 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1558 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1559 reset_mask |= RADEON_RESET_CP;
1560
1561 if (G_008010_GRBM_EE_BUSY(tmp))
1562 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1563
1564 /* DMA_STATUS_REG */
1565 tmp = RREG32(DMA_STATUS_REG);
1566 if (!(tmp & DMA_IDLE))
1567 reset_mask |= RADEON_RESET_DMA;
1568
1569 /* SRBM_STATUS */
1570 tmp = RREG32(R_000E50_SRBM_STATUS);
1571 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1572 reset_mask |= RADEON_RESET_RLC;
1573
1574 if (G_000E50_IH_BUSY(tmp))
1575 reset_mask |= RADEON_RESET_IH;
1576
1577 if (G_000E50_SEM_BUSY(tmp))
1578 reset_mask |= RADEON_RESET_SEM;
19fc42ed 1579
f13f7731
AD		 1580 if (G_000E50_GRBM_RQ_PENDING(tmp))
1581 reset_mask |= RADEON_RESET_GRBM;
1582
1583 if (G_000E50_VMC_BUSY(tmp))
1584 reset_mask |= RADEON_RESET_VMC;
1585
1586 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1587 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1588 G_000E50_MCDW_BUSY(tmp))
1589 reset_mask |= RADEON_RESET_MC;
1590
1591 if (r600_is_display_hung(rdev))
1592 reset_mask |= RADEON_RESET_DISPLAY;
1593
d808fc88
AD		 1594 /* Skip MC reset as it's mostly likely not hung, just busy */
1595 if (reset_mask & RADEON_RESET_MC) {
1596 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1597 reset_mask &= ~RADEON_RESET_MC;
1598 }
1599
f13f7731
AD		 1600 return reset_mask;
1601}
1602
1603static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1604{
1605 struct rv515_mc_save save;
1606 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1607 u32 tmp;
19fc42ed 1608
71e3d157 1609 if (reset_mask == 0)
f13f7731 1610 return;
71e3d157
AD		 1611
1612 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1613
d3cb781e
AD		 1614 r600_print_gpu_status_regs(rdev);
1615
d3cb781e
AD		 1616 /* Disable CP parsing/prefetching */
1617 if (rdev->family >= CHIP_RV770)
1618 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1619 else
1620 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1621
1622 /* disable the RLC */
1623 WREG32(RLC_CNTL, 0);
1624
1625 if (reset_mask & RADEON_RESET_DMA) {
1626 /* Disable DMA */
1627 tmp = RREG32(DMA_RB_CNTL);
1628 tmp &= ~DMA_RB_ENABLE;
1629 WREG32(DMA_RB_CNTL, tmp);
1630 }
1631
1632 mdelay(50);
1633
ca57802e
AD		 1634 rv515_mc_stop(rdev, &save);
1635 if (r600_mc_wait_for_idle(rdev)) {
1636 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1637 }
1638
d3cb781e
AD		 1639 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1640 if (rdev->family >= CHIP_RV770)
1641 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1642 S_008020_SOFT_RESET_CB(1) |
1643 S_008020_SOFT_RESET_PA(1) |
1644 S_008020_SOFT_RESET_SC(1) |
1645 S_008020_SOFT_RESET_SPI(1) |
1646 S_008020_SOFT_RESET_SX(1) |
1647 S_008020_SOFT_RESET_SH(1) |
1648 S_008020_SOFT_RESET_TC(1) |
1649 S_008020_SOFT_RESET_TA(1) |
1650 S_008020_SOFT_RESET_VC(1) |
1651 S_008020_SOFT_RESET_VGT(1);
1652 else
1653 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1654 S_008020_SOFT_RESET_DB(1) |
1655 S_008020_SOFT_RESET_CB(1) |
1656 S_008020_SOFT_RESET_PA(1) |
1657 S_008020_SOFT_RESET_SC(1) |
1658 S_008020_SOFT_RESET_SMX(1) |
1659 S_008020_SOFT_RESET_SPI(1) |
1660 S_008020_SOFT_RESET_SX(1) |
1661 S_008020_SOFT_RESET_SH(1) |
1662 S_008020_SOFT_RESET_TC(1) |
1663 S_008020_SOFT_RESET_TA(1) |
1664 S_008020_SOFT_RESET_VC(1) |
1665 S_008020_SOFT_RESET_VGT(1);
1666 }
1667
1668 if (reset_mask & RADEON_RESET_CP) {
1669 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1670 S_008020_SOFT_RESET_VGT(1);
1671
1672 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1673 }
1674
1675 if (reset_mask & RADEON_RESET_DMA) {
1676 if (rdev->family >= CHIP_RV770)
1677 srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1678 else
1679 srbm_soft_reset |= SOFT_RESET_DMA;
1680 }
1681
f13f7731
AD		 1682 if (reset_mask & RADEON_RESET_RLC)
1683 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1684
1685 if (reset_mask & RADEON_RESET_SEM)
1686 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1687
1688 if (reset_mask & RADEON_RESET_IH)
1689 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1690
1691 if (reset_mask & RADEON_RESET_GRBM)
1692 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1693
24178ec4
AD		 1694 if (!(rdev->flags & RADEON_IS_IGP)) {
1695 if (reset_mask & RADEON_RESET_MC)
1696 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1697 }
f13f7731
AD		 1698
1699 if (reset_mask & RADEON_RESET_VMC)
1700 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1701
d3cb781e
AD		 1702 if (grbm_soft_reset) {
1703 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1704 tmp |= grbm_soft_reset;
1705 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1706 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1707 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1708
1709 udelay(50);
1710
1711 tmp &= ~grbm_soft_reset;
1712 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1713 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1714 }
1715
1716 if (srbm_soft_reset) {
1717 tmp = RREG32(SRBM_SOFT_RESET);
1718 tmp |= srbm_soft_reset;
1719 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1720 WREG32(SRBM_SOFT_RESET, tmp);
1721 tmp = RREG32(SRBM_SOFT_RESET);
1722
1723 udelay(50);
71e3d157 1724
d3cb781e
AD		 1725 tmp &= ~srbm_soft_reset;
1726 WREG32(SRBM_SOFT_RESET, tmp);
1727 tmp = RREG32(SRBM_SOFT_RESET);
1728 }
71e3d157
AD		 1729
1730 /* Wait a little for things to settle down */
1731 mdelay(1);
1732
a3c1945a 1733 rv515_mc_resume(rdev, &save);
d3cb781e 1734 udelay(50);
410a3418 1735
d3cb781e 1736 r600_print_gpu_status_regs(rdev);
d3cb781e
AD		 1737}
1738
de9ae744
AD		 1739static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1740{
1741 struct rv515_mc_save save;
1742 u32 tmp, i;
1743
1744 dev_info(rdev->dev, "GPU pci config reset\n");
1745
1746 /* disable dpm? */
1747
1748 /* Disable CP parsing/prefetching */
1749 if (rdev->family >= CHIP_RV770)
1750 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1751 else
1752 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1753
1754 /* disable the RLC */
1755 WREG32(RLC_CNTL, 0);
1756
1757 /* Disable DMA */
1758 tmp = RREG32(DMA_RB_CNTL);
1759 tmp &= ~DMA_RB_ENABLE;
1760 WREG32(DMA_RB_CNTL, tmp);
1761
1762 mdelay(50);
1763
1764 /* set mclk/sclk to bypass */
1765 if (rdev->family >= CHIP_RV770)
1766 rv770_set_clk_bypass_mode(rdev);
1767 /* disable BM */
1768 pci_clear_master(rdev->pdev);
1769 /* disable mem access */
1770 rv515_mc_stop(rdev, &save);
1771 if (r600_mc_wait_for_idle(rdev)) {
1772 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1773 }
1774
1775 /* BIF reset workaround. Not sure if this is needed on 6xx */
1776 tmp = RREG32(BUS_CNTL);
1777 tmp |= VGA_COHE_SPEC_TIMER_DIS;
1778 WREG32(BUS_CNTL, tmp);
1779
1780 tmp = RREG32(BIF_SCRATCH0);
1781
1782 /* reset */
1783 radeon_pci_config_reset(rdev);
1784 mdelay(1);
1785
1786 /* BIF reset workaround. Not sure if this is needed on 6xx */
1787 tmp = SOFT_RESET_BIF;
1788 WREG32(SRBM_SOFT_RESET, tmp);
1789 mdelay(1);
1790 WREG32(SRBM_SOFT_RESET, 0);
1791
1792 /* wait for asic to come out of reset */
1793 for (i = 0; i < rdev->usec_timeout; i++) {
1794 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1795 break;
1796 udelay(1);
1797 }
1798}
1799
d3cb781e
AD		 1800int r600_asic_reset(struct radeon_device *rdev)
1801{
f13f7731
AD		 1802 u32 reset_mask;
1803
1804 reset_mask = r600_gpu_check_soft_reset(rdev);
1805
1806 if (reset_mask)
1807 r600_set_bios_scratch_engine_hung(rdev, true);
1808
de9ae744 1809 /* try soft reset */
f13f7731
AD		 1810 r600_gpu_soft_reset(rdev, reset_mask);
1811
1812 reset_mask = r600_gpu_check_soft_reset(rdev);
1813
de9ae744
AD		 1814 /* try pci config reset */
1815 if (reset_mask && radeon_hard_reset)
1816 r600_gpu_pci_config_reset(rdev);
1817
1818 reset_mask = r600_gpu_check_soft_reset(rdev);
1819
f13f7731
AD		 1820 if (!reset_mask)
1821 r600_set_bios_scratch_engine_hung(rdev, false);
1822
1823 return 0;
3ce0a23d
JG		 1824}
1825
123bc183
AD		 1826/**
1827 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1828 *
1829 * @rdev: radeon_device pointer
1830 * @ring: radeon_ring structure holding ring information
1831 *
1832 * Check if the GFX engine is locked up.
1833 * Returns true if the engine appears to be locked up, false if not.
1834 */
1835bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8 1836{
123bc183
AD		 1837 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1838
1839 if (!(reset_mask & (RADEON_RESET_GFX |
1840 RADEON_RESET_COMPUTE |
1841 RADEON_RESET_CP))) {
ff212f25 1842 radeon_ring_lockup_update(rdev, ring);
225758d8
JG		 1843 return false;
1844 }
069211e5 1845 return radeon_ring_test_lockup(rdev, ring);
225758d8
JG		 1846}
1847
416a2bd2
AD		 1848u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1849 u32 tiling_pipe_num,
1850 u32 max_rb_num,
1851 u32 total_max_rb_num,
1852 u32 disabled_rb_mask)
3ce0a23d 1853{
416a2bd2 1854 u32 rendering_pipe_num, rb_num_width, req_rb_num;
f689e3ac 1855 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
416a2bd2
AD		 1856 u32 data = 0, mask = 1 << (max_rb_num - 1);
1857 unsigned i, j;
3ce0a23d 1858
416a2bd2 1859 /* mask out the RBs that don't exist on that asic */
f689e3ac
MT		 1860 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1861 /* make sure at least one RB is available */
1862 if ((tmp & 0xff) != 0xff)
1863 disabled_rb_mask = tmp;
3ce0a23d 1864
416a2bd2
AD		 1865 rendering_pipe_num = 1 << tiling_pipe_num;
1866 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1867 BUG_ON(rendering_pipe_num < req_rb_num);
3ce0a23d 1868
416a2bd2
AD		 1869 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1870 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
3ce0a23d 1871
416a2bd2
AD		 1872 if (rdev->family <= CHIP_RV740) {
1873 /* r6xx/r7xx */
1874 rb_num_width = 2;
1875 } else {
1876 /* eg+ */
1877 rb_num_width = 4;
1878 }
3ce0a23d 1879
416a2bd2
AD		 1880 for (i = 0; i < max_rb_num; i++) {
1881 if (!(mask & disabled_rb_mask)) {
1882 for (j = 0; j < pipe_rb_ratio; j++) {
1883 data <<= rb_num_width;
1884 data |= max_rb_num - i - 1;
1885 }
1886 if (pipe_rb_remain) {
1887 data <<= rb_num_width;
1888 data |= max_rb_num - i - 1;
1889 pipe_rb_remain--;
1890 }
1891 }
1892 mask >>= 1;
3ce0a23d
JG		 1893 }
1894
416a2bd2 1895 return data;
3ce0a23d
JG		 1896}
1897
1898int r600_count_pipe_bits(uint32_t val)
1899{
ef8cf3a1 1900 return hweight32(val);
771fe6b9
JG		 1901}
1902
1109ca09 1903static void r600_gpu_init(struct radeon_device *rdev)
3ce0a23d
JG		 1904{
1905 u32 tiling_config;
1906 u32 ramcfg;
d03f5d59 1907 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1908 u32 tmp;
1909 int i, j;
1910 u32 sq_config;
1911 u32 sq_gpr_resource_mgmt_1 = 0;
1912 u32 sq_gpr_resource_mgmt_2 = 0;
1913 u32 sq_thread_resource_mgmt = 0;
1914 u32 sq_stack_resource_mgmt_1 = 0;
1915 u32 sq_stack_resource_mgmt_2 = 0;
416a2bd2 1916 u32 disabled_rb_mask;
3ce0a23d 1917
416a2bd2 1918 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1919 switch (rdev->family) {
1920 case CHIP_R600:
1921 rdev->config.r600.max_pipes = 4;
1922 rdev->config.r600.max_tile_pipes = 8;
1923 rdev->config.r600.max_simds = 4;
1924 rdev->config.r600.max_backends = 4;
1925 rdev->config.r600.max_gprs = 256;
1926 rdev->config.r600.max_threads = 192;
1927 rdev->config.r600.max_stack_entries = 256;
1928 rdev->config.r600.max_hw_contexts = 8;
1929 rdev->config.r600.max_gs_threads = 16;
1930 rdev->config.r600.sx_max_export_size = 128;
1931 rdev->config.r600.sx_max_export_pos_size = 16;
1932 rdev->config.r600.sx_max_export_smx_size = 128;
1933 rdev->config.r600.sq_num_cf_insts = 2;
1934 break;
1935 case CHIP_RV630:
1936 case CHIP_RV635:
1937 rdev->config.r600.max_pipes = 2;
1938 rdev->config.r600.max_tile_pipes = 2;
1939 rdev->config.r600.max_simds = 3;
1940 rdev->config.r600.max_backends = 1;
1941 rdev->config.r600.max_gprs = 128;
1942 rdev->config.r600.max_threads = 192;
1943 rdev->config.r600.max_stack_entries = 128;
1944 rdev->config.r600.max_hw_contexts = 8;
1945 rdev->config.r600.max_gs_threads = 4;
1946 rdev->config.r600.sx_max_export_size = 128;
1947 rdev->config.r600.sx_max_export_pos_size = 16;
1948 rdev->config.r600.sx_max_export_smx_size = 128;
1949 rdev->config.r600.sq_num_cf_insts = 2;
1950 break;
1951 case CHIP_RV610:
1952 case CHIP_RV620:
1953 case CHIP_RS780:
1954 case CHIP_RS880:
1955 rdev->config.r600.max_pipes = 1;
1956 rdev->config.r600.max_tile_pipes = 1;
1957 rdev->config.r600.max_simds = 2;
1958 rdev->config.r600.max_backends = 1;
1959 rdev->config.r600.max_gprs = 128;
1960 rdev->config.r600.max_threads = 192;
1961 rdev->config.r600.max_stack_entries = 128;
1962 rdev->config.r600.max_hw_contexts = 4;
1963 rdev->config.r600.max_gs_threads = 4;
1964 rdev->config.r600.sx_max_export_size = 128;
1965 rdev->config.r600.sx_max_export_pos_size = 16;
1966 rdev->config.r600.sx_max_export_smx_size = 128;
1967 rdev->config.r600.sq_num_cf_insts = 1;
1968 break;
1969 case CHIP_RV670:
1970 rdev->config.r600.max_pipes = 4;
1971 rdev->config.r600.max_tile_pipes = 4;
1972 rdev->config.r600.max_simds = 4;
1973 rdev->config.r600.max_backends = 4;
1974 rdev->config.r600.max_gprs = 192;
1975 rdev->config.r600.max_threads = 192;
1976 rdev->config.r600.max_stack_entries = 256;
1977 rdev->config.r600.max_hw_contexts = 8;
1978 rdev->config.r600.max_gs_threads = 16;
1979 rdev->config.r600.sx_max_export_size = 128;
1980 rdev->config.r600.sx_max_export_pos_size = 16;
1981 rdev->config.r600.sx_max_export_smx_size = 128;
1982 rdev->config.r600.sq_num_cf_insts = 2;
1983 break;
1984 default:
1985 break;
1986 }
1987
1988 /* Initialize HDP */
1989 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1990 WREG32((0x2c14 + j), 0x00000000);
1991 WREG32((0x2c18 + j), 0x00000000);
1992 WREG32((0x2c1c + j), 0x00000000);
1993 WREG32((0x2c20 + j), 0x00000000);
1994 WREG32((0x2c24 + j), 0x00000000);
1995 }
1996
1997 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1998
1999 /* Setup tiling */
2000 tiling_config = 0;
2001 ramcfg = RREG32(RAMCFG);
2002 switch (rdev->config.r600.max_tile_pipes) {
2003 case 1:
2004 tiling_config |= PIPE_TILING(0);
2005 break;
2006 case 2:
2007 tiling_config |= PIPE_TILING(1);
2008 break;
2009 case 4:
2010 tiling_config |= PIPE_TILING(2);
2011 break;
2012 case 8:
2013 tiling_config |= PIPE_TILING(3);
2014 break;
2015 default:
2016 break;
2017 }
d03f5d59 2018 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 2019 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 2020 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1 2021 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
416a2bd2 2022
3ce0a23d
JG		 2023 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
2024 if (tmp > 3) {
2025 tiling_config |= ROW_TILING(3);
2026 tiling_config |= SAMPLE_SPLIT(3);
2027 } else {
2028 tiling_config |= ROW_TILING(tmp);
2029 tiling_config |= SAMPLE_SPLIT(tmp);
2030 }
2031 tiling_config |= BANK_SWAPS(1);
d03f5d59 2032
416a2bd2 2033 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
65fcf668
AD		 2034 tmp = rdev->config.r600.max_simds -
2035 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
2036 rdev->config.r600.active_simds = tmp;
416a2bd2
AD		 2037
2038 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
0a5f6e9d
AD		 2039 tmp = 0;
2040 for (i = 0; i < rdev->config.r600.max_backends; i++)
2041 tmp |= (1 << i);
2042 /* if all the backends are disabled, fix it up here */
2043 if ((disabled_rb_mask & tmp) == tmp) {
2044 for (i = 0; i < rdev->config.r600.max_backends; i++)
2045 disabled_rb_mask &= ~(1 << i);
2046 }
416a2bd2
AD		 2047 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
2048 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
2049 R6XX_MAX_BACKENDS, disabled_rb_mask);
2050 tiling_config |= tmp << 16;
2051 rdev->config.r600.backend_map = tmp;
2052
e7aeeba6 2053 rdev->config.r600.tile_config = tiling_config;
3ce0a23d
JG		 2054 WREG32(GB_TILING_CONFIG, tiling_config);
2055 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
2056 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
4d75658b 2057 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
3ce0a23d 2058
d03f5d59 2059 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 2060 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
2061 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
2062
2063 /* Setup some CP states */
2064 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
2065 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
2066
2067 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
2068 SYNC_WALKER | SYNC_ALIGNER));
2069 /* Setup various GPU states */
2070 if (rdev->family == CHIP_RV670)
2071 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
2072
2073 tmp = RREG32(SX_DEBUG_1);
2074 tmp |= SMX_EVENT_RELEASE;
2075 if ((rdev->family > CHIP_R600))
2076 tmp |= ENABLE_NEW_SMX_ADDRESS;
2077 WREG32(SX_DEBUG_1, tmp);
2078
2079 if (((rdev->family) == CHIP_R600) ||
2080 ((rdev->family) == CHIP_RV630) ||
2081 ((rdev->family) == CHIP_RV610) ||
2082 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2083 ((rdev->family) == CHIP_RS780) ||
2084 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2085 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2086 } else {
2087 WREG32(DB_DEBUG, 0);
2088 }
2089 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2090 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
2091
2092 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2093 WREG32(VGT_NUM_INSTANCES, 0);
2094
2095 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2096 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2097
2098 tmp = RREG32(SQ_MS_FIFO_SIZES);
2099 if (((rdev->family) == CHIP_RV610) ||
2100 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2101 ((rdev->family) == CHIP_RS780) ||
2102 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2103 tmp = (CACHE_FIFO_SIZE(0xa) |
2104 FETCH_FIFO_HIWATER(0xa) |
2105 DONE_FIFO_HIWATER(0xe0) |
2106 ALU_UPDATE_FIFO_HIWATER(0x8));
2107 } else if (((rdev->family) == CHIP_R600) ||
2108 ((rdev->family) == CHIP_RV630)) {
2109 tmp &= ~DONE_FIFO_HIWATER(0xff);
2110 tmp |= DONE_FIFO_HIWATER(0x4);
2111 }
2112 WREG32(SQ_MS_FIFO_SIZES, tmp);
2113
2114 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2115 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
2116 */
2117 sq_config = RREG32(SQ_CONFIG);
2118 sq_config &= ~(PS_PRIO(3) |
2119 VS_PRIO(3) |
2120 GS_PRIO(3) |
2121 ES_PRIO(3));
2122 sq_config |= (DX9_CONSTS |
2123 VC_ENABLE |
2124 PS_PRIO(0) |
2125 VS_PRIO(1) |
2126 GS_PRIO(2) |
2127 ES_PRIO(3));
2128
2129 if ((rdev->family) == CHIP_R600) {
2130 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
2131 NUM_VS_GPRS(124) |
2132 NUM_CLAUSE_TEMP_GPRS(4));
2133 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
2134 NUM_ES_GPRS(0));
2135 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
2136 NUM_VS_THREADS(48) |
2137 NUM_GS_THREADS(4) |
2138 NUM_ES_THREADS(4));
2139 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
2140 NUM_VS_STACK_ENTRIES(128));
2141 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
2142 NUM_ES_STACK_ENTRIES(0));
2143 } else if (((rdev->family) == CHIP_RV610) ||
2144 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2145 ((rdev->family) == CHIP_RS780) ||
2146 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2147 /* no vertex cache */
2148 sq_config &= ~VC_ENABLE;
2149
2150 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2151 NUM_VS_GPRS(44) |
2152 NUM_CLAUSE_TEMP_GPRS(2));
2153 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2154 NUM_ES_GPRS(17));
2155 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2156 NUM_VS_THREADS(78) |
2157 NUM_GS_THREADS(4) |
2158 NUM_ES_THREADS(31));
2159 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2160 NUM_VS_STACK_ENTRIES(40));
2161 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2162 NUM_ES_STACK_ENTRIES(16));
2163 } else if (((rdev->family) == CHIP_RV630) ||
2164 ((rdev->family) == CHIP_RV635)) {
2165 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2166 NUM_VS_GPRS(44) |
2167 NUM_CLAUSE_TEMP_GPRS(2));
2168 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2169 NUM_ES_GPRS(18));
2170 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2171 NUM_VS_THREADS(78) |
2172 NUM_GS_THREADS(4) |
2173 NUM_ES_THREADS(31));
2174 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2175 NUM_VS_STACK_ENTRIES(40));
2176 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2177 NUM_ES_STACK_ENTRIES(16));
2178 } else if ((rdev->family) == CHIP_RV670) {
2179 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2180 NUM_VS_GPRS(44) |
2181 NUM_CLAUSE_TEMP_GPRS(2));
2182 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2183 NUM_ES_GPRS(17));
2184 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2185 NUM_VS_THREADS(78) |
2186 NUM_GS_THREADS(4) |
2187 NUM_ES_THREADS(31));
2188 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2189 NUM_VS_STACK_ENTRIES(64));
2190 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2191 NUM_ES_STACK_ENTRIES(64));
2192 }
2193
2194 WREG32(SQ_CONFIG, sq_config);
2195 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2196 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2197 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2198 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2199 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2200
2201 if (((rdev->family) == CHIP_RV610) ||
2202 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 2203 ((rdev->family) == CHIP_RS780) ||
2204 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2205 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2206 } else {
2207 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2208 }
2209
2210 /* More default values. 2D/3D driver should adjust as needed */
2211 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2212 S1_X(0x4) | S1_Y(0xc)));
2213 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2214 S1_X(0x2) | S1_Y(0x2) |
2215 S2_X(0xa) | S2_Y(0x6) |
2216 S3_X(0x6) | S3_Y(0xa)));
2217 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2218 S1_X(0x4) | S1_Y(0xc) |
2219 S2_X(0x1) | S2_Y(0x6) |
2220 S3_X(0xa) | S3_Y(0xe)));
2221 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2222 S5_X(0x0) | S5_Y(0x0) |
2223 S6_X(0xb) | S6_Y(0x4) |
2224 S7_X(0x7) | S7_Y(0x8)));
2225
2226 WREG32(VGT_STRMOUT_EN, 0);
2227 tmp = rdev->config.r600.max_pipes * 16;
2228 switch (rdev->family) {
2229 case CHIP_RV610:
3ce0a23d 2230 case CHIP_RV620:
ee59f2b4
AD		 2231 case CHIP_RS780:
2232 case CHIP_RS880:
3ce0a23d
JG		 2233 tmp += 32;
2234 break;
2235 case CHIP_RV670:
2236 tmp += 128;
2237 break;
2238 default:
2239 break;
2240 }
2241 if (tmp > 256) {
2242 tmp = 256;
2243 }
2244 WREG32(VGT_ES_PER_GS, 128);
2245 WREG32(VGT_GS_PER_ES, tmp);
2246 WREG32(VGT_GS_PER_VS, 2);
2247 WREG32(VGT_GS_VERTEX_REUSE, 16);
2248
2249 /* more default values. 2D/3D driver should adjust as needed */
2250 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2251 WREG32(VGT_STRMOUT_EN, 0);
2252 WREG32(SX_MISC, 0);
2253 WREG32(PA_SC_MODE_CNTL, 0);
2254 WREG32(PA_SC_AA_CONFIG, 0);
2255 WREG32(PA_SC_LINE_STIPPLE, 0);
2256 WREG32(SPI_INPUT_Z, 0);
2257 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2258 WREG32(CB_COLOR7_FRAG, 0);
2259
2260 /* Clear render buffer base addresses */
2261 WREG32(CB_COLOR0_BASE, 0);
2262 WREG32(CB_COLOR1_BASE, 0);
2263 WREG32(CB_COLOR2_BASE, 0);
2264 WREG32(CB_COLOR3_BASE, 0);
2265 WREG32(CB_COLOR4_BASE, 0);
2266 WREG32(CB_COLOR5_BASE, 0);
2267 WREG32(CB_COLOR6_BASE, 0);
2268 WREG32(CB_COLOR7_BASE, 0);
2269 WREG32(CB_COLOR7_FRAG, 0);
2270
2271 switch (rdev->family) {
2272 case CHIP_RV610:
3ce0a23d 2273 case CHIP_RV620:
ee59f2b4
AD		 2274 case CHIP_RS780:
2275 case CHIP_RS880:
3ce0a23d
JG		 2276 tmp = TC_L2_SIZE(8);
2277 break;
2278 case CHIP_RV630:
2279 case CHIP_RV635:
2280 tmp = TC_L2_SIZE(4);
2281 break;
2282 case CHIP_R600:
2283 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2284 break;
2285 default:
2286 tmp = TC_L2_SIZE(0);
2287 break;
2288 }
2289 WREG32(TC_CNTL, tmp);
2290
2291 tmp = RREG32(HDP_HOST_PATH_CNTL);
2292 WREG32(HDP_HOST_PATH_CNTL, tmp);
2293
2294 tmp = RREG32(ARB_POP);
2295 tmp |= ENABLE_TC128;
2296 WREG32(ARB_POP, tmp);
2297
2298 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2299 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2300 NUM_CLIP_SEQ(3)));
2301 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
b866d133 2302 WREG32(VC_ENHANCE, 0);
3ce0a23d
JG		 2303}
2304
2305
771fe6b9
JG		 2306/*
2307 * Indirect registers accessor
2308 */
3ce0a23d
JG		 2309u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2310{
0a5b7b0b 2311 unsigned long flags;
3ce0a23d
JG		 2312 u32 r;
2313
0a5b7b0b 2314 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2315 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2316 (void)RREG32(PCIE_PORT_INDEX);
2317 r = RREG32(PCIE_PORT_DATA);
0a5b7b0b 2318 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2319 return r;
2320}
2321
2322void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2323{
0a5b7b0b
AD		 2324 unsigned long flags;
2325
2326 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2327 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2328 (void)RREG32(PCIE_PORT_INDEX);
2329 WREG32(PCIE_PORT_DATA, (v));
2330 (void)RREG32(PCIE_PORT_DATA);
0a5b7b0b 2331 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2332}
2333
3ce0a23d
JG		 2334/*
2335 * CP & Ring
2336 */
2337void r600_cp_stop(struct radeon_device *rdev)
2338{
50efa51a
AD		 2339 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2340 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3ce0a23d 2341 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 2342 WREG32(SCRATCH_UMSK, 0);
4d75658b 2343 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3ce0a23d
JG		 2344}
2345
d8f60cfc 2346int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d 2347{
3ce0a23d 2348 const char *chip_name;
d8f60cfc 2349 const char *rlc_chip_name;
66229b20
AD		 2350 const char *smc_chip_name = "RV770";
2351 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
3ce0a23d
JG		 2352 char fw_name[30];
2353 int err;
2354
2355 DRM_DEBUG("\n");
2356
3ce0a23d 2357 switch (rdev->family) {
d8f60cfc
AD		 2358 case CHIP_R600:
2359 chip_name = "R600";
2360 rlc_chip_name = "R600";
2361 break;
2362 case CHIP_RV610:
2363 chip_name = "RV610";
2364 rlc_chip_name = "R600";
2365 break;
2366 case CHIP_RV630:
2367 chip_name = "RV630";
2368 rlc_chip_name = "R600";
2369 break;
2370 case CHIP_RV620:
2371 chip_name = "RV620";
2372 rlc_chip_name = "R600";
2373 break;
2374 case CHIP_RV635:
2375 chip_name = "RV635";
2376 rlc_chip_name = "R600";
2377 break;
2378 case CHIP_RV670:
2379 chip_name = "RV670";
2380 rlc_chip_name = "R600";
2381 break;
3ce0a23d 2382 case CHIP_RS780:
d8f60cfc
AD		 2383 case CHIP_RS880:
2384 chip_name = "RS780";
2385 rlc_chip_name = "R600";
2386 break;
2387 case CHIP_RV770:
2388 chip_name = "RV770";
2389 rlc_chip_name = "R700";
66229b20
AD		 2390 smc_chip_name = "RV770";
2391 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
d8f60cfc 2392 break;
3ce0a23d 2393 case CHIP_RV730:
d8f60cfc
AD		 2394 chip_name = "RV730";
2395 rlc_chip_name = "R700";
66229b20
AD		 2396 smc_chip_name = "RV730";
2397 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
d8f60cfc
AD		 2398 break;
2399 case CHIP_RV710:
2400 chip_name = "RV710";
2401 rlc_chip_name = "R700";
66229b20
AD		 2402 smc_chip_name = "RV710";
2403 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2404 break;
2405 case CHIP_RV740:
2406 chip_name = "RV730";
2407 rlc_chip_name = "R700";
2408 smc_chip_name = "RV740";
2409 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
d8f60cfc 2410 break;
fe251e2f
AD		 2411 case CHIP_CEDAR:
2412 chip_name = "CEDAR";
45f9a39b 2413 rlc_chip_name = "CEDAR";
dc50ba7f
AD		 2414 smc_chip_name = "CEDAR";
2415 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2416 break;
2417 case CHIP_REDWOOD:
2418 chip_name = "REDWOOD";
45f9a39b 2419 rlc_chip_name = "REDWOOD";
dc50ba7f
AD		 2420 smc_chip_name = "REDWOOD";
2421 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2422 break;
2423 case CHIP_JUNIPER:
2424 chip_name = "JUNIPER";
45f9a39b 2425 rlc_chip_name = "JUNIPER";
dc50ba7f
AD		 2426 smc_chip_name = "JUNIPER";
2427 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2428 break;
2429 case CHIP_CYPRESS:
2430 case CHIP_HEMLOCK:
2431 chip_name = "CYPRESS";
45f9a39b 2432 rlc_chip_name = "CYPRESS";
dc50ba7f
AD		 2433 smc_chip_name = "CYPRESS";
2434 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
fe251e2f 2435 break;
439bd6cd
AD		 2436 case CHIP_PALM:
2437 chip_name = "PALM";
2438 rlc_chip_name = "SUMO";
2439 break;
d5c5a72f
AD		 2440 case CHIP_SUMO:
2441 chip_name = "SUMO";
2442 rlc_chip_name = "SUMO";
2443 break;
2444 case CHIP_SUMO2:
2445 chip_name = "SUMO2";
2446 rlc_chip_name = "SUMO";
2447 break;
3ce0a23d
JG		 2448 default: BUG();
2449 }
2450
fe251e2f
AD		 2451 if (rdev->family >= CHIP_CEDAR) {
2452 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2453 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2454 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2455 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2456 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2457 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2458 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d 2459 } else {
138e4e16
AD		 2460 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2461 me_req_size = R600_PM4_UCODE_SIZE * 12;
2462 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2463 }
2464
d8f60cfc 2465 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2466
2467 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
0a168933 2468 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
3ce0a23d
JG		 2469 if (err)
2470 goto out;
2471 if (rdev->pfp_fw->size != pfp_req_size) {
2472 printk(KERN_ERR
2473 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2474 rdev->pfp_fw->size, fw_name);
2475 err = -EINVAL;
2476 goto out;
2477 }
2478
2479 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
0a168933 2480 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
3ce0a23d
JG		 2481 if (err)
2482 goto out;
2483 if (rdev->me_fw->size != me_req_size) {
2484 printk(KERN_ERR
2485 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2486 rdev->me_fw->size, fw_name);
2487 err = -EINVAL;
2488 }
d8f60cfc
AD		 2489
2490 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
0a168933 2491 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
d8f60cfc
AD		 2492 if (err)
2493 goto out;
2494 if (rdev->rlc_fw->size != rlc_req_size) {
2495 printk(KERN_ERR
2496 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2497 rdev->rlc_fw->size, fw_name);
2498 err = -EINVAL;
2499 }
2500
dc50ba7f 2501 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
66229b20 2502 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name);
0a168933 2503 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
8a53fa23
AD		 2504 if (err) {
2505 printk(KERN_ERR
2506 "smc: error loading firmware \"%s\"\n",
2507 fw_name);
2508 release_firmware(rdev->smc_fw);
2509 rdev->smc_fw = NULL;
d8367112 2510 err = 0;
8a53fa23 2511 } else if (rdev->smc_fw->size != smc_req_size) {
66229b20
AD		 2512 printk(KERN_ERR
2513 "smc: Bogus length %zu in firmware \"%s\"\n",
2514 rdev->smc_fw->size, fw_name);
2515 err = -EINVAL;
2516 }
2517 }
2518
3ce0a23d 2519out:
3ce0a23d
JG		 2520 if (err) {
2521 if (err != -EINVAL)
2522 printk(KERN_ERR
2523 "r600_cp: Failed to load firmware \"%s\"\n",
2524 fw_name);
2525 release_firmware(rdev->pfp_fw);
2526 rdev->pfp_fw = NULL;
2527 release_firmware(rdev->me_fw);
2528 rdev->me_fw = NULL;
d8f60cfc
AD		 2529 release_firmware(rdev->rlc_fw);
2530 rdev->rlc_fw = NULL;
66229b20
AD		 2531 release_firmware(rdev->smc_fw);
2532 rdev->smc_fw = NULL;
3ce0a23d
JG		 2533 }
2534 return err;
2535}
2536
ea31bf69
AD		 2537u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2538 struct radeon_ring *ring)
2539{
2540 u32 rptr;
2541
2542 if (rdev->wb.enabled)
2543 rptr = rdev->wb.wb[ring->rptr_offs/4];
2544 else
2545 rptr = RREG32(R600_CP_RB_RPTR);
2546
2547 return rptr;
2548}
2549
2550u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2551 struct radeon_ring *ring)
2552{
2553 u32 wptr;
2554
2555 wptr = RREG32(R600_CP_RB_WPTR);
2556
2557 return wptr;
2558}
2559
2560void r600_gfx_set_wptr(struct radeon_device *rdev,
2561 struct radeon_ring *ring)
2562{
2563 WREG32(R600_CP_RB_WPTR, ring->wptr);
2564 (void)RREG32(R600_CP_RB_WPTR);
2565}
2566
3ce0a23d
JG		 2567static int r600_cp_load_microcode(struct radeon_device *rdev)
2568{
2569 const __be32 *fw_data;
2570 int i;
2571
2572 if (!rdev->me_fw || !rdev->pfp_fw)
2573 return -EINVAL;
2574
2575 r600_cp_stop(rdev);
2576
4eace7fd
CC		 2577 WREG32(CP_RB_CNTL,
2578#ifdef __BIG_ENDIAN
2579 BUF_SWAP_32BIT |
2580#endif
2581 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3ce0a23d
JG		 2582
2583 /* Reset cp */
2584 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2585 RREG32(GRBM_SOFT_RESET);
2586 mdelay(15);
2587 WREG32(GRBM_SOFT_RESET, 0);
2588
2589 WREG32(CP_ME_RAM_WADDR, 0);
2590
2591 fw_data = (const __be32 *)rdev->me_fw->data;
2592 WREG32(CP_ME_RAM_WADDR, 0);
138e4e16 2593 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
3ce0a23d
JG		 2594 WREG32(CP_ME_RAM_DATA,
2595 be32_to_cpup(fw_data++));
2596
2597 fw_data = (const __be32 *)rdev->pfp_fw->data;
2598 WREG32(CP_PFP_UCODE_ADDR, 0);
138e4e16 2599 for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
3ce0a23d
JG		 2600 WREG32(CP_PFP_UCODE_DATA,
2601 be32_to_cpup(fw_data++));
2602
2603 WREG32(CP_PFP_UCODE_ADDR, 0);
2604 WREG32(CP_ME_RAM_WADDR, 0);
2605 WREG32(CP_ME_RAM_RADDR, 0);
2606 return 0;
2607}
2608
2609int r600_cp_start(struct radeon_device *rdev)
2610{
e32eb50d 2611 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2612 int r;
2613 uint32_t cp_me;
2614
e32eb50d 2615 r = radeon_ring_lock(rdev, ring, 7);
3ce0a23d
JG		 2616 if (r) {
2617 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2618 return r;
2619 }
e32eb50d
CK		 2620 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2621 radeon_ring_write(ring, 0x1);
7e7b41d2 2622 if (rdev->family >= CHIP_RV770) {
e32eb50d
CK		 2623 radeon_ring_write(ring, 0x0);
2624 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f 2625 } else {
e32eb50d
CK		 2626 radeon_ring_write(ring, 0x3);
2627 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d 2628 }
e32eb50d
CK		 2629 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2630 radeon_ring_write(ring, 0);
2631 radeon_ring_write(ring, 0);
1538a9e0 2632 radeon_ring_unlock_commit(rdev, ring, false);
3ce0a23d
JG		 2633
2634 cp_me = 0xff;
2635 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2636 return 0;
2637}
2638
2639int r600_cp_resume(struct radeon_device *rdev)
2640{
e32eb50d 2641 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2642 u32 tmp;
2643 u32 rb_bufsz;
2644 int r;
2645
2646 /* Reset cp */
2647 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2648 RREG32(GRBM_SOFT_RESET);
2649 mdelay(15);
2650 WREG32(GRBM_SOFT_RESET, 0);
2651
2652 /* Set ring buffer size */
b72a8925
DV		 2653 rb_bufsz = order_base_2(ring->ring_size / 8);
2654 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2655#ifdef __BIG_ENDIAN
d6f28938 2656 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2657#endif
d6f28938 2658 WREG32(CP_RB_CNTL, tmp);
15d3332f 2659 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3ce0a23d
JG		 2660
2661 /* Set the write pointer delay */
2662 WREG32(CP_RB_WPTR_DELAY, 0);
2663
2664 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2665 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2666 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 2667 ring->wptr = 0;
2668 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 2669
2670 /* set the wb address whether it's enabled or not */
4eace7fd 2671 WREG32(CP_RB_RPTR_ADDR,
4eace7fd 2672 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 2673 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2674 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2675
2676 if (rdev->wb.enabled)
2677 WREG32(SCRATCH_UMSK, 0xff);
2678 else {
2679 tmp |= RB_NO_UPDATE;
2680 WREG32(SCRATCH_UMSK, 0);
2681 }
2682
3ce0a23d
JG		 2683 mdelay(1);
2684 WREG32(CP_RB_CNTL, tmp);
2685
e32eb50d 2686 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
3ce0a23d
JG		 2687 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2688
3ce0a23d 2689 r600_cp_start(rdev);
e32eb50d 2690 ring->ready = true;
f712812e 2691 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
3ce0a23d 2692 if (r) {
e32eb50d 2693 ring->ready = false;
3ce0a23d
JG		 2694 return r;
2695 }
b9ace36f 2696
50efa51a 2697 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
b9ace36f
AD		 2698 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2699
3ce0a23d
JG		 2700 return 0;
2701}
2702
e32eb50d 2703void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
3ce0a23d
JG		 2704{
2705 u32 rb_bufsz;
45df6803 2706 int r;
3ce0a23d
JG		 2707
2708 /* Align ring size */
b72a8925 2709 rb_bufsz = order_base_2(ring_size / 8);
3ce0a23d 2710 ring_size = (1 << (rb_bufsz + 1)) * 4;
e32eb50d
CK		 2711 ring->ring_size = ring_size;
2712 ring->align_mask = 16 - 1;
45df6803 2713
89d35807
AD		 2714 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2715 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2716 if (r) {
2717 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2718 ring->rptr_save_reg = 0;
2719 }
45df6803 2720 }
3ce0a23d
JG		 2721}
2722
655efd3d
JG		 2723void r600_cp_fini(struct radeon_device *rdev)
2724{
45df6803 2725 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
655efd3d 2726 r600_cp_stop(rdev);
45df6803
CK		 2727 radeon_ring_fini(rdev, ring);
2728 radeon_scratch_free(rdev, ring->rptr_save_reg);
655efd3d
JG		 2729}
2730
3ce0a23d
JG		 2731/*
2732 * GPU scratch registers helpers function.
2733 */
2734void r600_scratch_init(struct radeon_device *rdev)
2735{
2736 int i;
2737
2738 rdev->scratch.num_reg = 7;
724c80e1 2739 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2740 for (i = 0; i < rdev->scratch.num_reg; i++) {
2741 rdev->scratch.free[i] = true;
724c80e1 2742 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2743 }
2744}
2745
e32eb50d 2746int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 2747{
2748 uint32_t scratch;
2749 uint32_t tmp = 0;
8b25ed34 2750 unsigned i;
3ce0a23d
JG		 2751 int r;
2752
2753 r = radeon_scratch_get(rdev, &scratch);
2754 if (r) {
2755 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2756 return r;
2757 }
2758 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 2759 r = radeon_ring_lock(rdev, ring, 3);
3ce0a23d 2760 if (r) {
8b25ed34 2761 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3ce0a23d
JG		 2762 radeon_scratch_free(rdev, scratch);
2763 return r;
2764 }
e32eb50d
CK		 2765 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2766 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2767 radeon_ring_write(ring, 0xDEADBEEF);
1538a9e0 2768 radeon_ring_unlock_commit(rdev, ring, false);
3ce0a23d
JG		 2769 for (i = 0; i < rdev->usec_timeout; i++) {
2770 tmp = RREG32(scratch);
2771 if (tmp == 0xDEADBEEF)
2772 break;
2773 DRM_UDELAY(1);
2774 }
2775 if (i < rdev->usec_timeout) {
8b25ed34 2776 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3ce0a23d 2777 } else {
bf852799 2778 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
8b25ed34 2779 ring->idx, scratch, tmp);
3ce0a23d
JG		 2780 r = -EINVAL;
2781 }
2782 radeon_scratch_free(rdev, scratch);
2783 return r;
2784}
2785
4d75658b
AD		 2786/*
2787 * CP fences/semaphores
2788 */
2789
3ce0a23d
JG		 2790void r600_fence_ring_emit(struct radeon_device *rdev,
2791 struct radeon_fence *fence)
2792{
e32eb50d 2793 struct radeon_ring *ring = &rdev->ring[fence->ring];
d45b964a
AD		 2794 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
2795 PACKET3_SH_ACTION_ENA;
2796
2797 if (rdev->family >= CHIP_RV770)
2798 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
7b1f2485 2799
d0f8a854 2800 if (rdev->wb.use_event) {
30eb77f4 2801 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
77b1bad4 2802 /* flush read cache over gart */
e32eb50d 2803 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
d45b964a 2804 radeon_ring_write(ring, cp_coher_cntl);
e32eb50d
CK		 2805 radeon_ring_write(ring, 0xFFFFFFFF);
2806 radeon_ring_write(ring, 0);
2807 radeon_ring_write(ring, 10); /* poll interval */
d0f8a854 2808 /* EVENT_WRITE_EOP - flush caches, send int */
e32eb50d
CK		 2809 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2810 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
5e167cdb 2811 radeon_ring_write(ring, lower_32_bits(addr));
e32eb50d
CK		 2812 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2813 radeon_ring_write(ring, fence->seq);
2814 radeon_ring_write(ring, 0);
d0f8a854 2815 } else {
77b1bad4 2816 /* flush read cache over gart */
e32eb50d 2817 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
d45b964a 2818 radeon_ring_write(ring, cp_coher_cntl);
e32eb50d
CK		 2819 radeon_ring_write(ring, 0xFFFFFFFF);
2820 radeon_ring_write(ring, 0);
2821 radeon_ring_write(ring, 10); /* poll interval */
2822 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2823 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
d0f8a854 2824 /* wait for 3D idle clean */
e32eb50d
CK		 2825 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2826 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2827 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
d0f8a854 2828 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 2829 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2830 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2831 radeon_ring_write(ring, fence->seq);
d0f8a854 2832 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
e32eb50d
CK		 2833 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2834 radeon_ring_write(ring, RB_INT_STAT);
d0f8a854 2835 }
3ce0a23d
JG		 2836}
2837
86302eea
CK		 2838/**
2839 * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2840 *
2841 * @rdev: radeon_device pointer
2842 * @ring: radeon ring buffer object
2843 * @semaphore: radeon semaphore object
2844 * @emit_wait: Is this a sempahore wait?
2845 *
2846 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2847 * from running ahead of semaphore waits.
2848 */
1654b817 2849bool r600_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 2850 struct radeon_ring *ring,
15d3332f 2851 struct radeon_semaphore *semaphore,
7b1f2485 2852 bool emit_wait)
15d3332f
CK		 2853{
2854 uint64_t addr = semaphore->gpu_addr;
2855 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2856
0be70439
CK		 2857 if (rdev->family < CHIP_CAYMAN)
2858 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2859
e32eb50d 2860 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
5e167cdb 2861 radeon_ring_write(ring, lower_32_bits(addr));
e32eb50d 2862 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
1654b817 2863
b6c2b4fa
AD		 2864 /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
2865 if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
86302eea
CK		 2866 /* Prevent the PFP from running ahead of the semaphore wait */
2867 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2868 radeon_ring_write(ring, 0x0);
2869 }
2870
1654b817 2871 return true;
15d3332f
CK		 2872}
2873
072b5acc
AD		 2874/**
2875 * r600_copy_cpdma - copy pages using the CP DMA engine
2876 *
2877 * @rdev: radeon_device pointer
2878 * @src_offset: src GPU address
2879 * @dst_offset: dst GPU address
2880 * @num_gpu_pages: number of GPU pages to xfer
2881 * @fence: radeon fence object
2882 *
2883 * Copy GPU paging using the CP DMA engine (r6xx+).
2884 * Used by the radeon ttm implementation to move pages if
2885 * registered as the asic copy callback.
2886 */
57d20a43
CK		 2887struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
2888 uint64_t src_offset, uint64_t dst_offset,
2889 unsigned num_gpu_pages,
2890 struct reservation_object *resv)
072b5acc
AD		 2891{
2892 struct radeon_semaphore *sem = NULL;
57d20a43 2893 struct radeon_fence *fence;
072b5acc
AD		 2894 int ring_index = rdev->asic->copy.blit_ring_index;
2895 struct radeon_ring *ring = &rdev->ring[ring_index];
2896 u32 size_in_bytes, cur_size_in_bytes, tmp;
2897 int i, num_loops;
2898 int r = 0;
2899
2900 r = radeon_semaphore_create(rdev, &sem);
2901 if (r) {
2902 DRM_ERROR("radeon: moving bo (%d).\n", r);
57d20a43 2903 return ERR_PTR(r);
072b5acc
AD		 2904 }
2905
2906 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2907 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
745a39a9 2908 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
072b5acc
AD		 2909 if (r) {
2910 DRM_ERROR("radeon: moving bo (%d).\n", r);
2911 radeon_semaphore_free(rdev, &sem, NULL);
57d20a43 2912 return ERR_PTR(r);
072b5acc
AD		 2913 }
2914
392a250b 2915 radeon_semaphore_sync_resv(rdev, sem, resv, false);
1654b817 2916 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
072b5acc 2917
745a39a9
AD		 2918 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2919 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2920 radeon_ring_write(ring, WAIT_3D_IDLE_bit);
072b5acc
AD		 2921 for (i = 0; i < num_loops; i++) {
2922 cur_size_in_bytes = size_in_bytes;
2923 if (cur_size_in_bytes > 0x1fffff)
2924 cur_size_in_bytes = 0x1fffff;
2925 size_in_bytes -= cur_size_in_bytes;
2926 tmp = upper_32_bits(src_offset) & 0xff;
2927 if (size_in_bytes == 0)
2928 tmp |= PACKET3_CP_DMA_CP_SYNC;
2929 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
5e167cdb 2930 radeon_ring_write(ring, lower_32_bits(src_offset));
072b5acc 2931 radeon_ring_write(ring, tmp);
5e167cdb 2932 radeon_ring_write(ring, lower_32_bits(dst_offset));
072b5acc
AD		 2933 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2934 radeon_ring_write(ring, cur_size_in_bytes);
2935 src_offset += cur_size_in_bytes;
2936 dst_offset += cur_size_in_bytes;
2937 }
2938 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2939 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2940 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
2941
57d20a43 2942 r = radeon_fence_emit(rdev, &fence, ring->idx);
072b5acc
AD		 2943 if (r) {
2944 radeon_ring_unlock_undo(rdev, ring);
aa4c8b36 2945 radeon_semaphore_free(rdev, &sem, NULL);
57d20a43 2946 return ERR_PTR(r);
072b5acc
AD		 2947 }
2948
1538a9e0 2949 radeon_ring_unlock_commit(rdev, ring, false);
57d20a43 2950 radeon_semaphore_free(rdev, &sem, fence);
072b5acc 2951
57d20a43 2952 return fence;
072b5acc
AD		 2953}
2954
3ce0a23d
JG		 2955int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2956 uint32_t tiling_flags, uint32_t pitch,
2957 uint32_t offset, uint32_t obj_size)
2958{
2959 /* FIXME: implement */
2960 return 0;
2961}
2962
2963void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2964{
2965 /* FIXME: implement */
2966}
2967
1109ca09 2968static int r600_startup(struct radeon_device *rdev)
3ce0a23d 2969{
4d75658b 2970 struct radeon_ring *ring;
3ce0a23d
JG		 2971 int r;
2972
9e46a48d
AD		 2973 /* enable pcie gen2 link */
2974 r600_pcie_gen2_enable(rdev);
2975
e5903d39
AD		 2976 /* scratch needs to be initialized before MC */
2977 r = r600_vram_scratch_init(rdev);
2978 if (r)
2979 return r;
2980
6fab3feb
AD		 2981 r600_mc_program(rdev);
2982
1a029b76
JG		 2983 if (rdev->flags & RADEON_IS_AGP) {
2984 r600_agp_enable(rdev);
2985 } else {
2986 r = r600_pcie_gart_enable(rdev);
2987 if (r)
2988 return r;
2989 }
3ce0a23d 2990 r600_gpu_init(rdev);
b70d6bb3 2991
724c80e1
AD		 2992 /* allocate wb buffer */
2993 r = radeon_wb_init(rdev);
2994 if (r)
2995 return r;
2996
30eb77f4
JG		 2997 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2998 if (r) {
2999 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3000 return r;
3001 }
3002
bdc99722
AD		 3003 if (rdev->has_uvd) {
3004 r = uvd_v1_0_resume(rdev);
3005 if (!r) {
3006 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
3007 if (r) {
3008 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
3009 }
856754c3 3010 }
bdc99722
AD		 3011 if (r)
3012 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
856754c3
CK		 3013 }
3014
d8f60cfc 3015 /* Enable IRQ */
e49f3959
AH		 3016 if (!rdev->irq.installed) {
3017 r = radeon_irq_kms_init(rdev);
3018 if (r)
3019 return r;
3020 }
3021
d8f60cfc
AD		 3022 r = r600_irq_init(rdev);
3023 if (r) {
3024 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3025 radeon_irq_kms_fini(rdev);
3026 return r;
3027 }
3028 r600_irq_set(rdev);
3029
4d75658b 3030 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
e32eb50d 3031 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2e1e6dad 3032 RADEON_CP_PACKET2);
4d75658b
AD		 3033 if (r)
3034 return r;
5596a9db 3035
3ce0a23d
JG		 3036 r = r600_cp_load_microcode(rdev);
3037 if (r)
3038 return r;
3039 r = r600_cp_resume(rdev);
3040 if (r)
3041 return r;
724c80e1 3042
bdc99722
AD		 3043 if (rdev->has_uvd) {
3044 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3045 if (ring->ring_size) {
3046 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
3047 RADEON_CP_PACKET2);
3048 if (!r)
3049 r = uvd_v1_0_init(rdev);
3050 if (r)
3051 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
3052 }
856754c3
CK		 3053 }
3054
2898c348
CK		 3055 r = radeon_ib_pool_init(rdev);
3056 if (r) {
3057 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3058 return r;
2898c348 3059 }
b15ba512 3060
d4e30ef0
AD		 3061 r = r600_audio_init(rdev);
3062 if (r) {
3063 DRM_ERROR("radeon: audio init failed\n");
3064 return r;
3065 }
3066
3ce0a23d
JG		 3067 return 0;
3068}
3069
28d52043
DA		 3070void r600_vga_set_state(struct radeon_device *rdev, bool state)
3071{
3072 uint32_t temp;
3073
3074 temp = RREG32(CONFIG_CNTL);
3075 if (state == false) {
3076 temp &= ~(1<<0);
3077 temp |= (1<<1);
3078 } else {
3079 temp &= ~(1<<1);
3080 }
3081 WREG32(CONFIG_CNTL, temp);
3082}
3083
fc30b8ef
DA		 3084int r600_resume(struct radeon_device *rdev)
3085{
3086 int r;
3087
1a029b76
JG		 3088 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
3089 * posting will perform necessary task to bring back GPU into good
3090 * shape.
3091 */
fc30b8ef 3092 /* post card */
e7d40b9a 3093 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef 3094
bc6a6295
AD		 3095 if (rdev->pm.pm_method == PM_METHOD_DPM)
3096 radeon_pm_resume(rdev);
6c7bccea 3097
b15ba512 3098 rdev->accel_working = true;
fc30b8ef
DA		 3099 r = r600_startup(rdev);
3100 if (r) {
3101 DRM_ERROR("r600 startup failed on resume\n");
6b7746e8 3102 rdev->accel_working = false;
fc30b8ef
DA		 3103 return r;
3104 }
3105
fc30b8ef
DA		 3106 return r;
3107}
3108
3ce0a23d
JG		 3109int r600_suspend(struct radeon_device *rdev)
3110{
6c7bccea 3111 radeon_pm_suspend(rdev);
38fd2c6f 3112 r600_audio_fini(rdev);
3ce0a23d 3113 r600_cp_stop(rdev);
bdc99722
AD		 3114 if (rdev->has_uvd) {
3115 uvd_v1_0_fini(rdev);
3116 radeon_uvd_suspend(rdev);
3117 }
0c45249f 3118 r600_irq_suspend(rdev);
724c80e1 3119 radeon_wb_disable(rdev);
4aac0473 3120 r600_pcie_gart_disable(rdev);
6ddddfe7 3121
3ce0a23d
JG		 3122 return 0;
3123}
3124
3125/* Plan is to move initialization in that function and use
3126 * helper function so that radeon_device_init pretty much
3127 * do nothing more than calling asic specific function. This
3128 * should also allow to remove a bunch of callback function
3129 * like vram_info.
3130 */
3131int r600_init(struct radeon_device *rdev)
771fe6b9 3132{
3ce0a23d 3133 int r;
771fe6b9 3134
3ce0a23d
JG		 3135 if (r600_debugfs_mc_info_init(rdev)) {
3136 DRM_ERROR("Failed to register debugfs file for mc !\n");
3137 }
3ce0a23d
JG		 3138 /* Read BIOS */
3139 if (!radeon_get_bios(rdev)) {
3140 if (ASIC_IS_AVIVO(rdev))
3141 return -EINVAL;
3142 }
3143 /* Must be an ATOMBIOS */
e7d40b9a
JG		 3144 if (!rdev->is_atom_bios) {
3145 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 3146 return -EINVAL;
e7d40b9a 3147 }
3ce0a23d
JG		 3148 r = radeon_atombios_init(rdev);
3149 if (r)
3150 return r;
3151 /* Post card if necessary */
fd909c37 3152 if (!radeon_card_posted(rdev)) {
72542d77
DA		 3153 if (!rdev->bios) {
3154 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3155 return -EINVAL;
3156 }
3ce0a23d
JG		 3157 DRM_INFO("GPU not posted. posting now...\n");
3158 atom_asic_init(rdev->mode_info.atom_context);
3159 }
3160 /* Initialize scratch registers */
3161 r600_scratch_init(rdev);
3162 /* Initialize surface registers */
3163 radeon_surface_init(rdev);
7433874e 3164 /* Initialize clocks */
5e6dde7e 3165 radeon_get_clock_info(rdev->ddev);
3ce0a23d 3166 /* Fence driver */
30eb77f4 3167 r = radeon_fence_driver_init(rdev);
3ce0a23d
JG		 3168 if (r)
3169 return r;
700a0cc0
JG		 3170 if (rdev->flags & RADEON_IS_AGP) {
3171 r = radeon_agp_init(rdev);
3172 if (r)
3173 radeon_agp_disable(rdev);
3174 }
3ce0a23d 3175 r = r600_mc_init(rdev);
b574f251 3176 if (r)
3ce0a23d 3177 return r;
3ce0a23d 3178 /* Memory manager */
4c788679 3179 r = radeon_bo_init(rdev);
3ce0a23d
JG		 3180 if (r)
3181 return r;
d8f60cfc 3182
01ac8794
AD		 3183 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3184 r = r600_init_microcode(rdev);
3185 if (r) {
3186 DRM_ERROR("Failed to load firmware!\n");
3187 return r;
3188 }
3189 }
3190
6c7bccea
AD		 3191 /* Initialize power management */
3192 radeon_pm_init(rdev);
3193
e32eb50d
CK		 3194 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3195 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3ce0a23d 3196
bdc99722
AD		 3197 if (rdev->has_uvd) {
3198 r = radeon_uvd_init(rdev);
3199 if (!r) {
3200 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3201 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
3202 }
856754c3
CK		 3203 }
3204
d8f60cfc
AD		 3205 rdev->ih.ring_obj = NULL;
3206 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 3207
4aac0473
JG		 3208 r = r600_pcie_gart_init(rdev);
3209 if (r)
3210 return r;
3211
779720a3 3212 rdev->accel_working = true;
fc30b8ef 3213 r = r600_startup(rdev);
3ce0a23d 3214 if (r) {
655efd3d
JG		 3215 dev_err(rdev->dev, "disabling GPU acceleration\n");
3216 r600_cp_fini(rdev);
655efd3d 3217 r600_irq_fini(rdev);
724c80e1 3218 radeon_wb_fini(rdev);
2898c348 3219 radeon_ib_pool_fini(rdev);
655efd3d 3220 radeon_irq_kms_fini(rdev);
75c81298 3221 r600_pcie_gart_fini(rdev);
733289c2 3222 rdev->accel_working = false;
3ce0a23d 3223 }
dafc3bd5 3224
3ce0a23d
JG		 3225 return 0;
3226}
3227
3228void r600_fini(struct radeon_device *rdev)
3229{
6c7bccea 3230 radeon_pm_fini(rdev);
dafc3bd5 3231 r600_audio_fini(rdev);
655efd3d 3232 r600_cp_fini(rdev);
d8f60cfc 3233 r600_irq_fini(rdev);
bdc99722
AD		 3234 if (rdev->has_uvd) {
3235 uvd_v1_0_fini(rdev);
3236 radeon_uvd_fini(rdev);
3237 }
724c80e1 3238 radeon_wb_fini(rdev);
2898c348 3239 radeon_ib_pool_fini(rdev);
d8f60cfc 3240 radeon_irq_kms_fini(rdev);
4aac0473 3241 r600_pcie_gart_fini(rdev);
16cdf04d 3242 r600_vram_scratch_fini(rdev);
655efd3d 3243 radeon_agp_fini(rdev);
3ce0a23d
JG		 3244 radeon_gem_fini(rdev);
3245 radeon_fence_driver_fini(rdev);
4c788679 3246 radeon_bo_fini(rdev);
e7d40b9a 3247 radeon_atombios_fini(rdev);
3ce0a23d
JG		 3248 kfree(rdev->bios);
3249 rdev->bios = NULL;
3ce0a23d
JG		 3250}
3251
3252
3253/*
3254 * CS stuff
3255 */
3256void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3257{
876dc9f3 3258 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 3259 u32 next_rptr;
7b1f2485 3260
45df6803 3261 if (ring->rptr_save_reg) {
89d35807 3262 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 3263 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3264 radeon_ring_write(ring, ((ring->rptr_save_reg -
3265 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3266 radeon_ring_write(ring, next_rptr);
89d35807
AD		 3267 } else if (rdev->wb.enabled) {
3268 next_rptr = ring->wptr + 5 + 4;
3269 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3270 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3271 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3272 radeon_ring_write(ring, next_rptr);
3273 radeon_ring_write(ring, 0);
45df6803
CK		 3274 }
3275
e32eb50d
CK		 3276 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3277 radeon_ring_write(ring,
4eace7fd
CC		 3278#ifdef __BIG_ENDIAN
3279 (2 << 0) |
3280#endif
3281 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 3282 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3283 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3284}
3285
f712812e 3286int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3287{
f2e39221 3288 struct radeon_ib ib;
3ce0a23d
JG		 3289 uint32_t scratch;
3290 uint32_t tmp = 0;
3291 unsigned i;
3292 int r;
3293
3294 r = radeon_scratch_get(rdev, &scratch);
3295 if (r) {
3296 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3297 return r;
3298 }
3299 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3300 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3ce0a23d
JG		 3301 if (r) {
3302 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
af026c5b 3303 goto free_scratch;
3ce0a23d 3304 }
f2e39221
JG		 3305 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3306 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3307 ib.ptr[2] = 0xDEADBEEF;
3308 ib.length_dw = 3;
1538a9e0 3309 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3ce0a23d 3310 if (r) {
3ce0a23d 3311 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
af026c5b 3312 goto free_ib;
3ce0a23d 3313 }
f2e39221 3314 r = radeon_fence_wait(ib.fence, false);
3ce0a23d
JG		 3315 if (r) {
3316 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
af026c5b 3317 goto free_ib;
3ce0a23d
JG		 3318 }
3319 for (i = 0; i < rdev->usec_timeout; i++) {
3320 tmp = RREG32(scratch);
3321 if (tmp == 0xDEADBEEF)
3322 break;
3323 DRM_UDELAY(1);
3324 }
3325 if (i < rdev->usec_timeout) {
f2e39221 3326 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3ce0a23d 3327 } else {
4417d7f6 3328 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3329 scratch, tmp);
3330 r = -EINVAL;
3331 }
af026c5b 3332free_ib:
3ce0a23d 3333 radeon_ib_free(rdev, &ib);
af026c5b
MD		 3334free_scratch:
3335 radeon_scratch_free(rdev, scratch);
771fe6b9
JG		 3336 return r;
3337}
3338
d8f60cfc
AD		 3339/*
3340 * Interrupts
3341 *
3342 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3343 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3344 * writing to the ring and the GPU consuming, the GPU writes to the ring
3345 * and host consumes. As the host irq handler processes interrupts, it
3346 * increments the rptr. When the rptr catches up with the wptr, all the
3347 * current interrupts have been processed.
3348 */
3349
3350void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3351{
3352 u32 rb_bufsz;
3353
3354 /* Align ring size */
b72a8925 3355 rb_bufsz = order_base_2(ring_size / 4);
d8f60cfc
AD		 3356 ring_size = (1 << rb_bufsz) * 4;
3357 rdev->ih.ring_size = ring_size;
0c45249f
JG		 3358 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3359 rdev->ih.rptr = 0;
d8f60cfc
AD		 3360}
3361
25a857fb 3362int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 3363{
3364 int r;
3365
d8f60cfc
AD		 3366 /* Allocate ring buffer */
3367 if (rdev->ih.ring_obj == NULL) {
441921d5 3368 r = radeon_bo_create(rdev, rdev->ih.ring_size,
268b2510 3369 PAGE_SIZE, true,
02376d82 3370 RADEON_GEM_DOMAIN_GTT, 0,
831b6966 3371 NULL, NULL, &rdev->ih.ring_obj);
d8f60cfc
AD		 3372 if (r) {
3373 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3374 return r;
3375 }
4c788679
JG		 3376 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3377 if (unlikely(r != 0))
3378 return r;
3379 r = radeon_bo_pin(rdev->ih.ring_obj,
3380 RADEON_GEM_DOMAIN_GTT,
3381 &rdev->ih.gpu_addr);
d8f60cfc 3382 if (r) {
4c788679 3383 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3384 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3385 return r;
3386 }
4c788679
JG		 3387 r = radeon_bo_kmap(rdev->ih.ring_obj,
3388 (void **)&rdev->ih.ring);
3389 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3390 if (r) {
3391 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3392 return r;
3393 }
3394 }
d8f60cfc
AD		 3395 return 0;
3396}
3397
25a857fb 3398void r600_ih_ring_fini(struct radeon_device *rdev)
d8f60cfc 3399{
4c788679 3400 int r;
d8f60cfc 3401 if (rdev->ih.ring_obj) {
4c788679
JG		 3402 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3403 if (likely(r == 0)) {
3404 radeon_bo_kunmap(rdev->ih.ring_obj);
3405 radeon_bo_unpin(rdev->ih.ring_obj);
3406 radeon_bo_unreserve(rdev->ih.ring_obj);
3407 }
3408 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 3409 rdev->ih.ring = NULL;
3410 rdev->ih.ring_obj = NULL;
3411 }
3412}
3413
45f9a39b 3414void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 3415{
3416
45f9a39b
AD		 3417 if ((rdev->family >= CHIP_RV770) &&
3418 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 3419 /* r7xx asics need to soft reset RLC before halting */
3420 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3421 RREG32(SRBM_SOFT_RESET);
4de833c3 3422 mdelay(15);
d8f60cfc
AD		 3423 WREG32(SRBM_SOFT_RESET, 0);
3424 RREG32(SRBM_SOFT_RESET);
3425 }
3426
3427 WREG32(RLC_CNTL, 0);
3428}
3429
3430static void r600_rlc_start(struct radeon_device *rdev)
3431{
3432 WREG32(RLC_CNTL, RLC_ENABLE);
3433}
3434
2948f5e6 3435static int r600_rlc_resume(struct radeon_device *rdev)
d8f60cfc
AD		 3436{
3437 u32 i;
3438 const __be32 *fw_data;
3439
3440 if (!rdev->rlc_fw)
3441 return -EINVAL;
3442
3443 r600_rlc_stop(rdev);
3444
d8f60cfc 3445 WREG32(RLC_HB_CNTL, 0);
c420c745 3446
2948f5e6
AD		 3447 WREG32(RLC_HB_BASE, 0);
3448 WREG32(RLC_HB_RPTR, 0);
3449 WREG32(RLC_HB_WPTR, 0);
3450 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3451 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
d8f60cfc
AD		 3452 WREG32(RLC_MC_CNTL, 0);
3453 WREG32(RLC_UCODE_CNTL, 0);
3454
3455 fw_data = (const __be32 *)rdev->rlc_fw->data;
2948f5e6 3456 if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 3457 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3458 WREG32(RLC_UCODE_ADDR, i);
3459 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3460 }
3461 } else {
138e4e16 3462 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
d8f60cfc
AD		 3463 WREG32(RLC_UCODE_ADDR, i);
3464 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3465 }
3466 }
3467 WREG32(RLC_UCODE_ADDR, 0);
3468
3469 r600_rlc_start(rdev);
3470
3471 return 0;
3472}
3473
3474static void r600_enable_interrupts(struct radeon_device *rdev)
3475{
3476 u32 ih_cntl = RREG32(IH_CNTL);
3477 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3478
3479 ih_cntl |= ENABLE_INTR;
3480 ih_rb_cntl |= IH_RB_ENABLE;
3481 WREG32(IH_CNTL, ih_cntl);
3482 WREG32(IH_RB_CNTL, ih_rb_cntl);
3483 rdev->ih.enabled = true;
3484}
3485
45f9a39b 3486void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 3487{
3488 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3489 u32 ih_cntl = RREG32(IH_CNTL);
3490
3491 ih_rb_cntl &= ~IH_RB_ENABLE;
3492 ih_cntl &= ~ENABLE_INTR;
3493 WREG32(IH_RB_CNTL, ih_rb_cntl);
3494 WREG32(IH_CNTL, ih_cntl);
3495 /* set rptr, wptr to 0 */
3496 WREG32(IH_RB_RPTR, 0);
3497 WREG32(IH_RB_WPTR, 0);
3498 rdev->ih.enabled = false;
d8f60cfc
AD		 3499 rdev->ih.rptr = 0;
3500}
3501
e0df1ac5
AD		 3502static void r600_disable_interrupt_state(struct radeon_device *rdev)
3503{
3504 u32 tmp;
3505
3555e53b 3506 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
4d75658b
AD		 3507 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3508 WREG32(DMA_CNTL, tmp);
e0df1ac5
AD		 3509 WREG32(GRBM_INT_CNTL, 0);
3510 WREG32(DxMODE_INT_MASK, 0);
6f34be50
AD		 3511 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3512 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
e0df1ac5
AD		 3513 if (ASIC_IS_DCE3(rdev)) {
3514 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3515 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3516 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3517 WREG32(DC_HPD1_INT_CONTROL, tmp);
3518 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3519 WREG32(DC_HPD2_INT_CONTROL, tmp);
3520 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3521 WREG32(DC_HPD3_INT_CONTROL, tmp);
3522 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3523 WREG32(DC_HPD4_INT_CONTROL, tmp);
3524 if (ASIC_IS_DCE32(rdev)) {
3525 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3526 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 3527 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3528 WREG32(DC_HPD6_INT_CONTROL, tmp);
c6543a6e
RM		 3529 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3530 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3531 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3532 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f122c610
AD		 3533 } else {
3534 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3535 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3536 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3537 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3538 }
3539 } else {
3540 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3541 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3542 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3543 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 3544 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3545 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 3546 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3547 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
f122c610
AD		 3548 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3549 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3550 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3551 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3552 }
3553}
3554
d8f60cfc
AD		 3555int r600_irq_init(struct radeon_device *rdev)
3556{
3557 int ret = 0;
3558 int rb_bufsz;
3559 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3560
3561 /* allocate ring */
0c45249f 3562 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 3563 if (ret)
3564 return ret;
3565
3566 /* disable irqs */
3567 r600_disable_interrupts(rdev);
3568
3569 /* init rlc */
2948f5e6
AD		 3570 if (rdev->family >= CHIP_CEDAR)
3571 ret = evergreen_rlc_resume(rdev);
3572 else
3573 ret = r600_rlc_resume(rdev);
d8f60cfc
AD		 3574 if (ret) {
3575 r600_ih_ring_fini(rdev);
3576 return ret;
3577 }
3578
3579 /* setup interrupt control */
3580 /* set dummy read address to ring address */
3581 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3582 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3583 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3584 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3585 */
3586 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3587 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3588 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3589 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3590
3591 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
b72a8925 3592 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
d8f60cfc
AD		 3593
3594 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3595 IH_WPTR_OVERFLOW_CLEAR |
3596 (rb_bufsz << 1));
724c80e1
AD		 3597
3598 if (rdev->wb.enabled)
3599 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3600
3601 /* set the writeback address whether it's enabled or not */
3602 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3603 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 3604
3605 WREG32(IH_RB_CNTL, ih_rb_cntl);
3606
3607 /* set rptr, wptr to 0 */
3608 WREG32(IH_RB_RPTR, 0);
3609 WREG32(IH_RB_WPTR, 0);
3610
3611 /* Default settings for IH_CNTL (disabled at first) */
3612 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3613 /* RPTR_REARM only works if msi's are enabled */
3614 if (rdev->msi_enabled)
3615 ih_cntl |= RPTR_REARM;
d8f60cfc
AD		 3616 WREG32(IH_CNTL, ih_cntl);
3617
3618 /* force the active interrupt state to all disabled */
45f9a39b
AD		 3619 if (rdev->family >= CHIP_CEDAR)
3620 evergreen_disable_interrupt_state(rdev);
3621 else
3622 r600_disable_interrupt_state(rdev);
d8f60cfc 3623
2099810f
DA		 3624 /* at this point everything should be setup correctly to enable master */
3625 pci_set_master(rdev->pdev);
3626
d8f60cfc
AD		 3627 /* enable irqs */
3628 r600_enable_interrupts(rdev);
3629
3630 return ret;
3631}
3632
0c45249f 3633void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 3634{
45f9a39b 3635 r600_irq_disable(rdev);
d8f60cfc 3636 r600_rlc_stop(rdev);
0c45249f
JG		 3637}
3638
3639void r600_irq_fini(struct radeon_device *rdev)
3640{
3641 r600_irq_suspend(rdev);
d8f60cfc
AD		 3642 r600_ih_ring_fini(rdev);
3643}
3644
3645int r600_irq_set(struct radeon_device *rdev)
3646{
e0df1ac5
AD		 3647 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3648 u32 mode_int = 0;
3649 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3650 u32 grbm_int_cntl = 0;
f122c610 3651 u32 hdmi0, hdmi1;
4d75658b 3652 u32 dma_cntl;
4a6369e9 3653 u32 thermal_int = 0;
d8f60cfc 3654
003e69f9 3655 if (!rdev->irq.installed) {
fce7d61b 3656 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3657 return -EINVAL;
3658 }
d8f60cfc 3659 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3660 if (!rdev->ih.enabled) {
3661 r600_disable_interrupts(rdev);
3662 /* force the active interrupt state to all disabled */
3663 r600_disable_interrupt_state(rdev);
d8f60cfc 3664 return 0;
79c2bbc5 3665 }
d8f60cfc 3666
e0df1ac5
AD		 3667 if (ASIC_IS_DCE3(rdev)) {
3668 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3669 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3670 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3671 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3672 if (ASIC_IS_DCE32(rdev)) {
3673 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3674 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
c6543a6e
RM		 3675 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3676 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
f122c610
AD		 3677 } else {
3678 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3679 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5
AD		 3680 }
3681 } else {
3682 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3683 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3684 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
f122c610
AD		 3685 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3686 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5 3687 }
4a6369e9 3688
4d75658b 3689 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
e0df1ac5 3690
4a6369e9
AD		 3691 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3692 thermal_int = RREG32(CG_THERMAL_INT) &
3693 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
66229b20
AD		 3694 } else if (rdev->family >= CHIP_RV770) {
3695 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3696 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3697 }
3698 if (rdev->irq.dpm_thermal) {
3699 DRM_DEBUG("dpm thermal\n");
3700 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
4a6369e9
AD		 3701 }
3702
736fc37f 3703 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
d8f60cfc
AD		 3704 DRM_DEBUG("r600_irq_set: sw int\n");
3705 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3706 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc 3707 }
4d75658b
AD		 3708
3709 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3710 DRM_DEBUG("r600_irq_set: sw int dma\n");
3711 dma_cntl |= TRAP_ENABLE;
3712 }
3713
6f34be50 3714 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3715 atomic_read(&rdev->irq.pflip[0])) {
d8f60cfc
AD		 3716 DRM_DEBUG("r600_irq_set: vblank 0\n");
3717 mode_int |= D1MODE_VBLANK_INT_MASK;
3718 }
6f34be50 3719 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3720 atomic_read(&rdev->irq.pflip[1])) {
d8f60cfc
AD		 3721 DRM_DEBUG("r600_irq_set: vblank 1\n");
3722 mode_int |= D2MODE_VBLANK_INT_MASK;
3723 }
e0df1ac5
AD		 3724 if (rdev->irq.hpd[0]) {
3725 DRM_DEBUG("r600_irq_set: hpd 1\n");
3726 hpd1 |= DC_HPDx_INT_EN;
3727 }
3728 if (rdev->irq.hpd[1]) {
3729 DRM_DEBUG("r600_irq_set: hpd 2\n");
3730 hpd2 |= DC_HPDx_INT_EN;
3731 }
3732 if (rdev->irq.hpd[2]) {
3733 DRM_DEBUG("r600_irq_set: hpd 3\n");
3734 hpd3 |= DC_HPDx_INT_EN;
3735 }
3736 if (rdev->irq.hpd[3]) {
3737 DRM_DEBUG("r600_irq_set: hpd 4\n");
3738 hpd4 |= DC_HPDx_INT_EN;
3739 }
3740 if (rdev->irq.hpd[4]) {
3741 DRM_DEBUG("r600_irq_set: hpd 5\n");
3742 hpd5 |= DC_HPDx_INT_EN;
3743 }
3744 if (rdev->irq.hpd[5]) {
3745 DRM_DEBUG("r600_irq_set: hpd 6\n");
3746 hpd6 |= DC_HPDx_INT_EN;
3747 }
f122c610
AD		 3748 if (rdev->irq.afmt[0]) {
3749 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3750 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3751 }
f122c610
AD		 3752 if (rdev->irq.afmt[1]) {
3753 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3754 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3755 }
d8f60cfc
AD		 3756
3757 WREG32(CP_INT_CNTL, cp_int_cntl);
4d75658b 3758 WREG32(DMA_CNTL, dma_cntl);
d8f60cfc 3759 WREG32(DxMODE_INT_MASK, mode_int);
f5d636d2
CK		 3760 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3761 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
2031f77c 3762 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
e0df1ac5
AD		 3763 if (ASIC_IS_DCE3(rdev)) {
3764 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3765 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3766 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3767 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3768 if (ASIC_IS_DCE32(rdev)) {
3769 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3770 WREG32(DC_HPD6_INT_CONTROL, hpd6);
c6543a6e
RM		 3771 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3772 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
f122c610
AD		 3773 } else {
3774 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3775 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5
AD		 3776 }
3777 } else {
3778 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3779 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3780 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
f122c610
AD		 3781 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3782 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5 3783 }
4a6369e9
AD		 3784 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3785 WREG32(CG_THERMAL_INT, thermal_int);
66229b20
AD		 3786 } else if (rdev->family >= CHIP_RV770) {
3787 WREG32(RV770_CG_THERMAL_INT, thermal_int);
4a6369e9 3788 }
d8f60cfc
AD		 3789
3790 return 0;
3791}
3792
ce580fab 3793static void r600_irq_ack(struct radeon_device *rdev)
d8f60cfc 3794{
e0df1ac5
AD		 3795 u32 tmp;
3796
3797 if (ASIC_IS_DCE3(rdev)) {
6f34be50
AD		 3798 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3799 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3800 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
f122c610 3801 if (ASIC_IS_DCE32(rdev)) {
c6543a6e
RM		 3802 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3803 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
f122c610
AD		 3804 } else {
3805 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3806 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3807 }
e0df1ac5 3808 } else {
6f34be50
AD		 3809 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3810 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3811 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
f122c610
AD		 3812 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3813 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
6f34be50
AD		 3814 }
3815 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3816 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3817
3818 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3819 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3820 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3821 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3822 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3823 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3824 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3825 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3826 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3827 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3828 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3829 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3830 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
e0df1ac5
AD		 3831 if (ASIC_IS_DCE3(rdev)) {
3832 tmp = RREG32(DC_HPD1_INT_CONTROL);
3833 tmp |= DC_HPDx_INT_ACK;
3834 WREG32(DC_HPD1_INT_CONTROL, tmp);
3835 } else {
3836 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3837 tmp |= DC_HPDx_INT_ACK;
3838 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3839 }
3840 }
6f34be50 3841 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
e0df1ac5
AD		 3842 if (ASIC_IS_DCE3(rdev)) {
3843 tmp = RREG32(DC_HPD2_INT_CONTROL);
3844 tmp |= DC_HPDx_INT_ACK;
3845 WREG32(DC_HPD2_INT_CONTROL, tmp);
3846 } else {
3847 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3848 tmp |= DC_HPDx_INT_ACK;
3849 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3850 }
3851 }
6f34be50 3852 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
e0df1ac5
AD		 3853 if (ASIC_IS_DCE3(rdev)) {
3854 tmp = RREG32(DC_HPD3_INT_CONTROL);
3855 tmp |= DC_HPDx_INT_ACK;
3856 WREG32(DC_HPD3_INT_CONTROL, tmp);
3857 } else {
3858 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3859 tmp |= DC_HPDx_INT_ACK;
3860 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3861 }
3862 }
6f34be50 3863 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
e0df1ac5
AD		 3864 tmp = RREG32(DC_HPD4_INT_CONTROL);
3865 tmp |= DC_HPDx_INT_ACK;
3866 WREG32(DC_HPD4_INT_CONTROL, tmp);
3867 }
3868 if (ASIC_IS_DCE32(rdev)) {
6f34be50 3869 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
e0df1ac5
AD		 3870 tmp = RREG32(DC_HPD5_INT_CONTROL);
3871 tmp |= DC_HPDx_INT_ACK;
3872 WREG32(DC_HPD5_INT_CONTROL, tmp);
3873 }
6f34be50 3874 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
e0df1ac5
AD		 3875 tmp = RREG32(DC_HPD5_INT_CONTROL);
3876 tmp |= DC_HPDx_INT_ACK;
3877 WREG32(DC_HPD6_INT_CONTROL, tmp);
3878 }
f122c610 3879 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3880 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
f122c610 3881 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3882 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
f122c610
AD		 3883 }
3884 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3885 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
f122c610 3886 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3887 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f2594933
CK		 3888 }
3889 } else {
f122c610
AD		 3890 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3891 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3892 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3893 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3894 }
3895 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3896 if (ASIC_IS_DCE3(rdev)) {
3897 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3898 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3899 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3900 } else {
3901 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3902 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3903 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3904 }
f2594933
CK		 3905 }
3906 }
d8f60cfc
AD		 3907}
3908
3909void r600_irq_disable(struct radeon_device *rdev)
3910{
d8f60cfc
AD		 3911 r600_disable_interrupts(rdev);
3912 /* Wait and acknowledge irq */
3913 mdelay(1);
6f34be50 3914 r600_irq_ack(rdev);
e0df1ac5 3915 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3916}
3917
ce580fab 3918static u32 r600_get_ih_wptr(struct radeon_device *rdev)
d8f60cfc
AD		 3919{
3920 u32 wptr, tmp;
3ce0a23d 3921
724c80e1 3922 if (rdev->wb.enabled)
204ae24d 3923 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 3924 else
3925 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3926
d8f60cfc 3927 if (wptr & RB_OVERFLOW) {
11bab0ae 3928 wptr &= ~RB_OVERFLOW;
7924e5eb
JG		 3929 /* When a ring buffer overflow happen start parsing interrupt
3930 * from the last not overwritten vector (wptr + 16). Hopefully
3931 * this should allow us to catchup.
3932 */
6cc2fda2
MD		 3933 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
3934 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
7924e5eb 3935 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3936 tmp = RREG32(IH_RB_CNTL);
3937 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3938 WREG32(IH_RB_CNTL, tmp);
3939 }
0c45249f 3940 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3941}
3ce0a23d 3942
d8f60cfc
AD		 3943/* r600 IV Ring
3944 * Each IV ring entry is 128 bits:
3945 * [7:0] - interrupt source id
3946 * [31:8] - reserved
3947 * [59:32] - interrupt source data
3948 * [127:60] - reserved
3949 *
3950 * The basic interrupt vector entries
3951 * are decoded as follows:
3952 * src_id src_data description
3953 * 1 0 D1 Vblank
3954 * 1 1 D1 Vline
3955 * 5 0 D2 Vblank
3956 * 5 1 D2 Vline
3957 * 19 0 FP Hot plug detection A
3958 * 19 1 FP Hot plug detection B
3959 * 19 2 DAC A auto-detection
3960 * 19 3 DAC B auto-detection
f2594933
CK		 3961 * 21 4 HDMI block A
3962 * 21 5 HDMI block B
d8f60cfc
AD		 3963 * 176 - CP_INT RB
3964 * 177 - CP_INT IB1
3965 * 178 - CP_INT IB2
3966 * 181 - EOP Interrupt
3967 * 233 - GUI Idle
3968 *
3969 * Note, these are based on r600 and may need to be
3970 * adjusted or added to on newer asics
3971 */
3972
3973int r600_irq_process(struct radeon_device *rdev)
3974{
682f1a54
DA		 3975 u32 wptr;
3976 u32 rptr;
d8f60cfc 3977 u32 src_id, src_data;
6f34be50 3978 u32 ring_index;
d4877cf2 3979 bool queue_hotplug = false;
f122c610 3980 bool queue_hdmi = false;
4a6369e9 3981 bool queue_thermal = false;
d8f60cfc 3982
682f1a54 3983 if (!rdev->ih.enabled || rdev->shutdown)
79c2bbc5 3984 return IRQ_NONE;
d8f60cfc 3985
f6a56939
BH		 3986 /* No MSIs, need a dummy read to flush PCI DMAs */
3987 if (!rdev->msi_enabled)
3988 RREG32(IH_RB_WPTR);
3989
682f1a54 3990 wptr = r600_get_ih_wptr(rdev);
d8f60cfc 3991
c20dc369
CK		 3992restart_ih:
3993 /* is somebody else already processing irqs? */
3994 if (atomic_xchg(&rdev->ih.lock, 1))
d8f60cfc 3995 return IRQ_NONE;
d8f60cfc 3996
c20dc369
CK		 3997 rptr = rdev->ih.rptr;
3998 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3999
964f6645
BH		 4000 /* Order reading of wptr vs. reading of IH ring data */
4001 rmb();
4002
d8f60cfc 4003 /* display interrupts */
6f34be50 4004 r600_irq_ack(rdev);
d8f60cfc 4005
d8f60cfc
AD		 4006 while (rptr != wptr) {
4007 /* wptr/rptr are in bytes! */
4008 ring_index = rptr / 4;
4eace7fd
CC		 4009 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4010 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
d8f60cfc
AD		 4011
4012 switch (src_id) {
4013 case 1: /* D1 vblank/vline */
4014 switch (src_data) {
4015 case 0: /* D1 vblank */
6f34be50 4016 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 4017 if (rdev->irq.crtc_vblank_int[0]) {
4018 drm_handle_vblank(rdev->ddev, 0);
4019 rdev->pm.vblank_sync = true;
4020 wake_up(&rdev->irq.vblank_queue);
4021 }
736fc37f 4022 if (atomic_read(&rdev->irq.pflip[0]))
1a0e7918 4023 radeon_crtc_handle_vblank(rdev, 0);
6f34be50 4024 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
d8f60cfc
AD		 4025 DRM_DEBUG("IH: D1 vblank\n");
4026 }
4027 break;
4028 case 1: /* D1 vline */
6f34be50
AD		 4029 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
4030 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
d8f60cfc
AD		 4031 DRM_DEBUG("IH: D1 vline\n");
4032 }
4033 break;
4034 default:
b042589c 4035 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 4036 break;
4037 }
4038 break;
4039 case 5: /* D2 vblank/vline */
4040 switch (src_data) {
4041 case 0: /* D2 vblank */
6f34be50 4042 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 4043 if (rdev->irq.crtc_vblank_int[1]) {
4044 drm_handle_vblank(rdev->ddev, 1);
4045 rdev->pm.vblank_sync = true;
4046 wake_up(&rdev->irq.vblank_queue);
4047 }
736fc37f 4048 if (atomic_read(&rdev->irq.pflip[1]))
1a0e7918 4049 radeon_crtc_handle_vblank(rdev, 1);
6f34be50 4050 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
d8f60cfc
AD		 4051 DRM_DEBUG("IH: D2 vblank\n");
4052 }
4053 break;
4054 case 1: /* D1 vline */
6f34be50
AD		 4055 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
4056 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
d8f60cfc
AD		 4057 DRM_DEBUG("IH: D2 vline\n");
4058 }
4059 break;
4060 default:
b042589c 4061 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 4062 break;
4063 }
4064 break;
f5d636d2
CK		 4065 case 9: /* D1 pflip */
4066 DRM_DEBUG("IH: D1 flip\n");
39dc5454
MK		 4067 if (radeon_use_pflipirq > 0)
4068 radeon_crtc_handle_flip(rdev, 0);
f5d636d2
CK		 4069 break;
4070 case 11: /* D2 pflip */
4071 DRM_DEBUG("IH: D2 flip\n");
39dc5454
MK		 4072 if (radeon_use_pflipirq > 0)
4073 radeon_crtc_handle_flip(rdev, 1);
f5d636d2 4074 break;
e0df1ac5
AD		 4075 case 19: /* HPD/DAC hotplug */
4076 switch (src_data) {
4077 case 0:
6f34be50
AD		 4078 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
4079 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 4080 queue_hotplug = true;
4081 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 4082 }
4083 break;
4084 case 1:
6f34be50
AD		 4085 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
4086 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 4087 queue_hotplug = true;
4088 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 4089 }
4090 break;
4091 case 4:
6f34be50
AD		 4092 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
4093 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 4094 queue_hotplug = true;
4095 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 4096 }
4097 break;
4098 case 5:
6f34be50
AD		 4099 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
4100 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 4101 queue_hotplug = true;
4102 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 4103 }
4104 break;
4105 case 10:
6f34be50
AD		 4106 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
4107 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 4108 queue_hotplug = true;
4109 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 4110 }
4111 break;
4112 case 12:
6f34be50
AD		 4113 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
4114 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 4115 queue_hotplug = true;
4116 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 4117 }
4118 break;
4119 default:
b042589c 4120 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 4121 break;
4122 }
4123 break;
f122c610
AD		 4124 case 21: /* hdmi */
4125 switch (src_data) {
4126 case 4:
4127 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
4128 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4129 queue_hdmi = true;
4130 DRM_DEBUG("IH: HDMI0\n");
4131 }
4132 break;
4133 case 5:
4134 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
4135 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
4136 queue_hdmi = true;
4137 DRM_DEBUG("IH: HDMI1\n");
4138 }
4139 break;
4140 default:
4141 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
4142 break;
4143 }
f2594933 4144 break;
858a41c8
AD		 4145 case 124: /* UVD */
4146 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4147 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4148 break;
d8f60cfc
AD		 4149 case 176: /* CP_INT in ring buffer */
4150 case 177: /* CP_INT in IB1 */
4151 case 178: /* CP_INT in IB2 */
4152 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 4153 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc
AD		 4154 break;
4155 case 181: /* CP EOP event */
4156 DRM_DEBUG("IH: CP EOP\n");
7465280c 4157 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc 4158 break;
4d75658b
AD		 4159 case 224: /* DMA trap event */
4160 DRM_DEBUG("IH: DMA trap\n");
4161 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4162 break;
4a6369e9
AD		 4163 case 230: /* thermal low to high */
4164 DRM_DEBUG("IH: thermal low to high\n");
4165 rdev->pm.dpm.thermal.high_to_low = false;
4166 queue_thermal = true;
4167 break;
4168 case 231: /* thermal high to low */
4169 DRM_DEBUG("IH: thermal high to low\n");
4170 rdev->pm.dpm.thermal.high_to_low = true;
4171 queue_thermal = true;
4172 break;
2031f77c 4173 case 233: /* GUI IDLE */
303c805c 4174 DRM_DEBUG("IH: GUI idle\n");
2031f77c 4175 break;
d8f60cfc 4176 default:
b042589c 4177 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 4178 break;
4179 }
4180
4181 /* wptr/rptr are in bytes! */
0c45249f
JG		 4182 rptr += 16;
4183 rptr &= rdev->ih.ptr_mask;
f55e03b9 4184 WREG32(IH_RB_RPTR, rptr);
d8f60cfc 4185 }
d4877cf2 4186 if (queue_hotplug)
32c87fca 4187 schedule_work(&rdev->hotplug_work);
f122c610
AD		 4188 if (queue_hdmi)
4189 schedule_work(&rdev->audio_work);
4a6369e9
AD		 4190 if (queue_thermal && rdev->pm.dpm_enabled)
4191 schedule_work(&rdev->pm.dpm.thermal.work);
d8f60cfc 4192 rdev->ih.rptr = rptr;
c20dc369
CK		 4193 atomic_set(&rdev->ih.lock, 0);
4194
4195 /* make sure wptr hasn't changed while processing */
4196 wptr = r600_get_ih_wptr(rdev);
4197 if (wptr != rptr)
4198 goto restart_ih;
4199
d8f60cfc
AD		 4200 return IRQ_HANDLED;
4201}
3ce0a23d
JG		 4202
4203/*
4204 * Debugfs info
4205 */
4206#if defined(CONFIG_DEBUG_FS)
4207
3ce0a23d
JG		 4208static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4209{
4210 struct drm_info_node *node = (struct drm_info_node *) m->private;
4211 struct drm_device *dev = node->minor->dev;
4212 struct radeon_device *rdev = dev->dev_private;
4213
4214 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4215 DREG32_SYS(m, rdev, VM_L2_STATUS);
4216 return 0;
4217}
4218
4219static struct drm_info_list r600_mc_info_list[] = {
4220 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3ce0a23d
JG		 4221};
4222#endif
4223
4224int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4225{
4226#if defined(CONFIG_DEBUG_FS)
4227 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4228#else
4229 return 0;
4230#endif
771fe6b9 4231}
062b389c
JG		 4232
4233/**
124764f1 4234 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
062b389c 4235 * rdev: radeon device structure
062b389c 4236 *
124764f1
MD		 4237 * Some R6XX/R7XX don't seem to take into account HDP flushes performed
4238 * through the ring buffer. This leads to corruption in rendering, see
4239 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
4240 * directly perform the HDP flush by writing the register through MMIO.
062b389c 4241 */
124764f1 4242void r600_mmio_hdp_flush(struct radeon_device *rdev)
062b389c 4243{
812d0469 4244 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 4245 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4246 * This seems to cause problems on some AGP cards. Just use the old
4247 * method for them.
812d0469 4248 */
e488459a 4249 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 4250 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 4251 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 4252 u32 tmp;
4253
4254 WREG32(HDP_DEBUG1, 0);
4255 tmp = readl((void __iomem *)ptr);
4256 } else
4257 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 4258}
3313e3d4
AD		 4259
4260void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4261{
d5445a17 4262 u32 link_width_cntl, mask;
3313e3d4
AD		 4263
4264 if (rdev->flags & RADEON_IS_IGP)
4265 return;
4266
4267 if (!(rdev->flags & RADEON_IS_PCIE))
4268 return;
4269
4270 /* x2 cards have a special sequence */
4271 if (ASIC_IS_X2(rdev))
4272 return;
4273
d5445a17 4274 radeon_gui_idle(rdev);
3313e3d4
AD		 4275
4276 switch (lanes) {
4277 case 0:
4278 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4279 break;
4280 case 1:
4281 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4282 break;
4283 case 2:
4284 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4285 break;
4286 case 4:
4287 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4288 break;
4289 case 8:
4290 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4291 break;
4292 case 12:
d5445a17 4293 /* not actually supported */
3313e3d4
AD		 4294 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4295 break;
4296 case 16:
3313e3d4
AD		 4297 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4298 break;
d5445a17
AD		 4299 default:
4300 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4301 return;
3313e3d4
AD		 4302 }
4303
492d2b61 4304 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
d5445a17
AD		 4305 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4306 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4307 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4308 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3313e3d4 4309
492d2b61 4310 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3313e3d4
AD		 4311}
4312
4313int r600_get_pcie_lanes(struct radeon_device *rdev)
4314{
4315 u32 link_width_cntl;
4316
4317 if (rdev->flags & RADEON_IS_IGP)
4318 return 0;
4319
4320 if (!(rdev->flags & RADEON_IS_PCIE))
4321 return 0;
4322
4323 /* x2 cards have a special sequence */
4324 if (ASIC_IS_X2(rdev))
4325 return 0;
4326
d5445a17 4327 radeon_gui_idle(rdev);
3313e3d4 4328
492d2b61 4329 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3313e3d4
AD		 4330
4331 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3313e3d4
AD		 4332 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4333 return 1;
4334 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4335 return 2;
4336 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4337 return 4;
4338 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4339 return 8;
d5445a17
AD		 4340 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4341 /* not actually supported */
4342 return 12;
4343 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3313e3d4
AD		 4344 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4345 default:
4346 return 16;
4347 }
4348}
4349
9e46a48d
AD		 4350static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4351{
4352 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4353 u16 link_cntl2;
4354
d42dd579
AD		 4355 if (radeon_pcie_gen2 == 0)
4356 return;
4357
9e46a48d
AD		 4358 if (rdev->flags & RADEON_IS_IGP)
4359 return;
4360
4361 if (!(rdev->flags & RADEON_IS_PCIE))
4362 return;
4363
4364 /* x2 cards have a special sequence */
4365 if (ASIC_IS_X2(rdev))
4366 return;
4367
4368 /* only RV6xx+ chips are supported */
4369 if (rdev->family <= CHIP_R600)
4370 return;
4371
7e0e4196
KSS		 4372 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4373 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
197bbb3d
DA		 4374 return;
4375
492d2b61 4376 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3691feea
AD		 4377 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4378 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4379 return;
4380 }
4381
197bbb3d
DA		 4382 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4383
9e46a48d
AD		 4384 /* 55 nm r6xx asics */
4385 if ((rdev->family == CHIP_RV670) ||
4386 (rdev->family == CHIP_RV620) ||
4387 (rdev->family == CHIP_RV635)) {
4388 /* advertise upconfig capability */
492d2b61 4389 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d 4390 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61
AD		 4391 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4392 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d
AD		 4393 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4394 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4395 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4396 LC_RECONFIG_ARC_MISSING_ESCAPE);
4397 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
492d2b61 4398 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4399 } else {
4400 link_width_cntl |= LC_UPCONFIGURE_DIS;
492d2b61 4401 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4402 }
4403 }
4404
492d2b61 4405 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d
AD		 4406 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4407 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4408
4409 /* 55 nm r6xx asics */
4410 if ((rdev->family == CHIP_RV670) ||
4411 (rdev->family == CHIP_RV620) ||
4412 (rdev->family == CHIP_RV635)) {
4413 WREG32(MM_CFGREGS_CNTL, 0x8);
4414 link_cntl2 = RREG32(0x4088);
4415 WREG32(MM_CFGREGS_CNTL, 0);
4416 /* not supported yet */
4417 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4418 return;
4419 }
4420
4421 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4422 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4423 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4424 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4425 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
492d2b61 4426 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4427
4428 tmp = RREG32(0x541c);
4429 WREG32(0x541c, tmp | 0x8);
4430 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4431 link_cntl2 = RREG16(0x4088);
4432 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4433 link_cntl2 |= 0x2;
4434 WREG16(0x4088, link_cntl2);
4435 WREG32(MM_CFGREGS_CNTL, 0);
4436
4437 if ((rdev->family == CHIP_RV670) ||
4438 (rdev->family == CHIP_RV620) ||
4439 (rdev->family == CHIP_RV635)) {
492d2b61 4440 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
9e46a48d 4441 training_cntl &= ~LC_POINT_7_PLUS_EN;
492d2b61 4442 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
9e46a48d 4443 } else {
492d2b61 4444 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4445 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
492d2b61 4446 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4447 }
4448
492d2b61 4449 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4450 speed_cntl |= LC_GEN2_EN_STRAP;
492d2b61 4451 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4452
4453 } else {
492d2b61 4454 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d
AD		 4455 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4456 if (1)
4457 link_width_cntl |= LC_UPCONFIGURE_DIS;
4458 else
4459 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61 4460 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4461 }
4462}
6759a0a7
MO		 4463
4464/**
d0418894 4465 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
6759a0a7
MO		 4466 *
4467 * @rdev: radeon_device pointer
4468 *
4469 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4470 * Returns the 64 bit clock counter snapshot.
4471 */
d0418894 4472uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
6759a0a7
MO		 4473{
4474 uint64_t clock;
4475
4476 mutex_lock(&rdev->gpu_clock_mutex);
4477 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4478 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4479 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4480 mutex_unlock(&rdev->gpu_clock_mutex);
4481 return clock;
4482}
Linux 6.x block layer and io_uring tree(s)