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drm/radeon/uvd: revert lower msg&fb buffer requirements on UVD3
[linux-2.6-block.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
e0cd3608 31#include <linux/module.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
771fe6b9 34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "radeon_mode.h"
3ce0a23d 37#include "r600d.h"
3ce0a23d 38#include "atom.h"
d39c3b89 39#include "avivod.h"
138e4e16 40#include "radeon_ucode.h"
3ce0a23d
JG		 41
42/* Firmware Names */
43MODULE_FIRMWARE("radeon/R600_pfp.bin");
44MODULE_FIRMWARE("radeon/R600_me.bin");
45MODULE_FIRMWARE("radeon/RV610_pfp.bin");
46MODULE_FIRMWARE("radeon/RV610_me.bin");
47MODULE_FIRMWARE("radeon/RV630_pfp.bin");
48MODULE_FIRMWARE("radeon/RV630_me.bin");
49MODULE_FIRMWARE("radeon/RV620_pfp.bin");
50MODULE_FIRMWARE("radeon/RV620_me.bin");
51MODULE_FIRMWARE("radeon/RV635_pfp.bin");
52MODULE_FIRMWARE("radeon/RV635_me.bin");
53MODULE_FIRMWARE("radeon/RV670_pfp.bin");
54MODULE_FIRMWARE("radeon/RV670_me.bin");
55MODULE_FIRMWARE("radeon/RS780_pfp.bin");
56MODULE_FIRMWARE("radeon/RS780_me.bin");
57MODULE_FIRMWARE("radeon/RV770_pfp.bin");
58MODULE_FIRMWARE("radeon/RV770_me.bin");
66229b20 59MODULE_FIRMWARE("radeon/RV770_smc.bin");
3ce0a23d
JG		 60MODULE_FIRMWARE("radeon/RV730_pfp.bin");
61MODULE_FIRMWARE("radeon/RV730_me.bin");
66229b20
AD		 62MODULE_FIRMWARE("radeon/RV730_smc.bin");
63MODULE_FIRMWARE("radeon/RV740_smc.bin");
3ce0a23d
JG		 64MODULE_FIRMWARE("radeon/RV710_pfp.bin");
65MODULE_FIRMWARE("radeon/RV710_me.bin");
66229b20 66MODULE_FIRMWARE("radeon/RV710_smc.bin");
d8f60cfc
AD		 67MODULE_FIRMWARE("radeon/R600_rlc.bin");
68MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 69MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
70MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 71MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
dc50ba7f 72MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
fe251e2f
AD		 73MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
74MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 75MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
dc50ba7f 76MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
fe251e2f
AD		 77MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
78MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 79MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
dc50ba7f 80MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
a7433742 81MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 82MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 83MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
dc50ba7f 84MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
439bd6cd
AD		 85MODULE_FIRMWARE("radeon/PALM_pfp.bin");
86MODULE_FIRMWARE("radeon/PALM_me.bin");
87MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
d5c5a72f
AD		 88MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
89MODULE_FIRMWARE("radeon/SUMO_me.bin");
90MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
91MODULE_FIRMWARE("radeon/SUMO2_me.bin");
3ce0a23d 92
f13f7731
AD		 93static const u32 crtc_offsets[2] =
94{
95 0,
96 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
97};
98
3ce0a23d 99int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 100
1a029b76 101/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9 102int r600_mc_wait_for_idle(struct radeon_device *rdev);
1109ca09 103static void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 104void r600_fini(struct radeon_device *rdev);
45f9a39b 105void r600_irq_disable(struct radeon_device *rdev);
9e46a48d 106static void r600_pcie_gen2_enable(struct radeon_device *rdev);
2948f5e6 107extern int evergreen_rlc_resume(struct radeon_device *rdev);
771fe6b9 108
454d2e2a
AD		 109/**
110 * r600_get_xclk - get the xclk
111 *
112 * @rdev: radeon_device pointer
113 *
114 * Returns the reference clock used by the gfx engine
115 * (r6xx, IGPs, APUs).
116 */
117u32 r600_get_xclk(struct radeon_device *rdev)
118{
119 return rdev->clock.spll.reference_freq;
120}
121
1b9ba70a
AD		 122int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
123{
124 return 0;
125}
126
21a8122a 127/* get temperature in millidegrees */
20d391d7 128int rv6xx_get_temp(struct radeon_device *rdev)
21a8122a
AD		 129{
130 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
131 ASIC_T_SHIFT;
20d391d7 132 int actual_temp = temp & 0xff;
21a8122a 133
20d391d7
AD		 134 if (temp & 0x100)
135 actual_temp -= 256;
136
137 return actual_temp * 1000;
21a8122a
AD		 138}
139
ce8f5370 140void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 141{
142 int i;
143
ce8f5370
AD		 144 rdev->pm.dynpm_can_upclock = true;
145 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 146
147 /* power state array is low to high, default is first */
148 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
149 int min_power_state_index = 0;
150
151 if (rdev->pm.num_power_states > 2)
152 min_power_state_index = 1;
153
ce8f5370
AD		 154 switch (rdev->pm.dynpm_planned_action) {
155 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 156 rdev->pm.requested_power_state_index = min_power_state_index;
157 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 158 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 159 break;
ce8f5370 160 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 161 if (rdev->pm.current_power_state_index == min_power_state_index) {
162 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 163 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 164 } else {
165 if (rdev->pm.active_crtc_count > 1) {
166 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 167 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 168 continue;
169 else if (i >= rdev->pm.current_power_state_index) {
170 rdev->pm.requested_power_state_index =
171 rdev->pm.current_power_state_index;
172 break;
173 } else {
174 rdev->pm.requested_power_state_index = i;
175 break;
176 }
177 }
773c3fa3
AD		 178 } else {
179 if (rdev->pm.current_power_state_index == 0)
180 rdev->pm.requested_power_state_index =
181 rdev->pm.num_power_states - 1;
182 else
183 rdev->pm.requested_power_state_index =
184 rdev->pm.current_power_state_index - 1;
185 }
a48b9b4e
AD		 186 }
187 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 188 /* don't use the power state if crtcs are active and no display flag is set */
189 if ((rdev->pm.active_crtc_count > 0) &&
190 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
191 clock_info[rdev->pm.requested_clock_mode_index].flags &
192 RADEON_PM_MODE_NO_DISPLAY)) {
193 rdev->pm.requested_power_state_index++;
194 }
a48b9b4e 195 break;
ce8f5370 196 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 197 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
198 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 199 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 200 } else {
201 if (rdev->pm.active_crtc_count > 1) {
202 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 203 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 204 continue;
205 else if (i <= rdev->pm.current_power_state_index) {
206 rdev->pm.requested_power_state_index =
207 rdev->pm.current_power_state_index;
208 break;
209 } else {
210 rdev->pm.requested_power_state_index = i;
211 break;
212 }
213 }
214 } else
215 rdev->pm.requested_power_state_index =
216 rdev->pm.current_power_state_index + 1;
217 }
218 rdev->pm.requested_clock_mode_index = 0;
219 break;
ce8f5370 220 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 221 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
222 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 223 rdev->pm.dynpm_can_upclock = false;
58e21dff 224 break;
ce8f5370 225 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 226 default:
227 DRM_ERROR("Requested mode for not defined action\n");
228 return;
229 }
230 } else {
231 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
232 /* for now just select the first power state and switch between clock modes */
233 /* power state array is low to high, default is first (0) */
234 if (rdev->pm.active_crtc_count > 1) {
235 rdev->pm.requested_power_state_index = -1;
236 /* start at 1 as we don't want the default mode */
237 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 238 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 239 continue;
240 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
241 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
242 rdev->pm.requested_power_state_index = i;
243 break;
244 }
245 }
246 /* if nothing selected, grab the default state. */
247 if (rdev->pm.requested_power_state_index == -1)
248 rdev->pm.requested_power_state_index = 0;
249 } else
250 rdev->pm.requested_power_state_index = 1;
251
ce8f5370
AD		 252 switch (rdev->pm.dynpm_planned_action) {
253 case DYNPM_ACTION_MINIMUM:
a48b9b4e 254 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 255 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 256 break;
ce8f5370 257 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 258 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
259 if (rdev->pm.current_clock_mode_index == 0) {
260 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 261 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 262 } else
263 rdev->pm.requested_clock_mode_index =
264 rdev->pm.current_clock_mode_index - 1;
265 } else {
266 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 267 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 268 }
d7311171
AD		 269 /* don't use the power state if crtcs are active and no display flag is set */
270 if ((rdev->pm.active_crtc_count > 0) &&
271 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
272 clock_info[rdev->pm.requested_clock_mode_index].flags &
273 RADEON_PM_MODE_NO_DISPLAY)) {
274 rdev->pm.requested_clock_mode_index++;
275 }
a48b9b4e 276 break;
ce8f5370 277 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 278 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
279 if (rdev->pm.current_clock_mode_index ==
280 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
281 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 282 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 283 } else
284 rdev->pm.requested_clock_mode_index =
285 rdev->pm.current_clock_mode_index + 1;
286 } else {
287 rdev->pm.requested_clock_mode_index =
288 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 289 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 290 }
291 break;
ce8f5370 292 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 293 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
294 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 295 rdev->pm.dynpm_can_upclock = false;
58e21dff 296 break;
ce8f5370 297 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 298 default:
299 DRM_ERROR("Requested mode for not defined action\n");
300 return;
301 }
302 }
303
d9fdaafb 304 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 305 rdev->pm.power_state[rdev->pm.requested_power_state_index].
306 clock_info[rdev->pm.requested_clock_mode_index].sclk,
307 rdev->pm.power_state[rdev->pm.requested_power_state_index].
308 clock_info[rdev->pm.requested_clock_mode_index].mclk,
309 rdev->pm.power_state[rdev->pm.requested_power_state_index].
310 pcie_lanes);
a48b9b4e
AD		 311}
312
ce8f5370
AD		 313void rs780_pm_init_profile(struct radeon_device *rdev)
314{
315 if (rdev->pm.num_power_states == 2) {
316 /* default */
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
321 /* low sh */
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 326 /* mid sh */
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 331 /* high sh */
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
336 /* low mh */
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 341 /* mid mh */
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 346 /* high mh */
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
351 } else if (rdev->pm.num_power_states == 3) {
352 /* default */
353 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
354 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
355 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
356 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
357 /* low sh */
358 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
360 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 362 /* mid sh */
363 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
364 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
365 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
366 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 367 /* high sh */
368 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
369 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
370 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
372 /* low mh */
373 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
374 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
375 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 377 /* mid mh */
378 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
379 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
380 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 382 /* high mh */
383 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
384 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
385 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
386 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
387 } else {
388 /* default */
389 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
390 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
391 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
392 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
393 /* low sh */
394 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
395 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
396 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
397 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 398 /* mid sh */
399 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
400 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
401 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
402 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 403 /* high sh */
404 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
405 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
406 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
407 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
408 /* low mh */
409 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
410 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
411 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
412 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 413 /* mid mh */
414 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
415 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
416 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
417 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 418 /* high mh */
419 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
420 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
421 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
422 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
423 }
424}
bae6b562 425
ce8f5370
AD		 426void r600_pm_init_profile(struct radeon_device *rdev)
427{
bbe26ffe
AD		 428 int idx;
429
ce8f5370
AD		 430 if (rdev->family == CHIP_R600) {
431 /* XXX */
432 /* default */
433 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
434 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
435 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 436 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 437 /* low sh */
438 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
439 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
440 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 441 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 442 /* mid sh */
443 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
444 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
445 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
446 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 447 /* high sh */
448 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
449 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 451 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 452 /* low mh */
453 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
454 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
455 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 456 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 457 /* mid mh */
458 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
459 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
460 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
461 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 462 /* high mh */
463 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
464 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
465 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 466 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 467 } else {
468 if (rdev->pm.num_power_states < 4) {
469 /* default */
470 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
471 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
472 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
473 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
474 /* low sh */
4bff5171
AD		 475 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
476 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 477 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 478 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
479 /* mid sh */
480 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
481 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
482 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
483 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 484 /* high sh */
4bff5171
AD		 485 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
486 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 487 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
488 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
489 /* low mh */
4bff5171
AD		 490 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
491 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 492 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 493 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
494 /* low mh */
495 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
496 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
497 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
498 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 499 /* high mh */
4bff5171
AD		 500 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
501 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 502 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
503 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
504 } else {
505 /* default */
506 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
507 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
508 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
509 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
510 /* low sh */
bbe26ffe
AD		 511 if (rdev->flags & RADEON_IS_MOBILITY)
512 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
513 else
514 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
515 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
516 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
517 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
518 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21 519 /* mid sh */
bbe26ffe
AD		 520 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
522 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
523 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 524 /* high sh */
bbe26ffe
AD		 525 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
526 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
527 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 528 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
529 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
530 /* low mh */
bbe26ffe
AD		 531 if (rdev->flags & RADEON_IS_MOBILITY)
532 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
533 else
534 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
535 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
536 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
537 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
538 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21 539 /* mid mh */
bbe26ffe
AD		 540 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
541 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
542 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
543 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 544 /* high mh */
bbe26ffe
AD		 545 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
546 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
547 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 548 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
549 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
550 }
551 }
bae6b562
AD		 552}
553
49e02b73
AD		 554void r600_pm_misc(struct radeon_device *rdev)
555{
a081a9d6
RM		 556 int req_ps_idx = rdev->pm.requested_power_state_index;
557 int req_cm_idx = rdev->pm.requested_clock_mode_index;
558 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
559 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 560
4d60173f 561 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
a377e187
AD		 562 /* 0xff01 is a flag rather then an actual voltage */
563 if (voltage->voltage == 0xff01)
564 return;
4d60173f 565 if (voltage->voltage != rdev->pm.current_vddc) {
8a83ec5e 566 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 567 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 568 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 569 }
570 }
49e02b73
AD		 571}
572
def9ba9c
AD		 573bool r600_gui_idle(struct radeon_device *rdev)
574{
575 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
576 return false;
577 else
578 return true;
579}
580
e0df1ac5
AD		 581/* hpd for digital panel detect/disconnect */
582bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
583{
584 bool connected = false;
585
586 if (ASIC_IS_DCE3(rdev)) {
587 switch (hpd) {
588 case RADEON_HPD_1:
589 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
590 connected = true;
591 break;
592 case RADEON_HPD_2:
593 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
594 connected = true;
595 break;
596 case RADEON_HPD_3:
597 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
598 connected = true;
599 break;
600 case RADEON_HPD_4:
601 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
602 connected = true;
603 break;
604 /* DCE 3.2 */
605 case RADEON_HPD_5:
606 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
607 connected = true;
608 break;
609 case RADEON_HPD_6:
610 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
611 connected = true;
612 break;
613 default:
614 break;
615 }
616 } else {
617 switch (hpd) {
618 case RADEON_HPD_1:
619 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
620 connected = true;
621 break;
622 case RADEON_HPD_2:
623 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
624 connected = true;
625 break;
626 case RADEON_HPD_3:
627 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
628 connected = true;
629 break;
630 default:
631 break;
632 }
633 }
634 return connected;
635}
636
637void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 638 enum radeon_hpd_id hpd)
e0df1ac5
AD		 639{
640 u32 tmp;
641 bool connected = r600_hpd_sense(rdev, hpd);
642
643 if (ASIC_IS_DCE3(rdev)) {
644 switch (hpd) {
645 case RADEON_HPD_1:
646 tmp = RREG32(DC_HPD1_INT_CONTROL);
647 if (connected)
648 tmp &= ~DC_HPDx_INT_POLARITY;
649 else
650 tmp |= DC_HPDx_INT_POLARITY;
651 WREG32(DC_HPD1_INT_CONTROL, tmp);
652 break;
653 case RADEON_HPD_2:
654 tmp = RREG32(DC_HPD2_INT_CONTROL);
655 if (connected)
656 tmp &= ~DC_HPDx_INT_POLARITY;
657 else
658 tmp |= DC_HPDx_INT_POLARITY;
659 WREG32(DC_HPD2_INT_CONTROL, tmp);
660 break;
661 case RADEON_HPD_3:
662 tmp = RREG32(DC_HPD3_INT_CONTROL);
663 if (connected)
664 tmp &= ~DC_HPDx_INT_POLARITY;
665 else
666 tmp |= DC_HPDx_INT_POLARITY;
667 WREG32(DC_HPD3_INT_CONTROL, tmp);
668 break;
669 case RADEON_HPD_4:
670 tmp = RREG32(DC_HPD4_INT_CONTROL);
671 if (connected)
672 tmp &= ~DC_HPDx_INT_POLARITY;
673 else
674 tmp |= DC_HPDx_INT_POLARITY;
675 WREG32(DC_HPD4_INT_CONTROL, tmp);
676 break;
677 case RADEON_HPD_5:
678 tmp = RREG32(DC_HPD5_INT_CONTROL);
679 if (connected)
680 tmp &= ~DC_HPDx_INT_POLARITY;
681 else
682 tmp |= DC_HPDx_INT_POLARITY;
683 WREG32(DC_HPD5_INT_CONTROL, tmp);
684 break;
685 /* DCE 3.2 */
686 case RADEON_HPD_6:
687 tmp = RREG32(DC_HPD6_INT_CONTROL);
688 if (connected)
689 tmp &= ~DC_HPDx_INT_POLARITY;
690 else
691 tmp |= DC_HPDx_INT_POLARITY;
692 WREG32(DC_HPD6_INT_CONTROL, tmp);
693 break;
694 default:
695 break;
696 }
697 } else {
698 switch (hpd) {
699 case RADEON_HPD_1:
700 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
701 if (connected)
702 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
703 else
704 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
705 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
706 break;
707 case RADEON_HPD_2:
708 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
709 if (connected)
710 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
711 else
712 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
713 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
714 break;
715 case RADEON_HPD_3:
716 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
717 if (connected)
718 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
719 else
720 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
721 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
722 break;
723 default:
724 break;
725 }
726 }
727}
728
729void r600_hpd_init(struct radeon_device *rdev)
730{
731 struct drm_device *dev = rdev->ddev;
732 struct drm_connector *connector;
fb98257a 733 unsigned enable = 0;
e0df1ac5 734
64912e99
AD		 735 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
736 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
737
455c89b9
JG		 738 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
739 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
740 /* don't try to enable hpd on eDP or LVDS avoid breaking the
741 * aux dp channel on imac and help (but not completely fix)
742 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
743 */
744 continue;
745 }
64912e99
AD		 746 if (ASIC_IS_DCE3(rdev)) {
747 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
748 if (ASIC_IS_DCE32(rdev))
749 tmp |= DC_HPDx_EN;
e0df1ac5 750
e0df1ac5
AD		 751 switch (radeon_connector->hpd.hpd) {
752 case RADEON_HPD_1:
753 WREG32(DC_HPD1_CONTROL, tmp);
e0df1ac5
AD		 754 break;
755 case RADEON_HPD_2:
756 WREG32(DC_HPD2_CONTROL, tmp);
e0df1ac5
AD		 757 break;
758 case RADEON_HPD_3:
759 WREG32(DC_HPD3_CONTROL, tmp);
e0df1ac5
AD		 760 break;
761 case RADEON_HPD_4:
762 WREG32(DC_HPD4_CONTROL, tmp);
e0df1ac5
AD		 763 break;
764 /* DCE 3.2 */
765 case RADEON_HPD_5:
766 WREG32(DC_HPD5_CONTROL, tmp);
e0df1ac5
AD		 767 break;
768 case RADEON_HPD_6:
769 WREG32(DC_HPD6_CONTROL, tmp);
e0df1ac5
AD		 770 break;
771 default:
772 break;
773 }
64912e99 774 } else {
e0df1ac5
AD		 775 switch (radeon_connector->hpd.hpd) {
776 case RADEON_HPD_1:
777 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 778 break;
779 case RADEON_HPD_2:
780 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 781 break;
782 case RADEON_HPD_3:
783 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
e0df1ac5
AD		 784 break;
785 default:
786 break;
787 }
788 }
fb98257a 789 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 790 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
e0df1ac5 791 }
fb98257a 792 radeon_irq_kms_enable_hpd(rdev, enable);
e0df1ac5
AD		 793}
794
795void r600_hpd_fini(struct radeon_device *rdev)
796{
797 struct drm_device *dev = rdev->ddev;
798 struct drm_connector *connector;
fb98257a 799 unsigned disable = 0;
e0df1ac5 800
fb98257a
CK		 801 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
802 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
803 if (ASIC_IS_DCE3(rdev)) {
e0df1ac5
AD		 804 switch (radeon_connector->hpd.hpd) {
805 case RADEON_HPD_1:
806 WREG32(DC_HPD1_CONTROL, 0);
e0df1ac5
AD		 807 break;
808 case RADEON_HPD_2:
809 WREG32(DC_HPD2_CONTROL, 0);
e0df1ac5
AD		 810 break;
811 case RADEON_HPD_3:
812 WREG32(DC_HPD3_CONTROL, 0);
e0df1ac5
AD		 813 break;
814 case RADEON_HPD_4:
815 WREG32(DC_HPD4_CONTROL, 0);
e0df1ac5
AD		 816 break;
817 /* DCE 3.2 */
818 case RADEON_HPD_5:
819 WREG32(DC_HPD5_CONTROL, 0);
e0df1ac5
AD		 820 break;
821 case RADEON_HPD_6:
822 WREG32(DC_HPD6_CONTROL, 0);
e0df1ac5
AD		 823 break;
824 default:
825 break;
826 }
fb98257a 827 } else {
e0df1ac5
AD		 828 switch (radeon_connector->hpd.hpd) {
829 case RADEON_HPD_1:
830 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
e0df1ac5
AD		 831 break;
832 case RADEON_HPD_2:
833 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
e0df1ac5
AD		 834 break;
835 case RADEON_HPD_3:
836 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
e0df1ac5
AD		 837 break;
838 default:
839 break;
840 }
841 }
fb98257a 842 disable |= 1 << radeon_connector->hpd.hpd;
e0df1ac5 843 }
fb98257a 844 radeon_irq_kms_disable_hpd(rdev, disable);
e0df1ac5
AD		 845}
846
771fe6b9 847/*
3ce0a23d 848 * R600 PCIE GART
771fe6b9 849 */
3ce0a23d
JG		 850void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
851{
852 unsigned i;
853 u32 tmp;
854
2e98f10a 855 /* flush hdp cache so updates hit vram */
f3886f85
AD		 856 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
857 !(rdev->flags & RADEON_IS_AGP)) {
c9a1be96 858 void __iomem *ptr = (void *)rdev->gart.ptr;
812d0469
AD		 859 u32 tmp;
860
861 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
862 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 863 * This seems to cause problems on some AGP cards. Just use the old
864 * method for them.
812d0469
AD		 865 */
866 WREG32(HDP_DEBUG1, 0);
867 tmp = readl((void __iomem *)ptr);
868 } else
869 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 870
3ce0a23d
JG		 871 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
872 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
873 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
874 for (i = 0; i < rdev->usec_timeout; i++) {
875 /* read MC_STATUS */
876 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
877 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
878 if (tmp == 2) {
879 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
880 return;
881 }
882 if (tmp) {
883 return;
884 }
885 udelay(1);
886 }
887}
888
4aac0473 889int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 890{
4aac0473 891 int r;
3ce0a23d 892
c9a1be96 893 if (rdev->gart.robj) {
fce7d61b 894 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 895 return 0;
896 }
3ce0a23d
JG		 897 /* Initialize common gart structure */
898 r = radeon_gart_init(rdev);
4aac0473 899 if (r)
3ce0a23d 900 return r;
3ce0a23d 901 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 902 return radeon_gart_table_vram_alloc(rdev);
903}
904
1109ca09 905static int r600_pcie_gart_enable(struct radeon_device *rdev)
4aac0473
JG		 906{
907 u32 tmp;
908 int r, i;
909
c9a1be96 910 if (rdev->gart.robj == NULL) {
4aac0473
JG		 911 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
912 return -EINVAL;
771fe6b9 913 }
4aac0473
JG		 914 r = radeon_gart_table_vram_pin(rdev);
915 if (r)
916 return r;
82568565 917 radeon_gart_restore(rdev);
bc1a631e 918
3ce0a23d
JG		 919 /* Setup L2 cache */
920 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
921 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
922 EFFECTIVE_L2_QUEUE_SIZE(7));
923 WREG32(VM_L2_CNTL2, 0);
924 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
925 /* Setup TLB control */
926 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
927 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
928 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
929 ENABLE_WAIT_L2_QUERY;
930 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
931 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
932 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
933 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
934 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
935 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
936 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
937 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
938 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
939 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
940 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
941 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
942 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
943 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
944 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 945 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 946 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
947 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
948 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
949 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
950 (u32)(rdev->dummy_page.addr >> 12));
951 for (i = 1; i < 7; i++)
952 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 953
3ce0a23d 954 r600_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 955 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
956 (unsigned)(rdev->mc.gtt_size >> 20),
957 (unsigned long long)rdev->gart.table_addr);
3ce0a23d 958 rdev->gart.ready = true;
771fe6b9
JG		 959 return 0;
960}
961
1109ca09 962static void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 963{
3ce0a23d 964 u32 tmp;
c9a1be96 965 int i;
771fe6b9 966
3ce0a23d
JG		 967 /* Disable all tables */
968 for (i = 0; i < 7; i++)
969 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 970
3ce0a23d
JG		 971 /* Disable L2 cache */
972 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
973 EFFECTIVE_L2_QUEUE_SIZE(7));
974 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
975 /* Setup L1 TLB control */
976 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
977 ENABLE_WAIT_L2_QUERY;
978 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
980 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
981 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
982 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
983 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
984 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
985 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
986 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
987 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
988 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
989 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
990 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
991 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
c9a1be96 992 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 993}
994
1109ca09 995static void r600_pcie_gart_fini(struct radeon_device *rdev)
4aac0473 996{
f9274562 997 radeon_gart_fini(rdev);
4aac0473
JG		 998 r600_pcie_gart_disable(rdev);
999 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 1000}
1001
1109ca09 1002static void r600_agp_enable(struct radeon_device *rdev)
1a029b76
JG		 1003{
1004 u32 tmp;
1005 int i;
1006
1007 /* Setup L2 cache */
1008 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1009 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1010 EFFECTIVE_L2_QUEUE_SIZE(7));
1011 WREG32(VM_L2_CNTL2, 0);
1012 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1013 /* Setup TLB control */
1014 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1015 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1016 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1017 ENABLE_WAIT_L2_QUERY;
1018 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1019 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1020 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1021 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1022 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1023 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1024 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1025 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1026 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1027 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1028 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1029 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1030 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1031 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1032 for (i = 0; i < 7; i++)
1033 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1034}
1035
771fe6b9
JG		 1036int r600_mc_wait_for_idle(struct radeon_device *rdev)
1037{
3ce0a23d
JG		 1038 unsigned i;
1039 u32 tmp;
1040
1041 for (i = 0; i < rdev->usec_timeout; i++) {
1042 /* read MC_STATUS */
1043 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1044 if (!tmp)
1045 return 0;
1046 udelay(1);
1047 }
1048 return -1;
771fe6b9
JG		 1049}
1050
65337e60
SL		 1051uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1052{
0a5b7b0b 1053 unsigned long flags;
65337e60
SL		 1054 uint32_t r;
1055
0a5b7b0b 1056 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
65337e60
SL		 1057 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1058 r = RREG32(R_0028FC_MC_DATA);
1059 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
0a5b7b0b 1060 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
65337e60
SL		 1061 return r;
1062}
1063
1064void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1065{
0a5b7b0b
AD		 1066 unsigned long flags;
1067
1068 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
65337e60
SL		 1069 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1070 S_0028F8_MC_IND_WR_EN(1));
1071 WREG32(R_0028FC_MC_DATA, v);
1072 WREG32(R_0028F8_MC_INDEX, 0x7F);
0a5b7b0b 1073 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
65337e60
SL		 1074}
1075
a3c1945a 1076static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1077{
a3c1945a 1078 struct rv515_mc_save save;
3ce0a23d
JG		 1079 u32 tmp;
1080 int i, j;
771fe6b9 1081
3ce0a23d
JG		 1082 /* Initialize HDP */
1083 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1084 WREG32((0x2c14 + j), 0x00000000);
1085 WREG32((0x2c18 + j), 0x00000000);
1086 WREG32((0x2c1c + j), 0x00000000);
1087 WREG32((0x2c20 + j), 0x00000000);
1088 WREG32((0x2c24 + j), 0x00000000);
1089 }
1090 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1091
a3c1945a 1092 rv515_mc_stop(rdev, &save);
3ce0a23d 1093 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1094 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1095 }
a3c1945a 1096 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1097 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1098 /* Update configuration */
1a029b76
JG		 1099 if (rdev->flags & RADEON_IS_AGP) {
1100 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1101 /* VRAM before AGP */
1102 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1103 rdev->mc.vram_start >> 12);
1104 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1105 rdev->mc.gtt_end >> 12);
1106 } else {
1107 /* VRAM after AGP */
1108 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1109 rdev->mc.gtt_start >> 12);
1110 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1111 rdev->mc.vram_end >> 12);
1112 }
1113 } else {
1114 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1115 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1116 }
16cdf04d 1117 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1a029b76 1118 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1119 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1120 WREG32(MC_VM_FB_LOCATION, tmp);
1121 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1122 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1123 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1124 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1125 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1126 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1127 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1128 } else {
1129 WREG32(MC_VM_AGP_BASE, 0);
1130 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1131 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1132 }
3ce0a23d 1133 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1134 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1135 }
a3c1945a 1136 rv515_mc_resume(rdev, &save);
698443d9
DA		 1137 /* we need to own VRAM, so turn off the VGA renderer here
1138 * to stop it overwriting our objects */
d39c3b89 1139 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1140}
1141
d594e46a
JG		 1142/**
1143 * r600_vram_gtt_location - try to find VRAM & GTT location
1144 * @rdev: radeon device structure holding all necessary informations
1145 * @mc: memory controller structure holding memory informations
1146 *
1147 * Function will place try to place VRAM at same place as in CPU (PCI)
1148 * address space as some GPU seems to have issue when we reprogram at
1149 * different address space.
1150 *
1151 * If there is not enough space to fit the unvisible VRAM after the
1152 * aperture then we limit the VRAM size to the aperture.
1153 *
1154 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1155 * them to be in one from GPU point of view so that we can program GPU to
1156 * catch access outside them (weird GPU policy see ??).
1157 *
1158 * This function will never fails, worst case are limiting VRAM or GTT.
1159 *
1160 * Note: GTT start, end, size should be initialized before calling this
1161 * function on AGP platform.
1162 */
0ef0c1f7 1163static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
d594e46a
JG		 1164{
1165 u64 size_bf, size_af;
1166
1167 if (mc->mc_vram_size > 0xE0000000) {
1168 /* leave room for at least 512M GTT */
1169 dev_warn(rdev->dev, "limiting VRAM\n");
1170 mc->real_vram_size = 0xE0000000;
1171 mc->mc_vram_size = 0xE0000000;
1172 }
1173 if (rdev->flags & RADEON_IS_AGP) {
1174 size_bf = mc->gtt_start;
9ed8b1f9 1175 size_af = mc->mc_mask - mc->gtt_end;
d594e46a
JG		 1176 if (size_bf > size_af) {
1177 if (mc->mc_vram_size > size_bf) {
1178 dev_warn(rdev->dev, "limiting VRAM\n");
1179 mc->real_vram_size = size_bf;
1180 mc->mc_vram_size = size_bf;
1181 }
1182 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1183 } else {
1184 if (mc->mc_vram_size > size_af) {
1185 dev_warn(rdev->dev, "limiting VRAM\n");
1186 mc->real_vram_size = size_af;
1187 mc->mc_vram_size = size_af;
1188 }
dfc6ae5b 1189 mc->vram_start = mc->gtt_end + 1;
d594e46a
JG		 1190 }
1191 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1192 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1193 mc->mc_vram_size >> 20, mc->vram_start,
1194 mc->vram_end, mc->real_vram_size >> 20);
1195 } else {
1196 u64 base = 0;
8961d52d
AD		 1197 if (rdev->flags & RADEON_IS_IGP) {
1198 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1199 base <<= 24;
1200 }
d594e46a 1201 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1202 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1203 radeon_gtt_location(rdev, mc);
1204 }
1205}
1206
1109ca09 1207static int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1208{
3ce0a23d 1209 u32 tmp;
5885b7a9 1210 int chansize, numchan;
65337e60
SL		 1211 uint32_t h_addr, l_addr;
1212 unsigned long long k8_addr;
771fe6b9 1213
3ce0a23d 1214 /* Get VRAM informations */
771fe6b9 1215 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1216 tmp = RREG32(RAMCFG);
1217 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1218 chansize = 16;
3ce0a23d 1219 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1220 chansize = 64;
1221 } else {
1222 chansize = 32;
1223 }
5885b7a9
AD		 1224 tmp = RREG32(CHMAP);
1225 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1226 case 0:
1227 default:
1228 numchan = 1;
1229 break;
1230 case 1:
1231 numchan = 2;
1232 break;
1233 case 2:
1234 numchan = 4;
1235 break;
1236 case 3:
1237 numchan = 8;
1238 break;
771fe6b9 1239 }
5885b7a9 1240 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1241 /* Could aper size report 0 ? */
01d73a69
JC		 1242 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1243 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1244 /* Setup GPU memory space */
1245 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1246 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1247 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1248 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1249
f892034a
AD		 1250 if (rdev->flags & RADEON_IS_IGP) {
1251 rs690_pm_info(rdev);
06b6476d 1252 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
65337e60
SL		 1253
1254 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1255 /* Use K8 direct mapping for fast fb access. */
1256 rdev->fastfb_working = false;
1257 h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1258 l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1259 k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1260#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1261 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1262#endif
1263 {
1264 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1265 * memory is present.
1266 */
1267 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1268 DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1269 (unsigned long long)rdev->mc.aper_base, k8_addr);
1270 rdev->mc.aper_base = (resource_size_t)k8_addr;
1271 rdev->fastfb_working = true;
1272 }
1273 }
1274 }
f892034a 1275 }
65337e60 1276
f47299c5 1277 radeon_update_bandwidth_info(rdev);
3ce0a23d 1278 return 0;
771fe6b9
JG		 1279}
1280
16cdf04d
AD		 1281int r600_vram_scratch_init(struct radeon_device *rdev)
1282{
1283 int r;
1284
1285 if (rdev->vram_scratch.robj == NULL) {
1286 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1287 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
40f5cf99 1288 NULL, &rdev->vram_scratch.robj);
16cdf04d
AD		 1289 if (r) {
1290 return r;
1291 }
1292 }
1293
1294 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1295 if (unlikely(r != 0))
1296 return r;
1297 r = radeon_bo_pin(rdev->vram_scratch.robj,
1298 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1299 if (r) {
1300 radeon_bo_unreserve(rdev->vram_scratch.robj);
1301 return r;
1302 }
1303 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1304 (void **)&rdev->vram_scratch.ptr);
1305 if (r)
1306 radeon_bo_unpin(rdev->vram_scratch.robj);
1307 radeon_bo_unreserve(rdev->vram_scratch.robj);
1308
1309 return r;
1310}
1311
1312void r600_vram_scratch_fini(struct radeon_device *rdev)
1313{
1314 int r;
1315
1316 if (rdev->vram_scratch.robj == NULL) {
1317 return;
1318 }
1319 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1320 if (likely(r == 0)) {
1321 radeon_bo_kunmap(rdev->vram_scratch.robj);
1322 radeon_bo_unpin(rdev->vram_scratch.robj);
1323 radeon_bo_unreserve(rdev->vram_scratch.robj);
1324 }
1325 radeon_bo_unref(&rdev->vram_scratch.robj);
1326}
1327
410a3418
AD		 1328void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1329{
1330 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1331
1332 if (hung)
1333 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1334 else
1335 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1336
1337 WREG32(R600_BIOS_3_SCRATCH, tmp);
1338}
1339
d3cb781e 1340static void r600_print_gpu_status_regs(struct radeon_device *rdev)
771fe6b9 1341{
64c56e8c 1342 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
d3cb781e 1343 RREG32(R_008010_GRBM_STATUS));
64c56e8c 1344 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
d3cb781e 1345 RREG32(R_008014_GRBM_STATUS2));
64c56e8c 1346 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
d3cb781e 1347 RREG32(R_000E50_SRBM_STATUS));
440a7cd8 1348 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
d3cb781e 1349 RREG32(CP_STALLED_STAT1));
440a7cd8 1350 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
d3cb781e 1351 RREG32(CP_STALLED_STAT2));
440a7cd8 1352 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
d3cb781e 1353 RREG32(CP_BUSY_STAT));
440a7cd8 1354 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
d3cb781e 1355 RREG32(CP_STAT));
71e3d157
AD		 1356 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1357 RREG32(DMA_STATUS_REG));
1358}
1359
f13f7731 1360static bool r600_is_display_hung(struct radeon_device *rdev)
71e3d157 1361{
f13f7731
AD		 1362 u32 crtc_hung = 0;
1363 u32 crtc_status[2];
1364 u32 i, j, tmp;
1365
1366 for (i = 0; i < rdev->num_crtc; i++) {
1367 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1368 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1369 crtc_hung |= (1 << i);
1370 }
1371 }
1372
1373 for (j = 0; j < 10; j++) {
1374 for (i = 0; i < rdev->num_crtc; i++) {
1375 if (crtc_hung & (1 << i)) {
1376 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1377 if (tmp != crtc_status[i])
1378 crtc_hung &= ~(1 << i);
1379 }
1380 }
1381 if (crtc_hung == 0)
1382 return false;
1383 udelay(100);
1384 }
1385
1386 return true;
1387}
1388
2483b4ea 1389u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
f13f7731
AD		 1390{
1391 u32 reset_mask = 0;
d3cb781e 1392 u32 tmp;
71e3d157 1393
f13f7731
AD		 1394 /* GRBM_STATUS */
1395 tmp = RREG32(R_008010_GRBM_STATUS);
1396 if (rdev->family >= CHIP_RV770) {
1397 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1398 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1399 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1400 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1401 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1402 reset_mask |= RADEON_RESET_GFX;
1403 } else {
1404 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1405 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1406 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1407 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1408 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1409 reset_mask |= RADEON_RESET_GFX;
1410 }
1411
1412 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1413 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1414 reset_mask |= RADEON_RESET_CP;
1415
1416 if (G_008010_GRBM_EE_BUSY(tmp))
1417 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1418
1419 /* DMA_STATUS_REG */
1420 tmp = RREG32(DMA_STATUS_REG);
1421 if (!(tmp & DMA_IDLE))
1422 reset_mask |= RADEON_RESET_DMA;
1423
1424 /* SRBM_STATUS */
1425 tmp = RREG32(R_000E50_SRBM_STATUS);
1426 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1427 reset_mask |= RADEON_RESET_RLC;
1428
1429 if (G_000E50_IH_BUSY(tmp))
1430 reset_mask |= RADEON_RESET_IH;
1431
1432 if (G_000E50_SEM_BUSY(tmp))
1433 reset_mask |= RADEON_RESET_SEM;
19fc42ed 1434
f13f7731
AD		 1435 if (G_000E50_GRBM_RQ_PENDING(tmp))
1436 reset_mask |= RADEON_RESET_GRBM;
1437
1438 if (G_000E50_VMC_BUSY(tmp))
1439 reset_mask |= RADEON_RESET_VMC;
1440
1441 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1442 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1443 G_000E50_MCDW_BUSY(tmp))
1444 reset_mask |= RADEON_RESET_MC;
1445
1446 if (r600_is_display_hung(rdev))
1447 reset_mask |= RADEON_RESET_DISPLAY;
1448
d808fc88
AD		 1449 /* Skip MC reset as it's mostly likely not hung, just busy */
1450 if (reset_mask & RADEON_RESET_MC) {
1451 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1452 reset_mask &= ~RADEON_RESET_MC;
1453 }
1454
f13f7731
AD		 1455 return reset_mask;
1456}
1457
1458static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1459{
1460 struct rv515_mc_save save;
1461 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1462 u32 tmp;
19fc42ed 1463
71e3d157 1464 if (reset_mask == 0)
f13f7731 1465 return;
71e3d157
AD		 1466
1467 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1468
d3cb781e
AD		 1469 r600_print_gpu_status_regs(rdev);
1470
d3cb781e
AD		 1471 /* Disable CP parsing/prefetching */
1472 if (rdev->family >= CHIP_RV770)
1473 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1474 else
1475 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1476
1477 /* disable the RLC */
1478 WREG32(RLC_CNTL, 0);
1479
1480 if (reset_mask & RADEON_RESET_DMA) {
1481 /* Disable DMA */
1482 tmp = RREG32(DMA_RB_CNTL);
1483 tmp &= ~DMA_RB_ENABLE;
1484 WREG32(DMA_RB_CNTL, tmp);
1485 }
1486
1487 mdelay(50);
1488
ca57802e
AD		 1489 rv515_mc_stop(rdev, &save);
1490 if (r600_mc_wait_for_idle(rdev)) {
1491 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1492 }
1493
d3cb781e
AD		 1494 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1495 if (rdev->family >= CHIP_RV770)
1496 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1497 S_008020_SOFT_RESET_CB(1) |
1498 S_008020_SOFT_RESET_PA(1) |
1499 S_008020_SOFT_RESET_SC(1) |
1500 S_008020_SOFT_RESET_SPI(1) |
1501 S_008020_SOFT_RESET_SX(1) |
1502 S_008020_SOFT_RESET_SH(1) |
1503 S_008020_SOFT_RESET_TC(1) |
1504 S_008020_SOFT_RESET_TA(1) |
1505 S_008020_SOFT_RESET_VC(1) |
1506 S_008020_SOFT_RESET_VGT(1);
1507 else
1508 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1509 S_008020_SOFT_RESET_DB(1) |
1510 S_008020_SOFT_RESET_CB(1) |
1511 S_008020_SOFT_RESET_PA(1) |
1512 S_008020_SOFT_RESET_SC(1) |
1513 S_008020_SOFT_RESET_SMX(1) |
1514 S_008020_SOFT_RESET_SPI(1) |
1515 S_008020_SOFT_RESET_SX(1) |
1516 S_008020_SOFT_RESET_SH(1) |
1517 S_008020_SOFT_RESET_TC(1) |
1518 S_008020_SOFT_RESET_TA(1) |
1519 S_008020_SOFT_RESET_VC(1) |
1520 S_008020_SOFT_RESET_VGT(1);
1521 }
1522
1523 if (reset_mask & RADEON_RESET_CP) {
1524 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1525 S_008020_SOFT_RESET_VGT(1);
1526
1527 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1528 }
1529
1530 if (reset_mask & RADEON_RESET_DMA) {
1531 if (rdev->family >= CHIP_RV770)
1532 srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1533 else
1534 srbm_soft_reset |= SOFT_RESET_DMA;
1535 }
1536
f13f7731
AD		 1537 if (reset_mask & RADEON_RESET_RLC)
1538 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1539
1540 if (reset_mask & RADEON_RESET_SEM)
1541 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1542
1543 if (reset_mask & RADEON_RESET_IH)
1544 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1545
1546 if (reset_mask & RADEON_RESET_GRBM)
1547 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1548
24178ec4
AD		 1549 if (!(rdev->flags & RADEON_IS_IGP)) {
1550 if (reset_mask & RADEON_RESET_MC)
1551 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1552 }
f13f7731
AD		 1553
1554 if (reset_mask & RADEON_RESET_VMC)
1555 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1556
d3cb781e
AD		 1557 if (grbm_soft_reset) {
1558 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1559 tmp |= grbm_soft_reset;
1560 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1561 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1562 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1563
1564 udelay(50);
1565
1566 tmp &= ~grbm_soft_reset;
1567 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1568 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1569 }
1570
1571 if (srbm_soft_reset) {
1572 tmp = RREG32(SRBM_SOFT_RESET);
1573 tmp |= srbm_soft_reset;
1574 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1575 WREG32(SRBM_SOFT_RESET, tmp);
1576 tmp = RREG32(SRBM_SOFT_RESET);
1577
1578 udelay(50);
71e3d157 1579
d3cb781e
AD		 1580 tmp &= ~srbm_soft_reset;
1581 WREG32(SRBM_SOFT_RESET, tmp);
1582 tmp = RREG32(SRBM_SOFT_RESET);
1583 }
71e3d157
AD		 1584
1585 /* Wait a little for things to settle down */
1586 mdelay(1);
1587
a3c1945a 1588 rv515_mc_resume(rdev, &save);
d3cb781e 1589 udelay(50);
410a3418 1590
d3cb781e 1591 r600_print_gpu_status_regs(rdev);
d3cb781e
AD		 1592}
1593
1594int r600_asic_reset(struct radeon_device *rdev)
1595{
f13f7731
AD		 1596 u32 reset_mask;
1597
1598 reset_mask = r600_gpu_check_soft_reset(rdev);
1599
1600 if (reset_mask)
1601 r600_set_bios_scratch_engine_hung(rdev, true);
1602
1603 r600_gpu_soft_reset(rdev, reset_mask);
1604
1605 reset_mask = r600_gpu_check_soft_reset(rdev);
1606
1607 if (!reset_mask)
1608 r600_set_bios_scratch_engine_hung(rdev, false);
1609
1610 return 0;
3ce0a23d
JG		 1611}
1612
123bc183
AD		 1613/**
1614 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1615 *
1616 * @rdev: radeon_device pointer
1617 * @ring: radeon_ring structure holding ring information
1618 *
1619 * Check if the GFX engine is locked up.
1620 * Returns true if the engine appears to be locked up, false if not.
1621 */
1622bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8 1623{
123bc183
AD		 1624 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1625
1626 if (!(reset_mask & (RADEON_RESET_GFX |
1627 RADEON_RESET_COMPUTE |
1628 RADEON_RESET_CP))) {
069211e5 1629 radeon_ring_lockup_update(ring);
225758d8
JG		 1630 return false;
1631 }
1632 /* force CP activities */
7b9ef16b 1633 radeon_ring_force_activity(rdev, ring);
069211e5 1634 return radeon_ring_test_lockup(rdev, ring);
225758d8
JG		 1635}
1636
416a2bd2
AD		 1637u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1638 u32 tiling_pipe_num,
1639 u32 max_rb_num,
1640 u32 total_max_rb_num,
1641 u32 disabled_rb_mask)
3ce0a23d 1642{
416a2bd2 1643 u32 rendering_pipe_num, rb_num_width, req_rb_num;
f689e3ac 1644 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
416a2bd2
AD		 1645 u32 data = 0, mask = 1 << (max_rb_num - 1);
1646 unsigned i, j;
3ce0a23d 1647
416a2bd2 1648 /* mask out the RBs that don't exist on that asic */
f689e3ac
MT		 1649 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1650 /* make sure at least one RB is available */
1651 if ((tmp & 0xff) != 0xff)
1652 disabled_rb_mask = tmp;
3ce0a23d 1653
416a2bd2
AD		 1654 rendering_pipe_num = 1 << tiling_pipe_num;
1655 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1656 BUG_ON(rendering_pipe_num < req_rb_num);
3ce0a23d 1657
416a2bd2
AD		 1658 pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1659 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
3ce0a23d 1660
416a2bd2
AD		 1661 if (rdev->family <= CHIP_RV740) {
1662 /* r6xx/r7xx */
1663 rb_num_width = 2;
1664 } else {
1665 /* eg+ */
1666 rb_num_width = 4;
1667 }
3ce0a23d 1668
416a2bd2
AD		 1669 for (i = 0; i < max_rb_num; i++) {
1670 if (!(mask & disabled_rb_mask)) {
1671 for (j = 0; j < pipe_rb_ratio; j++) {
1672 data <<= rb_num_width;
1673 data |= max_rb_num - i - 1;
1674 }
1675 if (pipe_rb_remain) {
1676 data <<= rb_num_width;
1677 data |= max_rb_num - i - 1;
1678 pipe_rb_remain--;
1679 }
1680 }
1681 mask >>= 1;
3ce0a23d
JG		 1682 }
1683
416a2bd2 1684 return data;
3ce0a23d
JG		 1685}
1686
1687int r600_count_pipe_bits(uint32_t val)
1688{
ef8cf3a1 1689 return hweight32(val);
771fe6b9
JG		 1690}
1691
1109ca09 1692static void r600_gpu_init(struct radeon_device *rdev)
3ce0a23d
JG		 1693{
1694 u32 tiling_config;
1695 u32 ramcfg;
d03f5d59
AD		 1696 u32 cc_rb_backend_disable;
1697 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1698 u32 tmp;
1699 int i, j;
1700 u32 sq_config;
1701 u32 sq_gpr_resource_mgmt_1 = 0;
1702 u32 sq_gpr_resource_mgmt_2 = 0;
1703 u32 sq_thread_resource_mgmt = 0;
1704 u32 sq_stack_resource_mgmt_1 = 0;
1705 u32 sq_stack_resource_mgmt_2 = 0;
416a2bd2 1706 u32 disabled_rb_mask;
3ce0a23d 1707
416a2bd2 1708 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1709 switch (rdev->family) {
1710 case CHIP_R600:
1711 rdev->config.r600.max_pipes = 4;
1712 rdev->config.r600.max_tile_pipes = 8;
1713 rdev->config.r600.max_simds = 4;
1714 rdev->config.r600.max_backends = 4;
1715 rdev->config.r600.max_gprs = 256;
1716 rdev->config.r600.max_threads = 192;
1717 rdev->config.r600.max_stack_entries = 256;
1718 rdev->config.r600.max_hw_contexts = 8;
1719 rdev->config.r600.max_gs_threads = 16;
1720 rdev->config.r600.sx_max_export_size = 128;
1721 rdev->config.r600.sx_max_export_pos_size = 16;
1722 rdev->config.r600.sx_max_export_smx_size = 128;
1723 rdev->config.r600.sq_num_cf_insts = 2;
1724 break;
1725 case CHIP_RV630:
1726 case CHIP_RV635:
1727 rdev->config.r600.max_pipes = 2;
1728 rdev->config.r600.max_tile_pipes = 2;
1729 rdev->config.r600.max_simds = 3;
1730 rdev->config.r600.max_backends = 1;
1731 rdev->config.r600.max_gprs = 128;
1732 rdev->config.r600.max_threads = 192;
1733 rdev->config.r600.max_stack_entries = 128;
1734 rdev->config.r600.max_hw_contexts = 8;
1735 rdev->config.r600.max_gs_threads = 4;
1736 rdev->config.r600.sx_max_export_size = 128;
1737 rdev->config.r600.sx_max_export_pos_size = 16;
1738 rdev->config.r600.sx_max_export_smx_size = 128;
1739 rdev->config.r600.sq_num_cf_insts = 2;
1740 break;
1741 case CHIP_RV610:
1742 case CHIP_RV620:
1743 case CHIP_RS780:
1744 case CHIP_RS880:
1745 rdev->config.r600.max_pipes = 1;
1746 rdev->config.r600.max_tile_pipes = 1;
1747 rdev->config.r600.max_simds = 2;
1748 rdev->config.r600.max_backends = 1;
1749 rdev->config.r600.max_gprs = 128;
1750 rdev->config.r600.max_threads = 192;
1751 rdev->config.r600.max_stack_entries = 128;
1752 rdev->config.r600.max_hw_contexts = 4;
1753 rdev->config.r600.max_gs_threads = 4;
1754 rdev->config.r600.sx_max_export_size = 128;
1755 rdev->config.r600.sx_max_export_pos_size = 16;
1756 rdev->config.r600.sx_max_export_smx_size = 128;
1757 rdev->config.r600.sq_num_cf_insts = 1;
1758 break;
1759 case CHIP_RV670:
1760 rdev->config.r600.max_pipes = 4;
1761 rdev->config.r600.max_tile_pipes = 4;
1762 rdev->config.r600.max_simds = 4;
1763 rdev->config.r600.max_backends = 4;
1764 rdev->config.r600.max_gprs = 192;
1765 rdev->config.r600.max_threads = 192;
1766 rdev->config.r600.max_stack_entries = 256;
1767 rdev->config.r600.max_hw_contexts = 8;
1768 rdev->config.r600.max_gs_threads = 16;
1769 rdev->config.r600.sx_max_export_size = 128;
1770 rdev->config.r600.sx_max_export_pos_size = 16;
1771 rdev->config.r600.sx_max_export_smx_size = 128;
1772 rdev->config.r600.sq_num_cf_insts = 2;
1773 break;
1774 default:
1775 break;
1776 }
1777
1778 /* Initialize HDP */
1779 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1780 WREG32((0x2c14 + j), 0x00000000);
1781 WREG32((0x2c18 + j), 0x00000000);
1782 WREG32((0x2c1c + j), 0x00000000);
1783 WREG32((0x2c20 + j), 0x00000000);
1784 WREG32((0x2c24 + j), 0x00000000);
1785 }
1786
1787 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1788
1789 /* Setup tiling */
1790 tiling_config = 0;
1791 ramcfg = RREG32(RAMCFG);
1792 switch (rdev->config.r600.max_tile_pipes) {
1793 case 1:
1794 tiling_config |= PIPE_TILING(0);
1795 break;
1796 case 2:
1797 tiling_config |= PIPE_TILING(1);
1798 break;
1799 case 4:
1800 tiling_config |= PIPE_TILING(2);
1801 break;
1802 case 8:
1803 tiling_config |= PIPE_TILING(3);
1804 break;
1805 default:
1806 break;
1807 }
d03f5d59 1808 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1809 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 1810 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1 1811 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
416a2bd2 1812
3ce0a23d
JG		 1813 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1814 if (tmp > 3) {
1815 tiling_config |= ROW_TILING(3);
1816 tiling_config |= SAMPLE_SPLIT(3);
1817 } else {
1818 tiling_config |= ROW_TILING(tmp);
1819 tiling_config |= SAMPLE_SPLIT(tmp);
1820 }
1821 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1822
1823 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
416a2bd2
AD		 1824 tmp = R6XX_MAX_BACKENDS -
1825 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1826 if (tmp < rdev->config.r600.max_backends) {
1827 rdev->config.r600.max_backends = tmp;
1828 }
1829
1830 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1831 tmp = R6XX_MAX_PIPES -
1832 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1833 if (tmp < rdev->config.r600.max_pipes) {
1834 rdev->config.r600.max_pipes = tmp;
1835 }
1836 tmp = R6XX_MAX_SIMDS -
1837 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1838 if (tmp < rdev->config.r600.max_simds) {
1839 rdev->config.r600.max_simds = tmp;
1840 }
1841
1842 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1843 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1844 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1845 R6XX_MAX_BACKENDS, disabled_rb_mask);
1846 tiling_config |= tmp << 16;
1847 rdev->config.r600.backend_map = tmp;
1848
e7aeeba6 1849 rdev->config.r600.tile_config = tiling_config;
3ce0a23d
JG		 1850 WREG32(GB_TILING_CONFIG, tiling_config);
1851 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1852 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
4d75658b 1853 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
3ce0a23d 1854
d03f5d59 1855 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1856 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1857 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1858
1859 /* Setup some CP states */
1860 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1861 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1862
1863 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1864 SYNC_WALKER | SYNC_ALIGNER));
1865 /* Setup various GPU states */
1866 if (rdev->family == CHIP_RV670)
1867 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1868
1869 tmp = RREG32(SX_DEBUG_1);
1870 tmp |= SMX_EVENT_RELEASE;
1871 if ((rdev->family > CHIP_R600))
1872 tmp |= ENABLE_NEW_SMX_ADDRESS;
1873 WREG32(SX_DEBUG_1, tmp);
1874
1875 if (((rdev->family) == CHIP_R600) ||
1876 ((rdev->family) == CHIP_RV630) ||
1877 ((rdev->family) == CHIP_RV610) ||
1878 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1879 ((rdev->family) == CHIP_RS780) ||
1880 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1881 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1882 } else {
1883 WREG32(DB_DEBUG, 0);
1884 }
1885 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1886 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1887
1888 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1889 WREG32(VGT_NUM_INSTANCES, 0);
1890
1891 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1892 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1893
1894 tmp = RREG32(SQ_MS_FIFO_SIZES);
1895 if (((rdev->family) == CHIP_RV610) ||
1896 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1897 ((rdev->family) == CHIP_RS780) ||
1898 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1899 tmp = (CACHE_FIFO_SIZE(0xa) |
1900 FETCH_FIFO_HIWATER(0xa) |
1901 DONE_FIFO_HIWATER(0xe0) |
1902 ALU_UPDATE_FIFO_HIWATER(0x8));
1903 } else if (((rdev->family) == CHIP_R600) ||
1904 ((rdev->family) == CHIP_RV630)) {
1905 tmp &= ~DONE_FIFO_HIWATER(0xff);
1906 tmp |= DONE_FIFO_HIWATER(0x4);
1907 }
1908 WREG32(SQ_MS_FIFO_SIZES, tmp);
1909
1910 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1911 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1912 */
1913 sq_config = RREG32(SQ_CONFIG);
1914 sq_config &= ~(PS_PRIO(3) |
1915 VS_PRIO(3) |
1916 GS_PRIO(3) |
1917 ES_PRIO(3));
1918 sq_config |= (DX9_CONSTS |
1919 VC_ENABLE |
1920 PS_PRIO(0) |
1921 VS_PRIO(1) |
1922 GS_PRIO(2) |
1923 ES_PRIO(3));
1924
1925 if ((rdev->family) == CHIP_R600) {
1926 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1927 NUM_VS_GPRS(124) |
1928 NUM_CLAUSE_TEMP_GPRS(4));
1929 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1930 NUM_ES_GPRS(0));
1931 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1932 NUM_VS_THREADS(48) |
1933 NUM_GS_THREADS(4) |
1934 NUM_ES_THREADS(4));
1935 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1936 NUM_VS_STACK_ENTRIES(128));
1937 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1938 NUM_ES_STACK_ENTRIES(0));
1939 } else if (((rdev->family) == CHIP_RV610) ||
1940 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1941 ((rdev->family) == CHIP_RS780) ||
1942 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1943 /* no vertex cache */
1944 sq_config &= ~VC_ENABLE;
1945
1946 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1947 NUM_VS_GPRS(44) |
1948 NUM_CLAUSE_TEMP_GPRS(2));
1949 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1950 NUM_ES_GPRS(17));
1951 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1952 NUM_VS_THREADS(78) |
1953 NUM_GS_THREADS(4) |
1954 NUM_ES_THREADS(31));
1955 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1956 NUM_VS_STACK_ENTRIES(40));
1957 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1958 NUM_ES_STACK_ENTRIES(16));
1959 } else if (((rdev->family) == CHIP_RV630) ||
1960 ((rdev->family) == CHIP_RV635)) {
1961 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1962 NUM_VS_GPRS(44) |
1963 NUM_CLAUSE_TEMP_GPRS(2));
1964 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1965 NUM_ES_GPRS(18));
1966 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1967 NUM_VS_THREADS(78) |
1968 NUM_GS_THREADS(4) |
1969 NUM_ES_THREADS(31));
1970 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1971 NUM_VS_STACK_ENTRIES(40));
1972 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1973 NUM_ES_STACK_ENTRIES(16));
1974 } else if ((rdev->family) == CHIP_RV670) {
1975 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1976 NUM_VS_GPRS(44) |
1977 NUM_CLAUSE_TEMP_GPRS(2));
1978 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1979 NUM_ES_GPRS(17));
1980 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1981 NUM_VS_THREADS(78) |
1982 NUM_GS_THREADS(4) |
1983 NUM_ES_THREADS(31));
1984 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1985 NUM_VS_STACK_ENTRIES(64));
1986 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1987 NUM_ES_STACK_ENTRIES(64));
1988 }
1989
1990 WREG32(SQ_CONFIG, sq_config);
1991 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1992 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1993 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1994 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1995 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1996
1997 if (((rdev->family) == CHIP_RV610) ||
1998 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1999 ((rdev->family) == CHIP_RS780) ||
2000 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 2001 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2002 } else {
2003 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2004 }
2005
2006 /* More default values. 2D/3D driver should adjust as needed */
2007 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2008 S1_X(0x4) | S1_Y(0xc)));
2009 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2010 S1_X(0x2) | S1_Y(0x2) |
2011 S2_X(0xa) | S2_Y(0x6) |
2012 S3_X(0x6) | S3_Y(0xa)));
2013 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2014 S1_X(0x4) | S1_Y(0xc) |
2015 S2_X(0x1) | S2_Y(0x6) |
2016 S3_X(0xa) | S3_Y(0xe)));
2017 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2018 S5_X(0x0) | S5_Y(0x0) |
2019 S6_X(0xb) | S6_Y(0x4) |
2020 S7_X(0x7) | S7_Y(0x8)));
2021
2022 WREG32(VGT_STRMOUT_EN, 0);
2023 tmp = rdev->config.r600.max_pipes * 16;
2024 switch (rdev->family) {
2025 case CHIP_RV610:
3ce0a23d 2026 case CHIP_RV620:
ee59f2b4
AD		 2027 case CHIP_RS780:
2028 case CHIP_RS880:
3ce0a23d
JG		 2029 tmp += 32;
2030 break;
2031 case CHIP_RV670:
2032 tmp += 128;
2033 break;
2034 default:
2035 break;
2036 }
2037 if (tmp > 256) {
2038 tmp = 256;
2039 }
2040 WREG32(VGT_ES_PER_GS, 128);
2041 WREG32(VGT_GS_PER_ES, tmp);
2042 WREG32(VGT_GS_PER_VS, 2);
2043 WREG32(VGT_GS_VERTEX_REUSE, 16);
2044
2045 /* more default values. 2D/3D driver should adjust as needed */
2046 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2047 WREG32(VGT_STRMOUT_EN, 0);
2048 WREG32(SX_MISC, 0);
2049 WREG32(PA_SC_MODE_CNTL, 0);
2050 WREG32(PA_SC_AA_CONFIG, 0);
2051 WREG32(PA_SC_LINE_STIPPLE, 0);
2052 WREG32(SPI_INPUT_Z, 0);
2053 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2054 WREG32(CB_COLOR7_FRAG, 0);
2055
2056 /* Clear render buffer base addresses */
2057 WREG32(CB_COLOR0_BASE, 0);
2058 WREG32(CB_COLOR1_BASE, 0);
2059 WREG32(CB_COLOR2_BASE, 0);
2060 WREG32(CB_COLOR3_BASE, 0);
2061 WREG32(CB_COLOR4_BASE, 0);
2062 WREG32(CB_COLOR5_BASE, 0);
2063 WREG32(CB_COLOR6_BASE, 0);
2064 WREG32(CB_COLOR7_BASE, 0);
2065 WREG32(CB_COLOR7_FRAG, 0);
2066
2067 switch (rdev->family) {
2068 case CHIP_RV610:
3ce0a23d 2069 case CHIP_RV620:
ee59f2b4
AD		 2070 case CHIP_RS780:
2071 case CHIP_RS880:
3ce0a23d
JG		 2072 tmp = TC_L2_SIZE(8);
2073 break;
2074 case CHIP_RV630:
2075 case CHIP_RV635:
2076 tmp = TC_L2_SIZE(4);
2077 break;
2078 case CHIP_R600:
2079 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2080 break;
2081 default:
2082 tmp = TC_L2_SIZE(0);
2083 break;
2084 }
2085 WREG32(TC_CNTL, tmp);
2086
2087 tmp = RREG32(HDP_HOST_PATH_CNTL);
2088 WREG32(HDP_HOST_PATH_CNTL, tmp);
2089
2090 tmp = RREG32(ARB_POP);
2091 tmp |= ENABLE_TC128;
2092 WREG32(ARB_POP, tmp);
2093
2094 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2095 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2096 NUM_CLIP_SEQ(3)));
2097 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
b866d133 2098 WREG32(VC_ENHANCE, 0);
3ce0a23d
JG		 2099}
2100
2101
771fe6b9
JG		 2102/*
2103 * Indirect registers accessor
2104 */
3ce0a23d
JG		 2105u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2106{
0a5b7b0b 2107 unsigned long flags;
3ce0a23d
JG		 2108 u32 r;
2109
0a5b7b0b 2110 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2111 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2112 (void)RREG32(PCIE_PORT_INDEX);
2113 r = RREG32(PCIE_PORT_DATA);
0a5b7b0b 2114 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2115 return r;
2116}
2117
2118void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2119{
0a5b7b0b
AD		 2120 unsigned long flags;
2121
2122 spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2123 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2124 (void)RREG32(PCIE_PORT_INDEX);
2125 WREG32(PCIE_PORT_DATA, (v));
2126 (void)RREG32(PCIE_PORT_DATA);
0a5b7b0b 2127 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
3ce0a23d
JG		 2128}
2129
3ce0a23d
JG		 2130/*
2131 * CP & Ring
2132 */
2133void r600_cp_stop(struct radeon_device *rdev)
2134{
53595338 2135 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3ce0a23d 2136 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 2137 WREG32(SCRATCH_UMSK, 0);
4d75658b 2138 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3ce0a23d
JG		 2139}
2140
d8f60cfc 2141int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d 2142{
3ce0a23d 2143 const char *chip_name;
d8f60cfc 2144 const char *rlc_chip_name;
66229b20
AD		 2145 const char *smc_chip_name = "RV770";
2146 size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
3ce0a23d
JG		 2147 char fw_name[30];
2148 int err;
2149
2150 DRM_DEBUG("\n");
2151
3ce0a23d 2152 switch (rdev->family) {
d8f60cfc
AD		 2153 case CHIP_R600:
2154 chip_name = "R600";
2155 rlc_chip_name = "R600";
2156 break;
2157 case CHIP_RV610:
2158 chip_name = "RV610";
2159 rlc_chip_name = "R600";
2160 break;
2161 case CHIP_RV630:
2162 chip_name = "RV630";
2163 rlc_chip_name = "R600";
2164 break;
2165 case CHIP_RV620:
2166 chip_name = "RV620";
2167 rlc_chip_name = "R600";
2168 break;
2169 case CHIP_RV635:
2170 chip_name = "RV635";
2171 rlc_chip_name = "R600";
2172 break;
2173 case CHIP_RV670:
2174 chip_name = "RV670";
2175 rlc_chip_name = "R600";
2176 break;
3ce0a23d 2177 case CHIP_RS780:
d8f60cfc
AD		 2178 case CHIP_RS880:
2179 chip_name = "RS780";
2180 rlc_chip_name = "R600";
2181 break;
2182 case CHIP_RV770:
2183 chip_name = "RV770";
2184 rlc_chip_name = "R700";
66229b20
AD		 2185 smc_chip_name = "RV770";
2186 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
d8f60cfc 2187 break;
3ce0a23d 2188 case CHIP_RV730:
d8f60cfc
AD		 2189 chip_name = "RV730";
2190 rlc_chip_name = "R700";
66229b20
AD		 2191 smc_chip_name = "RV730";
2192 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
d8f60cfc
AD		 2193 break;
2194 case CHIP_RV710:
2195 chip_name = "RV710";
2196 rlc_chip_name = "R700";
66229b20
AD		 2197 smc_chip_name = "RV710";
2198 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2199 break;
2200 case CHIP_RV740:
2201 chip_name = "RV730";
2202 rlc_chip_name = "R700";
2203 smc_chip_name = "RV740";
2204 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
d8f60cfc 2205 break;
fe251e2f
AD		 2206 case CHIP_CEDAR:
2207 chip_name = "CEDAR";
45f9a39b 2208 rlc_chip_name = "CEDAR";
dc50ba7f
AD		 2209 smc_chip_name = "CEDAR";
2210 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2211 break;
2212 case CHIP_REDWOOD:
2213 chip_name = "REDWOOD";
45f9a39b 2214 rlc_chip_name = "REDWOOD";
dc50ba7f
AD		 2215 smc_chip_name = "REDWOOD";
2216 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2217 break;
2218 case CHIP_JUNIPER:
2219 chip_name = "JUNIPER";
45f9a39b 2220 rlc_chip_name = "JUNIPER";
dc50ba7f
AD		 2221 smc_chip_name = "JUNIPER";
2222 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
fe251e2f
AD		 2223 break;
2224 case CHIP_CYPRESS:
2225 case CHIP_HEMLOCK:
2226 chip_name = "CYPRESS";
45f9a39b 2227 rlc_chip_name = "CYPRESS";
dc50ba7f
AD		 2228 smc_chip_name = "CYPRESS";
2229 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
fe251e2f 2230 break;
439bd6cd
AD		 2231 case CHIP_PALM:
2232 chip_name = "PALM";
2233 rlc_chip_name = "SUMO";
2234 break;
d5c5a72f
AD		 2235 case CHIP_SUMO:
2236 chip_name = "SUMO";
2237 rlc_chip_name = "SUMO";
2238 break;
2239 case CHIP_SUMO2:
2240 chip_name = "SUMO2";
2241 rlc_chip_name = "SUMO";
2242 break;
3ce0a23d
JG		 2243 default: BUG();
2244 }
2245
fe251e2f
AD		 2246 if (rdev->family >= CHIP_CEDAR) {
2247 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2248 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2249 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2250 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2251 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2252 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2253 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d 2254 } else {
138e4e16
AD		 2255 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2256 me_req_size = R600_PM4_UCODE_SIZE * 12;
2257 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2258 }
2259
d8f60cfc 2260 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2261
2262 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
0a168933 2263 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
3ce0a23d
JG		 2264 if (err)
2265 goto out;
2266 if (rdev->pfp_fw->size != pfp_req_size) {
2267 printk(KERN_ERR
2268 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2269 rdev->pfp_fw->size, fw_name);
2270 err = -EINVAL;
2271 goto out;
2272 }
2273
2274 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
0a168933 2275 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
3ce0a23d
JG		 2276 if (err)
2277 goto out;
2278 if (rdev->me_fw->size != me_req_size) {
2279 printk(KERN_ERR
2280 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2281 rdev->me_fw->size, fw_name);
2282 err = -EINVAL;
2283 }
d8f60cfc
AD		 2284
2285 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
0a168933 2286 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
d8f60cfc
AD		 2287 if (err)
2288 goto out;
2289 if (rdev->rlc_fw->size != rlc_req_size) {
2290 printk(KERN_ERR
2291 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2292 rdev->rlc_fw->size, fw_name);
2293 err = -EINVAL;
2294 }
2295
dc50ba7f 2296 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
66229b20 2297 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name);
0a168933 2298 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
8a53fa23
AD		 2299 if (err) {
2300 printk(KERN_ERR
2301 "smc: error loading firmware \"%s\"\n",
2302 fw_name);
2303 release_firmware(rdev->smc_fw);
2304 rdev->smc_fw = NULL;
2305 } else if (rdev->smc_fw->size != smc_req_size) {
66229b20
AD		 2306 printk(KERN_ERR
2307 "smc: Bogus length %zu in firmware \"%s\"\n",
2308 rdev->smc_fw->size, fw_name);
2309 err = -EINVAL;
2310 }
2311 }
2312
3ce0a23d 2313out:
3ce0a23d
JG		 2314 if (err) {
2315 if (err != -EINVAL)
2316 printk(KERN_ERR
2317 "r600_cp: Failed to load firmware \"%s\"\n",
2318 fw_name);
2319 release_firmware(rdev->pfp_fw);
2320 rdev->pfp_fw = NULL;
2321 release_firmware(rdev->me_fw);
2322 rdev->me_fw = NULL;
d8f60cfc
AD		 2323 release_firmware(rdev->rlc_fw);
2324 rdev->rlc_fw = NULL;
66229b20
AD		 2325 release_firmware(rdev->smc_fw);
2326 rdev->smc_fw = NULL;
3ce0a23d
JG		 2327 }
2328 return err;
2329}
2330
2331static int r600_cp_load_microcode(struct radeon_device *rdev)
2332{
2333 const __be32 *fw_data;
2334 int i;
2335
2336 if (!rdev->me_fw || !rdev->pfp_fw)
2337 return -EINVAL;
2338
2339 r600_cp_stop(rdev);
2340
4eace7fd
CC		 2341 WREG32(CP_RB_CNTL,
2342#ifdef __BIG_ENDIAN
2343 BUF_SWAP_32BIT |
2344#endif
2345 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3ce0a23d
JG		 2346
2347 /* Reset cp */
2348 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2349 RREG32(GRBM_SOFT_RESET);
2350 mdelay(15);
2351 WREG32(GRBM_SOFT_RESET, 0);
2352
2353 WREG32(CP_ME_RAM_WADDR, 0);
2354
2355 fw_data = (const __be32 *)rdev->me_fw->data;
2356 WREG32(CP_ME_RAM_WADDR, 0);
138e4e16 2357 for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
3ce0a23d
JG		 2358 WREG32(CP_ME_RAM_DATA,
2359 be32_to_cpup(fw_data++));
2360
2361 fw_data = (const __be32 *)rdev->pfp_fw->data;
2362 WREG32(CP_PFP_UCODE_ADDR, 0);
138e4e16 2363 for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
3ce0a23d
JG		 2364 WREG32(CP_PFP_UCODE_DATA,
2365 be32_to_cpup(fw_data++));
2366
2367 WREG32(CP_PFP_UCODE_ADDR, 0);
2368 WREG32(CP_ME_RAM_WADDR, 0);
2369 WREG32(CP_ME_RAM_RADDR, 0);
2370 return 0;
2371}
2372
2373int r600_cp_start(struct radeon_device *rdev)
2374{
e32eb50d 2375 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2376 int r;
2377 uint32_t cp_me;
2378
e32eb50d 2379 r = radeon_ring_lock(rdev, ring, 7);
3ce0a23d
JG		 2380 if (r) {
2381 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2382 return r;
2383 }
e32eb50d
CK		 2384 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2385 radeon_ring_write(ring, 0x1);
7e7b41d2 2386 if (rdev->family >= CHIP_RV770) {
e32eb50d
CK		 2387 radeon_ring_write(ring, 0x0);
2388 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f 2389 } else {
e32eb50d
CK		 2390 radeon_ring_write(ring, 0x3);
2391 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d 2392 }
e32eb50d
CK		 2393 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2394 radeon_ring_write(ring, 0);
2395 radeon_ring_write(ring, 0);
2396 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2397
2398 cp_me = 0xff;
2399 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2400 return 0;
2401}
2402
2403int r600_cp_resume(struct radeon_device *rdev)
2404{
e32eb50d 2405 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2406 u32 tmp;
2407 u32 rb_bufsz;
2408 int r;
2409
2410 /* Reset cp */
2411 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2412 RREG32(GRBM_SOFT_RESET);
2413 mdelay(15);
2414 WREG32(GRBM_SOFT_RESET, 0);
2415
2416 /* Set ring buffer size */
b72a8925
DV		 2417 rb_bufsz = order_base_2(ring->ring_size / 8);
2418 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2419#ifdef __BIG_ENDIAN
d6f28938 2420 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2421#endif
d6f28938 2422 WREG32(CP_RB_CNTL, tmp);
15d3332f 2423 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3ce0a23d
JG		 2424
2425 /* Set the write pointer delay */
2426 WREG32(CP_RB_WPTR_DELAY, 0);
2427
2428 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2429 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2430 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 2431 ring->wptr = 0;
2432 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 2433
2434 /* set the wb address whether it's enabled or not */
4eace7fd 2435 WREG32(CP_RB_RPTR_ADDR,
4eace7fd 2436 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 2437 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2438 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2439
2440 if (rdev->wb.enabled)
2441 WREG32(SCRATCH_UMSK, 0xff);
2442 else {
2443 tmp |= RB_NO_UPDATE;
2444 WREG32(SCRATCH_UMSK, 0);
2445 }
2446
3ce0a23d
JG		 2447 mdelay(1);
2448 WREG32(CP_RB_CNTL, tmp);
2449
e32eb50d 2450 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
3ce0a23d
JG		 2451 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2452
e32eb50d 2453 ring->rptr = RREG32(CP_RB_RPTR);
3ce0a23d
JG		 2454
2455 r600_cp_start(rdev);
e32eb50d 2456 ring->ready = true;
f712812e 2457 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
3ce0a23d 2458 if (r) {
e32eb50d 2459 ring->ready = false;
3ce0a23d
JG		 2460 return r;
2461 }
2462 return 0;
2463}
2464
e32eb50d 2465void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
3ce0a23d
JG		 2466{
2467 u32 rb_bufsz;
45df6803 2468 int r;
3ce0a23d
JG		 2469
2470 /* Align ring size */
b72a8925 2471 rb_bufsz = order_base_2(ring_size / 8);
3ce0a23d 2472 ring_size = (1 << (rb_bufsz + 1)) * 4;
e32eb50d
CK		 2473 ring->ring_size = ring_size;
2474 ring->align_mask = 16 - 1;
45df6803 2475
89d35807
AD		 2476 if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2477 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2478 if (r) {
2479 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2480 ring->rptr_save_reg = 0;
2481 }
45df6803 2482 }
3ce0a23d
JG		 2483}
2484
655efd3d
JG		 2485void r600_cp_fini(struct radeon_device *rdev)
2486{
45df6803 2487 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
655efd3d 2488 r600_cp_stop(rdev);
45df6803
CK		 2489 radeon_ring_fini(rdev, ring);
2490 radeon_scratch_free(rdev, ring->rptr_save_reg);
655efd3d
JG		 2491}
2492
3ce0a23d
JG		 2493/*
2494 * GPU scratch registers helpers function.
2495 */
2496void r600_scratch_init(struct radeon_device *rdev)
2497{
2498 int i;
2499
2500 rdev->scratch.num_reg = 7;
724c80e1 2501 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2502 for (i = 0; i < rdev->scratch.num_reg; i++) {
2503 rdev->scratch.free[i] = true;
724c80e1 2504 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2505 }
2506}
2507
e32eb50d 2508int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 2509{
2510 uint32_t scratch;
2511 uint32_t tmp = 0;
8b25ed34 2512 unsigned i;
3ce0a23d
JG		 2513 int r;
2514
2515 r = radeon_scratch_get(rdev, &scratch);
2516 if (r) {
2517 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2518 return r;
2519 }
2520 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 2521 r = radeon_ring_lock(rdev, ring, 3);
3ce0a23d 2522 if (r) {
8b25ed34 2523 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3ce0a23d
JG		 2524 radeon_scratch_free(rdev, scratch);
2525 return r;
2526 }
e32eb50d
CK		 2527 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2528 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2529 radeon_ring_write(ring, 0xDEADBEEF);
2530 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2531 for (i = 0; i < rdev->usec_timeout; i++) {
2532 tmp = RREG32(scratch);
2533 if (tmp == 0xDEADBEEF)
2534 break;
2535 DRM_UDELAY(1);
2536 }
2537 if (i < rdev->usec_timeout) {
8b25ed34 2538 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3ce0a23d 2539 } else {
bf852799 2540 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
8b25ed34 2541 ring->idx, scratch, tmp);
3ce0a23d
JG		 2542 r = -EINVAL;
2543 }
2544 radeon_scratch_free(rdev, scratch);
2545 return r;
2546}
2547
4d75658b
AD		 2548/*
2549 * CP fences/semaphores
2550 */
2551
3ce0a23d
JG		 2552void r600_fence_ring_emit(struct radeon_device *rdev,
2553 struct radeon_fence *fence)
2554{
e32eb50d 2555 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 2556
d0f8a854 2557 if (rdev->wb.use_event) {
30eb77f4 2558 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
77b1bad4 2559 /* flush read cache over gart */
e32eb50d
CK		 2560 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2561 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2562 PACKET3_VC_ACTION_ENA |
2563 PACKET3_SH_ACTION_ENA);
2564 radeon_ring_write(ring, 0xFFFFFFFF);
2565 radeon_ring_write(ring, 0);
2566 radeon_ring_write(ring, 10); /* poll interval */
d0f8a854 2567 /* EVENT_WRITE_EOP - flush caches, send int */
e32eb50d
CK		 2568 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2569 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2570 radeon_ring_write(ring, addr & 0xffffffff);
2571 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2572 radeon_ring_write(ring, fence->seq);
2573 radeon_ring_write(ring, 0);
d0f8a854 2574 } else {
77b1bad4 2575 /* flush read cache over gart */
e32eb50d
CK		 2576 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2577 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2578 PACKET3_VC_ACTION_ENA |
2579 PACKET3_SH_ACTION_ENA);
2580 radeon_ring_write(ring, 0xFFFFFFFF);
2581 radeon_ring_write(ring, 0);
2582 radeon_ring_write(ring, 10); /* poll interval */
2583 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2584 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
d0f8a854 2585 /* wait for 3D idle clean */
e32eb50d
CK		 2586 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2587 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2588 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
d0f8a854 2589 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 2590 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2591 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2592 radeon_ring_write(ring, fence->seq);
d0f8a854 2593 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
e32eb50d
CK		 2594 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2595 radeon_ring_write(ring, RB_INT_STAT);
d0f8a854 2596 }
3ce0a23d
JG		 2597}
2598
15d3332f 2599void r600_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 2600 struct radeon_ring *ring,
15d3332f 2601 struct radeon_semaphore *semaphore,
7b1f2485 2602 bool emit_wait)
15d3332f
CK		 2603{
2604 uint64_t addr = semaphore->gpu_addr;
2605 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2606
0be70439
CK		 2607 if (rdev->family < CHIP_CAYMAN)
2608 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2609
e32eb50d
CK		 2610 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2611 radeon_ring_write(ring, addr & 0xffffffff);
2612 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
15d3332f
CK		 2613}
2614
072b5acc
AD		 2615/**
2616 * r600_copy_cpdma - copy pages using the CP DMA engine
2617 *
2618 * @rdev: radeon_device pointer
2619 * @src_offset: src GPU address
2620 * @dst_offset: dst GPU address
2621 * @num_gpu_pages: number of GPU pages to xfer
2622 * @fence: radeon fence object
2623 *
2624 * Copy GPU paging using the CP DMA engine (r6xx+).
2625 * Used by the radeon ttm implementation to move pages if
2626 * registered as the asic copy callback.
2627 */
2628int r600_copy_cpdma(struct radeon_device *rdev,
2629 uint64_t src_offset, uint64_t dst_offset,
2630 unsigned num_gpu_pages,
2631 struct radeon_fence **fence)
2632{
2633 struct radeon_semaphore *sem = NULL;
2634 int ring_index = rdev->asic->copy.blit_ring_index;
2635 struct radeon_ring *ring = &rdev->ring[ring_index];
2636 u32 size_in_bytes, cur_size_in_bytes, tmp;
2637 int i, num_loops;
2638 int r = 0;
2639
2640 r = radeon_semaphore_create(rdev, &sem);
2641 if (r) {
2642 DRM_ERROR("radeon: moving bo (%d).\n", r);
2643 return r;
2644 }
2645
2646 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2647 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
745a39a9 2648 r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
072b5acc
AD		 2649 if (r) {
2650 DRM_ERROR("radeon: moving bo (%d).\n", r);
2651 radeon_semaphore_free(rdev, &sem, NULL);
2652 return r;
2653 }
2654
2655 if (radeon_fence_need_sync(*fence, ring->idx)) {
2656 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2657 ring->idx);
2658 radeon_fence_note_sync(*fence, ring->idx);
2659 } else {
2660 radeon_semaphore_free(rdev, &sem, NULL);
2661 }
2662
745a39a9
AD		 2663 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2664 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2665 radeon_ring_write(ring, WAIT_3D_IDLE_bit);
072b5acc
AD		 2666 for (i = 0; i < num_loops; i++) {
2667 cur_size_in_bytes = size_in_bytes;
2668 if (cur_size_in_bytes > 0x1fffff)
2669 cur_size_in_bytes = 0x1fffff;
2670 size_in_bytes -= cur_size_in_bytes;
2671 tmp = upper_32_bits(src_offset) & 0xff;
2672 if (size_in_bytes == 0)
2673 tmp |= PACKET3_CP_DMA_CP_SYNC;
2674 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
2675 radeon_ring_write(ring, src_offset & 0xffffffff);
2676 radeon_ring_write(ring, tmp);
2677 radeon_ring_write(ring, dst_offset & 0xffffffff);
2678 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2679 radeon_ring_write(ring, cur_size_in_bytes);
2680 src_offset += cur_size_in_bytes;
2681 dst_offset += cur_size_in_bytes;
2682 }
2683 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2684 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2685 radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
2686
2687 r = radeon_fence_emit(rdev, fence, ring->idx);
2688 if (r) {
2689 radeon_ring_unlock_undo(rdev, ring);
2690 return r;
2691 }
2692
2693 radeon_ring_unlock_commit(rdev, ring);
2694 radeon_semaphore_free(rdev, &sem, *fence);
2695
2696 return r;
2697}
2698
3ce0a23d
JG		 2699int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2700 uint32_t tiling_flags, uint32_t pitch,
2701 uint32_t offset, uint32_t obj_size)
2702{
2703 /* FIXME: implement */
2704 return 0;
2705}
2706
2707void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2708{
2709 /* FIXME: implement */
2710}
2711
1109ca09 2712static int r600_startup(struct radeon_device *rdev)
3ce0a23d 2713{
4d75658b 2714 struct radeon_ring *ring;
3ce0a23d
JG		 2715 int r;
2716
9e46a48d
AD		 2717 /* enable pcie gen2 link */
2718 r600_pcie_gen2_enable(rdev);
2719
e5903d39
AD		 2720 /* scratch needs to be initialized before MC */
2721 r = r600_vram_scratch_init(rdev);
2722 if (r)
2723 return r;
2724
6fab3feb
AD		 2725 r600_mc_program(rdev);
2726
779720a3
AD		 2727 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2728 r = r600_init_microcode(rdev);
2729 if (r) {
2730 DRM_ERROR("Failed to load firmware!\n");
2731 return r;
2732 }
2733 }
2734
1a029b76
JG		 2735 if (rdev->flags & RADEON_IS_AGP) {
2736 r600_agp_enable(rdev);
2737 } else {
2738 r = r600_pcie_gart_enable(rdev);
2739 if (r)
2740 return r;
2741 }
3ce0a23d 2742 r600_gpu_init(rdev);
b70d6bb3 2743
724c80e1
AD		 2744 /* allocate wb buffer */
2745 r = radeon_wb_init(rdev);
2746 if (r)
2747 return r;
2748
30eb77f4
JG		 2749 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2750 if (r) {
2751 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2752 return r;
2753 }
2754
4d75658b
AD		 2755 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2756 if (r) {
2757 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2758 return r;
2759 }
2760
d8f60cfc 2761 /* Enable IRQ */
e49f3959
AH		 2762 if (!rdev->irq.installed) {
2763 r = radeon_irq_kms_init(rdev);
2764 if (r)
2765 return r;
2766 }
2767
d8f60cfc
AD		 2768 r = r600_irq_init(rdev);
2769 if (r) {
2770 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2771 radeon_irq_kms_fini(rdev);
2772 return r;
2773 }
2774 r600_irq_set(rdev);
2775
4d75658b 2776 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
e32eb50d 2777 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a 2778 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2e1e6dad 2779 RADEON_CP_PACKET2);
4d75658b
AD		 2780 if (r)
2781 return r;
5596a9db 2782
4d75658b
AD		 2783 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2784 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2785 DMA_RB_RPTR, DMA_RB_WPTR,
2e1e6dad 2786 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3ce0a23d
JG		 2787 if (r)
2788 return r;
4d75658b 2789
3ce0a23d
JG		 2790 r = r600_cp_load_microcode(rdev);
2791 if (r)
2792 return r;
2793 r = r600_cp_resume(rdev);
2794 if (r)
2795 return r;
724c80e1 2796
4d75658b
AD		 2797 r = r600_dma_resume(rdev);
2798 if (r)
2799 return r;
2800
2898c348
CK		 2801 r = radeon_ib_pool_init(rdev);
2802 if (r) {
2803 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 2804 return r;
2898c348 2805 }
b15ba512 2806
d4e30ef0
AD		 2807 r = r600_audio_init(rdev);
2808 if (r) {
2809 DRM_ERROR("radeon: audio init failed\n");
2810 return r;
2811 }
2812
3ce0a23d
JG		 2813 return 0;
2814}
2815
28d52043
DA		 2816void r600_vga_set_state(struct radeon_device *rdev, bool state)
2817{
2818 uint32_t temp;
2819
2820 temp = RREG32(CONFIG_CNTL);
2821 if (state == false) {
2822 temp &= ~(1<<0);
2823 temp |= (1<<1);
2824 } else {
2825 temp &= ~(1<<1);
2826 }
2827 WREG32(CONFIG_CNTL, temp);
2828}
2829
fc30b8ef
DA		 2830int r600_resume(struct radeon_device *rdev)
2831{
2832 int r;
2833
1a029b76
JG		 2834 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2835 * posting will perform necessary task to bring back GPU into good
2836 * shape.
2837 */
fc30b8ef 2838 /* post card */
e7d40b9a 2839 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef 2840
b15ba512 2841 rdev->accel_working = true;
fc30b8ef
DA		 2842 r = r600_startup(rdev);
2843 if (r) {
2844 DRM_ERROR("r600 startup failed on resume\n");
6b7746e8 2845 rdev->accel_working = false;
fc30b8ef
DA		 2846 return r;
2847 }
2848
fc30b8ef
DA		 2849 return r;
2850}
2851
3ce0a23d
JG		 2852int r600_suspend(struct radeon_device *rdev)
2853{
38fd2c6f 2854 r600_audio_fini(rdev);
3ce0a23d 2855 r600_cp_stop(rdev);
4d75658b 2856 r600_dma_stop(rdev);
0c45249f 2857 r600_irq_suspend(rdev);
724c80e1 2858 radeon_wb_disable(rdev);
4aac0473 2859 r600_pcie_gart_disable(rdev);
6ddddfe7 2860
3ce0a23d
JG		 2861 return 0;
2862}
2863
2864/* Plan is to move initialization in that function and use
2865 * helper function so that radeon_device_init pretty much
2866 * do nothing more than calling asic specific function. This
2867 * should also allow to remove a bunch of callback function
2868 * like vram_info.
2869 */
2870int r600_init(struct radeon_device *rdev)
771fe6b9 2871{
3ce0a23d 2872 int r;
771fe6b9 2873
3ce0a23d
JG		 2874 if (r600_debugfs_mc_info_init(rdev)) {
2875 DRM_ERROR("Failed to register debugfs file for mc !\n");
2876 }
3ce0a23d
JG		 2877 /* Read BIOS */
2878 if (!radeon_get_bios(rdev)) {
2879 if (ASIC_IS_AVIVO(rdev))
2880 return -EINVAL;
2881 }
2882 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2883 if (!rdev->is_atom_bios) {
2884 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2885 return -EINVAL;
e7d40b9a 2886 }
3ce0a23d
JG		 2887 r = radeon_atombios_init(rdev);
2888 if (r)
2889 return r;
2890 /* Post card if necessary */
fd909c37 2891 if (!radeon_card_posted(rdev)) {
72542d77
DA		 2892 if (!rdev->bios) {
2893 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2894 return -EINVAL;
2895 }
3ce0a23d
JG		 2896 DRM_INFO("GPU not posted. posting now...\n");
2897 atom_asic_init(rdev->mode_info.atom_context);
2898 }
2899 /* Initialize scratch registers */
2900 r600_scratch_init(rdev);
2901 /* Initialize surface registers */
2902 radeon_surface_init(rdev);
7433874e 2903 /* Initialize clocks */
5e6dde7e 2904 radeon_get_clock_info(rdev->ddev);
3ce0a23d 2905 /* Fence driver */
30eb77f4 2906 r = radeon_fence_driver_init(rdev);
3ce0a23d
JG		 2907 if (r)
2908 return r;
700a0cc0
JG		 2909 if (rdev->flags & RADEON_IS_AGP) {
2910 r = radeon_agp_init(rdev);
2911 if (r)
2912 radeon_agp_disable(rdev);
2913 }
3ce0a23d 2914 r = r600_mc_init(rdev);
b574f251 2915 if (r)
3ce0a23d 2916 return r;
3ce0a23d 2917 /* Memory manager */
4c788679 2918 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2919 if (r)
2920 return r;
d8f60cfc 2921
e32eb50d
CK		 2922 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2923 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3ce0a23d 2924
4d75658b
AD		 2925 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2926 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2927
d8f60cfc
AD		 2928 rdev->ih.ring_obj = NULL;
2929 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2930
4aac0473
JG		 2931 r = r600_pcie_gart_init(rdev);
2932 if (r)
2933 return r;
2934
779720a3 2935 rdev->accel_working = true;
fc30b8ef 2936 r = r600_startup(rdev);
3ce0a23d 2937 if (r) {
655efd3d
JG		 2938 dev_err(rdev->dev, "disabling GPU acceleration\n");
2939 r600_cp_fini(rdev);
4d75658b 2940 r600_dma_fini(rdev);
655efd3d 2941 r600_irq_fini(rdev);
724c80e1 2942 radeon_wb_fini(rdev);
2898c348 2943 radeon_ib_pool_fini(rdev);
655efd3d 2944 radeon_irq_kms_fini(rdev);
75c81298 2945 r600_pcie_gart_fini(rdev);
733289c2 2946 rdev->accel_working = false;
3ce0a23d 2947 }
dafc3bd5 2948
3ce0a23d
JG		 2949 return 0;
2950}
2951
2952void r600_fini(struct radeon_device *rdev)
2953{
dafc3bd5 2954 r600_audio_fini(rdev);
655efd3d 2955 r600_cp_fini(rdev);
4d75658b 2956 r600_dma_fini(rdev);
d8f60cfc 2957 r600_irq_fini(rdev);
724c80e1 2958 radeon_wb_fini(rdev);
2898c348 2959 radeon_ib_pool_fini(rdev);
d8f60cfc 2960 radeon_irq_kms_fini(rdev);
4aac0473 2961 r600_pcie_gart_fini(rdev);
16cdf04d 2962 r600_vram_scratch_fini(rdev);
655efd3d 2963 radeon_agp_fini(rdev);
3ce0a23d
JG		 2964 radeon_gem_fini(rdev);
2965 radeon_fence_driver_fini(rdev);
4c788679 2966 radeon_bo_fini(rdev);
e7d40b9a 2967 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2968 kfree(rdev->bios);
2969 rdev->bios = NULL;
3ce0a23d
JG		 2970}
2971
2972
2973/*
2974 * CS stuff
2975 */
2976void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2977{
876dc9f3 2978 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 2979 u32 next_rptr;
7b1f2485 2980
45df6803 2981 if (ring->rptr_save_reg) {
89d35807 2982 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 2983 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2984 radeon_ring_write(ring, ((ring->rptr_save_reg -
2985 PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2986 radeon_ring_write(ring, next_rptr);
89d35807
AD		 2987 } else if (rdev->wb.enabled) {
2988 next_rptr = ring->wptr + 5 + 4;
2989 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
2990 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2991 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
2992 radeon_ring_write(ring, next_rptr);
2993 radeon_ring_write(ring, 0);
45df6803
CK		 2994 }
2995
e32eb50d
CK		 2996 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2997 radeon_ring_write(ring,
4eace7fd
CC		 2998#ifdef __BIG_ENDIAN
2999 (2 << 0) |
3000#endif
3001 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 3002 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3003 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3004}
3005
f712812e 3006int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3007{
f2e39221 3008 struct radeon_ib ib;
3ce0a23d
JG		 3009 uint32_t scratch;
3010 uint32_t tmp = 0;
3011 unsigned i;
3012 int r;
3013
3014 r = radeon_scratch_get(rdev, &scratch);
3015 if (r) {
3016 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3017 return r;
3018 }
3019 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3020 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3ce0a23d
JG		 3021 if (r) {
3022 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
af026c5b 3023 goto free_scratch;
3ce0a23d 3024 }
f2e39221
JG		 3025 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3026 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3027 ib.ptr[2] = 0xDEADBEEF;
3028 ib.length_dw = 3;
4ef72566 3029 r = radeon_ib_schedule(rdev, &ib, NULL);
3ce0a23d 3030 if (r) {
3ce0a23d 3031 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
af026c5b 3032 goto free_ib;
3ce0a23d 3033 }
f2e39221 3034 r = radeon_fence_wait(ib.fence, false);
3ce0a23d
JG		 3035 if (r) {
3036 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
af026c5b 3037 goto free_ib;
3ce0a23d
JG		 3038 }
3039 for (i = 0; i < rdev->usec_timeout; i++) {
3040 tmp = RREG32(scratch);
3041 if (tmp == 0xDEADBEEF)
3042 break;
3043 DRM_UDELAY(1);
3044 }
3045 if (i < rdev->usec_timeout) {
f2e39221 3046 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3ce0a23d 3047 } else {
4417d7f6 3048 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3049 scratch, tmp);
3050 r = -EINVAL;
3051 }
af026c5b 3052free_ib:
3ce0a23d 3053 radeon_ib_free(rdev, &ib);
af026c5b
MD		 3054free_scratch:
3055 radeon_scratch_free(rdev, scratch);
771fe6b9
JG		 3056 return r;
3057}
3058
d8f60cfc
AD		 3059/*
3060 * Interrupts
3061 *
3062 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
3063 * the same as the CP ring buffer, but in reverse. Rather than the CPU
3064 * writing to the ring and the GPU consuming, the GPU writes to the ring
3065 * and host consumes. As the host irq handler processes interrupts, it
3066 * increments the rptr. When the rptr catches up with the wptr, all the
3067 * current interrupts have been processed.
3068 */
3069
3070void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3071{
3072 u32 rb_bufsz;
3073
3074 /* Align ring size */
b72a8925 3075 rb_bufsz = order_base_2(ring_size / 4);
d8f60cfc
AD		 3076 ring_size = (1 << rb_bufsz) * 4;
3077 rdev->ih.ring_size = ring_size;
0c45249f
JG		 3078 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3079 rdev->ih.rptr = 0;
d8f60cfc
AD		 3080}
3081
25a857fb 3082int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 3083{
3084 int r;
3085
d8f60cfc
AD		 3086 /* Allocate ring buffer */
3087 if (rdev->ih.ring_obj == NULL) {
441921d5 3088 r = radeon_bo_create(rdev, rdev->ih.ring_size,
268b2510 3089 PAGE_SIZE, true,
4c788679 3090 RADEON_GEM_DOMAIN_GTT,
40f5cf99 3091 NULL, &rdev->ih.ring_obj);
d8f60cfc
AD		 3092 if (r) {
3093 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3094 return r;
3095 }
4c788679
JG		 3096 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3097 if (unlikely(r != 0))
3098 return r;
3099 r = radeon_bo_pin(rdev->ih.ring_obj,
3100 RADEON_GEM_DOMAIN_GTT,
3101 &rdev->ih.gpu_addr);
d8f60cfc 3102 if (r) {
4c788679 3103 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3104 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3105 return r;
3106 }
4c788679
JG		 3107 r = radeon_bo_kmap(rdev->ih.ring_obj,
3108 (void **)&rdev->ih.ring);
3109 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 3110 if (r) {
3111 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3112 return r;
3113 }
3114 }
d8f60cfc
AD		 3115 return 0;
3116}
3117
25a857fb 3118void r600_ih_ring_fini(struct radeon_device *rdev)
d8f60cfc 3119{
4c788679 3120 int r;
d8f60cfc 3121 if (rdev->ih.ring_obj) {
4c788679
JG		 3122 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3123 if (likely(r == 0)) {
3124 radeon_bo_kunmap(rdev->ih.ring_obj);
3125 radeon_bo_unpin(rdev->ih.ring_obj);
3126 radeon_bo_unreserve(rdev->ih.ring_obj);
3127 }
3128 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 3129 rdev->ih.ring = NULL;
3130 rdev->ih.ring_obj = NULL;
3131 }
3132}
3133
45f9a39b 3134void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 3135{
3136
45f9a39b
AD		 3137 if ((rdev->family >= CHIP_RV770) &&
3138 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 3139 /* r7xx asics need to soft reset RLC before halting */
3140 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3141 RREG32(SRBM_SOFT_RESET);
4de833c3 3142 mdelay(15);
d8f60cfc
AD		 3143 WREG32(SRBM_SOFT_RESET, 0);
3144 RREG32(SRBM_SOFT_RESET);
3145 }
3146
3147 WREG32(RLC_CNTL, 0);
3148}
3149
3150static void r600_rlc_start(struct radeon_device *rdev)
3151{
3152 WREG32(RLC_CNTL, RLC_ENABLE);
3153}
3154
2948f5e6 3155static int r600_rlc_resume(struct radeon_device *rdev)
d8f60cfc
AD		 3156{
3157 u32 i;
3158 const __be32 *fw_data;
3159
3160 if (!rdev->rlc_fw)
3161 return -EINVAL;
3162
3163 r600_rlc_stop(rdev);
3164
d8f60cfc 3165 WREG32(RLC_HB_CNTL, 0);
c420c745 3166
2948f5e6
AD		 3167 WREG32(RLC_HB_BASE, 0);
3168 WREG32(RLC_HB_RPTR, 0);
3169 WREG32(RLC_HB_WPTR, 0);
3170 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3171 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
d8f60cfc
AD		 3172 WREG32(RLC_MC_CNTL, 0);
3173 WREG32(RLC_UCODE_CNTL, 0);
3174
3175 fw_data = (const __be32 *)rdev->rlc_fw->data;
2948f5e6 3176 if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 3177 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3178 WREG32(RLC_UCODE_ADDR, i);
3179 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3180 }
3181 } else {
138e4e16 3182 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
d8f60cfc
AD		 3183 WREG32(RLC_UCODE_ADDR, i);
3184 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3185 }
3186 }
3187 WREG32(RLC_UCODE_ADDR, 0);
3188
3189 r600_rlc_start(rdev);
3190
3191 return 0;
3192}
3193
3194static void r600_enable_interrupts(struct radeon_device *rdev)
3195{
3196 u32 ih_cntl = RREG32(IH_CNTL);
3197 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3198
3199 ih_cntl |= ENABLE_INTR;
3200 ih_rb_cntl |= IH_RB_ENABLE;
3201 WREG32(IH_CNTL, ih_cntl);
3202 WREG32(IH_RB_CNTL, ih_rb_cntl);
3203 rdev->ih.enabled = true;
3204}
3205
45f9a39b 3206void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 3207{
3208 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3209 u32 ih_cntl = RREG32(IH_CNTL);
3210
3211 ih_rb_cntl &= ~IH_RB_ENABLE;
3212 ih_cntl &= ~ENABLE_INTR;
3213 WREG32(IH_RB_CNTL, ih_rb_cntl);
3214 WREG32(IH_CNTL, ih_cntl);
3215 /* set rptr, wptr to 0 */
3216 WREG32(IH_RB_RPTR, 0);
3217 WREG32(IH_RB_WPTR, 0);
3218 rdev->ih.enabled = false;
d8f60cfc
AD		 3219 rdev->ih.rptr = 0;
3220}
3221
e0df1ac5
AD		 3222static void r600_disable_interrupt_state(struct radeon_device *rdev)
3223{
3224 u32 tmp;
3225
3555e53b 3226 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
4d75658b
AD		 3227 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3228 WREG32(DMA_CNTL, tmp);
e0df1ac5
AD		 3229 WREG32(GRBM_INT_CNTL, 0);
3230 WREG32(DxMODE_INT_MASK, 0);
6f34be50
AD		 3231 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3232 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
e0df1ac5
AD		 3233 if (ASIC_IS_DCE3(rdev)) {
3234 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3235 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3236 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3237 WREG32(DC_HPD1_INT_CONTROL, tmp);
3238 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3239 WREG32(DC_HPD2_INT_CONTROL, tmp);
3240 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3241 WREG32(DC_HPD3_INT_CONTROL, tmp);
3242 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3243 WREG32(DC_HPD4_INT_CONTROL, tmp);
3244 if (ASIC_IS_DCE32(rdev)) {
3245 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3246 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 3247 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 3248 WREG32(DC_HPD6_INT_CONTROL, tmp);
c6543a6e
RM		 3249 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3250 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3251 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3252 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f122c610
AD		 3253 } else {
3254 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3255 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3256 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3257 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3258 }
3259 } else {
3260 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3261 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3262 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3263 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 3264 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3265 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 3266 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 3267 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
f122c610
AD		 3268 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3269 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3270 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3271 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
e0df1ac5
AD		 3272 }
3273}
3274
d8f60cfc
AD		 3275int r600_irq_init(struct radeon_device *rdev)
3276{
3277 int ret = 0;
3278 int rb_bufsz;
3279 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3280
3281 /* allocate ring */
0c45249f 3282 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 3283 if (ret)
3284 return ret;
3285
3286 /* disable irqs */
3287 r600_disable_interrupts(rdev);
3288
3289 /* init rlc */
2948f5e6
AD		 3290 if (rdev->family >= CHIP_CEDAR)
3291 ret = evergreen_rlc_resume(rdev);
3292 else
3293 ret = r600_rlc_resume(rdev);
d8f60cfc
AD		 3294 if (ret) {
3295 r600_ih_ring_fini(rdev);
3296 return ret;
3297 }
3298
3299 /* setup interrupt control */
3300 /* set dummy read address to ring address */
3301 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3302 interrupt_cntl = RREG32(INTERRUPT_CNTL);
3303 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3304 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3305 */
3306 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3307 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3308 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3309 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3310
3311 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
b72a8925 3312 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
d8f60cfc
AD		 3313
3314 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3315 IH_WPTR_OVERFLOW_CLEAR |
3316 (rb_bufsz << 1));
724c80e1
AD		 3317
3318 if (rdev->wb.enabled)
3319 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3320
3321 /* set the writeback address whether it's enabled or not */
3322 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3323 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 3324
3325 WREG32(IH_RB_CNTL, ih_rb_cntl);
3326
3327 /* set rptr, wptr to 0 */
3328 WREG32(IH_RB_RPTR, 0);
3329 WREG32(IH_RB_WPTR, 0);
3330
3331 /* Default settings for IH_CNTL (disabled at first) */
3332 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3333 /* RPTR_REARM only works if msi's are enabled */
3334 if (rdev->msi_enabled)
3335 ih_cntl |= RPTR_REARM;
d8f60cfc
AD		 3336 WREG32(IH_CNTL, ih_cntl);
3337
3338 /* force the active interrupt state to all disabled */
45f9a39b
AD		 3339 if (rdev->family >= CHIP_CEDAR)
3340 evergreen_disable_interrupt_state(rdev);
3341 else
3342 r600_disable_interrupt_state(rdev);
d8f60cfc 3343
2099810f
DA		 3344 /* at this point everything should be setup correctly to enable master */
3345 pci_set_master(rdev->pdev);
3346
d8f60cfc
AD		 3347 /* enable irqs */
3348 r600_enable_interrupts(rdev);
3349
3350 return ret;
3351}
3352
0c45249f 3353void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 3354{
45f9a39b 3355 r600_irq_disable(rdev);
d8f60cfc 3356 r600_rlc_stop(rdev);
0c45249f
JG		 3357}
3358
3359void r600_irq_fini(struct radeon_device *rdev)
3360{
3361 r600_irq_suspend(rdev);
d8f60cfc
AD		 3362 r600_ih_ring_fini(rdev);
3363}
3364
3365int r600_irq_set(struct radeon_device *rdev)
3366{
e0df1ac5
AD		 3367 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3368 u32 mode_int = 0;
3369 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3370 u32 grbm_int_cntl = 0;
f122c610 3371 u32 hdmi0, hdmi1;
6f34be50 3372 u32 d1grph = 0, d2grph = 0;
4d75658b 3373 u32 dma_cntl;
4a6369e9 3374 u32 thermal_int = 0;
d8f60cfc 3375
003e69f9 3376 if (!rdev->irq.installed) {
fce7d61b 3377 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3378 return -EINVAL;
3379 }
d8f60cfc 3380 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3381 if (!rdev->ih.enabled) {
3382 r600_disable_interrupts(rdev);
3383 /* force the active interrupt state to all disabled */
3384 r600_disable_interrupt_state(rdev);
d8f60cfc 3385 return 0;
79c2bbc5 3386 }
d8f60cfc 3387
e0df1ac5
AD		 3388 if (ASIC_IS_DCE3(rdev)) {
3389 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3390 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3391 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3392 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3393 if (ASIC_IS_DCE32(rdev)) {
3394 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3395 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
c6543a6e
RM		 3396 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3397 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
f122c610
AD		 3398 } else {
3399 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3400 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5
AD		 3401 }
3402 } else {
3403 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3404 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3405 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
f122c610
AD		 3406 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3407 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
e0df1ac5 3408 }
4a6369e9 3409
4d75658b 3410 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
e0df1ac5 3411
4a6369e9
AD		 3412 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3413 thermal_int = RREG32(CG_THERMAL_INT) &
3414 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
66229b20
AD		 3415 } else if (rdev->family >= CHIP_RV770) {
3416 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3417 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3418 }
3419 if (rdev->irq.dpm_thermal) {
3420 DRM_DEBUG("dpm thermal\n");
3421 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
4a6369e9
AD		 3422 }
3423
736fc37f 3424 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
d8f60cfc
AD		 3425 DRM_DEBUG("r600_irq_set: sw int\n");
3426 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3427 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc 3428 }
4d75658b
AD		 3429
3430 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3431 DRM_DEBUG("r600_irq_set: sw int dma\n");
3432 dma_cntl |= TRAP_ENABLE;
3433 }
3434
6f34be50 3435 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3436 atomic_read(&rdev->irq.pflip[0])) {
d8f60cfc
AD		 3437 DRM_DEBUG("r600_irq_set: vblank 0\n");
3438 mode_int |= D1MODE_VBLANK_INT_MASK;
3439 }
6f34be50 3440 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3441 atomic_read(&rdev->irq.pflip[1])) {
d8f60cfc
AD		 3442 DRM_DEBUG("r600_irq_set: vblank 1\n");
3443 mode_int |= D2MODE_VBLANK_INT_MASK;
3444 }
e0df1ac5
AD		 3445 if (rdev->irq.hpd[0]) {
3446 DRM_DEBUG("r600_irq_set: hpd 1\n");
3447 hpd1 |= DC_HPDx_INT_EN;
3448 }
3449 if (rdev->irq.hpd[1]) {
3450 DRM_DEBUG("r600_irq_set: hpd 2\n");
3451 hpd2 |= DC_HPDx_INT_EN;
3452 }
3453 if (rdev->irq.hpd[2]) {
3454 DRM_DEBUG("r600_irq_set: hpd 3\n");
3455 hpd3 |= DC_HPDx_INT_EN;
3456 }
3457 if (rdev->irq.hpd[3]) {
3458 DRM_DEBUG("r600_irq_set: hpd 4\n");
3459 hpd4 |= DC_HPDx_INT_EN;
3460 }
3461 if (rdev->irq.hpd[4]) {
3462 DRM_DEBUG("r600_irq_set: hpd 5\n");
3463 hpd5 |= DC_HPDx_INT_EN;
3464 }
3465 if (rdev->irq.hpd[5]) {
3466 DRM_DEBUG("r600_irq_set: hpd 6\n");
3467 hpd6 |= DC_HPDx_INT_EN;
3468 }
f122c610
AD		 3469 if (rdev->irq.afmt[0]) {
3470 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3471 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3472 }
f122c610
AD		 3473 if (rdev->irq.afmt[1]) {
3474 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3475 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
f2594933 3476 }
d8f60cfc
AD		 3477
3478 WREG32(CP_INT_CNTL, cp_int_cntl);
4d75658b 3479 WREG32(DMA_CNTL, dma_cntl);
d8f60cfc 3480 WREG32(DxMODE_INT_MASK, mode_int);
6f34be50
AD		 3481 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3482 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
2031f77c 3483 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
e0df1ac5
AD		 3484 if (ASIC_IS_DCE3(rdev)) {
3485 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3486 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3487 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3488 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3489 if (ASIC_IS_DCE32(rdev)) {
3490 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3491 WREG32(DC_HPD6_INT_CONTROL, hpd6);
c6543a6e
RM		 3492 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3493 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
f122c610
AD		 3494 } else {
3495 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3496 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5
AD		 3497 }
3498 } else {
3499 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3500 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3501 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
f122c610
AD		 3502 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3503 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
e0df1ac5 3504 }
4a6369e9
AD		 3505 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3506 WREG32(CG_THERMAL_INT, thermal_int);
66229b20
AD		 3507 } else if (rdev->family >= CHIP_RV770) {
3508 WREG32(RV770_CG_THERMAL_INT, thermal_int);
4a6369e9 3509 }
d8f60cfc
AD		 3510
3511 return 0;
3512}
3513
ce580fab 3514static void r600_irq_ack(struct radeon_device *rdev)
d8f60cfc 3515{
e0df1ac5
AD		 3516 u32 tmp;
3517
3518 if (ASIC_IS_DCE3(rdev)) {
6f34be50
AD		 3519 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3520 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3521 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
f122c610 3522 if (ASIC_IS_DCE32(rdev)) {
c6543a6e
RM		 3523 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3524 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
f122c610
AD		 3525 } else {
3526 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3527 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3528 }
e0df1ac5 3529 } else {
6f34be50
AD		 3530 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3531 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3532 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
f122c610
AD		 3533 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3534 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
6f34be50
AD		 3535 }
3536 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3537 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3538
3539 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3540 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3541 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3542 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3543 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3544 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3545 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3546 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3547 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3548 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3549 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3550 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3551 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
e0df1ac5
AD		 3552 if (ASIC_IS_DCE3(rdev)) {
3553 tmp = RREG32(DC_HPD1_INT_CONTROL);
3554 tmp |= DC_HPDx_INT_ACK;
3555 WREG32(DC_HPD1_INT_CONTROL, tmp);
3556 } else {
3557 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3558 tmp |= DC_HPDx_INT_ACK;
3559 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3560 }
3561 }
6f34be50 3562 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
e0df1ac5
AD		 3563 if (ASIC_IS_DCE3(rdev)) {
3564 tmp = RREG32(DC_HPD2_INT_CONTROL);
3565 tmp |= DC_HPDx_INT_ACK;
3566 WREG32(DC_HPD2_INT_CONTROL, tmp);
3567 } else {
3568 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3569 tmp |= DC_HPDx_INT_ACK;
3570 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3571 }
3572 }
6f34be50 3573 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
e0df1ac5
AD		 3574 if (ASIC_IS_DCE3(rdev)) {
3575 tmp = RREG32(DC_HPD3_INT_CONTROL);
3576 tmp |= DC_HPDx_INT_ACK;
3577 WREG32(DC_HPD3_INT_CONTROL, tmp);
3578 } else {
3579 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3580 tmp |= DC_HPDx_INT_ACK;
3581 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3582 }
3583 }
6f34be50 3584 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
e0df1ac5
AD		 3585 tmp = RREG32(DC_HPD4_INT_CONTROL);
3586 tmp |= DC_HPDx_INT_ACK;
3587 WREG32(DC_HPD4_INT_CONTROL, tmp);
3588 }
3589 if (ASIC_IS_DCE32(rdev)) {
6f34be50 3590 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
e0df1ac5
AD		 3591 tmp = RREG32(DC_HPD5_INT_CONTROL);
3592 tmp |= DC_HPDx_INT_ACK;
3593 WREG32(DC_HPD5_INT_CONTROL, tmp);
3594 }
6f34be50 3595 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
e0df1ac5
AD		 3596 tmp = RREG32(DC_HPD5_INT_CONTROL);
3597 tmp |= DC_HPDx_INT_ACK;
3598 WREG32(DC_HPD6_INT_CONTROL, tmp);
3599 }
f122c610 3600 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3601 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
f122c610 3602 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3603 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
f122c610
AD		 3604 }
3605 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
c6543a6e 3606 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
f122c610 3607 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
c6543a6e 3608 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
f2594933
CK		 3609 }
3610 } else {
f122c610
AD		 3611 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3612 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3613 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3614 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3615 }
3616 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3617 if (ASIC_IS_DCE3(rdev)) {
3618 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3619 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3620 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3621 } else {
3622 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3623 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3624 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3625 }
f2594933
CK		 3626 }
3627 }
d8f60cfc
AD		 3628}
3629
3630void r600_irq_disable(struct radeon_device *rdev)
3631{
d8f60cfc
AD		 3632 r600_disable_interrupts(rdev);
3633 /* Wait and acknowledge irq */
3634 mdelay(1);
6f34be50 3635 r600_irq_ack(rdev);
e0df1ac5 3636 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3637}
3638
ce580fab 3639static u32 r600_get_ih_wptr(struct radeon_device *rdev)
d8f60cfc
AD		 3640{
3641 u32 wptr, tmp;
3ce0a23d 3642
724c80e1 3643 if (rdev->wb.enabled)
204ae24d 3644 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 3645 else
3646 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3647
d8f60cfc 3648 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3649 /* When a ring buffer overflow happen start parsing interrupt
3650 * from the last not overwritten vector (wptr + 16). Hopefully
3651 * this should allow us to catchup.
3652 */
3653 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3654 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3655 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3656 tmp = RREG32(IH_RB_CNTL);
3657 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3658 WREG32(IH_RB_CNTL, tmp);
3659 }
0c45249f 3660 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3661}
3ce0a23d 3662
d8f60cfc
AD		 3663/* r600 IV Ring
3664 * Each IV ring entry is 128 bits:
3665 * [7:0] - interrupt source id
3666 * [31:8] - reserved
3667 * [59:32] - interrupt source data
3668 * [127:60] - reserved
3669 *
3670 * The basic interrupt vector entries
3671 * are decoded as follows:
3672 * src_id src_data description
3673 * 1 0 D1 Vblank
3674 * 1 1 D1 Vline
3675 * 5 0 D2 Vblank
3676 * 5 1 D2 Vline
3677 * 19 0 FP Hot plug detection A
3678 * 19 1 FP Hot plug detection B
3679 * 19 2 DAC A auto-detection
3680 * 19 3 DAC B auto-detection
f2594933
CK		 3681 * 21 4 HDMI block A
3682 * 21 5 HDMI block B
d8f60cfc
AD		 3683 * 176 - CP_INT RB
3684 * 177 - CP_INT IB1
3685 * 178 - CP_INT IB2
3686 * 181 - EOP Interrupt
3687 * 233 - GUI Idle
3688 *
3689 * Note, these are based on r600 and may need to be
3690 * adjusted or added to on newer asics
3691 */
3692
3693int r600_irq_process(struct radeon_device *rdev)
3694{
682f1a54
DA		 3695 u32 wptr;
3696 u32 rptr;
d8f60cfc 3697 u32 src_id, src_data;
6f34be50 3698 u32 ring_index;
d4877cf2 3699 bool queue_hotplug = false;
f122c610 3700 bool queue_hdmi = false;
4a6369e9 3701 bool queue_thermal = false;
d8f60cfc 3702
682f1a54 3703 if (!rdev->ih.enabled || rdev->shutdown)
79c2bbc5 3704 return IRQ_NONE;
d8f60cfc 3705
f6a56939
BH		 3706 /* No MSIs, need a dummy read to flush PCI DMAs */
3707 if (!rdev->msi_enabled)
3708 RREG32(IH_RB_WPTR);
3709
682f1a54 3710 wptr = r600_get_ih_wptr(rdev);
d8f60cfc 3711
c20dc369
CK		 3712restart_ih:
3713 /* is somebody else already processing irqs? */
3714 if (atomic_xchg(&rdev->ih.lock, 1))
d8f60cfc 3715 return IRQ_NONE;
d8f60cfc 3716
c20dc369
CK		 3717 rptr = rdev->ih.rptr;
3718 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3719
964f6645
BH		 3720 /* Order reading of wptr vs. reading of IH ring data */
3721 rmb();
3722
d8f60cfc 3723 /* display interrupts */
6f34be50 3724 r600_irq_ack(rdev);
d8f60cfc 3725
d8f60cfc
AD		 3726 while (rptr != wptr) {
3727 /* wptr/rptr are in bytes! */
3728 ring_index = rptr / 4;
4eace7fd
CC		 3729 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3730 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
d8f60cfc
AD		 3731
3732 switch (src_id) {
3733 case 1: /* D1 vblank/vline */
3734 switch (src_data) {
3735 case 0: /* D1 vblank */
6f34be50 3736 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3737 if (rdev->irq.crtc_vblank_int[0]) {
3738 drm_handle_vblank(rdev->ddev, 0);
3739 rdev->pm.vblank_sync = true;
3740 wake_up(&rdev->irq.vblank_queue);
3741 }
736fc37f 3742 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 3743 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3744 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
d8f60cfc
AD		 3745 DRM_DEBUG("IH: D1 vblank\n");
3746 }
3747 break;
3748 case 1: /* D1 vline */
6f34be50
AD		 3749 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3750 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
d8f60cfc
AD		 3751 DRM_DEBUG("IH: D1 vline\n");
3752 }
3753 break;
3754 default:
b042589c 3755 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3756 break;
3757 }
3758 break;
3759 case 5: /* D2 vblank/vline */
3760 switch (src_data) {
3761 case 0: /* D2 vblank */
6f34be50 3762 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3763 if (rdev->irq.crtc_vblank_int[1]) {
3764 drm_handle_vblank(rdev->ddev, 1);
3765 rdev->pm.vblank_sync = true;
3766 wake_up(&rdev->irq.vblank_queue);
3767 }
736fc37f 3768 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 3769 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3770 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
d8f60cfc
AD		 3771 DRM_DEBUG("IH: D2 vblank\n");
3772 }
3773 break;
3774 case 1: /* D1 vline */
6f34be50
AD		 3775 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3776 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
d8f60cfc
AD		 3777 DRM_DEBUG("IH: D2 vline\n");
3778 }
3779 break;
3780 default:
b042589c 3781 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3782 break;
3783 }
3784 break;
e0df1ac5
AD		 3785 case 19: /* HPD/DAC hotplug */
3786 switch (src_data) {
3787 case 0:
6f34be50
AD		 3788 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3789 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3790 queue_hotplug = true;
3791 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3792 }
3793 break;
3794 case 1:
6f34be50
AD		 3795 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3796 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3797 queue_hotplug = true;
3798 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3799 }
3800 break;
3801 case 4:
6f34be50
AD		 3802 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3803 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3804 queue_hotplug = true;
3805 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3806 }
3807 break;
3808 case 5:
6f34be50
AD		 3809 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3810 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3811 queue_hotplug = true;
3812 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3813 }
3814 break;
3815 case 10:
6f34be50
AD		 3816 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3817 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3818 queue_hotplug = true;
3819 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3820 }
3821 break;
3822 case 12:
6f34be50
AD		 3823 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3824 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3825 queue_hotplug = true;
3826 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3827 }
3828 break;
3829 default:
b042589c 3830 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3831 break;
3832 }
3833 break;
f122c610
AD		 3834 case 21: /* hdmi */
3835 switch (src_data) {
3836 case 4:
3837 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3838 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3839 queue_hdmi = true;
3840 DRM_DEBUG("IH: HDMI0\n");
3841 }
3842 break;
3843 case 5:
3844 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3845 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3846 queue_hdmi = true;
3847 DRM_DEBUG("IH: HDMI1\n");
3848 }
3849 break;
3850 default:
3851 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3852 break;
3853 }
f2594933 3854 break;
d8f60cfc
AD		 3855 case 176: /* CP_INT in ring buffer */
3856 case 177: /* CP_INT in IB1 */
3857 case 178: /* CP_INT in IB2 */
3858 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 3859 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc
AD		 3860 break;
3861 case 181: /* CP EOP event */
3862 DRM_DEBUG("IH: CP EOP\n");
7465280c 3863 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc 3864 break;
4d75658b
AD		 3865 case 224: /* DMA trap event */
3866 DRM_DEBUG("IH: DMA trap\n");
3867 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3868 break;
4a6369e9
AD		 3869 case 230: /* thermal low to high */
3870 DRM_DEBUG("IH: thermal low to high\n");
3871 rdev->pm.dpm.thermal.high_to_low = false;
3872 queue_thermal = true;
3873 break;
3874 case 231: /* thermal high to low */
3875 DRM_DEBUG("IH: thermal high to low\n");
3876 rdev->pm.dpm.thermal.high_to_low = true;
3877 queue_thermal = true;
3878 break;
2031f77c 3879 case 233: /* GUI IDLE */
303c805c 3880 DRM_DEBUG("IH: GUI idle\n");
2031f77c 3881 break;
d8f60cfc 3882 default:
b042589c 3883 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3884 break;
3885 }
3886
3887 /* wptr/rptr are in bytes! */
0c45249f
JG		 3888 rptr += 16;
3889 rptr &= rdev->ih.ptr_mask;
d8f60cfc 3890 }
d4877cf2 3891 if (queue_hotplug)
32c87fca 3892 schedule_work(&rdev->hotplug_work);
f122c610
AD		 3893 if (queue_hdmi)
3894 schedule_work(&rdev->audio_work);
4a6369e9
AD		 3895 if (queue_thermal && rdev->pm.dpm_enabled)
3896 schedule_work(&rdev->pm.dpm.thermal.work);
d8f60cfc
AD		 3897 rdev->ih.rptr = rptr;
3898 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 3899 atomic_set(&rdev->ih.lock, 0);
3900
3901 /* make sure wptr hasn't changed while processing */
3902 wptr = r600_get_ih_wptr(rdev);
3903 if (wptr != rptr)
3904 goto restart_ih;
3905
d8f60cfc
AD		 3906 return IRQ_HANDLED;
3907}
3ce0a23d
JG		 3908
3909/*
3910 * Debugfs info
3911 */
3912#if defined(CONFIG_DEBUG_FS)
3913
3ce0a23d
JG		 3914static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3915{
3916 struct drm_info_node *node = (struct drm_info_node *) m->private;
3917 struct drm_device *dev = node->minor->dev;
3918 struct radeon_device *rdev = dev->dev_private;
3919
3920 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3921 DREG32_SYS(m, rdev, VM_L2_STATUS);
3922 return 0;
3923}
3924
3925static struct drm_info_list r600_mc_info_list[] = {
3926 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3ce0a23d
JG		 3927};
3928#endif
3929
3930int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3931{
3932#if defined(CONFIG_DEBUG_FS)
3933 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3934#else
3935 return 0;
3936#endif
771fe6b9 3937}
062b389c
JG		 3938
3939/**
3940 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3941 * rdev: radeon device structure
3942 * bo: buffer object struct which userspace is waiting for idle
3943 *
3944 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3945 * through ring buffer, this leads to corruption in rendering, see
3946 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3947 * directly perform HDP flush by writing register through MMIO.
3948 */
3949void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3950{
812d0469 3951 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 3952 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3953 * This seems to cause problems on some AGP cards. Just use the old
3954 * method for them.
812d0469 3955 */
e488459a 3956 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 3957 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 3958 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 3959 u32 tmp;
3960
3961 WREG32(HDP_DEBUG1, 0);
3962 tmp = readl((void __iomem *)ptr);
3963 } else
3964 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 3965}
3313e3d4
AD		 3966
3967void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3968{
d5445a17 3969 u32 link_width_cntl, mask;
3313e3d4
AD		 3970
3971 if (rdev->flags & RADEON_IS_IGP)
3972 return;
3973
3974 if (!(rdev->flags & RADEON_IS_PCIE))
3975 return;
3976
3977 /* x2 cards have a special sequence */
3978 if (ASIC_IS_X2(rdev))
3979 return;
3980
d5445a17 3981 radeon_gui_idle(rdev);
3313e3d4
AD		 3982
3983 switch (lanes) {
3984 case 0:
3985 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3986 break;
3987 case 1:
3988 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3989 break;
3990 case 2:
3991 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3992 break;
3993 case 4:
3994 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3995 break;
3996 case 8:
3997 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3998 break;
3999 case 12:
d5445a17 4000 /* not actually supported */
3313e3d4
AD		 4001 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4002 break;
4003 case 16:
3313e3d4
AD		 4004 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4005 break;
d5445a17
AD		 4006 default:
4007 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4008 return;
3313e3d4
AD		 4009 }
4010
492d2b61 4011 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
d5445a17
AD		 4012 link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4013 link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4014 link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4015 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3313e3d4 4016
492d2b61 4017 WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3313e3d4
AD		 4018}
4019
4020int r600_get_pcie_lanes(struct radeon_device *rdev)
4021{
4022 u32 link_width_cntl;
4023
4024 if (rdev->flags & RADEON_IS_IGP)
4025 return 0;
4026
4027 if (!(rdev->flags & RADEON_IS_PCIE))
4028 return 0;
4029
4030 /* x2 cards have a special sequence */
4031 if (ASIC_IS_X2(rdev))
4032 return 0;
4033
d5445a17 4034 radeon_gui_idle(rdev);
3313e3d4 4035
492d2b61 4036 link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3313e3d4
AD		 4037
4038 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3313e3d4
AD		 4039 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4040 return 1;
4041 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4042 return 2;
4043 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4044 return 4;
4045 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4046 return 8;
d5445a17
AD		 4047 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4048 /* not actually supported */
4049 return 12;
4050 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3313e3d4
AD		 4051 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4052 default:
4053 return 16;
4054 }
4055}
4056
9e46a48d
AD		 4057static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4058{
4059 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4060 u16 link_cntl2;
4061
d42dd579
AD		 4062 if (radeon_pcie_gen2 == 0)
4063 return;
4064
9e46a48d
AD		 4065 if (rdev->flags & RADEON_IS_IGP)
4066 return;
4067
4068 if (!(rdev->flags & RADEON_IS_PCIE))
4069 return;
4070
4071 /* x2 cards have a special sequence */
4072 if (ASIC_IS_X2(rdev))
4073 return;
4074
4075 /* only RV6xx+ chips are supported */
4076 if (rdev->family <= CHIP_R600)
4077 return;
4078
7e0e4196
KSS		 4079 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4080 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
197bbb3d
DA		 4081 return;
4082
492d2b61 4083 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3691feea
AD		 4084 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4085 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4086 return;
4087 }
4088
197bbb3d
DA		 4089 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4090
9e46a48d
AD		 4091 /* 55 nm r6xx asics */
4092 if ((rdev->family == CHIP_RV670) ||
4093 (rdev->family == CHIP_RV620) ||
4094 (rdev->family == CHIP_RV635)) {
4095 /* advertise upconfig capability */
492d2b61 4096 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d 4097 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61
AD		 4098 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4099 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d
AD		 4100 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4101 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4102 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4103 LC_RECONFIG_ARC_MISSING_ESCAPE);
4104 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
492d2b61 4105 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4106 } else {
4107 link_width_cntl |= LC_UPCONFIGURE_DIS;
492d2b61 4108 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4109 }
4110 }
4111
492d2b61 4112 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d
AD		 4113 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4114 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4115
4116 /* 55 nm r6xx asics */
4117 if ((rdev->family == CHIP_RV670) ||
4118 (rdev->family == CHIP_RV620) ||
4119 (rdev->family == CHIP_RV635)) {
4120 WREG32(MM_CFGREGS_CNTL, 0x8);
4121 link_cntl2 = RREG32(0x4088);
4122 WREG32(MM_CFGREGS_CNTL, 0);
4123 /* not supported yet */
4124 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4125 return;
4126 }
4127
4128 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4129 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4130 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4131 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4132 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
492d2b61 4133 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4134
4135 tmp = RREG32(0x541c);
4136 WREG32(0x541c, tmp | 0x8);
4137 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4138 link_cntl2 = RREG16(0x4088);
4139 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4140 link_cntl2 |= 0x2;
4141 WREG16(0x4088, link_cntl2);
4142 WREG32(MM_CFGREGS_CNTL, 0);
4143
4144 if ((rdev->family == CHIP_RV670) ||
4145 (rdev->family == CHIP_RV620) ||
4146 (rdev->family == CHIP_RV635)) {
492d2b61 4147 training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
9e46a48d 4148 training_cntl &= ~LC_POINT_7_PLUS_EN;
492d2b61 4149 WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
9e46a48d 4150 } else {
492d2b61 4151 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4152 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
492d2b61 4153 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4154 }
4155
492d2b61 4156 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4157 speed_cntl |= LC_GEN2_EN_STRAP;
492d2b61 4158 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4159
4160 } else {
492d2b61 4161 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d
AD		 4162 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4163 if (1)
4164 link_width_cntl |= LC_UPCONFIGURE_DIS;
4165 else
4166 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61 4167 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4168 }
4169}
6759a0a7
MO		 4170
4171/**
d0418894 4172 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
6759a0a7
MO		 4173 *
4174 * @rdev: radeon_device pointer
4175 *
4176 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4177 * Returns the 64 bit clock counter snapshot.
4178 */
d0418894 4179uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
6759a0a7
MO		 4180{
4181 uint64_t clock;
4182
4183 mutex_lock(&rdev->gpu_clock_mutex);
4184 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4185 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4186 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4187 mutex_unlock(&rdev->gpu_clock_mutex);
4188 return clock;
4189}
Linux 6.x block layer and io_uring tree(s)