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drm/radeon: move ring debugfs into radeon_ring.c
[linux-2.6-block.git] / drivers / gpu / drm / radeon / r600.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
5a0e3ad6 28#include <linux/slab.h>
3ce0a23d
JG		 29#include <linux/seq_file.h>
30#include <linux/firmware.h>
31#include <linux/platform_device.h>
e0cd3608 32#include <linux/module.h>
771fe6b9 33#include "drmP.h"
3ce0a23d 34#include "radeon_drm.h"
771fe6b9 35#include "radeon.h"
e6990375 36#include "radeon_asic.h"
3ce0a23d 37#include "radeon_mode.h"
3ce0a23d 38#include "r600d.h"
3ce0a23d 39#include "atom.h"
d39c3b89 40#include "avivod.h"
771fe6b9 41
3ce0a23d
JG		 42#define PFP_UCODE_SIZE 576
43#define PM4_UCODE_SIZE 1792
d8f60cfc 44#define RLC_UCODE_SIZE 768
3ce0a23d
JG		 45#define R700_PFP_UCODE_SIZE 848
46#define R700_PM4_UCODE_SIZE 1360
d8f60cfc 47#define R700_RLC_UCODE_SIZE 1024
fe251e2f
AD		 48#define EVERGREEN_PFP_UCODE_SIZE 1120
49#define EVERGREEN_PM4_UCODE_SIZE 1376
45f9a39b 50#define EVERGREEN_RLC_UCODE_SIZE 768
12727809 51#define CAYMAN_RLC_UCODE_SIZE 1024
3ce0a23d
JG		 52
53/* Firmware Names */
54MODULE_FIRMWARE("radeon/R600_pfp.bin");
55MODULE_FIRMWARE("radeon/R600_me.bin");
56MODULE_FIRMWARE("radeon/RV610_pfp.bin");
57MODULE_FIRMWARE("radeon/RV610_me.bin");
58MODULE_FIRMWARE("radeon/RV630_pfp.bin");
59MODULE_FIRMWARE("radeon/RV630_me.bin");
60MODULE_FIRMWARE("radeon/RV620_pfp.bin");
61MODULE_FIRMWARE("radeon/RV620_me.bin");
62MODULE_FIRMWARE("radeon/RV635_pfp.bin");
63MODULE_FIRMWARE("radeon/RV635_me.bin");
64MODULE_FIRMWARE("radeon/RV670_pfp.bin");
65MODULE_FIRMWARE("radeon/RV670_me.bin");
66MODULE_FIRMWARE("radeon/RS780_pfp.bin");
67MODULE_FIRMWARE("radeon/RS780_me.bin");
68MODULE_FIRMWARE("radeon/RV770_pfp.bin");
69MODULE_FIRMWARE("radeon/RV770_me.bin");
70MODULE_FIRMWARE("radeon/RV730_pfp.bin");
71MODULE_FIRMWARE("radeon/RV730_me.bin");
72MODULE_FIRMWARE("radeon/RV710_pfp.bin");
73MODULE_FIRMWARE("radeon/RV710_me.bin");
d8f60cfc
AD		 74MODULE_FIRMWARE("radeon/R600_rlc.bin");
75MODULE_FIRMWARE("radeon/R700_rlc.bin");
fe251e2f
AD		 76MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
77MODULE_FIRMWARE("radeon/CEDAR_me.bin");
45f9a39b 78MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
fe251e2f
AD		 79MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
80MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
45f9a39b 81MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
fe251e2f
AD		 82MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
83MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
45f9a39b 84MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
a7433742 85MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
fe251e2f 86MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
45f9a39b 87MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
439bd6cd
AD		 88MODULE_FIRMWARE("radeon/PALM_pfp.bin");
89MODULE_FIRMWARE("radeon/PALM_me.bin");
90MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
d5c5a72f
AD		 91MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
92MODULE_FIRMWARE("radeon/SUMO_me.bin");
93MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
94MODULE_FIRMWARE("radeon/SUMO2_me.bin");
3ce0a23d
JG		 95
96int r600_debugfs_mc_info_init(struct radeon_device *rdev);
771fe6b9 97
1a029b76 98/* r600,rv610,rv630,rv620,rv635,rv670 */
771fe6b9
JG		 99int r600_mc_wait_for_idle(struct radeon_device *rdev);
100void r600_gpu_init(struct radeon_device *rdev);
3ce0a23d 101void r600_fini(struct radeon_device *rdev);
45f9a39b 102void r600_irq_disable(struct radeon_device *rdev);
9e46a48d 103static void r600_pcie_gen2_enable(struct radeon_device *rdev);
771fe6b9 104
21a8122a 105/* get temperature in millidegrees */
20d391d7 106int rv6xx_get_temp(struct radeon_device *rdev)
21a8122a
AD		 107{
108 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
109 ASIC_T_SHIFT;
20d391d7 110 int actual_temp = temp & 0xff;
21a8122a 111
20d391d7
AD		 112 if (temp & 0x100)
113 actual_temp -= 256;
114
115 return actual_temp * 1000;
21a8122a
AD		 116}
117
ce8f5370 118void r600_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 119{
120 int i;
121
ce8f5370
AD		 122 rdev->pm.dynpm_can_upclock = true;
123 rdev->pm.dynpm_can_downclock = true;
a48b9b4e
AD		 124
125 /* power state array is low to high, default is first */
126 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
127 int min_power_state_index = 0;
128
129 if (rdev->pm.num_power_states > 2)
130 min_power_state_index = 1;
131
ce8f5370
AD		 132 switch (rdev->pm.dynpm_planned_action) {
133 case DYNPM_ACTION_MINIMUM:
a48b9b4e
AD		 134 rdev->pm.requested_power_state_index = min_power_state_index;
135 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 136 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 137 break;
ce8f5370 138 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 139 if (rdev->pm.current_power_state_index == min_power_state_index) {
140 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 141 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 142 } else {
143 if (rdev->pm.active_crtc_count > 1) {
144 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 145 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 146 continue;
147 else if (i >= rdev->pm.current_power_state_index) {
148 rdev->pm.requested_power_state_index =
149 rdev->pm.current_power_state_index;
150 break;
151 } else {
152 rdev->pm.requested_power_state_index = i;
153 break;
154 }
155 }
773c3fa3
AD		 156 } else {
157 if (rdev->pm.current_power_state_index == 0)
158 rdev->pm.requested_power_state_index =
159 rdev->pm.num_power_states - 1;
160 else
161 rdev->pm.requested_power_state_index =
162 rdev->pm.current_power_state_index - 1;
163 }
a48b9b4e
AD		 164 }
165 rdev->pm.requested_clock_mode_index = 0;
d7311171
AD		 166 /* don't use the power state if crtcs are active and no display flag is set */
167 if ((rdev->pm.active_crtc_count > 0) &&
168 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
169 clock_info[rdev->pm.requested_clock_mode_index].flags &
170 RADEON_PM_MODE_NO_DISPLAY)) {
171 rdev->pm.requested_power_state_index++;
172 }
a48b9b4e 173 break;
ce8f5370 174 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 175 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
176 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 177 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 178 } else {
179 if (rdev->pm.active_crtc_count > 1) {
180 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 181 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 182 continue;
183 else if (i <= rdev->pm.current_power_state_index) {
184 rdev->pm.requested_power_state_index =
185 rdev->pm.current_power_state_index;
186 break;
187 } else {
188 rdev->pm.requested_power_state_index = i;
189 break;
190 }
191 }
192 } else
193 rdev->pm.requested_power_state_index =
194 rdev->pm.current_power_state_index + 1;
195 }
196 rdev->pm.requested_clock_mode_index = 0;
197 break;
ce8f5370 198 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 199 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
200 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 201 rdev->pm.dynpm_can_upclock = false;
58e21dff 202 break;
ce8f5370 203 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 204 default:
205 DRM_ERROR("Requested mode for not defined action\n");
206 return;
207 }
208 } else {
209 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
210 /* for now just select the first power state and switch between clock modes */
211 /* power state array is low to high, default is first (0) */
212 if (rdev->pm.active_crtc_count > 1) {
213 rdev->pm.requested_power_state_index = -1;
214 /* start at 1 as we don't want the default mode */
215 for (i = 1; i < rdev->pm.num_power_states; i++) {
d7311171 216 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 217 continue;
218 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
219 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
220 rdev->pm.requested_power_state_index = i;
221 break;
222 }
223 }
224 /* if nothing selected, grab the default state. */
225 if (rdev->pm.requested_power_state_index == -1)
226 rdev->pm.requested_power_state_index = 0;
227 } else
228 rdev->pm.requested_power_state_index = 1;
229
ce8f5370
AD		 230 switch (rdev->pm.dynpm_planned_action) {
231 case DYNPM_ACTION_MINIMUM:
a48b9b4e 232 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 233 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 234 break;
ce8f5370 235 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 236 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
237 if (rdev->pm.current_clock_mode_index == 0) {
238 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 239 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 240 } else
241 rdev->pm.requested_clock_mode_index =
242 rdev->pm.current_clock_mode_index - 1;
243 } else {
244 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 245 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 246 }
d7311171
AD		 247 /* don't use the power state if crtcs are active and no display flag is set */
248 if ((rdev->pm.active_crtc_count > 0) &&
249 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
250 clock_info[rdev->pm.requested_clock_mode_index].flags &
251 RADEON_PM_MODE_NO_DISPLAY)) {
252 rdev->pm.requested_clock_mode_index++;
253 }
a48b9b4e 254 break;
ce8f5370 255 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 256 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
257 if (rdev->pm.current_clock_mode_index ==
258 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
259 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
ce8f5370 260 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 261 } else
262 rdev->pm.requested_clock_mode_index =
263 rdev->pm.current_clock_mode_index + 1;
264 } else {
265 rdev->pm.requested_clock_mode_index =
266 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
ce8f5370 267 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 268 }
269 break;
ce8f5370 270 case DYNPM_ACTION_DEFAULT:
58e21dff
AD		 271 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
272 rdev->pm.requested_clock_mode_index = 0;
ce8f5370 273 rdev->pm.dynpm_can_upclock = false;
58e21dff 274 break;
ce8f5370 275 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 276 default:
277 DRM_ERROR("Requested mode for not defined action\n");
278 return;
279 }
280 }
281
d9fdaafb 282 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 283 rdev->pm.power_state[rdev->pm.requested_power_state_index].
284 clock_info[rdev->pm.requested_clock_mode_index].sclk,
285 rdev->pm.power_state[rdev->pm.requested_power_state_index].
286 clock_info[rdev->pm.requested_clock_mode_index].mclk,
287 rdev->pm.power_state[rdev->pm.requested_power_state_index].
288 pcie_lanes);
a48b9b4e
AD		 289}
290
ce8f5370
AD		 291void rs780_pm_init_profile(struct radeon_device *rdev)
292{
293 if (rdev->pm.num_power_states == 2) {
294 /* default */
295 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
299 /* low sh */
300 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 304 /* mid sh */
305 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 309 /* high sh */
310 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
314 /* low mh */
315 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 319 /* mid mh */
320 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 324 /* high mh */
325 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
329 } else if (rdev->pm.num_power_states == 3) {
330 /* default */
331 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
335 /* low sh */
336 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 340 /* mid sh */
341 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 345 /* high sh */
346 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
350 /* low mh */
351 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 355 /* mid mh */
356 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 360 /* high mh */
361 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
365 } else {
366 /* default */
367 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
371 /* low sh */
372 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 376 /* mid sh */
377 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 381 /* high sh */
382 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
386 /* low mh */
387 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 391 /* mid mh */
392 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 396 /* high mh */
397 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
401 }
402}
bae6b562 403
ce8f5370
AD		 404void r600_pm_init_profile(struct radeon_device *rdev)
405{
bbe26ffe
AD		 406 int idx;
407
ce8f5370
AD		 408 if (rdev->family == CHIP_R600) {
409 /* XXX */
410 /* default */
411 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
4bff5171 414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 415 /* low sh */
416 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 420 /* mid sh */
421 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 425 /* high sh */
426 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
4bff5171 429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 430 /* low mh */
431 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 435 /* mid mh */
436 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 440 /* high mh */
441 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
4bff5171 444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 445 } else {
446 if (rdev->pm.num_power_states < 4) {
447 /* default */
448 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
452 /* low sh */
4bff5171
AD		 453 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370 455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
457 /* mid sh */
458 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 462 /* high sh */
4bff5171
AD		 463 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
ce8f5370
AD		 465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
467 /* low mh */
4bff5171
AD		 468 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370 470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
c9e75b21
AD		 471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
472 /* low mh */
473 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 477 /* high mh */
4bff5171
AD		 478 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
ce8f5370
AD		 480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
482 } else {
483 /* default */
484 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
488 /* low sh */
bbe26ffe
AD		 489 if (rdev->flags & RADEON_IS_MOBILITY)
490 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
491 else
492 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
493 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21 497 /* mid sh */
bbe26ffe
AD		 498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
ce8f5370 502 /* high sh */
bbe26ffe
AD		 503 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
504 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
508 /* low mh */
bbe26ffe
AD		 509 if (rdev->flags & RADEON_IS_MOBILITY)
510 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
511 else
512 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
513 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21 517 /* mid mh */
bbe26ffe
AD		 518 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
ce8f5370 522 /* high mh */
bbe26ffe
AD		 523 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
524 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
ce8f5370
AD		 526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
528 }
529 }
bae6b562
AD		 530}
531
49e02b73
AD		 532void r600_pm_misc(struct radeon_device *rdev)
533{
a081a9d6
RM		 534 int req_ps_idx = rdev->pm.requested_power_state_index;
535 int req_cm_idx = rdev->pm.requested_clock_mode_index;
536 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
537 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
7ac9aa5a 538
4d60173f 539 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
a377e187
AD		 540 /* 0xff01 is a flag rather then an actual voltage */
541 if (voltage->voltage == 0xff01)
542 return;
4d60173f 543 if (voltage->voltage != rdev->pm.current_vddc) {
8a83ec5e 544 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 545 rdev->pm.current_vddc = voltage->voltage;
d9fdaafb 546 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 547 }
548 }
49e02b73
AD		 549}
550
def9ba9c
AD		 551bool r600_gui_idle(struct radeon_device *rdev)
552{
553 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
554 return false;
555 else
556 return true;
557}
558
e0df1ac5
AD		 559/* hpd for digital panel detect/disconnect */
560bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
561{
562 bool connected = false;
563
564 if (ASIC_IS_DCE3(rdev)) {
565 switch (hpd) {
566 case RADEON_HPD_1:
567 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
568 connected = true;
569 break;
570 case RADEON_HPD_2:
571 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
572 connected = true;
573 break;
574 case RADEON_HPD_3:
575 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
576 connected = true;
577 break;
578 case RADEON_HPD_4:
579 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
580 connected = true;
581 break;
582 /* DCE 3.2 */
583 case RADEON_HPD_5:
584 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
585 connected = true;
586 break;
587 case RADEON_HPD_6:
588 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
589 connected = true;
590 break;
591 default:
592 break;
593 }
594 } else {
595 switch (hpd) {
596 case RADEON_HPD_1:
597 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
598 connected = true;
599 break;
600 case RADEON_HPD_2:
601 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
602 connected = true;
603 break;
604 case RADEON_HPD_3:
605 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
606 connected = true;
607 break;
608 default:
609 break;
610 }
611 }
612 return connected;
613}
614
615void r600_hpd_set_polarity(struct radeon_device *rdev,
429770b3 616 enum radeon_hpd_id hpd)
e0df1ac5
AD		 617{
618 u32 tmp;
619 bool connected = r600_hpd_sense(rdev, hpd);
620
621 if (ASIC_IS_DCE3(rdev)) {
622 switch (hpd) {
623 case RADEON_HPD_1:
624 tmp = RREG32(DC_HPD1_INT_CONTROL);
625 if (connected)
626 tmp &= ~DC_HPDx_INT_POLARITY;
627 else
628 tmp |= DC_HPDx_INT_POLARITY;
629 WREG32(DC_HPD1_INT_CONTROL, tmp);
630 break;
631 case RADEON_HPD_2:
632 tmp = RREG32(DC_HPD2_INT_CONTROL);
633 if (connected)
634 tmp &= ~DC_HPDx_INT_POLARITY;
635 else
636 tmp |= DC_HPDx_INT_POLARITY;
637 WREG32(DC_HPD2_INT_CONTROL, tmp);
638 break;
639 case RADEON_HPD_3:
640 tmp = RREG32(DC_HPD3_INT_CONTROL);
641 if (connected)
642 tmp &= ~DC_HPDx_INT_POLARITY;
643 else
644 tmp |= DC_HPDx_INT_POLARITY;
645 WREG32(DC_HPD3_INT_CONTROL, tmp);
646 break;
647 case RADEON_HPD_4:
648 tmp = RREG32(DC_HPD4_INT_CONTROL);
649 if (connected)
650 tmp &= ~DC_HPDx_INT_POLARITY;
651 else
652 tmp |= DC_HPDx_INT_POLARITY;
653 WREG32(DC_HPD4_INT_CONTROL, tmp);
654 break;
655 case RADEON_HPD_5:
656 tmp = RREG32(DC_HPD5_INT_CONTROL);
657 if (connected)
658 tmp &= ~DC_HPDx_INT_POLARITY;
659 else
660 tmp |= DC_HPDx_INT_POLARITY;
661 WREG32(DC_HPD5_INT_CONTROL, tmp);
662 break;
663 /* DCE 3.2 */
664 case RADEON_HPD_6:
665 tmp = RREG32(DC_HPD6_INT_CONTROL);
666 if (connected)
667 tmp &= ~DC_HPDx_INT_POLARITY;
668 else
669 tmp |= DC_HPDx_INT_POLARITY;
670 WREG32(DC_HPD6_INT_CONTROL, tmp);
671 break;
672 default:
673 break;
674 }
675 } else {
676 switch (hpd) {
677 case RADEON_HPD_1:
678 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
679 if (connected)
680 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
681 else
682 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
683 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
684 break;
685 case RADEON_HPD_2:
686 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
687 if (connected)
688 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
689 else
690 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
691 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
692 break;
693 case RADEON_HPD_3:
694 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
695 if (connected)
696 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
697 else
698 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
699 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
700 break;
701 default:
702 break;
703 }
704 }
705}
706
707void r600_hpd_init(struct radeon_device *rdev)
708{
709 struct drm_device *dev = rdev->ddev;
710 struct drm_connector *connector;
711
64912e99
AD		 712 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
713 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
714
715 if (ASIC_IS_DCE3(rdev)) {
716 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
717 if (ASIC_IS_DCE32(rdev))
718 tmp |= DC_HPDx_EN;
e0df1ac5 719
e0df1ac5
AD		 720 switch (radeon_connector->hpd.hpd) {
721 case RADEON_HPD_1:
722 WREG32(DC_HPD1_CONTROL, tmp);
723 rdev->irq.hpd[0] = true;
724 break;
725 case RADEON_HPD_2:
726 WREG32(DC_HPD2_CONTROL, tmp);
727 rdev->irq.hpd[1] = true;
728 break;
729 case RADEON_HPD_3:
730 WREG32(DC_HPD3_CONTROL, tmp);
731 rdev->irq.hpd[2] = true;
732 break;
733 case RADEON_HPD_4:
734 WREG32(DC_HPD4_CONTROL, tmp);
735 rdev->irq.hpd[3] = true;
736 break;
737 /* DCE 3.2 */
738 case RADEON_HPD_5:
739 WREG32(DC_HPD5_CONTROL, tmp);
740 rdev->irq.hpd[4] = true;
741 break;
742 case RADEON_HPD_6:
743 WREG32(DC_HPD6_CONTROL, tmp);
744 rdev->irq.hpd[5] = true;
745 break;
746 default:
747 break;
748 }
64912e99 749 } else {
e0df1ac5
AD		 750 switch (radeon_connector->hpd.hpd) {
751 case RADEON_HPD_1:
752 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
753 rdev->irq.hpd[0] = true;
754 break;
755 case RADEON_HPD_2:
756 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
757 rdev->irq.hpd[1] = true;
758 break;
759 case RADEON_HPD_3:
760 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
761 rdev->irq.hpd[2] = true;
762 break;
763 default:
764 break;
765 }
766 }
64912e99 767 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
e0df1ac5 768 }
003e69f9
JG		 769 if (rdev->irq.installed)
770 r600_irq_set(rdev);
e0df1ac5
AD		 771}
772
773void r600_hpd_fini(struct radeon_device *rdev)
774{
775 struct drm_device *dev = rdev->ddev;
776 struct drm_connector *connector;
777
778 if (ASIC_IS_DCE3(rdev)) {
779 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
780 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
781 switch (radeon_connector->hpd.hpd) {
782 case RADEON_HPD_1:
783 WREG32(DC_HPD1_CONTROL, 0);
784 rdev->irq.hpd[0] = false;
785 break;
786 case RADEON_HPD_2:
787 WREG32(DC_HPD2_CONTROL, 0);
788 rdev->irq.hpd[1] = false;
789 break;
790 case RADEON_HPD_3:
791 WREG32(DC_HPD3_CONTROL, 0);
792 rdev->irq.hpd[2] = false;
793 break;
794 case RADEON_HPD_4:
795 WREG32(DC_HPD4_CONTROL, 0);
796 rdev->irq.hpd[3] = false;
797 break;
798 /* DCE 3.2 */
799 case RADEON_HPD_5:
800 WREG32(DC_HPD5_CONTROL, 0);
801 rdev->irq.hpd[4] = false;
802 break;
803 case RADEON_HPD_6:
804 WREG32(DC_HPD6_CONTROL, 0);
805 rdev->irq.hpd[5] = false;
806 break;
807 default:
808 break;
809 }
810 }
811 } else {
812 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
813 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
814 switch (radeon_connector->hpd.hpd) {
815 case RADEON_HPD_1:
816 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
817 rdev->irq.hpd[0] = false;
818 break;
819 case RADEON_HPD_2:
820 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
821 rdev->irq.hpd[1] = false;
822 break;
823 case RADEON_HPD_3:
824 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
825 rdev->irq.hpd[2] = false;
826 break;
827 default:
828 break;
829 }
830 }
831 }
832}
833
771fe6b9 834/*
3ce0a23d 835 * R600 PCIE GART
771fe6b9 836 */
3ce0a23d
JG		 837void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
838{
839 unsigned i;
840 u32 tmp;
841
2e98f10a 842 /* flush hdp cache so updates hit vram */
f3886f85
AD		 843 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
844 !(rdev->flags & RADEON_IS_AGP)) {
c9a1be96 845 void __iomem *ptr = (void *)rdev->gart.ptr;
812d0469
AD		 846 u32 tmp;
847
848 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
849 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
f3886f85
AD		 850 * This seems to cause problems on some AGP cards. Just use the old
851 * method for them.
812d0469
AD		 852 */
853 WREG32(HDP_DEBUG1, 0);
854 tmp = readl((void __iomem *)ptr);
855 } else
856 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2e98f10a 857
3ce0a23d
JG		 858 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
859 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
860 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
861 for (i = 0; i < rdev->usec_timeout; i++) {
862 /* read MC_STATUS */
863 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
864 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
865 if (tmp == 2) {
866 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
867 return;
868 }
869 if (tmp) {
870 return;
871 }
872 udelay(1);
873 }
874}
875
4aac0473 876int r600_pcie_gart_init(struct radeon_device *rdev)
3ce0a23d 877{
4aac0473 878 int r;
3ce0a23d 879
c9a1be96 880 if (rdev->gart.robj) {
fce7d61b 881 WARN(1, "R600 PCIE GART already initialized\n");
4aac0473
JG		 882 return 0;
883 }
3ce0a23d
JG		 884 /* Initialize common gart structure */
885 r = radeon_gart_init(rdev);
4aac0473 886 if (r)
3ce0a23d 887 return r;
3ce0a23d 888 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
4aac0473
JG		 889 return radeon_gart_table_vram_alloc(rdev);
890}
891
892int r600_pcie_gart_enable(struct radeon_device *rdev)
893{
894 u32 tmp;
895 int r, i;
896
c9a1be96 897 if (rdev->gart.robj == NULL) {
4aac0473
JG		 898 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
899 return -EINVAL;
771fe6b9 900 }
4aac0473
JG		 901 r = radeon_gart_table_vram_pin(rdev);
902 if (r)
903 return r;
82568565 904 radeon_gart_restore(rdev);
bc1a631e 905
3ce0a23d
JG		 906 /* Setup L2 cache */
907 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
908 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
909 EFFECTIVE_L2_QUEUE_SIZE(7));
910 WREG32(VM_L2_CNTL2, 0);
911 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
912 /* Setup TLB control */
913 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
914 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
915 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
916 ENABLE_WAIT_L2_QUERY;
917 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
918 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
919 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
920 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
921 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
922 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
923 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
924 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
925 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
926 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
927 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
928 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
929 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
930 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
931 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1a029b76 932 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3ce0a23d
JG		 933 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
934 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
935 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
936 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
937 (u32)(rdev->dummy_page.addr >> 12));
938 for (i = 1; i < 7; i++)
939 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 940
3ce0a23d 941 r600_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 942 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
943 (unsigned)(rdev->mc.gtt_size >> 20),
944 (unsigned long long)rdev->gart.table_addr);
3ce0a23d 945 rdev->gart.ready = true;
771fe6b9
JG		 946 return 0;
947}
948
3ce0a23d 949void r600_pcie_gart_disable(struct radeon_device *rdev)
771fe6b9 950{
3ce0a23d 951 u32 tmp;
c9a1be96 952 int i;
771fe6b9 953
3ce0a23d
JG		 954 /* Disable all tables */
955 for (i = 0; i < 7; i++)
956 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
771fe6b9 957
3ce0a23d
JG		 958 /* Disable L2 cache */
959 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
960 EFFECTIVE_L2_QUEUE_SIZE(7));
961 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
962 /* Setup L1 TLB control */
963 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
964 ENABLE_WAIT_L2_QUERY;
965 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
966 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
967 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
968 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
971 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
972 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
973 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
974 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
c9a1be96 979 radeon_gart_table_vram_unpin(rdev);
4aac0473
JG		 980}
981
982void r600_pcie_gart_fini(struct radeon_device *rdev)
983{
f9274562 984 radeon_gart_fini(rdev);
4aac0473
JG		 985 r600_pcie_gart_disable(rdev);
986 radeon_gart_table_vram_free(rdev);
771fe6b9
JG		 987}
988
1a029b76
JG		 989void r600_agp_enable(struct radeon_device *rdev)
990{
991 u32 tmp;
992 int i;
993
994 /* Setup L2 cache */
995 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
996 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
997 EFFECTIVE_L2_QUEUE_SIZE(7));
998 WREG32(VM_L2_CNTL2, 0);
999 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1000 /* Setup TLB control */
1001 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1002 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1003 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1004 ENABLE_WAIT_L2_QUERY;
1005 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1006 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1007 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1008 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1009 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1010 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1011 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1012 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1013 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1014 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1015 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1016 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1017 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1018 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1019 for (i = 0; i < 7; i++)
1020 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1021}
1022
771fe6b9
JG		 1023int r600_mc_wait_for_idle(struct radeon_device *rdev)
1024{
3ce0a23d
JG		 1025 unsigned i;
1026 u32 tmp;
1027
1028 for (i = 0; i < rdev->usec_timeout; i++) {
1029 /* read MC_STATUS */
1030 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1031 if (!tmp)
1032 return 0;
1033 udelay(1);
1034 }
1035 return -1;
771fe6b9
JG		 1036}
1037
a3c1945a 1038static void r600_mc_program(struct radeon_device *rdev)
771fe6b9 1039{
a3c1945a 1040 struct rv515_mc_save save;
3ce0a23d
JG		 1041 u32 tmp;
1042 int i, j;
771fe6b9 1043
3ce0a23d
JG		 1044 /* Initialize HDP */
1045 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1046 WREG32((0x2c14 + j), 0x00000000);
1047 WREG32((0x2c18 + j), 0x00000000);
1048 WREG32((0x2c1c + j), 0x00000000);
1049 WREG32((0x2c20 + j), 0x00000000);
1050 WREG32((0x2c24 + j), 0x00000000);
1051 }
1052 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
771fe6b9 1053
a3c1945a 1054 rv515_mc_stop(rdev, &save);
3ce0a23d 1055 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1056 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1057 }
a3c1945a 1058 /* Lockout access through VGA aperture (doesn't exist before R600) */
3ce0a23d 1059 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
3ce0a23d 1060 /* Update configuration */
1a029b76
JG		 1061 if (rdev->flags & RADEON_IS_AGP) {
1062 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1063 /* VRAM before AGP */
1064 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1065 rdev->mc.vram_start >> 12);
1066 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1067 rdev->mc.gtt_end >> 12);
1068 } else {
1069 /* VRAM after AGP */
1070 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1071 rdev->mc.gtt_start >> 12);
1072 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1073 rdev->mc.vram_end >> 12);
1074 }
1075 } else {
1076 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1077 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1078 }
16cdf04d 1079 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1a029b76 1080 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
3ce0a23d
JG		 1081 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1082 WREG32(MC_VM_FB_LOCATION, tmp);
1083 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1084 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1085 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
3ce0a23d 1086 if (rdev->flags & RADEON_IS_AGP) {
1a029b76
JG		 1087 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1088 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
3ce0a23d
JG		 1089 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1090 } else {
1091 WREG32(MC_VM_AGP_BASE, 0);
1092 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1093 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1094 }
3ce0a23d 1095 if (r600_mc_wait_for_idle(rdev)) {
a3c1945a 1096 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3ce0a23d 1097 }
a3c1945a 1098 rv515_mc_resume(rdev, &save);
698443d9
DA		 1099 /* we need to own VRAM, so turn off the VGA renderer here
1100 * to stop it overwriting our objects */
d39c3b89 1101 rv515_vga_render_disable(rdev);
3ce0a23d
JG		 1102}
1103
d594e46a
JG		 1104/**
1105 * r600_vram_gtt_location - try to find VRAM & GTT location
1106 * @rdev: radeon device structure holding all necessary informations
1107 * @mc: memory controller structure holding memory informations
1108 *
1109 * Function will place try to place VRAM at same place as in CPU (PCI)
1110 * address space as some GPU seems to have issue when we reprogram at
1111 * different address space.
1112 *
1113 * If there is not enough space to fit the unvisible VRAM after the
1114 * aperture then we limit the VRAM size to the aperture.
1115 *
1116 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1117 * them to be in one from GPU point of view so that we can program GPU to
1118 * catch access outside them (weird GPU policy see ??).
1119 *
1120 * This function will never fails, worst case are limiting VRAM or GTT.
1121 *
1122 * Note: GTT start, end, size should be initialized before calling this
1123 * function on AGP platform.
1124 */
0ef0c1f7 1125static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
d594e46a
JG		 1126{
1127 u64 size_bf, size_af;
1128
1129 if (mc->mc_vram_size > 0xE0000000) {
1130 /* leave room for at least 512M GTT */
1131 dev_warn(rdev->dev, "limiting VRAM\n");
1132 mc->real_vram_size = 0xE0000000;
1133 mc->mc_vram_size = 0xE0000000;
1134 }
1135 if (rdev->flags & RADEON_IS_AGP) {
1136 size_bf = mc->gtt_start;
1137 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1138 if (size_bf > size_af) {
1139 if (mc->mc_vram_size > size_bf) {
1140 dev_warn(rdev->dev, "limiting VRAM\n");
1141 mc->real_vram_size = size_bf;
1142 mc->mc_vram_size = size_bf;
1143 }
1144 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1145 } else {
1146 if (mc->mc_vram_size > size_af) {
1147 dev_warn(rdev->dev, "limiting VRAM\n");
1148 mc->real_vram_size = size_af;
1149 mc->mc_vram_size = size_af;
1150 }
1151 mc->vram_start = mc->gtt_end;
1152 }
1153 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1154 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1155 mc->mc_vram_size >> 20, mc->vram_start,
1156 mc->vram_end, mc->real_vram_size >> 20);
1157 } else {
1158 u64 base = 0;
8961d52d
AD		 1159 if (rdev->flags & RADEON_IS_IGP) {
1160 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1161 base <<= 24;
1162 }
d594e46a 1163 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 1164 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 1165 radeon_gtt_location(rdev, mc);
1166 }
1167}
1168
3ce0a23d 1169int r600_mc_init(struct radeon_device *rdev)
771fe6b9 1170{
3ce0a23d 1171 u32 tmp;
5885b7a9 1172 int chansize, numchan;
771fe6b9 1173
3ce0a23d 1174 /* Get VRAM informations */
771fe6b9 1175 rdev->mc.vram_is_ddr = true;
3ce0a23d
JG		 1176 tmp = RREG32(RAMCFG);
1177 if (tmp & CHANSIZE_OVERRIDE) {
771fe6b9 1178 chansize = 16;
3ce0a23d 1179 } else if (tmp & CHANSIZE_MASK) {
771fe6b9
JG		 1180 chansize = 64;
1181 } else {
1182 chansize = 32;
1183 }
5885b7a9
AD		 1184 tmp = RREG32(CHMAP);
1185 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1186 case 0:
1187 default:
1188 numchan = 1;
1189 break;
1190 case 1:
1191 numchan = 2;
1192 break;
1193 case 2:
1194 numchan = 4;
1195 break;
1196 case 3:
1197 numchan = 8;
1198 break;
771fe6b9 1199 }
5885b7a9 1200 rdev->mc.vram_width = numchan * chansize;
3ce0a23d 1201 /* Could aper size report 0 ? */
01d73a69
JC		 1202 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1203 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3ce0a23d
JG		 1204 /* Setup GPU memory space */
1205 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1206 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
51e5fcd3 1207 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a 1208 r600_vram_gtt_location(rdev, &rdev->mc);
f47299c5 1209
f892034a
AD		 1210 if (rdev->flags & RADEON_IS_IGP) {
1211 rs690_pm_info(rdev);
06b6476d 1212 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
f892034a 1213 }
f47299c5 1214 radeon_update_bandwidth_info(rdev);
3ce0a23d 1215 return 0;
771fe6b9
JG		 1216}
1217
16cdf04d
AD		 1218int r600_vram_scratch_init(struct radeon_device *rdev)
1219{
1220 int r;
1221
1222 if (rdev->vram_scratch.robj == NULL) {
1223 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1224 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1225 &rdev->vram_scratch.robj);
1226 if (r) {
1227 return r;
1228 }
1229 }
1230
1231 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1232 if (unlikely(r != 0))
1233 return r;
1234 r = radeon_bo_pin(rdev->vram_scratch.robj,
1235 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1236 if (r) {
1237 radeon_bo_unreserve(rdev->vram_scratch.robj);
1238 return r;
1239 }
1240 r = radeon_bo_kmap(rdev->vram_scratch.robj,
1241 (void **)&rdev->vram_scratch.ptr);
1242 if (r)
1243 radeon_bo_unpin(rdev->vram_scratch.robj);
1244 radeon_bo_unreserve(rdev->vram_scratch.robj);
1245
1246 return r;
1247}
1248
1249void r600_vram_scratch_fini(struct radeon_device *rdev)
1250{
1251 int r;
1252
1253 if (rdev->vram_scratch.robj == NULL) {
1254 return;
1255 }
1256 r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1257 if (likely(r == 0)) {
1258 radeon_bo_kunmap(rdev->vram_scratch.robj);
1259 radeon_bo_unpin(rdev->vram_scratch.robj);
1260 radeon_bo_unreserve(rdev->vram_scratch.robj);
1261 }
1262 radeon_bo_unref(&rdev->vram_scratch.robj);
1263}
1264
3ce0a23d
JG		 1265/* We doesn't check that the GPU really needs a reset we simply do the
1266 * reset, it's up to the caller to determine if the GPU needs one. We
1267 * might add an helper function to check that.
1268 */
1269int r600_gpu_soft_reset(struct radeon_device *rdev)
771fe6b9 1270{
a3c1945a 1271 struct rv515_mc_save save;
3ce0a23d
JG		 1272 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1273 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1274 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1275 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1276 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1277 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1278 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1279 S_008010_GUI_ACTIVE(1);
1280 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1281 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1282 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1283 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1284 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1285 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1286 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1287 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
a3c1945a 1288 u32 tmp;
771fe6b9 1289
8d96fe93
AD		 1290 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1291 return 0;
1292
1a029b76
JG		 1293 dev_info(rdev->dev, "GPU softreset \n");
1294 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1295 RREG32(R_008010_GRBM_STATUS));
1296 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
a3c1945a 1297 RREG32(R_008014_GRBM_STATUS2));
1a029b76
JG		 1298 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1299 RREG32(R_000E50_SRBM_STATUS));
a3c1945a
JG		 1300 rv515_mc_stop(rdev, &save);
1301 if (r600_mc_wait_for_idle(rdev)) {
1302 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1303 }
3ce0a23d 1304 /* Disable CP parsing/prefetching */
90aca4d2 1305 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
3ce0a23d
JG		 1306 /* Check if any of the rendering block is busy and reset it */
1307 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1308 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
a3c1945a 1309 tmp = S_008020_SOFT_RESET_CR(1) |
3ce0a23d
JG		 1310 S_008020_SOFT_RESET_DB(1) |
1311 S_008020_SOFT_RESET_CB(1) |
1312 S_008020_SOFT_RESET_PA(1) |
1313 S_008020_SOFT_RESET_SC(1) |
1314 S_008020_SOFT_RESET_SMX(1) |
1315 S_008020_SOFT_RESET_SPI(1) |
1316 S_008020_SOFT_RESET_SX(1) |
1317 S_008020_SOFT_RESET_SH(1) |
1318 S_008020_SOFT_RESET_TC(1) |
1319 S_008020_SOFT_RESET_TA(1) |
1320 S_008020_SOFT_RESET_VC(1) |
a3c1945a 1321 S_008020_SOFT_RESET_VGT(1);
1a029b76 1322 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
a3c1945a 1323 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1324 RREG32(R_008020_GRBM_SOFT_RESET);
1325 mdelay(15);
3ce0a23d 1326 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d
JG		 1327 }
1328 /* Reset CP (we always reset CP) */
a3c1945a
JG		 1329 tmp = S_008020_SOFT_RESET_CP(1);
1330 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1331 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
90aca4d2
JG		 1332 RREG32(R_008020_GRBM_SOFT_RESET);
1333 mdelay(15);
3ce0a23d 1334 WREG32(R_008020_GRBM_SOFT_RESET, 0);
3ce0a23d 1335 /* Wait a little for things to settle down */
225758d8 1336 mdelay(1);
1a029b76
JG		 1337 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1338 RREG32(R_008010_GRBM_STATUS));
1339 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1340 RREG32(R_008014_GRBM_STATUS2));
1341 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1342 RREG32(R_000E50_SRBM_STATUS));
a3c1945a 1343 rv515_mc_resume(rdev, &save);
3ce0a23d
JG		 1344 return 0;
1345}
1346
e32eb50d 1347bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8
JG		 1348{
1349 u32 srbm_status;
1350 u32 grbm_status;
1351 u32 grbm_status2;
e29ff729 1352 struct r100_gpu_lockup *lockup;
225758d8
JG		 1353 int r;
1354
e29ff729
AD		 1355 if (rdev->family >= CHIP_RV770)
1356 lockup = &rdev->config.rv770.lockup;
1357 else
1358 lockup = &rdev->config.r600.lockup;
1359
225758d8
JG		 1360 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1361 grbm_status = RREG32(R_008010_GRBM_STATUS);
1362 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1363 if (!G_008010_GUI_ACTIVE(grbm_status)) {
e32eb50d 1364 r100_gpu_lockup_update(lockup, ring);
225758d8
JG		 1365 return false;
1366 }
1367 /* force CP activities */
e32eb50d 1368 r = radeon_ring_lock(rdev, ring, 2);
225758d8
JG		 1369 if (!r) {
1370 /* PACKET2 NOP */
e32eb50d
CK		 1371 radeon_ring_write(ring, 0x80000000);
1372 radeon_ring_write(ring, 0x80000000);
1373 radeon_ring_unlock_commit(rdev, ring);
225758d8 1374 }
e32eb50d
CK		 1375 ring->rptr = RREG32(ring->rptr_reg);
1376 return r100_gpu_cp_is_lockup(rdev, lockup, ring);
225758d8
JG		 1377}
1378
a2d07b74 1379int r600_asic_reset(struct radeon_device *rdev)
3ce0a23d
JG		 1380{
1381 return r600_gpu_soft_reset(rdev);
1382}
1383
1384static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1385 u32 num_backends,
1386 u32 backend_disable_mask)
1387{
1388 u32 backend_map = 0;
1389 u32 enabled_backends_mask;
1390 u32 enabled_backends_count;
1391 u32 cur_pipe;
1392 u32 swizzle_pipe[R6XX_MAX_PIPES];
1393 u32 cur_backend;
1394 u32 i;
1395
1396 if (num_tile_pipes > R6XX_MAX_PIPES)
1397 num_tile_pipes = R6XX_MAX_PIPES;
1398 if (num_tile_pipes < 1)
1399 num_tile_pipes = 1;
1400 if (num_backends > R6XX_MAX_BACKENDS)
1401 num_backends = R6XX_MAX_BACKENDS;
1402 if (num_backends < 1)
1403 num_backends = 1;
1404
1405 enabled_backends_mask = 0;
1406 enabled_backends_count = 0;
1407 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1408 if (((backend_disable_mask >> i) & 1) == 0) {
1409 enabled_backends_mask |= (1 << i);
1410 ++enabled_backends_count;
1411 }
1412 if (enabled_backends_count == num_backends)
1413 break;
1414 }
1415
1416 if (enabled_backends_count == 0) {
1417 enabled_backends_mask = 1;
1418 enabled_backends_count = 1;
1419 }
1420
1421 if (enabled_backends_count != num_backends)
1422 num_backends = enabled_backends_count;
1423
1424 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1425 switch (num_tile_pipes) {
1426 case 1:
1427 swizzle_pipe[0] = 0;
1428 break;
1429 case 2:
1430 swizzle_pipe[0] = 0;
1431 swizzle_pipe[1] = 1;
1432 break;
1433 case 3:
1434 swizzle_pipe[0] = 0;
1435 swizzle_pipe[1] = 1;
1436 swizzle_pipe[2] = 2;
1437 break;
1438 case 4:
1439 swizzle_pipe[0] = 0;
1440 swizzle_pipe[1] = 1;
1441 swizzle_pipe[2] = 2;
1442 swizzle_pipe[3] = 3;
1443 break;
1444 case 5:
1445 swizzle_pipe[0] = 0;
1446 swizzle_pipe[1] = 1;
1447 swizzle_pipe[2] = 2;
1448 swizzle_pipe[3] = 3;
1449 swizzle_pipe[4] = 4;
1450 break;
1451 case 6:
1452 swizzle_pipe[0] = 0;
1453 swizzle_pipe[1] = 2;
1454 swizzle_pipe[2] = 4;
1455 swizzle_pipe[3] = 5;
1456 swizzle_pipe[4] = 1;
1457 swizzle_pipe[5] = 3;
1458 break;
1459 case 7:
1460 swizzle_pipe[0] = 0;
1461 swizzle_pipe[1] = 2;
1462 swizzle_pipe[2] = 4;
1463 swizzle_pipe[3] = 6;
1464 swizzle_pipe[4] = 1;
1465 swizzle_pipe[5] = 3;
1466 swizzle_pipe[6] = 5;
1467 break;
1468 case 8:
1469 swizzle_pipe[0] = 0;
1470 swizzle_pipe[1] = 2;
1471 swizzle_pipe[2] = 4;
1472 swizzle_pipe[3] = 6;
1473 swizzle_pipe[4] = 1;
1474 swizzle_pipe[5] = 3;
1475 swizzle_pipe[6] = 5;
1476 swizzle_pipe[7] = 7;
1477 break;
1478 }
1479
1480 cur_backend = 0;
1481 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1482 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1483 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1484
1485 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1486
1487 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1488 }
1489
1490 return backend_map;
1491}
1492
1493int r600_count_pipe_bits(uint32_t val)
1494{
1495 int i, ret = 0;
1496
1497 for (i = 0; i < 32; i++) {
1498 ret += val & 1;
1499 val >>= 1;
1500 }
1501 return ret;
771fe6b9
JG		 1502}
1503
3ce0a23d
JG		 1504void r600_gpu_init(struct radeon_device *rdev)
1505{
1506 u32 tiling_config;
1507 u32 ramcfg;
d03f5d59
AD		 1508 u32 backend_map;
1509 u32 cc_rb_backend_disable;
1510 u32 cc_gc_shader_pipe_config;
3ce0a23d
JG		 1511 u32 tmp;
1512 int i, j;
1513 u32 sq_config;
1514 u32 sq_gpr_resource_mgmt_1 = 0;
1515 u32 sq_gpr_resource_mgmt_2 = 0;
1516 u32 sq_thread_resource_mgmt = 0;
1517 u32 sq_stack_resource_mgmt_1 = 0;
1518 u32 sq_stack_resource_mgmt_2 = 0;
1519
1520 /* FIXME: implement */
1521 switch (rdev->family) {
1522 case CHIP_R600:
1523 rdev->config.r600.max_pipes = 4;
1524 rdev->config.r600.max_tile_pipes = 8;
1525 rdev->config.r600.max_simds = 4;
1526 rdev->config.r600.max_backends = 4;
1527 rdev->config.r600.max_gprs = 256;
1528 rdev->config.r600.max_threads = 192;
1529 rdev->config.r600.max_stack_entries = 256;
1530 rdev->config.r600.max_hw_contexts = 8;
1531 rdev->config.r600.max_gs_threads = 16;
1532 rdev->config.r600.sx_max_export_size = 128;
1533 rdev->config.r600.sx_max_export_pos_size = 16;
1534 rdev->config.r600.sx_max_export_smx_size = 128;
1535 rdev->config.r600.sq_num_cf_insts = 2;
1536 break;
1537 case CHIP_RV630:
1538 case CHIP_RV635:
1539 rdev->config.r600.max_pipes = 2;
1540 rdev->config.r600.max_tile_pipes = 2;
1541 rdev->config.r600.max_simds = 3;
1542 rdev->config.r600.max_backends = 1;
1543 rdev->config.r600.max_gprs = 128;
1544 rdev->config.r600.max_threads = 192;
1545 rdev->config.r600.max_stack_entries = 128;
1546 rdev->config.r600.max_hw_contexts = 8;
1547 rdev->config.r600.max_gs_threads = 4;
1548 rdev->config.r600.sx_max_export_size = 128;
1549 rdev->config.r600.sx_max_export_pos_size = 16;
1550 rdev->config.r600.sx_max_export_smx_size = 128;
1551 rdev->config.r600.sq_num_cf_insts = 2;
1552 break;
1553 case CHIP_RV610:
1554 case CHIP_RV620:
1555 case CHIP_RS780:
1556 case CHIP_RS880:
1557 rdev->config.r600.max_pipes = 1;
1558 rdev->config.r600.max_tile_pipes = 1;
1559 rdev->config.r600.max_simds = 2;
1560 rdev->config.r600.max_backends = 1;
1561 rdev->config.r600.max_gprs = 128;
1562 rdev->config.r600.max_threads = 192;
1563 rdev->config.r600.max_stack_entries = 128;
1564 rdev->config.r600.max_hw_contexts = 4;
1565 rdev->config.r600.max_gs_threads = 4;
1566 rdev->config.r600.sx_max_export_size = 128;
1567 rdev->config.r600.sx_max_export_pos_size = 16;
1568 rdev->config.r600.sx_max_export_smx_size = 128;
1569 rdev->config.r600.sq_num_cf_insts = 1;
1570 break;
1571 case CHIP_RV670:
1572 rdev->config.r600.max_pipes = 4;
1573 rdev->config.r600.max_tile_pipes = 4;
1574 rdev->config.r600.max_simds = 4;
1575 rdev->config.r600.max_backends = 4;
1576 rdev->config.r600.max_gprs = 192;
1577 rdev->config.r600.max_threads = 192;
1578 rdev->config.r600.max_stack_entries = 256;
1579 rdev->config.r600.max_hw_contexts = 8;
1580 rdev->config.r600.max_gs_threads = 16;
1581 rdev->config.r600.sx_max_export_size = 128;
1582 rdev->config.r600.sx_max_export_pos_size = 16;
1583 rdev->config.r600.sx_max_export_smx_size = 128;
1584 rdev->config.r600.sq_num_cf_insts = 2;
1585 break;
1586 default:
1587 break;
1588 }
1589
1590 /* Initialize HDP */
1591 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1592 WREG32((0x2c14 + j), 0x00000000);
1593 WREG32((0x2c18 + j), 0x00000000);
1594 WREG32((0x2c1c + j), 0x00000000);
1595 WREG32((0x2c20 + j), 0x00000000);
1596 WREG32((0x2c24 + j), 0x00000000);
1597 }
1598
1599 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1600
1601 /* Setup tiling */
1602 tiling_config = 0;
1603 ramcfg = RREG32(RAMCFG);
1604 switch (rdev->config.r600.max_tile_pipes) {
1605 case 1:
1606 tiling_config |= PIPE_TILING(0);
1607 break;
1608 case 2:
1609 tiling_config |= PIPE_TILING(1);
1610 break;
1611 case 4:
1612 tiling_config |= PIPE_TILING(2);
1613 break;
1614 case 8:
1615 tiling_config |= PIPE_TILING(3);
1616 break;
1617 default:
1618 break;
1619 }
d03f5d59 1620 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
961fb597 1621 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
3ce0a23d 1622 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
881fe6c1
AD		 1623 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1624 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1625 rdev->config.r600.tiling_group_size = 512;
1626 else
1627 rdev->config.r600.tiling_group_size = 256;
3ce0a23d
JG		 1628 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1629 if (tmp > 3) {
1630 tiling_config |= ROW_TILING(3);
1631 tiling_config |= SAMPLE_SPLIT(3);
1632 } else {
1633 tiling_config |= ROW_TILING(tmp);
1634 tiling_config |= SAMPLE_SPLIT(tmp);
1635 }
1636 tiling_config |= BANK_SWAPS(1);
d03f5d59
AD		 1637
1638 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1639 cc_rb_backend_disable |=
1640 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1641
1642 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1643 cc_gc_shader_pipe_config |=
1644 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1645 cc_gc_shader_pipe_config |=
1646 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1647
1648 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1649 (R6XX_MAX_BACKENDS -
1650 r600_count_pipe_bits((cc_rb_backend_disable &
1651 R6XX_MAX_BACKENDS_MASK) >> 16)),
1652 (cc_rb_backend_disable >> 16));
e7aeeba6 1653 rdev->config.r600.tile_config = tiling_config;
e55b9422 1654 rdev->config.r600.backend_map = backend_map;
d03f5d59 1655 tiling_config |= BACKEND_MAP(backend_map);
3ce0a23d
JG		 1656 WREG32(GB_TILING_CONFIG, tiling_config);
1657 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1658 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1659
3ce0a23d 1660 /* Setup pipes */
d03f5d59
AD		 1661 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1662 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1663 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
3ce0a23d 1664
d03f5d59 1665 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
3ce0a23d
JG		 1666 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1667 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1668
1669 /* Setup some CP states */
1670 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1671 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1672
1673 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1674 SYNC_WALKER | SYNC_ALIGNER));
1675 /* Setup various GPU states */
1676 if (rdev->family == CHIP_RV670)
1677 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1678
1679 tmp = RREG32(SX_DEBUG_1);
1680 tmp |= SMX_EVENT_RELEASE;
1681 if ((rdev->family > CHIP_R600))
1682 tmp |= ENABLE_NEW_SMX_ADDRESS;
1683 WREG32(SX_DEBUG_1, tmp);
1684
1685 if (((rdev->family) == CHIP_R600) ||
1686 ((rdev->family) == CHIP_RV630) ||
1687 ((rdev->family) == CHIP_RV610) ||
1688 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1689 ((rdev->family) == CHIP_RS780) ||
1690 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1691 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1692 } else {
1693 WREG32(DB_DEBUG, 0);
1694 }
1695 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1696 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1697
1698 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1699 WREG32(VGT_NUM_INSTANCES, 0);
1700
1701 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1702 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1703
1704 tmp = RREG32(SQ_MS_FIFO_SIZES);
1705 if (((rdev->family) == CHIP_RV610) ||
1706 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1707 ((rdev->family) == CHIP_RS780) ||
1708 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1709 tmp = (CACHE_FIFO_SIZE(0xa) |
1710 FETCH_FIFO_HIWATER(0xa) |
1711 DONE_FIFO_HIWATER(0xe0) |
1712 ALU_UPDATE_FIFO_HIWATER(0x8));
1713 } else if (((rdev->family) == CHIP_R600) ||
1714 ((rdev->family) == CHIP_RV630)) {
1715 tmp &= ~DONE_FIFO_HIWATER(0xff);
1716 tmp |= DONE_FIFO_HIWATER(0x4);
1717 }
1718 WREG32(SQ_MS_FIFO_SIZES, tmp);
1719
1720 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1721 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1722 */
1723 sq_config = RREG32(SQ_CONFIG);
1724 sq_config &= ~(PS_PRIO(3) |
1725 VS_PRIO(3) |
1726 GS_PRIO(3) |
1727 ES_PRIO(3));
1728 sq_config |= (DX9_CONSTS |
1729 VC_ENABLE |
1730 PS_PRIO(0) |
1731 VS_PRIO(1) |
1732 GS_PRIO(2) |
1733 ES_PRIO(3));
1734
1735 if ((rdev->family) == CHIP_R600) {
1736 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1737 NUM_VS_GPRS(124) |
1738 NUM_CLAUSE_TEMP_GPRS(4));
1739 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1740 NUM_ES_GPRS(0));
1741 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1742 NUM_VS_THREADS(48) |
1743 NUM_GS_THREADS(4) |
1744 NUM_ES_THREADS(4));
1745 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1746 NUM_VS_STACK_ENTRIES(128));
1747 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1748 NUM_ES_STACK_ENTRIES(0));
1749 } else if (((rdev->family) == CHIP_RV610) ||
1750 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1751 ((rdev->family) == CHIP_RS780) ||
1752 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1753 /* no vertex cache */
1754 sq_config &= ~VC_ENABLE;
1755
1756 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1757 NUM_VS_GPRS(44) |
1758 NUM_CLAUSE_TEMP_GPRS(2));
1759 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1760 NUM_ES_GPRS(17));
1761 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1762 NUM_VS_THREADS(78) |
1763 NUM_GS_THREADS(4) |
1764 NUM_ES_THREADS(31));
1765 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1766 NUM_VS_STACK_ENTRIES(40));
1767 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1768 NUM_ES_STACK_ENTRIES(16));
1769 } else if (((rdev->family) == CHIP_RV630) ||
1770 ((rdev->family) == CHIP_RV635)) {
1771 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1772 NUM_VS_GPRS(44) |
1773 NUM_CLAUSE_TEMP_GPRS(2));
1774 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1775 NUM_ES_GPRS(18));
1776 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1777 NUM_VS_THREADS(78) |
1778 NUM_GS_THREADS(4) |
1779 NUM_ES_THREADS(31));
1780 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1781 NUM_VS_STACK_ENTRIES(40));
1782 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1783 NUM_ES_STACK_ENTRIES(16));
1784 } else if ((rdev->family) == CHIP_RV670) {
1785 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1786 NUM_VS_GPRS(44) |
1787 NUM_CLAUSE_TEMP_GPRS(2));
1788 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1789 NUM_ES_GPRS(17));
1790 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1791 NUM_VS_THREADS(78) |
1792 NUM_GS_THREADS(4) |
1793 NUM_ES_THREADS(31));
1794 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1795 NUM_VS_STACK_ENTRIES(64));
1796 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1797 NUM_ES_STACK_ENTRIES(64));
1798 }
1799
1800 WREG32(SQ_CONFIG, sq_config);
1801 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1802 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1803 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1804 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1805 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1806
1807 if (((rdev->family) == CHIP_RV610) ||
1808 ((rdev->family) == CHIP_RV620) ||
ee59f2b4
AD		 1809 ((rdev->family) == CHIP_RS780) ||
1810 ((rdev->family) == CHIP_RS880)) {
3ce0a23d
JG		 1811 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1812 } else {
1813 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1814 }
1815
1816 /* More default values. 2D/3D driver should adjust as needed */
1817 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1818 S1_X(0x4) | S1_Y(0xc)));
1819 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1820 S1_X(0x2) | S1_Y(0x2) |
1821 S2_X(0xa) | S2_Y(0x6) |
1822 S3_X(0x6) | S3_Y(0xa)));
1823 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1824 S1_X(0x4) | S1_Y(0xc) |
1825 S2_X(0x1) | S2_Y(0x6) |
1826 S3_X(0xa) | S3_Y(0xe)));
1827 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1828 S5_X(0x0) | S5_Y(0x0) |
1829 S6_X(0xb) | S6_Y(0x4) |
1830 S7_X(0x7) | S7_Y(0x8)));
1831
1832 WREG32(VGT_STRMOUT_EN, 0);
1833 tmp = rdev->config.r600.max_pipes * 16;
1834 switch (rdev->family) {
1835 case CHIP_RV610:
3ce0a23d 1836 case CHIP_RV620:
ee59f2b4
AD		 1837 case CHIP_RS780:
1838 case CHIP_RS880:
3ce0a23d
JG		 1839 tmp += 32;
1840 break;
1841 case CHIP_RV670:
1842 tmp += 128;
1843 break;
1844 default:
1845 break;
1846 }
1847 if (tmp > 256) {
1848 tmp = 256;
1849 }
1850 WREG32(VGT_ES_PER_GS, 128);
1851 WREG32(VGT_GS_PER_ES, tmp);
1852 WREG32(VGT_GS_PER_VS, 2);
1853 WREG32(VGT_GS_VERTEX_REUSE, 16);
1854
1855 /* more default values. 2D/3D driver should adjust as needed */
1856 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1857 WREG32(VGT_STRMOUT_EN, 0);
1858 WREG32(SX_MISC, 0);
1859 WREG32(PA_SC_MODE_CNTL, 0);
1860 WREG32(PA_SC_AA_CONFIG, 0);
1861 WREG32(PA_SC_LINE_STIPPLE, 0);
1862 WREG32(SPI_INPUT_Z, 0);
1863 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1864 WREG32(CB_COLOR7_FRAG, 0);
1865
1866 /* Clear render buffer base addresses */
1867 WREG32(CB_COLOR0_BASE, 0);
1868 WREG32(CB_COLOR1_BASE, 0);
1869 WREG32(CB_COLOR2_BASE, 0);
1870 WREG32(CB_COLOR3_BASE, 0);
1871 WREG32(CB_COLOR4_BASE, 0);
1872 WREG32(CB_COLOR5_BASE, 0);
1873 WREG32(CB_COLOR6_BASE, 0);
1874 WREG32(CB_COLOR7_BASE, 0);
1875 WREG32(CB_COLOR7_FRAG, 0);
1876
1877 switch (rdev->family) {
1878 case CHIP_RV610:
3ce0a23d 1879 case CHIP_RV620:
ee59f2b4
AD		 1880 case CHIP_RS780:
1881 case CHIP_RS880:
3ce0a23d
JG		 1882 tmp = TC_L2_SIZE(8);
1883 break;
1884 case CHIP_RV630:
1885 case CHIP_RV635:
1886 tmp = TC_L2_SIZE(4);
1887 break;
1888 case CHIP_R600:
1889 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1890 break;
1891 default:
1892 tmp = TC_L2_SIZE(0);
1893 break;
1894 }
1895 WREG32(TC_CNTL, tmp);
1896
1897 tmp = RREG32(HDP_HOST_PATH_CNTL);
1898 WREG32(HDP_HOST_PATH_CNTL, tmp);
1899
1900 tmp = RREG32(ARB_POP);
1901 tmp |= ENABLE_TC128;
1902 WREG32(ARB_POP, tmp);
1903
1904 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1905 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1906 NUM_CLIP_SEQ(3)));
1907 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1908}
1909
1910
771fe6b9
JG		 1911/*
1912 * Indirect registers accessor
1913 */
3ce0a23d
JG		 1914u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1915{
1916 u32 r;
1917
1918 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1919 (void)RREG32(PCIE_PORT_INDEX);
1920 r = RREG32(PCIE_PORT_DATA);
1921 return r;
1922}
1923
1924void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1925{
1926 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1927 (void)RREG32(PCIE_PORT_INDEX);
1928 WREG32(PCIE_PORT_DATA, (v));
1929 (void)RREG32(PCIE_PORT_DATA);
1930}
1931
3ce0a23d
JG		 1932/*
1933 * CP & Ring
1934 */
1935void r600_cp_stop(struct radeon_device *rdev)
1936{
53595338 1937 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3ce0a23d 1938 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
724c80e1 1939 WREG32(SCRATCH_UMSK, 0);
3ce0a23d
JG		 1940}
1941
d8f60cfc 1942int r600_init_microcode(struct radeon_device *rdev)
3ce0a23d
JG		 1943{
1944 struct platform_device *pdev;
1945 const char *chip_name;
d8f60cfc
AD		 1946 const char *rlc_chip_name;
1947 size_t pfp_req_size, me_req_size, rlc_req_size;
3ce0a23d
JG		 1948 char fw_name[30];
1949 int err;
1950
1951 DRM_DEBUG("\n");
1952
1953 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1954 err = IS_ERR(pdev);
1955 if (err) {
1956 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1957 return -EINVAL;
1958 }
1959
1960 switch (rdev->family) {
d8f60cfc
AD		 1961 case CHIP_R600:
1962 chip_name = "R600";
1963 rlc_chip_name = "R600";
1964 break;
1965 case CHIP_RV610:
1966 chip_name = "RV610";
1967 rlc_chip_name = "R600";
1968 break;
1969 case CHIP_RV630:
1970 chip_name = "RV630";
1971 rlc_chip_name = "R600";
1972 break;
1973 case CHIP_RV620:
1974 chip_name = "RV620";
1975 rlc_chip_name = "R600";
1976 break;
1977 case CHIP_RV635:
1978 chip_name = "RV635";
1979 rlc_chip_name = "R600";
1980 break;
1981 case CHIP_RV670:
1982 chip_name = "RV670";
1983 rlc_chip_name = "R600";
1984 break;
3ce0a23d 1985 case CHIP_RS780:
d8f60cfc
AD		 1986 case CHIP_RS880:
1987 chip_name = "RS780";
1988 rlc_chip_name = "R600";
1989 break;
1990 case CHIP_RV770:
1991 chip_name = "RV770";
1992 rlc_chip_name = "R700";
1993 break;
3ce0a23d 1994 case CHIP_RV730:
d8f60cfc
AD		 1995 case CHIP_RV740:
1996 chip_name = "RV730";
1997 rlc_chip_name = "R700";
1998 break;
1999 case CHIP_RV710:
2000 chip_name = "RV710";
2001 rlc_chip_name = "R700";
2002 break;
fe251e2f
AD		 2003 case CHIP_CEDAR:
2004 chip_name = "CEDAR";
45f9a39b 2005 rlc_chip_name = "CEDAR";
fe251e2f
AD		 2006 break;
2007 case CHIP_REDWOOD:
2008 chip_name = "REDWOOD";
45f9a39b 2009 rlc_chip_name = "REDWOOD";
fe251e2f
AD		 2010 break;
2011 case CHIP_JUNIPER:
2012 chip_name = "JUNIPER";
45f9a39b 2013 rlc_chip_name = "JUNIPER";
fe251e2f
AD		 2014 break;
2015 case CHIP_CYPRESS:
2016 case CHIP_HEMLOCK:
2017 chip_name = "CYPRESS";
45f9a39b 2018 rlc_chip_name = "CYPRESS";
fe251e2f 2019 break;
439bd6cd
AD		 2020 case CHIP_PALM:
2021 chip_name = "PALM";
2022 rlc_chip_name = "SUMO";
2023 break;
d5c5a72f
AD		 2024 case CHIP_SUMO:
2025 chip_name = "SUMO";
2026 rlc_chip_name = "SUMO";
2027 break;
2028 case CHIP_SUMO2:
2029 chip_name = "SUMO2";
2030 rlc_chip_name = "SUMO";
2031 break;
3ce0a23d
JG		 2032 default: BUG();
2033 }
2034
fe251e2f
AD		 2035 if (rdev->family >= CHIP_CEDAR) {
2036 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2037 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
45f9a39b 2038 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
fe251e2f 2039 } else if (rdev->family >= CHIP_RV770) {
3ce0a23d
JG		 2040 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2041 me_req_size = R700_PM4_UCODE_SIZE * 4;
d8f60cfc 2042 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2043 } else {
2044 pfp_req_size = PFP_UCODE_SIZE * 4;
2045 me_req_size = PM4_UCODE_SIZE * 12;
d8f60cfc 2046 rlc_req_size = RLC_UCODE_SIZE * 4;
3ce0a23d
JG		 2047 }
2048
d8f60cfc 2049 DRM_INFO("Loading %s Microcode\n", chip_name);
3ce0a23d
JG		 2050
2051 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2052 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2053 if (err)
2054 goto out;
2055 if (rdev->pfp_fw->size != pfp_req_size) {
2056 printk(KERN_ERR
2057 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2058 rdev->pfp_fw->size, fw_name);
2059 err = -EINVAL;
2060 goto out;
2061 }
2062
2063 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2064 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2065 if (err)
2066 goto out;
2067 if (rdev->me_fw->size != me_req_size) {
2068 printk(KERN_ERR
2069 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2070 rdev->me_fw->size, fw_name);
2071 err = -EINVAL;
2072 }
d8f60cfc
AD		 2073
2074 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2075 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2076 if (err)
2077 goto out;
2078 if (rdev->rlc_fw->size != rlc_req_size) {
2079 printk(KERN_ERR
2080 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2081 rdev->rlc_fw->size, fw_name);
2082 err = -EINVAL;
2083 }
2084
3ce0a23d
JG		 2085out:
2086 platform_device_unregister(pdev);
2087
2088 if (err) {
2089 if (err != -EINVAL)
2090 printk(KERN_ERR
2091 "r600_cp: Failed to load firmware \"%s\"\n",
2092 fw_name);
2093 release_firmware(rdev->pfp_fw);
2094 rdev->pfp_fw = NULL;
2095 release_firmware(rdev->me_fw);
2096 rdev->me_fw = NULL;
d8f60cfc
AD		 2097 release_firmware(rdev->rlc_fw);
2098 rdev->rlc_fw = NULL;
3ce0a23d
JG		 2099 }
2100 return err;
2101}
2102
2103static int r600_cp_load_microcode(struct radeon_device *rdev)
2104{
2105 const __be32 *fw_data;
2106 int i;
2107
2108 if (!rdev->me_fw || !rdev->pfp_fw)
2109 return -EINVAL;
2110
2111 r600_cp_stop(rdev);
2112
4eace7fd
CC		 2113 WREG32(CP_RB_CNTL,
2114#ifdef __BIG_ENDIAN
2115 BUF_SWAP_32BIT |
2116#endif
2117 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
3ce0a23d
JG		 2118
2119 /* Reset cp */
2120 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2121 RREG32(GRBM_SOFT_RESET);
2122 mdelay(15);
2123 WREG32(GRBM_SOFT_RESET, 0);
2124
2125 WREG32(CP_ME_RAM_WADDR, 0);
2126
2127 fw_data = (const __be32 *)rdev->me_fw->data;
2128 WREG32(CP_ME_RAM_WADDR, 0);
2129 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2130 WREG32(CP_ME_RAM_DATA,
2131 be32_to_cpup(fw_data++));
2132
2133 fw_data = (const __be32 *)rdev->pfp_fw->data;
2134 WREG32(CP_PFP_UCODE_ADDR, 0);
2135 for (i = 0; i < PFP_UCODE_SIZE; i++)
2136 WREG32(CP_PFP_UCODE_DATA,
2137 be32_to_cpup(fw_data++));
2138
2139 WREG32(CP_PFP_UCODE_ADDR, 0);
2140 WREG32(CP_ME_RAM_WADDR, 0);
2141 WREG32(CP_ME_RAM_RADDR, 0);
2142 return 0;
2143}
2144
2145int r600_cp_start(struct radeon_device *rdev)
2146{
e32eb50d 2147 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2148 int r;
2149 uint32_t cp_me;
2150
e32eb50d 2151 r = radeon_ring_lock(rdev, ring, 7);
3ce0a23d
JG		 2152 if (r) {
2153 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2154 return r;
2155 }
e32eb50d
CK		 2156 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2157 radeon_ring_write(ring, 0x1);
7e7b41d2 2158 if (rdev->family >= CHIP_RV770) {
e32eb50d
CK		 2159 radeon_ring_write(ring, 0x0);
2160 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
fe251e2f 2161 } else {
e32eb50d
CK		 2162 radeon_ring_write(ring, 0x3);
2163 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
3ce0a23d 2164 }
e32eb50d
CK		 2165 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2166 radeon_ring_write(ring, 0);
2167 radeon_ring_write(ring, 0);
2168 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2169
2170 cp_me = 0xff;
2171 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2172 return 0;
2173}
2174
2175int r600_cp_resume(struct radeon_device *rdev)
2176{
e32eb50d 2177 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2178 u32 tmp;
2179 u32 rb_bufsz;
2180 int r;
2181
2182 /* Reset cp */
2183 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2184 RREG32(GRBM_SOFT_RESET);
2185 mdelay(15);
2186 WREG32(GRBM_SOFT_RESET, 0);
2187
2188 /* Set ring buffer size */
e32eb50d 2189 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 2190 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3ce0a23d 2191#ifdef __BIG_ENDIAN
d6f28938 2192 tmp |= BUF_SWAP_32BIT;
3ce0a23d 2193#endif
d6f28938 2194 WREG32(CP_RB_CNTL, tmp);
15d3332f 2195 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3ce0a23d
JG		 2196
2197 /* Set the write pointer delay */
2198 WREG32(CP_RB_WPTR_DELAY, 0);
2199
2200 /* Initialize the ring buffer's read and write pointers */
3ce0a23d
JG		 2201 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2202 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 2203 ring->wptr = 0;
2204 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 2205
2206 /* set the wb address whether it's enabled or not */
4eace7fd 2207 WREG32(CP_RB_RPTR_ADDR,
4eace7fd 2208 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 2209 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2210 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2211
2212 if (rdev->wb.enabled)
2213 WREG32(SCRATCH_UMSK, 0xff);
2214 else {
2215 tmp |= RB_NO_UPDATE;
2216 WREG32(SCRATCH_UMSK, 0);
2217 }
2218
3ce0a23d
JG		 2219 mdelay(1);
2220 WREG32(CP_RB_CNTL, tmp);
2221
e32eb50d 2222 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
3ce0a23d
JG		 2223 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2224
e32eb50d 2225 ring->rptr = RREG32(CP_RB_RPTR);
3ce0a23d
JG		 2226
2227 r600_cp_start(rdev);
e32eb50d
CK		 2228 ring->ready = true;
2229 r = radeon_ring_test(rdev, ring);
3ce0a23d 2230 if (r) {
e32eb50d 2231 ring->ready = false;
3ce0a23d
JG		 2232 return r;
2233 }
2234 return 0;
2235}
2236
e32eb50d 2237void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
3ce0a23d
JG		 2238{
2239 u32 rb_bufsz;
2240
2241 /* Align ring size */
2242 rb_bufsz = drm_order(ring_size / 8);
2243 ring_size = (1 << (rb_bufsz + 1)) * 4;
e32eb50d
CK		 2244 ring->ring_size = ring_size;
2245 ring->align_mask = 16 - 1;
3ce0a23d
JG		 2246}
2247
655efd3d
JG		 2248void r600_cp_fini(struct radeon_device *rdev)
2249{
2250 r600_cp_stop(rdev);
e32eb50d 2251 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
655efd3d
JG		 2252}
2253
3ce0a23d
JG		 2254
2255/*
2256 * GPU scratch registers helpers function.
2257 */
2258void r600_scratch_init(struct radeon_device *rdev)
2259{
2260 int i;
2261
2262 rdev->scratch.num_reg = 7;
724c80e1 2263 rdev->scratch.reg_base = SCRATCH_REG0;
3ce0a23d
JG		 2264 for (i = 0; i < rdev->scratch.num_reg; i++) {
2265 rdev->scratch.free[i] = true;
724c80e1 2266 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3ce0a23d
JG		 2267 }
2268}
2269
e32eb50d 2270int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 2271{
2272 uint32_t scratch;
2273 uint32_t tmp = 0;
e32eb50d 2274 unsigned i, ridx = radeon_ring_index(rdev, ring);
3ce0a23d
JG		 2275 int r;
2276
2277 r = radeon_scratch_get(rdev, &scratch);
2278 if (r) {
2279 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2280 return r;
2281 }
2282 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 2283 r = radeon_ring_lock(rdev, ring, 3);
3ce0a23d 2284 if (r) {
bf852799 2285 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ridx, r);
3ce0a23d
JG		 2286 radeon_scratch_free(rdev, scratch);
2287 return r;
2288 }
e32eb50d
CK		 2289 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2290 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2291 radeon_ring_write(ring, 0xDEADBEEF);
2292 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 2293 for (i = 0; i < rdev->usec_timeout; i++) {
2294 tmp = RREG32(scratch);
2295 if (tmp == 0xDEADBEEF)
2296 break;
2297 DRM_UDELAY(1);
2298 }
2299 if (i < rdev->usec_timeout) {
bf852799 2300 DRM_INFO("ring test on %d succeeded in %d usecs\n", ridx, i);
3ce0a23d 2301 } else {
bf852799
CK		 2302 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2303 ridx, scratch, tmp);
3ce0a23d
JG		 2304 r = -EINVAL;
2305 }
2306 radeon_scratch_free(rdev, scratch);
2307 return r;
2308}
2309
3ce0a23d
JG		 2310void r600_fence_ring_emit(struct radeon_device *rdev,
2311 struct radeon_fence *fence)
2312{
e32eb50d 2313 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 2314
d0f8a854
AD		 2315 if (rdev->wb.use_event) {
2316 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
7465280c 2317 (u64)(rdev->fence_drv[fence->ring].scratch_reg - rdev->scratch.reg_base);
77b1bad4 2318 /* flush read cache over gart */
e32eb50d
CK		 2319 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2320 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2321 PACKET3_VC_ACTION_ENA |
2322 PACKET3_SH_ACTION_ENA);
2323 radeon_ring_write(ring, 0xFFFFFFFF);
2324 radeon_ring_write(ring, 0);
2325 radeon_ring_write(ring, 10); /* poll interval */
d0f8a854 2326 /* EVENT_WRITE_EOP - flush caches, send int */
e32eb50d
CK		 2327 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2328 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2329 radeon_ring_write(ring, addr & 0xffffffff);
2330 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2331 radeon_ring_write(ring, fence->seq);
2332 radeon_ring_write(ring, 0);
d0f8a854 2333 } else {
77b1bad4 2334 /* flush read cache over gart */
e32eb50d
CK		 2335 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2336 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2337 PACKET3_VC_ACTION_ENA |
2338 PACKET3_SH_ACTION_ENA);
2339 radeon_ring_write(ring, 0xFFFFFFFF);
2340 radeon_ring_write(ring, 0);
2341 radeon_ring_write(ring, 10); /* poll interval */
2342 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2343 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
d0f8a854 2344 /* wait for 3D idle clean */
e32eb50d
CK		 2345 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2346 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2347 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
d0f8a854 2348 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 2349 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2350 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2351 radeon_ring_write(ring, fence->seq);
d0f8a854 2352 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
e32eb50d
CK		 2353 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2354 radeon_ring_write(ring, RB_INT_STAT);
d0f8a854 2355 }
3ce0a23d
JG		 2356}
2357
15d3332f 2358void r600_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 2359 struct radeon_ring *ring,
15d3332f 2360 struct radeon_semaphore *semaphore,
7b1f2485 2361 bool emit_wait)
15d3332f
CK		 2362{
2363 uint64_t addr = semaphore->gpu_addr;
2364 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2365
e32eb50d
CK		 2366 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2367 radeon_ring_write(ring, addr & 0xffffffff);
2368 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
15d3332f
CK		 2369}
2370
3ce0a23d 2371int r600_copy_blit(struct radeon_device *rdev,
003cefe0
AD		 2372 uint64_t src_offset,
2373 uint64_t dst_offset,
2374 unsigned num_gpu_pages,
2375 struct radeon_fence *fence)
3ce0a23d 2376{
ff82f052
JG		 2377 int r;
2378
2379 mutex_lock(&rdev->r600_blit.mutex);
2380 rdev->r600_blit.vb_ib = NULL;
017ed801 2381 r = r600_blit_prepare_copy(rdev, num_gpu_pages);
ff82f052
JG		 2382 if (r) {
2383 if (rdev->r600_blit.vb_ib)
2384 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2385 mutex_unlock(&rdev->r600_blit.mutex);
2386 return r;
2387 }
017ed801 2388 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages);
3ce0a23d 2389 r600_blit_done_copy(rdev, fence);
ff82f052 2390 mutex_unlock(&rdev->r600_blit.mutex);
3ce0a23d
JG		 2391 return 0;
2392}
2393
6ddddfe7
AD		 2394void r600_blit_suspend(struct radeon_device *rdev)
2395{
2396 int r;
2397
2398 /* unpin shaders bo */
2399 if (rdev->r600_blit.shader_obj) {
2400 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2401 if (!r) {
2402 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2403 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2404 }
2405 }
2406}
2407
3ce0a23d
JG		 2408int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2409 uint32_t tiling_flags, uint32_t pitch,
2410 uint32_t offset, uint32_t obj_size)
2411{
2412 /* FIXME: implement */
2413 return 0;
2414}
2415
2416void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2417{
2418 /* FIXME: implement */
2419}
2420
fc30b8ef 2421int r600_startup(struct radeon_device *rdev)
3ce0a23d 2422{
e32eb50d 2423 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3ce0a23d
JG		 2424 int r;
2425
9e46a48d
AD		 2426 /* enable pcie gen2 link */
2427 r600_pcie_gen2_enable(rdev);
2428
779720a3
AD		 2429 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2430 r = r600_init_microcode(rdev);
2431 if (r) {
2432 DRM_ERROR("Failed to load firmware!\n");
2433 return r;
2434 }
2435 }
2436
16cdf04d
AD		 2437 r = r600_vram_scratch_init(rdev);
2438 if (r)
2439 return r;
2440
a3c1945a 2441 r600_mc_program(rdev);
1a029b76
JG		 2442 if (rdev->flags & RADEON_IS_AGP) {
2443 r600_agp_enable(rdev);
2444 } else {
2445 r = r600_pcie_gart_enable(rdev);
2446 if (r)
2447 return r;
2448 }
3ce0a23d 2449 r600_gpu_init(rdev);
c38c7b64
JG		 2450 r = r600_blit_init(rdev);
2451 if (r) {
2452 r600_blit_fini(rdev);
2453 rdev->asic->copy = NULL;
2454 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2455 }
b70d6bb3 2456
724c80e1
AD		 2457 /* allocate wb buffer */
2458 r = radeon_wb_init(rdev);
2459 if (r)
2460 return r;
2461
d8f60cfc 2462 /* Enable IRQ */
d8f60cfc
AD		 2463 r = r600_irq_init(rdev);
2464 if (r) {
2465 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2466 radeon_irq_kms_fini(rdev);
2467 return r;
2468 }
2469 r600_irq_set(rdev);
2470
e32eb50d 2471 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
5596a9db
CK		 2472 R600_CP_RB_RPTR, R600_CP_RB_WPTR);
2473
3ce0a23d
JG		 2474 if (r)
2475 return r;
2476 r = r600_cp_load_microcode(rdev);
2477 if (r)
2478 return r;
2479 r = r600_cp_resume(rdev);
2480 if (r)
2481 return r;
724c80e1 2482
3ce0a23d
JG		 2483 return 0;
2484}
2485
28d52043
DA		 2486void r600_vga_set_state(struct radeon_device *rdev, bool state)
2487{
2488 uint32_t temp;
2489
2490 temp = RREG32(CONFIG_CNTL);
2491 if (state == false) {
2492 temp &= ~(1<<0);
2493 temp |= (1<<1);
2494 } else {
2495 temp &= ~(1<<1);
2496 }
2497 WREG32(CONFIG_CNTL, temp);
2498}
2499
fc30b8ef
DA		 2500int r600_resume(struct radeon_device *rdev)
2501{
2502 int r;
2503
1a029b76
JG		 2504 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2505 * posting will perform necessary task to bring back GPU into good
2506 * shape.
2507 */
fc30b8ef 2508 /* post card */
e7d40b9a 2509 atom_asic_init(rdev->mode_info.atom_context);
fc30b8ef
DA		 2510
2511 r = r600_startup(rdev);
2512 if (r) {
2513 DRM_ERROR("r600 startup failed on resume\n");
2514 return r;
2515 }
2516
7b1f2485 2517 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
fc30b8ef 2518 if (r) {
ec4f2ac4 2519 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
fc30b8ef
DA		 2520 return r;
2521 }
38fd2c6f
RM		 2522
2523 r = r600_audio_init(rdev);
2524 if (r) {
2525 DRM_ERROR("radeon: audio resume failed\n");
2526 return r;
2527 }
2528
fc30b8ef
DA		 2529 return r;
2530}
2531
3ce0a23d
JG		 2532int r600_suspend(struct radeon_device *rdev)
2533{
38fd2c6f 2534 r600_audio_fini(rdev);
3ce0a23d
JG		 2535 /* FIXME: we should wait for ring to be empty */
2536 r600_cp_stop(rdev);
e32eb50d 2537 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
0c45249f 2538 r600_irq_suspend(rdev);
724c80e1 2539 radeon_wb_disable(rdev);
4aac0473 2540 r600_pcie_gart_disable(rdev);
6ddddfe7
AD		 2541 r600_blit_suspend(rdev);
2542
3ce0a23d
JG		 2543 return 0;
2544}
2545
2546/* Plan is to move initialization in that function and use
2547 * helper function so that radeon_device_init pretty much
2548 * do nothing more than calling asic specific function. This
2549 * should also allow to remove a bunch of callback function
2550 * like vram_info.
2551 */
2552int r600_init(struct radeon_device *rdev)
771fe6b9 2553{
3ce0a23d 2554 int r;
771fe6b9 2555
3ce0a23d
JG		 2556 if (r600_debugfs_mc_info_init(rdev)) {
2557 DRM_ERROR("Failed to register debugfs file for mc !\n");
2558 }
2559 /* This don't do much */
2560 r = radeon_gem_init(rdev);
2561 if (r)
2562 return r;
2563 /* Read BIOS */
2564 if (!radeon_get_bios(rdev)) {
2565 if (ASIC_IS_AVIVO(rdev))
2566 return -EINVAL;
2567 }
2568 /* Must be an ATOMBIOS */
e7d40b9a
JG		 2569 if (!rdev->is_atom_bios) {
2570 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3ce0a23d 2571 return -EINVAL;
e7d40b9a 2572 }
3ce0a23d
JG		 2573 r = radeon_atombios_init(rdev);
2574 if (r)
2575 return r;
2576 /* Post card if necessary */
fd909c37 2577 if (!radeon_card_posted(rdev)) {
72542d77
DA		 2578 if (!rdev->bios) {
2579 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2580 return -EINVAL;
2581 }
3ce0a23d
JG		 2582 DRM_INFO("GPU not posted. posting now...\n");
2583 atom_asic_init(rdev->mode_info.atom_context);
2584 }
2585 /* Initialize scratch registers */
2586 r600_scratch_init(rdev);
2587 /* Initialize surface registers */
2588 radeon_surface_init(rdev);
7433874e 2589 /* Initialize clocks */
5e6dde7e 2590 radeon_get_clock_info(rdev->ddev);
3ce0a23d 2591 /* Fence driver */
7465280c 2592 r = radeon_fence_driver_init(rdev, 1);
3ce0a23d
JG		 2593 if (r)
2594 return r;
700a0cc0
JG		 2595 if (rdev->flags & RADEON_IS_AGP) {
2596 r = radeon_agp_init(rdev);
2597 if (r)
2598 radeon_agp_disable(rdev);
2599 }
3ce0a23d 2600 r = r600_mc_init(rdev);
b574f251 2601 if (r)
3ce0a23d 2602 return r;
3ce0a23d 2603 /* Memory manager */
4c788679 2604 r = radeon_bo_init(rdev);
3ce0a23d
JG		 2605 if (r)
2606 return r;
d8f60cfc
AD		 2607
2608 r = radeon_irq_kms_init(rdev);
2609 if (r)
2610 return r;
2611
e32eb50d
CK		 2612 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2613 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3ce0a23d 2614
d8f60cfc
AD		 2615 rdev->ih.ring_obj = NULL;
2616 r600_ih_ring_init(rdev, 64 * 1024);
3ce0a23d 2617
4aac0473
JG		 2618 r = r600_pcie_gart_init(rdev);
2619 if (r)
2620 return r;
2621
779720a3 2622 rdev->accel_working = true;
fc30b8ef 2623 r = r600_startup(rdev);
3ce0a23d 2624 if (r) {
655efd3d
JG		 2625 dev_err(rdev->dev, "disabling GPU acceleration\n");
2626 r600_cp_fini(rdev);
655efd3d 2627 r600_irq_fini(rdev);
724c80e1 2628 radeon_wb_fini(rdev);
655efd3d 2629 radeon_irq_kms_fini(rdev);
75c81298 2630 r600_pcie_gart_fini(rdev);
733289c2 2631 rdev->accel_working = false;
3ce0a23d 2632 }
733289c2
JG		 2633 if (rdev->accel_working) {
2634 r = radeon_ib_pool_init(rdev);
2635 if (r) {
db96380e 2636 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
733289c2 2637 rdev->accel_working = false;
db96380e 2638 } else {
7b1f2485 2639 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
db96380e
JG		 2640 if (r) {
2641 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2642 rdev->accel_working = false;
2643 }
733289c2 2644 }
3ce0a23d 2645 }
dafc3bd5
CK		 2646
2647 r = r600_audio_init(rdev);
2648 if (r)
2649 return r; /* TODO error handling */
3ce0a23d
JG		 2650 return 0;
2651}
2652
2653void r600_fini(struct radeon_device *rdev)
2654{
dafc3bd5 2655 r600_audio_fini(rdev);
3ce0a23d 2656 r600_blit_fini(rdev);
655efd3d 2657 r600_cp_fini(rdev);
d8f60cfc 2658 r600_irq_fini(rdev);
724c80e1 2659 radeon_wb_fini(rdev);
ccd6895d 2660 radeon_ib_pool_fini(rdev);
d8f60cfc 2661 radeon_irq_kms_fini(rdev);
4aac0473 2662 r600_pcie_gart_fini(rdev);
16cdf04d 2663 r600_vram_scratch_fini(rdev);
655efd3d 2664 radeon_agp_fini(rdev);
3ce0a23d 2665 radeon_gem_fini(rdev);
15d3332f 2666 radeon_semaphore_driver_fini(rdev);
3ce0a23d 2667 radeon_fence_driver_fini(rdev);
4c788679 2668 radeon_bo_fini(rdev);
e7d40b9a 2669 radeon_atombios_fini(rdev);
3ce0a23d
JG		 2670 kfree(rdev->bios);
2671 rdev->bios = NULL;
3ce0a23d
JG		 2672}
2673
2674
2675/*
2676 * CS stuff
2677 */
2678void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2679{
e32eb50d 2680 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
7b1f2485 2681
3ce0a23d 2682 /* FIXME: implement */
e32eb50d
CK		 2683 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2684 radeon_ring_write(ring,
4eace7fd
CC		 2685#ifdef __BIG_ENDIAN
2686 (2 << 0) |
2687#endif
2688 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 2689 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
2690 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 2691}
2692
7b1f2485 2693int r600_ib_test(struct radeon_device *rdev, int ring)
3ce0a23d
JG		 2694{
2695 struct radeon_ib *ib;
2696 uint32_t scratch;
2697 uint32_t tmp = 0;
2698 unsigned i;
2699 int r;
2700
2701 r = radeon_scratch_get(rdev, &scratch);
2702 if (r) {
2703 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2704 return r;
2705 }
2706 WREG32(scratch, 0xCAFEDEAD);
7b1f2485 2707 r = radeon_ib_get(rdev, ring, &ib);
3ce0a23d
JG		 2708 if (r) {
2709 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2710 return r;
2711 }
2712 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2713 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2714 ib->ptr[2] = 0xDEADBEEF;
2715 ib->ptr[3] = PACKET2(0);
2716 ib->ptr[4] = PACKET2(0);
2717 ib->ptr[5] = PACKET2(0);
2718 ib->ptr[6] = PACKET2(0);
2719 ib->ptr[7] = PACKET2(0);
2720 ib->ptr[8] = PACKET2(0);
2721 ib->ptr[9] = PACKET2(0);
2722 ib->ptr[10] = PACKET2(0);
2723 ib->ptr[11] = PACKET2(0);
2724 ib->ptr[12] = PACKET2(0);
2725 ib->ptr[13] = PACKET2(0);
2726 ib->ptr[14] = PACKET2(0);
2727 ib->ptr[15] = PACKET2(0);
2728 ib->length_dw = 16;
2729 r = radeon_ib_schedule(rdev, ib);
2730 if (r) {
2731 radeon_scratch_free(rdev, scratch);
2732 radeon_ib_free(rdev, &ib);
2733 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2734 return r;
2735 }
2736 r = radeon_fence_wait(ib->fence, false);
2737 if (r) {
2738 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2739 return r;
2740 }
2741 for (i = 0; i < rdev->usec_timeout; i++) {
2742 tmp = RREG32(scratch);
2743 if (tmp == 0xDEADBEEF)
2744 break;
2745 DRM_UDELAY(1);
2746 }
2747 if (i < rdev->usec_timeout) {
7b1f2485 2748 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib->fence->ring, i);
3ce0a23d 2749 } else {
4417d7f6 2750 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 2751 scratch, tmp);
2752 r = -EINVAL;
2753 }
2754 radeon_scratch_free(rdev, scratch);
2755 radeon_ib_free(rdev, &ib);
771fe6b9
JG		 2756 return r;
2757}
2758
d8f60cfc
AD		 2759/*
2760 * Interrupts
2761 *
2762 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2763 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2764 * writing to the ring and the GPU consuming, the GPU writes to the ring
2765 * and host consumes. As the host irq handler processes interrupts, it
2766 * increments the rptr. When the rptr catches up with the wptr, all the
2767 * current interrupts have been processed.
2768 */
2769
2770void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2771{
2772 u32 rb_bufsz;
2773
2774 /* Align ring size */
2775 rb_bufsz = drm_order(ring_size / 4);
2776 ring_size = (1 << rb_bufsz) * 4;
2777 rdev->ih.ring_size = ring_size;
0c45249f
JG		 2778 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2779 rdev->ih.rptr = 0;
d8f60cfc
AD		 2780}
2781
0c45249f 2782static int r600_ih_ring_alloc(struct radeon_device *rdev)
d8f60cfc
AD		 2783{
2784 int r;
2785
d8f60cfc
AD		 2786 /* Allocate ring buffer */
2787 if (rdev->ih.ring_obj == NULL) {
441921d5 2788 r = radeon_bo_create(rdev, rdev->ih.ring_size,
268b2510 2789 PAGE_SIZE, true,
4c788679
JG		 2790 RADEON_GEM_DOMAIN_GTT,
2791 &rdev->ih.ring_obj);
d8f60cfc
AD		 2792 if (r) {
2793 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2794 return r;
2795 }
4c788679
JG		 2796 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2797 if (unlikely(r != 0))
2798 return r;
2799 r = radeon_bo_pin(rdev->ih.ring_obj,
2800 RADEON_GEM_DOMAIN_GTT,
2801 &rdev->ih.gpu_addr);
d8f60cfc 2802 if (r) {
4c788679 2803 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2804 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2805 return r;
2806 }
4c788679
JG		 2807 r = radeon_bo_kmap(rdev->ih.ring_obj,
2808 (void **)&rdev->ih.ring);
2809 radeon_bo_unreserve(rdev->ih.ring_obj);
d8f60cfc
AD		 2810 if (r) {
2811 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2812 return r;
2813 }
2814 }
d8f60cfc
AD		 2815 return 0;
2816}
2817
2818static void r600_ih_ring_fini(struct radeon_device *rdev)
2819{
4c788679 2820 int r;
d8f60cfc 2821 if (rdev->ih.ring_obj) {
4c788679
JG		 2822 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2823 if (likely(r == 0)) {
2824 radeon_bo_kunmap(rdev->ih.ring_obj);
2825 radeon_bo_unpin(rdev->ih.ring_obj);
2826 radeon_bo_unreserve(rdev->ih.ring_obj);
2827 }
2828 radeon_bo_unref(&rdev->ih.ring_obj);
d8f60cfc
AD		 2829 rdev->ih.ring = NULL;
2830 rdev->ih.ring_obj = NULL;
2831 }
2832}
2833
45f9a39b 2834void r600_rlc_stop(struct radeon_device *rdev)
d8f60cfc
AD		 2835{
2836
45f9a39b
AD		 2837 if ((rdev->family >= CHIP_RV770) &&
2838 (rdev->family <= CHIP_RV740)) {
d8f60cfc
AD		 2839 /* r7xx asics need to soft reset RLC before halting */
2840 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2841 RREG32(SRBM_SOFT_RESET);
2842 udelay(15000);
2843 WREG32(SRBM_SOFT_RESET, 0);
2844 RREG32(SRBM_SOFT_RESET);
2845 }
2846
2847 WREG32(RLC_CNTL, 0);
2848}
2849
2850static void r600_rlc_start(struct radeon_device *rdev)
2851{
2852 WREG32(RLC_CNTL, RLC_ENABLE);
2853}
2854
2855static int r600_rlc_init(struct radeon_device *rdev)
2856{
2857 u32 i;
2858 const __be32 *fw_data;
2859
2860 if (!rdev->rlc_fw)
2861 return -EINVAL;
2862
2863 r600_rlc_stop(rdev);
2864
2865 WREG32(RLC_HB_BASE, 0);
2866 WREG32(RLC_HB_CNTL, 0);
2867 WREG32(RLC_HB_RPTR, 0);
2868 WREG32(RLC_HB_WPTR, 0);
12727809
AD		 2869 if (rdev->family <= CHIP_CAICOS) {
2870 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2871 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2872 }
d8f60cfc
AD		 2873 WREG32(RLC_MC_CNTL, 0);
2874 WREG32(RLC_UCODE_CNTL, 0);
2875
2876 fw_data = (const __be32 *)rdev->rlc_fw->data;
12727809
AD		 2877 if (rdev->family >= CHIP_CAYMAN) {
2878 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2879 WREG32(RLC_UCODE_ADDR, i);
2880 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2881 }
2882 } else if (rdev->family >= CHIP_CEDAR) {
45f9a39b
AD		 2883 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2884 WREG32(RLC_UCODE_ADDR, i);
2885 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2886 }
2887 } else if (rdev->family >= CHIP_RV770) {
d8f60cfc
AD		 2888 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2889 WREG32(RLC_UCODE_ADDR, i);
2890 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2891 }
2892 } else {
2893 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2894 WREG32(RLC_UCODE_ADDR, i);
2895 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2896 }
2897 }
2898 WREG32(RLC_UCODE_ADDR, 0);
2899
2900 r600_rlc_start(rdev);
2901
2902 return 0;
2903}
2904
2905static void r600_enable_interrupts(struct radeon_device *rdev)
2906{
2907 u32 ih_cntl = RREG32(IH_CNTL);
2908 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2909
2910 ih_cntl |= ENABLE_INTR;
2911 ih_rb_cntl |= IH_RB_ENABLE;
2912 WREG32(IH_CNTL, ih_cntl);
2913 WREG32(IH_RB_CNTL, ih_rb_cntl);
2914 rdev->ih.enabled = true;
2915}
2916
45f9a39b 2917void r600_disable_interrupts(struct radeon_device *rdev)
d8f60cfc
AD		 2918{
2919 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2920 u32 ih_cntl = RREG32(IH_CNTL);
2921
2922 ih_rb_cntl &= ~IH_RB_ENABLE;
2923 ih_cntl &= ~ENABLE_INTR;
2924 WREG32(IH_RB_CNTL, ih_rb_cntl);
2925 WREG32(IH_CNTL, ih_cntl);
2926 /* set rptr, wptr to 0 */
2927 WREG32(IH_RB_RPTR, 0);
2928 WREG32(IH_RB_WPTR, 0);
2929 rdev->ih.enabled = false;
2930 rdev->ih.wptr = 0;
2931 rdev->ih.rptr = 0;
2932}
2933
e0df1ac5
AD		 2934static void r600_disable_interrupt_state(struct radeon_device *rdev)
2935{
2936 u32 tmp;
2937
3555e53b 2938 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
e0df1ac5
AD		 2939 WREG32(GRBM_INT_CNTL, 0);
2940 WREG32(DxMODE_INT_MASK, 0);
6f34be50
AD		 2941 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2942 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
e0df1ac5
AD		 2943 if (ASIC_IS_DCE3(rdev)) {
2944 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2945 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2946 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2947 WREG32(DC_HPD1_INT_CONTROL, tmp);
2948 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2949 WREG32(DC_HPD2_INT_CONTROL, tmp);
2950 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2951 WREG32(DC_HPD3_INT_CONTROL, tmp);
2952 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2953 WREG32(DC_HPD4_INT_CONTROL, tmp);
2954 if (ASIC_IS_DCE32(rdev)) {
2955 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2956 WREG32(DC_HPD5_INT_CONTROL, tmp);
e0df1ac5 2957 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5898b1f3 2958 WREG32(DC_HPD6_INT_CONTROL, tmp);
e0df1ac5
AD		 2959 }
2960 } else {
2961 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2962 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2963 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2964 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
e0df1ac5 2965 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2966 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
e0df1ac5 2967 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
5898b1f3 2968 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
e0df1ac5
AD		 2969 }
2970}
2971
d8f60cfc
AD		 2972int r600_irq_init(struct radeon_device *rdev)
2973{
2974 int ret = 0;
2975 int rb_bufsz;
2976 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2977
2978 /* allocate ring */
0c45249f 2979 ret = r600_ih_ring_alloc(rdev);
d8f60cfc
AD		 2980 if (ret)
2981 return ret;
2982
2983 /* disable irqs */
2984 r600_disable_interrupts(rdev);
2985
2986 /* init rlc */
2987 ret = r600_rlc_init(rdev);
2988 if (ret) {
2989 r600_ih_ring_fini(rdev);
2990 return ret;
2991 }
2992
2993 /* setup interrupt control */
2994 /* set dummy read address to ring address */
2995 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2996 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2997 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2998 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2999 */
3000 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3001 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3002 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3003 WREG32(INTERRUPT_CNTL, interrupt_cntl);
3004
3005 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3006 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3007
3008 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3009 IH_WPTR_OVERFLOW_CLEAR |
3010 (rb_bufsz << 1));
724c80e1
AD		 3011
3012 if (rdev->wb.enabled)
3013 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3014
3015 /* set the writeback address whether it's enabled or not */
3016 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3017 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
d8f60cfc
AD		 3018
3019 WREG32(IH_RB_CNTL, ih_rb_cntl);
3020
3021 /* set rptr, wptr to 0 */
3022 WREG32(IH_RB_RPTR, 0);
3023 WREG32(IH_RB_WPTR, 0);
3024
3025 /* Default settings for IH_CNTL (disabled at first) */
3026 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3027 /* RPTR_REARM only works if msi's are enabled */
3028 if (rdev->msi_enabled)
3029 ih_cntl |= RPTR_REARM;
d8f60cfc
AD		 3030 WREG32(IH_CNTL, ih_cntl);
3031
3032 /* force the active interrupt state to all disabled */
45f9a39b
AD		 3033 if (rdev->family >= CHIP_CEDAR)
3034 evergreen_disable_interrupt_state(rdev);
3035 else
3036 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3037
3038 /* enable irqs */
3039 r600_enable_interrupts(rdev);
3040
3041 return ret;
3042}
3043
0c45249f 3044void r600_irq_suspend(struct radeon_device *rdev)
d8f60cfc 3045{
45f9a39b 3046 r600_irq_disable(rdev);
d8f60cfc 3047 r600_rlc_stop(rdev);
0c45249f
JG		 3048}
3049
3050void r600_irq_fini(struct radeon_device *rdev)
3051{
3052 r600_irq_suspend(rdev);
d8f60cfc
AD		 3053 r600_ih_ring_fini(rdev);
3054}
3055
3056int r600_irq_set(struct radeon_device *rdev)
3057{
e0df1ac5
AD		 3058 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3059 u32 mode_int = 0;
3060 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2031f77c 3061 u32 grbm_int_cntl = 0;
f2594933 3062 u32 hdmi1, hdmi2;
6f34be50 3063 u32 d1grph = 0, d2grph = 0;
d8f60cfc 3064
003e69f9 3065 if (!rdev->irq.installed) {
fce7d61b 3066 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 3067 return -EINVAL;
3068 }
d8f60cfc 3069 /* don't enable anything if the ih is disabled */
79c2bbc5
JG		 3070 if (!rdev->ih.enabled) {
3071 r600_disable_interrupts(rdev);
3072 /* force the active interrupt state to all disabled */
3073 r600_disable_interrupt_state(rdev);
d8f60cfc 3074 return 0;
79c2bbc5 3075 }
d8f60cfc 3076
f2594933 3077 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5 3078 if (ASIC_IS_DCE3(rdev)) {
f2594933 3079 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3080 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3081 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3082 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3083 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3084 if (ASIC_IS_DCE32(rdev)) {
3085 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3086 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3087 }
3088 } else {
f2594933 3089 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
e0df1ac5
AD		 3090 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3091 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3092 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3093 }
3094
d8f60cfc
AD		 3095 if (rdev->irq.sw_int) {
3096 DRM_DEBUG("r600_irq_set: sw int\n");
3097 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 3098 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
d8f60cfc 3099 }
6f34be50
AD		 3100 if (rdev->irq.crtc_vblank_int[0] ||
3101 rdev->irq.pflip[0]) {
d8f60cfc
AD		 3102 DRM_DEBUG("r600_irq_set: vblank 0\n");
3103 mode_int |= D1MODE_VBLANK_INT_MASK;
3104 }
6f34be50
AD		 3105 if (rdev->irq.crtc_vblank_int[1] ||
3106 rdev->irq.pflip[1]) {
d8f60cfc
AD		 3107 DRM_DEBUG("r600_irq_set: vblank 1\n");
3108 mode_int |= D2MODE_VBLANK_INT_MASK;
3109 }
e0df1ac5
AD		 3110 if (rdev->irq.hpd[0]) {
3111 DRM_DEBUG("r600_irq_set: hpd 1\n");
3112 hpd1 |= DC_HPDx_INT_EN;
3113 }
3114 if (rdev->irq.hpd[1]) {
3115 DRM_DEBUG("r600_irq_set: hpd 2\n");
3116 hpd2 |= DC_HPDx_INT_EN;
3117 }
3118 if (rdev->irq.hpd[2]) {
3119 DRM_DEBUG("r600_irq_set: hpd 3\n");
3120 hpd3 |= DC_HPDx_INT_EN;
3121 }
3122 if (rdev->irq.hpd[3]) {
3123 DRM_DEBUG("r600_irq_set: hpd 4\n");
3124 hpd4 |= DC_HPDx_INT_EN;
3125 }
3126 if (rdev->irq.hpd[4]) {
3127 DRM_DEBUG("r600_irq_set: hpd 5\n");
3128 hpd5 |= DC_HPDx_INT_EN;
3129 }
3130 if (rdev->irq.hpd[5]) {
3131 DRM_DEBUG("r600_irq_set: hpd 6\n");
3132 hpd6 |= DC_HPDx_INT_EN;
3133 }
f2594933
CK		 3134 if (rdev->irq.hdmi[0]) {
3135 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3136 hdmi1 |= R600_HDMI_INT_EN;
3137 }
3138 if (rdev->irq.hdmi[1]) {
3139 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3140 hdmi2 |= R600_HDMI_INT_EN;
3141 }
2031f77c
AD		 3142 if (rdev->irq.gui_idle) {
3143 DRM_DEBUG("gui idle\n");
3144 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3145 }
d8f60cfc
AD		 3146
3147 WREG32(CP_INT_CNTL, cp_int_cntl);
3148 WREG32(DxMODE_INT_MASK, mode_int);
6f34be50
AD		 3149 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3150 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
2031f77c 3151 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
f2594933 3152 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
e0df1ac5 3153 if (ASIC_IS_DCE3(rdev)) {
f2594933 3154 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3155 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3156 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3157 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3158 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3159 if (ASIC_IS_DCE32(rdev)) {
3160 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3161 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3162 }
3163 } else {
f2594933 3164 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
e0df1ac5
AD		 3165 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3166 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3167 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3168 }
d8f60cfc
AD		 3169
3170 return 0;
3171}
3172
ce580fab 3173static void r600_irq_ack(struct radeon_device *rdev)
d8f60cfc 3174{
e0df1ac5
AD		 3175 u32 tmp;
3176
3177 if (ASIC_IS_DCE3(rdev)) {
6f34be50
AD		 3178 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3179 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3180 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
e0df1ac5 3181 } else {
6f34be50
AD		 3182 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3183 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3184 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3185 }
3186 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3187 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3188
3189 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3190 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3191 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3192 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3193 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
d8f60cfc 3194 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3195 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
d8f60cfc 3196 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3197 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
d8f60cfc 3198 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
6f34be50 3199 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
d8f60cfc 3200 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
6f34be50 3201 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
e0df1ac5
AD		 3202 if (ASIC_IS_DCE3(rdev)) {
3203 tmp = RREG32(DC_HPD1_INT_CONTROL);
3204 tmp |= DC_HPDx_INT_ACK;
3205 WREG32(DC_HPD1_INT_CONTROL, tmp);
3206 } else {
3207 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3208 tmp |= DC_HPDx_INT_ACK;
3209 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3210 }
3211 }
6f34be50 3212 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
e0df1ac5
AD		 3213 if (ASIC_IS_DCE3(rdev)) {
3214 tmp = RREG32(DC_HPD2_INT_CONTROL);
3215 tmp |= DC_HPDx_INT_ACK;
3216 WREG32(DC_HPD2_INT_CONTROL, tmp);
3217 } else {
3218 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3219 tmp |= DC_HPDx_INT_ACK;
3220 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3221 }
3222 }
6f34be50 3223 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
e0df1ac5
AD		 3224 if (ASIC_IS_DCE3(rdev)) {
3225 tmp = RREG32(DC_HPD3_INT_CONTROL);
3226 tmp |= DC_HPDx_INT_ACK;
3227 WREG32(DC_HPD3_INT_CONTROL, tmp);
3228 } else {
3229 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3230 tmp |= DC_HPDx_INT_ACK;
3231 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3232 }
3233 }
6f34be50 3234 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
e0df1ac5
AD		 3235 tmp = RREG32(DC_HPD4_INT_CONTROL);
3236 tmp |= DC_HPDx_INT_ACK;
3237 WREG32(DC_HPD4_INT_CONTROL, tmp);
3238 }
3239 if (ASIC_IS_DCE32(rdev)) {
6f34be50 3240 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
e0df1ac5
AD		 3241 tmp = RREG32(DC_HPD5_INT_CONTROL);
3242 tmp |= DC_HPDx_INT_ACK;
3243 WREG32(DC_HPD5_INT_CONTROL, tmp);
3244 }
6f34be50 3245 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
e0df1ac5
AD		 3246 tmp = RREG32(DC_HPD5_INT_CONTROL);
3247 tmp |= DC_HPDx_INT_ACK;
3248 WREG32(DC_HPD6_INT_CONTROL, tmp);
3249 }
3250 }
f2594933
CK		 3251 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3252 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3253 }
3254 if (ASIC_IS_DCE3(rdev)) {
3255 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3256 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3257 }
3258 } else {
3259 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3260 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3261 }
3262 }
d8f60cfc
AD		 3263}
3264
3265void r600_irq_disable(struct radeon_device *rdev)
3266{
d8f60cfc
AD		 3267 r600_disable_interrupts(rdev);
3268 /* Wait and acknowledge irq */
3269 mdelay(1);
6f34be50 3270 r600_irq_ack(rdev);
e0df1ac5 3271 r600_disable_interrupt_state(rdev);
d8f60cfc
AD		 3272}
3273
ce580fab 3274static u32 r600_get_ih_wptr(struct radeon_device *rdev)
d8f60cfc
AD		 3275{
3276 u32 wptr, tmp;
3ce0a23d 3277
724c80e1 3278 if (rdev->wb.enabled)
204ae24d 3279 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 3280 else
3281 wptr = RREG32(IH_RB_WPTR);
3ce0a23d 3282
d8f60cfc 3283 if (wptr & RB_OVERFLOW) {
7924e5eb
JG		 3284 /* When a ring buffer overflow happen start parsing interrupt
3285 * from the last not overwritten vector (wptr + 16). Hopefully
3286 * this should allow us to catchup.
3287 */
3288 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3289 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3290 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
d8f60cfc
AD		 3291 tmp = RREG32(IH_RB_CNTL);
3292 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3293 WREG32(IH_RB_CNTL, tmp);
3294 }
0c45249f 3295 return (wptr & rdev->ih.ptr_mask);
d8f60cfc 3296}
3ce0a23d 3297
d8f60cfc
AD		 3298/* r600 IV Ring
3299 * Each IV ring entry is 128 bits:
3300 * [7:0] - interrupt source id
3301 * [31:8] - reserved
3302 * [59:32] - interrupt source data
3303 * [127:60] - reserved
3304 *
3305 * The basic interrupt vector entries
3306 * are decoded as follows:
3307 * src_id src_data description
3308 * 1 0 D1 Vblank
3309 * 1 1 D1 Vline
3310 * 5 0 D2 Vblank
3311 * 5 1 D2 Vline
3312 * 19 0 FP Hot plug detection A
3313 * 19 1 FP Hot plug detection B
3314 * 19 2 DAC A auto-detection
3315 * 19 3 DAC B auto-detection
f2594933
CK		 3316 * 21 4 HDMI block A
3317 * 21 5 HDMI block B
d8f60cfc
AD		 3318 * 176 - CP_INT RB
3319 * 177 - CP_INT IB1
3320 * 178 - CP_INT IB2
3321 * 181 - EOP Interrupt
3322 * 233 - GUI Idle
3323 *
3324 * Note, these are based on r600 and may need to be
3325 * adjusted or added to on newer asics
3326 */
3327
3328int r600_irq_process(struct radeon_device *rdev)
3329{
682f1a54
DA		 3330 u32 wptr;
3331 u32 rptr;
d8f60cfc 3332 u32 src_id, src_data;
6f34be50 3333 u32 ring_index;
d8f60cfc 3334 unsigned long flags;
d4877cf2 3335 bool queue_hotplug = false;
d8f60cfc 3336
682f1a54 3337 if (!rdev->ih.enabled || rdev->shutdown)
79c2bbc5 3338 return IRQ_NONE;
d8f60cfc 3339
f6a56939
BH		 3340 /* No MSIs, need a dummy read to flush PCI DMAs */
3341 if (!rdev->msi_enabled)
3342 RREG32(IH_RB_WPTR);
3343
682f1a54
DA		 3344 wptr = r600_get_ih_wptr(rdev);
3345 rptr = rdev->ih.rptr;
3346 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3347
d8f60cfc
AD		 3348 spin_lock_irqsave(&rdev->ih.lock, flags);
3349
3350 if (rptr == wptr) {
3351 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3352 return IRQ_NONE;
3353 }
d8f60cfc
AD		 3354
3355restart_ih:
964f6645
BH		 3356 /* Order reading of wptr vs. reading of IH ring data */
3357 rmb();
3358
d8f60cfc 3359 /* display interrupts */
6f34be50 3360 r600_irq_ack(rdev);
d8f60cfc
AD		 3361
3362 rdev->ih.wptr = wptr;
3363 while (rptr != wptr) {
3364 /* wptr/rptr are in bytes! */
3365 ring_index = rptr / 4;
4eace7fd
CC		 3366 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3367 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
d8f60cfc
AD		 3368
3369 switch (src_id) {
3370 case 1: /* D1 vblank/vline */
3371 switch (src_data) {
3372 case 0: /* D1 vblank */
6f34be50 3373 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3374 if (rdev->irq.crtc_vblank_int[0]) {
3375 drm_handle_vblank(rdev->ddev, 0);
3376 rdev->pm.vblank_sync = true;
3377 wake_up(&rdev->irq.vblank_queue);
3378 }
3e4ea742
MK		 3379 if (rdev->irq.pflip[0])
3380 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3381 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
d8f60cfc
AD		 3382 DRM_DEBUG("IH: D1 vblank\n");
3383 }
3384 break;
3385 case 1: /* D1 vline */
6f34be50
AD		 3386 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3387 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
d8f60cfc
AD		 3388 DRM_DEBUG("IH: D1 vline\n");
3389 }
3390 break;
3391 default:
b042589c 3392 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3393 break;
3394 }
3395 break;
3396 case 5: /* D2 vblank/vline */
3397 switch (src_data) {
3398 case 0: /* D2 vblank */
6f34be50 3399 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3400 if (rdev->irq.crtc_vblank_int[1]) {
3401 drm_handle_vblank(rdev->ddev, 1);
3402 rdev->pm.vblank_sync = true;
3403 wake_up(&rdev->irq.vblank_queue);
3404 }
3e4ea742
MK		 3405 if (rdev->irq.pflip[1])
3406 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3407 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
d8f60cfc
AD		 3408 DRM_DEBUG("IH: D2 vblank\n");
3409 }
3410 break;
3411 case 1: /* D1 vline */
6f34be50
AD		 3412 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3413 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
d8f60cfc
AD		 3414 DRM_DEBUG("IH: D2 vline\n");
3415 }
3416 break;
3417 default:
b042589c 3418 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3419 break;
3420 }
3421 break;
e0df1ac5
AD		 3422 case 19: /* HPD/DAC hotplug */
3423 switch (src_data) {
3424 case 0:
6f34be50
AD		 3425 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3426 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
d4877cf2
AD		 3427 queue_hotplug = true;
3428 DRM_DEBUG("IH: HPD1\n");
e0df1ac5
AD		 3429 }
3430 break;
3431 case 1:
6f34be50
AD		 3432 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3433 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
d4877cf2
AD		 3434 queue_hotplug = true;
3435 DRM_DEBUG("IH: HPD2\n");
e0df1ac5
AD		 3436 }
3437 break;
3438 case 4:
6f34be50
AD		 3439 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3440 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
d4877cf2
AD		 3441 queue_hotplug = true;
3442 DRM_DEBUG("IH: HPD3\n");
e0df1ac5
AD		 3443 }
3444 break;
3445 case 5:
6f34be50
AD		 3446 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3447 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
d4877cf2
AD		 3448 queue_hotplug = true;
3449 DRM_DEBUG("IH: HPD4\n");
e0df1ac5
AD		 3450 }
3451 break;
3452 case 10:
6f34be50
AD		 3453 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3454 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
d4877cf2
AD		 3455 queue_hotplug = true;
3456 DRM_DEBUG("IH: HPD5\n");
e0df1ac5
AD		 3457 }
3458 break;
3459 case 12:
6f34be50
AD		 3460 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3461 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
d4877cf2
AD		 3462 queue_hotplug = true;
3463 DRM_DEBUG("IH: HPD6\n");
e0df1ac5
AD		 3464 }
3465 break;
3466 default:
b042589c 3467 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
e0df1ac5
AD		 3468 break;
3469 }
3470 break;
f2594933
CK		 3471 case 21: /* HDMI */
3472 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3473 r600_audio_schedule_polling(rdev);
3474 break;
d8f60cfc
AD		 3475 case 176: /* CP_INT in ring buffer */
3476 case 177: /* CP_INT in IB1 */
3477 case 178: /* CP_INT in IB2 */
3478 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 3479 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc
AD		 3480 break;
3481 case 181: /* CP EOP event */
3482 DRM_DEBUG("IH: CP EOP\n");
7465280c 3483 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
d8f60cfc 3484 break;
2031f77c 3485 case 233: /* GUI IDLE */
303c805c 3486 DRM_DEBUG("IH: GUI idle\n");
2031f77c
AD		 3487 rdev->pm.gui_idle = true;
3488 wake_up(&rdev->irq.idle_queue);
3489 break;
d8f60cfc 3490 default:
b042589c 3491 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
d8f60cfc
AD		 3492 break;
3493 }
3494
3495 /* wptr/rptr are in bytes! */
0c45249f
JG		 3496 rptr += 16;
3497 rptr &= rdev->ih.ptr_mask;
d8f60cfc
AD		 3498 }
3499 /* make sure wptr hasn't changed while processing */
3500 wptr = r600_get_ih_wptr(rdev);
3501 if (wptr != rdev->ih.wptr)
3502 goto restart_ih;
d4877cf2 3503 if (queue_hotplug)
32c87fca 3504 schedule_work(&rdev->hotplug_work);
d8f60cfc
AD		 3505 rdev->ih.rptr = rptr;
3506 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3507 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3508 return IRQ_HANDLED;
3509}
3ce0a23d
JG		 3510
3511/*
3512 * Debugfs info
3513 */
3514#if defined(CONFIG_DEBUG_FS)
3515
3ce0a23d
JG		 3516static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3517{
3518 struct drm_info_node *node = (struct drm_info_node *) m->private;
3519 struct drm_device *dev = node->minor->dev;
3520 struct radeon_device *rdev = dev->dev_private;
3521
3522 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3523 DREG32_SYS(m, rdev, VM_L2_STATUS);
3524 return 0;
3525}
3526
3527static struct drm_info_list r600_mc_info_list[] = {
3528 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3ce0a23d
JG		 3529};
3530#endif
3531
3532int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3533{
3534#if defined(CONFIG_DEBUG_FS)
3535 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3536#else
3537 return 0;
3538#endif
771fe6b9 3539}
062b389c
JG		 3540
3541/**
3542 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3543 * rdev: radeon device structure
3544 * bo: buffer object struct which userspace is waiting for idle
3545 *
3546 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3547 * through ring buffer, this leads to corruption in rendering, see
3548 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3549 * directly perform HDP flush by writing register through MMIO.
3550 */
3551void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3552{
812d0469 3553 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
f3886f85
AD		 3554 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3555 * This seems to cause problems on some AGP cards. Just use the old
3556 * method for them.
812d0469 3557 */
e488459a 3558 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
f3886f85 3559 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
87cbf8f2 3560 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
812d0469
AD		 3561 u32 tmp;
3562
3563 WREG32(HDP_DEBUG1, 0);
3564 tmp = readl((void __iomem *)ptr);
3565 } else
3566 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
062b389c 3567}
3313e3d4
AD		 3568
3569void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3570{
3571 u32 link_width_cntl, mask, target_reg;
3572
3573 if (rdev->flags & RADEON_IS_IGP)
3574 return;
3575
3576 if (!(rdev->flags & RADEON_IS_PCIE))
3577 return;
3578
3579 /* x2 cards have a special sequence */
3580 if (ASIC_IS_X2(rdev))
3581 return;
3582
3583 /* FIXME wait for idle */
3584
3585 switch (lanes) {
3586 case 0:
3587 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3588 break;
3589 case 1:
3590 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3591 break;
3592 case 2:
3593 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3594 break;
3595 case 4:
3596 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3597 break;
3598 case 8:
3599 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3600 break;
3601 case 12:
3602 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3603 break;
3604 case 16:
3605 default:
3606 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3607 break;
3608 }
3609
3610 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3611
3612 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3613 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3614 return;
3615
3616 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3617 return;
3618
3619 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3620 RADEON_PCIE_LC_RECONFIG_NOW |
3621 R600_PCIE_LC_RENEGOTIATE_EN |
3622 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3623 link_width_cntl |= mask;
3624
3625 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3626
3627 /* some northbridges can renegotiate the link rather than requiring
3628 * a complete re-config.
3629 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3630 */
3631 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3632 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3633 else
3634 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3635
3636 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3637 RADEON_PCIE_LC_RECONFIG_NOW));
3638
3639 if (rdev->family >= CHIP_RV770)
3640 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3641 else
3642 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3643
3644 /* wait for lane set to complete */
3645 link_width_cntl = RREG32(target_reg);
3646 while (link_width_cntl == 0xffffffff)
3647 link_width_cntl = RREG32(target_reg);
3648
3649}
3650
3651int r600_get_pcie_lanes(struct radeon_device *rdev)
3652{
3653 u32 link_width_cntl;
3654
3655 if (rdev->flags & RADEON_IS_IGP)
3656 return 0;
3657
3658 if (!(rdev->flags & RADEON_IS_PCIE))
3659 return 0;
3660
3661 /* x2 cards have a special sequence */
3662 if (ASIC_IS_X2(rdev))
3663 return 0;
3664
3665 /* FIXME wait for idle */
3666
3667 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3668
3669 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3670 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3671 return 0;
3672 case RADEON_PCIE_LC_LINK_WIDTH_X1:
3673 return 1;
3674 case RADEON_PCIE_LC_LINK_WIDTH_X2:
3675 return 2;
3676 case RADEON_PCIE_LC_LINK_WIDTH_X4:
3677 return 4;
3678 case RADEON_PCIE_LC_LINK_WIDTH_X8:
3679 return 8;
3680 case RADEON_PCIE_LC_LINK_WIDTH_X16:
3681 default:
3682 return 16;
3683 }
3684}
3685
9e46a48d
AD		 3686static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3687{
3688 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3689 u16 link_cntl2;
3690
d42dd579
AD		 3691 if (radeon_pcie_gen2 == 0)
3692 return;
3693
9e46a48d
AD		 3694 if (rdev->flags & RADEON_IS_IGP)
3695 return;
3696
3697 if (!(rdev->flags & RADEON_IS_PCIE))
3698 return;
3699
3700 /* x2 cards have a special sequence */
3701 if (ASIC_IS_X2(rdev))
3702 return;
3703
3704 /* only RV6xx+ chips are supported */
3705 if (rdev->family <= CHIP_R600)
3706 return;
3707
3708 /* 55 nm r6xx asics */
3709 if ((rdev->family == CHIP_RV670) ||
3710 (rdev->family == CHIP_RV620) ||
3711 (rdev->family == CHIP_RV635)) {
3712 /* advertise upconfig capability */
3713 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3714 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3715 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3716 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3717 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3718 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3719 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3720 LC_RECONFIG_ARC_MISSING_ESCAPE);
3721 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3722 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3723 } else {
3724 link_width_cntl |= LC_UPCONFIGURE_DIS;
3725 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3726 }
3727 }
3728
3729 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3730 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3731 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3732
3733 /* 55 nm r6xx asics */
3734 if ((rdev->family == CHIP_RV670) ||
3735 (rdev->family == CHIP_RV620) ||
3736 (rdev->family == CHIP_RV635)) {
3737 WREG32(MM_CFGREGS_CNTL, 0x8);
3738 link_cntl2 = RREG32(0x4088);
3739 WREG32(MM_CFGREGS_CNTL, 0);
3740 /* not supported yet */
3741 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3742 return;
3743 }
3744
3745 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3746 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3747 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3748 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3749 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3750 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3751
3752 tmp = RREG32(0x541c);
3753 WREG32(0x541c, tmp | 0x8);
3754 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3755 link_cntl2 = RREG16(0x4088);
3756 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3757 link_cntl2 |= 0x2;
3758 WREG16(0x4088, link_cntl2);
3759 WREG32(MM_CFGREGS_CNTL, 0);
3760
3761 if ((rdev->family == CHIP_RV670) ||
3762 (rdev->family == CHIP_RV620) ||
3763 (rdev->family == CHIP_RV635)) {
3764 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3765 training_cntl &= ~LC_POINT_7_PLUS_EN;
3766 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3767 } else {
3768 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3769 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3770 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3771 }
3772
3773 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3774 speed_cntl |= LC_GEN2_EN_STRAP;
3775 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3776
3777 } else {
3778 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3779 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3780 if (1)
3781 link_width_cntl |= LC_UPCONFIGURE_DIS;
3782 else
3783 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3784 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3785 }
3786}
Linux 6.x block layer and io_uring tree(s)