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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
3ce0a23d JG |
28 | #include <linux/seq_file.h> |
29 | #include <linux/firmware.h> | |
30 | #include <linux/platform_device.h> | |
771fe6b9 | 31 | #include "drmP.h" |
3ce0a23d | 32 | #include "radeon_drm.h" |
771fe6b9 | 33 | #include "radeon.h" |
3ce0a23d | 34 | #include "radeon_mode.h" |
3ce0a23d | 35 | #include "r600d.h" |
3ce0a23d | 36 | #include "atom.h" |
d39c3b89 | 37 | #include "avivod.h" |
771fe6b9 | 38 | |
3ce0a23d JG |
39 | #define PFP_UCODE_SIZE 576 |
40 | #define PM4_UCODE_SIZE 1792 | |
d8f60cfc | 41 | #define RLC_UCODE_SIZE 768 |
3ce0a23d JG |
42 | #define R700_PFP_UCODE_SIZE 848 |
43 | #define R700_PM4_UCODE_SIZE 1360 | |
d8f60cfc | 44 | #define R700_RLC_UCODE_SIZE 1024 |
3ce0a23d JG |
45 | |
46 | /* Firmware Names */ | |
47 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); | |
48 | MODULE_FIRMWARE("radeon/R600_me.bin"); | |
49 | MODULE_FIRMWARE("radeon/RV610_pfp.bin"); | |
50 | MODULE_FIRMWARE("radeon/RV610_me.bin"); | |
51 | MODULE_FIRMWARE("radeon/RV630_pfp.bin"); | |
52 | MODULE_FIRMWARE("radeon/RV630_me.bin"); | |
53 | MODULE_FIRMWARE("radeon/RV620_pfp.bin"); | |
54 | MODULE_FIRMWARE("radeon/RV620_me.bin"); | |
55 | MODULE_FIRMWARE("radeon/RV635_pfp.bin"); | |
56 | MODULE_FIRMWARE("radeon/RV635_me.bin"); | |
57 | MODULE_FIRMWARE("radeon/RV670_pfp.bin"); | |
58 | MODULE_FIRMWARE("radeon/RV670_me.bin"); | |
59 | MODULE_FIRMWARE("radeon/RS780_pfp.bin"); | |
60 | MODULE_FIRMWARE("radeon/RS780_me.bin"); | |
61 | MODULE_FIRMWARE("radeon/RV770_pfp.bin"); | |
62 | MODULE_FIRMWARE("radeon/RV770_me.bin"); | |
63 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); | |
64 | MODULE_FIRMWARE("radeon/RV730_me.bin"); | |
65 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); | |
66 | MODULE_FIRMWARE("radeon/RV710_me.bin"); | |
d8f60cfc AD |
67 | MODULE_FIRMWARE("radeon/R600_rlc.bin"); |
68 | MODULE_FIRMWARE("radeon/R700_rlc.bin"); | |
3ce0a23d JG |
69 | |
70 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); | |
771fe6b9 | 71 | |
1a029b76 | 72 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
771fe6b9 JG |
73 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
74 | void r600_gpu_init(struct radeon_device *rdev); | |
3ce0a23d | 75 | void r600_fini(struct radeon_device *rdev); |
771fe6b9 | 76 | |
e0df1ac5 AD |
77 | /* hpd for digital panel detect/disconnect */ |
78 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
79 | { | |
80 | bool connected = false; | |
81 | ||
82 | if (ASIC_IS_DCE3(rdev)) { | |
83 | switch (hpd) { | |
84 | case RADEON_HPD_1: | |
85 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) | |
86 | connected = true; | |
87 | break; | |
88 | case RADEON_HPD_2: | |
89 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) | |
90 | connected = true; | |
91 | break; | |
92 | case RADEON_HPD_3: | |
93 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) | |
94 | connected = true; | |
95 | break; | |
96 | case RADEON_HPD_4: | |
97 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) | |
98 | connected = true; | |
99 | break; | |
100 | /* DCE 3.2 */ | |
101 | case RADEON_HPD_5: | |
102 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) | |
103 | connected = true; | |
104 | break; | |
105 | case RADEON_HPD_6: | |
106 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) | |
107 | connected = true; | |
108 | break; | |
109 | default: | |
110 | break; | |
111 | } | |
112 | } else { | |
113 | switch (hpd) { | |
114 | case RADEON_HPD_1: | |
115 | if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
116 | connected = true; | |
117 | break; | |
118 | case RADEON_HPD_2: | |
119 | if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
120 | connected = true; | |
121 | break; | |
122 | case RADEON_HPD_3: | |
123 | if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
124 | connected = true; | |
125 | break; | |
126 | default: | |
127 | break; | |
128 | } | |
129 | } | |
130 | return connected; | |
131 | } | |
132 | ||
133 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
429770b3 | 134 | enum radeon_hpd_id hpd) |
e0df1ac5 AD |
135 | { |
136 | u32 tmp; | |
137 | bool connected = r600_hpd_sense(rdev, hpd); | |
138 | ||
139 | if (ASIC_IS_DCE3(rdev)) { | |
140 | switch (hpd) { | |
141 | case RADEON_HPD_1: | |
142 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
143 | if (connected) | |
144 | tmp &= ~DC_HPDx_INT_POLARITY; | |
145 | else | |
146 | tmp |= DC_HPDx_INT_POLARITY; | |
147 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
148 | break; | |
149 | case RADEON_HPD_2: | |
150 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
151 | if (connected) | |
152 | tmp &= ~DC_HPDx_INT_POLARITY; | |
153 | else | |
154 | tmp |= DC_HPDx_INT_POLARITY; | |
155 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
156 | break; | |
157 | case RADEON_HPD_3: | |
158 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
159 | if (connected) | |
160 | tmp &= ~DC_HPDx_INT_POLARITY; | |
161 | else | |
162 | tmp |= DC_HPDx_INT_POLARITY; | |
163 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
164 | break; | |
165 | case RADEON_HPD_4: | |
166 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
167 | if (connected) | |
168 | tmp &= ~DC_HPDx_INT_POLARITY; | |
169 | else | |
170 | tmp |= DC_HPDx_INT_POLARITY; | |
171 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
172 | break; | |
173 | case RADEON_HPD_5: | |
174 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
175 | if (connected) | |
176 | tmp &= ~DC_HPDx_INT_POLARITY; | |
177 | else | |
178 | tmp |= DC_HPDx_INT_POLARITY; | |
179 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
180 | break; | |
181 | /* DCE 3.2 */ | |
182 | case RADEON_HPD_6: | |
183 | tmp = RREG32(DC_HPD6_INT_CONTROL); | |
184 | if (connected) | |
185 | tmp &= ~DC_HPDx_INT_POLARITY; | |
186 | else | |
187 | tmp |= DC_HPDx_INT_POLARITY; | |
188 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
189 | break; | |
190 | default: | |
191 | break; | |
192 | } | |
193 | } else { | |
194 | switch (hpd) { | |
195 | case RADEON_HPD_1: | |
196 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
197 | if (connected) | |
198 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
199 | else | |
200 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
201 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
202 | break; | |
203 | case RADEON_HPD_2: | |
204 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
205 | if (connected) | |
206 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
207 | else | |
208 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
209 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
210 | break; | |
211 | case RADEON_HPD_3: | |
212 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
213 | if (connected) | |
214 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
215 | else | |
216 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
217 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
218 | break; | |
219 | default: | |
220 | break; | |
221 | } | |
222 | } | |
223 | } | |
224 | ||
225 | void r600_hpd_init(struct radeon_device *rdev) | |
226 | { | |
227 | struct drm_device *dev = rdev->ddev; | |
228 | struct drm_connector *connector; | |
229 | ||
230 | if (ASIC_IS_DCE3(rdev)) { | |
231 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); | |
232 | if (ASIC_IS_DCE32(rdev)) | |
233 | tmp |= DC_HPDx_EN; | |
234 | ||
235 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
236 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
237 | switch (radeon_connector->hpd.hpd) { | |
238 | case RADEON_HPD_1: | |
239 | WREG32(DC_HPD1_CONTROL, tmp); | |
240 | rdev->irq.hpd[0] = true; | |
241 | break; | |
242 | case RADEON_HPD_2: | |
243 | WREG32(DC_HPD2_CONTROL, tmp); | |
244 | rdev->irq.hpd[1] = true; | |
245 | break; | |
246 | case RADEON_HPD_3: | |
247 | WREG32(DC_HPD3_CONTROL, tmp); | |
248 | rdev->irq.hpd[2] = true; | |
249 | break; | |
250 | case RADEON_HPD_4: | |
251 | WREG32(DC_HPD4_CONTROL, tmp); | |
252 | rdev->irq.hpd[3] = true; | |
253 | break; | |
254 | /* DCE 3.2 */ | |
255 | case RADEON_HPD_5: | |
256 | WREG32(DC_HPD5_CONTROL, tmp); | |
257 | rdev->irq.hpd[4] = true; | |
258 | break; | |
259 | case RADEON_HPD_6: | |
260 | WREG32(DC_HPD6_CONTROL, tmp); | |
261 | rdev->irq.hpd[5] = true; | |
262 | break; | |
263 | default: | |
264 | break; | |
265 | } | |
266 | } | |
267 | } else { | |
268 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
269 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
270 | switch (radeon_connector->hpd.hpd) { | |
271 | case RADEON_HPD_1: | |
272 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
273 | rdev->irq.hpd[0] = true; | |
274 | break; | |
275 | case RADEON_HPD_2: | |
276 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
277 | rdev->irq.hpd[1] = true; | |
278 | break; | |
279 | case RADEON_HPD_3: | |
280 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
281 | rdev->irq.hpd[2] = true; | |
282 | break; | |
283 | default: | |
284 | break; | |
285 | } | |
286 | } | |
287 | } | |
003e69f9 JG |
288 | if (rdev->irq.installed) |
289 | r600_irq_set(rdev); | |
e0df1ac5 AD |
290 | } |
291 | ||
292 | void r600_hpd_fini(struct radeon_device *rdev) | |
293 | { | |
294 | struct drm_device *dev = rdev->ddev; | |
295 | struct drm_connector *connector; | |
296 | ||
297 | if (ASIC_IS_DCE3(rdev)) { | |
298 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
299 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
300 | switch (radeon_connector->hpd.hpd) { | |
301 | case RADEON_HPD_1: | |
302 | WREG32(DC_HPD1_CONTROL, 0); | |
303 | rdev->irq.hpd[0] = false; | |
304 | break; | |
305 | case RADEON_HPD_2: | |
306 | WREG32(DC_HPD2_CONTROL, 0); | |
307 | rdev->irq.hpd[1] = false; | |
308 | break; | |
309 | case RADEON_HPD_3: | |
310 | WREG32(DC_HPD3_CONTROL, 0); | |
311 | rdev->irq.hpd[2] = false; | |
312 | break; | |
313 | case RADEON_HPD_4: | |
314 | WREG32(DC_HPD4_CONTROL, 0); | |
315 | rdev->irq.hpd[3] = false; | |
316 | break; | |
317 | /* DCE 3.2 */ | |
318 | case RADEON_HPD_5: | |
319 | WREG32(DC_HPD5_CONTROL, 0); | |
320 | rdev->irq.hpd[4] = false; | |
321 | break; | |
322 | case RADEON_HPD_6: | |
323 | WREG32(DC_HPD6_CONTROL, 0); | |
324 | rdev->irq.hpd[5] = false; | |
325 | break; | |
326 | default: | |
327 | break; | |
328 | } | |
329 | } | |
330 | } else { | |
331 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
332 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
333 | switch (radeon_connector->hpd.hpd) { | |
334 | case RADEON_HPD_1: | |
335 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); | |
336 | rdev->irq.hpd[0] = false; | |
337 | break; | |
338 | case RADEON_HPD_2: | |
339 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); | |
340 | rdev->irq.hpd[1] = false; | |
341 | break; | |
342 | case RADEON_HPD_3: | |
343 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); | |
344 | rdev->irq.hpd[2] = false; | |
345 | break; | |
346 | default: | |
347 | break; | |
348 | } | |
349 | } | |
350 | } | |
351 | } | |
352 | ||
771fe6b9 | 353 | /* |
3ce0a23d | 354 | * R600 PCIE GART |
771fe6b9 | 355 | */ |
3ce0a23d | 356 | int r600_gart_clear_page(struct radeon_device *rdev, int i) |
771fe6b9 | 357 | { |
3ce0a23d JG |
358 | void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; |
359 | u64 pte; | |
771fe6b9 | 360 | |
3ce0a23d JG |
361 | if (i < 0 || i > rdev->gart.num_gpu_pages) |
362 | return -EINVAL; | |
363 | pte = 0; | |
364 | writeq(pte, ((void __iomem *)ptr) + (i * 8)); | |
365 | return 0; | |
366 | } | |
771fe6b9 | 367 | |
3ce0a23d JG |
368 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) |
369 | { | |
370 | unsigned i; | |
371 | u32 tmp; | |
372 | ||
373 | WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); | |
374 | WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); | |
375 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); | |
376 | for (i = 0; i < rdev->usec_timeout; i++) { | |
377 | /* read MC_STATUS */ | |
378 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); | |
379 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; | |
380 | if (tmp == 2) { | |
381 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); | |
382 | return; | |
383 | } | |
384 | if (tmp) { | |
385 | return; | |
386 | } | |
387 | udelay(1); | |
388 | } | |
389 | } | |
390 | ||
4aac0473 | 391 | int r600_pcie_gart_init(struct radeon_device *rdev) |
3ce0a23d | 392 | { |
4aac0473 | 393 | int r; |
3ce0a23d | 394 | |
4aac0473 JG |
395 | if (rdev->gart.table.vram.robj) { |
396 | WARN(1, "R600 PCIE GART already initialized.\n"); | |
397 | return 0; | |
398 | } | |
3ce0a23d JG |
399 | /* Initialize common gart structure */ |
400 | r = radeon_gart_init(rdev); | |
4aac0473 | 401 | if (r) |
3ce0a23d | 402 | return r; |
3ce0a23d | 403 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
4aac0473 JG |
404 | return radeon_gart_table_vram_alloc(rdev); |
405 | } | |
406 | ||
407 | int r600_pcie_gart_enable(struct radeon_device *rdev) | |
408 | { | |
409 | u32 tmp; | |
410 | int r, i; | |
411 | ||
412 | if (rdev->gart.table.vram.robj == NULL) { | |
413 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); | |
414 | return -EINVAL; | |
771fe6b9 | 415 | } |
4aac0473 JG |
416 | r = radeon_gart_table_vram_pin(rdev); |
417 | if (r) | |
418 | return r; | |
bc1a631e | 419 | |
3ce0a23d JG |
420 | /* Setup L2 cache */ |
421 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
422 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
423 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
424 | WREG32(VM_L2_CNTL2, 0); | |
425 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
426 | /* Setup TLB control */ | |
427 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
428 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
429 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
430 | ENABLE_WAIT_L2_QUERY; | |
431 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
432 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
433 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
434 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
435 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
436 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
437 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
438 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
439 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
440 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
441 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
442 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
443 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
444 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
445 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
1a029b76 | 446 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
3ce0a23d JG |
447 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
448 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
449 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
450 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
451 | (u32)(rdev->dummy_page.addr >> 12)); | |
452 | for (i = 1; i < 7; i++) | |
453 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 454 | |
3ce0a23d JG |
455 | r600_pcie_gart_tlb_flush(rdev); |
456 | rdev->gart.ready = true; | |
771fe6b9 JG |
457 | return 0; |
458 | } | |
459 | ||
3ce0a23d | 460 | void r600_pcie_gart_disable(struct radeon_device *rdev) |
771fe6b9 | 461 | { |
3ce0a23d | 462 | u32 tmp; |
4c788679 | 463 | int i, r; |
771fe6b9 | 464 | |
3ce0a23d JG |
465 | /* Disable all tables */ |
466 | for (i = 0; i < 7; i++) | |
467 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 468 | |
3ce0a23d JG |
469 | /* Disable L2 cache */ |
470 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | | |
471 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
472 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
473 | /* Setup L1 TLB control */ | |
474 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
475 | ENABLE_WAIT_L2_QUERY; | |
476 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
477 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
478 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
479 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
480 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
481 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
482 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
483 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
484 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); | |
485 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); | |
486 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
487 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
488 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); | |
489 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
4aac0473 | 490 | if (rdev->gart.table.vram.robj) { |
4c788679 JG |
491 | r = radeon_bo_reserve(rdev->gart.table.vram.robj, false); |
492 | if (likely(r == 0)) { | |
493 | radeon_bo_kunmap(rdev->gart.table.vram.robj); | |
494 | radeon_bo_unpin(rdev->gart.table.vram.robj); | |
495 | radeon_bo_unreserve(rdev->gart.table.vram.robj); | |
496 | } | |
4aac0473 JG |
497 | } |
498 | } | |
499 | ||
500 | void r600_pcie_gart_fini(struct radeon_device *rdev) | |
501 | { | |
502 | r600_pcie_gart_disable(rdev); | |
503 | radeon_gart_table_vram_free(rdev); | |
504 | radeon_gart_fini(rdev); | |
771fe6b9 JG |
505 | } |
506 | ||
1a029b76 JG |
507 | void r600_agp_enable(struct radeon_device *rdev) |
508 | { | |
509 | u32 tmp; | |
510 | int i; | |
511 | ||
512 | /* Setup L2 cache */ | |
513 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
514 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
515 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
516 | WREG32(VM_L2_CNTL2, 0); | |
517 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
518 | /* Setup TLB control */ | |
519 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
520 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
521 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
522 | ENABLE_WAIT_L2_QUERY; | |
523 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
524 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
525 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
526 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
527 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
528 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
529 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
530 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
531 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
532 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
533 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
534 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
535 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
536 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
537 | for (i = 0; i < 7; i++) | |
538 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
539 | } | |
540 | ||
771fe6b9 JG |
541 | int r600_mc_wait_for_idle(struct radeon_device *rdev) |
542 | { | |
3ce0a23d JG |
543 | unsigned i; |
544 | u32 tmp; | |
545 | ||
546 | for (i = 0; i < rdev->usec_timeout; i++) { | |
547 | /* read MC_STATUS */ | |
548 | tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; | |
549 | if (!tmp) | |
550 | return 0; | |
551 | udelay(1); | |
552 | } | |
553 | return -1; | |
771fe6b9 JG |
554 | } |
555 | ||
a3c1945a | 556 | static void r600_mc_program(struct radeon_device *rdev) |
771fe6b9 | 557 | { |
a3c1945a | 558 | struct rv515_mc_save save; |
3ce0a23d JG |
559 | u32 tmp; |
560 | int i, j; | |
771fe6b9 | 561 | |
3ce0a23d JG |
562 | /* Initialize HDP */ |
563 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
564 | WREG32((0x2c14 + j), 0x00000000); | |
565 | WREG32((0x2c18 + j), 0x00000000); | |
566 | WREG32((0x2c1c + j), 0x00000000); | |
567 | WREG32((0x2c20 + j), 0x00000000); | |
568 | WREG32((0x2c24 + j), 0x00000000); | |
569 | } | |
570 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | |
771fe6b9 | 571 | |
a3c1945a | 572 | rv515_mc_stop(rdev, &save); |
3ce0a23d | 573 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 574 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 575 | } |
a3c1945a | 576 | /* Lockout access through VGA aperture (doesn't exist before R600) */ |
3ce0a23d | 577 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
3ce0a23d | 578 | /* Update configuration */ |
1a029b76 JG |
579 | if (rdev->flags & RADEON_IS_AGP) { |
580 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { | |
581 | /* VRAM before AGP */ | |
582 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
583 | rdev->mc.vram_start >> 12); | |
584 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
585 | rdev->mc.gtt_end >> 12); | |
586 | } else { | |
587 | /* VRAM after AGP */ | |
588 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
589 | rdev->mc.gtt_start >> 12); | |
590 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
591 | rdev->mc.vram_end >> 12); | |
592 | } | |
593 | } else { | |
594 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); | |
595 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); | |
596 | } | |
3ce0a23d | 597 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); |
1a029b76 | 598 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
3ce0a23d JG |
599 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
600 | WREG32(MC_VM_FB_LOCATION, tmp); | |
601 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
602 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); | |
1a029b76 | 603 | WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF); |
3ce0a23d | 604 | if (rdev->flags & RADEON_IS_AGP) { |
1a029b76 JG |
605 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); |
606 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); | |
3ce0a23d JG |
607 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
608 | } else { | |
609 | WREG32(MC_VM_AGP_BASE, 0); | |
610 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
611 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
612 | } | |
3ce0a23d | 613 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 614 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 615 | } |
a3c1945a | 616 | rv515_mc_resume(rdev, &save); |
698443d9 DA |
617 | /* we need to own VRAM, so turn off the VGA renderer here |
618 | * to stop it overwriting our objects */ | |
d39c3b89 | 619 | rv515_vga_render_disable(rdev); |
3ce0a23d JG |
620 | } |
621 | ||
622 | int r600_mc_init(struct radeon_device *rdev) | |
771fe6b9 | 623 | { |
3ce0a23d JG |
624 | fixed20_12 a; |
625 | u32 tmp; | |
5885b7a9 | 626 | int chansize, numchan; |
3ce0a23d | 627 | int r; |
771fe6b9 | 628 | |
3ce0a23d | 629 | /* Get VRAM informations */ |
771fe6b9 | 630 | rdev->mc.vram_is_ddr = true; |
3ce0a23d JG |
631 | tmp = RREG32(RAMCFG); |
632 | if (tmp & CHANSIZE_OVERRIDE) { | |
771fe6b9 | 633 | chansize = 16; |
3ce0a23d | 634 | } else if (tmp & CHANSIZE_MASK) { |
771fe6b9 JG |
635 | chansize = 64; |
636 | } else { | |
637 | chansize = 32; | |
638 | } | |
5885b7a9 AD |
639 | tmp = RREG32(CHMAP); |
640 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
641 | case 0: | |
642 | default: | |
643 | numchan = 1; | |
644 | break; | |
645 | case 1: | |
646 | numchan = 2; | |
647 | break; | |
648 | case 2: | |
649 | numchan = 4; | |
650 | break; | |
651 | case 3: | |
652 | numchan = 8; | |
653 | break; | |
771fe6b9 | 654 | } |
5885b7a9 | 655 | rdev->mc.vram_width = numchan * chansize; |
3ce0a23d JG |
656 | /* Could aper size report 0 ? */ |
657 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | |
658 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | |
659 | /* Setup GPU memory space */ | |
660 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | |
661 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | |
974b16e3 AD |
662 | |
663 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) | |
664 | rdev->mc.mc_vram_size = rdev->mc.aper_size; | |
665 | ||
666 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) | |
667 | rdev->mc.real_vram_size = rdev->mc.aper_size; | |
668 | ||
3ce0a23d JG |
669 | if (rdev->flags & RADEON_IS_AGP) { |
670 | r = radeon_agp_init(rdev); | |
671 | if (r) | |
672 | return r; | |
673 | /* gtt_size is setup by radeon_agp_init */ | |
674 | rdev->mc.gtt_location = rdev->mc.agp_base; | |
675 | tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; | |
676 | /* Try to put vram before or after AGP because we | |
677 | * we want SYSTEM_APERTURE to cover both VRAM and | |
678 | * AGP so that GPU can catch out of VRAM/AGP access | |
679 | */ | |
680 | if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { | |
af901ca1 | 681 | /* Enough place before */ |
3ce0a23d JG |
682 | rdev->mc.vram_location = rdev->mc.gtt_location - |
683 | rdev->mc.mc_vram_size; | |
684 | } else if (tmp > rdev->mc.mc_vram_size) { | |
af901ca1 | 685 | /* Enough place after */ |
3ce0a23d JG |
686 | rdev->mc.vram_location = rdev->mc.gtt_location + |
687 | rdev->mc.gtt_size; | |
688 | } else { | |
689 | /* Try to setup VRAM then AGP might not | |
690 | * not work on some card | |
691 | */ | |
692 | rdev->mc.vram_location = 0x00000000UL; | |
693 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; | |
694 | } | |
695 | } else { | |
4d357abb DA |
696 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
697 | rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) & | |
698 | 0xFFFF) << 24; | |
699 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; | |
700 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { | |
701 | /* Enough place after vram */ | |
702 | rdev->mc.gtt_location = tmp; | |
703 | } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) { | |
704 | /* Enough place before vram */ | |
705 | rdev->mc.gtt_location = 0; | |
706 | } else { | |
707 | /* Not enough place after or before shrink | |
708 | * gart size | |
709 | */ | |
710 | if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) { | |
3ce0a23d | 711 | rdev->mc.gtt_location = 0; |
4d357abb | 712 | rdev->mc.gtt_size = rdev->mc.vram_location; |
3ce0a23d | 713 | } else { |
4d357abb DA |
714 | rdev->mc.gtt_location = tmp; |
715 | rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp; | |
3ce0a23d | 716 | } |
3ce0a23d | 717 | } |
4d357abb | 718 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
3ce0a23d JG |
719 | } |
720 | rdev->mc.vram_start = rdev->mc.vram_location; | |
1a029b76 | 721 | rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
3ce0a23d | 722 | rdev->mc.gtt_start = rdev->mc.gtt_location; |
1a029b76 | 723 | rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
3ce0a23d JG |
724 | /* FIXME: we should enforce default clock in case GPU is not in |
725 | * default setup | |
726 | */ | |
727 | a.full = rfixed_const(100); | |
728 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); | |
729 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); | |
06b6476d AD |
730 | |
731 | if (rdev->flags & RADEON_IS_IGP) | |
732 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); | |
733 | ||
3ce0a23d | 734 | return 0; |
771fe6b9 JG |
735 | } |
736 | ||
3ce0a23d JG |
737 | /* We doesn't check that the GPU really needs a reset we simply do the |
738 | * reset, it's up to the caller to determine if the GPU needs one. We | |
739 | * might add an helper function to check that. | |
740 | */ | |
741 | int r600_gpu_soft_reset(struct radeon_device *rdev) | |
771fe6b9 | 742 | { |
a3c1945a | 743 | struct rv515_mc_save save; |
3ce0a23d JG |
744 | u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | |
745 | S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | | |
746 | S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | | |
747 | S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | | |
748 | S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | | |
749 | S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | | |
750 | S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | | |
751 | S_008010_GUI_ACTIVE(1); | |
752 | u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | | |
753 | S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | | |
754 | S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | | |
755 | S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | | |
756 | S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | | |
757 | S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | | |
758 | S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | | |
759 | S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); | |
760 | u32 srbm_reset = 0; | |
a3c1945a | 761 | u32 tmp; |
771fe6b9 | 762 | |
1a029b76 JG |
763 | dev_info(rdev->dev, "GPU softreset \n"); |
764 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", | |
765 | RREG32(R_008010_GRBM_STATUS)); | |
766 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", | |
a3c1945a | 767 | RREG32(R_008014_GRBM_STATUS2)); |
1a029b76 JG |
768 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", |
769 | RREG32(R_000E50_SRBM_STATUS)); | |
a3c1945a JG |
770 | rv515_mc_stop(rdev, &save); |
771 | if (r600_mc_wait_for_idle(rdev)) { | |
772 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
773 | } | |
3ce0a23d JG |
774 | /* Disable CP parsing/prefetching */ |
775 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff)); | |
776 | /* Check if any of the rendering block is busy and reset it */ | |
777 | if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || | |
778 | (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { | |
a3c1945a | 779 | tmp = S_008020_SOFT_RESET_CR(1) | |
3ce0a23d JG |
780 | S_008020_SOFT_RESET_DB(1) | |
781 | S_008020_SOFT_RESET_CB(1) | | |
782 | S_008020_SOFT_RESET_PA(1) | | |
783 | S_008020_SOFT_RESET_SC(1) | | |
784 | S_008020_SOFT_RESET_SMX(1) | | |
785 | S_008020_SOFT_RESET_SPI(1) | | |
786 | S_008020_SOFT_RESET_SX(1) | | |
787 | S_008020_SOFT_RESET_SH(1) | | |
788 | S_008020_SOFT_RESET_TC(1) | | |
789 | S_008020_SOFT_RESET_TA(1) | | |
790 | S_008020_SOFT_RESET_VC(1) | | |
a3c1945a | 791 | S_008020_SOFT_RESET_VGT(1); |
1a029b76 | 792 | dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); |
a3c1945a | 793 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); |
3ce0a23d JG |
794 | (void)RREG32(R_008020_GRBM_SOFT_RESET); |
795 | udelay(50); | |
796 | WREG32(R_008020_GRBM_SOFT_RESET, 0); | |
797 | (void)RREG32(R_008020_GRBM_SOFT_RESET); | |
798 | } | |
799 | /* Reset CP (we always reset CP) */ | |
a3c1945a JG |
800 | tmp = S_008020_SOFT_RESET_CP(1); |
801 | dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); | |
802 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); | |
3ce0a23d JG |
803 | (void)RREG32(R_008020_GRBM_SOFT_RESET); |
804 | udelay(50); | |
805 | WREG32(R_008020_GRBM_SOFT_RESET, 0); | |
806 | (void)RREG32(R_008020_GRBM_SOFT_RESET); | |
807 | /* Reset others GPU block if necessary */ | |
808 | if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
809 | srbm_reset |= S_000E60_SOFT_RESET_RLC(1); | |
810 | if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) | |
811 | srbm_reset |= S_000E60_SOFT_RESET_GRBM(1); | |
812 | if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS))) | |
813 | srbm_reset |= S_000E60_SOFT_RESET_IH(1); | |
814 | if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
815 | srbm_reset |= S_000E60_SOFT_RESET_VMC(1); | |
816 | if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
817 | srbm_reset |= S_000E60_SOFT_RESET_MC(1); | |
818 | if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
819 | srbm_reset |= S_000E60_SOFT_RESET_MC(1); | |
820 | if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
821 | srbm_reset |= S_000E60_SOFT_RESET_MC(1); | |
822 | if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
823 | srbm_reset |= S_000E60_SOFT_RESET_MC(1); | |
824 | if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
825 | srbm_reset |= S_000E60_SOFT_RESET_MC(1); | |
826 | if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
827 | srbm_reset |= S_000E60_SOFT_RESET_RLC(1); | |
828 | if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS))) | |
829 | srbm_reset |= S_000E60_SOFT_RESET_SEM(1); | |
1a029b76 JG |
830 | if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS))) |
831 | srbm_reset |= S_000E60_SOFT_RESET_BIF(1); | |
832 | dev_info(rdev->dev, " R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset); | |
833 | WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); | |
834 | (void)RREG32(R_000E60_SRBM_SOFT_RESET); | |
835 | udelay(50); | |
836 | WREG32(R_000E60_SRBM_SOFT_RESET, 0); | |
837 | (void)RREG32(R_000E60_SRBM_SOFT_RESET); | |
3ce0a23d JG |
838 | WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset); |
839 | (void)RREG32(R_000E60_SRBM_SOFT_RESET); | |
840 | udelay(50); | |
841 | WREG32(R_000E60_SRBM_SOFT_RESET, 0); | |
842 | (void)RREG32(R_000E60_SRBM_SOFT_RESET); | |
843 | /* Wait a little for things to settle down */ | |
844 | udelay(50); | |
1a029b76 JG |
845 | dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n", |
846 | RREG32(R_008010_GRBM_STATUS)); | |
847 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n", | |
848 | RREG32(R_008014_GRBM_STATUS2)); | |
849 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n", | |
850 | RREG32(R_000E50_SRBM_STATUS)); | |
a3c1945a JG |
851 | /* After reset we need to reinit the asic as GPU often endup in an |
852 | * incoherent state. | |
853 | */ | |
854 | atom_asic_init(rdev->mode_info.atom_context); | |
855 | rv515_mc_resume(rdev, &save); | |
3ce0a23d JG |
856 | return 0; |
857 | } | |
858 | ||
859 | int r600_gpu_reset(struct radeon_device *rdev) | |
860 | { | |
861 | return r600_gpu_soft_reset(rdev); | |
862 | } | |
863 | ||
864 | static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, | |
865 | u32 num_backends, | |
866 | u32 backend_disable_mask) | |
867 | { | |
868 | u32 backend_map = 0; | |
869 | u32 enabled_backends_mask; | |
870 | u32 enabled_backends_count; | |
871 | u32 cur_pipe; | |
872 | u32 swizzle_pipe[R6XX_MAX_PIPES]; | |
873 | u32 cur_backend; | |
874 | u32 i; | |
875 | ||
876 | if (num_tile_pipes > R6XX_MAX_PIPES) | |
877 | num_tile_pipes = R6XX_MAX_PIPES; | |
878 | if (num_tile_pipes < 1) | |
879 | num_tile_pipes = 1; | |
880 | if (num_backends > R6XX_MAX_BACKENDS) | |
881 | num_backends = R6XX_MAX_BACKENDS; | |
882 | if (num_backends < 1) | |
883 | num_backends = 1; | |
884 | ||
885 | enabled_backends_mask = 0; | |
886 | enabled_backends_count = 0; | |
887 | for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { | |
888 | if (((backend_disable_mask >> i) & 1) == 0) { | |
889 | enabled_backends_mask |= (1 << i); | |
890 | ++enabled_backends_count; | |
891 | } | |
892 | if (enabled_backends_count == num_backends) | |
893 | break; | |
894 | } | |
895 | ||
896 | if (enabled_backends_count == 0) { | |
897 | enabled_backends_mask = 1; | |
898 | enabled_backends_count = 1; | |
899 | } | |
900 | ||
901 | if (enabled_backends_count != num_backends) | |
902 | num_backends = enabled_backends_count; | |
903 | ||
904 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); | |
905 | switch (num_tile_pipes) { | |
906 | case 1: | |
907 | swizzle_pipe[0] = 0; | |
908 | break; | |
909 | case 2: | |
910 | swizzle_pipe[0] = 0; | |
911 | swizzle_pipe[1] = 1; | |
912 | break; | |
913 | case 3: | |
914 | swizzle_pipe[0] = 0; | |
915 | swizzle_pipe[1] = 1; | |
916 | swizzle_pipe[2] = 2; | |
917 | break; | |
918 | case 4: | |
919 | swizzle_pipe[0] = 0; | |
920 | swizzle_pipe[1] = 1; | |
921 | swizzle_pipe[2] = 2; | |
922 | swizzle_pipe[3] = 3; | |
923 | break; | |
924 | case 5: | |
925 | swizzle_pipe[0] = 0; | |
926 | swizzle_pipe[1] = 1; | |
927 | swizzle_pipe[2] = 2; | |
928 | swizzle_pipe[3] = 3; | |
929 | swizzle_pipe[4] = 4; | |
930 | break; | |
931 | case 6: | |
932 | swizzle_pipe[0] = 0; | |
933 | swizzle_pipe[1] = 2; | |
934 | swizzle_pipe[2] = 4; | |
935 | swizzle_pipe[3] = 5; | |
936 | swizzle_pipe[4] = 1; | |
937 | swizzle_pipe[5] = 3; | |
938 | break; | |
939 | case 7: | |
940 | swizzle_pipe[0] = 0; | |
941 | swizzle_pipe[1] = 2; | |
942 | swizzle_pipe[2] = 4; | |
943 | swizzle_pipe[3] = 6; | |
944 | swizzle_pipe[4] = 1; | |
945 | swizzle_pipe[5] = 3; | |
946 | swizzle_pipe[6] = 5; | |
947 | break; | |
948 | case 8: | |
949 | swizzle_pipe[0] = 0; | |
950 | swizzle_pipe[1] = 2; | |
951 | swizzle_pipe[2] = 4; | |
952 | swizzle_pipe[3] = 6; | |
953 | swizzle_pipe[4] = 1; | |
954 | swizzle_pipe[5] = 3; | |
955 | swizzle_pipe[6] = 5; | |
956 | swizzle_pipe[7] = 7; | |
957 | break; | |
958 | } | |
959 | ||
960 | cur_backend = 0; | |
961 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
962 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
963 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
964 | ||
965 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); | |
966 | ||
967 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
968 | } | |
969 | ||
970 | return backend_map; | |
971 | } | |
972 | ||
973 | int r600_count_pipe_bits(uint32_t val) | |
974 | { | |
975 | int i, ret = 0; | |
976 | ||
977 | for (i = 0; i < 32; i++) { | |
978 | ret += val & 1; | |
979 | val >>= 1; | |
980 | } | |
981 | return ret; | |
771fe6b9 JG |
982 | } |
983 | ||
3ce0a23d JG |
984 | void r600_gpu_init(struct radeon_device *rdev) |
985 | { | |
986 | u32 tiling_config; | |
987 | u32 ramcfg; | |
988 | u32 tmp; | |
989 | int i, j; | |
990 | u32 sq_config; | |
991 | u32 sq_gpr_resource_mgmt_1 = 0; | |
992 | u32 sq_gpr_resource_mgmt_2 = 0; | |
993 | u32 sq_thread_resource_mgmt = 0; | |
994 | u32 sq_stack_resource_mgmt_1 = 0; | |
995 | u32 sq_stack_resource_mgmt_2 = 0; | |
996 | ||
997 | /* FIXME: implement */ | |
998 | switch (rdev->family) { | |
999 | case CHIP_R600: | |
1000 | rdev->config.r600.max_pipes = 4; | |
1001 | rdev->config.r600.max_tile_pipes = 8; | |
1002 | rdev->config.r600.max_simds = 4; | |
1003 | rdev->config.r600.max_backends = 4; | |
1004 | rdev->config.r600.max_gprs = 256; | |
1005 | rdev->config.r600.max_threads = 192; | |
1006 | rdev->config.r600.max_stack_entries = 256; | |
1007 | rdev->config.r600.max_hw_contexts = 8; | |
1008 | rdev->config.r600.max_gs_threads = 16; | |
1009 | rdev->config.r600.sx_max_export_size = 128; | |
1010 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1011 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1012 | rdev->config.r600.sq_num_cf_insts = 2; | |
1013 | break; | |
1014 | case CHIP_RV630: | |
1015 | case CHIP_RV635: | |
1016 | rdev->config.r600.max_pipes = 2; | |
1017 | rdev->config.r600.max_tile_pipes = 2; | |
1018 | rdev->config.r600.max_simds = 3; | |
1019 | rdev->config.r600.max_backends = 1; | |
1020 | rdev->config.r600.max_gprs = 128; | |
1021 | rdev->config.r600.max_threads = 192; | |
1022 | rdev->config.r600.max_stack_entries = 128; | |
1023 | rdev->config.r600.max_hw_contexts = 8; | |
1024 | rdev->config.r600.max_gs_threads = 4; | |
1025 | rdev->config.r600.sx_max_export_size = 128; | |
1026 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1027 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1028 | rdev->config.r600.sq_num_cf_insts = 2; | |
1029 | break; | |
1030 | case CHIP_RV610: | |
1031 | case CHIP_RV620: | |
1032 | case CHIP_RS780: | |
1033 | case CHIP_RS880: | |
1034 | rdev->config.r600.max_pipes = 1; | |
1035 | rdev->config.r600.max_tile_pipes = 1; | |
1036 | rdev->config.r600.max_simds = 2; | |
1037 | rdev->config.r600.max_backends = 1; | |
1038 | rdev->config.r600.max_gprs = 128; | |
1039 | rdev->config.r600.max_threads = 192; | |
1040 | rdev->config.r600.max_stack_entries = 128; | |
1041 | rdev->config.r600.max_hw_contexts = 4; | |
1042 | rdev->config.r600.max_gs_threads = 4; | |
1043 | rdev->config.r600.sx_max_export_size = 128; | |
1044 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1045 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1046 | rdev->config.r600.sq_num_cf_insts = 1; | |
1047 | break; | |
1048 | case CHIP_RV670: | |
1049 | rdev->config.r600.max_pipes = 4; | |
1050 | rdev->config.r600.max_tile_pipes = 4; | |
1051 | rdev->config.r600.max_simds = 4; | |
1052 | rdev->config.r600.max_backends = 4; | |
1053 | rdev->config.r600.max_gprs = 192; | |
1054 | rdev->config.r600.max_threads = 192; | |
1055 | rdev->config.r600.max_stack_entries = 256; | |
1056 | rdev->config.r600.max_hw_contexts = 8; | |
1057 | rdev->config.r600.max_gs_threads = 16; | |
1058 | rdev->config.r600.sx_max_export_size = 128; | |
1059 | rdev->config.r600.sx_max_export_pos_size = 16; | |
1060 | rdev->config.r600.sx_max_export_smx_size = 128; | |
1061 | rdev->config.r600.sq_num_cf_insts = 2; | |
1062 | break; | |
1063 | default: | |
1064 | break; | |
1065 | } | |
1066 | ||
1067 | /* Initialize HDP */ | |
1068 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1069 | WREG32((0x2c14 + j), 0x00000000); | |
1070 | WREG32((0x2c18 + j), 0x00000000); | |
1071 | WREG32((0x2c1c + j), 0x00000000); | |
1072 | WREG32((0x2c20 + j), 0x00000000); | |
1073 | WREG32((0x2c24 + j), 0x00000000); | |
1074 | } | |
1075 | ||
1076 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
1077 | ||
1078 | /* Setup tiling */ | |
1079 | tiling_config = 0; | |
1080 | ramcfg = RREG32(RAMCFG); | |
1081 | switch (rdev->config.r600.max_tile_pipes) { | |
1082 | case 1: | |
1083 | tiling_config |= PIPE_TILING(0); | |
1084 | break; | |
1085 | case 2: | |
1086 | tiling_config |= PIPE_TILING(1); | |
1087 | break; | |
1088 | case 4: | |
1089 | tiling_config |= PIPE_TILING(2); | |
1090 | break; | |
1091 | case 8: | |
1092 | tiling_config |= PIPE_TILING(3); | |
1093 | break; | |
1094 | default: | |
1095 | break; | |
1096 | } | |
1097 | tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); | |
1098 | tiling_config |= GROUP_SIZE(0); | |
1099 | tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; | |
1100 | if (tmp > 3) { | |
1101 | tiling_config |= ROW_TILING(3); | |
1102 | tiling_config |= SAMPLE_SPLIT(3); | |
1103 | } else { | |
1104 | tiling_config |= ROW_TILING(tmp); | |
1105 | tiling_config |= SAMPLE_SPLIT(tmp); | |
1106 | } | |
1107 | tiling_config |= BANK_SWAPS(1); | |
1108 | tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes, | |
1109 | rdev->config.r600.max_backends, | |
1110 | (0xff << rdev->config.r600.max_backends) & 0xff); | |
1111 | tiling_config |= BACKEND_MAP(tmp); | |
1112 | WREG32(GB_TILING_CONFIG, tiling_config); | |
1113 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); | |
1114 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); | |
1115 | ||
1116 | tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK); | |
1117 | WREG32(CC_RB_BACKEND_DISABLE, tmp); | |
1118 | ||
1119 | /* Setup pipes */ | |
1120 | tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK); | |
1121 | tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK); | |
1122 | WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp); | |
1123 | WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp); | |
1124 | ||
1125 | tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK); | |
1126 | WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); | |
1127 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); | |
1128 | ||
1129 | /* Setup some CP states */ | |
1130 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); | |
1131 | WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); | |
1132 | ||
1133 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | | |
1134 | SYNC_WALKER | SYNC_ALIGNER)); | |
1135 | /* Setup various GPU states */ | |
1136 | if (rdev->family == CHIP_RV670) | |
1137 | WREG32(ARB_GDEC_RD_CNTL, 0x00000021); | |
1138 | ||
1139 | tmp = RREG32(SX_DEBUG_1); | |
1140 | tmp |= SMX_EVENT_RELEASE; | |
1141 | if ((rdev->family > CHIP_R600)) | |
1142 | tmp |= ENABLE_NEW_SMX_ADDRESS; | |
1143 | WREG32(SX_DEBUG_1, tmp); | |
1144 | ||
1145 | if (((rdev->family) == CHIP_R600) || | |
1146 | ((rdev->family) == CHIP_RV630) || | |
1147 | ((rdev->family) == CHIP_RV610) || | |
1148 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1149 | ((rdev->family) == CHIP_RS780) || |
1150 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1151 | WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); |
1152 | } else { | |
1153 | WREG32(DB_DEBUG, 0); | |
1154 | } | |
1155 | WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | | |
1156 | DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); | |
1157 | ||
1158 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
1159 | WREG32(VGT_NUM_INSTANCES, 0); | |
1160 | ||
1161 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); | |
1162 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); | |
1163 | ||
1164 | tmp = RREG32(SQ_MS_FIFO_SIZES); | |
1165 | if (((rdev->family) == CHIP_RV610) || | |
1166 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1167 | ((rdev->family) == CHIP_RS780) || |
1168 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1169 | tmp = (CACHE_FIFO_SIZE(0xa) | |
1170 | FETCH_FIFO_HIWATER(0xa) | | |
1171 | DONE_FIFO_HIWATER(0xe0) | | |
1172 | ALU_UPDATE_FIFO_HIWATER(0x8)); | |
1173 | } else if (((rdev->family) == CHIP_R600) || | |
1174 | ((rdev->family) == CHIP_RV630)) { | |
1175 | tmp &= ~DONE_FIFO_HIWATER(0xff); | |
1176 | tmp |= DONE_FIFO_HIWATER(0x4); | |
1177 | } | |
1178 | WREG32(SQ_MS_FIFO_SIZES, tmp); | |
1179 | ||
1180 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
1181 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
1182 | */ | |
1183 | sq_config = RREG32(SQ_CONFIG); | |
1184 | sq_config &= ~(PS_PRIO(3) | | |
1185 | VS_PRIO(3) | | |
1186 | GS_PRIO(3) | | |
1187 | ES_PRIO(3)); | |
1188 | sq_config |= (DX9_CONSTS | | |
1189 | VC_ENABLE | | |
1190 | PS_PRIO(0) | | |
1191 | VS_PRIO(1) | | |
1192 | GS_PRIO(2) | | |
1193 | ES_PRIO(3)); | |
1194 | ||
1195 | if ((rdev->family) == CHIP_R600) { | |
1196 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | | |
1197 | NUM_VS_GPRS(124) | | |
1198 | NUM_CLAUSE_TEMP_GPRS(4)); | |
1199 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | | |
1200 | NUM_ES_GPRS(0)); | |
1201 | sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | | |
1202 | NUM_VS_THREADS(48) | | |
1203 | NUM_GS_THREADS(4) | | |
1204 | NUM_ES_THREADS(4)); | |
1205 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | | |
1206 | NUM_VS_STACK_ENTRIES(128)); | |
1207 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | | |
1208 | NUM_ES_STACK_ENTRIES(0)); | |
1209 | } else if (((rdev->family) == CHIP_RV610) || | |
1210 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1211 | ((rdev->family) == CHIP_RS780) || |
1212 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1213 | /* no vertex cache */ |
1214 | sq_config &= ~VC_ENABLE; | |
1215 | ||
1216 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1217 | NUM_VS_GPRS(44) | | |
1218 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1219 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
1220 | NUM_ES_GPRS(17)); | |
1221 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1222 | NUM_VS_THREADS(78) | | |
1223 | NUM_GS_THREADS(4) | | |
1224 | NUM_ES_THREADS(31)); | |
1225 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
1226 | NUM_VS_STACK_ENTRIES(40)); | |
1227 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
1228 | NUM_ES_STACK_ENTRIES(16)); | |
1229 | } else if (((rdev->family) == CHIP_RV630) || | |
1230 | ((rdev->family) == CHIP_RV635)) { | |
1231 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1232 | NUM_VS_GPRS(44) | | |
1233 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1234 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | | |
1235 | NUM_ES_GPRS(18)); | |
1236 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1237 | NUM_VS_THREADS(78) | | |
1238 | NUM_GS_THREADS(4) | | |
1239 | NUM_ES_THREADS(31)); | |
1240 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
1241 | NUM_VS_STACK_ENTRIES(40)); | |
1242 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
1243 | NUM_ES_STACK_ENTRIES(16)); | |
1244 | } else if ((rdev->family) == CHIP_RV670) { | |
1245 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
1246 | NUM_VS_GPRS(44) | | |
1247 | NUM_CLAUSE_TEMP_GPRS(2)); | |
1248 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
1249 | NUM_ES_GPRS(17)); | |
1250 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
1251 | NUM_VS_THREADS(78) | | |
1252 | NUM_GS_THREADS(4) | | |
1253 | NUM_ES_THREADS(31)); | |
1254 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | | |
1255 | NUM_VS_STACK_ENTRIES(64)); | |
1256 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | | |
1257 | NUM_ES_STACK_ENTRIES(64)); | |
1258 | } | |
1259 | ||
1260 | WREG32(SQ_CONFIG, sq_config); | |
1261 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
1262 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
1263 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
1264 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
1265 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
1266 | ||
1267 | if (((rdev->family) == CHIP_RV610) || | |
1268 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
1269 | ((rdev->family) == CHIP_RS780) || |
1270 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
1271 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); |
1272 | } else { | |
1273 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); | |
1274 | } | |
1275 | ||
1276 | /* More default values. 2D/3D driver should adjust as needed */ | |
1277 | WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | | |
1278 | S1_X(0x4) | S1_Y(0xc))); | |
1279 | WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | | |
1280 | S1_X(0x2) | S1_Y(0x2) | | |
1281 | S2_X(0xa) | S2_Y(0x6) | | |
1282 | S3_X(0x6) | S3_Y(0xa))); | |
1283 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | | |
1284 | S1_X(0x4) | S1_Y(0xc) | | |
1285 | S2_X(0x1) | S2_Y(0x6) | | |
1286 | S3_X(0xa) | S3_Y(0xe))); | |
1287 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | | |
1288 | S5_X(0x0) | S5_Y(0x0) | | |
1289 | S6_X(0xb) | S6_Y(0x4) | | |
1290 | S7_X(0x7) | S7_Y(0x8))); | |
1291 | ||
1292 | WREG32(VGT_STRMOUT_EN, 0); | |
1293 | tmp = rdev->config.r600.max_pipes * 16; | |
1294 | switch (rdev->family) { | |
1295 | case CHIP_RV610: | |
3ce0a23d | 1296 | case CHIP_RV620: |
ee59f2b4 AD |
1297 | case CHIP_RS780: |
1298 | case CHIP_RS880: | |
3ce0a23d JG |
1299 | tmp += 32; |
1300 | break; | |
1301 | case CHIP_RV670: | |
1302 | tmp += 128; | |
1303 | break; | |
1304 | default: | |
1305 | break; | |
1306 | } | |
1307 | if (tmp > 256) { | |
1308 | tmp = 256; | |
1309 | } | |
1310 | WREG32(VGT_ES_PER_GS, 128); | |
1311 | WREG32(VGT_GS_PER_ES, tmp); | |
1312 | WREG32(VGT_GS_PER_VS, 2); | |
1313 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
1314 | ||
1315 | /* more default values. 2D/3D driver should adjust as needed */ | |
1316 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); | |
1317 | WREG32(VGT_STRMOUT_EN, 0); | |
1318 | WREG32(SX_MISC, 0); | |
1319 | WREG32(PA_SC_MODE_CNTL, 0); | |
1320 | WREG32(PA_SC_AA_CONFIG, 0); | |
1321 | WREG32(PA_SC_LINE_STIPPLE, 0); | |
1322 | WREG32(SPI_INPUT_Z, 0); | |
1323 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); | |
1324 | WREG32(CB_COLOR7_FRAG, 0); | |
1325 | ||
1326 | /* Clear render buffer base addresses */ | |
1327 | WREG32(CB_COLOR0_BASE, 0); | |
1328 | WREG32(CB_COLOR1_BASE, 0); | |
1329 | WREG32(CB_COLOR2_BASE, 0); | |
1330 | WREG32(CB_COLOR3_BASE, 0); | |
1331 | WREG32(CB_COLOR4_BASE, 0); | |
1332 | WREG32(CB_COLOR5_BASE, 0); | |
1333 | WREG32(CB_COLOR6_BASE, 0); | |
1334 | WREG32(CB_COLOR7_BASE, 0); | |
1335 | WREG32(CB_COLOR7_FRAG, 0); | |
1336 | ||
1337 | switch (rdev->family) { | |
1338 | case CHIP_RV610: | |
3ce0a23d | 1339 | case CHIP_RV620: |
ee59f2b4 AD |
1340 | case CHIP_RS780: |
1341 | case CHIP_RS880: | |
3ce0a23d JG |
1342 | tmp = TC_L2_SIZE(8); |
1343 | break; | |
1344 | case CHIP_RV630: | |
1345 | case CHIP_RV635: | |
1346 | tmp = TC_L2_SIZE(4); | |
1347 | break; | |
1348 | case CHIP_R600: | |
1349 | tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; | |
1350 | break; | |
1351 | default: | |
1352 | tmp = TC_L2_SIZE(0); | |
1353 | break; | |
1354 | } | |
1355 | WREG32(TC_CNTL, tmp); | |
1356 | ||
1357 | tmp = RREG32(HDP_HOST_PATH_CNTL); | |
1358 | WREG32(HDP_HOST_PATH_CNTL, tmp); | |
1359 | ||
1360 | tmp = RREG32(ARB_POP); | |
1361 | tmp |= ENABLE_TC128; | |
1362 | WREG32(ARB_POP, tmp); | |
1363 | ||
1364 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
1365 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | | |
1366 | NUM_CLIP_SEQ(3))); | |
1367 | WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); | |
1368 | } | |
1369 | ||
1370 | ||
771fe6b9 JG |
1371 | /* |
1372 | * Indirect registers accessor | |
1373 | */ | |
3ce0a23d JG |
1374 | u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) |
1375 | { | |
1376 | u32 r; | |
1377 | ||
1378 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); | |
1379 | (void)RREG32(PCIE_PORT_INDEX); | |
1380 | r = RREG32(PCIE_PORT_DATA); | |
1381 | return r; | |
1382 | } | |
1383 | ||
1384 | void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
1385 | { | |
1386 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); | |
1387 | (void)RREG32(PCIE_PORT_INDEX); | |
1388 | WREG32(PCIE_PORT_DATA, (v)); | |
1389 | (void)RREG32(PCIE_PORT_DATA); | |
1390 | } | |
1391 | ||
3ce0a23d JG |
1392 | /* |
1393 | * CP & Ring | |
1394 | */ | |
1395 | void r600_cp_stop(struct radeon_device *rdev) | |
1396 | { | |
1397 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); | |
1398 | } | |
1399 | ||
d8f60cfc | 1400 | int r600_init_microcode(struct radeon_device *rdev) |
3ce0a23d JG |
1401 | { |
1402 | struct platform_device *pdev; | |
1403 | const char *chip_name; | |
d8f60cfc AD |
1404 | const char *rlc_chip_name; |
1405 | size_t pfp_req_size, me_req_size, rlc_req_size; | |
3ce0a23d JG |
1406 | char fw_name[30]; |
1407 | int err; | |
1408 | ||
1409 | DRM_DEBUG("\n"); | |
1410 | ||
1411 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); | |
1412 | err = IS_ERR(pdev); | |
1413 | if (err) { | |
1414 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); | |
1415 | return -EINVAL; | |
1416 | } | |
1417 | ||
1418 | switch (rdev->family) { | |
d8f60cfc AD |
1419 | case CHIP_R600: |
1420 | chip_name = "R600"; | |
1421 | rlc_chip_name = "R600"; | |
1422 | break; | |
1423 | case CHIP_RV610: | |
1424 | chip_name = "RV610"; | |
1425 | rlc_chip_name = "R600"; | |
1426 | break; | |
1427 | case CHIP_RV630: | |
1428 | chip_name = "RV630"; | |
1429 | rlc_chip_name = "R600"; | |
1430 | break; | |
1431 | case CHIP_RV620: | |
1432 | chip_name = "RV620"; | |
1433 | rlc_chip_name = "R600"; | |
1434 | break; | |
1435 | case CHIP_RV635: | |
1436 | chip_name = "RV635"; | |
1437 | rlc_chip_name = "R600"; | |
1438 | break; | |
1439 | case CHIP_RV670: | |
1440 | chip_name = "RV670"; | |
1441 | rlc_chip_name = "R600"; | |
1442 | break; | |
3ce0a23d | 1443 | case CHIP_RS780: |
d8f60cfc AD |
1444 | case CHIP_RS880: |
1445 | chip_name = "RS780"; | |
1446 | rlc_chip_name = "R600"; | |
1447 | break; | |
1448 | case CHIP_RV770: | |
1449 | chip_name = "RV770"; | |
1450 | rlc_chip_name = "R700"; | |
1451 | break; | |
3ce0a23d | 1452 | case CHIP_RV730: |
d8f60cfc AD |
1453 | case CHIP_RV740: |
1454 | chip_name = "RV730"; | |
1455 | rlc_chip_name = "R700"; | |
1456 | break; | |
1457 | case CHIP_RV710: | |
1458 | chip_name = "RV710"; | |
1459 | rlc_chip_name = "R700"; | |
1460 | break; | |
3ce0a23d JG |
1461 | default: BUG(); |
1462 | } | |
1463 | ||
1464 | if (rdev->family >= CHIP_RV770) { | |
1465 | pfp_req_size = R700_PFP_UCODE_SIZE * 4; | |
1466 | me_req_size = R700_PM4_UCODE_SIZE * 4; | |
d8f60cfc | 1467 | rlc_req_size = R700_RLC_UCODE_SIZE * 4; |
3ce0a23d JG |
1468 | } else { |
1469 | pfp_req_size = PFP_UCODE_SIZE * 4; | |
1470 | me_req_size = PM4_UCODE_SIZE * 12; | |
d8f60cfc | 1471 | rlc_req_size = RLC_UCODE_SIZE * 4; |
3ce0a23d JG |
1472 | } |
1473 | ||
d8f60cfc | 1474 | DRM_INFO("Loading %s Microcode\n", chip_name); |
3ce0a23d JG |
1475 | |
1476 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); | |
1477 | err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev); | |
1478 | if (err) | |
1479 | goto out; | |
1480 | if (rdev->pfp_fw->size != pfp_req_size) { | |
1481 | printk(KERN_ERR | |
1482 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
1483 | rdev->pfp_fw->size, fw_name); | |
1484 | err = -EINVAL; | |
1485 | goto out; | |
1486 | } | |
1487 | ||
1488 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); | |
1489 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); | |
1490 | if (err) | |
1491 | goto out; | |
1492 | if (rdev->me_fw->size != me_req_size) { | |
1493 | printk(KERN_ERR | |
1494 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
1495 | rdev->me_fw->size, fw_name); | |
1496 | err = -EINVAL; | |
1497 | } | |
d8f60cfc AD |
1498 | |
1499 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); | |
1500 | err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev); | |
1501 | if (err) | |
1502 | goto out; | |
1503 | if (rdev->rlc_fw->size != rlc_req_size) { | |
1504 | printk(KERN_ERR | |
1505 | "r600_rlc: Bogus length %zu in firmware \"%s\"\n", | |
1506 | rdev->rlc_fw->size, fw_name); | |
1507 | err = -EINVAL; | |
1508 | } | |
1509 | ||
3ce0a23d JG |
1510 | out: |
1511 | platform_device_unregister(pdev); | |
1512 | ||
1513 | if (err) { | |
1514 | if (err != -EINVAL) | |
1515 | printk(KERN_ERR | |
1516 | "r600_cp: Failed to load firmware \"%s\"\n", | |
1517 | fw_name); | |
1518 | release_firmware(rdev->pfp_fw); | |
1519 | rdev->pfp_fw = NULL; | |
1520 | release_firmware(rdev->me_fw); | |
1521 | rdev->me_fw = NULL; | |
d8f60cfc AD |
1522 | release_firmware(rdev->rlc_fw); |
1523 | rdev->rlc_fw = NULL; | |
3ce0a23d JG |
1524 | } |
1525 | return err; | |
1526 | } | |
1527 | ||
1528 | static int r600_cp_load_microcode(struct radeon_device *rdev) | |
1529 | { | |
1530 | const __be32 *fw_data; | |
1531 | int i; | |
1532 | ||
1533 | if (!rdev->me_fw || !rdev->pfp_fw) | |
1534 | return -EINVAL; | |
1535 | ||
1536 | r600_cp_stop(rdev); | |
1537 | ||
1538 | WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | |
1539 | ||
1540 | /* Reset cp */ | |
1541 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
1542 | RREG32(GRBM_SOFT_RESET); | |
1543 | mdelay(15); | |
1544 | WREG32(GRBM_SOFT_RESET, 0); | |
1545 | ||
1546 | WREG32(CP_ME_RAM_WADDR, 0); | |
1547 | ||
1548 | fw_data = (const __be32 *)rdev->me_fw->data; | |
1549 | WREG32(CP_ME_RAM_WADDR, 0); | |
1550 | for (i = 0; i < PM4_UCODE_SIZE * 3; i++) | |
1551 | WREG32(CP_ME_RAM_DATA, | |
1552 | be32_to_cpup(fw_data++)); | |
1553 | ||
1554 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
1555 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1556 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
1557 | WREG32(CP_PFP_UCODE_DATA, | |
1558 | be32_to_cpup(fw_data++)); | |
1559 | ||
1560 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
1561 | WREG32(CP_ME_RAM_WADDR, 0); | |
1562 | WREG32(CP_ME_RAM_RADDR, 0); | |
1563 | return 0; | |
1564 | } | |
1565 | ||
1566 | int r600_cp_start(struct radeon_device *rdev) | |
1567 | { | |
1568 | int r; | |
1569 | uint32_t cp_me; | |
1570 | ||
1571 | r = radeon_ring_lock(rdev, 7); | |
1572 | if (r) { | |
1573 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
1574 | return r; | |
1575 | } | |
1576 | radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); | |
1577 | radeon_ring_write(rdev, 0x1); | |
1578 | if (rdev->family < CHIP_RV770) { | |
1579 | radeon_ring_write(rdev, 0x3); | |
1580 | radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); | |
1581 | } else { | |
1582 | radeon_ring_write(rdev, 0x0); | |
1583 | radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); | |
1584 | } | |
1585 | radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); | |
1586 | radeon_ring_write(rdev, 0); | |
1587 | radeon_ring_write(rdev, 0); | |
1588 | radeon_ring_unlock_commit(rdev); | |
1589 | ||
1590 | cp_me = 0xff; | |
1591 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); | |
1592 | return 0; | |
1593 | } | |
1594 | ||
1595 | int r600_cp_resume(struct radeon_device *rdev) | |
1596 | { | |
1597 | u32 tmp; | |
1598 | u32 rb_bufsz; | |
1599 | int r; | |
1600 | ||
1601 | /* Reset cp */ | |
1602 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
1603 | RREG32(GRBM_SOFT_RESET); | |
1604 | mdelay(15); | |
1605 | WREG32(GRBM_SOFT_RESET, 0); | |
1606 | ||
1607 | /* Set ring buffer size */ | |
1608 | rb_bufsz = drm_order(rdev->cp.ring_size / 8); | |
d6f28938 | 1609 | tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; |
3ce0a23d | 1610 | #ifdef __BIG_ENDIAN |
d6f28938 | 1611 | tmp |= BUF_SWAP_32BIT; |
3ce0a23d | 1612 | #endif |
d6f28938 | 1613 | WREG32(CP_RB_CNTL, tmp); |
3ce0a23d JG |
1614 | WREG32(CP_SEM_WAIT_TIMER, 0x4); |
1615 | ||
1616 | /* Set the write pointer delay */ | |
1617 | WREG32(CP_RB_WPTR_DELAY, 0); | |
1618 | ||
1619 | /* Initialize the ring buffer's read and write pointers */ | |
3ce0a23d JG |
1620 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
1621 | WREG32(CP_RB_RPTR_WR, 0); | |
1622 | WREG32(CP_RB_WPTR, 0); | |
1623 | WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF); | |
1624 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr)); | |
1625 | mdelay(1); | |
1626 | WREG32(CP_RB_CNTL, tmp); | |
1627 | ||
1628 | WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); | |
1629 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); | |
1630 | ||
1631 | rdev->cp.rptr = RREG32(CP_RB_RPTR); | |
1632 | rdev->cp.wptr = RREG32(CP_RB_WPTR); | |
1633 | ||
1634 | r600_cp_start(rdev); | |
1635 | rdev->cp.ready = true; | |
1636 | r = radeon_ring_test(rdev); | |
1637 | if (r) { | |
1638 | rdev->cp.ready = false; | |
1639 | return r; | |
1640 | } | |
1641 | return 0; | |
1642 | } | |
1643 | ||
1644 | void r600_cp_commit(struct radeon_device *rdev) | |
1645 | { | |
1646 | WREG32(CP_RB_WPTR, rdev->cp.wptr); | |
1647 | (void)RREG32(CP_RB_WPTR); | |
1648 | } | |
1649 | ||
1650 | void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) | |
1651 | { | |
1652 | u32 rb_bufsz; | |
1653 | ||
1654 | /* Align ring size */ | |
1655 | rb_bufsz = drm_order(ring_size / 8); | |
1656 | ring_size = (1 << (rb_bufsz + 1)) * 4; | |
1657 | rdev->cp.ring_size = ring_size; | |
1658 | rdev->cp.align_mask = 16 - 1; | |
1659 | } | |
1660 | ||
1661 | ||
1662 | /* | |
1663 | * GPU scratch registers helpers function. | |
1664 | */ | |
1665 | void r600_scratch_init(struct radeon_device *rdev) | |
1666 | { | |
1667 | int i; | |
1668 | ||
1669 | rdev->scratch.num_reg = 7; | |
1670 | for (i = 0; i < rdev->scratch.num_reg; i++) { | |
1671 | rdev->scratch.free[i] = true; | |
1672 | rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4); | |
1673 | } | |
1674 | } | |
1675 | ||
1676 | int r600_ring_test(struct radeon_device *rdev) | |
1677 | { | |
1678 | uint32_t scratch; | |
1679 | uint32_t tmp = 0; | |
1680 | unsigned i; | |
1681 | int r; | |
1682 | ||
1683 | r = radeon_scratch_get(rdev, &scratch); | |
1684 | if (r) { | |
1685 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); | |
1686 | return r; | |
1687 | } | |
1688 | WREG32(scratch, 0xCAFEDEAD); | |
1689 | r = radeon_ring_lock(rdev, 3); | |
1690 | if (r) { | |
1691 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
1692 | radeon_scratch_free(rdev, scratch); | |
1693 | return r; | |
1694 | } | |
1695 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
1696 | radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
1697 | radeon_ring_write(rdev, 0xDEADBEEF); | |
1698 | radeon_ring_unlock_commit(rdev); | |
1699 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1700 | tmp = RREG32(scratch); | |
1701 | if (tmp == 0xDEADBEEF) | |
1702 | break; | |
1703 | DRM_UDELAY(1); | |
1704 | } | |
1705 | if (i < rdev->usec_timeout) { | |
1706 | DRM_INFO("ring test succeeded in %d usecs\n", i); | |
1707 | } else { | |
1708 | DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", | |
1709 | scratch, tmp); | |
1710 | r = -EINVAL; | |
1711 | } | |
1712 | radeon_scratch_free(rdev, scratch); | |
1713 | return r; | |
1714 | } | |
1715 | ||
81cc35bf JG |
1716 | void r600_wb_disable(struct radeon_device *rdev) |
1717 | { | |
4c788679 JG |
1718 | int r; |
1719 | ||
81cc35bf JG |
1720 | WREG32(SCRATCH_UMSK, 0); |
1721 | if (rdev->wb.wb_obj) { | |
4c788679 JG |
1722 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
1723 | if (unlikely(r != 0)) | |
1724 | return; | |
1725 | radeon_bo_kunmap(rdev->wb.wb_obj); | |
1726 | radeon_bo_unpin(rdev->wb.wb_obj); | |
1727 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
81cc35bf JG |
1728 | } |
1729 | } | |
1730 | ||
1731 | void r600_wb_fini(struct radeon_device *rdev) | |
1732 | { | |
1733 | r600_wb_disable(rdev); | |
1734 | if (rdev->wb.wb_obj) { | |
4c788679 | 1735 | radeon_bo_unref(&rdev->wb.wb_obj); |
81cc35bf JG |
1736 | rdev->wb.wb = NULL; |
1737 | rdev->wb.wb_obj = NULL; | |
1738 | } | |
1739 | } | |
1740 | ||
1741 | int r600_wb_enable(struct radeon_device *rdev) | |
3ce0a23d JG |
1742 | { |
1743 | int r; | |
1744 | ||
1745 | if (rdev->wb.wb_obj == NULL) { | |
4c788679 JG |
1746 | r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, |
1747 | RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); | |
3ce0a23d | 1748 | if (r) { |
4c788679 | 1749 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
3ce0a23d JG |
1750 | return r; |
1751 | } | |
4c788679 JG |
1752 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
1753 | if (unlikely(r != 0)) { | |
1754 | r600_wb_fini(rdev); | |
3ce0a23d JG |
1755 | return r; |
1756 | } | |
4c788679 | 1757 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
81cc35bf | 1758 | &rdev->wb.gpu_addr); |
3ce0a23d | 1759 | if (r) { |
4c788679 JG |
1760 | radeon_bo_unreserve(rdev->wb.wb_obj); |
1761 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); | |
81cc35bf | 1762 | r600_wb_fini(rdev); |
3ce0a23d JG |
1763 | return r; |
1764 | } | |
4c788679 JG |
1765 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
1766 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
3ce0a23d | 1767 | if (r) { |
4c788679 | 1768 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
81cc35bf | 1769 | r600_wb_fini(rdev); |
3ce0a23d JG |
1770 | return r; |
1771 | } | |
1772 | } | |
1773 | WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF); | |
1774 | WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC); | |
1775 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF); | |
1776 | WREG32(SCRATCH_UMSK, 0xff); | |
1777 | return 0; | |
1778 | } | |
1779 | ||
3ce0a23d JG |
1780 | void r600_fence_ring_emit(struct radeon_device *rdev, |
1781 | struct radeon_fence *fence) | |
1782 | { | |
d8f60cfc | 1783 | /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */ |
3ce0a23d JG |
1784 | /* Emit fence sequence & fire IRQ */ |
1785 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
1786 | radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
1787 | radeon_ring_write(rdev, fence->seq); | |
cafe6609 JG |
1788 | radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); |
1789 | radeon_ring_write(rdev, 1); | |
d8f60cfc AD |
1790 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
1791 | radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); | |
1792 | radeon_ring_write(rdev, RB_INT_STAT); | |
3ce0a23d JG |
1793 | } |
1794 | ||
1795 | int r600_copy_dma(struct radeon_device *rdev, | |
1796 | uint64_t src_offset, | |
1797 | uint64_t dst_offset, | |
1798 | unsigned num_pages, | |
1799 | struct radeon_fence *fence) | |
1800 | { | |
1801 | /* FIXME: implement */ | |
1802 | return 0; | |
1803 | } | |
1804 | ||
1805 | int r600_copy_blit(struct radeon_device *rdev, | |
1806 | uint64_t src_offset, uint64_t dst_offset, | |
1807 | unsigned num_pages, struct radeon_fence *fence) | |
1808 | { | |
a77f1718 MT |
1809 | r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); |
1810 | r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); | |
3ce0a23d JG |
1811 | r600_blit_done_copy(rdev, fence); |
1812 | return 0; | |
1813 | } | |
1814 | ||
3ce0a23d JG |
1815 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
1816 | uint32_t tiling_flags, uint32_t pitch, | |
1817 | uint32_t offset, uint32_t obj_size) | |
1818 | { | |
1819 | /* FIXME: implement */ | |
1820 | return 0; | |
1821 | } | |
1822 | ||
1823 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg) | |
1824 | { | |
1825 | /* FIXME: implement */ | |
1826 | } | |
1827 | ||
1828 | ||
1829 | bool r600_card_posted(struct radeon_device *rdev) | |
1830 | { | |
1831 | uint32_t reg; | |
1832 | ||
1833 | /* first check CRTCs */ | |
1834 | reg = RREG32(D1CRTC_CONTROL) | | |
1835 | RREG32(D2CRTC_CONTROL); | |
1836 | if (reg & CRTC_EN) | |
1837 | return true; | |
1838 | ||
1839 | /* then check MEM_SIZE, in case the crtcs are off */ | |
1840 | if (RREG32(CONFIG_MEMSIZE)) | |
1841 | return true; | |
1842 | ||
1843 | return false; | |
1844 | } | |
1845 | ||
fc30b8ef | 1846 | int r600_startup(struct radeon_device *rdev) |
3ce0a23d JG |
1847 | { |
1848 | int r; | |
1849 | ||
779720a3 AD |
1850 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
1851 | r = r600_init_microcode(rdev); | |
1852 | if (r) { | |
1853 | DRM_ERROR("Failed to load firmware!\n"); | |
1854 | return r; | |
1855 | } | |
1856 | } | |
1857 | ||
a3c1945a | 1858 | r600_mc_program(rdev); |
1a029b76 JG |
1859 | if (rdev->flags & RADEON_IS_AGP) { |
1860 | r600_agp_enable(rdev); | |
1861 | } else { | |
1862 | r = r600_pcie_gart_enable(rdev); | |
1863 | if (r) | |
1864 | return r; | |
1865 | } | |
3ce0a23d | 1866 | r600_gpu_init(rdev); |
bc1a631e | 1867 | |
7923c615 AD |
1868 | if (!rdev->r600_blit.shader_obj) { |
1869 | r = r600_blit_init(rdev); | |
1870 | if (r) { | |
1871 | DRM_ERROR("radeon: failed blitter (%d).\n", r); | |
1872 | return r; | |
1873 | } | |
1874 | } | |
1875 | ||
4c788679 JG |
1876 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
1877 | if (unlikely(r != 0)) | |
1878 | return r; | |
1879 | r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, | |
1880 | &rdev->r600_blit.shader_gpu_addr); | |
1881 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | |
bc1a631e | 1882 | if (r) { |
4c788679 | 1883 | dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
bc1a631e DA |
1884 | return r; |
1885 | } | |
1886 | ||
d8f60cfc | 1887 | /* Enable IRQ */ |
d8f60cfc AD |
1888 | r = r600_irq_init(rdev); |
1889 | if (r) { | |
1890 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
1891 | radeon_irq_kms_fini(rdev); | |
1892 | return r; | |
1893 | } | |
1894 | r600_irq_set(rdev); | |
1895 | ||
3ce0a23d JG |
1896 | r = radeon_ring_init(rdev, rdev->cp.ring_size); |
1897 | if (r) | |
1898 | return r; | |
1899 | r = r600_cp_load_microcode(rdev); | |
1900 | if (r) | |
1901 | return r; | |
1902 | r = r600_cp_resume(rdev); | |
1903 | if (r) | |
1904 | return r; | |
81cc35bf JG |
1905 | /* write back buffer are not vital so don't worry about failure */ |
1906 | r600_wb_enable(rdev); | |
3ce0a23d JG |
1907 | return 0; |
1908 | } | |
1909 | ||
28d52043 DA |
1910 | void r600_vga_set_state(struct radeon_device *rdev, bool state) |
1911 | { | |
1912 | uint32_t temp; | |
1913 | ||
1914 | temp = RREG32(CONFIG_CNTL); | |
1915 | if (state == false) { | |
1916 | temp &= ~(1<<0); | |
1917 | temp |= (1<<1); | |
1918 | } else { | |
1919 | temp &= ~(1<<1); | |
1920 | } | |
1921 | WREG32(CONFIG_CNTL, temp); | |
1922 | } | |
1923 | ||
fc30b8ef DA |
1924 | int r600_resume(struct radeon_device *rdev) |
1925 | { | |
1926 | int r; | |
1927 | ||
1a029b76 JG |
1928 | /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, |
1929 | * posting will perform necessary task to bring back GPU into good | |
1930 | * shape. | |
1931 | */ | |
fc30b8ef | 1932 | /* post card */ |
e7d40b9a | 1933 | atom_asic_init(rdev->mode_info.atom_context); |
fc30b8ef DA |
1934 | /* Initialize clocks */ |
1935 | r = radeon_clocks_init(rdev); | |
1936 | if (r) { | |
1937 | return r; | |
1938 | } | |
1939 | ||
1940 | r = r600_startup(rdev); | |
1941 | if (r) { | |
1942 | DRM_ERROR("r600 startup failed on resume\n"); | |
1943 | return r; | |
1944 | } | |
1945 | ||
62a8ea3f | 1946 | r = r600_ib_test(rdev); |
fc30b8ef DA |
1947 | if (r) { |
1948 | DRM_ERROR("radeon: failled testing IB (%d).\n", r); | |
1949 | return r; | |
1950 | } | |
1951 | return r; | |
1952 | } | |
1953 | ||
3ce0a23d JG |
1954 | int r600_suspend(struct radeon_device *rdev) |
1955 | { | |
4c788679 JG |
1956 | int r; |
1957 | ||
3ce0a23d JG |
1958 | /* FIXME: we should wait for ring to be empty */ |
1959 | r600_cp_stop(rdev); | |
bc1a631e | 1960 | rdev->cp.ready = false; |
81cc35bf | 1961 | r600_wb_disable(rdev); |
4aac0473 | 1962 | r600_pcie_gart_disable(rdev); |
bc1a631e | 1963 | /* unpin shaders bo */ |
4c788679 JG |
1964 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
1965 | if (unlikely(r != 0)) | |
1966 | return r; | |
1967 | radeon_bo_unpin(rdev->r600_blit.shader_obj); | |
1968 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); | |
3ce0a23d JG |
1969 | return 0; |
1970 | } | |
1971 | ||
1972 | /* Plan is to move initialization in that function and use | |
1973 | * helper function so that radeon_device_init pretty much | |
1974 | * do nothing more than calling asic specific function. This | |
1975 | * should also allow to remove a bunch of callback function | |
1976 | * like vram_info. | |
1977 | */ | |
1978 | int r600_init(struct radeon_device *rdev) | |
771fe6b9 | 1979 | { |
3ce0a23d | 1980 | int r; |
771fe6b9 | 1981 | |
3ce0a23d JG |
1982 | r = radeon_dummy_page_init(rdev); |
1983 | if (r) | |
1984 | return r; | |
1985 | if (r600_debugfs_mc_info_init(rdev)) { | |
1986 | DRM_ERROR("Failed to register debugfs file for mc !\n"); | |
1987 | } | |
1988 | /* This don't do much */ | |
1989 | r = radeon_gem_init(rdev); | |
1990 | if (r) | |
1991 | return r; | |
1992 | /* Read BIOS */ | |
1993 | if (!radeon_get_bios(rdev)) { | |
1994 | if (ASIC_IS_AVIVO(rdev)) | |
1995 | return -EINVAL; | |
1996 | } | |
1997 | /* Must be an ATOMBIOS */ | |
e7d40b9a JG |
1998 | if (!rdev->is_atom_bios) { |
1999 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); | |
3ce0a23d | 2000 | return -EINVAL; |
e7d40b9a | 2001 | } |
3ce0a23d JG |
2002 | r = radeon_atombios_init(rdev); |
2003 | if (r) | |
2004 | return r; | |
2005 | /* Post card if necessary */ | |
72542d77 DA |
2006 | if (!r600_card_posted(rdev)) { |
2007 | if (!rdev->bios) { | |
2008 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
2009 | return -EINVAL; | |
2010 | } | |
3ce0a23d JG |
2011 | DRM_INFO("GPU not posted. posting now...\n"); |
2012 | atom_asic_init(rdev->mode_info.atom_context); | |
2013 | } | |
2014 | /* Initialize scratch registers */ | |
2015 | r600_scratch_init(rdev); | |
2016 | /* Initialize surface registers */ | |
2017 | radeon_surface_init(rdev); | |
7433874e | 2018 | /* Initialize clocks */ |
5e6dde7e | 2019 | radeon_get_clock_info(rdev->ddev); |
3ce0a23d JG |
2020 | r = radeon_clocks_init(rdev); |
2021 | if (r) | |
2022 | return r; | |
7433874e RM |
2023 | /* Initialize power management */ |
2024 | radeon_pm_init(rdev); | |
3ce0a23d JG |
2025 | /* Fence driver */ |
2026 | r = radeon_fence_driver_init(rdev); | |
2027 | if (r) | |
2028 | return r; | |
2029 | r = r600_mc_init(rdev); | |
b574f251 | 2030 | if (r) |
3ce0a23d | 2031 | return r; |
3ce0a23d | 2032 | /* Memory manager */ |
4c788679 | 2033 | r = radeon_bo_init(rdev); |
3ce0a23d JG |
2034 | if (r) |
2035 | return r; | |
d8f60cfc AD |
2036 | |
2037 | r = radeon_irq_kms_init(rdev); | |
2038 | if (r) | |
2039 | return r; | |
2040 | ||
3ce0a23d JG |
2041 | rdev->cp.ring_obj = NULL; |
2042 | r600_ring_init(rdev, 1024 * 1024); | |
2043 | ||
d8f60cfc AD |
2044 | rdev->ih.ring_obj = NULL; |
2045 | r600_ih_ring_init(rdev, 64 * 1024); | |
3ce0a23d | 2046 | |
4aac0473 JG |
2047 | r = r600_pcie_gart_init(rdev); |
2048 | if (r) | |
2049 | return r; | |
2050 | ||
779720a3 | 2051 | rdev->accel_working = true; |
fc30b8ef | 2052 | r = r600_startup(rdev); |
3ce0a23d | 2053 | if (r) { |
75c81298 JG |
2054 | r600_suspend(rdev); |
2055 | r600_wb_fini(rdev); | |
75c81298 JG |
2056 | radeon_ring_fini(rdev); |
2057 | r600_pcie_gart_fini(rdev); | |
733289c2 | 2058 | rdev->accel_working = false; |
3ce0a23d | 2059 | } |
733289c2 JG |
2060 | if (rdev->accel_working) { |
2061 | r = radeon_ib_pool_init(rdev); | |
2062 | if (r) { | |
779720a3 | 2063 | DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); |
733289c2 JG |
2064 | rdev->accel_working = false; |
2065 | } | |
62a8ea3f | 2066 | r = r600_ib_test(rdev); |
733289c2 | 2067 | if (r) { |
779720a3 | 2068 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
733289c2 JG |
2069 | rdev->accel_working = false; |
2070 | } | |
3ce0a23d | 2071 | } |
dafc3bd5 CK |
2072 | |
2073 | r = r600_audio_init(rdev); | |
2074 | if (r) | |
2075 | return r; /* TODO error handling */ | |
3ce0a23d JG |
2076 | return 0; |
2077 | } | |
2078 | ||
2079 | void r600_fini(struct radeon_device *rdev) | |
2080 | { | |
2081 | /* Suspend operations */ | |
2082 | r600_suspend(rdev); | |
2083 | ||
dafc3bd5 | 2084 | r600_audio_fini(rdev); |
3ce0a23d | 2085 | r600_blit_fini(rdev); |
d8f60cfc AD |
2086 | r600_irq_fini(rdev); |
2087 | radeon_irq_kms_fini(rdev); | |
3ce0a23d | 2088 | radeon_ring_fini(rdev); |
81cc35bf | 2089 | r600_wb_fini(rdev); |
4aac0473 | 2090 | r600_pcie_gart_fini(rdev); |
3ce0a23d JG |
2091 | radeon_gem_fini(rdev); |
2092 | radeon_fence_driver_fini(rdev); | |
2093 | radeon_clocks_fini(rdev); | |
d0269ed8 | 2094 | radeon_agp_fini(rdev); |
4c788679 | 2095 | radeon_bo_fini(rdev); |
e7d40b9a | 2096 | radeon_atombios_fini(rdev); |
3ce0a23d JG |
2097 | kfree(rdev->bios); |
2098 | rdev->bios = NULL; | |
2099 | radeon_dummy_page_fini(rdev); | |
2100 | } | |
2101 | ||
2102 | ||
2103 | /* | |
2104 | * CS stuff | |
2105 | */ | |
2106 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
2107 | { | |
2108 | /* FIXME: implement */ | |
2109 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); | |
2110 | radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); | |
2111 | radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); | |
2112 | radeon_ring_write(rdev, ib->length_dw); | |
2113 | } | |
2114 | ||
2115 | int r600_ib_test(struct radeon_device *rdev) | |
2116 | { | |
2117 | struct radeon_ib *ib; | |
2118 | uint32_t scratch; | |
2119 | uint32_t tmp = 0; | |
2120 | unsigned i; | |
2121 | int r; | |
2122 | ||
2123 | r = radeon_scratch_get(rdev, &scratch); | |
2124 | if (r) { | |
2125 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); | |
2126 | return r; | |
2127 | } | |
2128 | WREG32(scratch, 0xCAFEDEAD); | |
2129 | r = radeon_ib_get(rdev, &ib); | |
2130 | if (r) { | |
2131 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); | |
2132 | return r; | |
2133 | } | |
2134 | ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); | |
2135 | ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2136 | ib->ptr[2] = 0xDEADBEEF; | |
2137 | ib->ptr[3] = PACKET2(0); | |
2138 | ib->ptr[4] = PACKET2(0); | |
2139 | ib->ptr[5] = PACKET2(0); | |
2140 | ib->ptr[6] = PACKET2(0); | |
2141 | ib->ptr[7] = PACKET2(0); | |
2142 | ib->ptr[8] = PACKET2(0); | |
2143 | ib->ptr[9] = PACKET2(0); | |
2144 | ib->ptr[10] = PACKET2(0); | |
2145 | ib->ptr[11] = PACKET2(0); | |
2146 | ib->ptr[12] = PACKET2(0); | |
2147 | ib->ptr[13] = PACKET2(0); | |
2148 | ib->ptr[14] = PACKET2(0); | |
2149 | ib->ptr[15] = PACKET2(0); | |
2150 | ib->length_dw = 16; | |
2151 | r = radeon_ib_schedule(rdev, ib); | |
2152 | if (r) { | |
2153 | radeon_scratch_free(rdev, scratch); | |
2154 | radeon_ib_free(rdev, &ib); | |
2155 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); | |
2156 | return r; | |
2157 | } | |
2158 | r = radeon_fence_wait(ib->fence, false); | |
2159 | if (r) { | |
2160 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); | |
2161 | return r; | |
2162 | } | |
2163 | for (i = 0; i < rdev->usec_timeout; i++) { | |
2164 | tmp = RREG32(scratch); | |
2165 | if (tmp == 0xDEADBEEF) | |
2166 | break; | |
2167 | DRM_UDELAY(1); | |
2168 | } | |
2169 | if (i < rdev->usec_timeout) { | |
2170 | DRM_INFO("ib test succeeded in %u usecs\n", i); | |
2171 | } else { | |
2172 | DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", | |
2173 | scratch, tmp); | |
2174 | r = -EINVAL; | |
2175 | } | |
2176 | radeon_scratch_free(rdev, scratch); | |
2177 | radeon_ib_free(rdev, &ib); | |
771fe6b9 JG |
2178 | return r; |
2179 | } | |
2180 | ||
d8f60cfc AD |
2181 | /* |
2182 | * Interrupts | |
2183 | * | |
2184 | * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty | |
2185 | * the same as the CP ring buffer, but in reverse. Rather than the CPU | |
2186 | * writing to the ring and the GPU consuming, the GPU writes to the ring | |
2187 | * and host consumes. As the host irq handler processes interrupts, it | |
2188 | * increments the rptr. When the rptr catches up with the wptr, all the | |
2189 | * current interrupts have been processed. | |
2190 | */ | |
2191 | ||
2192 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) | |
2193 | { | |
2194 | u32 rb_bufsz; | |
2195 | ||
2196 | /* Align ring size */ | |
2197 | rb_bufsz = drm_order(ring_size / 4); | |
2198 | ring_size = (1 << rb_bufsz) * 4; | |
2199 | rdev->ih.ring_size = ring_size; | |
2200 | rdev->ih.align_mask = 4 - 1; | |
2201 | } | |
2202 | ||
2203 | static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size) | |
2204 | { | |
2205 | int r; | |
2206 | ||
2207 | rdev->ih.ring_size = ring_size; | |
2208 | /* Allocate ring buffer */ | |
2209 | if (rdev->ih.ring_obj == NULL) { | |
4c788679 JG |
2210 | r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size, |
2211 | true, | |
2212 | RADEON_GEM_DOMAIN_GTT, | |
2213 | &rdev->ih.ring_obj); | |
d8f60cfc AD |
2214 | if (r) { |
2215 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); | |
2216 | return r; | |
2217 | } | |
4c788679 JG |
2218 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
2219 | if (unlikely(r != 0)) | |
2220 | return r; | |
2221 | r = radeon_bo_pin(rdev->ih.ring_obj, | |
2222 | RADEON_GEM_DOMAIN_GTT, | |
2223 | &rdev->ih.gpu_addr); | |
d8f60cfc | 2224 | if (r) { |
4c788679 | 2225 | radeon_bo_unreserve(rdev->ih.ring_obj); |
d8f60cfc AD |
2226 | DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); |
2227 | return r; | |
2228 | } | |
4c788679 JG |
2229 | r = radeon_bo_kmap(rdev->ih.ring_obj, |
2230 | (void **)&rdev->ih.ring); | |
2231 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
d8f60cfc AD |
2232 | if (r) { |
2233 | DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); | |
2234 | return r; | |
2235 | } | |
2236 | } | |
2237 | rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1; | |
2238 | rdev->ih.rptr = 0; | |
2239 | ||
2240 | return 0; | |
2241 | } | |
2242 | ||
2243 | static void r600_ih_ring_fini(struct radeon_device *rdev) | |
2244 | { | |
4c788679 | 2245 | int r; |
d8f60cfc | 2246 | if (rdev->ih.ring_obj) { |
4c788679 JG |
2247 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
2248 | if (likely(r == 0)) { | |
2249 | radeon_bo_kunmap(rdev->ih.ring_obj); | |
2250 | radeon_bo_unpin(rdev->ih.ring_obj); | |
2251 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
2252 | } | |
2253 | radeon_bo_unref(&rdev->ih.ring_obj); | |
d8f60cfc AD |
2254 | rdev->ih.ring = NULL; |
2255 | rdev->ih.ring_obj = NULL; | |
2256 | } | |
2257 | } | |
2258 | ||
2259 | static void r600_rlc_stop(struct radeon_device *rdev) | |
2260 | { | |
2261 | ||
2262 | if (rdev->family >= CHIP_RV770) { | |
2263 | /* r7xx asics need to soft reset RLC before halting */ | |
2264 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); | |
2265 | RREG32(SRBM_SOFT_RESET); | |
2266 | udelay(15000); | |
2267 | WREG32(SRBM_SOFT_RESET, 0); | |
2268 | RREG32(SRBM_SOFT_RESET); | |
2269 | } | |
2270 | ||
2271 | WREG32(RLC_CNTL, 0); | |
2272 | } | |
2273 | ||
2274 | static void r600_rlc_start(struct radeon_device *rdev) | |
2275 | { | |
2276 | WREG32(RLC_CNTL, RLC_ENABLE); | |
2277 | } | |
2278 | ||
2279 | static int r600_rlc_init(struct radeon_device *rdev) | |
2280 | { | |
2281 | u32 i; | |
2282 | const __be32 *fw_data; | |
2283 | ||
2284 | if (!rdev->rlc_fw) | |
2285 | return -EINVAL; | |
2286 | ||
2287 | r600_rlc_stop(rdev); | |
2288 | ||
2289 | WREG32(RLC_HB_BASE, 0); | |
2290 | WREG32(RLC_HB_CNTL, 0); | |
2291 | WREG32(RLC_HB_RPTR, 0); | |
2292 | WREG32(RLC_HB_WPTR, 0); | |
2293 | WREG32(RLC_HB_WPTR_LSB_ADDR, 0); | |
2294 | WREG32(RLC_HB_WPTR_MSB_ADDR, 0); | |
2295 | WREG32(RLC_MC_CNTL, 0); | |
2296 | WREG32(RLC_UCODE_CNTL, 0); | |
2297 | ||
2298 | fw_data = (const __be32 *)rdev->rlc_fw->data; | |
2299 | if (rdev->family >= CHIP_RV770) { | |
2300 | for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { | |
2301 | WREG32(RLC_UCODE_ADDR, i); | |
2302 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2303 | } | |
2304 | } else { | |
2305 | for (i = 0; i < RLC_UCODE_SIZE; i++) { | |
2306 | WREG32(RLC_UCODE_ADDR, i); | |
2307 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
2308 | } | |
2309 | } | |
2310 | WREG32(RLC_UCODE_ADDR, 0); | |
2311 | ||
2312 | r600_rlc_start(rdev); | |
2313 | ||
2314 | return 0; | |
2315 | } | |
2316 | ||
2317 | static void r600_enable_interrupts(struct radeon_device *rdev) | |
2318 | { | |
2319 | u32 ih_cntl = RREG32(IH_CNTL); | |
2320 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
2321 | ||
2322 | ih_cntl |= ENABLE_INTR; | |
2323 | ih_rb_cntl |= IH_RB_ENABLE; | |
2324 | WREG32(IH_CNTL, ih_cntl); | |
2325 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2326 | rdev->ih.enabled = true; | |
2327 | } | |
2328 | ||
2329 | static void r600_disable_interrupts(struct radeon_device *rdev) | |
2330 | { | |
2331 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
2332 | u32 ih_cntl = RREG32(IH_CNTL); | |
2333 | ||
2334 | ih_rb_cntl &= ~IH_RB_ENABLE; | |
2335 | ih_cntl &= ~ENABLE_INTR; | |
2336 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2337 | WREG32(IH_CNTL, ih_cntl); | |
2338 | /* set rptr, wptr to 0 */ | |
2339 | WREG32(IH_RB_RPTR, 0); | |
2340 | WREG32(IH_RB_WPTR, 0); | |
2341 | rdev->ih.enabled = false; | |
2342 | rdev->ih.wptr = 0; | |
2343 | rdev->ih.rptr = 0; | |
2344 | } | |
2345 | ||
e0df1ac5 AD |
2346 | static void r600_disable_interrupt_state(struct radeon_device *rdev) |
2347 | { | |
2348 | u32 tmp; | |
2349 | ||
2350 | WREG32(CP_INT_CNTL, 0); | |
2351 | WREG32(GRBM_INT_CNTL, 0); | |
2352 | WREG32(DxMODE_INT_MASK, 0); | |
2353 | if (ASIC_IS_DCE3(rdev)) { | |
2354 | WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); | |
2355 | WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); | |
2356 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2357 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2358 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2359 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2360 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2361 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2362 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2363 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2364 | if (ASIC_IS_DCE32(rdev)) { | |
2365 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2366 | WREG32(DC_HPD5_INT_CONTROL, 0); | |
2367 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
2368 | WREG32(DC_HPD6_INT_CONTROL, 0); | |
2369 | } | |
2370 | } else { | |
2371 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
2372 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); | |
2373 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
2374 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0); | |
2375 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
2376 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0); | |
2377 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
2378 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0); | |
2379 | } | |
2380 | } | |
2381 | ||
d8f60cfc AD |
2382 | int r600_irq_init(struct radeon_device *rdev) |
2383 | { | |
2384 | int ret = 0; | |
2385 | int rb_bufsz; | |
2386 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; | |
2387 | ||
2388 | /* allocate ring */ | |
2389 | ret = r600_ih_ring_alloc(rdev, rdev->ih.ring_size); | |
2390 | if (ret) | |
2391 | return ret; | |
2392 | ||
2393 | /* disable irqs */ | |
2394 | r600_disable_interrupts(rdev); | |
2395 | ||
2396 | /* init rlc */ | |
2397 | ret = r600_rlc_init(rdev); | |
2398 | if (ret) { | |
2399 | r600_ih_ring_fini(rdev); | |
2400 | return ret; | |
2401 | } | |
2402 | ||
2403 | /* setup interrupt control */ | |
2404 | /* set dummy read address to ring address */ | |
2405 | WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); | |
2406 | interrupt_cntl = RREG32(INTERRUPT_CNTL); | |
2407 | /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi | |
2408 | * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN | |
2409 | */ | |
2410 | interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; | |
2411 | /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ | |
2412 | interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; | |
2413 | WREG32(INTERRUPT_CNTL, interrupt_cntl); | |
2414 | ||
2415 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); | |
2416 | rb_bufsz = drm_order(rdev->ih.ring_size / 4); | |
2417 | ||
2418 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | | |
2419 | IH_WPTR_OVERFLOW_CLEAR | | |
2420 | (rb_bufsz << 1)); | |
2421 | /* WPTR writeback, not yet */ | |
2422 | /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/ | |
2423 | WREG32(IH_RB_WPTR_ADDR_LO, 0); | |
2424 | WREG32(IH_RB_WPTR_ADDR_HI, 0); | |
2425 | ||
2426 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
2427 | ||
2428 | /* set rptr, wptr to 0 */ | |
2429 | WREG32(IH_RB_RPTR, 0); | |
2430 | WREG32(IH_RB_WPTR, 0); | |
2431 | ||
2432 | /* Default settings for IH_CNTL (disabled at first) */ | |
2433 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); | |
2434 | /* RPTR_REARM only works if msi's are enabled */ | |
2435 | if (rdev->msi_enabled) | |
2436 | ih_cntl |= RPTR_REARM; | |
2437 | ||
2438 | #ifdef __BIG_ENDIAN | |
2439 | ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT); | |
2440 | #endif | |
2441 | WREG32(IH_CNTL, ih_cntl); | |
2442 | ||
2443 | /* force the active interrupt state to all disabled */ | |
e0df1ac5 | 2444 | r600_disable_interrupt_state(rdev); |
d8f60cfc AD |
2445 | |
2446 | /* enable irqs */ | |
2447 | r600_enable_interrupts(rdev); | |
2448 | ||
2449 | return ret; | |
2450 | } | |
2451 | ||
2452 | void r600_irq_fini(struct radeon_device *rdev) | |
2453 | { | |
2454 | r600_disable_interrupts(rdev); | |
2455 | r600_rlc_stop(rdev); | |
2456 | r600_ih_ring_fini(rdev); | |
2457 | } | |
2458 | ||
2459 | int r600_irq_set(struct radeon_device *rdev) | |
2460 | { | |
e0df1ac5 AD |
2461 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
2462 | u32 mode_int = 0; | |
2463 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; | |
d8f60cfc | 2464 | |
003e69f9 JG |
2465 | if (!rdev->irq.installed) { |
2466 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); | |
2467 | return -EINVAL; | |
2468 | } | |
d8f60cfc AD |
2469 | /* don't enable anything if the ih is disabled */ |
2470 | if (!rdev->ih.enabled) | |
2471 | return 0; | |
2472 | ||
e0df1ac5 AD |
2473 | if (ASIC_IS_DCE3(rdev)) { |
2474 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2475 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2476 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2477 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2478 | if (ASIC_IS_DCE32(rdev)) { | |
2479 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2480 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2481 | } | |
2482 | } else { | |
2483 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2484 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2485 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
2486 | } | |
2487 | ||
d8f60cfc AD |
2488 | if (rdev->irq.sw_int) { |
2489 | DRM_DEBUG("r600_irq_set: sw int\n"); | |
2490 | cp_int_cntl |= RB_INT_ENABLE; | |
2491 | } | |
2492 | if (rdev->irq.crtc_vblank_int[0]) { | |
2493 | DRM_DEBUG("r600_irq_set: vblank 0\n"); | |
2494 | mode_int |= D1MODE_VBLANK_INT_MASK; | |
2495 | } | |
2496 | if (rdev->irq.crtc_vblank_int[1]) { | |
2497 | DRM_DEBUG("r600_irq_set: vblank 1\n"); | |
2498 | mode_int |= D2MODE_VBLANK_INT_MASK; | |
2499 | } | |
e0df1ac5 AD |
2500 | if (rdev->irq.hpd[0]) { |
2501 | DRM_DEBUG("r600_irq_set: hpd 1\n"); | |
2502 | hpd1 |= DC_HPDx_INT_EN; | |
2503 | } | |
2504 | if (rdev->irq.hpd[1]) { | |
2505 | DRM_DEBUG("r600_irq_set: hpd 2\n"); | |
2506 | hpd2 |= DC_HPDx_INT_EN; | |
2507 | } | |
2508 | if (rdev->irq.hpd[2]) { | |
2509 | DRM_DEBUG("r600_irq_set: hpd 3\n"); | |
2510 | hpd3 |= DC_HPDx_INT_EN; | |
2511 | } | |
2512 | if (rdev->irq.hpd[3]) { | |
2513 | DRM_DEBUG("r600_irq_set: hpd 4\n"); | |
2514 | hpd4 |= DC_HPDx_INT_EN; | |
2515 | } | |
2516 | if (rdev->irq.hpd[4]) { | |
2517 | DRM_DEBUG("r600_irq_set: hpd 5\n"); | |
2518 | hpd5 |= DC_HPDx_INT_EN; | |
2519 | } | |
2520 | if (rdev->irq.hpd[5]) { | |
2521 | DRM_DEBUG("r600_irq_set: hpd 6\n"); | |
2522 | hpd6 |= DC_HPDx_INT_EN; | |
2523 | } | |
d8f60cfc AD |
2524 | |
2525 | WREG32(CP_INT_CNTL, cp_int_cntl); | |
2526 | WREG32(DxMODE_INT_MASK, mode_int); | |
e0df1ac5 AD |
2527 | if (ASIC_IS_DCE3(rdev)) { |
2528 | WREG32(DC_HPD1_INT_CONTROL, hpd1); | |
2529 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | |
2530 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | |
2531 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | |
2532 | if (ASIC_IS_DCE32(rdev)) { | |
2533 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | |
2534 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | |
2535 | } | |
2536 | } else { | |
2537 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); | |
2538 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | |
2539 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); | |
2540 | } | |
d8f60cfc AD |
2541 | |
2542 | return 0; | |
2543 | } | |
2544 | ||
e0df1ac5 AD |
2545 | static inline void r600_irq_ack(struct radeon_device *rdev, |
2546 | u32 *disp_int, | |
2547 | u32 *disp_int_cont, | |
2548 | u32 *disp_int_cont2) | |
d8f60cfc | 2549 | { |
e0df1ac5 AD |
2550 | u32 tmp; |
2551 | ||
2552 | if (ASIC_IS_DCE3(rdev)) { | |
2553 | *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); | |
2554 | *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); | |
2555 | *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); | |
2556 | } else { | |
2557 | *disp_int = RREG32(DISP_INTERRUPT_STATUS); | |
2558 | *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | |
2559 | *disp_int_cont2 = 0; | |
2560 | } | |
d8f60cfc | 2561 | |
e0df1ac5 | 2562 | if (*disp_int & LB_D1_VBLANK_INTERRUPT) |
d8f60cfc | 2563 | WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
e0df1ac5 | 2564 | if (*disp_int & LB_D1_VLINE_INTERRUPT) |
d8f60cfc | 2565 | WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
e0df1ac5 | 2566 | if (*disp_int & LB_D2_VBLANK_INTERRUPT) |
d8f60cfc | 2567 | WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
e0df1ac5 | 2568 | if (*disp_int & LB_D2_VLINE_INTERRUPT) |
d8f60cfc | 2569 | WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
e0df1ac5 AD |
2570 | if (*disp_int & DC_HPD1_INTERRUPT) { |
2571 | if (ASIC_IS_DCE3(rdev)) { | |
2572 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
2573 | tmp |= DC_HPDx_INT_ACK; | |
2574 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
2575 | } else { | |
2576 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
2577 | tmp |= DC_HPDx_INT_ACK; | |
2578 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
2579 | } | |
2580 | } | |
2581 | if (*disp_int & DC_HPD2_INTERRUPT) { | |
2582 | if (ASIC_IS_DCE3(rdev)) { | |
2583 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
2584 | tmp |= DC_HPDx_INT_ACK; | |
2585 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
2586 | } else { | |
2587 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
2588 | tmp |= DC_HPDx_INT_ACK; | |
2589 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
2590 | } | |
2591 | } | |
2592 | if (*disp_int_cont & DC_HPD3_INTERRUPT) { | |
2593 | if (ASIC_IS_DCE3(rdev)) { | |
2594 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
2595 | tmp |= DC_HPDx_INT_ACK; | |
2596 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
2597 | } else { | |
2598 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
2599 | tmp |= DC_HPDx_INT_ACK; | |
2600 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
2601 | } | |
2602 | } | |
2603 | if (*disp_int_cont & DC_HPD4_INTERRUPT) { | |
2604 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
2605 | tmp |= DC_HPDx_INT_ACK; | |
2606 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
2607 | } | |
2608 | if (ASIC_IS_DCE32(rdev)) { | |
2609 | if (*disp_int_cont2 & DC_HPD5_INTERRUPT) { | |
2610 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
2611 | tmp |= DC_HPDx_INT_ACK; | |
2612 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
2613 | } | |
2614 | if (*disp_int_cont2 & DC_HPD6_INTERRUPT) { | |
2615 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
2616 | tmp |= DC_HPDx_INT_ACK; | |
2617 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
2618 | } | |
2619 | } | |
d8f60cfc AD |
2620 | } |
2621 | ||
2622 | void r600_irq_disable(struct radeon_device *rdev) | |
2623 | { | |
e0df1ac5 | 2624 | u32 disp_int, disp_int_cont, disp_int_cont2; |
d8f60cfc AD |
2625 | |
2626 | r600_disable_interrupts(rdev); | |
2627 | /* Wait and acknowledge irq */ | |
2628 | mdelay(1); | |
e0df1ac5 AD |
2629 | r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); |
2630 | r600_disable_interrupt_state(rdev); | |
d8f60cfc AD |
2631 | } |
2632 | ||
2633 | static inline u32 r600_get_ih_wptr(struct radeon_device *rdev) | |
2634 | { | |
2635 | u32 wptr, tmp; | |
3ce0a23d | 2636 | |
d8f60cfc AD |
2637 | /* XXX use writeback */ |
2638 | wptr = RREG32(IH_RB_WPTR); | |
3ce0a23d | 2639 | |
d8f60cfc AD |
2640 | if (wptr & RB_OVERFLOW) { |
2641 | WARN_ON(1); | |
2642 | /* XXX deal with overflow */ | |
2643 | DRM_ERROR("IH RB overflow\n"); | |
2644 | tmp = RREG32(IH_RB_CNTL); | |
2645 | tmp |= IH_WPTR_OVERFLOW_CLEAR; | |
2646 | WREG32(IH_RB_CNTL, tmp); | |
2647 | } | |
2648 | wptr = wptr & WPTR_OFFSET_MASK; | |
3ce0a23d | 2649 | |
d8f60cfc AD |
2650 | return wptr; |
2651 | } | |
3ce0a23d | 2652 | |
d8f60cfc AD |
2653 | /* r600 IV Ring |
2654 | * Each IV ring entry is 128 bits: | |
2655 | * [7:0] - interrupt source id | |
2656 | * [31:8] - reserved | |
2657 | * [59:32] - interrupt source data | |
2658 | * [127:60] - reserved | |
2659 | * | |
2660 | * The basic interrupt vector entries | |
2661 | * are decoded as follows: | |
2662 | * src_id src_data description | |
2663 | * 1 0 D1 Vblank | |
2664 | * 1 1 D1 Vline | |
2665 | * 5 0 D2 Vblank | |
2666 | * 5 1 D2 Vline | |
2667 | * 19 0 FP Hot plug detection A | |
2668 | * 19 1 FP Hot plug detection B | |
2669 | * 19 2 DAC A auto-detection | |
2670 | * 19 3 DAC B auto-detection | |
2671 | * 176 - CP_INT RB | |
2672 | * 177 - CP_INT IB1 | |
2673 | * 178 - CP_INT IB2 | |
2674 | * 181 - EOP Interrupt | |
2675 | * 233 - GUI Idle | |
2676 | * | |
2677 | * Note, these are based on r600 and may need to be | |
2678 | * adjusted or added to on newer asics | |
2679 | */ | |
2680 | ||
2681 | int r600_irq_process(struct radeon_device *rdev) | |
2682 | { | |
2683 | u32 wptr = r600_get_ih_wptr(rdev); | |
2684 | u32 rptr = rdev->ih.rptr; | |
2685 | u32 src_id, src_data; | |
2686 | u32 last_entry = rdev->ih.ring_size - 16; | |
e0df1ac5 | 2687 | u32 ring_index, disp_int, disp_int_cont, disp_int_cont2; |
d8f60cfc | 2688 | unsigned long flags; |
d4877cf2 | 2689 | bool queue_hotplug = false; |
d8f60cfc AD |
2690 | |
2691 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | |
2692 | ||
2693 | spin_lock_irqsave(&rdev->ih.lock, flags); | |
2694 | ||
2695 | if (rptr == wptr) { | |
2696 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
2697 | return IRQ_NONE; | |
2698 | } | |
2699 | if (rdev->shutdown) { | |
2700 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
2701 | return IRQ_NONE; | |
2702 | } | |
2703 | ||
2704 | restart_ih: | |
2705 | /* display interrupts */ | |
e0df1ac5 | 2706 | r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2); |
d8f60cfc AD |
2707 | |
2708 | rdev->ih.wptr = wptr; | |
2709 | while (rptr != wptr) { | |
2710 | /* wptr/rptr are in bytes! */ | |
2711 | ring_index = rptr / 4; | |
2712 | src_id = rdev->ih.ring[ring_index] & 0xff; | |
2713 | src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; | |
2714 | ||
2715 | switch (src_id) { | |
2716 | case 1: /* D1 vblank/vline */ | |
2717 | switch (src_data) { | |
2718 | case 0: /* D1 vblank */ | |
2719 | if (disp_int & LB_D1_VBLANK_INTERRUPT) { | |
2720 | drm_handle_vblank(rdev->ddev, 0); | |
2721 | disp_int &= ~LB_D1_VBLANK_INTERRUPT; | |
2722 | DRM_DEBUG("IH: D1 vblank\n"); | |
2723 | } | |
2724 | break; | |
2725 | case 1: /* D1 vline */ | |
2726 | if (disp_int & LB_D1_VLINE_INTERRUPT) { | |
2727 | disp_int &= ~LB_D1_VLINE_INTERRUPT; | |
2728 | DRM_DEBUG("IH: D1 vline\n"); | |
2729 | } | |
2730 | break; | |
2731 | default: | |
b042589c | 2732 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
2733 | break; |
2734 | } | |
2735 | break; | |
2736 | case 5: /* D2 vblank/vline */ | |
2737 | switch (src_data) { | |
2738 | case 0: /* D2 vblank */ | |
2739 | if (disp_int & LB_D2_VBLANK_INTERRUPT) { | |
2740 | drm_handle_vblank(rdev->ddev, 1); | |
2741 | disp_int &= ~LB_D2_VBLANK_INTERRUPT; | |
2742 | DRM_DEBUG("IH: D2 vblank\n"); | |
2743 | } | |
2744 | break; | |
2745 | case 1: /* D1 vline */ | |
2746 | if (disp_int & LB_D2_VLINE_INTERRUPT) { | |
2747 | disp_int &= ~LB_D2_VLINE_INTERRUPT; | |
2748 | DRM_DEBUG("IH: D2 vline\n"); | |
2749 | } | |
2750 | break; | |
2751 | default: | |
b042589c | 2752 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
2753 | break; |
2754 | } | |
2755 | break; | |
e0df1ac5 AD |
2756 | case 19: /* HPD/DAC hotplug */ |
2757 | switch (src_data) { | |
2758 | case 0: | |
2759 | if (disp_int & DC_HPD1_INTERRUPT) { | |
2760 | disp_int &= ~DC_HPD1_INTERRUPT; | |
d4877cf2 AD |
2761 | queue_hotplug = true; |
2762 | DRM_DEBUG("IH: HPD1\n"); | |
e0df1ac5 AD |
2763 | } |
2764 | break; | |
2765 | case 1: | |
2766 | if (disp_int & DC_HPD2_INTERRUPT) { | |
2767 | disp_int &= ~DC_HPD2_INTERRUPT; | |
d4877cf2 AD |
2768 | queue_hotplug = true; |
2769 | DRM_DEBUG("IH: HPD2\n"); | |
e0df1ac5 AD |
2770 | } |
2771 | break; | |
2772 | case 4: | |
2773 | if (disp_int_cont & DC_HPD3_INTERRUPT) { | |
2774 | disp_int_cont &= ~DC_HPD3_INTERRUPT; | |
d4877cf2 AD |
2775 | queue_hotplug = true; |
2776 | DRM_DEBUG("IH: HPD3\n"); | |
e0df1ac5 AD |
2777 | } |
2778 | break; | |
2779 | case 5: | |
2780 | if (disp_int_cont & DC_HPD4_INTERRUPT) { | |
2781 | disp_int_cont &= ~DC_HPD4_INTERRUPT; | |
d4877cf2 AD |
2782 | queue_hotplug = true; |
2783 | DRM_DEBUG("IH: HPD4\n"); | |
e0df1ac5 AD |
2784 | } |
2785 | break; | |
2786 | case 10: | |
2787 | if (disp_int_cont2 & DC_HPD5_INTERRUPT) { | |
2788 | disp_int_cont &= ~DC_HPD5_INTERRUPT; | |
d4877cf2 AD |
2789 | queue_hotplug = true; |
2790 | DRM_DEBUG("IH: HPD5\n"); | |
e0df1ac5 AD |
2791 | } |
2792 | break; | |
2793 | case 12: | |
2794 | if (disp_int_cont2 & DC_HPD6_INTERRUPT) { | |
2795 | disp_int_cont &= ~DC_HPD6_INTERRUPT; | |
d4877cf2 AD |
2796 | queue_hotplug = true; |
2797 | DRM_DEBUG("IH: HPD6\n"); | |
e0df1ac5 AD |
2798 | } |
2799 | break; | |
2800 | default: | |
b042589c | 2801 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
e0df1ac5 AD |
2802 | break; |
2803 | } | |
2804 | break; | |
d8f60cfc AD |
2805 | case 176: /* CP_INT in ring buffer */ |
2806 | case 177: /* CP_INT in IB1 */ | |
2807 | case 178: /* CP_INT in IB2 */ | |
2808 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); | |
2809 | radeon_fence_process(rdev); | |
2810 | break; | |
2811 | case 181: /* CP EOP event */ | |
2812 | DRM_DEBUG("IH: CP EOP\n"); | |
2813 | break; | |
2814 | default: | |
b042589c | 2815 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
2816 | break; |
2817 | } | |
2818 | ||
2819 | /* wptr/rptr are in bytes! */ | |
2820 | if (rptr == last_entry) | |
2821 | rptr = 0; | |
2822 | else | |
2823 | rptr += 16; | |
2824 | } | |
2825 | /* make sure wptr hasn't changed while processing */ | |
2826 | wptr = r600_get_ih_wptr(rdev); | |
2827 | if (wptr != rdev->ih.wptr) | |
2828 | goto restart_ih; | |
d4877cf2 AD |
2829 | if (queue_hotplug) |
2830 | queue_work(rdev->wq, &rdev->hotplug_work); | |
d8f60cfc AD |
2831 | rdev->ih.rptr = rptr; |
2832 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | |
2833 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | |
2834 | return IRQ_HANDLED; | |
2835 | } | |
3ce0a23d JG |
2836 | |
2837 | /* | |
2838 | * Debugfs info | |
2839 | */ | |
2840 | #if defined(CONFIG_DEBUG_FS) | |
2841 | ||
2842 | static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data) | |
771fe6b9 | 2843 | { |
3ce0a23d JG |
2844 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
2845 | struct drm_device *dev = node->minor->dev; | |
2846 | struct radeon_device *rdev = dev->dev_private; | |
3ce0a23d JG |
2847 | unsigned count, i, j; |
2848 | ||
2849 | radeon_ring_free_size(rdev); | |
d6840766 | 2850 | count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw; |
3ce0a23d | 2851 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); |
d6840766 RM |
2852 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); |
2853 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); | |
2854 | seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr); | |
2855 | seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr); | |
3ce0a23d JG |
2856 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); |
2857 | seq_printf(m, "%u dwords in ring\n", count); | |
d6840766 | 2858 | i = rdev->cp.rptr; |
3ce0a23d | 2859 | for (j = 0; j <= count; j++) { |
3ce0a23d | 2860 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); |
d6840766 | 2861 | i = (i + 1) & rdev->cp.ptr_mask; |
3ce0a23d JG |
2862 | } |
2863 | return 0; | |
2864 | } | |
2865 | ||
2866 | static int r600_debugfs_mc_info(struct seq_file *m, void *data) | |
2867 | { | |
2868 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2869 | struct drm_device *dev = node->minor->dev; | |
2870 | struct radeon_device *rdev = dev->dev_private; | |
2871 | ||
2872 | DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); | |
2873 | DREG32_SYS(m, rdev, VM_L2_STATUS); | |
2874 | return 0; | |
2875 | } | |
2876 | ||
2877 | static struct drm_info_list r600_mc_info_list[] = { | |
2878 | {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, | |
2879 | {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL}, | |
2880 | }; | |
2881 | #endif | |
2882 | ||
2883 | int r600_debugfs_mc_info_init(struct radeon_device *rdev) | |
2884 | { | |
2885 | #if defined(CONFIG_DEBUG_FS) | |
2886 | return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); | |
2887 | #else | |
2888 | return 0; | |
2889 | #endif | |
771fe6b9 | 2890 | } |