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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
5a0e3ad6 | 28 | #include <linux/slab.h> |
3ce0a23d JG |
29 | #include <linux/seq_file.h> |
30 | #include <linux/firmware.h> | |
e0cd3608 | 31 | #include <linux/module.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/radeon_drm.h> | |
771fe6b9 | 34 | #include "radeon.h" |
e6990375 | 35 | #include "radeon_asic.h" |
bfc1f97d | 36 | #include "radeon_audio.h" |
3ce0a23d | 37 | #include "radeon_mode.h" |
3ce0a23d | 38 | #include "r600d.h" |
3ce0a23d | 39 | #include "atom.h" |
d39c3b89 | 40 | #include "avivod.h" |
138e4e16 | 41 | #include "radeon_ucode.h" |
3ce0a23d JG |
42 | |
43 | /* Firmware Names */ | |
44 | MODULE_FIRMWARE("radeon/R600_pfp.bin"); | |
45 | MODULE_FIRMWARE("radeon/R600_me.bin"); | |
46 | MODULE_FIRMWARE("radeon/RV610_pfp.bin"); | |
47 | MODULE_FIRMWARE("radeon/RV610_me.bin"); | |
48 | MODULE_FIRMWARE("radeon/RV630_pfp.bin"); | |
49 | MODULE_FIRMWARE("radeon/RV630_me.bin"); | |
50 | MODULE_FIRMWARE("radeon/RV620_pfp.bin"); | |
51 | MODULE_FIRMWARE("radeon/RV620_me.bin"); | |
52 | MODULE_FIRMWARE("radeon/RV635_pfp.bin"); | |
53 | MODULE_FIRMWARE("radeon/RV635_me.bin"); | |
54 | MODULE_FIRMWARE("radeon/RV670_pfp.bin"); | |
55 | MODULE_FIRMWARE("radeon/RV670_me.bin"); | |
56 | MODULE_FIRMWARE("radeon/RS780_pfp.bin"); | |
57 | MODULE_FIRMWARE("radeon/RS780_me.bin"); | |
58 | MODULE_FIRMWARE("radeon/RV770_pfp.bin"); | |
59 | MODULE_FIRMWARE("radeon/RV770_me.bin"); | |
66229b20 | 60 | MODULE_FIRMWARE("radeon/RV770_smc.bin"); |
3ce0a23d JG |
61 | MODULE_FIRMWARE("radeon/RV730_pfp.bin"); |
62 | MODULE_FIRMWARE("radeon/RV730_me.bin"); | |
66229b20 AD |
63 | MODULE_FIRMWARE("radeon/RV730_smc.bin"); |
64 | MODULE_FIRMWARE("radeon/RV740_smc.bin"); | |
3ce0a23d JG |
65 | MODULE_FIRMWARE("radeon/RV710_pfp.bin"); |
66 | MODULE_FIRMWARE("radeon/RV710_me.bin"); | |
66229b20 | 67 | MODULE_FIRMWARE("radeon/RV710_smc.bin"); |
d8f60cfc AD |
68 | MODULE_FIRMWARE("radeon/R600_rlc.bin"); |
69 | MODULE_FIRMWARE("radeon/R700_rlc.bin"); | |
fe251e2f AD |
70 | MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); |
71 | MODULE_FIRMWARE("radeon/CEDAR_me.bin"); | |
45f9a39b | 72 | MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); |
dc50ba7f | 73 | MODULE_FIRMWARE("radeon/CEDAR_smc.bin"); |
fe251e2f AD |
74 | MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); |
75 | MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); | |
45f9a39b | 76 | MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); |
dc50ba7f | 77 | MODULE_FIRMWARE("radeon/REDWOOD_smc.bin"); |
fe251e2f AD |
78 | MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); |
79 | MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); | |
45f9a39b | 80 | MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); |
dc50ba7f | 81 | MODULE_FIRMWARE("radeon/JUNIPER_smc.bin"); |
a7433742 | 82 | MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); |
fe251e2f | 83 | MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); |
45f9a39b | 84 | MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); |
dc50ba7f | 85 | MODULE_FIRMWARE("radeon/CYPRESS_smc.bin"); |
439bd6cd AD |
86 | MODULE_FIRMWARE("radeon/PALM_pfp.bin"); |
87 | MODULE_FIRMWARE("radeon/PALM_me.bin"); | |
88 | MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); | |
d5c5a72f AD |
89 | MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); |
90 | MODULE_FIRMWARE("radeon/SUMO_me.bin"); | |
91 | MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); | |
92 | MODULE_FIRMWARE("radeon/SUMO2_me.bin"); | |
3ce0a23d | 93 | |
f13f7731 AD |
94 | static const u32 crtc_offsets[2] = |
95 | { | |
96 | 0, | |
97 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL | |
98 | }; | |
99 | ||
3ce0a23d | 100 | int r600_debugfs_mc_info_init(struct radeon_device *rdev); |
771fe6b9 | 101 | |
1a029b76 | 102 | /* r600,rv610,rv630,rv620,rv635,rv670 */ |
771fe6b9 | 103 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
1109ca09 | 104 | static void r600_gpu_init(struct radeon_device *rdev); |
3ce0a23d | 105 | void r600_fini(struct radeon_device *rdev); |
45f9a39b | 106 | void r600_irq_disable(struct radeon_device *rdev); |
9e46a48d | 107 | static void r600_pcie_gen2_enable(struct radeon_device *rdev); |
2948f5e6 | 108 | extern int evergreen_rlc_resume(struct radeon_device *rdev); |
de9ae744 | 109 | extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev); |
771fe6b9 | 110 | |
9e5acbc2 DV |
111 | /* |
112 | * Indirect registers accessor | |
113 | */ | |
114 | u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) | |
115 | { | |
116 | unsigned long flags; | |
117 | u32 r; | |
118 | ||
119 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); | |
120 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); | |
121 | r = RREG32(R600_RCU_DATA); | |
122 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); | |
123 | return r; | |
124 | } | |
125 | ||
126 | void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
127 | { | |
128 | unsigned long flags; | |
129 | ||
130 | spin_lock_irqsave(&rdev->rcu_idx_lock, flags); | |
131 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); | |
132 | WREG32(R600_RCU_DATA, (v)); | |
133 | spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); | |
134 | } | |
135 | ||
136 | u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) | |
137 | { | |
138 | unsigned long flags; | |
139 | u32 r; | |
140 | ||
141 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); | |
142 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); | |
143 | r = RREG32(R600_UVD_CTX_DATA); | |
144 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); | |
145 | return r; | |
146 | } | |
147 | ||
148 | void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
149 | { | |
150 | unsigned long flags; | |
151 | ||
152 | spin_lock_irqsave(&rdev->uvd_idx_lock, flags); | |
153 | WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); | |
154 | WREG32(R600_UVD_CTX_DATA, (v)); | |
155 | spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); | |
156 | } | |
157 | ||
c6d2ac2c AD |
158 | /** |
159 | * r600_get_allowed_info_register - fetch the register for the info ioctl | |
160 | * | |
161 | * @rdev: radeon_device pointer | |
162 | * @reg: register offset in bytes | |
163 | * @val: register value | |
164 | * | |
165 | * Returns 0 for success or -EINVAL for an invalid register | |
166 | * | |
167 | */ | |
168 | int r600_get_allowed_info_register(struct radeon_device *rdev, | |
169 | u32 reg, u32 *val) | |
170 | { | |
171 | switch (reg) { | |
172 | case GRBM_STATUS: | |
173 | case GRBM_STATUS2: | |
174 | case R_000E50_SRBM_STATUS: | |
175 | case DMA_STATUS_REG: | |
176 | case UVD_STATUS: | |
177 | *val = RREG32(reg); | |
178 | return 0; | |
179 | default: | |
180 | return -EINVAL; | |
181 | } | |
182 | } | |
183 | ||
454d2e2a AD |
184 | /** |
185 | * r600_get_xclk - get the xclk | |
186 | * | |
187 | * @rdev: radeon_device pointer | |
188 | * | |
189 | * Returns the reference clock used by the gfx engine | |
190 | * (r6xx, IGPs, APUs). | |
191 | */ | |
192 | u32 r600_get_xclk(struct radeon_device *rdev) | |
193 | { | |
194 | return rdev->clock.spll.reference_freq; | |
195 | } | |
196 | ||
1b9ba70a AD |
197 | int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) |
198 | { | |
4a956a70 AD |
199 | unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; |
200 | int r; | |
201 | ||
202 | /* bypass vclk and dclk with bclk */ | |
203 | WREG32_P(CG_UPLL_FUNC_CNTL_2, | |
204 | VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), | |
205 | ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); | |
206 | ||
207 | /* assert BYPASS_EN, deassert UPLL_RESET, UPLL_SLEEP and UPLL_CTLREQ */ | |
208 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( | |
209 | UPLL_RESET_MASK | UPLL_SLEEP_MASK | UPLL_CTLREQ_MASK)); | |
210 | ||
211 | if (rdev->family >= CHIP_RS780) | |
212 | WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, | |
213 | ~UPLL_BYPASS_CNTL); | |
214 | ||
215 | if (!vclk || !dclk) { | |
216 | /* keep the Bypass mode, put PLL to sleep */ | |
217 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); | |
218 | return 0; | |
219 | } | |
220 | ||
221 | if (rdev->clock.spll.reference_freq == 10000) | |
222 | ref_div = 34; | |
223 | else | |
224 | ref_div = 4; | |
225 | ||
226 | r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, | |
227 | ref_div + 1, 0xFFF, 2, 30, ~0, | |
228 | &fb_div, &vclk_div, &dclk_div); | |
229 | if (r) | |
230 | return r; | |
231 | ||
232 | if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) | |
233 | fb_div >>= 1; | |
234 | else | |
235 | fb_div |= 1; | |
236 | ||
237 | r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); | |
3cf8bb1a JG |
238 | if (r) |
239 | return r; | |
4a956a70 AD |
240 | |
241 | /* assert PLL_RESET */ | |
242 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); | |
243 | ||
244 | /* For RS780 we have to choose ref clk */ | |
245 | if (rdev->family >= CHIP_RS780) | |
246 | WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, | |
247 | ~UPLL_REFCLK_SRC_SEL_MASK); | |
248 | ||
249 | /* set the required fb, ref and post divder values */ | |
250 | WREG32_P(CG_UPLL_FUNC_CNTL, | |
251 | UPLL_FB_DIV(fb_div) | | |
252 | UPLL_REF_DIV(ref_div), | |
253 | ~(UPLL_FB_DIV_MASK | UPLL_REF_DIV_MASK)); | |
254 | WREG32_P(CG_UPLL_FUNC_CNTL_2, | |
255 | UPLL_SW_HILEN(vclk_div >> 1) | | |
256 | UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | | |
257 | UPLL_SW_HILEN2(dclk_div >> 1) | | |
258 | UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)) | | |
259 | UPLL_DIVEN_MASK | UPLL_DIVEN2_MASK, | |
260 | ~UPLL_SW_MASK); | |
261 | ||
262 | /* give the PLL some time to settle */ | |
263 | mdelay(15); | |
264 | ||
265 | /* deassert PLL_RESET */ | |
266 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); | |
267 | ||
268 | mdelay(15); | |
269 | ||
270 | /* deassert BYPASS EN */ | |
271 | WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); | |
272 | ||
273 | if (rdev->family >= CHIP_RS780) | |
274 | WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~UPLL_BYPASS_CNTL); | |
275 | ||
276 | r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); | |
277 | if (r) | |
278 | return r; | |
279 | ||
280 | /* switch VCLK and DCLK selection */ | |
281 | WREG32_P(CG_UPLL_FUNC_CNTL_2, | |
282 | VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), | |
283 | ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); | |
284 | ||
285 | mdelay(100); | |
286 | ||
1b9ba70a AD |
287 | return 0; |
288 | } | |
289 | ||
134b480f AD |
290 | void dce3_program_fmt(struct drm_encoder *encoder) |
291 | { | |
292 | struct drm_device *dev = encoder->dev; | |
293 | struct radeon_device *rdev = dev->dev_private; | |
294 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
295 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); | |
296 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | |
297 | int bpc = 0; | |
298 | u32 tmp = 0; | |
6214bb74 | 299 | enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; |
134b480f | 300 | |
6214bb74 AD |
301 | if (connector) { |
302 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
134b480f | 303 | bpc = radeon_get_monitor_bpc(connector); |
6214bb74 AD |
304 | dither = radeon_connector->dither; |
305 | } | |
134b480f AD |
306 | |
307 | /* LVDS FMT is set up by atom */ | |
308 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) | |
309 | return; | |
310 | ||
311 | /* not needed for analog */ | |
312 | if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || | |
313 | (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) | |
314 | return; | |
315 | ||
316 | if (bpc == 0) | |
317 | return; | |
318 | ||
319 | switch (bpc) { | |
320 | case 6: | |
6214bb74 | 321 | if (dither == RADEON_FMT_DITHER_ENABLE) |
134b480f AD |
322 | /* XXX sort out optimal dither settings */ |
323 | tmp |= FMT_SPATIAL_DITHER_EN; | |
324 | else | |
325 | tmp |= FMT_TRUNCATE_EN; | |
326 | break; | |
327 | case 8: | |
6214bb74 | 328 | if (dither == RADEON_FMT_DITHER_ENABLE) |
134b480f AD |
329 | /* XXX sort out optimal dither settings */ |
330 | tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); | |
331 | else | |
332 | tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); | |
333 | break; | |
334 | case 10: | |
335 | default: | |
336 | /* not needed */ | |
337 | break; | |
338 | } | |
339 | ||
340 | WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); | |
341 | } | |
342 | ||
21a8122a | 343 | /* get temperature in millidegrees */ |
20d391d7 | 344 | int rv6xx_get_temp(struct radeon_device *rdev) |
21a8122a AD |
345 | { |
346 | u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> | |
347 | ASIC_T_SHIFT; | |
20d391d7 | 348 | int actual_temp = temp & 0xff; |
21a8122a | 349 | |
20d391d7 AD |
350 | if (temp & 0x100) |
351 | actual_temp -= 256; | |
352 | ||
353 | return actual_temp * 1000; | |
21a8122a AD |
354 | } |
355 | ||
ce8f5370 | 356 | void r600_pm_get_dynpm_state(struct radeon_device *rdev) |
a48b9b4e AD |
357 | { |
358 | int i; | |
359 | ||
ce8f5370 AD |
360 | rdev->pm.dynpm_can_upclock = true; |
361 | rdev->pm.dynpm_can_downclock = true; | |
a48b9b4e AD |
362 | |
363 | /* power state array is low to high, default is first */ | |
364 | if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { | |
365 | int min_power_state_index = 0; | |
366 | ||
367 | if (rdev->pm.num_power_states > 2) | |
368 | min_power_state_index = 1; | |
369 | ||
ce8f5370 AD |
370 | switch (rdev->pm.dynpm_planned_action) { |
371 | case DYNPM_ACTION_MINIMUM: | |
a48b9b4e AD |
372 | rdev->pm.requested_power_state_index = min_power_state_index; |
373 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 374 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 375 | break; |
ce8f5370 | 376 | case DYNPM_ACTION_DOWNCLOCK: |
a48b9b4e AD |
377 | if (rdev->pm.current_power_state_index == min_power_state_index) { |
378 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 379 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e AD |
380 | } else { |
381 | if (rdev->pm.active_crtc_count > 1) { | |
382 | for (i = 0; i < rdev->pm.num_power_states; i++) { | |
d7311171 | 383 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
384 | continue; |
385 | else if (i >= rdev->pm.current_power_state_index) { | |
386 | rdev->pm.requested_power_state_index = | |
387 | rdev->pm.current_power_state_index; | |
388 | break; | |
389 | } else { | |
390 | rdev->pm.requested_power_state_index = i; | |
391 | break; | |
392 | } | |
393 | } | |
773c3fa3 AD |
394 | } else { |
395 | if (rdev->pm.current_power_state_index == 0) | |
396 | rdev->pm.requested_power_state_index = | |
397 | rdev->pm.num_power_states - 1; | |
398 | else | |
399 | rdev->pm.requested_power_state_index = | |
400 | rdev->pm.current_power_state_index - 1; | |
401 | } | |
a48b9b4e AD |
402 | } |
403 | rdev->pm.requested_clock_mode_index = 0; | |
d7311171 AD |
404 | /* don't use the power state if crtcs are active and no display flag is set */ |
405 | if ((rdev->pm.active_crtc_count > 0) && | |
406 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
407 | clock_info[rdev->pm.requested_clock_mode_index].flags & | |
408 | RADEON_PM_MODE_NO_DISPLAY)) { | |
409 | rdev->pm.requested_power_state_index++; | |
410 | } | |
a48b9b4e | 411 | break; |
ce8f5370 | 412 | case DYNPM_ACTION_UPCLOCK: |
a48b9b4e AD |
413 | if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { |
414 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 415 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
416 | } else { |
417 | if (rdev->pm.active_crtc_count > 1) { | |
418 | for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { | |
d7311171 | 419 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
420 | continue; |
421 | else if (i <= rdev->pm.current_power_state_index) { | |
422 | rdev->pm.requested_power_state_index = | |
423 | rdev->pm.current_power_state_index; | |
424 | break; | |
425 | } else { | |
426 | rdev->pm.requested_power_state_index = i; | |
427 | break; | |
428 | } | |
429 | } | |
430 | } else | |
431 | rdev->pm.requested_power_state_index = | |
432 | rdev->pm.current_power_state_index + 1; | |
433 | } | |
434 | rdev->pm.requested_clock_mode_index = 0; | |
435 | break; | |
ce8f5370 | 436 | case DYNPM_ACTION_DEFAULT: |
58e21dff AD |
437 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
438 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 439 | rdev->pm.dynpm_can_upclock = false; |
58e21dff | 440 | break; |
ce8f5370 | 441 | case DYNPM_ACTION_NONE: |
a48b9b4e AD |
442 | default: |
443 | DRM_ERROR("Requested mode for not defined action\n"); | |
444 | return; | |
445 | } | |
446 | } else { | |
447 | /* XXX select a power state based on AC/DC, single/dualhead, etc. */ | |
448 | /* for now just select the first power state and switch between clock modes */ | |
449 | /* power state array is low to high, default is first (0) */ | |
450 | if (rdev->pm.active_crtc_count > 1) { | |
451 | rdev->pm.requested_power_state_index = -1; | |
452 | /* start at 1 as we don't want the default mode */ | |
453 | for (i = 1; i < rdev->pm.num_power_states; i++) { | |
d7311171 | 454 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
455 | continue; |
456 | else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || | |
457 | (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { | |
458 | rdev->pm.requested_power_state_index = i; | |
459 | break; | |
460 | } | |
461 | } | |
462 | /* if nothing selected, grab the default state. */ | |
463 | if (rdev->pm.requested_power_state_index == -1) | |
464 | rdev->pm.requested_power_state_index = 0; | |
465 | } else | |
466 | rdev->pm.requested_power_state_index = 1; | |
467 | ||
ce8f5370 AD |
468 | switch (rdev->pm.dynpm_planned_action) { |
469 | case DYNPM_ACTION_MINIMUM: | |
a48b9b4e | 470 | rdev->pm.requested_clock_mode_index = 0; |
ce8f5370 | 471 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 472 | break; |
ce8f5370 | 473 | case DYNPM_ACTION_DOWNCLOCK: |
a48b9b4e AD |
474 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
475 | if (rdev->pm.current_clock_mode_index == 0) { | |
476 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 477 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e AD |
478 | } else |
479 | rdev->pm.requested_clock_mode_index = | |
480 | rdev->pm.current_clock_mode_index - 1; | |
481 | } else { | |
482 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 483 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 484 | } |
d7311171 AD |
485 | /* don't use the power state if crtcs are active and no display flag is set */ |
486 | if ((rdev->pm.active_crtc_count > 0) && | |
487 | (rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
488 | clock_info[rdev->pm.requested_clock_mode_index].flags & | |
489 | RADEON_PM_MODE_NO_DISPLAY)) { | |
490 | rdev->pm.requested_clock_mode_index++; | |
491 | } | |
a48b9b4e | 492 | break; |
ce8f5370 | 493 | case DYNPM_ACTION_UPCLOCK: |
a48b9b4e AD |
494 | if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { |
495 | if (rdev->pm.current_clock_mode_index == | |
496 | (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { | |
497 | rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; | |
ce8f5370 | 498 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
499 | } else |
500 | rdev->pm.requested_clock_mode_index = | |
501 | rdev->pm.current_clock_mode_index + 1; | |
502 | } else { | |
503 | rdev->pm.requested_clock_mode_index = | |
504 | rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; | |
ce8f5370 | 505 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
506 | } |
507 | break; | |
ce8f5370 | 508 | case DYNPM_ACTION_DEFAULT: |
58e21dff AD |
509 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
510 | rdev->pm.requested_clock_mode_index = 0; | |
ce8f5370 | 511 | rdev->pm.dynpm_can_upclock = false; |
58e21dff | 512 | break; |
ce8f5370 | 513 | case DYNPM_ACTION_NONE: |
a48b9b4e AD |
514 | default: |
515 | DRM_ERROR("Requested mode for not defined action\n"); | |
516 | return; | |
517 | } | |
518 | } | |
519 | ||
d9fdaafb | 520 | DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", |
ce8a3eb2 AD |
521 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. |
522 | clock_info[rdev->pm.requested_clock_mode_index].sclk, | |
523 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
524 | clock_info[rdev->pm.requested_clock_mode_index].mclk, | |
525 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
526 | pcie_lanes); | |
a48b9b4e AD |
527 | } |
528 | ||
ce8f5370 AD |
529 | void rs780_pm_init_profile(struct radeon_device *rdev) |
530 | { | |
531 | if (rdev->pm.num_power_states == 2) { | |
532 | /* default */ | |
533 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
534 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
535 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
536 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
537 | /* low sh */ | |
538 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; | |
539 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; | |
540 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
541 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
542 | /* mid sh */ |
543 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; | |
544 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; | |
545 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
546 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
547 | /* high sh */ |
548 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; | |
549 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; | |
550 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
551 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
552 | /* low mh */ | |
553 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; | |
554 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; | |
555 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
556 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
557 | /* mid mh */ |
558 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; | |
559 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; | |
560 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
561 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
562 | /* high mh */ |
563 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; | |
564 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; | |
565 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
566 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
567 | } else if (rdev->pm.num_power_states == 3) { | |
568 | /* default */ | |
569 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
570 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
571 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
572 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
573 | /* low sh */ | |
574 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; | |
575 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; | |
576 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
577 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
578 | /* mid sh */ |
579 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; | |
580 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; | |
581 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
582 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
583 | /* high sh */ |
584 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; | |
585 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; | |
586 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
587 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
588 | /* low mh */ | |
589 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; | |
590 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; | |
591 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
592 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
593 | /* mid mh */ |
594 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; | |
595 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; | |
596 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
597 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
598 | /* high mh */ |
599 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; | |
600 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; | |
601 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
602 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
603 | } else { | |
604 | /* default */ | |
605 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
606 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
607 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
608 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
609 | /* low sh */ | |
610 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; | |
611 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; | |
612 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
613 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
614 | /* mid sh */ |
615 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; | |
616 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; | |
617 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
618 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
619 | /* high sh */ |
620 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; | |
621 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; | |
622 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
623 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
624 | /* low mh */ | |
625 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; | |
626 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; | |
627 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
628 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 AD |
629 | /* mid mh */ |
630 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; | |
631 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; | |
632 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
633 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
634 | /* high mh */ |
635 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; | |
636 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; | |
637 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
638 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
639 | } | |
640 | } | |
bae6b562 | 641 | |
ce8f5370 AD |
642 | void r600_pm_init_profile(struct radeon_device *rdev) |
643 | { | |
bbe26ffe AD |
644 | int idx; |
645 | ||
ce8f5370 AD |
646 | if (rdev->family == CHIP_R600) { |
647 | /* XXX */ | |
648 | /* default */ | |
649 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
650 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
651 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 652 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
653 | /* low sh */ |
654 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
655 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
656 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 657 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
c9e75b21 AD |
658 | /* mid sh */ |
659 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
660 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
661 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
662 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
663 | /* high sh */ |
664 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
665 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
666 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 667 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
668 | /* low mh */ |
669 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
670 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
671 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 672 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
c9e75b21 AD |
673 | /* mid mh */ |
674 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
675 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
676 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
677 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; | |
ce8f5370 AD |
678 | /* high mh */ |
679 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
680 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
681 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
4bff5171 | 682 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; |
ce8f5370 AD |
683 | } else { |
684 | if (rdev->pm.num_power_states < 4) { | |
685 | /* default */ | |
686 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
687 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
688 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
689 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; | |
690 | /* low sh */ | |
4bff5171 AD |
691 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; |
692 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; | |
ce8f5370 | 693 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; |
c9e75b21 AD |
694 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; |
695 | /* mid sh */ | |
696 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; | |
697 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; | |
698 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
699 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 700 | /* high sh */ |
4bff5171 AD |
701 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; |
702 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; | |
ce8f5370 AD |
703 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
704 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; | |
705 | /* low mh */ | |
4bff5171 AD |
706 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; |
707 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; | |
ce8f5370 | 708 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; |
c9e75b21 AD |
709 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; |
710 | /* low mh */ | |
711 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; | |
712 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; | |
713 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
714 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 715 | /* high mh */ |
4bff5171 AD |
716 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; |
717 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; | |
ce8f5370 AD |
718 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
719 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; | |
720 | } else { | |
721 | /* default */ | |
722 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
723 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
724 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
725 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; | |
726 | /* low sh */ | |
bbe26ffe AD |
727 | if (rdev->flags & RADEON_IS_MOBILITY) |
728 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); | |
729 | else | |
730 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); | |
731 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; | |
732 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; | |
733 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
734 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 | 735 | /* mid sh */ |
bbe26ffe AD |
736 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; |
737 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; | |
738 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; | |
739 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 740 | /* high sh */ |
bbe26ffe AD |
741 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); |
742 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; | |
743 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; | |
ce8f5370 AD |
744 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; |
745 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; | |
746 | /* low mh */ | |
bbe26ffe AD |
747 | if (rdev->flags & RADEON_IS_MOBILITY) |
748 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); | |
749 | else | |
750 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); | |
751 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; | |
752 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; | |
753 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
754 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
c9e75b21 | 755 | /* mid mh */ |
bbe26ffe AD |
756 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; |
757 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; | |
758 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; | |
759 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; | |
ce8f5370 | 760 | /* high mh */ |
bbe26ffe AD |
761 | idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); |
762 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; | |
763 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; | |
ce8f5370 AD |
764 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; |
765 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; | |
766 | } | |
767 | } | |
bae6b562 AD |
768 | } |
769 | ||
49e02b73 AD |
770 | void r600_pm_misc(struct radeon_device *rdev) |
771 | { | |
a081a9d6 RM |
772 | int req_ps_idx = rdev->pm.requested_power_state_index; |
773 | int req_cm_idx = rdev->pm.requested_clock_mode_index; | |
774 | struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; | |
775 | struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; | |
7ac9aa5a | 776 | |
4d60173f | 777 | if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
a377e187 AD |
778 | /* 0xff01 is a flag rather then an actual voltage */ |
779 | if (voltage->voltage == 0xff01) | |
780 | return; | |
4d60173f | 781 | if (voltage->voltage != rdev->pm.current_vddc) { |
8a83ec5e | 782 | radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
4d60173f | 783 | rdev->pm.current_vddc = voltage->voltage; |
d9fdaafb | 784 | DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); |
4d60173f AD |
785 | } |
786 | } | |
49e02b73 AD |
787 | } |
788 | ||
def9ba9c AD |
789 | bool r600_gui_idle(struct radeon_device *rdev) |
790 | { | |
791 | if (RREG32(GRBM_STATUS) & GUI_ACTIVE) | |
792 | return false; | |
793 | else | |
794 | return true; | |
795 | } | |
796 | ||
e0df1ac5 AD |
797 | /* hpd for digital panel detect/disconnect */ |
798 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
799 | { | |
800 | bool connected = false; | |
801 | ||
802 | if (ASIC_IS_DCE3(rdev)) { | |
803 | switch (hpd) { | |
804 | case RADEON_HPD_1: | |
805 | if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) | |
806 | connected = true; | |
807 | break; | |
808 | case RADEON_HPD_2: | |
809 | if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) | |
810 | connected = true; | |
811 | break; | |
812 | case RADEON_HPD_3: | |
813 | if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) | |
814 | connected = true; | |
815 | break; | |
816 | case RADEON_HPD_4: | |
817 | if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) | |
818 | connected = true; | |
819 | break; | |
820 | /* DCE 3.2 */ | |
821 | case RADEON_HPD_5: | |
822 | if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) | |
823 | connected = true; | |
824 | break; | |
825 | case RADEON_HPD_6: | |
826 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) | |
827 | connected = true; | |
828 | break; | |
829 | default: | |
830 | break; | |
831 | } | |
832 | } else { | |
833 | switch (hpd) { | |
834 | case RADEON_HPD_1: | |
835 | if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
836 | connected = true; | |
837 | break; | |
838 | case RADEON_HPD_2: | |
839 | if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
840 | connected = true; | |
841 | break; | |
842 | case RADEON_HPD_3: | |
843 | if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) | |
844 | connected = true; | |
845 | break; | |
846 | default: | |
847 | break; | |
848 | } | |
849 | } | |
850 | return connected; | |
851 | } | |
852 | ||
853 | void r600_hpd_set_polarity(struct radeon_device *rdev, | |
429770b3 | 854 | enum radeon_hpd_id hpd) |
e0df1ac5 AD |
855 | { |
856 | u32 tmp; | |
857 | bool connected = r600_hpd_sense(rdev, hpd); | |
858 | ||
859 | if (ASIC_IS_DCE3(rdev)) { | |
860 | switch (hpd) { | |
861 | case RADEON_HPD_1: | |
862 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
863 | if (connected) | |
864 | tmp &= ~DC_HPDx_INT_POLARITY; | |
865 | else | |
866 | tmp |= DC_HPDx_INT_POLARITY; | |
867 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
868 | break; | |
869 | case RADEON_HPD_2: | |
870 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
871 | if (connected) | |
872 | tmp &= ~DC_HPDx_INT_POLARITY; | |
873 | else | |
874 | tmp |= DC_HPDx_INT_POLARITY; | |
875 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
876 | break; | |
877 | case RADEON_HPD_3: | |
878 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
879 | if (connected) | |
880 | tmp &= ~DC_HPDx_INT_POLARITY; | |
881 | else | |
882 | tmp |= DC_HPDx_INT_POLARITY; | |
883 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
884 | break; | |
885 | case RADEON_HPD_4: | |
886 | tmp = RREG32(DC_HPD4_INT_CONTROL); | |
887 | if (connected) | |
888 | tmp &= ~DC_HPDx_INT_POLARITY; | |
889 | else | |
890 | tmp |= DC_HPDx_INT_POLARITY; | |
891 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
892 | break; | |
893 | case RADEON_HPD_5: | |
894 | tmp = RREG32(DC_HPD5_INT_CONTROL); | |
895 | if (connected) | |
896 | tmp &= ~DC_HPDx_INT_POLARITY; | |
897 | else | |
898 | tmp |= DC_HPDx_INT_POLARITY; | |
899 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
900 | break; | |
901 | /* DCE 3.2 */ | |
902 | case RADEON_HPD_6: | |
903 | tmp = RREG32(DC_HPD6_INT_CONTROL); | |
904 | if (connected) | |
905 | tmp &= ~DC_HPDx_INT_POLARITY; | |
906 | else | |
907 | tmp |= DC_HPDx_INT_POLARITY; | |
908 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
909 | break; | |
910 | default: | |
911 | break; | |
912 | } | |
913 | } else { | |
914 | switch (hpd) { | |
915 | case RADEON_HPD_1: | |
916 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
917 | if (connected) | |
918 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
919 | else | |
920 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
921 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
922 | break; | |
923 | case RADEON_HPD_2: | |
924 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
925 | if (connected) | |
926 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
927 | else | |
928 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
929 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
930 | break; | |
931 | case RADEON_HPD_3: | |
932 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
933 | if (connected) | |
934 | tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
935 | else | |
936 | tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
937 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
938 | break; | |
939 | default: | |
940 | break; | |
941 | } | |
942 | } | |
943 | } | |
944 | ||
945 | void r600_hpd_init(struct radeon_device *rdev) | |
946 | { | |
947 | struct drm_device *dev = rdev->ddev; | |
948 | struct drm_connector *connector; | |
fb98257a | 949 | unsigned enable = 0; |
e0df1ac5 | 950 | |
64912e99 AD |
951 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
952 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
953 | ||
455c89b9 JG |
954 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || |
955 | connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { | |
956 | /* don't try to enable hpd on eDP or LVDS avoid breaking the | |
957 | * aux dp channel on imac and help (but not completely fix) | |
958 | * https://bugzilla.redhat.com/show_bug.cgi?id=726143 | |
959 | */ | |
960 | continue; | |
961 | } | |
64912e99 AD |
962 | if (ASIC_IS_DCE3(rdev)) { |
963 | u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); | |
964 | if (ASIC_IS_DCE32(rdev)) | |
965 | tmp |= DC_HPDx_EN; | |
e0df1ac5 | 966 | |
e0df1ac5 AD |
967 | switch (radeon_connector->hpd.hpd) { |
968 | case RADEON_HPD_1: | |
969 | WREG32(DC_HPD1_CONTROL, tmp); | |
e0df1ac5 AD |
970 | break; |
971 | case RADEON_HPD_2: | |
972 | WREG32(DC_HPD2_CONTROL, tmp); | |
e0df1ac5 AD |
973 | break; |
974 | case RADEON_HPD_3: | |
975 | WREG32(DC_HPD3_CONTROL, tmp); | |
e0df1ac5 AD |
976 | break; |
977 | case RADEON_HPD_4: | |
978 | WREG32(DC_HPD4_CONTROL, tmp); | |
e0df1ac5 AD |
979 | break; |
980 | /* DCE 3.2 */ | |
981 | case RADEON_HPD_5: | |
982 | WREG32(DC_HPD5_CONTROL, tmp); | |
e0df1ac5 AD |
983 | break; |
984 | case RADEON_HPD_6: | |
985 | WREG32(DC_HPD6_CONTROL, tmp); | |
e0df1ac5 AD |
986 | break; |
987 | default: | |
988 | break; | |
989 | } | |
64912e99 | 990 | } else { |
e0df1ac5 AD |
991 | switch (radeon_connector->hpd.hpd) { |
992 | case RADEON_HPD_1: | |
993 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
e0df1ac5 AD |
994 | break; |
995 | case RADEON_HPD_2: | |
996 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
e0df1ac5 AD |
997 | break; |
998 | case RADEON_HPD_3: | |
999 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); | |
e0df1ac5 AD |
1000 | break; |
1001 | default: | |
1002 | break; | |
1003 | } | |
1004 | } | |
b2c0cbd6 NS |
1005 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
1006 | enable |= 1 << radeon_connector->hpd.hpd; | |
64912e99 | 1007 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
e0df1ac5 | 1008 | } |
fb98257a | 1009 | radeon_irq_kms_enable_hpd(rdev, enable); |
e0df1ac5 AD |
1010 | } |
1011 | ||
1012 | void r600_hpd_fini(struct radeon_device *rdev) | |
1013 | { | |
1014 | struct drm_device *dev = rdev->ddev; | |
1015 | struct drm_connector *connector; | |
fb98257a | 1016 | unsigned disable = 0; |
e0df1ac5 | 1017 | |
fb98257a CK |
1018 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
1019 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
1020 | if (ASIC_IS_DCE3(rdev)) { | |
e0df1ac5 AD |
1021 | switch (radeon_connector->hpd.hpd) { |
1022 | case RADEON_HPD_1: | |
1023 | WREG32(DC_HPD1_CONTROL, 0); | |
e0df1ac5 AD |
1024 | break; |
1025 | case RADEON_HPD_2: | |
1026 | WREG32(DC_HPD2_CONTROL, 0); | |
e0df1ac5 AD |
1027 | break; |
1028 | case RADEON_HPD_3: | |
1029 | WREG32(DC_HPD3_CONTROL, 0); | |
e0df1ac5 AD |
1030 | break; |
1031 | case RADEON_HPD_4: | |
1032 | WREG32(DC_HPD4_CONTROL, 0); | |
e0df1ac5 AD |
1033 | break; |
1034 | /* DCE 3.2 */ | |
1035 | case RADEON_HPD_5: | |
1036 | WREG32(DC_HPD5_CONTROL, 0); | |
e0df1ac5 AD |
1037 | break; |
1038 | case RADEON_HPD_6: | |
1039 | WREG32(DC_HPD6_CONTROL, 0); | |
e0df1ac5 AD |
1040 | break; |
1041 | default: | |
1042 | break; | |
1043 | } | |
fb98257a | 1044 | } else { |
e0df1ac5 AD |
1045 | switch (radeon_connector->hpd.hpd) { |
1046 | case RADEON_HPD_1: | |
1047 | WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); | |
e0df1ac5 AD |
1048 | break; |
1049 | case RADEON_HPD_2: | |
1050 | WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); | |
e0df1ac5 AD |
1051 | break; |
1052 | case RADEON_HPD_3: | |
1053 | WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); | |
e0df1ac5 AD |
1054 | break; |
1055 | default: | |
1056 | break; | |
1057 | } | |
1058 | } | |
b2c0cbd6 NS |
1059 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
1060 | disable |= 1 << radeon_connector->hpd.hpd; | |
e0df1ac5 | 1061 | } |
fb98257a | 1062 | radeon_irq_kms_disable_hpd(rdev, disable); |
e0df1ac5 AD |
1063 | } |
1064 | ||
771fe6b9 | 1065 | /* |
3ce0a23d | 1066 | * R600 PCIE GART |
771fe6b9 | 1067 | */ |
3ce0a23d JG |
1068 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) |
1069 | { | |
1070 | unsigned i; | |
1071 | u32 tmp; | |
1072 | ||
2e98f10a | 1073 | /* flush hdp cache so updates hit vram */ |
f3886f85 AD |
1074 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
1075 | !(rdev->flags & RADEON_IS_AGP)) { | |
c9a1be96 | 1076 | void __iomem *ptr = (void *)rdev->gart.ptr; |
812d0469 AD |
1077 | u32 tmp; |
1078 | ||
1079 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read | |
1080 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL | |
f3886f85 AD |
1081 | * This seems to cause problems on some AGP cards. Just use the old |
1082 | * method for them. | |
812d0469 AD |
1083 | */ |
1084 | WREG32(HDP_DEBUG1, 0); | |
1085 | tmp = readl((void __iomem *)ptr); | |
1086 | } else | |
1087 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
2e98f10a | 1088 | |
3ce0a23d JG |
1089 | WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); |
1090 | WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); | |
1091 | WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); | |
1092 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1093 | /* read MC_STATUS */ | |
1094 | tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); | |
1095 | tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; | |
1096 | if (tmp == 2) { | |
1097 | printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); | |
1098 | return; | |
1099 | } | |
1100 | if (tmp) { | |
1101 | return; | |
1102 | } | |
1103 | udelay(1); | |
1104 | } | |
1105 | } | |
1106 | ||
4aac0473 | 1107 | int r600_pcie_gart_init(struct radeon_device *rdev) |
3ce0a23d | 1108 | { |
4aac0473 | 1109 | int r; |
3ce0a23d | 1110 | |
c9a1be96 | 1111 | if (rdev->gart.robj) { |
fce7d61b | 1112 | WARN(1, "R600 PCIE GART already initialized\n"); |
4aac0473 JG |
1113 | return 0; |
1114 | } | |
3ce0a23d JG |
1115 | /* Initialize common gart structure */ |
1116 | r = radeon_gart_init(rdev); | |
4aac0473 | 1117 | if (r) |
3ce0a23d | 1118 | return r; |
3ce0a23d | 1119 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
4aac0473 JG |
1120 | return radeon_gart_table_vram_alloc(rdev); |
1121 | } | |
1122 | ||
1109ca09 | 1123 | static int r600_pcie_gart_enable(struct radeon_device *rdev) |
4aac0473 JG |
1124 | { |
1125 | u32 tmp; | |
1126 | int r, i; | |
1127 | ||
c9a1be96 | 1128 | if (rdev->gart.robj == NULL) { |
4aac0473 JG |
1129 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
1130 | return -EINVAL; | |
771fe6b9 | 1131 | } |
4aac0473 JG |
1132 | r = radeon_gart_table_vram_pin(rdev); |
1133 | if (r) | |
1134 | return r; | |
bc1a631e | 1135 | |
3ce0a23d JG |
1136 | /* Setup L2 cache */ |
1137 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
1138 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
1139 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
1140 | WREG32(VM_L2_CNTL2, 0); | |
1141 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
1142 | /* Setup TLB control */ | |
1143 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
1144 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
1145 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
1146 | ENABLE_WAIT_L2_QUERY; | |
1147 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
1148 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
1149 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
1150 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
1151 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
1152 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
1153 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
1154 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
1155 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
1156 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
1157 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
1158 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
a8fba64a CK |
1159 | WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); |
1160 | WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); | |
3ce0a23d JG |
1161 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); |
1162 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
1163 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); | |
7c0411d2 | 1164 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
3ce0a23d JG |
1165 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
1166 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | | |
1167 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); | |
1168 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, | |
1169 | (u32)(rdev->dummy_page.addr >> 12)); | |
1170 | for (i = 1; i < 7; i++) | |
1171 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 1172 | |
3ce0a23d | 1173 | r600_pcie_gart_tlb_flush(rdev); |
fcf4de5a TV |
1174 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
1175 | (unsigned)(rdev->mc.gtt_size >> 20), | |
1176 | (unsigned long long)rdev->gart.table_addr); | |
3ce0a23d | 1177 | rdev->gart.ready = true; |
771fe6b9 JG |
1178 | return 0; |
1179 | } | |
1180 | ||
1109ca09 | 1181 | static void r600_pcie_gart_disable(struct radeon_device *rdev) |
771fe6b9 | 1182 | { |
3ce0a23d | 1183 | u32 tmp; |
c9a1be96 | 1184 | int i; |
771fe6b9 | 1185 | |
3ce0a23d JG |
1186 | /* Disable all tables */ |
1187 | for (i = 0; i < 7; i++) | |
1188 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
771fe6b9 | 1189 | |
3ce0a23d JG |
1190 | /* Disable L2 cache */ |
1191 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | | |
1192 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
1193 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
1194 | /* Setup L1 TLB control */ | |
1195 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
1196 | ENABLE_WAIT_L2_QUERY; | |
1197 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
1198 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
1199 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
1200 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
1201 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
1202 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
1203 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
1204 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
1205 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); | |
1206 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); | |
1207 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
1208 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
1209 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); | |
1210 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
a8fba64a CK |
1211 | WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); |
1212 | WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); | |
c9a1be96 | 1213 | radeon_gart_table_vram_unpin(rdev); |
4aac0473 JG |
1214 | } |
1215 | ||
1109ca09 | 1216 | static void r600_pcie_gart_fini(struct radeon_device *rdev) |
4aac0473 | 1217 | { |
f9274562 | 1218 | radeon_gart_fini(rdev); |
4aac0473 JG |
1219 | r600_pcie_gart_disable(rdev); |
1220 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
1221 | } |
1222 | ||
1109ca09 | 1223 | static void r600_agp_enable(struct radeon_device *rdev) |
1a029b76 JG |
1224 | { |
1225 | u32 tmp; | |
1226 | int i; | |
1227 | ||
1228 | /* Setup L2 cache */ | |
1229 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | | |
1230 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | | |
1231 | EFFECTIVE_L2_QUEUE_SIZE(7)); | |
1232 | WREG32(VM_L2_CNTL2, 0); | |
1233 | WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); | |
1234 | /* Setup TLB control */ | |
1235 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | | |
1236 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | | |
1237 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | | |
1238 | ENABLE_WAIT_L2_QUERY; | |
1239 | WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); | |
1240 | WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); | |
1241 | WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); | |
1242 | WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); | |
1243 | WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); | |
1244 | WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); | |
1245 | WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); | |
1246 | WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); | |
1247 | WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); | |
1248 | WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); | |
1249 | WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); | |
1250 | WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); | |
1251 | WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
1252 | WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); | |
1253 | for (i = 0; i < 7; i++) | |
1254 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); | |
1255 | } | |
1256 | ||
771fe6b9 JG |
1257 | int r600_mc_wait_for_idle(struct radeon_device *rdev) |
1258 | { | |
3ce0a23d JG |
1259 | unsigned i; |
1260 | u32 tmp; | |
1261 | ||
1262 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1263 | /* read MC_STATUS */ | |
1264 | tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; | |
1265 | if (!tmp) | |
1266 | return 0; | |
1267 | udelay(1); | |
1268 | } | |
1269 | return -1; | |
771fe6b9 JG |
1270 | } |
1271 | ||
65337e60 SL |
1272 | uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
1273 | { | |
0a5b7b0b | 1274 | unsigned long flags; |
65337e60 SL |
1275 | uint32_t r; |
1276 | ||
0a5b7b0b | 1277 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
65337e60 SL |
1278 | WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); |
1279 | r = RREG32(R_0028FC_MC_DATA); | |
1280 | WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); | |
0a5b7b0b | 1281 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
65337e60 SL |
1282 | return r; |
1283 | } | |
1284 | ||
1285 | void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1286 | { | |
0a5b7b0b AD |
1287 | unsigned long flags; |
1288 | ||
1289 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); | |
65337e60 SL |
1290 | WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | |
1291 | S_0028F8_MC_IND_WR_EN(1)); | |
1292 | WREG32(R_0028FC_MC_DATA, v); | |
1293 | WREG32(R_0028F8_MC_INDEX, 0x7F); | |
0a5b7b0b | 1294 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
65337e60 SL |
1295 | } |
1296 | ||
a3c1945a | 1297 | static void r600_mc_program(struct radeon_device *rdev) |
771fe6b9 | 1298 | { |
a3c1945a | 1299 | struct rv515_mc_save save; |
3ce0a23d JG |
1300 | u32 tmp; |
1301 | int i, j; | |
771fe6b9 | 1302 | |
3ce0a23d JG |
1303 | /* Initialize HDP */ |
1304 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
1305 | WREG32((0x2c14 + j), 0x00000000); | |
1306 | WREG32((0x2c18 + j), 0x00000000); | |
1307 | WREG32((0x2c1c + j), 0x00000000); | |
1308 | WREG32((0x2c20 + j), 0x00000000); | |
1309 | WREG32((0x2c24 + j), 0x00000000); | |
1310 | } | |
1311 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); | |
771fe6b9 | 1312 | |
a3c1945a | 1313 | rv515_mc_stop(rdev, &save); |
3ce0a23d | 1314 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 1315 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 1316 | } |
a3c1945a | 1317 | /* Lockout access through VGA aperture (doesn't exist before R600) */ |
3ce0a23d | 1318 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
3ce0a23d | 1319 | /* Update configuration */ |
1a029b76 JG |
1320 | if (rdev->flags & RADEON_IS_AGP) { |
1321 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { | |
1322 | /* VRAM before AGP */ | |
1323 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1324 | rdev->mc.vram_start >> 12); | |
1325 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1326 | rdev->mc.gtt_end >> 12); | |
1327 | } else { | |
1328 | /* VRAM after AGP */ | |
1329 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, | |
1330 | rdev->mc.gtt_start >> 12); | |
1331 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, | |
1332 | rdev->mc.vram_end >> 12); | |
1333 | } | |
1334 | } else { | |
1335 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); | |
1336 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); | |
1337 | } | |
16cdf04d | 1338 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); |
1a029b76 | 1339 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
3ce0a23d JG |
1340 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
1341 | WREG32(MC_VM_FB_LOCATION, tmp); | |
1342 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | |
1343 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); | |
46fcd2b3 | 1344 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
3ce0a23d | 1345 | if (rdev->flags & RADEON_IS_AGP) { |
1a029b76 JG |
1346 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); |
1347 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); | |
3ce0a23d JG |
1348 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
1349 | } else { | |
1350 | WREG32(MC_VM_AGP_BASE, 0); | |
1351 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); | |
1352 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); | |
1353 | } | |
3ce0a23d | 1354 | if (r600_mc_wait_for_idle(rdev)) { |
a3c1945a | 1355 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
3ce0a23d | 1356 | } |
a3c1945a | 1357 | rv515_mc_resume(rdev, &save); |
698443d9 DA |
1358 | /* we need to own VRAM, so turn off the VGA renderer here |
1359 | * to stop it overwriting our objects */ | |
d39c3b89 | 1360 | rv515_vga_render_disable(rdev); |
3ce0a23d JG |
1361 | } |
1362 | ||
d594e46a JG |
1363 | /** |
1364 | * r600_vram_gtt_location - try to find VRAM & GTT location | |
1365 | * @rdev: radeon device structure holding all necessary informations | |
1366 | * @mc: memory controller structure holding memory informations | |
1367 | * | |
1368 | * Function will place try to place VRAM at same place as in CPU (PCI) | |
1369 | * address space as some GPU seems to have issue when we reprogram at | |
1370 | * different address space. | |
1371 | * | |
1372 | * If there is not enough space to fit the unvisible VRAM after the | |
1373 | * aperture then we limit the VRAM size to the aperture. | |
1374 | * | |
1375 | * If we are using AGP then place VRAM adjacent to AGP aperture are we need | |
1376 | * them to be in one from GPU point of view so that we can program GPU to | |
1377 | * catch access outside them (weird GPU policy see ??). | |
1378 | * | |
1379 | * This function will never fails, worst case are limiting VRAM or GTT. | |
1380 | * | |
1381 | * Note: GTT start, end, size should be initialized before calling this | |
1382 | * function on AGP platform. | |
1383 | */ | |
0ef0c1f7 | 1384 | static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
d594e46a JG |
1385 | { |
1386 | u64 size_bf, size_af; | |
1387 | ||
1388 | if (mc->mc_vram_size > 0xE0000000) { | |
1389 | /* leave room for at least 512M GTT */ | |
1390 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1391 | mc->real_vram_size = 0xE0000000; | |
1392 | mc->mc_vram_size = 0xE0000000; | |
1393 | } | |
1394 | if (rdev->flags & RADEON_IS_AGP) { | |
1395 | size_bf = mc->gtt_start; | |
9ed8b1f9 | 1396 | size_af = mc->mc_mask - mc->gtt_end; |
d594e46a JG |
1397 | if (size_bf > size_af) { |
1398 | if (mc->mc_vram_size > size_bf) { | |
1399 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1400 | mc->real_vram_size = size_bf; | |
1401 | mc->mc_vram_size = size_bf; | |
1402 | } | |
1403 | mc->vram_start = mc->gtt_start - mc->mc_vram_size; | |
1404 | } else { | |
1405 | if (mc->mc_vram_size > size_af) { | |
1406 | dev_warn(rdev->dev, "limiting VRAM\n"); | |
1407 | mc->real_vram_size = size_af; | |
1408 | mc->mc_vram_size = size_af; | |
1409 | } | |
dfc6ae5b | 1410 | mc->vram_start = mc->gtt_end + 1; |
d594e46a JG |
1411 | } |
1412 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; | |
1413 | dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", | |
1414 | mc->mc_vram_size >> 20, mc->vram_start, | |
1415 | mc->vram_end, mc->real_vram_size >> 20); | |
1416 | } else { | |
1417 | u64 base = 0; | |
8961d52d AD |
1418 | if (rdev->flags & RADEON_IS_IGP) { |
1419 | base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; | |
1420 | base <<= 24; | |
1421 | } | |
d594e46a | 1422 | radeon_vram_location(rdev, &rdev->mc, base); |
8d369bb1 | 1423 | rdev->mc.gtt_base_align = 0; |
d594e46a JG |
1424 | radeon_gtt_location(rdev, mc); |
1425 | } | |
1426 | } | |
1427 | ||
1109ca09 | 1428 | static int r600_mc_init(struct radeon_device *rdev) |
771fe6b9 | 1429 | { |
3ce0a23d | 1430 | u32 tmp; |
5885b7a9 | 1431 | int chansize, numchan; |
65337e60 SL |
1432 | uint32_t h_addr, l_addr; |
1433 | unsigned long long k8_addr; | |
771fe6b9 | 1434 | |
3ce0a23d | 1435 | /* Get VRAM informations */ |
771fe6b9 | 1436 | rdev->mc.vram_is_ddr = true; |
3ce0a23d JG |
1437 | tmp = RREG32(RAMCFG); |
1438 | if (tmp & CHANSIZE_OVERRIDE) { | |
771fe6b9 | 1439 | chansize = 16; |
3ce0a23d | 1440 | } else if (tmp & CHANSIZE_MASK) { |
771fe6b9 JG |
1441 | chansize = 64; |
1442 | } else { | |
1443 | chansize = 32; | |
1444 | } | |
5885b7a9 AD |
1445 | tmp = RREG32(CHMAP); |
1446 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | |
1447 | case 0: | |
1448 | default: | |
1449 | numchan = 1; | |
1450 | break; | |
1451 | case 1: | |
1452 | numchan = 2; | |
1453 | break; | |
1454 | case 2: | |
1455 | numchan = 4; | |
1456 | break; | |
1457 | case 3: | |
1458 | numchan = 8; | |
1459 | break; | |
771fe6b9 | 1460 | } |
5885b7a9 | 1461 | rdev->mc.vram_width = numchan * chansize; |
3ce0a23d | 1462 | /* Could aper size report 0 ? */ |
01d73a69 JC |
1463 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
1464 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); | |
3ce0a23d JG |
1465 | /* Setup GPU memory space */ |
1466 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); | |
1467 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); | |
51e5fcd3 | 1468 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
d594e46a | 1469 | r600_vram_gtt_location(rdev, &rdev->mc); |
f47299c5 | 1470 | |
f892034a AD |
1471 | if (rdev->flags & RADEON_IS_IGP) { |
1472 | rs690_pm_info(rdev); | |
06b6476d | 1473 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
65337e60 SL |
1474 | |
1475 | if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { | |
1476 | /* Use K8 direct mapping for fast fb access. */ | |
1477 | rdev->fastfb_working = false; | |
1478 | h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL)); | |
1479 | l_addr = RREG32_MC(R_000011_K8_FB_LOCATION); | |
1480 | k8_addr = ((unsigned long long)h_addr) << 32 | l_addr; | |
1481 | #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE) | |
1482 | if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) | |
1483 | #endif | |
1484 | { | |
1485 | /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport | |
1486 | * memory is present. | |
1487 | */ | |
1488 | if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { | |
1489 | DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n", | |
1490 | (unsigned long long)rdev->mc.aper_base, k8_addr); | |
1491 | rdev->mc.aper_base = (resource_size_t)k8_addr; | |
1492 | rdev->fastfb_working = true; | |
1493 | } | |
1494 | } | |
3cf8bb1a | 1495 | } |
f892034a | 1496 | } |
65337e60 | 1497 | |
f47299c5 | 1498 | radeon_update_bandwidth_info(rdev); |
3ce0a23d | 1499 | return 0; |
771fe6b9 JG |
1500 | } |
1501 | ||
16cdf04d AD |
1502 | int r600_vram_scratch_init(struct radeon_device *rdev) |
1503 | { | |
1504 | int r; | |
1505 | ||
1506 | if (rdev->vram_scratch.robj == NULL) { | |
1507 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, | |
1508 | PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, | |
831b6966 | 1509 | 0, NULL, NULL, &rdev->vram_scratch.robj); |
16cdf04d AD |
1510 | if (r) { |
1511 | return r; | |
1512 | } | |
1513 | } | |
1514 | ||
1515 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); | |
1516 | if (unlikely(r != 0)) | |
1517 | return r; | |
1518 | r = radeon_bo_pin(rdev->vram_scratch.robj, | |
1519 | RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); | |
1520 | if (r) { | |
1521 | radeon_bo_unreserve(rdev->vram_scratch.robj); | |
1522 | return r; | |
1523 | } | |
1524 | r = radeon_bo_kmap(rdev->vram_scratch.robj, | |
1525 | (void **)&rdev->vram_scratch.ptr); | |
1526 | if (r) | |
1527 | radeon_bo_unpin(rdev->vram_scratch.robj); | |
1528 | radeon_bo_unreserve(rdev->vram_scratch.robj); | |
1529 | ||
1530 | return r; | |
1531 | } | |
1532 | ||
1533 | void r600_vram_scratch_fini(struct radeon_device *rdev) | |
1534 | { | |
1535 | int r; | |
1536 | ||
1537 | if (rdev->vram_scratch.robj == NULL) { | |
1538 | return; | |
1539 | } | |
1540 | r = radeon_bo_reserve(rdev->vram_scratch.robj, false); | |
1541 | if (likely(r == 0)) { | |
1542 | radeon_bo_kunmap(rdev->vram_scratch.robj); | |
1543 | radeon_bo_unpin(rdev->vram_scratch.robj); | |
1544 | radeon_bo_unreserve(rdev->vram_scratch.robj); | |
1545 | } | |
1546 | radeon_bo_unref(&rdev->vram_scratch.robj); | |
1547 | } | |
1548 | ||
410a3418 AD |
1549 | void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung) |
1550 | { | |
1551 | u32 tmp = RREG32(R600_BIOS_3_SCRATCH); | |
1552 | ||
1553 | if (hung) | |
1554 | tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; | |
1555 | else | |
1556 | tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; | |
1557 | ||
1558 | WREG32(R600_BIOS_3_SCRATCH, tmp); | |
1559 | } | |
1560 | ||
d3cb781e | 1561 | static void r600_print_gpu_status_regs(struct radeon_device *rdev) |
771fe6b9 | 1562 | { |
64c56e8c | 1563 | dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", |
d3cb781e | 1564 | RREG32(R_008010_GRBM_STATUS)); |
64c56e8c | 1565 | dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", |
d3cb781e | 1566 | RREG32(R_008014_GRBM_STATUS2)); |
64c56e8c | 1567 | dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", |
d3cb781e | 1568 | RREG32(R_000E50_SRBM_STATUS)); |
440a7cd8 | 1569 | dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", |
d3cb781e | 1570 | RREG32(CP_STALLED_STAT1)); |
440a7cd8 | 1571 | dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", |
d3cb781e | 1572 | RREG32(CP_STALLED_STAT2)); |
440a7cd8 | 1573 | dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", |
d3cb781e | 1574 | RREG32(CP_BUSY_STAT)); |
440a7cd8 | 1575 | dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", |
d3cb781e | 1576 | RREG32(CP_STAT)); |
71e3d157 AD |
1577 | dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", |
1578 | RREG32(DMA_STATUS_REG)); | |
1579 | } | |
1580 | ||
f13f7731 | 1581 | static bool r600_is_display_hung(struct radeon_device *rdev) |
71e3d157 | 1582 | { |
f13f7731 AD |
1583 | u32 crtc_hung = 0; |
1584 | u32 crtc_status[2]; | |
1585 | u32 i, j, tmp; | |
1586 | ||
1587 | for (i = 0; i < rdev->num_crtc; i++) { | |
1588 | if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { | |
1589 | crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); | |
1590 | crtc_hung |= (1 << i); | |
1591 | } | |
1592 | } | |
1593 | ||
1594 | for (j = 0; j < 10; j++) { | |
1595 | for (i = 0; i < rdev->num_crtc; i++) { | |
1596 | if (crtc_hung & (1 << i)) { | |
1597 | tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); | |
1598 | if (tmp != crtc_status[i]) | |
1599 | crtc_hung &= ~(1 << i); | |
1600 | } | |
1601 | } | |
1602 | if (crtc_hung == 0) | |
1603 | return false; | |
1604 | udelay(100); | |
1605 | } | |
1606 | ||
1607 | return true; | |
1608 | } | |
1609 | ||
2483b4ea | 1610 | u32 r600_gpu_check_soft_reset(struct radeon_device *rdev) |
f13f7731 AD |
1611 | { |
1612 | u32 reset_mask = 0; | |
d3cb781e | 1613 | u32 tmp; |
71e3d157 | 1614 | |
f13f7731 AD |
1615 | /* GRBM_STATUS */ |
1616 | tmp = RREG32(R_008010_GRBM_STATUS); | |
1617 | if (rdev->family >= CHIP_RV770) { | |
1618 | if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | | |
1619 | G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | | |
1620 | G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | | |
1621 | G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | | |
1622 | G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) | |
1623 | reset_mask |= RADEON_RESET_GFX; | |
1624 | } else { | |
1625 | if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | | |
1626 | G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | | |
1627 | G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | | |
1628 | G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | | |
1629 | G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) | |
1630 | reset_mask |= RADEON_RESET_GFX; | |
1631 | } | |
1632 | ||
1633 | if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | | |
1634 | G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) | |
1635 | reset_mask |= RADEON_RESET_CP; | |
1636 | ||
1637 | if (G_008010_GRBM_EE_BUSY(tmp)) | |
1638 | reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; | |
1639 | ||
1640 | /* DMA_STATUS_REG */ | |
1641 | tmp = RREG32(DMA_STATUS_REG); | |
1642 | if (!(tmp & DMA_IDLE)) | |
1643 | reset_mask |= RADEON_RESET_DMA; | |
1644 | ||
1645 | /* SRBM_STATUS */ | |
1646 | tmp = RREG32(R_000E50_SRBM_STATUS); | |
1647 | if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) | |
1648 | reset_mask |= RADEON_RESET_RLC; | |
1649 | ||
1650 | if (G_000E50_IH_BUSY(tmp)) | |
1651 | reset_mask |= RADEON_RESET_IH; | |
1652 | ||
1653 | if (G_000E50_SEM_BUSY(tmp)) | |
1654 | reset_mask |= RADEON_RESET_SEM; | |
19fc42ed | 1655 | |
f13f7731 AD |
1656 | if (G_000E50_GRBM_RQ_PENDING(tmp)) |
1657 | reset_mask |= RADEON_RESET_GRBM; | |
1658 | ||
1659 | if (G_000E50_VMC_BUSY(tmp)) | |
1660 | reset_mask |= RADEON_RESET_VMC; | |
1661 | ||
1662 | if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | | |
1663 | G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | | |
1664 | G_000E50_MCDW_BUSY(tmp)) | |
1665 | reset_mask |= RADEON_RESET_MC; | |
1666 | ||
1667 | if (r600_is_display_hung(rdev)) | |
1668 | reset_mask |= RADEON_RESET_DISPLAY; | |
1669 | ||
d808fc88 AD |
1670 | /* Skip MC reset as it's mostly likely not hung, just busy */ |
1671 | if (reset_mask & RADEON_RESET_MC) { | |
1672 | DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); | |
1673 | reset_mask &= ~RADEON_RESET_MC; | |
1674 | } | |
1675 | ||
f13f7731 AD |
1676 | return reset_mask; |
1677 | } | |
1678 | ||
1679 | static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) | |
1680 | { | |
1681 | struct rv515_mc_save save; | |
1682 | u32 grbm_soft_reset = 0, srbm_soft_reset = 0; | |
1683 | u32 tmp; | |
19fc42ed | 1684 | |
71e3d157 | 1685 | if (reset_mask == 0) |
f13f7731 | 1686 | return; |
71e3d157 AD |
1687 | |
1688 | dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); | |
1689 | ||
d3cb781e AD |
1690 | r600_print_gpu_status_regs(rdev); |
1691 | ||
d3cb781e AD |
1692 | /* Disable CP parsing/prefetching */ |
1693 | if (rdev->family >= CHIP_RV770) | |
1694 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); | |
1695 | else | |
1696 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); | |
1697 | ||
1698 | /* disable the RLC */ | |
1699 | WREG32(RLC_CNTL, 0); | |
1700 | ||
1701 | if (reset_mask & RADEON_RESET_DMA) { | |
1702 | /* Disable DMA */ | |
1703 | tmp = RREG32(DMA_RB_CNTL); | |
1704 | tmp &= ~DMA_RB_ENABLE; | |
1705 | WREG32(DMA_RB_CNTL, tmp); | |
1706 | } | |
1707 | ||
1708 | mdelay(50); | |
1709 | ||
ca57802e AD |
1710 | rv515_mc_stop(rdev, &save); |
1711 | if (r600_mc_wait_for_idle(rdev)) { | |
1712 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
1713 | } | |
1714 | ||
d3cb781e AD |
1715 | if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) { |
1716 | if (rdev->family >= CHIP_RV770) | |
1717 | grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) | | |
1718 | S_008020_SOFT_RESET_CB(1) | | |
1719 | S_008020_SOFT_RESET_PA(1) | | |
1720 | S_008020_SOFT_RESET_SC(1) | | |
1721 | S_008020_SOFT_RESET_SPI(1) | | |
1722 | S_008020_SOFT_RESET_SX(1) | | |
1723 | S_008020_SOFT_RESET_SH(1) | | |
1724 | S_008020_SOFT_RESET_TC(1) | | |
1725 | S_008020_SOFT_RESET_TA(1) | | |
1726 | S_008020_SOFT_RESET_VC(1) | | |
1727 | S_008020_SOFT_RESET_VGT(1); | |
1728 | else | |
1729 | grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) | | |
1730 | S_008020_SOFT_RESET_DB(1) | | |
1731 | S_008020_SOFT_RESET_CB(1) | | |
1732 | S_008020_SOFT_RESET_PA(1) | | |
1733 | S_008020_SOFT_RESET_SC(1) | | |
1734 | S_008020_SOFT_RESET_SMX(1) | | |
1735 | S_008020_SOFT_RESET_SPI(1) | | |
1736 | S_008020_SOFT_RESET_SX(1) | | |
1737 | S_008020_SOFT_RESET_SH(1) | | |
1738 | S_008020_SOFT_RESET_TC(1) | | |
1739 | S_008020_SOFT_RESET_TA(1) | | |
1740 | S_008020_SOFT_RESET_VC(1) | | |
1741 | S_008020_SOFT_RESET_VGT(1); | |
1742 | } | |
1743 | ||
1744 | if (reset_mask & RADEON_RESET_CP) { | |
1745 | grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) | | |
1746 | S_008020_SOFT_RESET_VGT(1); | |
1747 | ||
1748 | srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); | |
1749 | } | |
1750 | ||
1751 | if (reset_mask & RADEON_RESET_DMA) { | |
1752 | if (rdev->family >= CHIP_RV770) | |
1753 | srbm_soft_reset |= RV770_SOFT_RESET_DMA; | |
1754 | else | |
1755 | srbm_soft_reset |= SOFT_RESET_DMA; | |
1756 | } | |
1757 | ||
f13f7731 AD |
1758 | if (reset_mask & RADEON_RESET_RLC) |
1759 | srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1); | |
1760 | ||
1761 | if (reset_mask & RADEON_RESET_SEM) | |
1762 | srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1); | |
1763 | ||
1764 | if (reset_mask & RADEON_RESET_IH) | |
1765 | srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1); | |
1766 | ||
1767 | if (reset_mask & RADEON_RESET_GRBM) | |
1768 | srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1); | |
1769 | ||
24178ec4 AD |
1770 | if (!(rdev->flags & RADEON_IS_IGP)) { |
1771 | if (reset_mask & RADEON_RESET_MC) | |
1772 | srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1); | |
1773 | } | |
f13f7731 AD |
1774 | |
1775 | if (reset_mask & RADEON_RESET_VMC) | |
1776 | srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1); | |
1777 | ||
d3cb781e AD |
1778 | if (grbm_soft_reset) { |
1779 | tmp = RREG32(R_008020_GRBM_SOFT_RESET); | |
1780 | tmp |= grbm_soft_reset; | |
1781 | dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); | |
1782 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); | |
1783 | tmp = RREG32(R_008020_GRBM_SOFT_RESET); | |
1784 | ||
1785 | udelay(50); | |
1786 | ||
1787 | tmp &= ~grbm_soft_reset; | |
1788 | WREG32(R_008020_GRBM_SOFT_RESET, tmp); | |
1789 | tmp = RREG32(R_008020_GRBM_SOFT_RESET); | |
1790 | } | |
1791 | ||
1792 | if (srbm_soft_reset) { | |
1793 | tmp = RREG32(SRBM_SOFT_RESET); | |
1794 | tmp |= srbm_soft_reset; | |
1795 | dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); | |
1796 | WREG32(SRBM_SOFT_RESET, tmp); | |
1797 | tmp = RREG32(SRBM_SOFT_RESET); | |
1798 | ||
1799 | udelay(50); | |
71e3d157 | 1800 | |
d3cb781e AD |
1801 | tmp &= ~srbm_soft_reset; |
1802 | WREG32(SRBM_SOFT_RESET, tmp); | |
1803 | tmp = RREG32(SRBM_SOFT_RESET); | |
1804 | } | |
71e3d157 AD |
1805 | |
1806 | /* Wait a little for things to settle down */ | |
1807 | mdelay(1); | |
1808 | ||
a3c1945a | 1809 | rv515_mc_resume(rdev, &save); |
d3cb781e | 1810 | udelay(50); |
410a3418 | 1811 | |
d3cb781e | 1812 | r600_print_gpu_status_regs(rdev); |
d3cb781e AD |
1813 | } |
1814 | ||
de9ae744 AD |
1815 | static void r600_gpu_pci_config_reset(struct radeon_device *rdev) |
1816 | { | |
1817 | struct rv515_mc_save save; | |
1818 | u32 tmp, i; | |
1819 | ||
1820 | dev_info(rdev->dev, "GPU pci config reset\n"); | |
1821 | ||
1822 | /* disable dpm? */ | |
1823 | ||
1824 | /* Disable CP parsing/prefetching */ | |
1825 | if (rdev->family >= CHIP_RV770) | |
1826 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); | |
1827 | else | |
1828 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); | |
1829 | ||
1830 | /* disable the RLC */ | |
1831 | WREG32(RLC_CNTL, 0); | |
1832 | ||
1833 | /* Disable DMA */ | |
1834 | tmp = RREG32(DMA_RB_CNTL); | |
1835 | tmp &= ~DMA_RB_ENABLE; | |
1836 | WREG32(DMA_RB_CNTL, tmp); | |
1837 | ||
1838 | mdelay(50); | |
1839 | ||
1840 | /* set mclk/sclk to bypass */ | |
1841 | if (rdev->family >= CHIP_RV770) | |
1842 | rv770_set_clk_bypass_mode(rdev); | |
1843 | /* disable BM */ | |
1844 | pci_clear_master(rdev->pdev); | |
1845 | /* disable mem access */ | |
1846 | rv515_mc_stop(rdev, &save); | |
1847 | if (r600_mc_wait_for_idle(rdev)) { | |
1848 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | |
1849 | } | |
1850 | ||
1851 | /* BIF reset workaround. Not sure if this is needed on 6xx */ | |
1852 | tmp = RREG32(BUS_CNTL); | |
1853 | tmp |= VGA_COHE_SPEC_TIMER_DIS; | |
1854 | WREG32(BUS_CNTL, tmp); | |
1855 | ||
1856 | tmp = RREG32(BIF_SCRATCH0); | |
1857 | ||
1858 | /* reset */ | |
1859 | radeon_pci_config_reset(rdev); | |
1860 | mdelay(1); | |
1861 | ||
1862 | /* BIF reset workaround. Not sure if this is needed on 6xx */ | |
1863 | tmp = SOFT_RESET_BIF; | |
1864 | WREG32(SRBM_SOFT_RESET, tmp); | |
1865 | mdelay(1); | |
1866 | WREG32(SRBM_SOFT_RESET, 0); | |
1867 | ||
1868 | /* wait for asic to come out of reset */ | |
1869 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1870 | if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) | |
1871 | break; | |
1872 | udelay(1); | |
1873 | } | |
1874 | } | |
1875 | ||
71fe2899 | 1876 | int r600_asic_reset(struct radeon_device *rdev, bool hard) |
d3cb781e | 1877 | { |
f13f7731 AD |
1878 | u32 reset_mask; |
1879 | ||
71fe2899 JG |
1880 | if (hard) { |
1881 | r600_gpu_pci_config_reset(rdev); | |
1882 | return 0; | |
1883 | } | |
1884 | ||
f13f7731 AD |
1885 | reset_mask = r600_gpu_check_soft_reset(rdev); |
1886 | ||
1887 | if (reset_mask) | |
1888 | r600_set_bios_scratch_engine_hung(rdev, true); | |
1889 | ||
de9ae744 | 1890 | /* try soft reset */ |
f13f7731 AD |
1891 | r600_gpu_soft_reset(rdev, reset_mask); |
1892 | ||
1893 | reset_mask = r600_gpu_check_soft_reset(rdev); | |
1894 | ||
de9ae744 AD |
1895 | /* try pci config reset */ |
1896 | if (reset_mask && radeon_hard_reset) | |
1897 | r600_gpu_pci_config_reset(rdev); | |
1898 | ||
1899 | reset_mask = r600_gpu_check_soft_reset(rdev); | |
1900 | ||
f13f7731 AD |
1901 | if (!reset_mask) |
1902 | r600_set_bios_scratch_engine_hung(rdev, false); | |
1903 | ||
1904 | return 0; | |
3ce0a23d JG |
1905 | } |
1906 | ||
123bc183 AD |
1907 | /** |
1908 | * r600_gfx_is_lockup - Check if the GFX engine is locked up | |
1909 | * | |
1910 | * @rdev: radeon_device pointer | |
1911 | * @ring: radeon_ring structure holding ring information | |
1912 | * | |
1913 | * Check if the GFX engine is locked up. | |
1914 | * Returns true if the engine appears to be locked up, false if not. | |
1915 | */ | |
1916 | bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) | |
225758d8 | 1917 | { |
123bc183 AD |
1918 | u32 reset_mask = r600_gpu_check_soft_reset(rdev); |
1919 | ||
1920 | if (!(reset_mask & (RADEON_RESET_GFX | | |
1921 | RADEON_RESET_COMPUTE | | |
1922 | RADEON_RESET_CP))) { | |
ff212f25 | 1923 | radeon_ring_lockup_update(rdev, ring); |
225758d8 JG |
1924 | return false; |
1925 | } | |
069211e5 | 1926 | return radeon_ring_test_lockup(rdev, ring); |
225758d8 JG |
1927 | } |
1928 | ||
416a2bd2 AD |
1929 | u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
1930 | u32 tiling_pipe_num, | |
1931 | u32 max_rb_num, | |
1932 | u32 total_max_rb_num, | |
1933 | u32 disabled_rb_mask) | |
3ce0a23d | 1934 | { |
416a2bd2 | 1935 | u32 rendering_pipe_num, rb_num_width, req_rb_num; |
f689e3ac | 1936 | u32 pipe_rb_ratio, pipe_rb_remain, tmp; |
416a2bd2 AD |
1937 | u32 data = 0, mask = 1 << (max_rb_num - 1); |
1938 | unsigned i, j; | |
3ce0a23d | 1939 | |
416a2bd2 | 1940 | /* mask out the RBs that don't exist on that asic */ |
f689e3ac MT |
1941 | tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); |
1942 | /* make sure at least one RB is available */ | |
1943 | if ((tmp & 0xff) != 0xff) | |
1944 | disabled_rb_mask = tmp; | |
3ce0a23d | 1945 | |
416a2bd2 AD |
1946 | rendering_pipe_num = 1 << tiling_pipe_num; |
1947 | req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); | |
1948 | BUG_ON(rendering_pipe_num < req_rb_num); | |
3ce0a23d | 1949 | |
416a2bd2 AD |
1950 | pipe_rb_ratio = rendering_pipe_num / req_rb_num; |
1951 | pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; | |
3ce0a23d | 1952 | |
416a2bd2 AD |
1953 | if (rdev->family <= CHIP_RV740) { |
1954 | /* r6xx/r7xx */ | |
1955 | rb_num_width = 2; | |
1956 | } else { | |
1957 | /* eg+ */ | |
1958 | rb_num_width = 4; | |
1959 | } | |
3ce0a23d | 1960 | |
416a2bd2 AD |
1961 | for (i = 0; i < max_rb_num; i++) { |
1962 | if (!(mask & disabled_rb_mask)) { | |
1963 | for (j = 0; j < pipe_rb_ratio; j++) { | |
1964 | data <<= rb_num_width; | |
1965 | data |= max_rb_num - i - 1; | |
1966 | } | |
1967 | if (pipe_rb_remain) { | |
1968 | data <<= rb_num_width; | |
1969 | data |= max_rb_num - i - 1; | |
1970 | pipe_rb_remain--; | |
1971 | } | |
1972 | } | |
1973 | mask >>= 1; | |
3ce0a23d JG |
1974 | } |
1975 | ||
416a2bd2 | 1976 | return data; |
3ce0a23d JG |
1977 | } |
1978 | ||
1979 | int r600_count_pipe_bits(uint32_t val) | |
1980 | { | |
ef8cf3a1 | 1981 | return hweight32(val); |
771fe6b9 JG |
1982 | } |
1983 | ||
1109ca09 | 1984 | static void r600_gpu_init(struct radeon_device *rdev) |
3ce0a23d JG |
1985 | { |
1986 | u32 tiling_config; | |
1987 | u32 ramcfg; | |
d03f5d59 | 1988 | u32 cc_gc_shader_pipe_config; |
3ce0a23d JG |
1989 | u32 tmp; |
1990 | int i, j; | |
1991 | u32 sq_config; | |
1992 | u32 sq_gpr_resource_mgmt_1 = 0; | |
1993 | u32 sq_gpr_resource_mgmt_2 = 0; | |
1994 | u32 sq_thread_resource_mgmt = 0; | |
1995 | u32 sq_stack_resource_mgmt_1 = 0; | |
1996 | u32 sq_stack_resource_mgmt_2 = 0; | |
416a2bd2 | 1997 | u32 disabled_rb_mask; |
3ce0a23d | 1998 | |
416a2bd2 | 1999 | rdev->config.r600.tiling_group_size = 256; |
3ce0a23d JG |
2000 | switch (rdev->family) { |
2001 | case CHIP_R600: | |
2002 | rdev->config.r600.max_pipes = 4; | |
2003 | rdev->config.r600.max_tile_pipes = 8; | |
2004 | rdev->config.r600.max_simds = 4; | |
2005 | rdev->config.r600.max_backends = 4; | |
2006 | rdev->config.r600.max_gprs = 256; | |
2007 | rdev->config.r600.max_threads = 192; | |
2008 | rdev->config.r600.max_stack_entries = 256; | |
2009 | rdev->config.r600.max_hw_contexts = 8; | |
2010 | rdev->config.r600.max_gs_threads = 16; | |
2011 | rdev->config.r600.sx_max_export_size = 128; | |
2012 | rdev->config.r600.sx_max_export_pos_size = 16; | |
2013 | rdev->config.r600.sx_max_export_smx_size = 128; | |
2014 | rdev->config.r600.sq_num_cf_insts = 2; | |
2015 | break; | |
2016 | case CHIP_RV630: | |
2017 | case CHIP_RV635: | |
2018 | rdev->config.r600.max_pipes = 2; | |
2019 | rdev->config.r600.max_tile_pipes = 2; | |
2020 | rdev->config.r600.max_simds = 3; | |
2021 | rdev->config.r600.max_backends = 1; | |
2022 | rdev->config.r600.max_gprs = 128; | |
2023 | rdev->config.r600.max_threads = 192; | |
2024 | rdev->config.r600.max_stack_entries = 128; | |
2025 | rdev->config.r600.max_hw_contexts = 8; | |
2026 | rdev->config.r600.max_gs_threads = 4; | |
2027 | rdev->config.r600.sx_max_export_size = 128; | |
2028 | rdev->config.r600.sx_max_export_pos_size = 16; | |
2029 | rdev->config.r600.sx_max_export_smx_size = 128; | |
2030 | rdev->config.r600.sq_num_cf_insts = 2; | |
2031 | break; | |
2032 | case CHIP_RV610: | |
2033 | case CHIP_RV620: | |
2034 | case CHIP_RS780: | |
2035 | case CHIP_RS880: | |
2036 | rdev->config.r600.max_pipes = 1; | |
2037 | rdev->config.r600.max_tile_pipes = 1; | |
2038 | rdev->config.r600.max_simds = 2; | |
2039 | rdev->config.r600.max_backends = 1; | |
2040 | rdev->config.r600.max_gprs = 128; | |
2041 | rdev->config.r600.max_threads = 192; | |
2042 | rdev->config.r600.max_stack_entries = 128; | |
2043 | rdev->config.r600.max_hw_contexts = 4; | |
2044 | rdev->config.r600.max_gs_threads = 4; | |
2045 | rdev->config.r600.sx_max_export_size = 128; | |
2046 | rdev->config.r600.sx_max_export_pos_size = 16; | |
2047 | rdev->config.r600.sx_max_export_smx_size = 128; | |
2048 | rdev->config.r600.sq_num_cf_insts = 1; | |
2049 | break; | |
2050 | case CHIP_RV670: | |
2051 | rdev->config.r600.max_pipes = 4; | |
2052 | rdev->config.r600.max_tile_pipes = 4; | |
2053 | rdev->config.r600.max_simds = 4; | |
2054 | rdev->config.r600.max_backends = 4; | |
2055 | rdev->config.r600.max_gprs = 192; | |
2056 | rdev->config.r600.max_threads = 192; | |
2057 | rdev->config.r600.max_stack_entries = 256; | |
2058 | rdev->config.r600.max_hw_contexts = 8; | |
2059 | rdev->config.r600.max_gs_threads = 16; | |
2060 | rdev->config.r600.sx_max_export_size = 128; | |
2061 | rdev->config.r600.sx_max_export_pos_size = 16; | |
2062 | rdev->config.r600.sx_max_export_smx_size = 128; | |
2063 | rdev->config.r600.sq_num_cf_insts = 2; | |
2064 | break; | |
2065 | default: | |
2066 | break; | |
2067 | } | |
2068 | ||
2069 | /* Initialize HDP */ | |
2070 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { | |
2071 | WREG32((0x2c14 + j), 0x00000000); | |
2072 | WREG32((0x2c18 + j), 0x00000000); | |
2073 | WREG32((0x2c1c + j), 0x00000000); | |
2074 | WREG32((0x2c20 + j), 0x00000000); | |
2075 | WREG32((0x2c24 + j), 0x00000000); | |
2076 | } | |
2077 | ||
2078 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | |
2079 | ||
2080 | /* Setup tiling */ | |
2081 | tiling_config = 0; | |
2082 | ramcfg = RREG32(RAMCFG); | |
2083 | switch (rdev->config.r600.max_tile_pipes) { | |
2084 | case 1: | |
2085 | tiling_config |= PIPE_TILING(0); | |
2086 | break; | |
2087 | case 2: | |
2088 | tiling_config |= PIPE_TILING(1); | |
2089 | break; | |
2090 | case 4: | |
2091 | tiling_config |= PIPE_TILING(2); | |
2092 | break; | |
2093 | case 8: | |
2094 | tiling_config |= PIPE_TILING(3); | |
2095 | break; | |
2096 | default: | |
2097 | break; | |
2098 | } | |
d03f5d59 | 2099 | rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; |
961fb597 | 2100 | rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
3ce0a23d | 2101 | tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
881fe6c1 | 2102 | tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); |
416a2bd2 | 2103 | |
3ce0a23d JG |
2104 | tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; |
2105 | if (tmp > 3) { | |
2106 | tiling_config |= ROW_TILING(3); | |
2107 | tiling_config |= SAMPLE_SPLIT(3); | |
2108 | } else { | |
2109 | tiling_config |= ROW_TILING(tmp); | |
2110 | tiling_config |= SAMPLE_SPLIT(tmp); | |
2111 | } | |
2112 | tiling_config |= BANK_SWAPS(1); | |
d03f5d59 | 2113 | |
416a2bd2 | 2114 | cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; |
65fcf668 AD |
2115 | tmp = rdev->config.r600.max_simds - |
2116 | r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); | |
2117 | rdev->config.r600.active_simds = tmp; | |
416a2bd2 AD |
2118 | |
2119 | disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; | |
0a5f6e9d AD |
2120 | tmp = 0; |
2121 | for (i = 0; i < rdev->config.r600.max_backends; i++) | |
2122 | tmp |= (1 << i); | |
2123 | /* if all the backends are disabled, fix it up here */ | |
2124 | if ((disabled_rb_mask & tmp) == tmp) { | |
2125 | for (i = 0; i < rdev->config.r600.max_backends; i++) | |
2126 | disabled_rb_mask &= ~(1 << i); | |
2127 | } | |
416a2bd2 AD |
2128 | tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; |
2129 | tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, | |
2130 | R6XX_MAX_BACKENDS, disabled_rb_mask); | |
2131 | tiling_config |= tmp << 16; | |
2132 | rdev->config.r600.backend_map = tmp; | |
2133 | ||
e7aeeba6 | 2134 | rdev->config.r600.tile_config = tiling_config; |
3ce0a23d JG |
2135 | WREG32(GB_TILING_CONFIG, tiling_config); |
2136 | WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); | |
2137 | WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); | |
4d75658b | 2138 | WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); |
3ce0a23d | 2139 | |
d03f5d59 | 2140 | tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); |
3ce0a23d JG |
2141 | WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); |
2142 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); | |
2143 | ||
2144 | /* Setup some CP states */ | |
2145 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); | |
2146 | WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); | |
2147 | ||
2148 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | | |
2149 | SYNC_WALKER | SYNC_ALIGNER)); | |
2150 | /* Setup various GPU states */ | |
2151 | if (rdev->family == CHIP_RV670) | |
2152 | WREG32(ARB_GDEC_RD_CNTL, 0x00000021); | |
2153 | ||
2154 | tmp = RREG32(SX_DEBUG_1); | |
2155 | tmp |= SMX_EVENT_RELEASE; | |
2156 | if ((rdev->family > CHIP_R600)) | |
2157 | tmp |= ENABLE_NEW_SMX_ADDRESS; | |
2158 | WREG32(SX_DEBUG_1, tmp); | |
2159 | ||
2160 | if (((rdev->family) == CHIP_R600) || | |
2161 | ((rdev->family) == CHIP_RV630) || | |
2162 | ((rdev->family) == CHIP_RV610) || | |
2163 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
2164 | ((rdev->family) == CHIP_RS780) || |
2165 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
2166 | WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); |
2167 | } else { | |
2168 | WREG32(DB_DEBUG, 0); | |
2169 | } | |
2170 | WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | | |
2171 | DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); | |
2172 | ||
2173 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
2174 | WREG32(VGT_NUM_INSTANCES, 0); | |
2175 | ||
2176 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); | |
2177 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); | |
2178 | ||
2179 | tmp = RREG32(SQ_MS_FIFO_SIZES); | |
2180 | if (((rdev->family) == CHIP_RV610) || | |
2181 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
2182 | ((rdev->family) == CHIP_RS780) || |
2183 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
2184 | tmp = (CACHE_FIFO_SIZE(0xa) | |
2185 | FETCH_FIFO_HIWATER(0xa) | | |
2186 | DONE_FIFO_HIWATER(0xe0) | | |
2187 | ALU_UPDATE_FIFO_HIWATER(0x8)); | |
2188 | } else if (((rdev->family) == CHIP_R600) || | |
2189 | ((rdev->family) == CHIP_RV630)) { | |
2190 | tmp &= ~DONE_FIFO_HIWATER(0xff); | |
2191 | tmp |= DONE_FIFO_HIWATER(0x4); | |
2192 | } | |
2193 | WREG32(SQ_MS_FIFO_SIZES, tmp); | |
2194 | ||
2195 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
2196 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
2197 | */ | |
2198 | sq_config = RREG32(SQ_CONFIG); | |
2199 | sq_config &= ~(PS_PRIO(3) | | |
2200 | VS_PRIO(3) | | |
2201 | GS_PRIO(3) | | |
2202 | ES_PRIO(3)); | |
2203 | sq_config |= (DX9_CONSTS | | |
2204 | VC_ENABLE | | |
2205 | PS_PRIO(0) | | |
2206 | VS_PRIO(1) | | |
2207 | GS_PRIO(2) | | |
2208 | ES_PRIO(3)); | |
2209 | ||
2210 | if ((rdev->family) == CHIP_R600) { | |
2211 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | | |
2212 | NUM_VS_GPRS(124) | | |
2213 | NUM_CLAUSE_TEMP_GPRS(4)); | |
2214 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | | |
2215 | NUM_ES_GPRS(0)); | |
2216 | sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | | |
2217 | NUM_VS_THREADS(48) | | |
2218 | NUM_GS_THREADS(4) | | |
2219 | NUM_ES_THREADS(4)); | |
2220 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | | |
2221 | NUM_VS_STACK_ENTRIES(128)); | |
2222 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | | |
2223 | NUM_ES_STACK_ENTRIES(0)); | |
2224 | } else if (((rdev->family) == CHIP_RV610) || | |
2225 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
2226 | ((rdev->family) == CHIP_RS780) || |
2227 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
2228 | /* no vertex cache */ |
2229 | sq_config &= ~VC_ENABLE; | |
2230 | ||
2231 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
2232 | NUM_VS_GPRS(44) | | |
2233 | NUM_CLAUSE_TEMP_GPRS(2)); | |
2234 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
2235 | NUM_ES_GPRS(17)); | |
2236 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
2237 | NUM_VS_THREADS(78) | | |
2238 | NUM_GS_THREADS(4) | | |
2239 | NUM_ES_THREADS(31)); | |
2240 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
2241 | NUM_VS_STACK_ENTRIES(40)); | |
2242 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
2243 | NUM_ES_STACK_ENTRIES(16)); | |
2244 | } else if (((rdev->family) == CHIP_RV630) || | |
2245 | ((rdev->family) == CHIP_RV635)) { | |
2246 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
2247 | NUM_VS_GPRS(44) | | |
2248 | NUM_CLAUSE_TEMP_GPRS(2)); | |
2249 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | | |
2250 | NUM_ES_GPRS(18)); | |
2251 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
2252 | NUM_VS_THREADS(78) | | |
2253 | NUM_GS_THREADS(4) | | |
2254 | NUM_ES_THREADS(31)); | |
2255 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | | |
2256 | NUM_VS_STACK_ENTRIES(40)); | |
2257 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | | |
2258 | NUM_ES_STACK_ENTRIES(16)); | |
2259 | } else if ((rdev->family) == CHIP_RV670) { | |
2260 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | | |
2261 | NUM_VS_GPRS(44) | | |
2262 | NUM_CLAUSE_TEMP_GPRS(2)); | |
2263 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | | |
2264 | NUM_ES_GPRS(17)); | |
2265 | sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | | |
2266 | NUM_VS_THREADS(78) | | |
2267 | NUM_GS_THREADS(4) | | |
2268 | NUM_ES_THREADS(31)); | |
2269 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | | |
2270 | NUM_VS_STACK_ENTRIES(64)); | |
2271 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | | |
2272 | NUM_ES_STACK_ENTRIES(64)); | |
2273 | } | |
2274 | ||
2275 | WREG32(SQ_CONFIG, sq_config); | |
2276 | WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
2277 | WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
2278 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
2279 | WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
2280 | WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
2281 | ||
2282 | if (((rdev->family) == CHIP_RV610) || | |
2283 | ((rdev->family) == CHIP_RV620) || | |
ee59f2b4 AD |
2284 | ((rdev->family) == CHIP_RS780) || |
2285 | ((rdev->family) == CHIP_RS880)) { | |
3ce0a23d JG |
2286 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); |
2287 | } else { | |
2288 | WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); | |
2289 | } | |
2290 | ||
2291 | /* More default values. 2D/3D driver should adjust as needed */ | |
2292 | WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | | |
2293 | S1_X(0x4) | S1_Y(0xc))); | |
2294 | WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | | |
2295 | S1_X(0x2) | S1_Y(0x2) | | |
2296 | S2_X(0xa) | S2_Y(0x6) | | |
2297 | S3_X(0x6) | S3_Y(0xa))); | |
2298 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | | |
2299 | S1_X(0x4) | S1_Y(0xc) | | |
2300 | S2_X(0x1) | S2_Y(0x6) | | |
2301 | S3_X(0xa) | S3_Y(0xe))); | |
2302 | WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | | |
2303 | S5_X(0x0) | S5_Y(0x0) | | |
2304 | S6_X(0xb) | S6_Y(0x4) | | |
2305 | S7_X(0x7) | S7_Y(0x8))); | |
2306 | ||
2307 | WREG32(VGT_STRMOUT_EN, 0); | |
2308 | tmp = rdev->config.r600.max_pipes * 16; | |
2309 | switch (rdev->family) { | |
2310 | case CHIP_RV610: | |
3ce0a23d | 2311 | case CHIP_RV620: |
ee59f2b4 AD |
2312 | case CHIP_RS780: |
2313 | case CHIP_RS880: | |
3ce0a23d JG |
2314 | tmp += 32; |
2315 | break; | |
2316 | case CHIP_RV670: | |
2317 | tmp += 128; | |
2318 | break; | |
2319 | default: | |
2320 | break; | |
2321 | } | |
2322 | if (tmp > 256) { | |
2323 | tmp = 256; | |
2324 | } | |
2325 | WREG32(VGT_ES_PER_GS, 128); | |
2326 | WREG32(VGT_GS_PER_ES, tmp); | |
2327 | WREG32(VGT_GS_PER_VS, 2); | |
2328 | WREG32(VGT_GS_VERTEX_REUSE, 16); | |
2329 | ||
2330 | /* more default values. 2D/3D driver should adjust as needed */ | |
2331 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); | |
2332 | WREG32(VGT_STRMOUT_EN, 0); | |
2333 | WREG32(SX_MISC, 0); | |
2334 | WREG32(PA_SC_MODE_CNTL, 0); | |
2335 | WREG32(PA_SC_AA_CONFIG, 0); | |
2336 | WREG32(PA_SC_LINE_STIPPLE, 0); | |
2337 | WREG32(SPI_INPUT_Z, 0); | |
2338 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); | |
2339 | WREG32(CB_COLOR7_FRAG, 0); | |
2340 | ||
2341 | /* Clear render buffer base addresses */ | |
2342 | WREG32(CB_COLOR0_BASE, 0); | |
2343 | WREG32(CB_COLOR1_BASE, 0); | |
2344 | WREG32(CB_COLOR2_BASE, 0); | |
2345 | WREG32(CB_COLOR3_BASE, 0); | |
2346 | WREG32(CB_COLOR4_BASE, 0); | |
2347 | WREG32(CB_COLOR5_BASE, 0); | |
2348 | WREG32(CB_COLOR6_BASE, 0); | |
2349 | WREG32(CB_COLOR7_BASE, 0); | |
2350 | WREG32(CB_COLOR7_FRAG, 0); | |
2351 | ||
2352 | switch (rdev->family) { | |
2353 | case CHIP_RV610: | |
3ce0a23d | 2354 | case CHIP_RV620: |
ee59f2b4 AD |
2355 | case CHIP_RS780: |
2356 | case CHIP_RS880: | |
3ce0a23d JG |
2357 | tmp = TC_L2_SIZE(8); |
2358 | break; | |
2359 | case CHIP_RV630: | |
2360 | case CHIP_RV635: | |
2361 | tmp = TC_L2_SIZE(4); | |
2362 | break; | |
2363 | case CHIP_R600: | |
2364 | tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; | |
2365 | break; | |
2366 | default: | |
2367 | tmp = TC_L2_SIZE(0); | |
2368 | break; | |
2369 | } | |
2370 | WREG32(TC_CNTL, tmp); | |
2371 | ||
2372 | tmp = RREG32(HDP_HOST_PATH_CNTL); | |
2373 | WREG32(HDP_HOST_PATH_CNTL, tmp); | |
2374 | ||
2375 | tmp = RREG32(ARB_POP); | |
2376 | tmp |= ENABLE_TC128; | |
2377 | WREG32(ARB_POP, tmp); | |
2378 | ||
2379 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); | |
2380 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | | |
2381 | NUM_CLIP_SEQ(3))); | |
2382 | WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); | |
b866d133 | 2383 | WREG32(VC_ENHANCE, 0); |
3ce0a23d JG |
2384 | } |
2385 | ||
2386 | ||
771fe6b9 JG |
2387 | /* |
2388 | * Indirect registers accessor | |
2389 | */ | |
3ce0a23d JG |
2390 | u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) |
2391 | { | |
0a5b7b0b | 2392 | unsigned long flags; |
3ce0a23d JG |
2393 | u32 r; |
2394 | ||
0a5b7b0b | 2395 | spin_lock_irqsave(&rdev->pciep_idx_lock, flags); |
3ce0a23d JG |
2396 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); |
2397 | (void)RREG32(PCIE_PORT_INDEX); | |
2398 | r = RREG32(PCIE_PORT_DATA); | |
0a5b7b0b | 2399 | spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); |
3ce0a23d JG |
2400 | return r; |
2401 | } | |
2402 | ||
2403 | void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
2404 | { | |
0a5b7b0b AD |
2405 | unsigned long flags; |
2406 | ||
2407 | spin_lock_irqsave(&rdev->pciep_idx_lock, flags); | |
3ce0a23d JG |
2408 | WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); |
2409 | (void)RREG32(PCIE_PORT_INDEX); | |
2410 | WREG32(PCIE_PORT_DATA, (v)); | |
2411 | (void)RREG32(PCIE_PORT_DATA); | |
0a5b7b0b | 2412 | spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); |
3ce0a23d JG |
2413 | } |
2414 | ||
3ce0a23d JG |
2415 | /* |
2416 | * CP & Ring | |
2417 | */ | |
2418 | void r600_cp_stop(struct radeon_device *rdev) | |
2419 | { | |
50efa51a AD |
2420 | if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) |
2421 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | |
3ce0a23d | 2422 | WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); |
724c80e1 | 2423 | WREG32(SCRATCH_UMSK, 0); |
4d75658b | 2424 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
3ce0a23d JG |
2425 | } |
2426 | ||
d8f60cfc | 2427 | int r600_init_microcode(struct radeon_device *rdev) |
3ce0a23d | 2428 | { |
3ce0a23d | 2429 | const char *chip_name; |
d8f60cfc | 2430 | const char *rlc_chip_name; |
66229b20 AD |
2431 | const char *smc_chip_name = "RV770"; |
2432 | size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0; | |
3ce0a23d JG |
2433 | char fw_name[30]; |
2434 | int err; | |
2435 | ||
2436 | DRM_DEBUG("\n"); | |
2437 | ||
3ce0a23d | 2438 | switch (rdev->family) { |
d8f60cfc AD |
2439 | case CHIP_R600: |
2440 | chip_name = "R600"; | |
2441 | rlc_chip_name = "R600"; | |
2442 | break; | |
2443 | case CHIP_RV610: | |
2444 | chip_name = "RV610"; | |
2445 | rlc_chip_name = "R600"; | |
2446 | break; | |
2447 | case CHIP_RV630: | |
2448 | chip_name = "RV630"; | |
2449 | rlc_chip_name = "R600"; | |
2450 | break; | |
2451 | case CHIP_RV620: | |
2452 | chip_name = "RV620"; | |
2453 | rlc_chip_name = "R600"; | |
2454 | break; | |
2455 | case CHIP_RV635: | |
2456 | chip_name = "RV635"; | |
2457 | rlc_chip_name = "R600"; | |
2458 | break; | |
2459 | case CHIP_RV670: | |
2460 | chip_name = "RV670"; | |
2461 | rlc_chip_name = "R600"; | |
2462 | break; | |
3ce0a23d | 2463 | case CHIP_RS780: |
d8f60cfc AD |
2464 | case CHIP_RS880: |
2465 | chip_name = "RS780"; | |
2466 | rlc_chip_name = "R600"; | |
2467 | break; | |
2468 | case CHIP_RV770: | |
2469 | chip_name = "RV770"; | |
2470 | rlc_chip_name = "R700"; | |
66229b20 AD |
2471 | smc_chip_name = "RV770"; |
2472 | smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4); | |
d8f60cfc | 2473 | break; |
3ce0a23d | 2474 | case CHIP_RV730: |
d8f60cfc AD |
2475 | chip_name = "RV730"; |
2476 | rlc_chip_name = "R700"; | |
66229b20 AD |
2477 | smc_chip_name = "RV730"; |
2478 | smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4); | |
d8f60cfc AD |
2479 | break; |
2480 | case CHIP_RV710: | |
2481 | chip_name = "RV710"; | |
2482 | rlc_chip_name = "R700"; | |
66229b20 AD |
2483 | smc_chip_name = "RV710"; |
2484 | smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4); | |
2485 | break; | |
2486 | case CHIP_RV740: | |
2487 | chip_name = "RV730"; | |
2488 | rlc_chip_name = "R700"; | |
2489 | smc_chip_name = "RV740"; | |
2490 | smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4); | |
d8f60cfc | 2491 | break; |
fe251e2f AD |
2492 | case CHIP_CEDAR: |
2493 | chip_name = "CEDAR"; | |
45f9a39b | 2494 | rlc_chip_name = "CEDAR"; |
dc50ba7f AD |
2495 | smc_chip_name = "CEDAR"; |
2496 | smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4); | |
fe251e2f AD |
2497 | break; |
2498 | case CHIP_REDWOOD: | |
2499 | chip_name = "REDWOOD"; | |
45f9a39b | 2500 | rlc_chip_name = "REDWOOD"; |
dc50ba7f AD |
2501 | smc_chip_name = "REDWOOD"; |
2502 | smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4); | |
fe251e2f AD |
2503 | break; |
2504 | case CHIP_JUNIPER: | |
2505 | chip_name = "JUNIPER"; | |
45f9a39b | 2506 | rlc_chip_name = "JUNIPER"; |
dc50ba7f AD |
2507 | smc_chip_name = "JUNIPER"; |
2508 | smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4); | |
fe251e2f AD |
2509 | break; |
2510 | case CHIP_CYPRESS: | |
2511 | case CHIP_HEMLOCK: | |
2512 | chip_name = "CYPRESS"; | |
45f9a39b | 2513 | rlc_chip_name = "CYPRESS"; |
dc50ba7f AD |
2514 | smc_chip_name = "CYPRESS"; |
2515 | smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4); | |
fe251e2f | 2516 | break; |
439bd6cd AD |
2517 | case CHIP_PALM: |
2518 | chip_name = "PALM"; | |
2519 | rlc_chip_name = "SUMO"; | |
2520 | break; | |
d5c5a72f AD |
2521 | case CHIP_SUMO: |
2522 | chip_name = "SUMO"; | |
2523 | rlc_chip_name = "SUMO"; | |
2524 | break; | |
2525 | case CHIP_SUMO2: | |
2526 | chip_name = "SUMO2"; | |
2527 | rlc_chip_name = "SUMO"; | |
2528 | break; | |
3ce0a23d JG |
2529 | default: BUG(); |
2530 | } | |
2531 | ||
fe251e2f AD |
2532 | if (rdev->family >= CHIP_CEDAR) { |
2533 | pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; | |
2534 | me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; | |
45f9a39b | 2535 | rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; |
fe251e2f | 2536 | } else if (rdev->family >= CHIP_RV770) { |
3ce0a23d JG |
2537 | pfp_req_size = R700_PFP_UCODE_SIZE * 4; |
2538 | me_req_size = R700_PM4_UCODE_SIZE * 4; | |
d8f60cfc | 2539 | rlc_req_size = R700_RLC_UCODE_SIZE * 4; |
3ce0a23d | 2540 | } else { |
138e4e16 AD |
2541 | pfp_req_size = R600_PFP_UCODE_SIZE * 4; |
2542 | me_req_size = R600_PM4_UCODE_SIZE * 12; | |
2543 | rlc_req_size = R600_RLC_UCODE_SIZE * 4; | |
3ce0a23d JG |
2544 | } |
2545 | ||
d8f60cfc | 2546 | DRM_INFO("Loading %s Microcode\n", chip_name); |
3ce0a23d JG |
2547 | |
2548 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name); | |
0a168933 | 2549 | err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); |
3ce0a23d JG |
2550 | if (err) |
2551 | goto out; | |
2552 | if (rdev->pfp_fw->size != pfp_req_size) { | |
2553 | printk(KERN_ERR | |
2554 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
2555 | rdev->pfp_fw->size, fw_name); | |
2556 | err = -EINVAL; | |
2557 | goto out; | |
2558 | } | |
2559 | ||
2560 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name); | |
0a168933 | 2561 | err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); |
3ce0a23d JG |
2562 | if (err) |
2563 | goto out; | |
2564 | if (rdev->me_fw->size != me_req_size) { | |
2565 | printk(KERN_ERR | |
2566 | "r600_cp: Bogus length %zu in firmware \"%s\"\n", | |
2567 | rdev->me_fw->size, fw_name); | |
2568 | err = -EINVAL; | |
2569 | } | |
d8f60cfc AD |
2570 | |
2571 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name); | |
0a168933 | 2572 | err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); |
d8f60cfc AD |
2573 | if (err) |
2574 | goto out; | |
2575 | if (rdev->rlc_fw->size != rlc_req_size) { | |
2576 | printk(KERN_ERR | |
2577 | "r600_rlc: Bogus length %zu in firmware \"%s\"\n", | |
2578 | rdev->rlc_fw->size, fw_name); | |
2579 | err = -EINVAL; | |
2580 | } | |
2581 | ||
dc50ba7f | 2582 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { |
66229b20 | 2583 | snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name); |
0a168933 | 2584 | err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); |
8a53fa23 AD |
2585 | if (err) { |
2586 | printk(KERN_ERR | |
2587 | "smc: error loading firmware \"%s\"\n", | |
2588 | fw_name); | |
2589 | release_firmware(rdev->smc_fw); | |
2590 | rdev->smc_fw = NULL; | |
d8367112 | 2591 | err = 0; |
8a53fa23 | 2592 | } else if (rdev->smc_fw->size != smc_req_size) { |
66229b20 AD |
2593 | printk(KERN_ERR |
2594 | "smc: Bogus length %zu in firmware \"%s\"\n", | |
2595 | rdev->smc_fw->size, fw_name); | |
2596 | err = -EINVAL; | |
2597 | } | |
2598 | } | |
2599 | ||
3ce0a23d | 2600 | out: |
3ce0a23d JG |
2601 | if (err) { |
2602 | if (err != -EINVAL) | |
2603 | printk(KERN_ERR | |
2604 | "r600_cp: Failed to load firmware \"%s\"\n", | |
2605 | fw_name); | |
2606 | release_firmware(rdev->pfp_fw); | |
2607 | rdev->pfp_fw = NULL; | |
2608 | release_firmware(rdev->me_fw); | |
2609 | rdev->me_fw = NULL; | |
d8f60cfc AD |
2610 | release_firmware(rdev->rlc_fw); |
2611 | rdev->rlc_fw = NULL; | |
66229b20 AD |
2612 | release_firmware(rdev->smc_fw); |
2613 | rdev->smc_fw = NULL; | |
3ce0a23d JG |
2614 | } |
2615 | return err; | |
2616 | } | |
2617 | ||
ea31bf69 AD |
2618 | u32 r600_gfx_get_rptr(struct radeon_device *rdev, |
2619 | struct radeon_ring *ring) | |
2620 | { | |
2621 | u32 rptr; | |
2622 | ||
2623 | if (rdev->wb.enabled) | |
2624 | rptr = rdev->wb.wb[ring->rptr_offs/4]; | |
2625 | else | |
2626 | rptr = RREG32(R600_CP_RB_RPTR); | |
2627 | ||
2628 | return rptr; | |
2629 | } | |
2630 | ||
2631 | u32 r600_gfx_get_wptr(struct radeon_device *rdev, | |
2632 | struct radeon_ring *ring) | |
2633 | { | |
2634 | u32 wptr; | |
2635 | ||
2636 | wptr = RREG32(R600_CP_RB_WPTR); | |
2637 | ||
2638 | return wptr; | |
2639 | } | |
2640 | ||
2641 | void r600_gfx_set_wptr(struct radeon_device *rdev, | |
2642 | struct radeon_ring *ring) | |
2643 | { | |
2644 | WREG32(R600_CP_RB_WPTR, ring->wptr); | |
2645 | (void)RREG32(R600_CP_RB_WPTR); | |
2646 | } | |
2647 | ||
3ce0a23d JG |
2648 | static int r600_cp_load_microcode(struct radeon_device *rdev) |
2649 | { | |
2650 | const __be32 *fw_data; | |
2651 | int i; | |
2652 | ||
2653 | if (!rdev->me_fw || !rdev->pfp_fw) | |
2654 | return -EINVAL; | |
2655 | ||
2656 | r600_cp_stop(rdev); | |
2657 | ||
4eace7fd CC |
2658 | WREG32(CP_RB_CNTL, |
2659 | #ifdef __BIG_ENDIAN | |
2660 | BUF_SWAP_32BIT | | |
2661 | #endif | |
2662 | RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); | |
3ce0a23d JG |
2663 | |
2664 | /* Reset cp */ | |
2665 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
2666 | RREG32(GRBM_SOFT_RESET); | |
2667 | mdelay(15); | |
2668 | WREG32(GRBM_SOFT_RESET, 0); | |
2669 | ||
2670 | WREG32(CP_ME_RAM_WADDR, 0); | |
2671 | ||
2672 | fw_data = (const __be32 *)rdev->me_fw->data; | |
2673 | WREG32(CP_ME_RAM_WADDR, 0); | |
138e4e16 | 2674 | for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++) |
3ce0a23d JG |
2675 | WREG32(CP_ME_RAM_DATA, |
2676 | be32_to_cpup(fw_data++)); | |
2677 | ||
2678 | fw_data = (const __be32 *)rdev->pfp_fw->data; | |
2679 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
138e4e16 | 2680 | for (i = 0; i < R600_PFP_UCODE_SIZE; i++) |
3ce0a23d JG |
2681 | WREG32(CP_PFP_UCODE_DATA, |
2682 | be32_to_cpup(fw_data++)); | |
2683 | ||
2684 | WREG32(CP_PFP_UCODE_ADDR, 0); | |
2685 | WREG32(CP_ME_RAM_WADDR, 0); | |
2686 | WREG32(CP_ME_RAM_RADDR, 0); | |
2687 | return 0; | |
2688 | } | |
2689 | ||
2690 | int r600_cp_start(struct radeon_device *rdev) | |
2691 | { | |
e32eb50d | 2692 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
3ce0a23d JG |
2693 | int r; |
2694 | uint32_t cp_me; | |
2695 | ||
e32eb50d | 2696 | r = radeon_ring_lock(rdev, ring, 7); |
3ce0a23d JG |
2697 | if (r) { |
2698 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
2699 | return r; | |
2700 | } | |
e32eb50d CK |
2701 | radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); |
2702 | radeon_ring_write(ring, 0x1); | |
7e7b41d2 | 2703 | if (rdev->family >= CHIP_RV770) { |
e32eb50d CK |
2704 | radeon_ring_write(ring, 0x0); |
2705 | radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); | |
fe251e2f | 2706 | } else { |
e32eb50d CK |
2707 | radeon_ring_write(ring, 0x3); |
2708 | radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); | |
3ce0a23d | 2709 | } |
e32eb50d CK |
2710 | radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); |
2711 | radeon_ring_write(ring, 0); | |
2712 | radeon_ring_write(ring, 0); | |
1538a9e0 | 2713 | radeon_ring_unlock_commit(rdev, ring, false); |
3ce0a23d JG |
2714 | |
2715 | cp_me = 0xff; | |
2716 | WREG32(R_0086D8_CP_ME_CNTL, cp_me); | |
2717 | return 0; | |
2718 | } | |
2719 | ||
2720 | int r600_cp_resume(struct radeon_device *rdev) | |
2721 | { | |
e32eb50d | 2722 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
3ce0a23d JG |
2723 | u32 tmp; |
2724 | u32 rb_bufsz; | |
2725 | int r; | |
2726 | ||
2727 | /* Reset cp */ | |
2728 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); | |
2729 | RREG32(GRBM_SOFT_RESET); | |
2730 | mdelay(15); | |
2731 | WREG32(GRBM_SOFT_RESET, 0); | |
2732 | ||
2733 | /* Set ring buffer size */ | |
b72a8925 DV |
2734 | rb_bufsz = order_base_2(ring->ring_size / 8); |
2735 | tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; | |
3ce0a23d | 2736 | #ifdef __BIG_ENDIAN |
d6f28938 | 2737 | tmp |= BUF_SWAP_32BIT; |
3ce0a23d | 2738 | #endif |
d6f28938 | 2739 | WREG32(CP_RB_CNTL, tmp); |
15d3332f | 2740 | WREG32(CP_SEM_WAIT_TIMER, 0x0); |
3ce0a23d JG |
2741 | |
2742 | /* Set the write pointer delay */ | |
2743 | WREG32(CP_RB_WPTR_DELAY, 0); | |
2744 | ||
2745 | /* Initialize the ring buffer's read and write pointers */ | |
3ce0a23d JG |
2746 | WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); |
2747 | WREG32(CP_RB_RPTR_WR, 0); | |
e32eb50d CK |
2748 | ring->wptr = 0; |
2749 | WREG32(CP_RB_WPTR, ring->wptr); | |
724c80e1 AD |
2750 | |
2751 | /* set the wb address whether it's enabled or not */ | |
4eace7fd | 2752 | WREG32(CP_RB_RPTR_ADDR, |
4eace7fd | 2753 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
724c80e1 AD |
2754 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
2755 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); | |
2756 | ||
2757 | if (rdev->wb.enabled) | |
2758 | WREG32(SCRATCH_UMSK, 0xff); | |
2759 | else { | |
2760 | tmp |= RB_NO_UPDATE; | |
2761 | WREG32(SCRATCH_UMSK, 0); | |
2762 | } | |
2763 | ||
3ce0a23d JG |
2764 | mdelay(1); |
2765 | WREG32(CP_RB_CNTL, tmp); | |
2766 | ||
e32eb50d | 2767 | WREG32(CP_RB_BASE, ring->gpu_addr >> 8); |
3ce0a23d JG |
2768 | WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); |
2769 | ||
3ce0a23d | 2770 | r600_cp_start(rdev); |
e32eb50d | 2771 | ring->ready = true; |
f712812e | 2772 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
3ce0a23d | 2773 | if (r) { |
e32eb50d | 2774 | ring->ready = false; |
3ce0a23d JG |
2775 | return r; |
2776 | } | |
b9ace36f | 2777 | |
50efa51a | 2778 | if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) |
b9ace36f AD |
2779 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
2780 | ||
3ce0a23d JG |
2781 | return 0; |
2782 | } | |
2783 | ||
e32eb50d | 2784 | void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) |
3ce0a23d JG |
2785 | { |
2786 | u32 rb_bufsz; | |
45df6803 | 2787 | int r; |
3ce0a23d JG |
2788 | |
2789 | /* Align ring size */ | |
b72a8925 | 2790 | rb_bufsz = order_base_2(ring_size / 8); |
3ce0a23d | 2791 | ring_size = (1 << (rb_bufsz + 1)) * 4; |
e32eb50d CK |
2792 | ring->ring_size = ring_size; |
2793 | ring->align_mask = 16 - 1; | |
45df6803 | 2794 | |
89d35807 AD |
2795 | if (radeon_ring_supports_scratch_reg(rdev, ring)) { |
2796 | r = radeon_scratch_get(rdev, &ring->rptr_save_reg); | |
2797 | if (r) { | |
2798 | DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); | |
2799 | ring->rptr_save_reg = 0; | |
2800 | } | |
45df6803 | 2801 | } |
3ce0a23d JG |
2802 | } |
2803 | ||
655efd3d JG |
2804 | void r600_cp_fini(struct radeon_device *rdev) |
2805 | { | |
45df6803 | 2806 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
655efd3d | 2807 | r600_cp_stop(rdev); |
45df6803 CK |
2808 | radeon_ring_fini(rdev, ring); |
2809 | radeon_scratch_free(rdev, ring->rptr_save_reg); | |
655efd3d JG |
2810 | } |
2811 | ||
3ce0a23d JG |
2812 | /* |
2813 | * GPU scratch registers helpers function. | |
2814 | */ | |
2815 | void r600_scratch_init(struct radeon_device *rdev) | |
2816 | { | |
2817 | int i; | |
2818 | ||
2819 | rdev->scratch.num_reg = 7; | |
724c80e1 | 2820 | rdev->scratch.reg_base = SCRATCH_REG0; |
3ce0a23d JG |
2821 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
2822 | rdev->scratch.free[i] = true; | |
724c80e1 | 2823 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
3ce0a23d JG |
2824 | } |
2825 | } | |
2826 | ||
e32eb50d | 2827 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3ce0a23d JG |
2828 | { |
2829 | uint32_t scratch; | |
2830 | uint32_t tmp = 0; | |
8b25ed34 | 2831 | unsigned i; |
3ce0a23d JG |
2832 | int r; |
2833 | ||
2834 | r = radeon_scratch_get(rdev, &scratch); | |
2835 | if (r) { | |
2836 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); | |
2837 | return r; | |
2838 | } | |
2839 | WREG32(scratch, 0xCAFEDEAD); | |
e32eb50d | 2840 | r = radeon_ring_lock(rdev, ring, 3); |
3ce0a23d | 2841 | if (r) { |
8b25ed34 | 2842 | DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); |
3ce0a23d JG |
2843 | radeon_scratch_free(rdev, scratch); |
2844 | return r; | |
2845 | } | |
e32eb50d CK |
2846 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2847 | radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
2848 | radeon_ring_write(ring, 0xDEADBEEF); | |
1538a9e0 | 2849 | radeon_ring_unlock_commit(rdev, ring, false); |
3ce0a23d JG |
2850 | for (i = 0; i < rdev->usec_timeout; i++) { |
2851 | tmp = RREG32(scratch); | |
2852 | if (tmp == 0xDEADBEEF) | |
2853 | break; | |
2854 | DRM_UDELAY(1); | |
2855 | } | |
2856 | if (i < rdev->usec_timeout) { | |
8b25ed34 | 2857 | DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); |
3ce0a23d | 2858 | } else { |
bf852799 | 2859 | DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", |
8b25ed34 | 2860 | ring->idx, scratch, tmp); |
3ce0a23d JG |
2861 | r = -EINVAL; |
2862 | } | |
2863 | radeon_scratch_free(rdev, scratch); | |
2864 | return r; | |
2865 | } | |
2866 | ||
4d75658b AD |
2867 | /* |
2868 | * CP fences/semaphores | |
2869 | */ | |
2870 | ||
3ce0a23d JG |
2871 | void r600_fence_ring_emit(struct radeon_device *rdev, |
2872 | struct radeon_fence *fence) | |
2873 | { | |
e32eb50d | 2874 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
d45b964a AD |
2875 | u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | |
2876 | PACKET3_SH_ACTION_ENA; | |
2877 | ||
2878 | if (rdev->family >= CHIP_RV770) | |
2879 | cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; | |
7b1f2485 | 2880 | |
d0f8a854 | 2881 | if (rdev->wb.use_event) { |
30eb77f4 | 2882 | u64 addr = rdev->fence_drv[fence->ring].gpu_addr; |
77b1bad4 | 2883 | /* flush read cache over gart */ |
e32eb50d | 2884 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
d45b964a | 2885 | radeon_ring_write(ring, cp_coher_cntl); |
e32eb50d CK |
2886 | radeon_ring_write(ring, 0xFFFFFFFF); |
2887 | radeon_ring_write(ring, 0); | |
2888 | radeon_ring_write(ring, 10); /* poll interval */ | |
d0f8a854 | 2889 | /* EVENT_WRITE_EOP - flush caches, send int */ |
e32eb50d CK |
2890 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); |
2891 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); | |
5e167cdb | 2892 | radeon_ring_write(ring, lower_32_bits(addr)); |
e32eb50d CK |
2893 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); |
2894 | radeon_ring_write(ring, fence->seq); | |
2895 | radeon_ring_write(ring, 0); | |
d0f8a854 | 2896 | } else { |
77b1bad4 | 2897 | /* flush read cache over gart */ |
e32eb50d | 2898 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
d45b964a | 2899 | radeon_ring_write(ring, cp_coher_cntl); |
e32eb50d CK |
2900 | radeon_ring_write(ring, 0xFFFFFFFF); |
2901 | radeon_ring_write(ring, 0); | |
2902 | radeon_ring_write(ring, 10); /* poll interval */ | |
2903 | radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); | |
2904 | radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); | |
d0f8a854 | 2905 | /* wait for 3D idle clean */ |
e32eb50d CK |
2906 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2907 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2908 | radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); | |
d0f8a854 | 2909 | /* Emit fence sequence & fire IRQ */ |
e32eb50d CK |
2910 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2911 | radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
2912 | radeon_ring_write(ring, fence->seq); | |
d0f8a854 | 2913 | /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ |
e32eb50d CK |
2914 | radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); |
2915 | radeon_ring_write(ring, RB_INT_STAT); | |
d0f8a854 | 2916 | } |
3ce0a23d JG |
2917 | } |
2918 | ||
86302eea CK |
2919 | /** |
2920 | * r600_semaphore_ring_emit - emit a semaphore on the CP ring | |
2921 | * | |
2922 | * @rdev: radeon_device pointer | |
2923 | * @ring: radeon ring buffer object | |
2924 | * @semaphore: radeon semaphore object | |
2925 | * @emit_wait: Is this a sempahore wait? | |
2926 | * | |
2927 | * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP | |
2928 | * from running ahead of semaphore waits. | |
2929 | */ | |
1654b817 | 2930 | bool r600_semaphore_ring_emit(struct radeon_device *rdev, |
e32eb50d | 2931 | struct radeon_ring *ring, |
15d3332f | 2932 | struct radeon_semaphore *semaphore, |
7b1f2485 | 2933 | bool emit_wait) |
15d3332f CK |
2934 | { |
2935 | uint64_t addr = semaphore->gpu_addr; | |
2936 | unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; | |
2937 | ||
0be70439 CK |
2938 | if (rdev->family < CHIP_CAYMAN) |
2939 | sel |= PACKET3_SEM_WAIT_ON_SIGNAL; | |
2940 | ||
e32eb50d | 2941 | radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); |
5e167cdb | 2942 | radeon_ring_write(ring, lower_32_bits(addr)); |
e32eb50d | 2943 | radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); |
1654b817 | 2944 | |
b6c2b4fa AD |
2945 | /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */ |
2946 | if (emit_wait && (rdev->family >= CHIP_CEDAR)) { | |
86302eea CK |
2947 | /* Prevent the PFP from running ahead of the semaphore wait */ |
2948 | radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); | |
2949 | radeon_ring_write(ring, 0x0); | |
2950 | } | |
2951 | ||
1654b817 | 2952 | return true; |
15d3332f CK |
2953 | } |
2954 | ||
072b5acc AD |
2955 | /** |
2956 | * r600_copy_cpdma - copy pages using the CP DMA engine | |
2957 | * | |
2958 | * @rdev: radeon_device pointer | |
2959 | * @src_offset: src GPU address | |
2960 | * @dst_offset: dst GPU address | |
2961 | * @num_gpu_pages: number of GPU pages to xfer | |
2962 | * @fence: radeon fence object | |
2963 | * | |
2964 | * Copy GPU paging using the CP DMA engine (r6xx+). | |
2965 | * Used by the radeon ttm implementation to move pages if | |
2966 | * registered as the asic copy callback. | |
2967 | */ | |
57d20a43 CK |
2968 | struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, |
2969 | uint64_t src_offset, uint64_t dst_offset, | |
2970 | unsigned num_gpu_pages, | |
2971 | struct reservation_object *resv) | |
072b5acc | 2972 | { |
57d20a43 | 2973 | struct radeon_fence *fence; |
975700d2 | 2974 | struct radeon_sync sync; |
072b5acc AD |
2975 | int ring_index = rdev->asic->copy.blit_ring_index; |
2976 | struct radeon_ring *ring = &rdev->ring[ring_index]; | |
2977 | u32 size_in_bytes, cur_size_in_bytes, tmp; | |
2978 | int i, num_loops; | |
2979 | int r = 0; | |
2980 | ||
975700d2 | 2981 | radeon_sync_create(&sync); |
072b5acc AD |
2982 | |
2983 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); | |
2984 | num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); | |
745a39a9 | 2985 | r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24); |
072b5acc AD |
2986 | if (r) { |
2987 | DRM_ERROR("radeon: moving bo (%d).\n", r); | |
975700d2 | 2988 | radeon_sync_free(rdev, &sync, NULL); |
57d20a43 | 2989 | return ERR_PTR(r); |
072b5acc AD |
2990 | } |
2991 | ||
975700d2 CK |
2992 | radeon_sync_resv(rdev, &sync, resv, false); |
2993 | radeon_sync_rings(rdev, &sync, ring->idx); | |
072b5acc | 2994 | |
745a39a9 AD |
2995 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
2996 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
2997 | radeon_ring_write(ring, WAIT_3D_IDLE_bit); | |
072b5acc AD |
2998 | for (i = 0; i < num_loops; i++) { |
2999 | cur_size_in_bytes = size_in_bytes; | |
3000 | if (cur_size_in_bytes > 0x1fffff) | |
3001 | cur_size_in_bytes = 0x1fffff; | |
3002 | size_in_bytes -= cur_size_in_bytes; | |
3003 | tmp = upper_32_bits(src_offset) & 0xff; | |
3004 | if (size_in_bytes == 0) | |
3005 | tmp |= PACKET3_CP_DMA_CP_SYNC; | |
3006 | radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); | |
5e167cdb | 3007 | radeon_ring_write(ring, lower_32_bits(src_offset)); |
072b5acc | 3008 | radeon_ring_write(ring, tmp); |
5e167cdb | 3009 | radeon_ring_write(ring, lower_32_bits(dst_offset)); |
072b5acc AD |
3010 | radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); |
3011 | radeon_ring_write(ring, cur_size_in_bytes); | |
3012 | src_offset += cur_size_in_bytes; | |
3013 | dst_offset += cur_size_in_bytes; | |
3014 | } | |
3015 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | |
3016 | radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
3017 | radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit); | |
3018 | ||
57d20a43 | 3019 | r = radeon_fence_emit(rdev, &fence, ring->idx); |
072b5acc AD |
3020 | if (r) { |
3021 | radeon_ring_unlock_undo(rdev, ring); | |
975700d2 | 3022 | radeon_sync_free(rdev, &sync, NULL); |
57d20a43 | 3023 | return ERR_PTR(r); |
072b5acc AD |
3024 | } |
3025 | ||
1538a9e0 | 3026 | radeon_ring_unlock_commit(rdev, ring, false); |
975700d2 | 3027 | radeon_sync_free(rdev, &sync, fence); |
072b5acc | 3028 | |
57d20a43 | 3029 | return fence; |
072b5acc AD |
3030 | } |
3031 | ||
3ce0a23d JG |
3032 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
3033 | uint32_t tiling_flags, uint32_t pitch, | |
3034 | uint32_t offset, uint32_t obj_size) | |
3035 | { | |
3036 | /* FIXME: implement */ | |
3037 | return 0; | |
3038 | } | |
3039 | ||
3040 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg) | |
3041 | { | |
3042 | /* FIXME: implement */ | |
3043 | } | |
3044 | ||
c91f9368 JG |
3045 | static void r600_uvd_init(struct radeon_device *rdev) |
3046 | { | |
3047 | int r; | |
3048 | ||
3049 | if (!rdev->has_uvd) | |
3050 | return; | |
3051 | ||
3052 | r = radeon_uvd_init(rdev); | |
3053 | if (r) { | |
3054 | dev_err(rdev->dev, "failed UVD (%d) init.\n", r); | |
3055 | /* | |
3056 | * At this point rdev->uvd.vcpu_bo is NULL which trickles down | |
3057 | * to early fails uvd_v1_0_resume() and thus nothing happens | |
3058 | * there. So it is pointless to try to go through that code | |
3059 | * hence why we disable uvd here. | |
3060 | */ | |
3061 | rdev->has_uvd = 0; | |
3062 | return; | |
3063 | } | |
3064 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; | |
3065 | r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); | |
3066 | } | |
3067 | ||
3068 | static void r600_uvd_start(struct radeon_device *rdev) | |
3069 | { | |
3070 | int r; | |
3071 | ||
3072 | if (!rdev->has_uvd) | |
3073 | return; | |
3074 | ||
3075 | r = uvd_v1_0_resume(rdev); | |
3076 | if (r) { | |
3077 | dev_err(rdev->dev, "failed UVD resume (%d).\n", r); | |
3078 | goto error; | |
3079 | } | |
3080 | r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); | |
3081 | if (r) { | |
3082 | dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); | |
3083 | goto error; | |
3084 | } | |
3085 | return; | |
3086 | ||
3087 | error: | |
3088 | rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; | |
3089 | } | |
3090 | ||
3091 | static void r600_uvd_resume(struct radeon_device *rdev) | |
3092 | { | |
3093 | struct radeon_ring *ring; | |
3094 | int r; | |
3095 | ||
3096 | if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) | |
3097 | return; | |
3098 | ||
3099 | ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; | |
3100 | r = radeon_ring_init(rdev, ring, ring->ring_size, 0, RADEON_CP_PACKET2); | |
3101 | if (r) { | |
3102 | dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); | |
3103 | return; | |
3104 | } | |
3105 | r = uvd_v1_0_init(rdev); | |
3106 | if (r) { | |
3107 | dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); | |
3108 | return; | |
3109 | } | |
3110 | } | |
3111 | ||
1109ca09 | 3112 | static int r600_startup(struct radeon_device *rdev) |
3ce0a23d | 3113 | { |
4d75658b | 3114 | struct radeon_ring *ring; |
3ce0a23d JG |
3115 | int r; |
3116 | ||
9e46a48d AD |
3117 | /* enable pcie gen2 link */ |
3118 | r600_pcie_gen2_enable(rdev); | |
3119 | ||
e5903d39 AD |
3120 | /* scratch needs to be initialized before MC */ |
3121 | r = r600_vram_scratch_init(rdev); | |
3122 | if (r) | |
3123 | return r; | |
3124 | ||
6fab3feb AD |
3125 | r600_mc_program(rdev); |
3126 | ||
1a029b76 JG |
3127 | if (rdev->flags & RADEON_IS_AGP) { |
3128 | r600_agp_enable(rdev); | |
3129 | } else { | |
3130 | r = r600_pcie_gart_enable(rdev); | |
3131 | if (r) | |
3132 | return r; | |
3133 | } | |
3ce0a23d | 3134 | r600_gpu_init(rdev); |
b70d6bb3 | 3135 | |
724c80e1 AD |
3136 | /* allocate wb buffer */ |
3137 | r = radeon_wb_init(rdev); | |
3138 | if (r) | |
3139 | return r; | |
3140 | ||
30eb77f4 JG |
3141 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
3142 | if (r) { | |
3143 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
3144 | return r; | |
3145 | } | |
3146 | ||
c91f9368 | 3147 | r600_uvd_start(rdev); |
856754c3 | 3148 | |
d8f60cfc | 3149 | /* Enable IRQ */ |
e49f3959 AH |
3150 | if (!rdev->irq.installed) { |
3151 | r = radeon_irq_kms_init(rdev); | |
3152 | if (r) | |
3153 | return r; | |
3154 | } | |
3155 | ||
d8f60cfc AD |
3156 | r = r600_irq_init(rdev); |
3157 | if (r) { | |
3158 | DRM_ERROR("radeon: IH init failed (%d).\n", r); | |
3159 | radeon_irq_kms_fini(rdev); | |
3160 | return r; | |
3161 | } | |
3162 | r600_irq_set(rdev); | |
3163 | ||
4d75658b | 3164 | ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
e32eb50d | 3165 | r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, |
2e1e6dad | 3166 | RADEON_CP_PACKET2); |
4d75658b AD |
3167 | if (r) |
3168 | return r; | |
5596a9db | 3169 | |
3ce0a23d JG |
3170 | r = r600_cp_load_microcode(rdev); |
3171 | if (r) | |
3172 | return r; | |
3173 | r = r600_cp_resume(rdev); | |
3174 | if (r) | |
3175 | return r; | |
724c80e1 | 3176 | |
c91f9368 | 3177 | r600_uvd_resume(rdev); |
856754c3 | 3178 | |
2898c348 CK |
3179 | r = radeon_ib_pool_init(rdev); |
3180 | if (r) { | |
3181 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
b15ba512 | 3182 | return r; |
2898c348 | 3183 | } |
b15ba512 | 3184 | |
bfc1f97d | 3185 | r = radeon_audio_init(rdev); |
d4e30ef0 AD |
3186 | if (r) { |
3187 | DRM_ERROR("radeon: audio init failed\n"); | |
3188 | return r; | |
3189 | } | |
3190 | ||
3ce0a23d JG |
3191 | return 0; |
3192 | } | |
3193 | ||
28d52043 DA |
3194 | void r600_vga_set_state(struct radeon_device *rdev, bool state) |
3195 | { | |
3196 | uint32_t temp; | |
3197 | ||
3198 | temp = RREG32(CONFIG_CNTL); | |
3199 | if (state == false) { | |
3200 | temp &= ~(1<<0); | |
3201 | temp |= (1<<1); | |
3202 | } else { | |
3203 | temp &= ~(1<<1); | |
3204 | } | |
3205 | WREG32(CONFIG_CNTL, temp); | |
3206 | } | |
3207 | ||
fc30b8ef DA |
3208 | int r600_resume(struct radeon_device *rdev) |
3209 | { | |
3210 | int r; | |
3211 | ||
1a029b76 JG |
3212 | /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, |
3213 | * posting will perform necessary task to bring back GPU into good | |
3214 | * shape. | |
3215 | */ | |
fc30b8ef | 3216 | /* post card */ |
e7d40b9a | 3217 | atom_asic_init(rdev->mode_info.atom_context); |
fc30b8ef | 3218 | |
bc6a6295 AD |
3219 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
3220 | radeon_pm_resume(rdev); | |
6c7bccea | 3221 | |
b15ba512 | 3222 | rdev->accel_working = true; |
fc30b8ef DA |
3223 | r = r600_startup(rdev); |
3224 | if (r) { | |
3225 | DRM_ERROR("r600 startup failed on resume\n"); | |
6b7746e8 | 3226 | rdev->accel_working = false; |
fc30b8ef DA |
3227 | return r; |
3228 | } | |
3229 | ||
fc30b8ef DA |
3230 | return r; |
3231 | } | |
3232 | ||
3ce0a23d JG |
3233 | int r600_suspend(struct radeon_device *rdev) |
3234 | { | |
6c7bccea | 3235 | radeon_pm_suspend(rdev); |
7991d665 | 3236 | radeon_audio_fini(rdev); |
3ce0a23d | 3237 | r600_cp_stop(rdev); |
bdc99722 AD |
3238 | if (rdev->has_uvd) { |
3239 | uvd_v1_0_fini(rdev); | |
3240 | radeon_uvd_suspend(rdev); | |
3241 | } | |
0c45249f | 3242 | r600_irq_suspend(rdev); |
724c80e1 | 3243 | radeon_wb_disable(rdev); |
4aac0473 | 3244 | r600_pcie_gart_disable(rdev); |
6ddddfe7 | 3245 | |
3ce0a23d JG |
3246 | return 0; |
3247 | } | |
3248 | ||
3249 | /* Plan is to move initialization in that function and use | |
3250 | * helper function so that radeon_device_init pretty much | |
3251 | * do nothing more than calling asic specific function. This | |
3252 | * should also allow to remove a bunch of callback function | |
3253 | * like vram_info. | |
3254 | */ | |
3255 | int r600_init(struct radeon_device *rdev) | |
771fe6b9 | 3256 | { |
3ce0a23d | 3257 | int r; |
771fe6b9 | 3258 | |
3ce0a23d JG |
3259 | if (r600_debugfs_mc_info_init(rdev)) { |
3260 | DRM_ERROR("Failed to register debugfs file for mc !\n"); | |
3261 | } | |
3ce0a23d JG |
3262 | /* Read BIOS */ |
3263 | if (!radeon_get_bios(rdev)) { | |
3264 | if (ASIC_IS_AVIVO(rdev)) | |
3265 | return -EINVAL; | |
3266 | } | |
3267 | /* Must be an ATOMBIOS */ | |
e7d40b9a JG |
3268 | if (!rdev->is_atom_bios) { |
3269 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); | |
3ce0a23d | 3270 | return -EINVAL; |
e7d40b9a | 3271 | } |
3ce0a23d JG |
3272 | r = radeon_atombios_init(rdev); |
3273 | if (r) | |
3274 | return r; | |
3275 | /* Post card if necessary */ | |
fd909c37 | 3276 | if (!radeon_card_posted(rdev)) { |
72542d77 DA |
3277 | if (!rdev->bios) { |
3278 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); | |
3279 | return -EINVAL; | |
3280 | } | |
3ce0a23d JG |
3281 | DRM_INFO("GPU not posted. posting now...\n"); |
3282 | atom_asic_init(rdev->mode_info.atom_context); | |
3283 | } | |
3284 | /* Initialize scratch registers */ | |
3285 | r600_scratch_init(rdev); | |
3286 | /* Initialize surface registers */ | |
3287 | radeon_surface_init(rdev); | |
7433874e | 3288 | /* Initialize clocks */ |
5e6dde7e | 3289 | radeon_get_clock_info(rdev->ddev); |
3ce0a23d | 3290 | /* Fence driver */ |
30eb77f4 | 3291 | r = radeon_fence_driver_init(rdev); |
3ce0a23d JG |
3292 | if (r) |
3293 | return r; | |
700a0cc0 JG |
3294 | if (rdev->flags & RADEON_IS_AGP) { |
3295 | r = radeon_agp_init(rdev); | |
3296 | if (r) | |
3297 | radeon_agp_disable(rdev); | |
3298 | } | |
3ce0a23d | 3299 | r = r600_mc_init(rdev); |
b574f251 | 3300 | if (r) |
3ce0a23d | 3301 | return r; |
3ce0a23d | 3302 | /* Memory manager */ |
4c788679 | 3303 | r = radeon_bo_init(rdev); |
3ce0a23d JG |
3304 | if (r) |
3305 | return r; | |
d8f60cfc | 3306 | |
01ac8794 AD |
3307 | if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { |
3308 | r = r600_init_microcode(rdev); | |
3309 | if (r) { | |
3310 | DRM_ERROR("Failed to load firmware!\n"); | |
3311 | return r; | |
3312 | } | |
3313 | } | |
3314 | ||
6c7bccea AD |
3315 | /* Initialize power management */ |
3316 | radeon_pm_init(rdev); | |
3317 | ||
e32eb50d CK |
3318 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
3319 | r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); | |
3ce0a23d | 3320 | |
c91f9368 | 3321 | r600_uvd_init(rdev); |
856754c3 | 3322 | |
d8f60cfc AD |
3323 | rdev->ih.ring_obj = NULL; |
3324 | r600_ih_ring_init(rdev, 64 * 1024); | |
3ce0a23d | 3325 | |
4aac0473 JG |
3326 | r = r600_pcie_gart_init(rdev); |
3327 | if (r) | |
3328 | return r; | |
3329 | ||
779720a3 | 3330 | rdev->accel_working = true; |
fc30b8ef | 3331 | r = r600_startup(rdev); |
3ce0a23d | 3332 | if (r) { |
655efd3d JG |
3333 | dev_err(rdev->dev, "disabling GPU acceleration\n"); |
3334 | r600_cp_fini(rdev); | |
655efd3d | 3335 | r600_irq_fini(rdev); |
724c80e1 | 3336 | radeon_wb_fini(rdev); |
2898c348 | 3337 | radeon_ib_pool_fini(rdev); |
655efd3d | 3338 | radeon_irq_kms_fini(rdev); |
75c81298 | 3339 | r600_pcie_gart_fini(rdev); |
733289c2 | 3340 | rdev->accel_working = false; |
3ce0a23d | 3341 | } |
dafc3bd5 | 3342 | |
3ce0a23d JG |
3343 | return 0; |
3344 | } | |
3345 | ||
3346 | void r600_fini(struct radeon_device *rdev) | |
3347 | { | |
6c7bccea | 3348 | radeon_pm_fini(rdev); |
7991d665 | 3349 | radeon_audio_fini(rdev); |
655efd3d | 3350 | r600_cp_fini(rdev); |
d8f60cfc | 3351 | r600_irq_fini(rdev); |
bdc99722 AD |
3352 | if (rdev->has_uvd) { |
3353 | uvd_v1_0_fini(rdev); | |
3354 | radeon_uvd_fini(rdev); | |
3355 | } | |
724c80e1 | 3356 | radeon_wb_fini(rdev); |
2898c348 | 3357 | radeon_ib_pool_fini(rdev); |
d8f60cfc | 3358 | radeon_irq_kms_fini(rdev); |
4aac0473 | 3359 | r600_pcie_gart_fini(rdev); |
16cdf04d | 3360 | r600_vram_scratch_fini(rdev); |
655efd3d | 3361 | radeon_agp_fini(rdev); |
3ce0a23d JG |
3362 | radeon_gem_fini(rdev); |
3363 | radeon_fence_driver_fini(rdev); | |
4c788679 | 3364 | radeon_bo_fini(rdev); |
e7d40b9a | 3365 | radeon_atombios_fini(rdev); |
3ce0a23d JG |
3366 | kfree(rdev->bios); |
3367 | rdev->bios = NULL; | |
3ce0a23d JG |
3368 | } |
3369 | ||
3370 | ||
3371 | /* | |
3372 | * CS stuff | |
3373 | */ | |
3374 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
3375 | { | |
876dc9f3 | 3376 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
89d35807 | 3377 | u32 next_rptr; |
7b1f2485 | 3378 | |
45df6803 | 3379 | if (ring->rptr_save_reg) { |
89d35807 | 3380 | next_rptr = ring->wptr + 3 + 4; |
45df6803 CK |
3381 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
3382 | radeon_ring_write(ring, ((ring->rptr_save_reg - | |
3383 | PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); | |
3384 | radeon_ring_write(ring, next_rptr); | |
89d35807 AD |
3385 | } else if (rdev->wb.enabled) { |
3386 | next_rptr = ring->wptr + 5 + 4; | |
3387 | radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); | |
3388 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); | |
3389 | radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); | |
3390 | radeon_ring_write(ring, next_rptr); | |
3391 | radeon_ring_write(ring, 0); | |
45df6803 CK |
3392 | } |
3393 | ||
e32eb50d CK |
3394 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
3395 | radeon_ring_write(ring, | |
4eace7fd CC |
3396 | #ifdef __BIG_ENDIAN |
3397 | (2 << 0) | | |
3398 | #endif | |
3399 | (ib->gpu_addr & 0xFFFFFFFC)); | |
e32eb50d CK |
3400 | radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); |
3401 | radeon_ring_write(ring, ib->length_dw); | |
3ce0a23d JG |
3402 | } |
3403 | ||
f712812e | 3404 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3ce0a23d | 3405 | { |
f2e39221 | 3406 | struct radeon_ib ib; |
3ce0a23d JG |
3407 | uint32_t scratch; |
3408 | uint32_t tmp = 0; | |
3409 | unsigned i; | |
3410 | int r; | |
3411 | ||
3412 | r = radeon_scratch_get(rdev, &scratch); | |
3413 | if (r) { | |
3414 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); | |
3415 | return r; | |
3416 | } | |
3417 | WREG32(scratch, 0xCAFEDEAD); | |
4bf3dd92 | 3418 | r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); |
3ce0a23d JG |
3419 | if (r) { |
3420 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); | |
af026c5b | 3421 | goto free_scratch; |
3ce0a23d | 3422 | } |
f2e39221 JG |
3423 | ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); |
3424 | ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); | |
3425 | ib.ptr[2] = 0xDEADBEEF; | |
3426 | ib.length_dw = 3; | |
1538a9e0 | 3427 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
3ce0a23d | 3428 | if (r) { |
3ce0a23d | 3429 | DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); |
af026c5b | 3430 | goto free_ib; |
3ce0a23d | 3431 | } |
04db4caf MD |
3432 | r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies( |
3433 | RADEON_USEC_IB_TEST_TIMEOUT)); | |
3434 | if (r < 0) { | |
3ce0a23d | 3435 | DRM_ERROR("radeon: fence wait failed (%d).\n", r); |
af026c5b | 3436 | goto free_ib; |
04db4caf MD |
3437 | } else if (r == 0) { |
3438 | DRM_ERROR("radeon: fence wait timed out.\n"); | |
3439 | r = -ETIMEDOUT; | |
3440 | goto free_ib; | |
3ce0a23d | 3441 | } |
04db4caf | 3442 | r = 0; |
3ce0a23d JG |
3443 | for (i = 0; i < rdev->usec_timeout; i++) { |
3444 | tmp = RREG32(scratch); | |
3445 | if (tmp == 0xDEADBEEF) | |
3446 | break; | |
3447 | DRM_UDELAY(1); | |
3448 | } | |
3449 | if (i < rdev->usec_timeout) { | |
f2e39221 | 3450 | DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); |
3ce0a23d | 3451 | } else { |
4417d7f6 | 3452 | DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", |
3ce0a23d JG |
3453 | scratch, tmp); |
3454 | r = -EINVAL; | |
3455 | } | |
af026c5b | 3456 | free_ib: |
3ce0a23d | 3457 | radeon_ib_free(rdev, &ib); |
af026c5b MD |
3458 | free_scratch: |
3459 | radeon_scratch_free(rdev, scratch); | |
771fe6b9 JG |
3460 | return r; |
3461 | } | |
3462 | ||
d8f60cfc AD |
3463 | /* |
3464 | * Interrupts | |
3465 | * | |
3466 | * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty | |
3467 | * the same as the CP ring buffer, but in reverse. Rather than the CPU | |
3468 | * writing to the ring and the GPU consuming, the GPU writes to the ring | |
3469 | * and host consumes. As the host irq handler processes interrupts, it | |
3470 | * increments the rptr. When the rptr catches up with the wptr, all the | |
3471 | * current interrupts have been processed. | |
3472 | */ | |
3473 | ||
3474 | void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) | |
3475 | { | |
3476 | u32 rb_bufsz; | |
3477 | ||
3478 | /* Align ring size */ | |
b72a8925 | 3479 | rb_bufsz = order_base_2(ring_size / 4); |
d8f60cfc AD |
3480 | ring_size = (1 << rb_bufsz) * 4; |
3481 | rdev->ih.ring_size = ring_size; | |
0c45249f JG |
3482 | rdev->ih.ptr_mask = rdev->ih.ring_size - 1; |
3483 | rdev->ih.rptr = 0; | |
d8f60cfc AD |
3484 | } |
3485 | ||
25a857fb | 3486 | int r600_ih_ring_alloc(struct radeon_device *rdev) |
d8f60cfc AD |
3487 | { |
3488 | int r; | |
3489 | ||
d8f60cfc AD |
3490 | /* Allocate ring buffer */ |
3491 | if (rdev->ih.ring_obj == NULL) { | |
441921d5 | 3492 | r = radeon_bo_create(rdev, rdev->ih.ring_size, |
268b2510 | 3493 | PAGE_SIZE, true, |
02376d82 | 3494 | RADEON_GEM_DOMAIN_GTT, 0, |
831b6966 | 3495 | NULL, NULL, &rdev->ih.ring_obj); |
d8f60cfc AD |
3496 | if (r) { |
3497 | DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); | |
3498 | return r; | |
3499 | } | |
4c788679 JG |
3500 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
3501 | if (unlikely(r != 0)) | |
3502 | return r; | |
3503 | r = radeon_bo_pin(rdev->ih.ring_obj, | |
3504 | RADEON_GEM_DOMAIN_GTT, | |
3505 | &rdev->ih.gpu_addr); | |
d8f60cfc | 3506 | if (r) { |
4c788679 | 3507 | radeon_bo_unreserve(rdev->ih.ring_obj); |
d8f60cfc AD |
3508 | DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); |
3509 | return r; | |
3510 | } | |
4c788679 JG |
3511 | r = radeon_bo_kmap(rdev->ih.ring_obj, |
3512 | (void **)&rdev->ih.ring); | |
3513 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
d8f60cfc AD |
3514 | if (r) { |
3515 | DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); | |
3516 | return r; | |
3517 | } | |
3518 | } | |
d8f60cfc AD |
3519 | return 0; |
3520 | } | |
3521 | ||
25a857fb | 3522 | void r600_ih_ring_fini(struct radeon_device *rdev) |
d8f60cfc | 3523 | { |
4c788679 | 3524 | int r; |
d8f60cfc | 3525 | if (rdev->ih.ring_obj) { |
4c788679 JG |
3526 | r = radeon_bo_reserve(rdev->ih.ring_obj, false); |
3527 | if (likely(r == 0)) { | |
3528 | radeon_bo_kunmap(rdev->ih.ring_obj); | |
3529 | radeon_bo_unpin(rdev->ih.ring_obj); | |
3530 | radeon_bo_unreserve(rdev->ih.ring_obj); | |
3531 | } | |
3532 | radeon_bo_unref(&rdev->ih.ring_obj); | |
d8f60cfc AD |
3533 | rdev->ih.ring = NULL; |
3534 | rdev->ih.ring_obj = NULL; | |
3535 | } | |
3536 | } | |
3537 | ||
45f9a39b | 3538 | void r600_rlc_stop(struct radeon_device *rdev) |
d8f60cfc AD |
3539 | { |
3540 | ||
45f9a39b AD |
3541 | if ((rdev->family >= CHIP_RV770) && |
3542 | (rdev->family <= CHIP_RV740)) { | |
d8f60cfc AD |
3543 | /* r7xx asics need to soft reset RLC before halting */ |
3544 | WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); | |
3545 | RREG32(SRBM_SOFT_RESET); | |
4de833c3 | 3546 | mdelay(15); |
d8f60cfc AD |
3547 | WREG32(SRBM_SOFT_RESET, 0); |
3548 | RREG32(SRBM_SOFT_RESET); | |
3549 | } | |
3550 | ||
3551 | WREG32(RLC_CNTL, 0); | |
3552 | } | |
3553 | ||
3554 | static void r600_rlc_start(struct radeon_device *rdev) | |
3555 | { | |
3556 | WREG32(RLC_CNTL, RLC_ENABLE); | |
3557 | } | |
3558 | ||
2948f5e6 | 3559 | static int r600_rlc_resume(struct radeon_device *rdev) |
d8f60cfc AD |
3560 | { |
3561 | u32 i; | |
3562 | const __be32 *fw_data; | |
3563 | ||
3564 | if (!rdev->rlc_fw) | |
3565 | return -EINVAL; | |
3566 | ||
3567 | r600_rlc_stop(rdev); | |
3568 | ||
d8f60cfc | 3569 | WREG32(RLC_HB_CNTL, 0); |
c420c745 | 3570 | |
2948f5e6 AD |
3571 | WREG32(RLC_HB_BASE, 0); |
3572 | WREG32(RLC_HB_RPTR, 0); | |
3573 | WREG32(RLC_HB_WPTR, 0); | |
3574 | WREG32(RLC_HB_WPTR_LSB_ADDR, 0); | |
3575 | WREG32(RLC_HB_WPTR_MSB_ADDR, 0); | |
d8f60cfc AD |
3576 | WREG32(RLC_MC_CNTL, 0); |
3577 | WREG32(RLC_UCODE_CNTL, 0); | |
3578 | ||
3579 | fw_data = (const __be32 *)rdev->rlc_fw->data; | |
2948f5e6 | 3580 | if (rdev->family >= CHIP_RV770) { |
d8f60cfc AD |
3581 | for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { |
3582 | WREG32(RLC_UCODE_ADDR, i); | |
3583 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
3584 | } | |
3585 | } else { | |
138e4e16 | 3586 | for (i = 0; i < R600_RLC_UCODE_SIZE; i++) { |
d8f60cfc AD |
3587 | WREG32(RLC_UCODE_ADDR, i); |
3588 | WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); | |
3589 | } | |
3590 | } | |
3591 | WREG32(RLC_UCODE_ADDR, 0); | |
3592 | ||
3593 | r600_rlc_start(rdev); | |
3594 | ||
3595 | return 0; | |
3596 | } | |
3597 | ||
3598 | static void r600_enable_interrupts(struct radeon_device *rdev) | |
3599 | { | |
3600 | u32 ih_cntl = RREG32(IH_CNTL); | |
3601 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
3602 | ||
3603 | ih_cntl |= ENABLE_INTR; | |
3604 | ih_rb_cntl |= IH_RB_ENABLE; | |
3605 | WREG32(IH_CNTL, ih_cntl); | |
3606 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
3607 | rdev->ih.enabled = true; | |
3608 | } | |
3609 | ||
45f9a39b | 3610 | void r600_disable_interrupts(struct radeon_device *rdev) |
d8f60cfc AD |
3611 | { |
3612 | u32 ih_rb_cntl = RREG32(IH_RB_CNTL); | |
3613 | u32 ih_cntl = RREG32(IH_CNTL); | |
3614 | ||
3615 | ih_rb_cntl &= ~IH_RB_ENABLE; | |
3616 | ih_cntl &= ~ENABLE_INTR; | |
3617 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
3618 | WREG32(IH_CNTL, ih_cntl); | |
3619 | /* set rptr, wptr to 0 */ | |
3620 | WREG32(IH_RB_RPTR, 0); | |
3621 | WREG32(IH_RB_WPTR, 0); | |
3622 | rdev->ih.enabled = false; | |
d8f60cfc AD |
3623 | rdev->ih.rptr = 0; |
3624 | } | |
3625 | ||
e0df1ac5 AD |
3626 | static void r600_disable_interrupt_state(struct radeon_device *rdev) |
3627 | { | |
3628 | u32 tmp; | |
3629 | ||
3555e53b | 3630 | WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); |
4d75658b AD |
3631 | tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
3632 | WREG32(DMA_CNTL, tmp); | |
e0df1ac5 AD |
3633 | WREG32(GRBM_INT_CNTL, 0); |
3634 | WREG32(DxMODE_INT_MASK, 0); | |
6f34be50 AD |
3635 | WREG32(D1GRPH_INTERRUPT_CONTROL, 0); |
3636 | WREG32(D2GRPH_INTERRUPT_CONTROL, 0); | |
e0df1ac5 AD |
3637 | if (ASIC_IS_DCE3(rdev)) { |
3638 | WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); | |
3639 | WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); | |
3640 | tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3641 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
3642 | tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3643 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
3644 | tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3645 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
3646 | tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
3647 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
3648 | if (ASIC_IS_DCE32(rdev)) { | |
3649 | tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; | |
5898b1f3 | 3650 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
e0df1ac5 | 3651 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
5898b1f3 | 3652 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
c6543a6e RM |
3653 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
3654 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); | |
3655 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
3656 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); | |
f122c610 AD |
3657 | } else { |
3658 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
3659 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); | |
3660 | tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
3661 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); | |
e0df1ac5 AD |
3662 | } |
3663 | } else { | |
3664 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | |
3665 | WREG32(DACB_AUTODETECT_INT_CONTROL, 0); | |
3666 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; | |
5898b1f3 | 3667 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
e0df1ac5 | 3668 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 3669 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
e0df1ac5 | 3670 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
5898b1f3 | 3671 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
f122c610 AD |
3672 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
3673 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); | |
3674 | tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
3675 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); | |
e0df1ac5 AD |
3676 | } |
3677 | } | |
3678 | ||
d8f60cfc AD |
3679 | int r600_irq_init(struct radeon_device *rdev) |
3680 | { | |
3681 | int ret = 0; | |
3682 | int rb_bufsz; | |
3683 | u32 interrupt_cntl, ih_cntl, ih_rb_cntl; | |
3684 | ||
3685 | /* allocate ring */ | |
0c45249f | 3686 | ret = r600_ih_ring_alloc(rdev); |
d8f60cfc AD |
3687 | if (ret) |
3688 | return ret; | |
3689 | ||
3690 | /* disable irqs */ | |
3691 | r600_disable_interrupts(rdev); | |
3692 | ||
3693 | /* init rlc */ | |
2948f5e6 AD |
3694 | if (rdev->family >= CHIP_CEDAR) |
3695 | ret = evergreen_rlc_resume(rdev); | |
3696 | else | |
3697 | ret = r600_rlc_resume(rdev); | |
d8f60cfc AD |
3698 | if (ret) { |
3699 | r600_ih_ring_fini(rdev); | |
3700 | return ret; | |
3701 | } | |
3702 | ||
3703 | /* setup interrupt control */ | |
3704 | /* set dummy read address to ring address */ | |
3705 | WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); | |
3706 | interrupt_cntl = RREG32(INTERRUPT_CNTL); | |
3707 | /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi | |
3708 | * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN | |
3709 | */ | |
3710 | interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; | |
3711 | /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ | |
3712 | interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; | |
3713 | WREG32(INTERRUPT_CNTL, interrupt_cntl); | |
3714 | ||
3715 | WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); | |
b72a8925 | 3716 | rb_bufsz = order_base_2(rdev->ih.ring_size / 4); |
d8f60cfc AD |
3717 | |
3718 | ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | | |
3719 | IH_WPTR_OVERFLOW_CLEAR | | |
3720 | (rb_bufsz << 1)); | |
724c80e1 AD |
3721 | |
3722 | if (rdev->wb.enabled) | |
3723 | ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; | |
3724 | ||
3725 | /* set the writeback address whether it's enabled or not */ | |
3726 | WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); | |
3727 | WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); | |
d8f60cfc AD |
3728 | |
3729 | WREG32(IH_RB_CNTL, ih_rb_cntl); | |
3730 | ||
3731 | /* set rptr, wptr to 0 */ | |
3732 | WREG32(IH_RB_RPTR, 0); | |
3733 | WREG32(IH_RB_WPTR, 0); | |
3734 | ||
3735 | /* Default settings for IH_CNTL (disabled at first) */ | |
3736 | ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); | |
3737 | /* RPTR_REARM only works if msi's are enabled */ | |
3738 | if (rdev->msi_enabled) | |
3739 | ih_cntl |= RPTR_REARM; | |
d8f60cfc AD |
3740 | WREG32(IH_CNTL, ih_cntl); |
3741 | ||
3742 | /* force the active interrupt state to all disabled */ | |
45f9a39b AD |
3743 | if (rdev->family >= CHIP_CEDAR) |
3744 | evergreen_disable_interrupt_state(rdev); | |
3745 | else | |
3746 | r600_disable_interrupt_state(rdev); | |
d8f60cfc | 3747 | |
2099810f DA |
3748 | /* at this point everything should be setup correctly to enable master */ |
3749 | pci_set_master(rdev->pdev); | |
3750 | ||
d8f60cfc AD |
3751 | /* enable irqs */ |
3752 | r600_enable_interrupts(rdev); | |
3753 | ||
3754 | return ret; | |
3755 | } | |
3756 | ||
0c45249f | 3757 | void r600_irq_suspend(struct radeon_device *rdev) |
d8f60cfc | 3758 | { |
45f9a39b | 3759 | r600_irq_disable(rdev); |
d8f60cfc | 3760 | r600_rlc_stop(rdev); |
0c45249f JG |
3761 | } |
3762 | ||
3763 | void r600_irq_fini(struct radeon_device *rdev) | |
3764 | { | |
3765 | r600_irq_suspend(rdev); | |
d8f60cfc AD |
3766 | r600_ih_ring_fini(rdev); |
3767 | } | |
3768 | ||
3769 | int r600_irq_set(struct radeon_device *rdev) | |
3770 | { | |
e0df1ac5 AD |
3771 | u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
3772 | u32 mode_int = 0; | |
3773 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; | |
2031f77c | 3774 | u32 grbm_int_cntl = 0; |
f122c610 | 3775 | u32 hdmi0, hdmi1; |
4d75658b | 3776 | u32 dma_cntl; |
4a6369e9 | 3777 | u32 thermal_int = 0; |
d8f60cfc | 3778 | |
003e69f9 | 3779 | if (!rdev->irq.installed) { |
fce7d61b | 3780 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
003e69f9 JG |
3781 | return -EINVAL; |
3782 | } | |
d8f60cfc | 3783 | /* don't enable anything if the ih is disabled */ |
79c2bbc5 JG |
3784 | if (!rdev->ih.enabled) { |
3785 | r600_disable_interrupts(rdev); | |
3786 | /* force the active interrupt state to all disabled */ | |
3787 | r600_disable_interrupt_state(rdev); | |
d8f60cfc | 3788 | return 0; |
79c2bbc5 | 3789 | } |
d8f60cfc | 3790 | |
e0df1ac5 AD |
3791 | if (ASIC_IS_DCE3(rdev)) { |
3792 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3793 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3794 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3795 | hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3796 | if (ASIC_IS_DCE32(rdev)) { | |
3797 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3798 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
c6543a6e RM |
3799 | hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; |
3800 | hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | |
f122c610 AD |
3801 | } else { |
3802 | hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
3803 | hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
e0df1ac5 AD |
3804 | } |
3805 | } else { | |
3806 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3807 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
3808 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; | |
f122c610 AD |
3809 | hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; |
3810 | hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | |
e0df1ac5 | 3811 | } |
4a6369e9 | 3812 | |
4d75658b | 3813 | dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
e0df1ac5 | 3814 | |
4a6369e9 AD |
3815 | if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { |
3816 | thermal_int = RREG32(CG_THERMAL_INT) & | |
3817 | ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); | |
66229b20 AD |
3818 | } else if (rdev->family >= CHIP_RV770) { |
3819 | thermal_int = RREG32(RV770_CG_THERMAL_INT) & | |
3820 | ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); | |
3821 | } | |
3822 | if (rdev->irq.dpm_thermal) { | |
3823 | DRM_DEBUG("dpm thermal\n"); | |
3824 | thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; | |
4a6369e9 AD |
3825 | } |
3826 | ||
736fc37f | 3827 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
d8f60cfc AD |
3828 | DRM_DEBUG("r600_irq_set: sw int\n"); |
3829 | cp_int_cntl |= RB_INT_ENABLE; | |
d0f8a854 | 3830 | cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
d8f60cfc | 3831 | } |
4d75658b AD |
3832 | |
3833 | if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { | |
3834 | DRM_DEBUG("r600_irq_set: sw int dma\n"); | |
3835 | dma_cntl |= TRAP_ENABLE; | |
3836 | } | |
3837 | ||
6f34be50 | 3838 | if (rdev->irq.crtc_vblank_int[0] || |
736fc37f | 3839 | atomic_read(&rdev->irq.pflip[0])) { |
d8f60cfc AD |
3840 | DRM_DEBUG("r600_irq_set: vblank 0\n"); |
3841 | mode_int |= D1MODE_VBLANK_INT_MASK; | |
3842 | } | |
6f34be50 | 3843 | if (rdev->irq.crtc_vblank_int[1] || |
736fc37f | 3844 | atomic_read(&rdev->irq.pflip[1])) { |
d8f60cfc AD |
3845 | DRM_DEBUG("r600_irq_set: vblank 1\n"); |
3846 | mode_int |= D2MODE_VBLANK_INT_MASK; | |
3847 | } | |
e0df1ac5 AD |
3848 | if (rdev->irq.hpd[0]) { |
3849 | DRM_DEBUG("r600_irq_set: hpd 1\n"); | |
3850 | hpd1 |= DC_HPDx_INT_EN; | |
3851 | } | |
3852 | if (rdev->irq.hpd[1]) { | |
3853 | DRM_DEBUG("r600_irq_set: hpd 2\n"); | |
3854 | hpd2 |= DC_HPDx_INT_EN; | |
3855 | } | |
3856 | if (rdev->irq.hpd[2]) { | |
3857 | DRM_DEBUG("r600_irq_set: hpd 3\n"); | |
3858 | hpd3 |= DC_HPDx_INT_EN; | |
3859 | } | |
3860 | if (rdev->irq.hpd[3]) { | |
3861 | DRM_DEBUG("r600_irq_set: hpd 4\n"); | |
3862 | hpd4 |= DC_HPDx_INT_EN; | |
3863 | } | |
3864 | if (rdev->irq.hpd[4]) { | |
3865 | DRM_DEBUG("r600_irq_set: hpd 5\n"); | |
3866 | hpd5 |= DC_HPDx_INT_EN; | |
3867 | } | |
3868 | if (rdev->irq.hpd[5]) { | |
3869 | DRM_DEBUG("r600_irq_set: hpd 6\n"); | |
3870 | hpd6 |= DC_HPDx_INT_EN; | |
3871 | } | |
f122c610 AD |
3872 | if (rdev->irq.afmt[0]) { |
3873 | DRM_DEBUG("r600_irq_set: hdmi 0\n"); | |
3874 | hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; | |
f2594933 | 3875 | } |
f122c610 AD |
3876 | if (rdev->irq.afmt[1]) { |
3877 | DRM_DEBUG("r600_irq_set: hdmi 0\n"); | |
3878 | hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; | |
f2594933 | 3879 | } |
d8f60cfc AD |
3880 | |
3881 | WREG32(CP_INT_CNTL, cp_int_cntl); | |
4d75658b | 3882 | WREG32(DMA_CNTL, dma_cntl); |
d8f60cfc | 3883 | WREG32(DxMODE_INT_MASK, mode_int); |
f5d636d2 CK |
3884 | WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); |
3885 | WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); | |
2031f77c | 3886 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
e0df1ac5 AD |
3887 | if (ASIC_IS_DCE3(rdev)) { |
3888 | WREG32(DC_HPD1_INT_CONTROL, hpd1); | |
3889 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | |
3890 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | |
3891 | WREG32(DC_HPD4_INT_CONTROL, hpd4); | |
3892 | if (ASIC_IS_DCE32(rdev)) { | |
3893 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | |
3894 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | |
c6543a6e RM |
3895 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); |
3896 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); | |
f122c610 AD |
3897 | } else { |
3898 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); | |
3899 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); | |
e0df1ac5 AD |
3900 | } |
3901 | } else { | |
3902 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); | |
3903 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | |
3904 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); | |
f122c610 AD |
3905 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
3906 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); | |
e0df1ac5 | 3907 | } |
4a6369e9 AD |
3908 | if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { |
3909 | WREG32(CG_THERMAL_INT, thermal_int); | |
66229b20 AD |
3910 | } else if (rdev->family >= CHIP_RV770) { |
3911 | WREG32(RV770_CG_THERMAL_INT, thermal_int); | |
4a6369e9 | 3912 | } |
d8f60cfc | 3913 | |
9d1393f2 AD |
3914 | /* posting read */ |
3915 | RREG32(R_000E50_SRBM_STATUS); | |
3916 | ||
d8f60cfc AD |
3917 | return 0; |
3918 | } | |
3919 | ||
ce580fab | 3920 | static void r600_irq_ack(struct radeon_device *rdev) |
d8f60cfc | 3921 | { |
e0df1ac5 AD |
3922 | u32 tmp; |
3923 | ||
3924 | if (ASIC_IS_DCE3(rdev)) { | |
6f34be50 AD |
3925 | rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); |
3926 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); | |
3927 | rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); | |
f122c610 | 3928 | if (ASIC_IS_DCE32(rdev)) { |
c6543a6e RM |
3929 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); |
3930 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); | |
f122c610 AD |
3931 | } else { |
3932 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); | |
3933 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); | |
3934 | } | |
e0df1ac5 | 3935 | } else { |
6f34be50 AD |
3936 | rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
3937 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | |
3938 | rdev->irq.stat_regs.r600.disp_int_cont2 = 0; | |
f122c610 AD |
3939 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); |
3940 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); | |
6f34be50 AD |
3941 | } |
3942 | rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); | |
3943 | rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); | |
3944 | ||
3945 | if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) | |
3946 | WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); | |
3947 | if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) | |
3948 | WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); | |
3949 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) | |
d8f60cfc | 3950 | WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
6f34be50 | 3951 | if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) |
d8f60cfc | 3952 | WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
6f34be50 | 3953 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) |
d8f60cfc | 3954 | WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); |
6f34be50 | 3955 | if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) |
d8f60cfc | 3956 | WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); |
6f34be50 | 3957 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { |
e0df1ac5 AD |
3958 | if (ASIC_IS_DCE3(rdev)) { |
3959 | tmp = RREG32(DC_HPD1_INT_CONTROL); | |
3960 | tmp |= DC_HPDx_INT_ACK; | |
3961 | WREG32(DC_HPD1_INT_CONTROL, tmp); | |
3962 | } else { | |
3963 | tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); | |
3964 | tmp |= DC_HPDx_INT_ACK; | |
3965 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); | |
3966 | } | |
3967 | } | |
6f34be50 | 3968 | if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { |
e0df1ac5 AD |
3969 | if (ASIC_IS_DCE3(rdev)) { |
3970 | tmp = RREG32(DC_HPD2_INT_CONTROL); | |
3971 | tmp |= DC_HPDx_INT_ACK; | |
3972 | WREG32(DC_HPD2_INT_CONTROL, tmp); | |
3973 | } else { | |
3974 | tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); | |
3975 | tmp |= DC_HPDx_INT_ACK; | |
3976 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | |
3977 | } | |
3978 | } | |
6f34be50 | 3979 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { |
e0df1ac5 AD |
3980 | if (ASIC_IS_DCE3(rdev)) { |
3981 | tmp = RREG32(DC_HPD3_INT_CONTROL); | |
3982 | tmp |= DC_HPDx_INT_ACK; | |
3983 | WREG32(DC_HPD3_INT_CONTROL, tmp); | |
3984 | } else { | |
3985 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); | |
3986 | tmp |= DC_HPDx_INT_ACK; | |
3987 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | |
3988 | } | |
3989 | } | |
6f34be50 | 3990 | if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { |
e0df1ac5 AD |
3991 | tmp = RREG32(DC_HPD4_INT_CONTROL); |
3992 | tmp |= DC_HPDx_INT_ACK; | |
3993 | WREG32(DC_HPD4_INT_CONTROL, tmp); | |
3994 | } | |
3995 | if (ASIC_IS_DCE32(rdev)) { | |
6f34be50 | 3996 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { |
e0df1ac5 AD |
3997 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
3998 | tmp |= DC_HPDx_INT_ACK; | |
3999 | WREG32(DC_HPD5_INT_CONTROL, tmp); | |
4000 | } | |
6f34be50 | 4001 | if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { |
e0df1ac5 AD |
4002 | tmp = RREG32(DC_HPD5_INT_CONTROL); |
4003 | tmp |= DC_HPDx_INT_ACK; | |
4004 | WREG32(DC_HPD6_INT_CONTROL, tmp); | |
4005 | } | |
f122c610 | 4006 | if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { |
c6543a6e | 4007 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); |
f122c610 | 4008 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; |
c6543a6e | 4009 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); |
f122c610 AD |
4010 | } |
4011 | if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { | |
c6543a6e | 4012 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); |
f122c610 | 4013 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; |
c6543a6e | 4014 | WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); |
f2594933 CK |
4015 | } |
4016 | } else { | |
f122c610 AD |
4017 | if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { |
4018 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); | |
4019 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; | |
4020 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); | |
4021 | } | |
4022 | if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { | |
4023 | if (ASIC_IS_DCE3(rdev)) { | |
4024 | tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); | |
4025 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; | |
4026 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); | |
4027 | } else { | |
4028 | tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); | |
4029 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; | |
4030 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); | |
4031 | } | |
f2594933 CK |
4032 | } |
4033 | } | |
d8f60cfc AD |
4034 | } |
4035 | ||
4036 | void r600_irq_disable(struct radeon_device *rdev) | |
4037 | { | |
d8f60cfc AD |
4038 | r600_disable_interrupts(rdev); |
4039 | /* Wait and acknowledge irq */ | |
4040 | mdelay(1); | |
6f34be50 | 4041 | r600_irq_ack(rdev); |
e0df1ac5 | 4042 | r600_disable_interrupt_state(rdev); |
d8f60cfc AD |
4043 | } |
4044 | ||
ce580fab | 4045 | static u32 r600_get_ih_wptr(struct radeon_device *rdev) |
d8f60cfc AD |
4046 | { |
4047 | u32 wptr, tmp; | |
3ce0a23d | 4048 | |
724c80e1 | 4049 | if (rdev->wb.enabled) |
204ae24d | 4050 | wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); |
724c80e1 AD |
4051 | else |
4052 | wptr = RREG32(IH_RB_WPTR); | |
3ce0a23d | 4053 | |
d8f60cfc | 4054 | if (wptr & RB_OVERFLOW) { |
11bab0ae | 4055 | wptr &= ~RB_OVERFLOW; |
7924e5eb JG |
4056 | /* When a ring buffer overflow happen start parsing interrupt |
4057 | * from the last not overwritten vector (wptr + 16). Hopefully | |
4058 | * this should allow us to catchup. | |
4059 | */ | |
6cc2fda2 MD |
4060 | dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", |
4061 | wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); | |
7924e5eb | 4062 | rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; |
d8f60cfc AD |
4063 | tmp = RREG32(IH_RB_CNTL); |
4064 | tmp |= IH_WPTR_OVERFLOW_CLEAR; | |
4065 | WREG32(IH_RB_CNTL, tmp); | |
4066 | } | |
0c45249f | 4067 | return (wptr & rdev->ih.ptr_mask); |
d8f60cfc | 4068 | } |
3ce0a23d | 4069 | |
d8f60cfc AD |
4070 | /* r600 IV Ring |
4071 | * Each IV ring entry is 128 bits: | |
4072 | * [7:0] - interrupt source id | |
4073 | * [31:8] - reserved | |
4074 | * [59:32] - interrupt source data | |
4075 | * [127:60] - reserved | |
4076 | * | |
4077 | * The basic interrupt vector entries | |
4078 | * are decoded as follows: | |
4079 | * src_id src_data description | |
4080 | * 1 0 D1 Vblank | |
4081 | * 1 1 D1 Vline | |
4082 | * 5 0 D2 Vblank | |
4083 | * 5 1 D2 Vline | |
4084 | * 19 0 FP Hot plug detection A | |
4085 | * 19 1 FP Hot plug detection B | |
4086 | * 19 2 DAC A auto-detection | |
4087 | * 19 3 DAC B auto-detection | |
f2594933 CK |
4088 | * 21 4 HDMI block A |
4089 | * 21 5 HDMI block B | |
d8f60cfc AD |
4090 | * 176 - CP_INT RB |
4091 | * 177 - CP_INT IB1 | |
4092 | * 178 - CP_INT IB2 | |
4093 | * 181 - EOP Interrupt | |
4094 | * 233 - GUI Idle | |
4095 | * | |
4096 | * Note, these are based on r600 and may need to be | |
4097 | * adjusted or added to on newer asics | |
4098 | */ | |
4099 | ||
4100 | int r600_irq_process(struct radeon_device *rdev) | |
4101 | { | |
682f1a54 DA |
4102 | u32 wptr; |
4103 | u32 rptr; | |
d8f60cfc | 4104 | u32 src_id, src_data; |
6f34be50 | 4105 | u32 ring_index; |
d4877cf2 | 4106 | bool queue_hotplug = false; |
f122c610 | 4107 | bool queue_hdmi = false; |
4a6369e9 | 4108 | bool queue_thermal = false; |
d8f60cfc | 4109 | |
682f1a54 | 4110 | if (!rdev->ih.enabled || rdev->shutdown) |
79c2bbc5 | 4111 | return IRQ_NONE; |
d8f60cfc | 4112 | |
f6a56939 BH |
4113 | /* No MSIs, need a dummy read to flush PCI DMAs */ |
4114 | if (!rdev->msi_enabled) | |
4115 | RREG32(IH_RB_WPTR); | |
4116 | ||
682f1a54 | 4117 | wptr = r600_get_ih_wptr(rdev); |
d8f60cfc | 4118 | |
c20dc369 CK |
4119 | restart_ih: |
4120 | /* is somebody else already processing irqs? */ | |
4121 | if (atomic_xchg(&rdev->ih.lock, 1)) | |
d8f60cfc | 4122 | return IRQ_NONE; |
d8f60cfc | 4123 | |
c20dc369 CK |
4124 | rptr = rdev->ih.rptr; |
4125 | DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); | |
4126 | ||
964f6645 BH |
4127 | /* Order reading of wptr vs. reading of IH ring data */ |
4128 | rmb(); | |
4129 | ||
d8f60cfc | 4130 | /* display interrupts */ |
6f34be50 | 4131 | r600_irq_ack(rdev); |
d8f60cfc | 4132 | |
d8f60cfc AD |
4133 | while (rptr != wptr) { |
4134 | /* wptr/rptr are in bytes! */ | |
4135 | ring_index = rptr / 4; | |
4eace7fd CC |
4136 | src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; |
4137 | src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; | |
d8f60cfc AD |
4138 | |
4139 | switch (src_id) { | |
4140 | case 1: /* D1 vblank/vline */ | |
4141 | switch (src_data) { | |
4142 | case 0: /* D1 vblank */ | |
07f18f0b MK |
4143 | if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) |
4144 | DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); | |
4145 | ||
4146 | if (rdev->irq.crtc_vblank_int[0]) { | |
4147 | drm_handle_vblank(rdev->ddev, 0); | |
4148 | rdev->pm.vblank_sync = true; | |
4149 | wake_up(&rdev->irq.vblank_queue); | |
d8f60cfc | 4150 | } |
07f18f0b MK |
4151 | if (atomic_read(&rdev->irq.pflip[0])) |
4152 | radeon_crtc_handle_vblank(rdev, 0); | |
4153 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; | |
4154 | DRM_DEBUG("IH: D1 vblank\n"); | |
4155 | ||
d8f60cfc AD |
4156 | break; |
4157 | case 1: /* D1 vline */ | |
07f18f0b MK |
4158 | if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) |
4159 | DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); | |
4160 | ||
4161 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; | |
4162 | DRM_DEBUG("IH: D1 vline\n"); | |
4163 | ||
d8f60cfc AD |
4164 | break; |
4165 | default: | |
b042589c | 4166 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
4167 | break; |
4168 | } | |
4169 | break; | |
4170 | case 5: /* D2 vblank/vline */ | |
4171 | switch (src_data) { | |
4172 | case 0: /* D2 vblank */ | |
07f18f0b MK |
4173 | if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) |
4174 | DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); | |
4175 | ||
4176 | if (rdev->irq.crtc_vblank_int[1]) { | |
4177 | drm_handle_vblank(rdev->ddev, 1); | |
4178 | rdev->pm.vblank_sync = true; | |
4179 | wake_up(&rdev->irq.vblank_queue); | |
d8f60cfc | 4180 | } |
07f18f0b MK |
4181 | if (atomic_read(&rdev->irq.pflip[1])) |
4182 | radeon_crtc_handle_vblank(rdev, 1); | |
4183 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; | |
4184 | DRM_DEBUG("IH: D2 vblank\n"); | |
4185 | ||
d8f60cfc AD |
4186 | break; |
4187 | case 1: /* D1 vline */ | |
07f18f0b MK |
4188 | if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) |
4189 | DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); | |
4190 | ||
4191 | rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; | |
4192 | DRM_DEBUG("IH: D2 vline\n"); | |
4193 | ||
d8f60cfc AD |
4194 | break; |
4195 | default: | |
b042589c | 4196 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
4197 | break; |
4198 | } | |
4199 | break; | |
f5d636d2 CK |
4200 | case 9: /* D1 pflip */ |
4201 | DRM_DEBUG("IH: D1 flip\n"); | |
39dc5454 MK |
4202 | if (radeon_use_pflipirq > 0) |
4203 | radeon_crtc_handle_flip(rdev, 0); | |
f5d636d2 CK |
4204 | break; |
4205 | case 11: /* D2 pflip */ | |
4206 | DRM_DEBUG("IH: D2 flip\n"); | |
39dc5454 MK |
4207 | if (radeon_use_pflipirq > 0) |
4208 | radeon_crtc_handle_flip(rdev, 1); | |
f5d636d2 | 4209 | break; |
e0df1ac5 AD |
4210 | case 19: /* HPD/DAC hotplug */ |
4211 | switch (src_data) { | |
4212 | case 0: | |
07f18f0b MK |
4213 | if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) |
4214 | DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n"); | |
4215 | ||
4216 | rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; | |
4217 | queue_hotplug = true; | |
4218 | DRM_DEBUG("IH: HPD1\n"); | |
e0df1ac5 AD |
4219 | break; |
4220 | case 1: | |
07f18f0b MK |
4221 | if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) |
4222 | DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n"); | |
4223 | ||
4224 | rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; | |
4225 | queue_hotplug = true; | |
4226 | DRM_DEBUG("IH: HPD2\n"); | |
e0df1ac5 AD |
4227 | break; |
4228 | case 4: | |
07f18f0b MK |
4229 | if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) |
4230 | DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n"); | |
4231 | ||
4232 | rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; | |
4233 | queue_hotplug = true; | |
4234 | DRM_DEBUG("IH: HPD3\n"); | |
e0df1ac5 AD |
4235 | break; |
4236 | case 5: | |
07f18f0b MK |
4237 | if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) |
4238 | DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n"); | |
4239 | ||
4240 | rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; | |
4241 | queue_hotplug = true; | |
4242 | DRM_DEBUG("IH: HPD4\n"); | |
e0df1ac5 AD |
4243 | break; |
4244 | case 10: | |
07f18f0b MK |
4245 | if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) |
4246 | DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n"); | |
4247 | ||
4248 | rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; | |
4249 | queue_hotplug = true; | |
4250 | DRM_DEBUG("IH: HPD5\n"); | |
e0df1ac5 AD |
4251 | break; |
4252 | case 12: | |
07f18f0b MK |
4253 | if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) |
4254 | DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n"); | |
4255 | ||
4256 | rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; | |
4257 | queue_hotplug = true; | |
4258 | DRM_DEBUG("IH: HPD6\n"); | |
4259 | ||
e0df1ac5 AD |
4260 | break; |
4261 | default: | |
b042589c | 4262 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
e0df1ac5 AD |
4263 | break; |
4264 | } | |
4265 | break; | |
f122c610 AD |
4266 | case 21: /* hdmi */ |
4267 | switch (src_data) { | |
4268 | case 4: | |
07f18f0b MK |
4269 | if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) |
4270 | DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n"); | |
4271 | ||
4272 | rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; | |
4273 | queue_hdmi = true; | |
4274 | DRM_DEBUG("IH: HDMI0\n"); | |
4275 | ||
f122c610 AD |
4276 | break; |
4277 | case 5: | |
07f18f0b MK |
4278 | if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) |
4279 | DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n"); | |
4280 | ||
4281 | rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; | |
4282 | queue_hdmi = true; | |
4283 | DRM_DEBUG("IH: HDMI1\n"); | |
4284 | ||
f122c610 AD |
4285 | break; |
4286 | default: | |
4287 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); | |
4288 | break; | |
4289 | } | |
f2594933 | 4290 | break; |
858a41c8 AD |
4291 | case 124: /* UVD */ |
4292 | DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); | |
4293 | radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); | |
4294 | break; | |
d8f60cfc AD |
4295 | case 176: /* CP_INT in ring buffer */ |
4296 | case 177: /* CP_INT in IB1 */ | |
4297 | case 178: /* CP_INT in IB2 */ | |
4298 | DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); | |
7465280c | 4299 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
d8f60cfc AD |
4300 | break; |
4301 | case 181: /* CP EOP event */ | |
4302 | DRM_DEBUG("IH: CP EOP\n"); | |
7465280c | 4303 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
d8f60cfc | 4304 | break; |
4d75658b AD |
4305 | case 224: /* DMA trap event */ |
4306 | DRM_DEBUG("IH: DMA trap\n"); | |
4307 | radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); | |
4308 | break; | |
4a6369e9 AD |
4309 | case 230: /* thermal low to high */ |
4310 | DRM_DEBUG("IH: thermal low to high\n"); | |
4311 | rdev->pm.dpm.thermal.high_to_low = false; | |
4312 | queue_thermal = true; | |
4313 | break; | |
4314 | case 231: /* thermal high to low */ | |
4315 | DRM_DEBUG("IH: thermal high to low\n"); | |
4316 | rdev->pm.dpm.thermal.high_to_low = true; | |
4317 | queue_thermal = true; | |
4318 | break; | |
2031f77c | 4319 | case 233: /* GUI IDLE */ |
303c805c | 4320 | DRM_DEBUG("IH: GUI idle\n"); |
2031f77c | 4321 | break; |
d8f60cfc | 4322 | default: |
b042589c | 4323 | DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
d8f60cfc AD |
4324 | break; |
4325 | } | |
4326 | ||
4327 | /* wptr/rptr are in bytes! */ | |
0c45249f JG |
4328 | rptr += 16; |
4329 | rptr &= rdev->ih.ptr_mask; | |
f55e03b9 | 4330 | WREG32(IH_RB_RPTR, rptr); |
d8f60cfc | 4331 | } |
d4877cf2 | 4332 | if (queue_hotplug) |
cb5d4166 | 4333 | schedule_delayed_work(&rdev->hotplug_work, 0); |
f122c610 AD |
4334 | if (queue_hdmi) |
4335 | schedule_work(&rdev->audio_work); | |
4a6369e9 AD |
4336 | if (queue_thermal && rdev->pm.dpm_enabled) |
4337 | schedule_work(&rdev->pm.dpm.thermal.work); | |
d8f60cfc | 4338 | rdev->ih.rptr = rptr; |
c20dc369 CK |
4339 | atomic_set(&rdev->ih.lock, 0); |
4340 | ||
4341 | /* make sure wptr hasn't changed while processing */ | |
4342 | wptr = r600_get_ih_wptr(rdev); | |
4343 | if (wptr != rptr) | |
4344 | goto restart_ih; | |
4345 | ||
d8f60cfc AD |
4346 | return IRQ_HANDLED; |
4347 | } | |
3ce0a23d JG |
4348 | |
4349 | /* | |
4350 | * Debugfs info | |
4351 | */ | |
4352 | #if defined(CONFIG_DEBUG_FS) | |
4353 | ||
3ce0a23d JG |
4354 | static int r600_debugfs_mc_info(struct seq_file *m, void *data) |
4355 | { | |
4356 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
4357 | struct drm_device *dev = node->minor->dev; | |
4358 | struct radeon_device *rdev = dev->dev_private; | |
4359 | ||
4360 | DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); | |
4361 | DREG32_SYS(m, rdev, VM_L2_STATUS); | |
4362 | return 0; | |
4363 | } | |
4364 | ||
4365 | static struct drm_info_list r600_mc_info_list[] = { | |
4366 | {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, | |
3ce0a23d JG |
4367 | }; |
4368 | #endif | |
4369 | ||
4370 | int r600_debugfs_mc_info_init(struct radeon_device *rdev) | |
4371 | { | |
4372 | #if defined(CONFIG_DEBUG_FS) | |
4373 | return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); | |
4374 | #else | |
4375 | return 0; | |
4376 | #endif | |
771fe6b9 | 4377 | } |
062b389c JG |
4378 | |
4379 | /** | |
124764f1 | 4380 | * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO |
062b389c | 4381 | * rdev: radeon device structure |
062b389c | 4382 | * |
124764f1 MD |
4383 | * Some R6XX/R7XX don't seem to take into account HDP flushes performed |
4384 | * through the ring buffer. This leads to corruption in rendering, see | |
4385 | * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we | |
4386 | * directly perform the HDP flush by writing the register through MMIO. | |
062b389c | 4387 | */ |
124764f1 | 4388 | void r600_mmio_hdp_flush(struct radeon_device *rdev) |
062b389c | 4389 | { |
812d0469 | 4390 | /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read |
f3886f85 AD |
4391 | * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. |
4392 | * This seems to cause problems on some AGP cards. Just use the old | |
4393 | * method for them. | |
812d0469 | 4394 | */ |
e488459a | 4395 | if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && |
f3886f85 | 4396 | rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { |
87cbf8f2 | 4397 | void __iomem *ptr = (void *)rdev->vram_scratch.ptr; |
812d0469 AD |
4398 | u32 tmp; |
4399 | ||
4400 | WREG32(HDP_DEBUG1, 0); | |
4401 | tmp = readl((void __iomem *)ptr); | |
4402 | } else | |
4403 | WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); | |
062b389c | 4404 | } |
3313e3d4 AD |
4405 | |
4406 | void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) | |
4407 | { | |
d5445a17 | 4408 | u32 link_width_cntl, mask; |
3313e3d4 AD |
4409 | |
4410 | if (rdev->flags & RADEON_IS_IGP) | |
4411 | return; | |
4412 | ||
4413 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
4414 | return; | |
4415 | ||
4416 | /* x2 cards have a special sequence */ | |
4417 | if (ASIC_IS_X2(rdev)) | |
4418 | return; | |
4419 | ||
d5445a17 | 4420 | radeon_gui_idle(rdev); |
3313e3d4 AD |
4421 | |
4422 | switch (lanes) { | |
4423 | case 0: | |
4424 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; | |
4425 | break; | |
4426 | case 1: | |
4427 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; | |
4428 | break; | |
4429 | case 2: | |
4430 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; | |
4431 | break; | |
4432 | case 4: | |
4433 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; | |
4434 | break; | |
4435 | case 8: | |
4436 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; | |
4437 | break; | |
4438 | case 12: | |
d5445a17 | 4439 | /* not actually supported */ |
3313e3d4 AD |
4440 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; |
4441 | break; | |
4442 | case 16: | |
3313e3d4 AD |
4443 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; |
4444 | break; | |
d5445a17 AD |
4445 | default: |
4446 | DRM_ERROR("invalid pcie lane request: %d\n", lanes); | |
4447 | return; | |
3313e3d4 AD |
4448 | } |
4449 | ||
492d2b61 | 4450 | link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
d5445a17 AD |
4451 | link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK; |
4452 | link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT; | |
4453 | link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW | | |
4454 | R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); | |
3313e3d4 | 4455 | |
492d2b61 | 4456 | WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
3313e3d4 AD |
4457 | } |
4458 | ||
4459 | int r600_get_pcie_lanes(struct radeon_device *rdev) | |
4460 | { | |
4461 | u32 link_width_cntl; | |
4462 | ||
4463 | if (rdev->flags & RADEON_IS_IGP) | |
4464 | return 0; | |
4465 | ||
4466 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
4467 | return 0; | |
4468 | ||
4469 | /* x2 cards have a special sequence */ | |
4470 | if (ASIC_IS_X2(rdev)) | |
4471 | return 0; | |
4472 | ||
d5445a17 | 4473 | radeon_gui_idle(rdev); |
3313e3d4 | 4474 | |
492d2b61 | 4475 | link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
3313e3d4 AD |
4476 | |
4477 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { | |
3313e3d4 AD |
4478 | case RADEON_PCIE_LC_LINK_WIDTH_X1: |
4479 | return 1; | |
4480 | case RADEON_PCIE_LC_LINK_WIDTH_X2: | |
4481 | return 2; | |
4482 | case RADEON_PCIE_LC_LINK_WIDTH_X4: | |
4483 | return 4; | |
4484 | case RADEON_PCIE_LC_LINK_WIDTH_X8: | |
4485 | return 8; | |
d5445a17 AD |
4486 | case RADEON_PCIE_LC_LINK_WIDTH_X12: |
4487 | /* not actually supported */ | |
4488 | return 12; | |
4489 | case RADEON_PCIE_LC_LINK_WIDTH_X0: | |
3313e3d4 AD |
4490 | case RADEON_PCIE_LC_LINK_WIDTH_X16: |
4491 | default: | |
4492 | return 16; | |
4493 | } | |
4494 | } | |
4495 | ||
9e46a48d AD |
4496 | static void r600_pcie_gen2_enable(struct radeon_device *rdev) |
4497 | { | |
4498 | u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; | |
4499 | u16 link_cntl2; | |
4500 | ||
d42dd579 AD |
4501 | if (radeon_pcie_gen2 == 0) |
4502 | return; | |
4503 | ||
9e46a48d AD |
4504 | if (rdev->flags & RADEON_IS_IGP) |
4505 | return; | |
4506 | ||
4507 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
4508 | return; | |
4509 | ||
4510 | /* x2 cards have a special sequence */ | |
4511 | if (ASIC_IS_X2(rdev)) | |
4512 | return; | |
4513 | ||
4514 | /* only RV6xx+ chips are supported */ | |
4515 | if (rdev->family <= CHIP_R600) | |
4516 | return; | |
4517 | ||
7e0e4196 KSS |
4518 | if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && |
4519 | (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) | |
197bbb3d DA |
4520 | return; |
4521 | ||
492d2b61 | 4522 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
3691feea AD |
4523 | if (speed_cntl & LC_CURRENT_DATA_RATE) { |
4524 | DRM_INFO("PCIE gen 2 link speeds already enabled\n"); | |
4525 | return; | |
4526 | } | |
4527 | ||
197bbb3d DA |
4528 | DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); |
4529 | ||
9e46a48d AD |
4530 | /* 55 nm r6xx asics */ |
4531 | if ((rdev->family == CHIP_RV670) || | |
4532 | (rdev->family == CHIP_RV620) || | |
4533 | (rdev->family == CHIP_RV635)) { | |
4534 | /* advertise upconfig capability */ | |
492d2b61 | 4535 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
9e46a48d | 4536 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
492d2b61 AD |
4537 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
4538 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); | |
9e46a48d AD |
4539 | if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { |
4540 | lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; | |
4541 | link_width_cntl &= ~(LC_LINK_WIDTH_MASK | | |
4542 | LC_RECONFIG_ARC_MISSING_ESCAPE); | |
4543 | link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; | |
492d2b61 | 4544 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
9e46a48d AD |
4545 | } else { |
4546 | link_width_cntl |= LC_UPCONFIGURE_DIS; | |
492d2b61 | 4547 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
9e46a48d AD |
4548 | } |
4549 | } | |
4550 | ||
492d2b61 | 4551 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
9e46a48d AD |
4552 | if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && |
4553 | (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { | |
4554 | ||
4555 | /* 55 nm r6xx asics */ | |
4556 | if ((rdev->family == CHIP_RV670) || | |
4557 | (rdev->family == CHIP_RV620) || | |
4558 | (rdev->family == CHIP_RV635)) { | |
4559 | WREG32(MM_CFGREGS_CNTL, 0x8); | |
4560 | link_cntl2 = RREG32(0x4088); | |
4561 | WREG32(MM_CFGREGS_CNTL, 0); | |
4562 | /* not supported yet */ | |
4563 | if (link_cntl2 & SELECTABLE_DEEMPHASIS) | |
4564 | return; | |
4565 | } | |
4566 | ||
4567 | speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; | |
4568 | speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); | |
4569 | speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; | |
4570 | speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; | |
4571 | speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; | |
492d2b61 | 4572 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
9e46a48d AD |
4573 | |
4574 | tmp = RREG32(0x541c); | |
4575 | WREG32(0x541c, tmp | 0x8); | |
4576 | WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); | |
4577 | link_cntl2 = RREG16(0x4088); | |
4578 | link_cntl2 &= ~TARGET_LINK_SPEED_MASK; | |
4579 | link_cntl2 |= 0x2; | |
4580 | WREG16(0x4088, link_cntl2); | |
4581 | WREG32(MM_CFGREGS_CNTL, 0); | |
4582 | ||
4583 | if ((rdev->family == CHIP_RV670) || | |
4584 | (rdev->family == CHIP_RV620) || | |
4585 | (rdev->family == CHIP_RV635)) { | |
492d2b61 | 4586 | training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL); |
9e46a48d | 4587 | training_cntl &= ~LC_POINT_7_PLUS_EN; |
492d2b61 | 4588 | WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl); |
9e46a48d | 4589 | } else { |
492d2b61 | 4590 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
9e46a48d | 4591 | speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; |
492d2b61 | 4592 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
9e46a48d AD |
4593 | } |
4594 | ||
492d2b61 | 4595 | speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
9e46a48d | 4596 | speed_cntl |= LC_GEN2_EN_STRAP; |
492d2b61 | 4597 | WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
9e46a48d AD |
4598 | |
4599 | } else { | |
492d2b61 | 4600 | link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
9e46a48d AD |
4601 | /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ |
4602 | if (1) | |
4603 | link_width_cntl |= LC_UPCONFIGURE_DIS; | |
4604 | else | |
4605 | link_width_cntl &= ~LC_UPCONFIGURE_DIS; | |
492d2b61 | 4606 | WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
9e46a48d AD |
4607 | } |
4608 | } | |
6759a0a7 MO |
4609 | |
4610 | /** | |
d0418894 | 4611 | * r600_get_gpu_clock_counter - return GPU clock counter snapshot |
6759a0a7 MO |
4612 | * |
4613 | * @rdev: radeon_device pointer | |
4614 | * | |
4615 | * Fetches a GPU clock counter snapshot (R6xx-cayman). | |
4616 | * Returns the 64 bit clock counter snapshot. | |
4617 | */ | |
d0418894 | 4618 | uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev) |
6759a0a7 MO |
4619 | { |
4620 | uint64_t clock; | |
4621 | ||
4622 | mutex_lock(&rdev->gpu_clock_mutex); | |
4623 | WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); | |
4624 | clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | | |
3cf8bb1a | 4625 | ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); |
6759a0a7 MO |
4626 | mutex_unlock(&rdev->gpu_clock_mutex); |
4627 | return clock; | |
4628 | } |