Commit | Line | Data |
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414ed537 DA |
1 | /* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*- |
2 | * | |
3 | * Copyright (C) The Weather Channel, Inc. 2002. | |
4 | * Copyright (C) 2004 Nicolai Haehnle. | |
5 | * All Rights Reserved. | |
6 | * | |
7 | * The Weather Channel (TM) funded Tungsten Graphics to develop the | |
8 | * initial release of the Radeon 8500 driver under the XFree86 license. | |
9 | * This notice must be preserved. | |
10 | * | |
11 | * Permission is hereby granted, free of charge, to any person obtaining a | |
12 | * copy of this software and associated documentation files (the "Software"), | |
13 | * to deal in the Software without restriction, including without limitation | |
14 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
15 | * and/or sell copies of the Software, and to permit persons to whom the | |
16 | * Software is furnished to do so, subject to the following conditions: | |
17 | * | |
18 | * The above copyright notice and this permission notice (including the next | |
19 | * paragraph) shall be included in all copies or substantial portions of the | |
20 | * Software. | |
21 | * | |
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
25 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
26 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
27 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
28 | * DEALINGS IN THE SOFTWARE. | |
29 | * | |
30 | * Authors: | |
31 | * Nicolai Haehnle <prefect_@gmx.net> | |
32 | */ | |
33 | ||
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_buffer.h> | |
36 | #include <drm/radeon_drm.h> | |
414ed537 DA |
37 | #include "radeon_drv.h" |
38 | #include "r300_reg.h" | |
39 | ||
958a6f8c DM |
40 | #include <asm/unaligned.h> |
41 | ||
414ed537 DA |
42 | #define R300_SIMULTANEOUS_CLIPRECTS 4 |
43 | ||
44 | /* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects | |
45 | */ | |
46 | static const int r300_cliprect_cntl[4] = { | |
47 | 0xAAAA, | |
48 | 0xEEEE, | |
49 | 0xFEFE, | |
50 | 0xFFFE | |
51 | }; | |
52 | ||
414ed537 DA |
53 | /** |
54 | * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command | |
55 | * buffer, starting with index n. | |
56 | */ | |
d985c108 DA |
57 | static int r300_emit_cliprects(drm_radeon_private_t *dev_priv, |
58 | drm_radeon_kcmd_buffer_t *cmdbuf, int n) | |
414ed537 | 59 | { |
c60ce623 | 60 | struct drm_clip_rect box; |
414ed537 DA |
61 | int nr; |
62 | int i; | |
63 | RING_LOCALS; | |
64 | ||
65 | nr = cmdbuf->nbox - n; | |
66 | if (nr > R300_SIMULTANEOUS_CLIPRECTS) | |
67 | nr = R300_SIMULTANEOUS_CLIPRECTS; | |
68 | ||
69 | DRM_DEBUG("%i cliprects\n", nr); | |
70 | ||
71 | if (nr) { | |
b5e89ed5 DA |
72 | BEGIN_RING(6 + nr * 2); |
73 | OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); | |
414ed537 | 74 | |
b5e89ed5 DA |
75 | for (i = 0; i < nr; ++i) { |
76 | if (DRM_COPY_FROM_USER_UNCHECKED | |
77 | (&box, &cmdbuf->boxes[n + i], sizeof(box))) { | |
414ed537 | 78 | DRM_ERROR("copy cliprect faulted\n"); |
20caafa6 | 79 | return -EFAULT; |
414ed537 DA |
80 | } |
81 | ||
649ffc06 NH |
82 | box.x2--; /* Hardware expects inclusive bottom-right corner */ |
83 | box.y2--; | |
84 | ||
3d5e2c13 DA |
85 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { |
86 | box.x1 = (box.x1) & | |
87 | R300_CLIPRECT_MASK; | |
88 | box.y1 = (box.y1) & | |
89 | R300_CLIPRECT_MASK; | |
90 | box.x2 = (box.x2) & | |
91 | R300_CLIPRECT_MASK; | |
92 | box.y2 = (box.y2) & | |
93 | R300_CLIPRECT_MASK; | |
94 | } else { | |
95 | box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) & | |
96 | R300_CLIPRECT_MASK; | |
97 | box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) & | |
98 | R300_CLIPRECT_MASK; | |
99 | box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) & | |
100 | R300_CLIPRECT_MASK; | |
101 | box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) & | |
102 | R300_CLIPRECT_MASK; | |
3d5e2c13 | 103 | } |
649ffc06 | 104 | |
414ed537 | 105 | OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | |
b5e89ed5 | 106 | (box.y1 << R300_CLIPRECT_Y_SHIFT)); |
414ed537 | 107 | OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | |
b5e89ed5 | 108 | (box.y2 << R300_CLIPRECT_Y_SHIFT)); |
3d5e2c13 | 109 | |
414ed537 DA |
110 | } |
111 | ||
b5e89ed5 | 112 | OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]); |
414ed537 DA |
113 | |
114 | /* TODO/SECURITY: Force scissors to a safe value, otherwise the | |
b5e89ed5 DA |
115 | * client might be able to trample over memory. |
116 | * The impact should be very limited, but I'd rather be safe than | |
117 | * sorry. | |
118 | */ | |
119 | OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); | |
120 | OUT_RING(0); | |
121 | OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); | |
414ed537 | 122 | ADVANCE_RING(); |
b5e89ed5 | 123 | } else { |
414ed537 DA |
124 | /* Why we allow zero cliprect rendering: |
125 | * There are some commands in a command buffer that must be submitted | |
126 | * even when there are no cliprects, e.g. DMA buffer discard | |
127 | * or state setting (though state setting could be avoided by | |
128 | * simulating a loss of context). | |
129 | * | |
130 | * Now since the cmdbuf interface is so chaotic right now (and is | |
131 | * bound to remain that way for a bit until things settle down), | |
132 | * it is basically impossible to filter out the commands that are | |
133 | * necessary and those that aren't. | |
134 | * | |
135 | * So I choose the safe way and don't do any filtering at all; | |
136 | * instead, I simply set up the engine so that all rendering | |
137 | * can't produce any fragments. | |
138 | */ | |
139 | BEGIN_RING(2); | |
b5e89ed5 | 140 | OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0); |
414ed537 | 141 | ADVANCE_RING(); |
b5e89ed5 | 142 | } |
414ed537 | 143 | |
54f961a6 JG |
144 | /* flus cache and wait idle clean after cliprect change */ |
145 | BEGIN_RING(2); | |
146 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | |
147 | OUT_RING(R300_RB3D_DC_FLUSH); | |
148 | ADVANCE_RING(); | |
149 | BEGIN_RING(2); | |
150 | OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); | |
151 | OUT_RING(RADEON_WAIT_3D_IDLECLEAN); | |
152 | ADVANCE_RING(); | |
153 | /* set flush flag */ | |
154 | dev_priv->track_flush |= RADEON_FLUSH_EMITED; | |
155 | ||
414ed537 DA |
156 | return 0; |
157 | } | |
158 | ||
b3a83639 | 159 | static u8 r300_reg_flags[0x10000 >> 2]; |
414ed537 | 160 | |
3d5e2c13 | 161 | void r300_init_reg_flags(struct drm_device *dev) |
414ed537 DA |
162 | { |
163 | int i; | |
3d5e2c13 DA |
164 | drm_radeon_private_t *dev_priv = dev->dev_private; |
165 | ||
b5e89ed5 DA |
166 | memset(r300_reg_flags, 0, 0x10000 >> 2); |
167 | #define ADD_RANGE_MARK(reg, count,mark) \ | |
414ed537 DA |
168 | for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\ |
169 | r300_reg_flags[i]|=(mark); | |
b5e89ed5 DA |
170 | |
171 | #define MARK_SAFE 1 | |
172 | #define MARK_CHECK_OFFSET 2 | |
173 | ||
174 | #define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE) | |
414ed537 DA |
175 | |
176 | /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */ | |
177 | ADD_RANGE(R300_SE_VPORT_XSCALE, 6); | |
c6c656b4 | 178 | ADD_RANGE(R300_VAP_CNTL, 1); |
414ed537 DA |
179 | ADD_RANGE(R300_SE_VTE_CNTL, 2); |
180 | ADD_RANGE(0x2134, 2); | |
c6c656b4 | 181 | ADD_RANGE(R300_VAP_CNTL_STATUS, 1); |
414ed537 DA |
182 | ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2); |
183 | ADD_RANGE(0x21DC, 1); | |
c6c656b4 OM |
184 | ADD_RANGE(R300_VAP_UNKNOWN_221C, 1); |
185 | ADD_RANGE(R300_VAP_CLIP_X_0, 4); | |
54f961a6 | 186 | ADD_RANGE(R300_VAP_PVS_STATE_FLUSH_REG, 1); |
c6c656b4 | 187 | ADD_RANGE(R300_VAP_UNKNOWN_2288, 1); |
414ed537 DA |
188 | ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2); |
189 | ADD_RANGE(R300_VAP_PVS_CNTL_1, 3); | |
190 | ADD_RANGE(R300_GB_ENABLE, 1); | |
191 | ADD_RANGE(R300_GB_MSPOS0, 5); | |
54f961a6 | 192 | ADD_RANGE(R300_TX_INVALTAGS, 1); |
414ed537 DA |
193 | ADD_RANGE(R300_TX_ENABLE, 1); |
194 | ADD_RANGE(0x4200, 4); | |
195 | ADD_RANGE(0x4214, 1); | |
196 | ADD_RANGE(R300_RE_POINTSIZE, 1); | |
197 | ADD_RANGE(0x4230, 3); | |
198 | ADD_RANGE(R300_RE_LINE_CNT, 1); | |
c6c656b4 | 199 | ADD_RANGE(R300_RE_UNK4238, 1); |
414ed537 | 200 | ADD_RANGE(0x4260, 3); |
c6c656b4 OM |
201 | ADD_RANGE(R300_RE_SHADE, 4); |
202 | ADD_RANGE(R300_RE_POLYGON_MODE, 5); | |
203 | ADD_RANGE(R300_RE_ZBIAS_CNTL, 1); | |
414ed537 | 204 | ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4); |
c6c656b4 | 205 | ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1); |
414ed537 DA |
206 | ADD_RANGE(R300_RE_CULL_CNTL, 1); |
207 | ADD_RANGE(0x42C0, 2); | |
208 | ADD_RANGE(R300_RS_CNTL_0, 2); | |
c0beb2a7 | 209 | |
af7ae351 MC |
210 | ADD_RANGE(R300_SU_REG_DEST, 1); |
211 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) | |
212 | ADD_RANGE(RV530_FG_ZBREG_DEST, 1); | |
213 | ||
21efa2ba | 214 | ADD_RANGE(R300_SC_HYPERZ, 2); |
414ed537 | 215 | ADD_RANGE(0x43E8, 1); |
c0beb2a7 | 216 | |
414ed537 | 217 | ADD_RANGE(0x46A4, 5); |
c0beb2a7 | 218 | |
c6c656b4 OM |
219 | ADD_RANGE(R300_RE_FOG_STATE, 1); |
220 | ADD_RANGE(R300_FOG_COLOR_R, 3); | |
414ed537 DA |
221 | ADD_RANGE(R300_PP_ALPHA_TEST, 2); |
222 | ADD_RANGE(0x4BD8, 1); | |
223 | ADD_RANGE(R300_PFS_PARAM_0_X, 64); | |
224 | ADD_RANGE(0x4E00, 1); | |
225 | ADD_RANGE(R300_RB3D_CBLEND, 2); | |
226 | ADD_RANGE(R300_RB3D_COLORMASK, 1); | |
c6c656b4 | 227 | ADD_RANGE(R300_RB3D_BLEND_COLOR, 3); |
b5e89ed5 | 228 | ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */ |
414ed537 DA |
229 | ADD_RANGE(R300_RB3D_COLORPITCH0, 1); |
230 | ADD_RANGE(0x4E50, 9); | |
231 | ADD_RANGE(0x4E88, 1); | |
232 | ADD_RANGE(0x4EA0, 2); | |
21efa2ba DA |
233 | ADD_RANGE(R300_ZB_CNTL, 3); |
234 | ADD_RANGE(R300_ZB_FORMAT, 4); | |
235 | ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ | |
236 | ADD_RANGE(R300_ZB_DEPTHPITCH, 1); | |
237 | ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1); | |
238 | ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13); | |
af7ae351 | 239 | ADD_RANGE(R300_ZB_ZPASS_DATA, 2); /* ZB_ZPASS_DATA, ZB_ZPASS_ADDR */ |
414ed537 DA |
240 | |
241 | ADD_RANGE(R300_TX_FILTER_0, 16); | |
45f17100 | 242 | ADD_RANGE(R300_TX_FILTER1_0, 16); |
414ed537 DA |
243 | ADD_RANGE(R300_TX_SIZE_0, 16); |
244 | ADD_RANGE(R300_TX_FORMAT_0, 16); | |
d985c108 | 245 | ADD_RANGE(R300_TX_PITCH_0, 16); |
b5e89ed5 | 246 | /* Texture offset is dangerous and needs more checking */ |
414ed537 | 247 | ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET); |
45f17100 | 248 | ADD_RANGE(R300_TX_CHROMA_KEY_0, 16); |
414ed537 DA |
249 | ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); |
250 | ||
251 | /* Sporadic registers used as primitives are emitted */ | |
21efa2ba | 252 | ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1); |
414ed537 DA |
253 | ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); |
254 | ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); | |
255 | ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); | |
256 | ||
3d5e2c13 | 257 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { |
c0beb2a7 DA |
258 | ADD_RANGE(R500_VAP_INDEX_OFFSET, 1); |
259 | ADD_RANGE(R500_US_CONFIG, 2); | |
260 | ADD_RANGE(R500_US_CODE_ADDR, 3); | |
261 | ADD_RANGE(R500_US_FC_CTRL, 1); | |
262 | ADD_RANGE(R500_RS_IP_0, 16); | |
263 | ADD_RANGE(R500_RS_INST_0, 16); | |
264 | ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2); | |
265 | ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2); | |
21efa2ba | 266 | ADD_RANGE(R500_ZB_FIFO_SIZE, 2); |
c0beb2a7 DA |
267 | } else { |
268 | ADD_RANGE(R300_PFS_CNTL_0, 3); | |
269 | ADD_RANGE(R300_PFS_NODE_0, 4); | |
270 | ADD_RANGE(R300_PFS_TEXI_0, 64); | |
271 | ADD_RANGE(R300_PFS_INSTR0_0, 64); | |
272 | ADD_RANGE(R300_PFS_INSTR1_0, 64); | |
273 | ADD_RANGE(R300_PFS_INSTR2_0, 64); | |
274 | ADD_RANGE(R300_PFS_INSTR3_0, 64); | |
275 | ADD_RANGE(R300_RS_INTERP_0, 8); | |
276 | ADD_RANGE(R300_RS_ROUTE_0, 8); | |
277 | ||
3d5e2c13 | 278 | } |
414ed537 DA |
279 | } |
280 | ||
b5e89ed5 | 281 | static __inline__ int r300_check_range(unsigned reg, int count) |
414ed537 DA |
282 | { |
283 | int i; | |
b5e89ed5 DA |
284 | if (reg & ~0xffff) |
285 | return -1; | |
286 | for (i = (reg >> 2); i < (reg >> 2) + count; i++) | |
287 | if (r300_reg_flags[i] != MARK_SAFE) | |
288 | return 1; | |
414ed537 DA |
289 | return 0; |
290 | } | |
291 | ||
b5e89ed5 DA |
292 | static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t * |
293 | dev_priv, | |
b3a83639 | 294 | drm_radeon_kcmd_buffer_t |
b5e89ed5 DA |
295 | * cmdbuf, |
296 | drm_r300_cmd_header_t | |
297 | header) | |
414ed537 DA |
298 | { |
299 | int reg; | |
300 | int sz; | |
301 | int i; | |
b4fe9454 | 302 | u32 *value; |
414ed537 DA |
303 | RING_LOCALS; |
304 | ||
305 | sz = header.packet0.count; | |
306 | reg = (header.packet0.reghi << 8) | header.packet0.reglo; | |
b5e89ed5 DA |
307 | |
308 | if ((sz > 64) || (sz < 0)) { | |
b4fe9454 PN |
309 | DRM_ERROR("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", |
310 | reg, sz); | |
20caafa6 | 311 | return -EINVAL; |
b5e89ed5 | 312 | } |
b4fe9454 | 313 | |
b5e89ed5 | 314 | for (i = 0; i < sz; i++) { |
b5e89ed5 | 315 | switch (r300_reg_flags[(reg >> 2) + i]) { |
414ed537 DA |
316 | case MARK_SAFE: |
317 | break; | |
318 | case MARK_CHECK_OFFSET: | |
b4fe9454 PN |
319 | value = drm_buffer_pointer_to_dword(cmdbuf->buffer, i); |
320 | if (!radeon_check_offset(dev_priv, *value)) { | |
321 | DRM_ERROR("Offset failed range check (reg=%04x sz=%d)\n", | |
322 | reg, sz); | |
20caafa6 | 323 | return -EINVAL; |
b5e89ed5 | 324 | } |
414ed537 DA |
325 | break; |
326 | default: | |
b5e89ed5 | 327 | DRM_ERROR("Register %04x failed check as flag=%02x\n", |
b4fe9454 | 328 | reg + i * 4, r300_reg_flags[(reg >> 2) + i]); |
20caafa6 | 329 | return -EINVAL; |
414ed537 | 330 | } |
b5e89ed5 DA |
331 | } |
332 | ||
333 | BEGIN_RING(1 + sz); | |
334 | OUT_RING(CP_PACKET0(reg, sz - 1)); | |
b4fe9454 | 335 | OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz); |
414ed537 DA |
336 | ADVANCE_RING(); |
337 | ||
414ed537 DA |
338 | return 0; |
339 | } | |
340 | ||
341 | /** | |
342 | * Emits a packet0 setting arbitrary registers. | |
343 | * Called by r300_do_cp_cmdbuf. | |
344 | * | |
345 | * Note that checks are performed on contents and addresses of the registers | |
346 | */ | |
d985c108 DA |
347 | static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv, |
348 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
b5e89ed5 | 349 | drm_r300_cmd_header_t header) |
414ed537 DA |
350 | { |
351 | int reg; | |
352 | int sz; | |
353 | RING_LOCALS; | |
354 | ||
355 | sz = header.packet0.count; | |
356 | reg = (header.packet0.reghi << 8) | header.packet0.reglo; | |
357 | ||
358 | if (!sz) | |
359 | return 0; | |
360 | ||
b4fe9454 | 361 | if (sz * 4 > drm_buffer_unprocessed(cmdbuf->buffer)) |
20caafa6 | 362 | return -EINVAL; |
b5e89ed5 DA |
363 | |
364 | if (reg + sz * 4 >= 0x10000) { | |
365 | DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg, | |
366 | sz); | |
20caafa6 | 367 | return -EINVAL; |
b5e89ed5 | 368 | } |
414ed537 | 369 | |
b5e89ed5 | 370 | if (r300_check_range(reg, sz)) { |
414ed537 | 371 | /* go and check everything */ |
b5e89ed5 DA |
372 | return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf, |
373 | header); | |
374 | } | |
414ed537 DA |
375 | /* the rest of the data is safe to emit, whatever the values the user passed */ |
376 | ||
b5e89ed5 DA |
377 | BEGIN_RING(1 + sz); |
378 | OUT_RING(CP_PACKET0(reg, sz - 1)); | |
b4fe9454 | 379 | OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz); |
414ed537 DA |
380 | ADVANCE_RING(); |
381 | ||
414ed537 DA |
382 | return 0; |
383 | } | |
384 | ||
414ed537 DA |
385 | /** |
386 | * Uploads user-supplied vertex program instructions or parameters onto | |
387 | * the graphics card. | |
388 | * Called by r300_do_cp_cmdbuf. | |
389 | */ | |
d985c108 DA |
390 | static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv, |
391 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
414ed537 DA |
392 | drm_r300_cmd_header_t header) |
393 | { | |
394 | int sz; | |
395 | int addr; | |
396 | RING_LOCALS; | |
397 | ||
398 | sz = header.vpu.count; | |
399 | addr = (header.vpu.adrhi << 8) | header.vpu.adrlo; | |
400 | ||
401 | if (!sz) | |
402 | return 0; | |
b4fe9454 | 403 | if (sz * 16 > drm_buffer_unprocessed(cmdbuf->buffer)) |
20caafa6 | 404 | return -EINVAL; |
414ed537 | 405 | |
54f961a6 JG |
406 | /* VAP is very sensitive so we purge cache before we program it |
407 | * and we also flush its state before & after */ | |
408 | BEGIN_RING(6); | |
409 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | |
410 | OUT_RING(R300_RB3D_DC_FLUSH); | |
411 | OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); | |
412 | OUT_RING(RADEON_WAIT_3D_IDLECLEAN); | |
413 | OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); | |
414 | OUT_RING(0); | |
415 | ADVANCE_RING(); | |
416 | /* set flush flag */ | |
417 | dev_priv->track_flush |= RADEON_FLUSH_EMITED; | |
418 | ||
419 | BEGIN_RING(3 + sz * 4); | |
b5e89ed5 DA |
420 | OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr); |
421 | OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1)); | |
b4fe9454 | 422 | OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz * 4); |
54f961a6 | 423 | ADVANCE_RING(); |
414ed537 | 424 | |
54f961a6 JG |
425 | BEGIN_RING(2); |
426 | OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0)); | |
427 | OUT_RING(0); | |
414ed537 DA |
428 | ADVANCE_RING(); |
429 | ||
414ed537 DA |
430 | return 0; |
431 | } | |
432 | ||
414ed537 DA |
433 | /** |
434 | * Emit a clear packet from userspace. | |
435 | * Called by r300_emit_packet3. | |
436 | */ | |
d985c108 DA |
437 | static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv, |
438 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
414ed537 DA |
439 | { |
440 | RING_LOCALS; | |
441 | ||
b4fe9454 | 442 | if (8 * 4 > drm_buffer_unprocessed(cmdbuf->buffer)) |
20caafa6 | 443 | return -EINVAL; |
414ed537 DA |
444 | |
445 | BEGIN_RING(10); | |
b5e89ed5 DA |
446 | OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); |
447 | OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | | |
448 | (1 << R300_PRIM_NUM_VERTICES_SHIFT)); | |
b4fe9454 | 449 | OUT_RING_DRM_BUFFER(cmdbuf->buffer, 8); |
414ed537 DA |
450 | ADVANCE_RING(); |
451 | ||
54f961a6 JG |
452 | BEGIN_RING(4); |
453 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | |
454 | OUT_RING(R300_RB3D_DC_FLUSH); | |
455 | OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); | |
456 | OUT_RING(RADEON_WAIT_3D_IDLECLEAN); | |
457 | ADVANCE_RING(); | |
458 | /* set flush flag */ | |
459 | dev_priv->track_flush |= RADEON_FLUSH_EMITED; | |
460 | ||
414ed537 DA |
461 | return 0; |
462 | } | |
463 | ||
d985c108 DA |
464 | static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv, |
465 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
b5e89ed5 | 466 | u32 header) |
414ed537 | 467 | { |
b5e89ed5 DA |
468 | int count, i, k; |
469 | #define MAX_ARRAY_PACKET 64 | |
b4fe9454 | 470 | u32 *data; |
414ed537 DA |
471 | u32 narrays; |
472 | RING_LOCALS; | |
473 | ||
b4fe9454 | 474 | count = (header & RADEON_CP_PACKET_COUNT_MASK) >> 16; |
b5e89ed5 DA |
475 | |
476 | if ((count + 1) > MAX_ARRAY_PACKET) { | |
477 | DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", | |
478 | count); | |
20caafa6 | 479 | return -EINVAL; |
b5e89ed5 | 480 | } |
414ed537 | 481 | /* carefully check packet contents */ |
b5e89ed5 | 482 | |
b4fe9454 PN |
483 | /* We have already read the header so advance the buffer. */ |
484 | drm_buffer_advance(cmdbuf->buffer, 4); | |
485 | ||
486 | narrays = *(u32 *)drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); | |
b5e89ed5 DA |
487 | k = 0; |
488 | i = 1; | |
489 | while ((k < narrays) && (i < (count + 1))) { | |
490 | i++; /* skip attribute field */ | |
b4fe9454 PN |
491 | data = drm_buffer_pointer_to_dword(cmdbuf->buffer, i); |
492 | if (!radeon_check_offset(dev_priv, *data)) { | |
b5e89ed5 DA |
493 | DRM_ERROR |
494 | ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", | |
495 | k, i); | |
20caafa6 | 496 | return -EINVAL; |
b5e89ed5 | 497 | } |
414ed537 DA |
498 | k++; |
499 | i++; | |
b5e89ed5 DA |
500 | if (k == narrays) |
501 | break; | |
414ed537 | 502 | /* have one more to process, they come in pairs */ |
b4fe9454 PN |
503 | data = drm_buffer_pointer_to_dword(cmdbuf->buffer, i); |
504 | if (!radeon_check_offset(dev_priv, *data)) { | |
b5e89ed5 DA |
505 | DRM_ERROR |
506 | ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", | |
507 | k, i); | |
20caafa6 | 508 | return -EINVAL; |
414ed537 | 509 | } |
b5e89ed5 DA |
510 | k++; |
511 | i++; | |
512 | } | |
414ed537 | 513 | /* do the counts match what we expect ? */ |
b5e89ed5 DA |
514 | if ((k != narrays) || (i != (count + 1))) { |
515 | DRM_ERROR | |
516 | ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", | |
517 | k, i, narrays, count + 1); | |
20caafa6 | 518 | return -EINVAL; |
b5e89ed5 | 519 | } |
414ed537 DA |
520 | |
521 | /* all clear, output packet */ | |
522 | ||
b5e89ed5 | 523 | BEGIN_RING(count + 2); |
414ed537 | 524 | OUT_RING(header); |
b4fe9454 | 525 | OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 1); |
414ed537 DA |
526 | ADVANCE_RING(); |
527 | ||
414ed537 DA |
528 | return 0; |
529 | } | |
d5ea702f | 530 | |
4e5e2e25 DA |
531 | static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv, |
532 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
533 | { | |
b4fe9454 | 534 | u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); |
4e5e2e25 DA |
535 | int count, ret; |
536 | RING_LOCALS; | |
537 | ||
4e5e2e25 | 538 | |
b4fe9454 | 539 | count = (*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16; |
4e5e2e25 | 540 | |
b4fe9454 PN |
541 | if (*cmd & 0x8000) { |
542 | u32 offset; | |
543 | u32 *cmd1 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1); | |
544 | if (*cmd1 & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
4e5e2e25 | 545 | | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { |
b4fe9454 PN |
546 | |
547 | u32 *cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2); | |
548 | offset = *cmd2 << 10; | |
1d6bb8e5 | 549 | ret = !radeon_check_offset(dev_priv, offset); |
73d72cff | 550 | if (ret) { |
4e5e2e25 | 551 | DRM_ERROR("Invalid bitblt first offset is %08X\n", offset); |
20caafa6 | 552 | return -EINVAL; |
4e5e2e25 DA |
553 | } |
554 | } | |
555 | ||
b4fe9454 PN |
556 | if ((*cmd1 & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && |
557 | (*cmd1 & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { | |
558 | u32 *cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3); | |
559 | offset = *cmd3 << 10; | |
1d6bb8e5 | 560 | ret = !radeon_check_offset(dev_priv, offset); |
73d72cff | 561 | if (ret) { |
4e5e2e25 | 562 | DRM_ERROR("Invalid bitblt second offset is %08X\n", offset); |
20caafa6 | 563 | return -EINVAL; |
4e5e2e25 | 564 | } |
bc5f4523 | 565 | |
4e5e2e25 DA |
566 | } |
567 | } | |
568 | ||
569 | BEGIN_RING(count+2); | |
b4fe9454 | 570 | OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 2); |
4e5e2e25 DA |
571 | ADVANCE_RING(); |
572 | ||
4e5e2e25 DA |
573 | return 0; |
574 | } | |
414ed537 | 575 | |
e2898c5f NH |
576 | static __inline__ int r300_emit_draw_indx_2(drm_radeon_private_t *dev_priv, |
577 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
a1aa2897 | 578 | { |
b4fe9454 PN |
579 | u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); |
580 | u32 *cmd1 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1); | |
e2898c5f NH |
581 | int count; |
582 | int expected_count; | |
a1aa2897 RS |
583 | RING_LOCALS; |
584 | ||
b4fe9454 PN |
585 | count = (*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16; |
586 | ||
587 | expected_count = *cmd1 >> 16; | |
588 | if (!(*cmd1 & R300_VAP_VF_CNTL__INDEX_SIZE_32bit)) | |
e2898c5f | 589 | expected_count = (expected_count+1)/2; |
a1aa2897 | 590 | |
e2898c5f NH |
591 | if (count && count != expected_count) { |
592 | DRM_ERROR("3D_DRAW_INDX_2: packet size %i, expected %i\n", | |
593 | count, expected_count); | |
20caafa6 | 594 | return -EINVAL; |
a1aa2897 RS |
595 | } |
596 | ||
597 | BEGIN_RING(count+2); | |
b4fe9454 | 598 | OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 2); |
a1aa2897 RS |
599 | ADVANCE_RING(); |
600 | ||
e2898c5f | 601 | if (!count) { |
b4fe9454 PN |
602 | drm_r300_cmd_header_t stack_header, *header; |
603 | u32 *cmd1, *cmd2, *cmd3; | |
e2898c5f | 604 | |
b4fe9454 PN |
605 | if (drm_buffer_unprocessed(cmdbuf->buffer) |
606 | < 4*4 + sizeof(stack_header)) { | |
e2898c5f NH |
607 | DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER, but stream is too short.\n"); |
608 | return -EINVAL; | |
609 | } | |
610 | ||
b4fe9454 PN |
611 | header = drm_buffer_read_object(cmdbuf->buffer, |
612 | sizeof(stack_header), &stack_header); | |
e2898c5f | 613 | |
b4fe9454 PN |
614 | cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); |
615 | cmd1 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1); | |
616 | cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2); | |
617 | cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3); | |
e2898c5f | 618 | |
b4fe9454 PN |
619 | if (header->header.cmd_type != R300_CMD_PACKET3 || |
620 | header->packet3.packet != R300_CMD_PACKET3_RAW || | |
621 | *cmd != CP_PACKET3(RADEON_CP_INDX_BUFFER, 2)) { | |
e2898c5f NH |
622 | DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER.\n"); |
623 | return -EINVAL; | |
624 | } | |
625 | ||
b4fe9454 PN |
626 | if ((*cmd1 & 0x8000ffff) != 0x80000810) { |
627 | DRM_ERROR("Invalid indx_buffer reg address %08X\n", | |
628 | *cmd1); | |
e2898c5f NH |
629 | return -EINVAL; |
630 | } | |
b4fe9454 PN |
631 | if (!radeon_check_offset(dev_priv, *cmd2)) { |
632 | DRM_ERROR("Invalid indx_buffer offset is %08X\n", | |
633 | *cmd2); | |
e2898c5f NH |
634 | return -EINVAL; |
635 | } | |
b4fe9454 | 636 | if (*cmd3 != expected_count) { |
e2898c5f | 637 | DRM_ERROR("INDX_BUFFER: buffer size %i, expected %i\n", |
b4fe9454 | 638 | *cmd3, expected_count); |
e2898c5f NH |
639 | return -EINVAL; |
640 | } | |
641 | ||
642 | BEGIN_RING(4); | |
b4fe9454 | 643 | OUT_RING_DRM_BUFFER(cmdbuf->buffer, 4); |
e2898c5f | 644 | ADVANCE_RING(); |
e2898c5f NH |
645 | } |
646 | ||
a1aa2897 RS |
647 | return 0; |
648 | } | |
649 | ||
d985c108 DA |
650 | static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv, |
651 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
414ed537 | 652 | { |
b4fe9454 | 653 | u32 *header; |
414ed537 DA |
654 | int count; |
655 | RING_LOCALS; | |
656 | ||
b4fe9454 | 657 | if (4 > drm_buffer_unprocessed(cmdbuf->buffer)) |
20caafa6 | 658 | return -EINVAL; |
414ed537 | 659 | |
b5e89ed5 | 660 | /* Fixme !! This simply emits a packet without much checking. |
414ed537 DA |
661 | We need to be smarter. */ |
662 | ||
663 | /* obtain first word - actual packet3 header */ | |
b4fe9454 | 664 | header = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); |
414ed537 DA |
665 | |
666 | /* Is it packet 3 ? */ | |
b4fe9454 PN |
667 | if ((*header >> 30) != 0x3) { |
668 | DRM_ERROR("Not a packet3 header (0x%08x)\n", *header); | |
20caafa6 | 669 | return -EINVAL; |
b5e89ed5 | 670 | } |
414ed537 | 671 | |
b4fe9454 | 672 | count = (*header >> 16) & 0x3fff; |
414ed537 DA |
673 | |
674 | /* Check again now that we know how much data to expect */ | |
b4fe9454 | 675 | if ((count + 2) * 4 > drm_buffer_unprocessed(cmdbuf->buffer)) { |
b5e89ed5 DA |
676 | DRM_ERROR |
677 | ("Expected packet3 of length %d but have only %d bytes left\n", | |
b4fe9454 | 678 | (count + 2) * 4, drm_buffer_unprocessed(cmdbuf->buffer)); |
20caafa6 | 679 | return -EINVAL; |
b5e89ed5 | 680 | } |
414ed537 DA |
681 | |
682 | /* Is it a packet type we know about ? */ | |
b4fe9454 | 683 | switch (*header & 0xff00) { |
b5e89ed5 | 684 | case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */ |
b4fe9454 | 685 | return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, *header); |
414ed537 | 686 | |
4e5e2e25 DA |
687 | case RADEON_CNTL_BITBLT_MULTI: |
688 | return r300_emit_bitblt_multi(dev_priv, cmdbuf); | |
689 | ||
54f961a6 | 690 | case RADEON_CP_INDX_BUFFER: |
e2898c5f NH |
691 | DRM_ERROR("packet3 INDX_BUFFER without preceding 3D_DRAW_INDX_2 is illegal.\n"); |
692 | return -EINVAL; | |
54f961a6 JG |
693 | case RADEON_CP_3D_DRAW_IMMD_2: |
694 | /* triggers drawing using in-packet vertex data */ | |
695 | case RADEON_CP_3D_DRAW_VBUF_2: | |
696 | /* triggers drawing of vertex buffers setup elsewhere */ | |
e2898c5f NH |
697 | dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED | |
698 | RADEON_PURGE_EMITED); | |
699 | break; | |
54f961a6 JG |
700 | case RADEON_CP_3D_DRAW_INDX_2: |
701 | /* triggers drawing using indices to vertex buffer */ | |
702 | /* whenever we send vertex we clear flush & purge */ | |
703 | dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED | | |
704 | RADEON_PURGE_EMITED); | |
e2898c5f | 705 | return r300_emit_draw_indx_2(dev_priv, cmdbuf); |
414ed537 DA |
706 | case RADEON_WAIT_FOR_IDLE: |
707 | case RADEON_CP_NOP: | |
708 | /* these packets are safe */ | |
709 | break; | |
710 | default: | |
b4fe9454 | 711 | DRM_ERROR("Unknown packet3 header (0x%08x)\n", *header); |
20caafa6 | 712 | return -EINVAL; |
b5e89ed5 | 713 | } |
414ed537 | 714 | |
b5e89ed5 | 715 | BEGIN_RING(count + 2); |
b4fe9454 | 716 | OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 2); |
414ed537 DA |
717 | ADVANCE_RING(); |
718 | ||
414ed537 DA |
719 | return 0; |
720 | } | |
721 | ||
414ed537 DA |
722 | /** |
723 | * Emit a rendering packet3 from userspace. | |
724 | * Called by r300_do_cp_cmdbuf. | |
725 | */ | |
d985c108 DA |
726 | static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv, |
727 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
414ed537 DA |
728 | drm_r300_cmd_header_t header) |
729 | { | |
730 | int n; | |
731 | int ret; | |
b4fe9454 | 732 | int orig_iter = cmdbuf->buffer->iterator; |
414ed537 DA |
733 | |
734 | /* This is a do-while-loop so that we run the interior at least once, | |
735 | * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale. | |
736 | */ | |
737 | n = 0; | |
738 | do { | |
739 | if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) { | |
740 | ret = r300_emit_cliprects(dev_priv, cmdbuf, n); | |
741 | if (ret) | |
742 | return ret; | |
743 | ||
b4fe9454 | 744 | cmdbuf->buffer->iterator = orig_iter; |
b5e89ed5 | 745 | } |
414ed537 | 746 | |
b5e89ed5 | 747 | switch (header.packet3.packet) { |
414ed537 DA |
748 | case R300_CMD_PACKET3_CLEAR: |
749 | DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n"); | |
750 | ret = r300_emit_clear(dev_priv, cmdbuf); | |
751 | if (ret) { | |
752 | DRM_ERROR("r300_emit_clear failed\n"); | |
753 | return ret; | |
b5e89ed5 | 754 | } |
414ed537 DA |
755 | break; |
756 | ||
757 | case R300_CMD_PACKET3_RAW: | |
758 | DRM_DEBUG("R300_CMD_PACKET3_RAW\n"); | |
759 | ret = r300_emit_raw_packet3(dev_priv, cmdbuf); | |
760 | if (ret) { | |
761 | DRM_ERROR("r300_emit_raw_packet3 failed\n"); | |
762 | return ret; | |
b5e89ed5 | 763 | } |
414ed537 DA |
764 | break; |
765 | ||
766 | default: | |
b4fe9454 | 767 | DRM_ERROR("bad packet3 type %i at byte %d\n", |
b5e89ed5 | 768 | header.packet3.packet, |
55a5cb5d | 769 | cmdbuf->buffer->iterator - (int)sizeof(header)); |
20caafa6 | 770 | return -EINVAL; |
b5e89ed5 | 771 | } |
414ed537 DA |
772 | |
773 | n += R300_SIMULTANEOUS_CLIPRECTS; | |
b5e89ed5 | 774 | } while (n < cmdbuf->nbox); |
414ed537 DA |
775 | |
776 | return 0; | |
777 | } | |
778 | ||
779 | /* Some of the R300 chips seem to be extremely touchy about the two registers | |
780 | * that are configured in r300_pacify. | |
781 | * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace | |
782 | * sends a command buffer that contains only state setting commands and a | |
783 | * vertex program/parameter upload sequence, this will eventually lead to a | |
784 | * lockup, unless the sequence is bracketed by calls to r300_pacify. | |
785 | * So we should take great care to *always* call r300_pacify before | |
786 | * *anything* 3D related, and again afterwards. This is what the | |
787 | * call bracket in r300_do_cp_cmdbuf is for. | |
788 | */ | |
789 | ||
790 | /** | |
791 | * Emit the sequence to pacify R300. | |
792 | */ | |
ce580fab | 793 | static void r300_pacify(drm_radeon_private_t *dev_priv) |
414ed537 | 794 | { |
54f961a6 | 795 | uint32_t cache_z, cache_3d, cache_2d; |
414ed537 | 796 | RING_LOCALS; |
e2898c5f | 797 | |
54f961a6 JG |
798 | cache_z = R300_ZC_FLUSH; |
799 | cache_2d = R300_RB2D_DC_FLUSH; | |
800 | cache_3d = R300_RB3D_DC_FLUSH; | |
801 | if (!(dev_priv->track_flush & RADEON_PURGE_EMITED)) { | |
802 | /* we can purge, primitive where draw since last purge */ | |
803 | cache_z |= R300_ZC_FREE; | |
804 | cache_2d |= R300_RB2D_DC_FREE; | |
805 | cache_3d |= R300_RB3D_DC_FREE; | |
806 | } | |
414ed537 | 807 | |
54f961a6 JG |
808 | /* flush & purge zbuffer */ |
809 | BEGIN_RING(2); | |
21efa2ba | 810 | OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); |
54f961a6 JG |
811 | OUT_RING(cache_z); |
812 | ADVANCE_RING(); | |
813 | /* flush & purge 3d */ | |
814 | BEGIN_RING(2); | |
815 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | |
816 | OUT_RING(cache_3d); | |
817 | ADVANCE_RING(); | |
818 | /* flush & purge texture */ | |
819 | BEGIN_RING(2); | |
820 | OUT_RING(CP_PACKET0(R300_TX_INVALTAGS, 0)); | |
821 | OUT_RING(0); | |
822 | ADVANCE_RING(); | |
823 | /* FIXME: is this one really needed ? */ | |
824 | BEGIN_RING(2); | |
825 | OUT_RING(CP_PACKET0(R300_RB3D_AARESOLVE_CTL, 0)); | |
826 | OUT_RING(0); | |
827 | ADVANCE_RING(); | |
828 | BEGIN_RING(2); | |
829 | OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); | |
830 | OUT_RING(RADEON_WAIT_3D_IDLECLEAN); | |
831 | ADVANCE_RING(); | |
832 | /* flush & purge 2d through E2 as RB2D will trigger lockup */ | |
833 | BEGIN_RING(4); | |
834 | OUT_RING(CP_PACKET0(R300_DSTCACHE_CTLSTAT, 0)); | |
835 | OUT_RING(cache_2d); | |
836 | OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); | |
837 | OUT_RING(RADEON_WAIT_2D_IDLECLEAN | | |
838 | RADEON_WAIT_HOST_IDLECLEAN); | |
414ed537 | 839 | ADVANCE_RING(); |
54f961a6 JG |
840 | /* set flush & purge flags */ |
841 | dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; | |
414ed537 DA |
842 | } |
843 | ||
414ed537 DA |
844 | /** |
845 | * Called by r300_do_cp_cmdbuf to update the internal buffer age and state. | |
846 | * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must | |
847 | * be careful about how this function is called. | |
848 | */ | |
7c1c2871 | 849 | static void r300_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf) |
414ed537 | 850 | { |
414ed537 | 851 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; |
7c1c2871 | 852 | struct drm_radeon_master_private *master_priv = master->driver_priv; |
414ed537 | 853 | |
7c1c2871 | 854 | buf_priv->age = ++master_priv->sarea_priv->last_dispatch; |
414ed537 DA |
855 | buf->pending = 1; |
856 | buf->used = 0; | |
857 | } | |
858 | ||
0c76be35 DA |
859 | static void r300_cmd_wait(drm_radeon_private_t * dev_priv, |
860 | drm_r300_cmd_header_t header) | |
861 | { | |
862 | u32 wait_until; | |
863 | RING_LOCALS; | |
864 | ||
865 | if (!header.wait.flags) | |
866 | return; | |
867 | ||
868 | wait_until = 0; | |
869 | ||
870 | switch(header.wait.flags) { | |
871 | case R300_WAIT_2D: | |
872 | wait_until = RADEON_WAIT_2D_IDLE; | |
873 | break; | |
874 | case R300_WAIT_3D: | |
875 | wait_until = RADEON_WAIT_3D_IDLE; | |
876 | break; | |
877 | case R300_NEW_WAIT_2D_3D: | |
878 | wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_3D_IDLE; | |
879 | break; | |
880 | case R300_NEW_WAIT_2D_2D_CLEAN: | |
881 | wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN; | |
882 | break; | |
883 | case R300_NEW_WAIT_3D_3D_CLEAN: | |
884 | wait_until = RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN; | |
885 | break; | |
886 | case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN: | |
887 | wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN; | |
888 | wait_until |= RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN; | |
889 | break; | |
890 | default: | |
891 | return; | |
892 | } | |
893 | ||
894 | BEGIN_RING(2); | |
895 | OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); | |
896 | OUT_RING(wait_until); | |
897 | ADVANCE_RING(); | |
898 | } | |
899 | ||
ee4621f0 DA |
900 | static int r300_scratch(drm_radeon_private_t *dev_priv, |
901 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
902 | drm_r300_cmd_header_t header) | |
903 | { | |
904 | u32 *ref_age_base; | |
b4fe9454 PN |
905 | u32 i, *buf_idx, h_pending; |
906 | u64 *ptr_addr; | |
907 | u64 stack_ptr_addr; | |
ee4621f0 | 908 | RING_LOCALS; |
bc5f4523 | 909 | |
b4fe9454 PN |
910 | if (drm_buffer_unprocessed(cmdbuf->buffer) < |
911 | (sizeof(u64) + header.scratch.n_bufs * sizeof(*buf_idx))) { | |
20caafa6 | 912 | return -EINVAL; |
ee4621f0 | 913 | } |
bc5f4523 | 914 | |
ee4621f0 | 915 | if (header.scratch.reg >= 5) { |
20caafa6 | 916 | return -EINVAL; |
ee4621f0 | 917 | } |
bc5f4523 | 918 | |
ee4621f0 | 919 | dev_priv->scratch_ages[header.scratch.reg]++; |
bc5f4523 | 920 | |
b4fe9454 PN |
921 | ptr_addr = drm_buffer_read_object(cmdbuf->buffer, |
922 | sizeof(stack_ptr_addr), &stack_ptr_addr); | |
88b04507 | 923 | ref_age_base = (u32 *)(unsigned long)get_unaligned(ptr_addr); |
bc5f4523 | 924 | |
ee4621f0 | 925 | for (i=0; i < header.scratch.n_bufs; i++) { |
b4fe9454 PN |
926 | buf_idx = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0); |
927 | *buf_idx *= 2; /* 8 bytes per buf */ | |
bc5f4523 | 928 | |
b4fe9454 PN |
929 | if (DRM_COPY_TO_USER(ref_age_base + *buf_idx, |
930 | &dev_priv->scratch_ages[header.scratch.reg], | |
931 | sizeof(u32))) | |
20caafa6 | 932 | return -EINVAL; |
bc5f4523 | 933 | |
b4fe9454 PN |
934 | if (DRM_COPY_FROM_USER(&h_pending, |
935 | ref_age_base + *buf_idx + 1, | |
936 | sizeof(u32))) | |
20caafa6 | 937 | return -EINVAL; |
bc5f4523 | 938 | |
b4fe9454 | 939 | if (h_pending == 0) |
20caafa6 | 940 | return -EINVAL; |
bc5f4523 | 941 | |
ee4621f0 | 942 | h_pending--; |
bc5f4523 | 943 | |
b4fe9454 PN |
944 | if (DRM_COPY_TO_USER(ref_age_base + *buf_idx + 1, |
945 | &h_pending, | |
946 | sizeof(u32))) | |
20caafa6 | 947 | return -EINVAL; |
bc5f4523 | 948 | |
b4fe9454 | 949 | drm_buffer_advance(cmdbuf->buffer, sizeof(*buf_idx)); |
ee4621f0 | 950 | } |
bc5f4523 | 951 | |
ee4621f0 | 952 | BEGIN_RING(2); |
c6c656b4 OM |
953 | OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) ); |
954 | OUT_RING( dev_priv->scratch_ages[header.scratch.reg] ); | |
ee4621f0 | 955 | ADVANCE_RING(); |
bc5f4523 | 956 | |
ee4621f0 DA |
957 | return 0; |
958 | } | |
959 | ||
c0beb2a7 DA |
960 | /** |
961 | * Uploads user-supplied vertex program instructions or parameters onto | |
962 | * the graphics card. | |
963 | * Called by r300_do_cp_cmdbuf. | |
964 | */ | |
965 | static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv, | |
966 | drm_radeon_kcmd_buffer_t *cmdbuf, | |
967 | drm_r300_cmd_header_t header) | |
968 | { | |
969 | int sz; | |
970 | int addr; | |
971 | int type; | |
01136acf | 972 | int isclamp; |
c0beb2a7 DA |
973 | int stride; |
974 | RING_LOCALS; | |
975 | ||
976 | sz = header.r500fp.count; | |
977 | /* address is 9 bits 0 - 8, bit 1 of flags is part of address */ | |
978 | addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo; | |
979 | ||
980 | type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE); | |
01136acf | 981 | isclamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP); |
c0beb2a7 DA |
982 | |
983 | addr |= (type << 16); | |
01136acf | 984 | addr |= (isclamp << 17); |
c0beb2a7 DA |
985 | |
986 | stride = type ? 4 : 6; | |
987 | ||
988 | DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type); | |
989 | if (!sz) | |
990 | return 0; | |
b4fe9454 | 991 | if (sz * stride * 4 > drm_buffer_unprocessed(cmdbuf->buffer)) |
c0beb2a7 DA |
992 | return -EINVAL; |
993 | ||
994 | BEGIN_RING(3 + sz * stride); | |
995 | OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr); | |
996 | OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1)); | |
b4fe9454 | 997 | OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz * stride); |
c0beb2a7 DA |
998 | |
999 | ADVANCE_RING(); | |
1000 | ||
c0beb2a7 DA |
1001 | return 0; |
1002 | } | |
1003 | ||
1004 | ||
414ed537 DA |
1005 | /** |
1006 | * Parses and validates a user-supplied command buffer and emits appropriate | |
1007 | * commands on the DMA ring buffer. | |
1008 | * Called by the ioctl handler function radeon_cp_cmdbuf. | |
1009 | */ | |
84b1fd10 | 1010 | int r300_do_cp_cmdbuf(struct drm_device *dev, |
6c340eac | 1011 | struct drm_file *file_priv, |
d985c108 | 1012 | drm_radeon_kcmd_buffer_t *cmdbuf) |
414ed537 DA |
1013 | { |
1014 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 1015 | struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; |
cdd55a29 | 1016 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 1017 | struct drm_buf *buf = NULL; |
414ed537 DA |
1018 | int emit_dispatch_age = 0; |
1019 | int ret = 0; | |
1020 | ||
1021 | DRM_DEBUG("\n"); | |
1022 | ||
54f961a6 | 1023 | /* pacify */ |
414ed537 DA |
1024 | r300_pacify(dev_priv); |
1025 | ||
1026 | if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) { | |
1027 | ret = r300_emit_cliprects(dev_priv, cmdbuf, 0); | |
1028 | if (ret) | |
1029 | goto cleanup; | |
b5e89ed5 | 1030 | } |
414ed537 | 1031 | |
b4fe9454 PN |
1032 | while (drm_buffer_unprocessed(cmdbuf->buffer) |
1033 | >= sizeof(drm_r300_cmd_header_t)) { | |
414ed537 | 1034 | int idx; |
b4fe9454 | 1035 | drm_r300_cmd_header_t *header, stack_header; |
414ed537 | 1036 | |
b4fe9454 PN |
1037 | header = drm_buffer_read_object(cmdbuf->buffer, |
1038 | sizeof(stack_header), &stack_header); | |
414ed537 | 1039 | |
b4fe9454 | 1040 | switch (header->header.cmd_type) { |
b5e89ed5 | 1041 | case R300_CMD_PACKET0: |
414ed537 | 1042 | DRM_DEBUG("R300_CMD_PACKET0\n"); |
b4fe9454 | 1043 | ret = r300_emit_packet0(dev_priv, cmdbuf, *header); |
414ed537 DA |
1044 | if (ret) { |
1045 | DRM_ERROR("r300_emit_packet0 failed\n"); | |
1046 | goto cleanup; | |
b5e89ed5 | 1047 | } |
414ed537 DA |
1048 | break; |
1049 | ||
1050 | case R300_CMD_VPU: | |
1051 | DRM_DEBUG("R300_CMD_VPU\n"); | |
b4fe9454 | 1052 | ret = r300_emit_vpu(dev_priv, cmdbuf, *header); |
414ed537 DA |
1053 | if (ret) { |
1054 | DRM_ERROR("r300_emit_vpu failed\n"); | |
1055 | goto cleanup; | |
b5e89ed5 | 1056 | } |
414ed537 DA |
1057 | break; |
1058 | ||
1059 | case R300_CMD_PACKET3: | |
1060 | DRM_DEBUG("R300_CMD_PACKET3\n"); | |
b4fe9454 | 1061 | ret = r300_emit_packet3(dev_priv, cmdbuf, *header); |
414ed537 DA |
1062 | if (ret) { |
1063 | DRM_ERROR("r300_emit_packet3 failed\n"); | |
1064 | goto cleanup; | |
b5e89ed5 | 1065 | } |
414ed537 DA |
1066 | break; |
1067 | ||
1068 | case R300_CMD_END3D: | |
1069 | DRM_DEBUG("R300_CMD_END3D\n"); | |
b5e89ed5 DA |
1070 | /* TODO: |
1071 | Ideally userspace driver should not need to issue this call, | |
1072 | i.e. the drm driver should issue it automatically and prevent | |
1073 | lockups. | |
1074 | ||
1075 | In practice, we do not understand why this call is needed and what | |
1076 | it does (except for some vague guesses that it has to do with cache | |
1077 | coherence) and so the user space driver does it. | |
1078 | ||
1079 | Once we are sure which uses prevent lockups the code could be moved | |
1080 | into the kernel and the userspace driver will not | |
1081 | need to use this command. | |
1082 | ||
1083 | Note that issuing this command does not hurt anything | |
1084 | except, possibly, performance */ | |
414ed537 DA |
1085 | r300_pacify(dev_priv); |
1086 | break; | |
1087 | ||
1088 | case R300_CMD_CP_DELAY: | |
1089 | /* simple enough, we can do it here */ | |
1090 | DRM_DEBUG("R300_CMD_CP_DELAY\n"); | |
1091 | { | |
1092 | int i; | |
1093 | RING_LOCALS; | |
1094 | ||
b4fe9454 PN |
1095 | BEGIN_RING(header->delay.count); |
1096 | for (i = 0; i < header->delay.count; i++) | |
414ed537 DA |
1097 | OUT_RING(RADEON_CP_PACKET2); |
1098 | ADVANCE_RING(); | |
1099 | } | |
1100 | break; | |
1101 | ||
1102 | case R300_CMD_DMA_DISCARD: | |
1103 | DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); | |
b4fe9454 | 1104 | idx = header->dma.buf_idx; |
b5e89ed5 DA |
1105 | if (idx < 0 || idx >= dma->buf_count) { |
1106 | DRM_ERROR("buffer index %d (of %d max)\n", | |
1107 | idx, dma->buf_count - 1); | |
20caafa6 | 1108 | ret = -EINVAL; |
414ed537 | 1109 | goto cleanup; |
b5e89ed5 DA |
1110 | } |
1111 | ||
1112 | buf = dma->buflist[idx]; | |
6c340eac | 1113 | if (buf->file_priv != file_priv || buf->pending) { |
b5e89ed5 | 1114 | DRM_ERROR("bad buffer %p %p %d\n", |
6c340eac EA |
1115 | buf->file_priv, file_priv, |
1116 | buf->pending); | |
20caafa6 | 1117 | ret = -EINVAL; |
b5e89ed5 DA |
1118 | goto cleanup; |
1119 | } | |
414ed537 DA |
1120 | |
1121 | emit_dispatch_age = 1; | |
7c1c2871 | 1122 | r300_discard_buffer(dev, file_priv->master, buf); |
b5e89ed5 | 1123 | break; |
414ed537 DA |
1124 | |
1125 | case R300_CMD_WAIT: | |
414ed537 | 1126 | DRM_DEBUG("R300_CMD_WAIT\n"); |
b4fe9454 | 1127 | r300_cmd_wait(dev_priv, *header); |
414ed537 DA |
1128 | break; |
1129 | ||
ee4621f0 DA |
1130 | case R300_CMD_SCRATCH: |
1131 | DRM_DEBUG("R300_CMD_SCRATCH\n"); | |
b4fe9454 | 1132 | ret = r300_scratch(dev_priv, cmdbuf, *header); |
ee4621f0 DA |
1133 | if (ret) { |
1134 | DRM_ERROR("r300_scratch failed\n"); | |
1135 | goto cleanup; | |
1136 | } | |
1137 | break; | |
bc5f4523 | 1138 | |
c0beb2a7 DA |
1139 | case R300_CMD_R500FP: |
1140 | if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { | |
1141 | DRM_ERROR("Calling r500 command on r300 card\n"); | |
1142 | ret = -EINVAL; | |
1143 | goto cleanup; | |
1144 | } | |
1145 | DRM_DEBUG("R300_CMD_R500FP\n"); | |
b4fe9454 | 1146 | ret = r300_emit_r500fp(dev_priv, cmdbuf, *header); |
c0beb2a7 DA |
1147 | if (ret) { |
1148 | DRM_ERROR("r300_emit_r500fp failed\n"); | |
1149 | goto cleanup; | |
1150 | } | |
1151 | break; | |
414ed537 | 1152 | default: |
b4fe9454 PN |
1153 | DRM_ERROR("bad cmd_type %i at byte %d\n", |
1154 | header->header.cmd_type, | |
55a5cb5d | 1155 | cmdbuf->buffer->iterator - (int)sizeof(*header)); |
20caafa6 | 1156 | ret = -EINVAL; |
414ed537 | 1157 | goto cleanup; |
b5e89ed5 | 1158 | } |
414ed537 DA |
1159 | } |
1160 | ||
1161 | DRM_DEBUG("END\n"); | |
1162 | ||
b5e89ed5 | 1163 | cleanup: |
414ed537 DA |
1164 | r300_pacify(dev_priv); |
1165 | ||
1166 | /* We emit the vertex buffer age here, outside the pacifier "brackets" | |
1167 | * for two reasons: | |
1168 | * (1) This may coalesce multiple age emissions into a single one and | |
1169 | * (2) more importantly, some chips lock up hard when scratch registers | |
1170 | * are written inside the pacifier bracket. | |
1171 | */ | |
1172 | if (emit_dispatch_age) { | |
1173 | RING_LOCALS; | |
1174 | ||
1175 | /* Emit the vertex buffer age */ | |
1176 | BEGIN_RING(2); | |
7c1c2871 | 1177 | RADEON_DISPATCH_AGE(master_priv->sarea_priv->last_dispatch); |
414ed537 | 1178 | ADVANCE_RING(); |
b5e89ed5 | 1179 | } |
414ed537 DA |
1180 | |
1181 | COMMIT_RING(); | |
1182 | ||
1183 | return ret; | |
1184 | } |