Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
c182615f | 28 | |
2ef79416 | 29 | #include <linux/pci.h> |
771fe6b9 | 30 | #include <linux/seq_file.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
c182615f | 32 | |
225758d8 JG |
33 | #include <drm/drm.h> |
34 | #include <drm/drm_crtc_helper.h> | |
c182615f SR |
35 | #include <drm/drm_debugfs.h> |
36 | #include <drm/drm_device.h> | |
37 | #include <drm/drm_file.h> | |
760285e7 | 38 | #include <drm/radeon_drm.h> |
c182615f | 39 | |
551ebd83 | 40 | #include "r100_track.h" |
c182615f | 41 | #include "r300_reg_safe.h" |
3ce0a23d | 42 | #include "r300d.h" |
c182615f SR |
43 | #include "radeon.h" |
44 | #include "radeon_asic.h" | |
45 | #include "radeon_reg.h" | |
ca6ffc64 | 46 | #include "rv350d.h" |
50f15303 | 47 | |
cafe6609 JG |
48 | /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 |
49 | * | |
50 | * GPU Errata: | |
51 | * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL | |
52 | * using MMIO to flush host path read cache, this lead to HARDLOCKUP. | |
53 | * However, scheduling such write to the ring seems harmless, i suspect | |
54 | * the CP read collide with the flush somehow, or maybe the MC, hard to | |
55 | * tell. (Jerome Glisse) | |
56 | */ | |
771fe6b9 | 57 | |
9e5acbc2 DV |
58 | /* |
59 | * Indirect registers accessor | |
60 | */ | |
61 | uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
62 | { | |
63 | unsigned long flags; | |
64 | uint32_t r; | |
65 | ||
66 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); | |
67 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
68 | r = RREG32(RADEON_PCIE_DATA); | |
69 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); | |
70 | return r; | |
71 | } | |
72 | ||
73 | void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
74 | { | |
75 | unsigned long flags; | |
76 | ||
77 | spin_lock_irqsave(&rdev->pcie_idx_lock, flags); | |
78 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
79 | WREG32(RADEON_PCIE_DATA, (v)); | |
80 | spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); | |
81 | } | |
82 | ||
771fe6b9 JG |
83 | /* |
84 | * rv370,rv380 PCIE GART | |
85 | */ | |
207bf9e9 JG |
86 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
87 | ||
771fe6b9 JG |
88 | void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) |
89 | { | |
90 | uint32_t tmp; | |
91 | int i; | |
92 | ||
93 | /* Workaround HW bug do flush 2 times */ | |
94 | for (i = 0; i < 2; i++) { | |
95 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); | |
96 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); | |
97 | (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); | |
98 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); | |
771fe6b9 | 99 | } |
de1b2898 | 100 | mb(); |
771fe6b9 JG |
101 | } |
102 | ||
77497f27 | 103 | #define R300_PTE_UNSNOOPED (1 << 0) |
d75ee3be AD |
104 | #define R300_PTE_WRITEABLE (1 << 2) |
105 | #define R300_PTE_READABLE (1 << 3) | |
106 | ||
cb658906 | 107 | uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags) |
4aac0473 | 108 | { |
4aac0473 | 109 | addr = (lower_32_bits(addr) >> 8) | |
77497f27 MD |
110 | ((upper_32_bits(addr) & 0xff) << 24); |
111 | if (flags & RADEON_GART_PAGE_READ) | |
112 | addr |= R300_PTE_READABLE; | |
113 | if (flags & RADEON_GART_PAGE_WRITE) | |
114 | addr |= R300_PTE_WRITEABLE; | |
115 | if (!(flags & RADEON_GART_PAGE_SNOOP)) | |
116 | addr |= R300_PTE_UNSNOOPED; | |
cb658906 MD |
117 | return addr; |
118 | } | |
119 | ||
120 | void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, | |
121 | uint64_t entry) | |
122 | { | |
123 | void __iomem *ptr = rdev->gart.ptr; | |
124 | ||
4aac0473 JG |
125 | /* on x86 we want this to be CPU endian, on powerpc |
126 | * on powerpc without HW swappers, it'll get swapped on way | |
127 | * into VRAM - so no need for cpu_to_le32 on VRAM tables */ | |
cb658906 | 128 | writel(entry, ((void __iomem *)ptr) + (i * 4)); |
4aac0473 JG |
129 | } |
130 | ||
131 | int rv370_pcie_gart_init(struct radeon_device *rdev) | |
771fe6b9 | 132 | { |
771fe6b9 JG |
133 | int r; |
134 | ||
c9a1be96 | 135 | if (rdev->gart.robj) { |
fce7d61b | 136 | WARN(1, "RV370 PCIE GART already initialized\n"); |
4aac0473 JG |
137 | return 0; |
138 | } | |
771fe6b9 JG |
139 | /* Initialize common gart structure */ |
140 | r = radeon_gart_init(rdev); | |
4aac0473 | 141 | if (r) |
771fe6b9 | 142 | return r; |
771fe6b9 | 143 | r = rv370_debugfs_pcie_gart_info_init(rdev); |
4aac0473 | 144 | if (r) |
771fe6b9 | 145 | DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); |
771fe6b9 | 146 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
c5b3b850 | 147 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
cb658906 | 148 | rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; |
c5b3b850 | 149 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; |
4aac0473 JG |
150 | return radeon_gart_table_vram_alloc(rdev); |
151 | } | |
152 | ||
153 | int rv370_pcie_gart_enable(struct radeon_device *rdev) | |
154 | { | |
155 | uint32_t table_addr; | |
156 | uint32_t tmp; | |
157 | int r; | |
158 | ||
c9a1be96 | 159 | if (rdev->gart.robj == NULL) { |
4aac0473 JG |
160 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
161 | return -EINVAL; | |
771fe6b9 | 162 | } |
4aac0473 JG |
163 | r = radeon_gart_table_vram_pin(rdev); |
164 | if (r) | |
165 | return r; | |
771fe6b9 JG |
166 | /* discard memory request outside of configured range */ |
167 | tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; | |
168 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); | |
d594e46a JG |
169 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); |
170 | tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; | |
771fe6b9 JG |
171 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); |
172 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); | |
173 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); | |
174 | table_addr = rdev->gart.table_addr; | |
175 | WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); | |
176 | /* FIXME: setup default page */ | |
d594e46a | 177 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); |
771fe6b9 JG |
178 | WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); |
179 | /* Clear error */ | |
d75ee3be | 180 | WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); |
771fe6b9 JG |
181 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
182 | tmp |= RADEON_PCIE_TX_GART_EN; | |
183 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; | |
184 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); | |
185 | rv370_pcie_gart_tlb_flush(rdev); | |
fcf4de5a TV |
186 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
187 | (unsigned)(rdev->mc.gtt_size >> 20), | |
188 | (unsigned long long)table_addr); | |
771fe6b9 JG |
189 | rdev->gart.ready = true; |
190 | return 0; | |
191 | } | |
192 | ||
193 | void rv370_pcie_gart_disable(struct radeon_device *rdev) | |
194 | { | |
4c788679 | 195 | u32 tmp; |
771fe6b9 | 196 | |
90aca4d2 JG |
197 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); |
198 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); | |
199 | WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); | |
200 | WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); | |
771fe6b9 JG |
201 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); |
202 | tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; | |
203 | WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); | |
c9a1be96 | 204 | radeon_gart_table_vram_unpin(rdev); |
771fe6b9 JG |
205 | } |
206 | ||
4aac0473 | 207 | void rv370_pcie_gart_fini(struct radeon_device *rdev) |
771fe6b9 | 208 | { |
f9274562 | 209 | radeon_gart_fini(rdev); |
4aac0473 JG |
210 | rv370_pcie_gart_disable(rdev); |
211 | radeon_gart_table_vram_free(rdev); | |
771fe6b9 JG |
212 | } |
213 | ||
771fe6b9 JG |
214 | void r300_fence_ring_emit(struct radeon_device *rdev, |
215 | struct radeon_fence *fence) | |
216 | { | |
e32eb50d | 217 | struct radeon_ring *ring = &rdev->ring[fence->ring]; |
7b1f2485 | 218 | |
771fe6b9 JG |
219 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
220 | * for enough space (today caller are ib schedule and buffer move) */ | |
221 | /* Write SC register so SC & US assert idle */ | |
e32eb50d CK |
222 | radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); |
223 | radeon_ring_write(ring, 0); | |
224 | radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); | |
225 | radeon_ring_write(ring, 0); | |
771fe6b9 | 226 | /* Flush 3D cache */ |
e32eb50d CK |
227 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
228 | radeon_ring_write(ring, R300_RB3D_DC_FLUSH); | |
229 | radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | |
230 | radeon_ring_write(ring, R300_ZC_FLUSH); | |
771fe6b9 | 231 | /* Wait until IDLE & CLEAN */ |
e32eb50d CK |
232 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); |
233 | radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | | |
4612dc97 AD |
234 | RADEON_WAIT_2D_IDLECLEAN | |
235 | RADEON_WAIT_DMA_GUI_IDLE)); | |
e32eb50d CK |
236 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
237 | radeon_ring_write(ring, rdev->config.r300.hdp_cntl | | |
cafe6609 | 238 | RADEON_HDP_READ_BUFFER_INVALIDATE); |
e32eb50d CK |
239 | radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
240 | radeon_ring_write(ring, rdev->config.r300.hdp_cntl); | |
771fe6b9 | 241 | /* Emit fence sequence & fire IRQ */ |
e32eb50d CK |
242 | radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); |
243 | radeon_ring_write(ring, fence->seq); | |
244 | radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); | |
245 | radeon_ring_write(ring, RADEON_SW_INT_FIRE); | |
771fe6b9 JG |
246 | } |
247 | ||
f712812e | 248 | void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
771fe6b9 JG |
249 | { |
250 | unsigned gb_tile_config; | |
251 | int r; | |
252 | ||
253 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ | |
254 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); | |
068a117c | 255 | switch(rdev->num_gb_pipes) { |
771fe6b9 JG |
256 | case 2: |
257 | gb_tile_config |= R300_PIPE_COUNT_R300; | |
258 | break; | |
259 | case 3: | |
260 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; | |
261 | break; | |
262 | case 4: | |
263 | gb_tile_config |= R300_PIPE_COUNT_R420; | |
264 | break; | |
265 | case 1: | |
266 | default: | |
267 | gb_tile_config |= R300_PIPE_COUNT_RV350; | |
268 | break; | |
269 | } | |
270 | ||
e32eb50d | 271 | r = radeon_ring_lock(rdev, ring, 64); |
771fe6b9 JG |
272 | if (r) { |
273 | return; | |
274 | } | |
e32eb50d CK |
275 | radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); |
276 | radeon_ring_write(ring, | |
771fe6b9 JG |
277 | RADEON_ISYNC_ANY2D_IDLE3D | |
278 | RADEON_ISYNC_ANY3D_IDLE2D | | |
279 | RADEON_ISYNC_WAIT_IDLEGUI | | |
280 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); | |
e32eb50d CK |
281 | radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); |
282 | radeon_ring_write(ring, gb_tile_config); | |
283 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); | |
284 | radeon_ring_write(ring, | |
771fe6b9 JG |
285 | RADEON_WAIT_2D_IDLECLEAN | |
286 | RADEON_WAIT_3D_IDLECLEAN); | |
e32eb50d CK |
287 | radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); |
288 | radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); | |
289 | radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); | |
290 | radeon_ring_write(ring, 0); | |
291 | radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); | |
292 | radeon_ring_write(ring, 0); | |
293 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | |
294 | radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); | |
295 | radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | |
296 | radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); | |
297 | radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); | |
298 | radeon_ring_write(ring, | |
771fe6b9 JG |
299 | RADEON_WAIT_2D_IDLECLEAN | |
300 | RADEON_WAIT_3D_IDLECLEAN); | |
e32eb50d CK |
301 | radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); |
302 | radeon_ring_write(ring, 0); | |
303 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | |
304 | radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); | |
305 | radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | |
306 | radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); | |
307 | radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); | |
308 | radeon_ring_write(ring, | |
771fe6b9 JG |
309 | ((6 << R300_MS_X0_SHIFT) | |
310 | (6 << R300_MS_Y0_SHIFT) | | |
311 | (6 << R300_MS_X1_SHIFT) | | |
312 | (6 << R300_MS_Y1_SHIFT) | | |
313 | (6 << R300_MS_X2_SHIFT) | | |
314 | (6 << R300_MS_Y2_SHIFT) | | |
315 | (6 << R300_MSBD0_Y_SHIFT) | | |
316 | (6 << R300_MSBD0_X_SHIFT))); | |
e32eb50d CK |
317 | radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); |
318 | radeon_ring_write(ring, | |
771fe6b9 JG |
319 | ((6 << R300_MS_X3_SHIFT) | |
320 | (6 << R300_MS_Y3_SHIFT) | | |
321 | (6 << R300_MS_X4_SHIFT) | | |
322 | (6 << R300_MS_Y4_SHIFT) | | |
323 | (6 << R300_MS_X5_SHIFT) | | |
324 | (6 << R300_MS_Y5_SHIFT) | | |
325 | (6 << R300_MSBD1_SHIFT))); | |
e32eb50d CK |
326 | radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); |
327 | radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); | |
328 | radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); | |
329 | radeon_ring_write(ring, | |
771fe6b9 | 330 | R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
e32eb50d CK |
331 | radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); |
332 | radeon_ring_write(ring, | |
771fe6b9 JG |
333 | R300_GEOMETRY_ROUND_NEAREST | |
334 | R300_COLOR_ROUND_NEAREST); | |
1538a9e0 | 335 | radeon_ring_unlock_commit(rdev, ring, false); |
771fe6b9 JG |
336 | } |
337 | ||
1109ca09 | 338 | static void r300_errata(struct radeon_device *rdev) |
771fe6b9 JG |
339 | { |
340 | rdev->pll_errata = 0; | |
341 | ||
342 | if (rdev->family == CHIP_R300 && | |
343 | (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { | |
344 | rdev->pll_errata |= CHIP_ERRATA_R300_CG; | |
345 | } | |
346 | } | |
347 | ||
348 | int r300_mc_wait_for_idle(struct radeon_device *rdev) | |
349 | { | |
350 | unsigned i; | |
351 | uint32_t tmp; | |
352 | ||
353 | for (i = 0; i < rdev->usec_timeout; i++) { | |
354 | /* read MC_STATUS */ | |
4612dc97 AD |
355 | tmp = RREG32(RADEON_MC_STATUS); |
356 | if (tmp & R300_MC_IDLE) { | |
771fe6b9 JG |
357 | return 0; |
358 | } | |
0e1a351d | 359 | udelay(1); |
771fe6b9 JG |
360 | } |
361 | return -1; | |
362 | } | |
363 | ||
1109ca09 | 364 | static void r300_gpu_init(struct radeon_device *rdev) |
771fe6b9 JG |
365 | { |
366 | uint32_t gb_tile_config, tmp; | |
367 | ||
57b54ea6 | 368 | if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || |
94f7bf64 | 369 | (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { |
771fe6b9 JG |
370 | /* r300,r350 */ |
371 | rdev->num_gb_pipes = 2; | |
372 | } else { | |
94f7bf64 | 373 | /* rv350,rv370,rv380,r300 AD, r350 AH */ |
771fe6b9 JG |
374 | rdev->num_gb_pipes = 1; |
375 | } | |
f779b3e5 | 376 | rdev->num_z_pipes = 1; |
771fe6b9 JG |
377 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); |
378 | switch (rdev->num_gb_pipes) { | |
379 | case 2: | |
380 | gb_tile_config |= R300_PIPE_COUNT_R300; | |
381 | break; | |
382 | case 3: | |
383 | gb_tile_config |= R300_PIPE_COUNT_R420_3P; | |
384 | break; | |
385 | case 4: | |
386 | gb_tile_config |= R300_PIPE_COUNT_R420; | |
387 | break; | |
771fe6b9 | 388 | default: |
068a117c | 389 | case 1: |
771fe6b9 JG |
390 | gb_tile_config |= R300_PIPE_COUNT_RV350; |
391 | break; | |
392 | } | |
393 | WREG32(R300_GB_TILE_CONFIG, gb_tile_config); | |
394 | ||
395 | if (r100_gui_wait_for_idle(rdev)) { | |
7ca85295 | 396 | pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); |
771fe6b9 JG |
397 | } |
398 | ||
4612dc97 AD |
399 | tmp = RREG32(R300_DST_PIPE_CONFIG); |
400 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); | |
771fe6b9 JG |
401 | |
402 | WREG32(R300_RB2D_DSTCACHE_MODE, | |
403 | R300_DC_AUTOFLUSH_ENABLE | | |
404 | R300_DC_DC_DISABLE_IGNORE_PE); | |
405 | ||
406 | if (r100_gui_wait_for_idle(rdev)) { | |
7ca85295 | 407 | pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n"); |
771fe6b9 JG |
408 | } |
409 | if (r300_mc_wait_for_idle(rdev)) { | |
7ca85295 | 410 | pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n"); |
771fe6b9 | 411 | } |
7ca85295 | 412 | DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized\n", |
f779b3e5 | 413 | rdev->num_gb_pipes, rdev->num_z_pipes); |
771fe6b9 JG |
414 | } |
415 | ||
71fe2899 | 416 | int r300_asic_reset(struct radeon_device *rdev, bool hard) |
771fe6b9 | 417 | { |
90aca4d2 JG |
418 | struct r100_mc_save save; |
419 | u32 status, tmp; | |
25b2ec5b | 420 | int ret = 0; |
771fe6b9 | 421 | |
90aca4d2 JG |
422 | status = RREG32(R_000E40_RBBM_STATUS); |
423 | if (!G_000E40_GUI_ACTIVE(status)) { | |
424 | return 0; | |
771fe6b9 | 425 | } |
25b2ec5b | 426 | r100_mc_stop(rdev, &save); |
90aca4d2 JG |
427 | status = RREG32(R_000E40_RBBM_STATUS); |
428 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
429 | /* stop CP */ | |
430 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
431 | tmp = RREG32(RADEON_CP_RB_CNTL); | |
432 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); | |
433 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | |
434 | WREG32(RADEON_CP_RB_WPTR, 0); | |
435 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
436 | /* save PCI state */ | |
437 | pci_save_state(rdev->pdev); | |
438 | /* disable bus mastering */ | |
439 | r100_bm_disable(rdev); | |
440 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | | |
441 | S_0000F0_SOFT_RESET_GA(1)); | |
442 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
443 | mdelay(500); | |
444 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
445 | mdelay(1); | |
446 | status = RREG32(R_000E40_RBBM_STATUS); | |
447 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
448 | /* resetting the CP seems to be problematic sometimes it end up | |
25985edc | 449 | * hard locking the computer, but it's necessary for successful |
90aca4d2 JG |
450 | * reset more test & playing is needed on R3XX/R4XX to find a |
451 | * reliable (if any solution) | |
452 | */ | |
453 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); | |
454 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
455 | mdelay(500); | |
456 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
457 | mdelay(1); | |
458 | status = RREG32(R_000E40_RBBM_STATUS); | |
459 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
90aca4d2 JG |
460 | /* restore PCI & busmastering */ |
461 | pci_restore_state(rdev->pdev); | |
462 | r100_enable_bm(rdev); | |
771fe6b9 | 463 | /* Check if GPU is idle */ |
90aca4d2 JG |
464 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
465 | dev_err(rdev->dev, "failed to reset GPU\n"); | |
25b2ec5b AD |
466 | ret = -1; |
467 | } else | |
468 | dev_info(rdev->dev, "GPU reset succeed\n"); | |
90aca4d2 | 469 | r100_mc_resume(rdev, &save); |
25b2ec5b | 470 | return ret; |
771fe6b9 JG |
471 | } |
472 | ||
771fe6b9 JG |
473 | /* |
474 | * r300,r350,rv350,rv380 VRAM info | |
475 | */ | |
d594e46a | 476 | void r300_mc_init(struct radeon_device *rdev) |
771fe6b9 | 477 | { |
8e361130 JG |
478 | u64 base; |
479 | u32 tmp; | |
771fe6b9 JG |
480 | |
481 | /* DDR for all card after R300 & IGP */ | |
482 | rdev->mc.vram_is_ddr = true; | |
483 | tmp = RREG32(RADEON_MEM_CNTL); | |
5ff55717 DA |
484 | tmp &= R300_MEM_NUM_CHANNELS_MASK; |
485 | switch (tmp) { | |
486 | case 0: rdev->mc.vram_width = 64; break; | |
487 | case 1: rdev->mc.vram_width = 128; break; | |
488 | case 2: rdev->mc.vram_width = 256; break; | |
489 | default: rdev->mc.vram_width = 128; break; | |
771fe6b9 | 490 | } |
2a0f8918 | 491 | r100_vram_init_sizes(rdev); |
8e361130 JG |
492 | base = rdev->mc.aper_base; |
493 | if (rdev->flags & RADEON_IS_IGP) | |
494 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; | |
495 | radeon_vram_location(rdev, &rdev->mc, base); | |
8d369bb1 | 496 | rdev->mc.gtt_base_align = 0; |
d594e46a JG |
497 | if (!(rdev->flags & RADEON_IS_AGP)) |
498 | radeon_gtt_location(rdev, &rdev->mc); | |
f47299c5 | 499 | radeon_update_bandwidth_info(rdev); |
771fe6b9 JG |
500 | } |
501 | ||
771fe6b9 JG |
502 | void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) |
503 | { | |
504 | uint32_t link_width_cntl, mask; | |
505 | ||
506 | if (rdev->flags & RADEON_IS_IGP) | |
507 | return; | |
508 | ||
509 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
510 | return; | |
511 | ||
512 | /* FIXME wait for idle */ | |
513 | ||
514 | switch (lanes) { | |
515 | case 0: | |
516 | mask = RADEON_PCIE_LC_LINK_WIDTH_X0; | |
517 | break; | |
518 | case 1: | |
519 | mask = RADEON_PCIE_LC_LINK_WIDTH_X1; | |
520 | break; | |
521 | case 2: | |
522 | mask = RADEON_PCIE_LC_LINK_WIDTH_X2; | |
523 | break; | |
524 | case 4: | |
525 | mask = RADEON_PCIE_LC_LINK_WIDTH_X4; | |
526 | break; | |
527 | case 8: | |
528 | mask = RADEON_PCIE_LC_LINK_WIDTH_X8; | |
529 | break; | |
530 | case 12: | |
531 | mask = RADEON_PCIE_LC_LINK_WIDTH_X12; | |
532 | break; | |
533 | case 16: | |
534 | default: | |
535 | mask = RADEON_PCIE_LC_LINK_WIDTH_X16; | |
536 | break; | |
537 | } | |
538 | ||
539 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | |
540 | ||
541 | if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == | |
542 | (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) | |
543 | return; | |
544 | ||
545 | link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | | |
546 | RADEON_PCIE_LC_RECONFIG_NOW | | |
547 | RADEON_PCIE_LC_RECONFIG_LATER | | |
548 | RADEON_PCIE_LC_SHORT_RECONFIG_EN); | |
549 | link_width_cntl |= mask; | |
550 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); | |
551 | WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | | |
552 | RADEON_PCIE_LC_RECONFIG_NOW)); | |
553 | ||
554 | /* wait for lane set to complete */ | |
555 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | |
556 | while (link_width_cntl == 0xffffffff) | |
557 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); | |
558 | ||
559 | } | |
560 | ||
c836a412 AD |
561 | int rv370_get_pcie_lanes(struct radeon_device *rdev) |
562 | { | |
563 | u32 link_width_cntl; | |
564 | ||
565 | if (rdev->flags & RADEON_IS_IGP) | |
566 | return 0; | |
567 | ||
568 | if (!(rdev->flags & RADEON_IS_PCIE)) | |
569 | return 0; | |
570 | ||
571 | /* FIXME wait for idle */ | |
572 | ||
3313e3d4 | 573 | link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); |
c836a412 AD |
574 | |
575 | switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { | |
576 | case RADEON_PCIE_LC_LINK_WIDTH_X0: | |
577 | return 0; | |
578 | case RADEON_PCIE_LC_LINK_WIDTH_X1: | |
579 | return 1; | |
580 | case RADEON_PCIE_LC_LINK_WIDTH_X2: | |
581 | return 2; | |
582 | case RADEON_PCIE_LC_LINK_WIDTH_X4: | |
583 | return 4; | |
584 | case RADEON_PCIE_LC_LINK_WIDTH_X8: | |
585 | return 8; | |
586 | case RADEON_PCIE_LC_LINK_WIDTH_X16: | |
587 | default: | |
588 | return 16; | |
589 | } | |
590 | } | |
591 | ||
771fe6b9 JG |
592 | #if defined(CONFIG_DEBUG_FS) |
593 | static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) | |
594 | { | |
595 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
596 | struct drm_device *dev = node->minor->dev; | |
597 | struct radeon_device *rdev = dev->dev_private; | |
598 | uint32_t tmp; | |
599 | ||
600 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); | |
601 | seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); | |
602 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); | |
603 | seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); | |
604 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); | |
605 | seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); | |
606 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); | |
607 | seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); | |
608 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); | |
609 | seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); | |
610 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); | |
611 | seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); | |
612 | tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); | |
613 | seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); | |
614 | return 0; | |
615 | } | |
616 | ||
617 | static struct drm_info_list rv370_pcie_gart_info_list[] = { | |
618 | {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, | |
619 | }; | |
620 | #endif | |
621 | ||
207bf9e9 | 622 | static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
771fe6b9 JG |
623 | { |
624 | #if defined(CONFIG_DEBUG_FS) | |
625 | return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); | |
626 | #else | |
627 | return 0; | |
628 | #endif | |
629 | } | |
630 | ||
771fe6b9 JG |
631 | static int r300_packet0_check(struct radeon_cs_parser *p, |
632 | struct radeon_cs_packet *pkt, | |
633 | unsigned idx, unsigned reg) | |
634 | { | |
1d0c0942 | 635 | struct radeon_bo_list *reloc; |
551ebd83 | 636 | struct r100_cs_track *track; |
771fe6b9 | 637 | volatile uint32_t *ib; |
e024e110 | 638 | uint32_t tmp, tile_flags = 0; |
771fe6b9 JG |
639 | unsigned i; |
640 | int r; | |
513bcb46 | 641 | u32 idx_value; |
771fe6b9 | 642 | |
f2e39221 | 643 | ib = p->ib.ptr; |
551ebd83 | 644 | track = (struct r100_cs_track *)p->track; |
513bcb46 DA |
645 | idx_value = radeon_get_ib_value(p, idx); |
646 | ||
068a117c | 647 | switch(reg) { |
531369e6 DA |
648 | case AVIVO_D1MODE_VLINE_START_END: |
649 | case RADEON_CRTC_GUI_TRIG_VLINE: | |
650 | r = r100_cs_packet_parse_vline(p); | |
651 | if (r) { | |
652 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
653 | idx, reg); | |
c3ad63af | 654 | radeon_cs_dump_packet(p, pkt); |
531369e6 DA |
655 | return r; |
656 | } | |
657 | break; | |
771fe6b9 JG |
658 | case RADEON_DST_PITCH_OFFSET: |
659 | case RADEON_SRC_PITCH_OFFSET: | |
551ebd83 DA |
660 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); |
661 | if (r) | |
771fe6b9 | 662 | return r; |
771fe6b9 JG |
663 | break; |
664 | case R300_RB3D_COLOROFFSET0: | |
665 | case R300_RB3D_COLOROFFSET1: | |
666 | case R300_RB3D_COLOROFFSET2: | |
667 | case R300_RB3D_COLOROFFSET3: | |
668 | i = (reg - R300_RB3D_COLOROFFSET0) >> 2; | |
012e976d | 669 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
670 | if (r) { |
671 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
672 | idx, reg); | |
c3ad63af | 673 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
674 | return r; |
675 | } | |
676 | track->cb[i].robj = reloc->robj; | |
513bcb46 | 677 | track->cb[i].offset = idx_value; |
40b4a759 | 678 | track->cb_dirty = true; |
df0af440 | 679 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
771fe6b9 JG |
680 | break; |
681 | case R300_ZB_DEPTHOFFSET: | |
012e976d | 682 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
683 | if (r) { |
684 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
685 | idx, reg); | |
c3ad63af | 686 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
687 | return r; |
688 | } | |
689 | track->zb.robj = reloc->robj; | |
513bcb46 | 690 | track->zb.offset = idx_value; |
40b4a759 | 691 | track->zb_dirty = true; |
df0af440 | 692 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
771fe6b9 JG |
693 | break; |
694 | case R300_TX_OFFSET_0: | |
695 | case R300_TX_OFFSET_0+4: | |
696 | case R300_TX_OFFSET_0+8: | |
697 | case R300_TX_OFFSET_0+12: | |
698 | case R300_TX_OFFSET_0+16: | |
699 | case R300_TX_OFFSET_0+20: | |
700 | case R300_TX_OFFSET_0+24: | |
701 | case R300_TX_OFFSET_0+28: | |
702 | case R300_TX_OFFSET_0+32: | |
703 | case R300_TX_OFFSET_0+36: | |
704 | case R300_TX_OFFSET_0+40: | |
705 | case R300_TX_OFFSET_0+44: | |
706 | case R300_TX_OFFSET_0+48: | |
707 | case R300_TX_OFFSET_0+52: | |
708 | case R300_TX_OFFSET_0+56: | |
709 | case R300_TX_OFFSET_0+60: | |
068a117c | 710 | i = (reg - R300_TX_OFFSET_0) >> 2; |
012e976d | 711 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
712 | if (r) { |
713 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
714 | idx, reg); | |
c3ad63af | 715 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
716 | return r; |
717 | } | |
6e726772 | 718 | |
721604a1 | 719 | if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { |
e70f224c | 720 | ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ |
df0af440 | 721 | ((idx_value & ~31) + (u32)reloc->gpu_offset); |
e70f224c | 722 | } else { |
df0af440 | 723 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
e70f224c | 724 | tile_flags |= R300_TXO_MACRO_TILE; |
df0af440 | 725 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
e70f224c | 726 | tile_flags |= R300_TXO_MICRO_TILE; |
df0af440 | 727 | else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
e70f224c MO |
728 | tile_flags |= R300_TXO_MICRO_TILE_SQUARE; |
729 | ||
df0af440 | 730 | tmp = idx_value + ((u32)reloc->gpu_offset); |
e70f224c MO |
731 | tmp |= tile_flags; |
732 | ib[idx] = tmp; | |
733 | } | |
068a117c | 734 | track->textures[i].robj = reloc->robj; |
40b4a759 | 735 | track->tex_dirty = true; |
771fe6b9 JG |
736 | break; |
737 | /* Tracked registers */ | |
068a117c JG |
738 | case 0x2084: |
739 | /* VAP_VF_CNTL */ | |
513bcb46 | 740 | track->vap_vf_cntl = idx_value; |
068a117c JG |
741 | break; |
742 | case 0x20B4: | |
743 | /* VAP_VTX_SIZE */ | |
513bcb46 | 744 | track->vtx_size = idx_value & 0x7F; |
068a117c JG |
745 | break; |
746 | case 0x2134: | |
747 | /* VAP_VF_MAX_VTX_INDX */ | |
513bcb46 | 748 | track->max_indx = idx_value & 0x00FFFFFFUL; |
068a117c | 749 | break; |
cae94b0a MO |
750 | case 0x2088: |
751 | /* VAP_ALT_NUM_VERTICES - only valid on r500 */ | |
752 | if (p->rdev->family < CHIP_RV515) | |
753 | goto fail; | |
754 | track->vap_alt_nverts = idx_value & 0xFFFFFF; | |
755 | break; | |
771fe6b9 JG |
756 | case 0x43E4: |
757 | /* SC_SCISSOR1 */ | |
513bcb46 | 758 | track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; |
771fe6b9 JG |
759 | if (p->rdev->family < CHIP_RV515) { |
760 | track->maxy -= 1440; | |
761 | } | |
40b4a759 MO |
762 | track->cb_dirty = true; |
763 | track->zb_dirty = true; | |
771fe6b9 JG |
764 | break; |
765 | case 0x4E00: | |
766 | /* RB3D_CCTL */ | |
9eba4a93 MO |
767 | if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ |
768 | p->rdev->cmask_filp != p->filp) { | |
769 | DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); | |
770 | return -EINVAL; | |
771 | } | |
513bcb46 | 772 | track->num_cb = ((idx_value >> 5) & 0x3) + 1; |
40b4a759 | 773 | track->cb_dirty = true; |
771fe6b9 JG |
774 | break; |
775 | case 0x4E38: | |
776 | case 0x4E3C: | |
777 | case 0x4E40: | |
778 | case 0x4E44: | |
779 | /* RB3D_COLORPITCH0 */ | |
780 | /* RB3D_COLORPITCH1 */ | |
781 | /* RB3D_COLORPITCH2 */ | |
782 | /* RB3D_COLORPITCH3 */ | |
721604a1 | 783 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
012e976d | 784 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
e70f224c MO |
785 | if (r) { |
786 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
787 | idx, reg); | |
c3ad63af | 788 | radeon_cs_dump_packet(p, pkt); |
e70f224c MO |
789 | return r; |
790 | } | |
e024e110 | 791 | |
df0af440 | 792 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
e70f224c | 793 | tile_flags |= R300_COLOR_TILE_ENABLE; |
df0af440 | 794 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
e70f224c | 795 | tile_flags |= R300_COLOR_MICROTILE_ENABLE; |
df0af440 | 796 | else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
e70f224c | 797 | tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; |
e024e110 | 798 | |
e70f224c MO |
799 | tmp = idx_value & ~(0x7 << 16); |
800 | tmp |= tile_flags; | |
801 | ib[idx] = tmp; | |
802 | } | |
771fe6b9 | 803 | i = (reg - 0x4E38) >> 2; |
513bcb46 DA |
804 | track->cb[i].pitch = idx_value & 0x3FFE; |
805 | switch (((idx_value >> 21) & 0xF)) { | |
771fe6b9 JG |
806 | case 9: |
807 | case 11: | |
808 | case 12: | |
809 | track->cb[i].cpp = 1; | |
810 | break; | |
811 | case 3: | |
812 | case 4: | |
813 | case 13: | |
814 | case 15: | |
815 | track->cb[i].cpp = 2; | |
816 | break; | |
204663c4 MO |
817 | case 5: |
818 | if (p->rdev->family < CHIP_RV515) { | |
819 | DRM_ERROR("Invalid color buffer format (%d)!\n", | |
820 | ((idx_value >> 21) & 0xF)); | |
821 | return -EINVAL; | |
822 | } | |
df561f66 | 823 | fallthrough; |
771fe6b9 JG |
824 | case 6: |
825 | track->cb[i].cpp = 4; | |
826 | break; | |
827 | case 10: | |
828 | track->cb[i].cpp = 8; | |
829 | break; | |
830 | case 7: | |
831 | track->cb[i].cpp = 16; | |
832 | break; | |
833 | default: | |
834 | DRM_ERROR("Invalid color buffer format (%d) !\n", | |
513bcb46 | 835 | ((idx_value >> 21) & 0xF)); |
771fe6b9 JG |
836 | return -EINVAL; |
837 | } | |
40b4a759 | 838 | track->cb_dirty = true; |
771fe6b9 JG |
839 | break; |
840 | case 0x4F00: | |
841 | /* ZB_CNTL */ | |
513bcb46 | 842 | if (idx_value & 2) { |
771fe6b9 JG |
843 | track->z_enabled = true; |
844 | } else { | |
845 | track->z_enabled = false; | |
846 | } | |
40b4a759 | 847 | track->zb_dirty = true; |
771fe6b9 JG |
848 | break; |
849 | case 0x4F10: | |
850 | /* ZB_FORMAT */ | |
513bcb46 | 851 | switch ((idx_value & 0xF)) { |
771fe6b9 JG |
852 | case 0: |
853 | case 1: | |
854 | track->zb.cpp = 2; | |
855 | break; | |
856 | case 2: | |
857 | track->zb.cpp = 4; | |
858 | break; | |
859 | default: | |
860 | DRM_ERROR("Invalid z buffer format (%d) !\n", | |
513bcb46 | 861 | (idx_value & 0xF)); |
771fe6b9 JG |
862 | return -EINVAL; |
863 | } | |
40b4a759 | 864 | track->zb_dirty = true; |
771fe6b9 JG |
865 | break; |
866 | case 0x4F24: | |
867 | /* ZB_DEPTHPITCH */ | |
721604a1 | 868 | if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { |
012e976d | 869 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
e70f224c MO |
870 | if (r) { |
871 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
872 | idx, reg); | |
c3ad63af | 873 | radeon_cs_dump_packet(p, pkt); |
e70f224c MO |
874 | return r; |
875 | } | |
e024e110 | 876 | |
df0af440 | 877 | if (reloc->tiling_flags & RADEON_TILING_MACRO) |
e70f224c | 878 | tile_flags |= R300_DEPTHMACROTILE_ENABLE; |
df0af440 | 879 | if (reloc->tiling_flags & RADEON_TILING_MICRO) |
e70f224c | 880 | tile_flags |= R300_DEPTHMICROTILE_TILED; |
df0af440 | 881 | else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) |
e70f224c | 882 | tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; |
e024e110 | 883 | |
e70f224c MO |
884 | tmp = idx_value & ~(0x7 << 16); |
885 | tmp |= tile_flags; | |
886 | ib[idx] = tmp; | |
887 | } | |
513bcb46 | 888 | track->zb.pitch = idx_value & 0x3FFC; |
40b4a759 | 889 | track->zb_dirty = true; |
771fe6b9 | 890 | break; |
068a117c | 891 | case 0x4104: |
50183434 | 892 | /* TX_ENABLE */ |
068a117c JG |
893 | for (i = 0; i < 16; i++) { |
894 | bool enabled; | |
895 | ||
513bcb46 | 896 | enabled = !!(idx_value & (1 << i)); |
068a117c JG |
897 | track->textures[i].enabled = enabled; |
898 | } | |
40b4a759 | 899 | track->tex_dirty = true; |
068a117c JG |
900 | break; |
901 | case 0x44C0: | |
902 | case 0x44C4: | |
903 | case 0x44C8: | |
904 | case 0x44CC: | |
905 | case 0x44D0: | |
906 | case 0x44D4: | |
907 | case 0x44D8: | |
908 | case 0x44DC: | |
909 | case 0x44E0: | |
910 | case 0x44E4: | |
911 | case 0x44E8: | |
912 | case 0x44EC: | |
913 | case 0x44F0: | |
914 | case 0x44F4: | |
915 | case 0x44F8: | |
916 | case 0x44FC: | |
917 | /* TX_FORMAT1_[0-15] */ | |
918 | i = (reg - 0x44C0) >> 2; | |
513bcb46 | 919 | tmp = (idx_value >> 25) & 0x3; |
068a117c | 920 | track->textures[i].tex_coord_type = tmp; |
513bcb46 | 921 | switch ((idx_value & 0x1F)) { |
551ebd83 DA |
922 | case R300_TX_FORMAT_X8: |
923 | case R300_TX_FORMAT_Y4X4: | |
924 | case R300_TX_FORMAT_Z3Y3X2: | |
068a117c | 925 | track->textures[i].cpp = 1; |
f9da52d5 | 926 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 927 | break; |
551ebd83 | 928 | case R300_TX_FORMAT_X16: |
16e4b8a6 | 929 | case R300_TX_FORMAT_FL_I16: |
551ebd83 DA |
930 | case R300_TX_FORMAT_Y8X8: |
931 | case R300_TX_FORMAT_Z5Y6X5: | |
932 | case R300_TX_FORMAT_Z6Y5X5: | |
933 | case R300_TX_FORMAT_W4Z4Y4X4: | |
934 | case R300_TX_FORMAT_W1Z5Y5X5: | |
551ebd83 DA |
935 | case R300_TX_FORMAT_D3DMFT_CxV8U8: |
936 | case R300_TX_FORMAT_B8G8_B8G8: | |
937 | case R300_TX_FORMAT_G8R8_G8B8: | |
068a117c | 938 | track->textures[i].cpp = 2; |
f9da52d5 | 939 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 940 | break; |
551ebd83 | 941 | case R300_TX_FORMAT_Y16X16: |
16e4b8a6 | 942 | case R300_TX_FORMAT_FL_I16A16: |
551ebd83 DA |
943 | case R300_TX_FORMAT_Z11Y11X10: |
944 | case R300_TX_FORMAT_Z10Y11X11: | |
945 | case R300_TX_FORMAT_W8Z8Y8X8: | |
946 | case R300_TX_FORMAT_W2Z10Y10X10: | |
947 | case 0x17: | |
948 | case R300_TX_FORMAT_FL_I32: | |
949 | case 0x1e: | |
068a117c | 950 | track->textures[i].cpp = 4; |
f9da52d5 | 951 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 952 | break; |
551ebd83 DA |
953 | case R300_TX_FORMAT_W16Z16Y16X16: |
954 | case R300_TX_FORMAT_FL_R16G16B16A16: | |
955 | case R300_TX_FORMAT_FL_I32A32: | |
068a117c | 956 | track->textures[i].cpp = 8; |
f9da52d5 | 957 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 958 | break; |
551ebd83 | 959 | case R300_TX_FORMAT_FL_R32G32B32A32: |
068a117c | 960 | track->textures[i].cpp = 16; |
f9da52d5 | 961 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
068a117c | 962 | break; |
d785d78b DA |
963 | case R300_TX_FORMAT_DXT1: |
964 | track->textures[i].cpp = 1; | |
965 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; | |
966 | break; | |
512889f4 MO |
967 | case R300_TX_FORMAT_ATI2N: |
968 | if (p->rdev->family < CHIP_R420) { | |
969 | DRM_ERROR("Invalid texture format %u\n", | |
970 | (idx_value & 0x1F)); | |
971 | return -EINVAL; | |
972 | } | |
973 | /* The same rules apply as for DXT3/5. */ | |
df561f66 | 974 | fallthrough; |
d785d78b DA |
975 | case R300_TX_FORMAT_DXT3: |
976 | case R300_TX_FORMAT_DXT5: | |
977 | track->textures[i].cpp = 1; | |
978 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; | |
979 | break; | |
068a117c JG |
980 | default: |
981 | DRM_ERROR("Invalid texture format %u\n", | |
513bcb46 | 982 | (idx_value & 0x1F)); |
068a117c | 983 | return -EINVAL; |
068a117c | 984 | } |
40b4a759 | 985 | track->tex_dirty = true; |
068a117c JG |
986 | break; |
987 | case 0x4400: | |
988 | case 0x4404: | |
989 | case 0x4408: | |
990 | case 0x440C: | |
991 | case 0x4410: | |
992 | case 0x4414: | |
993 | case 0x4418: | |
994 | case 0x441C: | |
995 | case 0x4420: | |
996 | case 0x4424: | |
997 | case 0x4428: | |
998 | case 0x442C: | |
999 | case 0x4430: | |
1000 | case 0x4434: | |
1001 | case 0x4438: | |
1002 | case 0x443C: | |
1003 | /* TX_FILTER0_[0-15] */ | |
1004 | i = (reg - 0x4400) >> 2; | |
513bcb46 | 1005 | tmp = idx_value & 0x7; |
068a117c JG |
1006 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
1007 | track->textures[i].roundup_w = false; | |
1008 | } | |
513bcb46 | 1009 | tmp = (idx_value >> 3) & 0x7; |
068a117c JG |
1010 | if (tmp == 2 || tmp == 4 || tmp == 6) { |
1011 | track->textures[i].roundup_h = false; | |
1012 | } | |
40b4a759 | 1013 | track->tex_dirty = true; |
068a117c JG |
1014 | break; |
1015 | case 0x4500: | |
1016 | case 0x4504: | |
1017 | case 0x4508: | |
1018 | case 0x450C: | |
1019 | case 0x4510: | |
1020 | case 0x4514: | |
1021 | case 0x4518: | |
1022 | case 0x451C: | |
1023 | case 0x4520: | |
1024 | case 0x4524: | |
1025 | case 0x4528: | |
1026 | case 0x452C: | |
1027 | case 0x4530: | |
1028 | case 0x4534: | |
1029 | case 0x4538: | |
1030 | case 0x453C: | |
1031 | /* TX_FORMAT2_[0-15] */ | |
1032 | i = (reg - 0x4500) >> 2; | |
513bcb46 | 1033 | tmp = idx_value & 0x3FFF; |
068a117c JG |
1034 | track->textures[i].pitch = tmp + 1; |
1035 | if (p->rdev->family >= CHIP_RV515) { | |
513bcb46 | 1036 | tmp = ((idx_value >> 15) & 1) << 11; |
068a117c | 1037 | track->textures[i].width_11 = tmp; |
513bcb46 | 1038 | tmp = ((idx_value >> 16) & 1) << 11; |
068a117c | 1039 | track->textures[i].height_11 = tmp; |
512889f4 MO |
1040 | |
1041 | /* ATI1N */ | |
1042 | if (idx_value & (1 << 14)) { | |
1043 | /* The same rules apply as for DXT1. */ | |
1044 | track->textures[i].compress_format = | |
1045 | R100_TRACK_COMP_DXT1; | |
1046 | } | |
1047 | } else if (idx_value & (1 << 14)) { | |
1048 | DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); | |
1049 | return -EINVAL; | |
068a117c | 1050 | } |
40b4a759 | 1051 | track->tex_dirty = true; |
068a117c JG |
1052 | break; |
1053 | case 0x4480: | |
1054 | case 0x4484: | |
1055 | case 0x4488: | |
1056 | case 0x448C: | |
1057 | case 0x4490: | |
1058 | case 0x4494: | |
1059 | case 0x4498: | |
1060 | case 0x449C: | |
1061 | case 0x44A0: | |
1062 | case 0x44A4: | |
1063 | case 0x44A8: | |
1064 | case 0x44AC: | |
1065 | case 0x44B0: | |
1066 | case 0x44B4: | |
1067 | case 0x44B8: | |
1068 | case 0x44BC: | |
1069 | /* TX_FORMAT0_[0-15] */ | |
1070 | i = (reg - 0x4480) >> 2; | |
513bcb46 | 1071 | tmp = idx_value & 0x7FF; |
068a117c | 1072 | track->textures[i].width = tmp + 1; |
513bcb46 | 1073 | tmp = (idx_value >> 11) & 0x7FF; |
068a117c | 1074 | track->textures[i].height = tmp + 1; |
513bcb46 | 1075 | tmp = (idx_value >> 26) & 0xF; |
068a117c | 1076 | track->textures[i].num_levels = tmp; |
513bcb46 | 1077 | tmp = idx_value & (1 << 31); |
068a117c | 1078 | track->textures[i].use_pitch = !!tmp; |
513bcb46 | 1079 | tmp = (idx_value >> 22) & 0xF; |
068a117c | 1080 | track->textures[i].txdepth = tmp; |
40b4a759 | 1081 | track->tex_dirty = true; |
068a117c | 1082 | break; |
3f8befec | 1083 | case R300_ZB_ZPASS_ADDR: |
012e976d | 1084 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
3f8befec DA |
1085 | if (r) { |
1086 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1087 | idx, reg); | |
c3ad63af | 1088 | radeon_cs_dump_packet(p, pkt); |
3f8befec DA |
1089 | return r; |
1090 | } | |
df0af440 | 1091 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
3f8befec | 1092 | break; |
46c64d4b MO |
1093 | case 0x4e0c: |
1094 | /* RB3D_COLOR_CHANNEL_MASK */ | |
1095 | track->color_channel_mask = idx_value; | |
40b4a759 | 1096 | track->cb_dirty = true; |
46c64d4b | 1097 | break; |
ab9e1f59 DA |
1098 | case 0x43a4: |
1099 | /* SC_HYPERZ_EN */ | |
1100 | /* r300c emits this register - we need to disable hyperz for it | |
1101 | * without complaining */ | |
1102 | if (p->rdev->hyperz_filp != p->filp) { | |
1103 | if (idx_value & 0x1) | |
1104 | ib[idx] = idx_value & ~1; | |
1105 | } | |
1106 | break; | |
1107 | case 0x4f1c: | |
46c64d4b | 1108 | /* ZB_BW_CNTL */ |
797fd5b9 | 1109 | track->zb_cb_clear = !!(idx_value & (1 << 5)); |
40b4a759 MO |
1110 | track->cb_dirty = true; |
1111 | track->zb_dirty = true; | |
ab9e1f59 DA |
1112 | if (p->rdev->hyperz_filp != p->filp) { |
1113 | if (idx_value & (R300_HIZ_ENABLE | | |
1114 | R300_RD_COMP_ENABLE | | |
1115 | R300_WR_COMP_ENABLE | | |
1116 | R300_FAST_FILL_ENABLE)) | |
1117 | goto fail; | |
1118 | } | |
46c64d4b MO |
1119 | break; |
1120 | case 0x4e04: | |
1121 | /* RB3D_BLENDCNTL */ | |
1122 | track->blend_read_enable = !!(idx_value & (1 << 2)); | |
40b4a759 | 1123 | track->cb_dirty = true; |
46c64d4b | 1124 | break; |
fff1ce4d | 1125 | case R300_RB3D_AARESOLVE_OFFSET: |
012e976d | 1126 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
fff1ce4d MO |
1127 | if (r) { |
1128 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1129 | idx, reg); | |
c3ad63af | 1130 | radeon_cs_dump_packet(p, pkt); |
fff1ce4d MO |
1131 | return r; |
1132 | } | |
1133 | track->aa.robj = reloc->robj; | |
1134 | track->aa.offset = idx_value; | |
1135 | track->aa_dirty = true; | |
df0af440 | 1136 | ib[idx] = idx_value + ((u32)reloc->gpu_offset); |
fff1ce4d MO |
1137 | break; |
1138 | case R300_RB3D_AARESOLVE_PITCH: | |
1139 | track->aa.pitch = idx_value & 0x3FFE; | |
1140 | track->aa_dirty = true; | |
1141 | break; | |
1142 | case R300_RB3D_AARESOLVE_CTL: | |
1143 | track->aaresolve = idx_value & 0x1; | |
1144 | track->aa_dirty = true; | |
1145 | break; | |
ab9e1f59 DA |
1146 | case 0x4f30: /* ZB_MASK_OFFSET */ |
1147 | case 0x4f34: /* ZB_ZMASK_PITCH */ | |
1148 | case 0x4f44: /* ZB_HIZ_OFFSET */ | |
1149 | case 0x4f54: /* ZB_HIZ_PITCH */ | |
1150 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) | |
1151 | goto fail; | |
1152 | break; | |
1153 | case 0x4028: | |
1154 | if (idx_value && (p->rdev->hyperz_filp != p->filp)) | |
1155 | goto fail; | |
1156 | /* GB_Z_PEQ_CONFIG */ | |
1157 | if (p->rdev->family >= CHIP_RV350) | |
1158 | break; | |
1159 | goto fail; | |
1160 | break; | |
3f8befec DA |
1161 | case 0x4be8: |
1162 | /* valid register only on RV530 */ | |
1163 | if (p->rdev->family == CHIP_RV530) | |
1164 | break; | |
1165 | /* fallthrough do not move */ | |
771fe6b9 | 1166 | default: |
cae94b0a | 1167 | goto fail; |
771fe6b9 JG |
1168 | } |
1169 | return 0; | |
cae94b0a | 1170 | fail: |
7ca85295 | 1171 | pr_err("Forbidden register 0x%04X in cs at %d (val=%08x)\n", |
ab9e1f59 | 1172 | reg, idx, idx_value); |
cae94b0a | 1173 | return -EINVAL; |
771fe6b9 JG |
1174 | } |
1175 | ||
1176 | static int r300_packet3_check(struct radeon_cs_parser *p, | |
1177 | struct radeon_cs_packet *pkt) | |
1178 | { | |
1d0c0942 | 1179 | struct radeon_bo_list *reloc; |
551ebd83 | 1180 | struct r100_cs_track *track; |
771fe6b9 JG |
1181 | volatile uint32_t *ib; |
1182 | unsigned idx; | |
771fe6b9 JG |
1183 | int r; |
1184 | ||
f2e39221 | 1185 | ib = p->ib.ptr; |
771fe6b9 | 1186 | idx = pkt->idx + 1; |
551ebd83 | 1187 | track = (struct r100_cs_track *)p->track; |
068a117c | 1188 | switch(pkt->opcode) { |
771fe6b9 | 1189 | case PACKET3_3D_LOAD_VBPNTR: |
513bcb46 DA |
1190 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1191 | if (r) | |
1192 | return r; | |
771fe6b9 JG |
1193 | break; |
1194 | case PACKET3_INDX_BUFFER: | |
012e976d | 1195 | r = radeon_cs_packet_next_reloc(p, &reloc, 0); |
771fe6b9 JG |
1196 | if (r) { |
1197 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | |
c3ad63af | 1198 | radeon_cs_dump_packet(p, pkt); |
771fe6b9 JG |
1199 | return r; |
1200 | } | |
df0af440 | 1201 | ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); |
068a117c JG |
1202 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1203 | if (r) { | |
1204 | return r; | |
1205 | } | |
771fe6b9 JG |
1206 | break; |
1207 | /* Draw packet */ | |
771fe6b9 | 1208 | case PACKET3_3D_DRAW_IMMD: |
068a117c JG |
1209 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1210 | * PRIM_WALK must be equal to 3 vertex data in embedded | |
1211 | * in cmd stream */ | |
513bcb46 | 1212 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
068a117c JG |
1213 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1214 | return -EINVAL; | |
1215 | } | |
513bcb46 | 1216 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
068a117c | 1217 | track->immd_dwords = pkt->count - 1; |
551ebd83 | 1218 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1219 | if (r) { |
1220 | return r; | |
1221 | } | |
1222 | break; | |
771fe6b9 | 1223 | case PACKET3_3D_DRAW_IMMD_2: |
068a117c JG |
1224 | /* Number of dwords is vtx_size * (num_vertices - 1) |
1225 | * PRIM_WALK must be equal to 3 vertex data in embedded | |
1226 | * in cmd stream */ | |
513bcb46 | 1227 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
068a117c JG |
1228 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1229 | return -EINVAL; | |
1230 | } | |
513bcb46 | 1231 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
068a117c | 1232 | track->immd_dwords = pkt->count; |
551ebd83 | 1233 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1234 | if (r) { |
1235 | return r; | |
1236 | } | |
1237 | break; | |
1238 | case PACKET3_3D_DRAW_VBUF: | |
513bcb46 | 1239 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 | 1240 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1241 | if (r) { |
1242 | return r; | |
1243 | } | |
1244 | break; | |
1245 | case PACKET3_3D_DRAW_VBUF_2: | |
513bcb46 | 1246 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 | 1247 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1248 | if (r) { |
1249 | return r; | |
1250 | } | |
1251 | break; | |
1252 | case PACKET3_3D_DRAW_INDX: | |
513bcb46 | 1253 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 | 1254 | r = r100_cs_track_check(p->rdev, track); |
068a117c JG |
1255 | if (r) { |
1256 | return r; | |
1257 | } | |
1258 | break; | |
771fe6b9 | 1259 | case PACKET3_3D_DRAW_INDX_2: |
513bcb46 | 1260 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 | 1261 | r = r100_cs_track_check(p->rdev, track); |
771fe6b9 JG |
1262 | if (r) { |
1263 | return r; | |
1264 | } | |
1265 | break; | |
ab9e1f59 DA |
1266 | case PACKET3_3D_CLEAR_HIZ: |
1267 | case PACKET3_3D_CLEAR_ZMASK: | |
1268 | if (p->rdev->hyperz_filp != p->filp) | |
1269 | return -EINVAL; | |
1270 | break; | |
9eba4a93 MO |
1271 | case PACKET3_3D_CLEAR_CMASK: |
1272 | if (p->rdev->cmask_filp != p->filp) | |
1273 | return -EINVAL; | |
1274 | break; | |
771fe6b9 JG |
1275 | case PACKET3_NOP: |
1276 | break; | |
1277 | default: | |
1278 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); | |
1279 | return -EINVAL; | |
1280 | } | |
1281 | return 0; | |
1282 | } | |
1283 | ||
1284 | int r300_cs_parse(struct radeon_cs_parser *p) | |
1285 | { | |
1286 | struct radeon_cs_packet pkt; | |
9f022ddf | 1287 | struct r100_cs_track *track; |
771fe6b9 JG |
1288 | int r; |
1289 | ||
9f022ddf | 1290 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
bbb642f9 KV |
1291 | if (track == NULL) |
1292 | return -ENOMEM; | |
9f022ddf JG |
1293 | r100_cs_track_clear(p->rdev, track); |
1294 | p->track = track; | |
771fe6b9 | 1295 | do { |
c38f34b5 | 1296 | r = radeon_cs_packet_parse(p, &pkt, p->idx); |
771fe6b9 JG |
1297 | if (r) { |
1298 | return r; | |
1299 | } | |
1300 | p->idx += pkt.count + 2; | |
1301 | switch (pkt.type) { | |
4e872ae2 | 1302 | case RADEON_PACKET_TYPE0: |
771fe6b9 | 1303 | r = r100_cs_parse_packet0(p, &pkt, |
068a117c JG |
1304 | p->rdev->config.r300.reg_safe_bm, |
1305 | p->rdev->config.r300.reg_safe_bm_size, | |
771fe6b9 JG |
1306 | &r300_packet0_check); |
1307 | break; | |
4e872ae2 | 1308 | case RADEON_PACKET_TYPE2: |
771fe6b9 | 1309 | break; |
4e872ae2 | 1310 | case RADEON_PACKET_TYPE3: |
771fe6b9 JG |
1311 | r = r300_packet3_check(p, &pkt); |
1312 | break; | |
1313 | default: | |
1314 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); | |
1315 | return -EINVAL; | |
1316 | } | |
1317 | if (r) { | |
1318 | return r; | |
1319 | } | |
6d2d13dd | 1320 | } while (p->idx < p->chunk_ib->length_dw); |
771fe6b9 JG |
1321 | return 0; |
1322 | } | |
068a117c | 1323 | |
9f022ddf | 1324 | void r300_set_reg_safe(struct radeon_device *rdev) |
068a117c JG |
1325 | { |
1326 | rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; | |
1327 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); | |
9f022ddf JG |
1328 | } |
1329 | ||
9f022ddf JG |
1330 | void r300_mc_program(struct radeon_device *rdev) |
1331 | { | |
1332 | struct r100_mc_save save; | |
1333 | int r; | |
1334 | ||
1335 | r = r100_debugfs_mc_info_init(rdev); | |
1336 | if (r) { | |
1337 | dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); | |
1338 | } | |
1339 | ||
1340 | /* Stops all mc clients */ | |
1341 | r100_mc_stop(rdev, &save); | |
9f022ddf JG |
1342 | if (rdev->flags & RADEON_IS_AGP) { |
1343 | WREG32(R_00014C_MC_AGP_LOCATION, | |
1344 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
1345 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
1346 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
1347 | WREG32(R_00015C_AGP_BASE_2, | |
1348 | upper_32_bits(rdev->mc.agp_base) & 0xff); | |
1349 | } else { | |
1350 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); | |
1351 | WREG32(R_000170_AGP_BASE, 0); | |
1352 | WREG32(R_00015C_AGP_BASE_2, 0); | |
1353 | } | |
1354 | /* Wait for mc idle */ | |
1355 | if (r300_mc_wait_for_idle(rdev)) | |
1356 | DRM_INFO("Failed to wait MC idle before programming MC.\n"); | |
1357 | /* Program MC, should be a 32bits limited address space */ | |
1358 | WREG32(R_000148_MC_FB_LOCATION, | |
1359 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | | |
1360 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
1361 | r100_mc_resume(rdev, &save); | |
1362 | } | |
ca6ffc64 JG |
1363 | |
1364 | void r300_clock_startup(struct radeon_device *rdev) | |
1365 | { | |
1366 | u32 tmp; | |
1367 | ||
1368 | if (radeon_dynclks != -1 && radeon_dynclks) | |
1369 | radeon_legacy_set_clock_gating(rdev, 1); | |
1370 | /* We need to force on some of the block */ | |
1371 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); | |
1372 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); | |
1373 | if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) | |
1374 | tmp |= S_00000D_FORCE_VAP(1); | |
1375 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); | |
1376 | } | |
207bf9e9 JG |
1377 | |
1378 | static int r300_startup(struct radeon_device *rdev) | |
1379 | { | |
1380 | int r; | |
1381 | ||
92cde00c AD |
1382 | /* set common regs */ |
1383 | r100_set_common_regs(rdev); | |
1384 | /* program mc */ | |
207bf9e9 JG |
1385 | r300_mc_program(rdev); |
1386 | /* Resume clock */ | |
1387 | r300_clock_startup(rdev); | |
1388 | /* Initialize GPU configuration (# pipes, ...) */ | |
1389 | r300_gpu_init(rdev); | |
1390 | /* Initialize GART (initialize after TTM so we can allocate | |
1391 | * memory through TTM but finalize after TTM) */ | |
1392 | if (rdev->flags & RADEON_IS_PCIE) { | |
1393 | r = rv370_pcie_gart_enable(rdev); | |
1394 | if (r) | |
1395 | return r; | |
1396 | } | |
17e15b0c DA |
1397 | |
1398 | if (rdev->family == CHIP_R300 || | |
1399 | rdev->family == CHIP_R350 || | |
1400 | rdev->family == CHIP_RV350) | |
1401 | r100_enable_bm(rdev); | |
1402 | ||
207bf9e9 JG |
1403 | if (rdev->flags & RADEON_IS_PCI) { |
1404 | r = r100_pci_gart_enable(rdev); | |
1405 | if (r) | |
1406 | return r; | |
1407 | } | |
724c80e1 AD |
1408 | |
1409 | /* allocate wb buffer */ | |
1410 | r = radeon_wb_init(rdev); | |
1411 | if (r) | |
1412 | return r; | |
1413 | ||
30eb77f4 JG |
1414 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
1415 | if (r) { | |
1416 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); | |
1417 | return r; | |
1418 | } | |
1419 | ||
207bf9e9 | 1420 | /* Enable IRQ */ |
e49f3959 AH |
1421 | if (!rdev->irq.installed) { |
1422 | r = radeon_irq_kms_init(rdev); | |
1423 | if (r) | |
1424 | return r; | |
1425 | } | |
1426 | ||
207bf9e9 | 1427 | r100_irq_set(rdev); |
cafe6609 | 1428 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
207bf9e9 JG |
1429 | /* 1M ring buffer */ |
1430 | r = r100_cp_init(rdev, 1024 * 1024); | |
1431 | if (r) { | |
ec4f2ac4 | 1432 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
207bf9e9 JG |
1433 | return r; |
1434 | } | |
b15ba512 | 1435 | |
2898c348 CK |
1436 | r = radeon_ib_pool_init(rdev); |
1437 | if (r) { | |
1438 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); | |
b15ba512 | 1439 | return r; |
2898c348 | 1440 | } |
b15ba512 | 1441 | |
207bf9e9 JG |
1442 | return 0; |
1443 | } | |
1444 | ||
1445 | int r300_resume(struct radeon_device *rdev) | |
1446 | { | |
6b7746e8 JG |
1447 | int r; |
1448 | ||
207bf9e9 JG |
1449 | /* Make sur GART are not working */ |
1450 | if (rdev->flags & RADEON_IS_PCIE) | |
1451 | rv370_pcie_gart_disable(rdev); | |
1452 | if (rdev->flags & RADEON_IS_PCI) | |
1453 | r100_pci_gart_disable(rdev); | |
1454 | /* Resume clock before doing reset */ | |
1455 | r300_clock_startup(rdev); | |
1456 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 1457 | if (radeon_asic_reset(rdev)) { |
207bf9e9 JG |
1458 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
1459 | RREG32(R_000E40_RBBM_STATUS), | |
1460 | RREG32(R_0007C0_CP_STAT)); | |
1461 | } | |
1462 | /* post */ | |
1463 | radeon_combios_asic_init(rdev->ddev); | |
1464 | /* Resume clock after posting */ | |
1465 | r300_clock_startup(rdev); | |
550e2d92 DA |
1466 | /* Initialize surface registers */ |
1467 | radeon_surface_init(rdev); | |
b15ba512 JG |
1468 | |
1469 | rdev->accel_working = true; | |
6b7746e8 JG |
1470 | r = r300_startup(rdev); |
1471 | if (r) { | |
1472 | rdev->accel_working = false; | |
1473 | } | |
1474 | return r; | |
207bf9e9 JG |
1475 | } |
1476 | ||
1477 | int r300_suspend(struct radeon_device *rdev) | |
1478 | { | |
6c7bccea | 1479 | radeon_pm_suspend(rdev); |
207bf9e9 | 1480 | r100_cp_disable(rdev); |
724c80e1 | 1481 | radeon_wb_disable(rdev); |
207bf9e9 JG |
1482 | r100_irq_disable(rdev); |
1483 | if (rdev->flags & RADEON_IS_PCIE) | |
1484 | rv370_pcie_gart_disable(rdev); | |
1485 | if (rdev->flags & RADEON_IS_PCI) | |
1486 | r100_pci_gart_disable(rdev); | |
1487 | return 0; | |
1488 | } | |
1489 | ||
1490 | void r300_fini(struct radeon_device *rdev) | |
1491 | { | |
6c7bccea | 1492 | radeon_pm_fini(rdev); |
207bf9e9 | 1493 | r100_cp_fini(rdev); |
724c80e1 | 1494 | radeon_wb_fini(rdev); |
2898c348 | 1495 | radeon_ib_pool_fini(rdev); |
207bf9e9 JG |
1496 | radeon_gem_fini(rdev); |
1497 | if (rdev->flags & RADEON_IS_PCIE) | |
1498 | rv370_pcie_gart_fini(rdev); | |
1499 | if (rdev->flags & RADEON_IS_PCI) | |
1500 | r100_pci_gart_fini(rdev); | |
d0269ed8 | 1501 | radeon_agp_fini(rdev); |
207bf9e9 JG |
1502 | radeon_irq_kms_fini(rdev); |
1503 | radeon_fence_driver_fini(rdev); | |
4c788679 | 1504 | radeon_bo_fini(rdev); |
207bf9e9 JG |
1505 | radeon_atombios_fini(rdev); |
1506 | kfree(rdev->bios); | |
1507 | rdev->bios = NULL; | |
1508 | } | |
1509 | ||
1510 | int r300_init(struct radeon_device *rdev) | |
1511 | { | |
1512 | int r; | |
1513 | ||
207bf9e9 JG |
1514 | /* Disable VGA */ |
1515 | r100_vga_render_disable(rdev); | |
1516 | /* Initialize scratch registers */ | |
1517 | radeon_scratch_init(rdev); | |
1518 | /* Initialize surface registers */ | |
1519 | radeon_surface_init(rdev); | |
1520 | /* TODO: disable VGA need to use VGA request */ | |
4c712e6c DA |
1521 | /* restore some register to sane defaults */ |
1522 | r100_restore_sanity(rdev); | |
207bf9e9 JG |
1523 | /* BIOS*/ |
1524 | if (!radeon_get_bios(rdev)) { | |
1525 | if (ASIC_IS_AVIVO(rdev)) | |
1526 | return -EINVAL; | |
1527 | } | |
1528 | if (rdev->is_atom_bios) { | |
1529 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); | |
1530 | return -EINVAL; | |
1531 | } else { | |
1532 | r = radeon_combios_init(rdev); | |
1533 | if (r) | |
1534 | return r; | |
1535 | } | |
1536 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 1537 | if (radeon_asic_reset(rdev)) { |
207bf9e9 JG |
1538 | dev_warn(rdev->dev, |
1539 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
1540 | RREG32(R_000E40_RBBM_STATUS), | |
1541 | RREG32(R_0007C0_CP_STAT)); | |
1542 | } | |
1543 | /* check if cards are posted or not */ | |
72542d77 DA |
1544 | if (radeon_boot_test_post_card(rdev) == false) |
1545 | return -EINVAL; | |
207bf9e9 JG |
1546 | /* Set asic errata */ |
1547 | r300_errata(rdev); | |
1548 | /* Initialize clocks */ | |
1549 | radeon_get_clock_info(rdev->ddev); | |
d594e46a JG |
1550 | /* initialize AGP */ |
1551 | if (rdev->flags & RADEON_IS_AGP) { | |
1552 | r = radeon_agp_init(rdev); | |
1553 | if (r) { | |
1554 | radeon_agp_disable(rdev); | |
1555 | } | |
1556 | } | |
1557 | /* initialize memory controller */ | |
1558 | r300_mc_init(rdev); | |
207bf9e9 | 1559 | /* Fence driver */ |
30eb77f4 | 1560 | r = radeon_fence_driver_init(rdev); |
207bf9e9 JG |
1561 | if (r) |
1562 | return r; | |
1563 | /* Memory manager */ | |
4c788679 | 1564 | r = radeon_bo_init(rdev); |
207bf9e9 JG |
1565 | if (r) |
1566 | return r; | |
1567 | if (rdev->flags & RADEON_IS_PCIE) { | |
1568 | r = rv370_pcie_gart_init(rdev); | |
1569 | if (r) | |
1570 | return r; | |
1571 | } | |
1572 | if (rdev->flags & RADEON_IS_PCI) { | |
1573 | r = r100_pci_gart_init(rdev); | |
1574 | if (r) | |
1575 | return r; | |
1576 | } | |
1577 | r300_set_reg_safe(rdev); | |
b15ba512 | 1578 | |
6c7bccea AD |
1579 | /* Initialize power management */ |
1580 | radeon_pm_init(rdev); | |
1581 | ||
207bf9e9 JG |
1582 | rdev->accel_working = true; |
1583 | r = r300_startup(rdev); | |
1584 | if (r) { | |
0dc5d4f7 | 1585 | /* Something went wrong with the accel init, so stop accel */ |
207bf9e9 | 1586 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
207bf9e9 | 1587 | r100_cp_fini(rdev); |
724c80e1 | 1588 | radeon_wb_fini(rdev); |
2898c348 | 1589 | radeon_ib_pool_fini(rdev); |
655efd3d | 1590 | radeon_irq_kms_fini(rdev); |
207bf9e9 JG |
1591 | if (rdev->flags & RADEON_IS_PCIE) |
1592 | rv370_pcie_gart_fini(rdev); | |
1593 | if (rdev->flags & RADEON_IS_PCI) | |
1594 | r100_pci_gart_fini(rdev); | |
655efd3d | 1595 | radeon_agp_fini(rdev); |
207bf9e9 JG |
1596 | rdev->accel_working = false; |
1597 | } | |
1598 | return 0; | |
1599 | } |