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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/seq_file.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
771fe6b9 JG |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "radeon_drm.h" | |
771fe6b9 JG |
33 | #include "radeon_reg.h" |
34 | #include "radeon.h" | |
e6990375 | 35 | #include "radeon_asic.h" |
3ce0a23d | 36 | #include "r100d.h" |
d4550907 JG |
37 | #include "rs100d.h" |
38 | #include "rv200d.h" | |
39 | #include "rv250d.h" | |
49e02b73 | 40 | #include "atom.h" |
3ce0a23d | 41 | |
70967ab9 BH |
42 | #include <linux/firmware.h> |
43 | #include <linux/platform_device.h> | |
44 | ||
551ebd83 DA |
45 | #include "r100_reg_safe.h" |
46 | #include "rn50_reg_safe.h" | |
47 | ||
70967ab9 BH |
48 | /* Firmware Names */ |
49 | #define FIRMWARE_R100 "radeon/R100_cp.bin" | |
50 | #define FIRMWARE_R200 "radeon/R200_cp.bin" | |
51 | #define FIRMWARE_R300 "radeon/R300_cp.bin" | |
52 | #define FIRMWARE_R420 "radeon/R420_cp.bin" | |
53 | #define FIRMWARE_RS690 "radeon/RS690_cp.bin" | |
54 | #define FIRMWARE_RS600 "radeon/RS600_cp.bin" | |
55 | #define FIRMWARE_R520 "radeon/R520_cp.bin" | |
56 | ||
57 | MODULE_FIRMWARE(FIRMWARE_R100); | |
58 | MODULE_FIRMWARE(FIRMWARE_R200); | |
59 | MODULE_FIRMWARE(FIRMWARE_R300); | |
60 | MODULE_FIRMWARE(FIRMWARE_R420); | |
61 | MODULE_FIRMWARE(FIRMWARE_RS690); | |
62 | MODULE_FIRMWARE(FIRMWARE_RS600); | |
63 | MODULE_FIRMWARE(FIRMWARE_R520); | |
771fe6b9 | 64 | |
551ebd83 DA |
65 | #include "r100_track.h" |
66 | ||
771fe6b9 JG |
67 | /* This files gather functions specifics to: |
68 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 | |
771fe6b9 | 69 | */ |
771fe6b9 | 70 | |
ce8f5370 | 71 | void r100_pm_get_dynpm_state(struct radeon_device *rdev) |
a48b9b4e AD |
72 | { |
73 | int i; | |
ce8f5370 AD |
74 | rdev->pm.dynpm_can_upclock = true; |
75 | rdev->pm.dynpm_can_downclock = true; | |
a48b9b4e | 76 | |
ce8f5370 AD |
77 | switch (rdev->pm.dynpm_planned_action) { |
78 | case DYNPM_ACTION_MINIMUM: | |
a48b9b4e | 79 | rdev->pm.requested_power_state_index = 0; |
ce8f5370 | 80 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e | 81 | break; |
ce8f5370 | 82 | case DYNPM_ACTION_DOWNCLOCK: |
a48b9b4e AD |
83 | if (rdev->pm.current_power_state_index == 0) { |
84 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 85 | rdev->pm.dynpm_can_downclock = false; |
a48b9b4e AD |
86 | } else { |
87 | if (rdev->pm.active_crtc_count > 1) { | |
88 | for (i = 0; i < rdev->pm.num_power_states; i++) { | |
d7311171 | 89 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
90 | continue; |
91 | else if (i >= rdev->pm.current_power_state_index) { | |
92 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
93 | break; | |
94 | } else { | |
95 | rdev->pm.requested_power_state_index = i; | |
96 | break; | |
97 | } | |
98 | } | |
99 | } else | |
100 | rdev->pm.requested_power_state_index = | |
101 | rdev->pm.current_power_state_index - 1; | |
102 | } | |
d7311171 AD |
103 | /* don't use the power state if crtcs are active and no display flag is set */ |
104 | if ((rdev->pm.active_crtc_count > 0) && | |
105 | (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & | |
106 | RADEON_PM_MODE_NO_DISPLAY)) { | |
107 | rdev->pm.requested_power_state_index++; | |
108 | } | |
a48b9b4e | 109 | break; |
ce8f5370 | 110 | case DYNPM_ACTION_UPCLOCK: |
a48b9b4e AD |
111 | if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { |
112 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
ce8f5370 | 113 | rdev->pm.dynpm_can_upclock = false; |
a48b9b4e AD |
114 | } else { |
115 | if (rdev->pm.active_crtc_count > 1) { | |
116 | for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { | |
d7311171 | 117 | if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) |
a48b9b4e AD |
118 | continue; |
119 | else if (i <= rdev->pm.current_power_state_index) { | |
120 | rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; | |
121 | break; | |
122 | } else { | |
123 | rdev->pm.requested_power_state_index = i; | |
124 | break; | |
125 | } | |
126 | } | |
127 | } else | |
128 | rdev->pm.requested_power_state_index = | |
129 | rdev->pm.current_power_state_index + 1; | |
130 | } | |
131 | break; | |
ce8f5370 | 132 | case DYNPM_ACTION_DEFAULT: |
58e21dff | 133 | rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; |
ce8f5370 | 134 | rdev->pm.dynpm_can_upclock = false; |
58e21dff | 135 | break; |
ce8f5370 | 136 | case DYNPM_ACTION_NONE: |
a48b9b4e AD |
137 | default: |
138 | DRM_ERROR("Requested mode for not defined action\n"); | |
139 | return; | |
140 | } | |
141 | /* only one clock mode per power state */ | |
142 | rdev->pm.requested_clock_mode_index = 0; | |
143 | ||
ce8a3eb2 AD |
144 | DRM_DEBUG("Requested: e: %d m: %d p: %d\n", |
145 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
146 | clock_info[rdev->pm.requested_clock_mode_index].sclk, | |
147 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
148 | clock_info[rdev->pm.requested_clock_mode_index].mclk, | |
149 | rdev->pm.power_state[rdev->pm.requested_power_state_index]. | |
150 | pcie_lanes); | |
a48b9b4e AD |
151 | } |
152 | ||
ce8f5370 AD |
153 | void r100_pm_init_profile(struct radeon_device *rdev) |
154 | { | |
155 | /* default */ | |
156 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; | |
157 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
158 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; | |
159 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; | |
160 | /* low sh */ | |
161 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; | |
162 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; | |
163 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; | |
164 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; | |
165 | /* high sh */ | |
166 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; | |
167 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
168 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; | |
169 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; | |
170 | /* low mh */ | |
171 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; | |
172 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
173 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; | |
174 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; | |
175 | /* high mh */ | |
176 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; | |
177 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; | |
178 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; | |
179 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; | |
bae6b562 AD |
180 | } |
181 | ||
49e02b73 AD |
182 | void r100_pm_misc(struct radeon_device *rdev) |
183 | { | |
49e02b73 AD |
184 | int requested_index = rdev->pm.requested_power_state_index; |
185 | struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; | |
186 | struct radeon_voltage *voltage = &ps->clock_info[0].voltage; | |
187 | u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; | |
188 | ||
189 | if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { | |
190 | if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { | |
191 | tmp = RREG32(voltage->gpio.reg); | |
192 | if (voltage->active_high) | |
193 | tmp |= voltage->gpio.mask; | |
194 | else | |
195 | tmp &= ~(voltage->gpio.mask); | |
196 | WREG32(voltage->gpio.reg, tmp); | |
197 | if (voltage->delay) | |
198 | udelay(voltage->delay); | |
199 | } else { | |
200 | tmp = RREG32(voltage->gpio.reg); | |
201 | if (voltage->active_high) | |
202 | tmp &= ~voltage->gpio.mask; | |
203 | else | |
204 | tmp |= voltage->gpio.mask; | |
205 | WREG32(voltage->gpio.reg, tmp); | |
206 | if (voltage->delay) | |
207 | udelay(voltage->delay); | |
208 | } | |
209 | } | |
210 | ||
211 | sclk_cntl = RREG32_PLL(SCLK_CNTL); | |
212 | sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); | |
213 | sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); | |
214 | sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); | |
215 | sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); | |
216 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { | |
217 | sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; | |
218 | if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) | |
219 | sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; | |
220 | else | |
221 | sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; | |
222 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) | |
223 | sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); | |
224 | else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) | |
225 | sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); | |
226 | } else | |
227 | sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; | |
228 | ||
229 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { | |
230 | sclk_more_cntl |= IO_CG_VOLTAGE_DROP; | |
231 | if (voltage->delay) { | |
232 | sclk_more_cntl |= VOLTAGE_DROP_SYNC; | |
233 | switch (voltage->delay) { | |
234 | case 33: | |
235 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); | |
236 | break; | |
237 | case 66: | |
238 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); | |
239 | break; | |
240 | case 99: | |
241 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); | |
242 | break; | |
243 | case 132: | |
244 | sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); | |
245 | break; | |
246 | } | |
247 | } else | |
248 | sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; | |
249 | } else | |
250 | sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; | |
251 | ||
252 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) | |
253 | sclk_cntl &= ~FORCE_HDP; | |
254 | else | |
255 | sclk_cntl |= FORCE_HDP; | |
256 | ||
257 | WREG32_PLL(SCLK_CNTL, sclk_cntl); | |
258 | WREG32_PLL(SCLK_CNTL2, sclk_cntl2); | |
259 | WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); | |
260 | ||
261 | /* set pcie lanes */ | |
262 | if ((rdev->flags & RADEON_IS_PCIE) && | |
263 | !(rdev->flags & RADEON_IS_IGP) && | |
264 | rdev->asic->set_pcie_lanes && | |
265 | (ps->pcie_lanes != | |
266 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { | |
267 | radeon_set_pcie_lanes(rdev, | |
268 | ps->pcie_lanes); | |
ce8a3eb2 | 269 | DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); |
49e02b73 | 270 | } |
49e02b73 AD |
271 | } |
272 | ||
273 | void r100_pm_prepare(struct radeon_device *rdev) | |
274 | { | |
275 | struct drm_device *ddev = rdev->ddev; | |
276 | struct drm_crtc *crtc; | |
277 | struct radeon_crtc *radeon_crtc; | |
278 | u32 tmp; | |
279 | ||
280 | /* disable any active CRTCs */ | |
281 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
282 | radeon_crtc = to_radeon_crtc(crtc); | |
283 | if (radeon_crtc->enabled) { | |
284 | if (radeon_crtc->crtc_id) { | |
285 | tmp = RREG32(RADEON_CRTC2_GEN_CNTL); | |
286 | tmp |= RADEON_CRTC2_DISP_REQ_EN_B; | |
287 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); | |
288 | } else { | |
289 | tmp = RREG32(RADEON_CRTC_GEN_CNTL); | |
290 | tmp |= RADEON_CRTC_DISP_REQ_EN_B; | |
291 | WREG32(RADEON_CRTC_GEN_CNTL, tmp); | |
292 | } | |
293 | } | |
294 | } | |
295 | } | |
296 | ||
297 | void r100_pm_finish(struct radeon_device *rdev) | |
298 | { | |
299 | struct drm_device *ddev = rdev->ddev; | |
300 | struct drm_crtc *crtc; | |
301 | struct radeon_crtc *radeon_crtc; | |
302 | u32 tmp; | |
303 | ||
304 | /* enable any active CRTCs */ | |
305 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { | |
306 | radeon_crtc = to_radeon_crtc(crtc); | |
307 | if (radeon_crtc->enabled) { | |
308 | if (radeon_crtc->crtc_id) { | |
309 | tmp = RREG32(RADEON_CRTC2_GEN_CNTL); | |
310 | tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; | |
311 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); | |
312 | } else { | |
313 | tmp = RREG32(RADEON_CRTC_GEN_CNTL); | |
314 | tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; | |
315 | WREG32(RADEON_CRTC_GEN_CNTL, tmp); | |
316 | } | |
317 | } | |
318 | } | |
319 | } | |
320 | ||
def9ba9c AD |
321 | bool r100_gui_idle(struct radeon_device *rdev) |
322 | { | |
323 | if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) | |
324 | return false; | |
325 | else | |
326 | return true; | |
327 | } | |
328 | ||
05a05c50 AD |
329 | /* hpd for digital panel detect/disconnect */ |
330 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |
331 | { | |
332 | bool connected = false; | |
333 | ||
334 | switch (hpd) { | |
335 | case RADEON_HPD_1: | |
336 | if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) | |
337 | connected = true; | |
338 | break; | |
339 | case RADEON_HPD_2: | |
340 | if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) | |
341 | connected = true; | |
342 | break; | |
343 | default: | |
344 | break; | |
345 | } | |
346 | return connected; | |
347 | } | |
348 | ||
349 | void r100_hpd_set_polarity(struct radeon_device *rdev, | |
350 | enum radeon_hpd_id hpd) | |
351 | { | |
352 | u32 tmp; | |
353 | bool connected = r100_hpd_sense(rdev, hpd); | |
354 | ||
355 | switch (hpd) { | |
356 | case RADEON_HPD_1: | |
357 | tmp = RREG32(RADEON_FP_GEN_CNTL); | |
358 | if (connected) | |
359 | tmp &= ~RADEON_FP_DETECT_INT_POL; | |
360 | else | |
361 | tmp |= RADEON_FP_DETECT_INT_POL; | |
362 | WREG32(RADEON_FP_GEN_CNTL, tmp); | |
363 | break; | |
364 | case RADEON_HPD_2: | |
365 | tmp = RREG32(RADEON_FP2_GEN_CNTL); | |
366 | if (connected) | |
367 | tmp &= ~RADEON_FP2_DETECT_INT_POL; | |
368 | else | |
369 | tmp |= RADEON_FP2_DETECT_INT_POL; | |
370 | WREG32(RADEON_FP2_GEN_CNTL, tmp); | |
371 | break; | |
372 | default: | |
373 | break; | |
374 | } | |
375 | } | |
376 | ||
377 | void r100_hpd_init(struct radeon_device *rdev) | |
378 | { | |
379 | struct drm_device *dev = rdev->ddev; | |
380 | struct drm_connector *connector; | |
381 | ||
382 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
383 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
384 | switch (radeon_connector->hpd.hpd) { | |
385 | case RADEON_HPD_1: | |
386 | rdev->irq.hpd[0] = true; | |
387 | break; | |
388 | case RADEON_HPD_2: | |
389 | rdev->irq.hpd[1] = true; | |
390 | break; | |
391 | default: | |
392 | break; | |
393 | } | |
394 | } | |
003e69f9 JG |
395 | if (rdev->irq.installed) |
396 | r100_irq_set(rdev); | |
05a05c50 AD |
397 | } |
398 | ||
399 | void r100_hpd_fini(struct radeon_device *rdev) | |
400 | { | |
401 | struct drm_device *dev = rdev->ddev; | |
402 | struct drm_connector *connector; | |
403 | ||
404 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
405 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | |
406 | switch (radeon_connector->hpd.hpd) { | |
407 | case RADEON_HPD_1: | |
408 | rdev->irq.hpd[0] = false; | |
409 | break; | |
410 | case RADEON_HPD_2: | |
411 | rdev->irq.hpd[1] = false; | |
412 | break; | |
413 | default: | |
414 | break; | |
415 | } | |
416 | } | |
417 | } | |
418 | ||
771fe6b9 JG |
419 | /* |
420 | * PCI GART | |
421 | */ | |
422 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev) | |
423 | { | |
424 | /* TODO: can we do somethings here ? */ | |
425 | /* It seems hw only cache one entry so we should discard this | |
426 | * entry otherwise if first GPU GART read hit this entry it | |
427 | * could end up in wrong address. */ | |
428 | } | |
429 | ||
4aac0473 | 430 | int r100_pci_gart_init(struct radeon_device *rdev) |
771fe6b9 | 431 | { |
771fe6b9 JG |
432 | int r; |
433 | ||
4aac0473 JG |
434 | if (rdev->gart.table.ram.ptr) { |
435 | WARN(1, "R100 PCI GART already initialized.\n"); | |
436 | return 0; | |
437 | } | |
771fe6b9 JG |
438 | /* Initialize common gart structure */ |
439 | r = radeon_gart_init(rdev); | |
4aac0473 | 440 | if (r) |
771fe6b9 | 441 | return r; |
4aac0473 JG |
442 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
443 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; | |
444 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; | |
445 | return radeon_gart_table_ram_alloc(rdev); | |
446 | } | |
447 | ||
17e15b0c DA |
448 | /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ |
449 | void r100_enable_bm(struct radeon_device *rdev) | |
450 | { | |
451 | uint32_t tmp; | |
452 | /* Enable bus mastering */ | |
453 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; | |
454 | WREG32(RADEON_BUS_CNTL, tmp); | |
455 | } | |
456 | ||
4aac0473 JG |
457 | int r100_pci_gart_enable(struct radeon_device *rdev) |
458 | { | |
459 | uint32_t tmp; | |
460 | ||
82568565 | 461 | radeon_gart_restore(rdev); |
771fe6b9 JG |
462 | /* discard memory request outside of configured range */ |
463 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; | |
464 | WREG32(RADEON_AIC_CNTL, tmp); | |
465 | /* set address range for PCI address translate */ | |
d594e46a JG |
466 | WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); |
467 | WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); | |
771fe6b9 JG |
468 | /* set PCI GART page-table base address */ |
469 | WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); | |
470 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; | |
471 | WREG32(RADEON_AIC_CNTL, tmp); | |
472 | r100_pci_gart_tlb_flush(rdev); | |
473 | rdev->gart.ready = true; | |
474 | return 0; | |
475 | } | |
476 | ||
477 | void r100_pci_gart_disable(struct radeon_device *rdev) | |
478 | { | |
479 | uint32_t tmp; | |
480 | ||
481 | /* discard memory request outside of configured range */ | |
482 | tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; | |
483 | WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); | |
484 | WREG32(RADEON_AIC_LO_ADDR, 0); | |
485 | WREG32(RADEON_AIC_HI_ADDR, 0); | |
486 | } | |
487 | ||
488 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) | |
489 | { | |
490 | if (i < 0 || i > rdev->gart.num_gpu_pages) { | |
491 | return -EINVAL; | |
492 | } | |
ed10f95d | 493 | rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr)); |
771fe6b9 JG |
494 | return 0; |
495 | } | |
496 | ||
4aac0473 | 497 | void r100_pci_gart_fini(struct radeon_device *rdev) |
771fe6b9 | 498 | { |
f9274562 | 499 | radeon_gart_fini(rdev); |
4aac0473 JG |
500 | r100_pci_gart_disable(rdev); |
501 | radeon_gart_table_ram_free(rdev); | |
771fe6b9 JG |
502 | } |
503 | ||
7ed220d7 MD |
504 | int r100_irq_set(struct radeon_device *rdev) |
505 | { | |
506 | uint32_t tmp = 0; | |
507 | ||
003e69f9 JG |
508 | if (!rdev->irq.installed) { |
509 | WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); | |
510 | WREG32(R_000040_GEN_INT_CNTL, 0); | |
511 | return -EINVAL; | |
512 | } | |
7ed220d7 MD |
513 | if (rdev->irq.sw_int) { |
514 | tmp |= RADEON_SW_INT_ENABLE; | |
515 | } | |
2031f77c AD |
516 | if (rdev->irq.gui_idle) { |
517 | tmp |= RADEON_GUI_IDLE_MASK; | |
518 | } | |
7ed220d7 MD |
519 | if (rdev->irq.crtc_vblank_int[0]) { |
520 | tmp |= RADEON_CRTC_VBLANK_MASK; | |
521 | } | |
522 | if (rdev->irq.crtc_vblank_int[1]) { | |
523 | tmp |= RADEON_CRTC2_VBLANK_MASK; | |
524 | } | |
05a05c50 AD |
525 | if (rdev->irq.hpd[0]) { |
526 | tmp |= RADEON_FP_DETECT_MASK; | |
527 | } | |
528 | if (rdev->irq.hpd[1]) { | |
529 | tmp |= RADEON_FP2_DETECT_MASK; | |
530 | } | |
7ed220d7 MD |
531 | WREG32(RADEON_GEN_INT_CNTL, tmp); |
532 | return 0; | |
533 | } | |
534 | ||
9f022ddf JG |
535 | void r100_irq_disable(struct radeon_device *rdev) |
536 | { | |
537 | u32 tmp; | |
538 | ||
539 | WREG32(R_000040_GEN_INT_CNTL, 0); | |
540 | /* Wait and acknowledge irq */ | |
541 | mdelay(1); | |
542 | tmp = RREG32(R_000044_GEN_INT_STATUS); | |
543 | WREG32(R_000044_GEN_INT_STATUS, tmp); | |
544 | } | |
545 | ||
7ed220d7 MD |
546 | static inline uint32_t r100_irq_ack(struct radeon_device *rdev) |
547 | { | |
548 | uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); | |
05a05c50 AD |
549 | uint32_t irq_mask = RADEON_SW_INT_TEST | |
550 | RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | | |
551 | RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; | |
7ed220d7 | 552 | |
2031f77c AD |
553 | /* the interrupt works, but the status bit is permanently asserted */ |
554 | if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) { | |
555 | if (!rdev->irq.gui_idle_acked) | |
556 | irq_mask |= RADEON_GUI_IDLE_STAT; | |
557 | } | |
558 | ||
7ed220d7 MD |
559 | if (irqs) { |
560 | WREG32(RADEON_GEN_INT_STATUS, irqs); | |
561 | } | |
562 | return irqs & irq_mask; | |
563 | } | |
564 | ||
565 | int r100_irq_process(struct radeon_device *rdev) | |
566 | { | |
3e5cb98d | 567 | uint32_t status, msi_rearm; |
d4877cf2 | 568 | bool queue_hotplug = false; |
7ed220d7 | 569 | |
2031f77c AD |
570 | /* reset gui idle ack. the status bit is broken */ |
571 | rdev->irq.gui_idle_acked = false; | |
572 | ||
7ed220d7 MD |
573 | status = r100_irq_ack(rdev); |
574 | if (!status) { | |
575 | return IRQ_NONE; | |
576 | } | |
a513c184 JG |
577 | if (rdev->shutdown) { |
578 | return IRQ_NONE; | |
579 | } | |
7ed220d7 MD |
580 | while (status) { |
581 | /* SW interrupt */ | |
582 | if (status & RADEON_SW_INT_TEST) { | |
583 | radeon_fence_process(rdev); | |
584 | } | |
2031f77c AD |
585 | /* gui idle interrupt */ |
586 | if (status & RADEON_GUI_IDLE_STAT) { | |
587 | rdev->irq.gui_idle_acked = true; | |
588 | rdev->pm.gui_idle = true; | |
589 | wake_up(&rdev->irq.idle_queue); | |
590 | } | |
7ed220d7 MD |
591 | /* Vertical blank interrupts */ |
592 | if (status & RADEON_CRTC_VBLANK_STAT) { | |
593 | drm_handle_vblank(rdev->ddev, 0); | |
839461d3 | 594 | rdev->pm.vblank_sync = true; |
73a6d3fc | 595 | wake_up(&rdev->irq.vblank_queue); |
7ed220d7 MD |
596 | } |
597 | if (status & RADEON_CRTC2_VBLANK_STAT) { | |
598 | drm_handle_vblank(rdev->ddev, 1); | |
839461d3 | 599 | rdev->pm.vblank_sync = true; |
73a6d3fc | 600 | wake_up(&rdev->irq.vblank_queue); |
7ed220d7 | 601 | } |
05a05c50 | 602 | if (status & RADEON_FP_DETECT_STAT) { |
d4877cf2 AD |
603 | queue_hotplug = true; |
604 | DRM_DEBUG("HPD1\n"); | |
05a05c50 AD |
605 | } |
606 | if (status & RADEON_FP2_DETECT_STAT) { | |
d4877cf2 AD |
607 | queue_hotplug = true; |
608 | DRM_DEBUG("HPD2\n"); | |
05a05c50 | 609 | } |
7ed220d7 MD |
610 | status = r100_irq_ack(rdev); |
611 | } | |
2031f77c AD |
612 | /* reset gui idle ack. the status bit is broken */ |
613 | rdev->irq.gui_idle_acked = false; | |
d4877cf2 AD |
614 | if (queue_hotplug) |
615 | queue_work(rdev->wq, &rdev->hotplug_work); | |
3e5cb98d AD |
616 | if (rdev->msi_enabled) { |
617 | switch (rdev->family) { | |
618 | case CHIP_RS400: | |
619 | case CHIP_RS480: | |
620 | msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; | |
621 | WREG32(RADEON_AIC_CNTL, msi_rearm); | |
622 | WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); | |
623 | break; | |
624 | default: | |
625 | msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; | |
626 | WREG32(RADEON_MSI_REARM_EN, msi_rearm); | |
627 | WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); | |
628 | break; | |
629 | } | |
630 | } | |
7ed220d7 MD |
631 | return IRQ_HANDLED; |
632 | } | |
633 | ||
634 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) | |
635 | { | |
636 | if (crtc == 0) | |
637 | return RREG32(RADEON_CRTC_CRNT_FRAME); | |
638 | else | |
639 | return RREG32(RADEON_CRTC2_CRNT_FRAME); | |
640 | } | |
641 | ||
9e5b2af7 PN |
642 | /* Who ever call radeon_fence_emit should call ring_lock and ask |
643 | * for enough space (today caller are ib schedule and buffer move) */ | |
771fe6b9 JG |
644 | void r100_fence_ring_emit(struct radeon_device *rdev, |
645 | struct radeon_fence *fence) | |
646 | { | |
9e5b2af7 PN |
647 | /* We have to make sure that caches are flushed before |
648 | * CPU might read something from VRAM. */ | |
649 | radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); | |
650 | radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL); | |
651 | radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); | |
652 | radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); | |
771fe6b9 | 653 | /* Wait until IDLE & CLEAN */ |
4612dc97 AD |
654 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
655 | radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); | |
cafe6609 JG |
656 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); |
657 | radeon_ring_write(rdev, rdev->config.r100.hdp_cntl | | |
658 | RADEON_HDP_READ_BUFFER_INVALIDATE); | |
659 | radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); | |
660 | radeon_ring_write(rdev, rdev->config.r100.hdp_cntl); | |
771fe6b9 JG |
661 | /* Emit fence sequence & fire IRQ */ |
662 | radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); | |
663 | radeon_ring_write(rdev, fence->seq); | |
664 | radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); | |
665 | radeon_ring_write(rdev, RADEON_SW_INT_FIRE); | |
666 | } | |
667 | ||
771fe6b9 JG |
668 | int r100_wb_init(struct radeon_device *rdev) |
669 | { | |
670 | int r; | |
671 | ||
672 | if (rdev->wb.wb_obj == NULL) { | |
4c788679 JG |
673 | r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true, |
674 | RADEON_GEM_DOMAIN_GTT, | |
675 | &rdev->wb.wb_obj); | |
771fe6b9 | 676 | if (r) { |
4c788679 | 677 | dev_err(rdev->dev, "(%d) create WB buffer failed\n", r); |
771fe6b9 JG |
678 | return r; |
679 | } | |
4c788679 JG |
680 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
681 | if (unlikely(r != 0)) | |
682 | return r; | |
683 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, | |
684 | &rdev->wb.gpu_addr); | |
771fe6b9 | 685 | if (r) { |
4c788679 JG |
686 | dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r); |
687 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
771fe6b9 JG |
688 | return r; |
689 | } | |
4c788679 JG |
690 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
691 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
771fe6b9 | 692 | if (r) { |
4c788679 | 693 | dev_err(rdev->dev, "(%d) map WB buffer failed\n", r); |
771fe6b9 JG |
694 | return r; |
695 | } | |
696 | } | |
9f022ddf JG |
697 | WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr); |
698 | WREG32(R_00070C_CP_RB_RPTR_ADDR, | |
699 | S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2)); | |
700 | WREG32(R_000770_SCRATCH_UMSK, 0xff); | |
771fe6b9 JG |
701 | return 0; |
702 | } | |
703 | ||
9f022ddf JG |
704 | void r100_wb_disable(struct radeon_device *rdev) |
705 | { | |
706 | WREG32(R_000770_SCRATCH_UMSK, 0); | |
707 | } | |
708 | ||
771fe6b9 JG |
709 | void r100_wb_fini(struct radeon_device *rdev) |
710 | { | |
4c788679 JG |
711 | int r; |
712 | ||
9f022ddf | 713 | r100_wb_disable(rdev); |
771fe6b9 | 714 | if (rdev->wb.wb_obj) { |
4c788679 JG |
715 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
716 | if (unlikely(r != 0)) { | |
717 | dev_err(rdev->dev, "(%d) can't finish WB\n", r); | |
718 | return; | |
719 | } | |
720 | radeon_bo_kunmap(rdev->wb.wb_obj); | |
721 | radeon_bo_unpin(rdev->wb.wb_obj); | |
722 | radeon_bo_unreserve(rdev->wb.wb_obj); | |
723 | radeon_bo_unref(&rdev->wb.wb_obj); | |
771fe6b9 JG |
724 | rdev->wb.wb = NULL; |
725 | rdev->wb.wb_obj = NULL; | |
726 | } | |
727 | } | |
728 | ||
729 | int r100_copy_blit(struct radeon_device *rdev, | |
730 | uint64_t src_offset, | |
731 | uint64_t dst_offset, | |
732 | unsigned num_pages, | |
733 | struct radeon_fence *fence) | |
734 | { | |
735 | uint32_t cur_pages; | |
736 | uint32_t stride_bytes = PAGE_SIZE; | |
737 | uint32_t pitch; | |
738 | uint32_t stride_pixels; | |
739 | unsigned ndw; | |
740 | int num_loops; | |
741 | int r = 0; | |
742 | ||
743 | /* radeon limited to 16k stride */ | |
744 | stride_bytes &= 0x3fff; | |
745 | /* radeon pitch is /64 */ | |
746 | pitch = stride_bytes / 64; | |
747 | stride_pixels = stride_bytes / 4; | |
748 | num_loops = DIV_ROUND_UP(num_pages, 8191); | |
749 | ||
750 | /* Ask for enough room for blit + flush + fence */ | |
751 | ndw = 64 + (10 * num_loops); | |
752 | r = radeon_ring_lock(rdev, ndw); | |
753 | if (r) { | |
754 | DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); | |
755 | return -EINVAL; | |
756 | } | |
757 | while (num_pages > 0) { | |
758 | cur_pages = num_pages; | |
759 | if (cur_pages > 8191) { | |
760 | cur_pages = 8191; | |
761 | } | |
762 | num_pages -= cur_pages; | |
763 | ||
764 | /* pages are in Y direction - height | |
765 | page width in X direction - width */ | |
766 | radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8)); | |
767 | radeon_ring_write(rdev, | |
768 | RADEON_GMC_SRC_PITCH_OFFSET_CNTL | | |
769 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | | |
770 | RADEON_GMC_SRC_CLIPPING | | |
771 | RADEON_GMC_DST_CLIPPING | | |
772 | RADEON_GMC_BRUSH_NONE | | |
773 | (RADEON_COLOR_FORMAT_ARGB8888 << 8) | | |
774 | RADEON_GMC_SRC_DATATYPE_COLOR | | |
775 | RADEON_ROP3_S | | |
776 | RADEON_DP_SRC_SOURCE_MEMORY | | |
777 | RADEON_GMC_CLR_CMP_CNTL_DIS | | |
778 | RADEON_GMC_WR_MSK_DIS); | |
779 | radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10)); | |
780 | radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10)); | |
781 | radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); | |
782 | radeon_ring_write(rdev, 0); | |
783 | radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); | |
784 | radeon_ring_write(rdev, num_pages); | |
785 | radeon_ring_write(rdev, num_pages); | |
786 | radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); | |
787 | } | |
788 | radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); | |
789 | radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); | |
790 | radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); | |
791 | radeon_ring_write(rdev, | |
792 | RADEON_WAIT_2D_IDLECLEAN | | |
793 | RADEON_WAIT_HOST_IDLECLEAN | | |
794 | RADEON_WAIT_DMA_GUI_IDLE); | |
795 | if (fence) { | |
796 | r = radeon_fence_emit(rdev, fence); | |
797 | } | |
798 | radeon_ring_unlock_commit(rdev); | |
799 | return r; | |
800 | } | |
801 | ||
45600232 JG |
802 | static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
803 | { | |
804 | unsigned i; | |
805 | u32 tmp; | |
806 | ||
807 | for (i = 0; i < rdev->usec_timeout; i++) { | |
808 | tmp = RREG32(R_000E40_RBBM_STATUS); | |
809 | if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { | |
810 | return 0; | |
811 | } | |
812 | udelay(1); | |
813 | } | |
814 | return -1; | |
815 | } | |
816 | ||
771fe6b9 JG |
817 | void r100_ring_start(struct radeon_device *rdev) |
818 | { | |
819 | int r; | |
820 | ||
821 | r = radeon_ring_lock(rdev, 2); | |
822 | if (r) { | |
823 | return; | |
824 | } | |
825 | radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); | |
826 | radeon_ring_write(rdev, | |
827 | RADEON_ISYNC_ANY2D_IDLE3D | | |
828 | RADEON_ISYNC_ANY3D_IDLE2D | | |
829 | RADEON_ISYNC_WAIT_IDLEGUI | | |
830 | RADEON_ISYNC_CPSCRATCH_IDLEGUI); | |
831 | radeon_ring_unlock_commit(rdev); | |
832 | } | |
833 | ||
70967ab9 BH |
834 | |
835 | /* Load the microcode for the CP */ | |
836 | static int r100_cp_init_microcode(struct radeon_device *rdev) | |
771fe6b9 | 837 | { |
70967ab9 BH |
838 | struct platform_device *pdev; |
839 | const char *fw_name = NULL; | |
840 | int err; | |
771fe6b9 | 841 | |
70967ab9 | 842 | DRM_DEBUG("\n"); |
771fe6b9 | 843 | |
70967ab9 BH |
844 | pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); |
845 | err = IS_ERR(pdev); | |
846 | if (err) { | |
847 | printk(KERN_ERR "radeon_cp: Failed to register firmware\n"); | |
848 | return -EINVAL; | |
849 | } | |
771fe6b9 JG |
850 | if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
851 | (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || | |
852 | (rdev->family == CHIP_RS200)) { | |
853 | DRM_INFO("Loading R100 Microcode\n"); | |
70967ab9 | 854 | fw_name = FIRMWARE_R100; |
771fe6b9 JG |
855 | } else if ((rdev->family == CHIP_R200) || |
856 | (rdev->family == CHIP_RV250) || | |
857 | (rdev->family == CHIP_RV280) || | |
858 | (rdev->family == CHIP_RS300)) { | |
859 | DRM_INFO("Loading R200 Microcode\n"); | |
70967ab9 | 860 | fw_name = FIRMWARE_R200; |
771fe6b9 JG |
861 | } else if ((rdev->family == CHIP_R300) || |
862 | (rdev->family == CHIP_R350) || | |
863 | (rdev->family == CHIP_RV350) || | |
864 | (rdev->family == CHIP_RV380) || | |
865 | (rdev->family == CHIP_RS400) || | |
866 | (rdev->family == CHIP_RS480)) { | |
867 | DRM_INFO("Loading R300 Microcode\n"); | |
70967ab9 | 868 | fw_name = FIRMWARE_R300; |
771fe6b9 JG |
869 | } else if ((rdev->family == CHIP_R420) || |
870 | (rdev->family == CHIP_R423) || | |
871 | (rdev->family == CHIP_RV410)) { | |
872 | DRM_INFO("Loading R400 Microcode\n"); | |
70967ab9 | 873 | fw_name = FIRMWARE_R420; |
771fe6b9 JG |
874 | } else if ((rdev->family == CHIP_RS690) || |
875 | (rdev->family == CHIP_RS740)) { | |
876 | DRM_INFO("Loading RS690/RS740 Microcode\n"); | |
70967ab9 | 877 | fw_name = FIRMWARE_RS690; |
771fe6b9 JG |
878 | } else if (rdev->family == CHIP_RS600) { |
879 | DRM_INFO("Loading RS600 Microcode\n"); | |
70967ab9 | 880 | fw_name = FIRMWARE_RS600; |
771fe6b9 JG |
881 | } else if ((rdev->family == CHIP_RV515) || |
882 | (rdev->family == CHIP_R520) || | |
883 | (rdev->family == CHIP_RV530) || | |
884 | (rdev->family == CHIP_R580) || | |
885 | (rdev->family == CHIP_RV560) || | |
886 | (rdev->family == CHIP_RV570)) { | |
887 | DRM_INFO("Loading R500 Microcode\n"); | |
70967ab9 BH |
888 | fw_name = FIRMWARE_R520; |
889 | } | |
890 | ||
3ce0a23d | 891 | err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); |
70967ab9 BH |
892 | platform_device_unregister(pdev); |
893 | if (err) { | |
894 | printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n", | |
895 | fw_name); | |
3ce0a23d | 896 | } else if (rdev->me_fw->size % 8) { |
70967ab9 BH |
897 | printk(KERN_ERR |
898 | "radeon_cp: Bogus length %zu in firmware \"%s\"\n", | |
3ce0a23d | 899 | rdev->me_fw->size, fw_name); |
70967ab9 | 900 | err = -EINVAL; |
3ce0a23d JG |
901 | release_firmware(rdev->me_fw); |
902 | rdev->me_fw = NULL; | |
70967ab9 BH |
903 | } |
904 | return err; | |
905 | } | |
d4550907 | 906 | |
70967ab9 BH |
907 | static void r100_cp_load_microcode(struct radeon_device *rdev) |
908 | { | |
909 | const __be32 *fw_data; | |
910 | int i, size; | |
911 | ||
912 | if (r100_gui_wait_for_idle(rdev)) { | |
913 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
914 | "programming pipes. Bad things might happen.\n"); | |
915 | } | |
916 | ||
3ce0a23d JG |
917 | if (rdev->me_fw) { |
918 | size = rdev->me_fw->size / 4; | |
919 | fw_data = (const __be32 *)&rdev->me_fw->data[0]; | |
70967ab9 BH |
920 | WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
921 | for (i = 0; i < size; i += 2) { | |
922 | WREG32(RADEON_CP_ME_RAM_DATAH, | |
923 | be32_to_cpup(&fw_data[i])); | |
924 | WREG32(RADEON_CP_ME_RAM_DATAL, | |
925 | be32_to_cpup(&fw_data[i + 1])); | |
771fe6b9 JG |
926 | } |
927 | } | |
928 | } | |
929 | ||
930 | int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) | |
931 | { | |
932 | unsigned rb_bufsz; | |
933 | unsigned rb_blksz; | |
934 | unsigned max_fetch; | |
935 | unsigned pre_write_timer; | |
936 | unsigned pre_write_limit; | |
937 | unsigned indirect2_start; | |
938 | unsigned indirect1_start; | |
939 | uint32_t tmp; | |
940 | int r; | |
941 | ||
942 | if (r100_debugfs_cp_init(rdev)) { | |
943 | DRM_ERROR("Failed to register debugfs file for CP !\n"); | |
944 | } | |
3ce0a23d | 945 | if (!rdev->me_fw) { |
70967ab9 BH |
946 | r = r100_cp_init_microcode(rdev); |
947 | if (r) { | |
948 | DRM_ERROR("Failed to load firmware!\n"); | |
949 | return r; | |
950 | } | |
951 | } | |
952 | ||
771fe6b9 JG |
953 | /* Align ring size */ |
954 | rb_bufsz = drm_order(ring_size / 8); | |
955 | ring_size = (1 << (rb_bufsz + 1)) * 4; | |
956 | r100_cp_load_microcode(rdev); | |
957 | r = radeon_ring_init(rdev, ring_size); | |
958 | if (r) { | |
959 | return r; | |
960 | } | |
961 | /* Each time the cp read 1024 bytes (16 dword/quadword) update | |
962 | * the rptr copy in system ram */ | |
963 | rb_blksz = 9; | |
964 | /* cp will read 128bytes at a time (4 dwords) */ | |
965 | max_fetch = 1; | |
966 | rdev->cp.align_mask = 16 - 1; | |
967 | /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ | |
968 | pre_write_timer = 64; | |
969 | /* Force CP_RB_WPTR write if written more than one time before the | |
970 | * delay expire | |
971 | */ | |
972 | pre_write_limit = 0; | |
973 | /* Setup the cp cache like this (cache size is 96 dwords) : | |
974 | * RING 0 to 15 | |
975 | * INDIRECT1 16 to 79 | |
976 | * INDIRECT2 80 to 95 | |
977 | * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) | |
978 | * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) | |
979 | * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) | |
980 | * Idea being that most of the gpu cmd will be through indirect1 buffer | |
981 | * so it gets the bigger cache. | |
982 | */ | |
983 | indirect2_start = 80; | |
984 | indirect1_start = 16; | |
985 | /* cp setup */ | |
986 | WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); | |
d6f28938 | 987 | tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | |
771fe6b9 JG |
988 | REG_SET(RADEON_RB_BLKSZ, rb_blksz) | |
989 | REG_SET(RADEON_MAX_FETCH, max_fetch) | | |
990 | RADEON_RB_NO_UPDATE); | |
d6f28938 AD |
991 | #ifdef __BIG_ENDIAN |
992 | tmp |= RADEON_BUF_SWAP_32BIT; | |
993 | #endif | |
994 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
995 | ||
771fe6b9 JG |
996 | /* Set ring address */ |
997 | DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); | |
998 | WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); | |
999 | /* Force read & write ptr to 0 */ | |
771fe6b9 JG |
1000 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
1001 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | |
1002 | WREG32(RADEON_CP_RB_WPTR, 0); | |
1003 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
1004 | udelay(10); | |
1005 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); | |
1006 | rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); | |
9e5786bd DA |
1007 | /* protect against crazy HW on resume */ |
1008 | rdev->cp.wptr &= rdev->cp.ptr_mask; | |
771fe6b9 JG |
1009 | /* Set cp mode to bus mastering & enable cp*/ |
1010 | WREG32(RADEON_CP_CSQ_MODE, | |
1011 | REG_SET(RADEON_INDIRECT2_START, indirect2_start) | | |
1012 | REG_SET(RADEON_INDIRECT1_START, indirect1_start)); | |
1013 | WREG32(0x718, 0); | |
1014 | WREG32(0x744, 0x00004D4D); | |
1015 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); | |
1016 | radeon_ring_start(rdev); | |
1017 | r = radeon_ring_test(rdev); | |
1018 | if (r) { | |
1019 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); | |
1020 | return r; | |
1021 | } | |
1022 | rdev->cp.ready = true; | |
1023 | return 0; | |
1024 | } | |
1025 | ||
1026 | void r100_cp_fini(struct radeon_device *rdev) | |
1027 | { | |
45600232 JG |
1028 | if (r100_cp_wait_for_idle(rdev)) { |
1029 | DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); | |
1030 | } | |
771fe6b9 | 1031 | /* Disable ring */ |
a18d7ea1 | 1032 | r100_cp_disable(rdev); |
771fe6b9 JG |
1033 | radeon_ring_fini(rdev); |
1034 | DRM_INFO("radeon: cp finalized\n"); | |
1035 | } | |
1036 | ||
1037 | void r100_cp_disable(struct radeon_device *rdev) | |
1038 | { | |
1039 | /* Disable ring */ | |
1040 | rdev->cp.ready = false; | |
1041 | WREG32(RADEON_CP_CSQ_MODE, 0); | |
1042 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
1043 | if (r100_gui_wait_for_idle(rdev)) { | |
1044 | printk(KERN_WARNING "Failed to wait GUI idle while " | |
1045 | "programming pipes. Bad things might happen.\n"); | |
1046 | } | |
1047 | } | |
1048 | ||
3ce0a23d JG |
1049 | void r100_cp_commit(struct radeon_device *rdev) |
1050 | { | |
1051 | WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); | |
1052 | (void)RREG32(RADEON_CP_RB_WPTR); | |
1053 | } | |
1054 | ||
771fe6b9 JG |
1055 | |
1056 | /* | |
1057 | * CS functions | |
1058 | */ | |
1059 | int r100_cs_parse_packet0(struct radeon_cs_parser *p, | |
1060 | struct radeon_cs_packet *pkt, | |
068a117c | 1061 | const unsigned *auth, unsigned n, |
771fe6b9 JG |
1062 | radeon_packet0_check_t check) |
1063 | { | |
1064 | unsigned reg; | |
1065 | unsigned i, j, m; | |
1066 | unsigned idx; | |
1067 | int r; | |
1068 | ||
1069 | idx = pkt->idx + 1; | |
1070 | reg = pkt->reg; | |
068a117c JG |
1071 | /* Check that register fall into register range |
1072 | * determined by the number of entry (n) in the | |
1073 | * safe register bitmap. | |
1074 | */ | |
771fe6b9 JG |
1075 | if (pkt->one_reg_wr) { |
1076 | if ((reg >> 7) > n) { | |
1077 | return -EINVAL; | |
1078 | } | |
1079 | } else { | |
1080 | if (((reg + (pkt->count << 2)) >> 7) > n) { | |
1081 | return -EINVAL; | |
1082 | } | |
1083 | } | |
1084 | for (i = 0; i <= pkt->count; i++, idx++) { | |
1085 | j = (reg >> 7); | |
1086 | m = 1 << ((reg >> 2) & 31); | |
1087 | if (auth[j] & m) { | |
1088 | r = check(p, pkt, idx, reg); | |
1089 | if (r) { | |
1090 | return r; | |
1091 | } | |
1092 | } | |
1093 | if (pkt->one_reg_wr) { | |
1094 | if (!(auth[j] & m)) { | |
1095 | break; | |
1096 | } | |
1097 | } else { | |
1098 | reg += 4; | |
1099 | } | |
1100 | } | |
1101 | return 0; | |
1102 | } | |
1103 | ||
771fe6b9 JG |
1104 | void r100_cs_dump_packet(struct radeon_cs_parser *p, |
1105 | struct radeon_cs_packet *pkt) | |
1106 | { | |
771fe6b9 JG |
1107 | volatile uint32_t *ib; |
1108 | unsigned i; | |
1109 | unsigned idx; | |
1110 | ||
1111 | ib = p->ib->ptr; | |
771fe6b9 JG |
1112 | idx = pkt->idx; |
1113 | for (i = 0; i <= (pkt->count + 1); i++, idx++) { | |
1114 | DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); | |
1115 | } | |
1116 | } | |
1117 | ||
1118 | /** | |
1119 | * r100_cs_packet_parse() - parse cp packet and point ib index to next packet | |
1120 | * @parser: parser structure holding parsing context. | |
1121 | * @pkt: where to store packet informations | |
1122 | * | |
1123 | * Assume that chunk_ib_index is properly set. Will return -EINVAL | |
1124 | * if packet is bigger than remaining ib size. or if packets is unknown. | |
1125 | **/ | |
1126 | int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
1127 | struct radeon_cs_packet *pkt, | |
1128 | unsigned idx) | |
1129 | { | |
1130 | struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; | |
fa99239c | 1131 | uint32_t header; |
771fe6b9 JG |
1132 | |
1133 | if (idx >= ib_chunk->length_dw) { | |
1134 | DRM_ERROR("Can not parse packet at %d after CS end %d !\n", | |
1135 | idx, ib_chunk->length_dw); | |
1136 | return -EINVAL; | |
1137 | } | |
513bcb46 | 1138 | header = radeon_get_ib_value(p, idx); |
771fe6b9 JG |
1139 | pkt->idx = idx; |
1140 | pkt->type = CP_PACKET_GET_TYPE(header); | |
1141 | pkt->count = CP_PACKET_GET_COUNT(header); | |
1142 | switch (pkt->type) { | |
1143 | case PACKET_TYPE0: | |
1144 | pkt->reg = CP_PACKET0_GET_REG(header); | |
1145 | pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); | |
1146 | break; | |
1147 | case PACKET_TYPE3: | |
1148 | pkt->opcode = CP_PACKET3_GET_OPCODE(header); | |
1149 | break; | |
1150 | case PACKET_TYPE2: | |
1151 | pkt->count = -1; | |
1152 | break; | |
1153 | default: | |
1154 | DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); | |
1155 | return -EINVAL; | |
1156 | } | |
1157 | if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { | |
1158 | DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", | |
1159 | pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); | |
1160 | return -EINVAL; | |
1161 | } | |
1162 | return 0; | |
1163 | } | |
1164 | ||
531369e6 DA |
1165 | /** |
1166 | * r100_cs_packet_next_vline() - parse userspace VLINE packet | |
1167 | * @parser: parser structure holding parsing context. | |
1168 | * | |
1169 | * Userspace sends a special sequence for VLINE waits. | |
1170 | * PACKET0 - VLINE_START_END + value | |
1171 | * PACKET0 - WAIT_UNTIL +_value | |
1172 | * RELOC (P3) - crtc_id in reloc. | |
1173 | * | |
1174 | * This function parses this and relocates the VLINE START END | |
1175 | * and WAIT UNTIL packets to the correct crtc. | |
1176 | * It also detects a switched off crtc and nulls out the | |
1177 | * wait in that case. | |
1178 | */ | |
1179 | int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) | |
1180 | { | |
531369e6 DA |
1181 | struct drm_mode_object *obj; |
1182 | struct drm_crtc *crtc; | |
1183 | struct radeon_crtc *radeon_crtc; | |
1184 | struct radeon_cs_packet p3reloc, waitreloc; | |
1185 | int crtc_id; | |
1186 | int r; | |
1187 | uint32_t header, h_idx, reg; | |
513bcb46 | 1188 | volatile uint32_t *ib; |
531369e6 | 1189 | |
513bcb46 | 1190 | ib = p->ib->ptr; |
531369e6 DA |
1191 | |
1192 | /* parse the wait until */ | |
1193 | r = r100_cs_packet_parse(p, &waitreloc, p->idx); | |
1194 | if (r) | |
1195 | return r; | |
1196 | ||
1197 | /* check its a wait until and only 1 count */ | |
1198 | if (waitreloc.reg != RADEON_WAIT_UNTIL || | |
1199 | waitreloc.count != 0) { | |
1200 | DRM_ERROR("vline wait had illegal wait until segment\n"); | |
1201 | r = -EINVAL; | |
1202 | return r; | |
1203 | } | |
1204 | ||
513bcb46 | 1205 | if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { |
531369e6 DA |
1206 | DRM_ERROR("vline wait had illegal wait until\n"); |
1207 | r = -EINVAL; | |
1208 | return r; | |
1209 | } | |
1210 | ||
1211 | /* jump over the NOP */ | |
90ebd065 | 1212 | r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); |
531369e6 DA |
1213 | if (r) |
1214 | return r; | |
1215 | ||
1216 | h_idx = p->idx - 2; | |
90ebd065 AD |
1217 | p->idx += waitreloc.count + 2; |
1218 | p->idx += p3reloc.count + 2; | |
531369e6 | 1219 | |
513bcb46 DA |
1220 | header = radeon_get_ib_value(p, h_idx); |
1221 | crtc_id = radeon_get_ib_value(p, h_idx + 5); | |
d4ac6a05 | 1222 | reg = CP_PACKET0_GET_REG(header); |
531369e6 DA |
1223 | mutex_lock(&p->rdev->ddev->mode_config.mutex); |
1224 | obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); | |
1225 | if (!obj) { | |
1226 | DRM_ERROR("cannot find crtc %d\n", crtc_id); | |
1227 | r = -EINVAL; | |
1228 | goto out; | |
1229 | } | |
1230 | crtc = obj_to_crtc(obj); | |
1231 | radeon_crtc = to_radeon_crtc(crtc); | |
1232 | crtc_id = radeon_crtc->crtc_id; | |
1233 | ||
1234 | if (!crtc->enabled) { | |
1235 | /* if the CRTC isn't enabled - we need to nop out the wait until */ | |
513bcb46 DA |
1236 | ib[h_idx + 2] = PACKET2(0); |
1237 | ib[h_idx + 3] = PACKET2(0); | |
531369e6 DA |
1238 | } else if (crtc_id == 1) { |
1239 | switch (reg) { | |
1240 | case AVIVO_D1MODE_VLINE_START_END: | |
90ebd065 | 1241 | header &= ~R300_CP_PACKET0_REG_MASK; |
531369e6 DA |
1242 | header |= AVIVO_D2MODE_VLINE_START_END >> 2; |
1243 | break; | |
1244 | case RADEON_CRTC_GUI_TRIG_VLINE: | |
90ebd065 | 1245 | header &= ~R300_CP_PACKET0_REG_MASK; |
531369e6 DA |
1246 | header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; |
1247 | break; | |
1248 | default: | |
1249 | DRM_ERROR("unknown crtc reloc\n"); | |
1250 | r = -EINVAL; | |
1251 | goto out; | |
1252 | } | |
513bcb46 DA |
1253 | ib[h_idx] = header; |
1254 | ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; | |
531369e6 DA |
1255 | } |
1256 | out: | |
1257 | mutex_unlock(&p->rdev->ddev->mode_config.mutex); | |
1258 | return r; | |
1259 | } | |
1260 | ||
771fe6b9 JG |
1261 | /** |
1262 | * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 | |
1263 | * @parser: parser structure holding parsing context. | |
1264 | * @data: pointer to relocation data | |
1265 | * @offset_start: starting offset | |
1266 | * @offset_mask: offset mask (to align start offset on) | |
1267 | * @reloc: reloc informations | |
1268 | * | |
1269 | * Check next packet is relocation packet3, do bo validation and compute | |
1270 | * GPU offset using the provided start. | |
1271 | **/ | |
1272 | int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, | |
1273 | struct radeon_cs_reloc **cs_reloc) | |
1274 | { | |
771fe6b9 JG |
1275 | struct radeon_cs_chunk *relocs_chunk; |
1276 | struct radeon_cs_packet p3reloc; | |
1277 | unsigned idx; | |
1278 | int r; | |
1279 | ||
1280 | if (p->chunk_relocs_idx == -1) { | |
1281 | DRM_ERROR("No relocation chunk !\n"); | |
1282 | return -EINVAL; | |
1283 | } | |
1284 | *cs_reloc = NULL; | |
771fe6b9 JG |
1285 | relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
1286 | r = r100_cs_packet_parse(p, &p3reloc, p->idx); | |
1287 | if (r) { | |
1288 | return r; | |
1289 | } | |
1290 | p->idx += p3reloc.count + 2; | |
1291 | if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { | |
1292 | DRM_ERROR("No packet3 for relocation for packet at %d.\n", | |
1293 | p3reloc.idx); | |
1294 | r100_cs_dump_packet(p, &p3reloc); | |
1295 | return -EINVAL; | |
1296 | } | |
513bcb46 | 1297 | idx = radeon_get_ib_value(p, p3reloc.idx + 1); |
771fe6b9 JG |
1298 | if (idx >= relocs_chunk->length_dw) { |
1299 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", | |
1300 | idx, relocs_chunk->length_dw); | |
1301 | r100_cs_dump_packet(p, &p3reloc); | |
1302 | return -EINVAL; | |
1303 | } | |
1304 | /* FIXME: we assume reloc size is 4 dwords */ | |
1305 | *cs_reloc = p->relocs_ptr[(idx / 4)]; | |
1306 | return 0; | |
1307 | } | |
1308 | ||
551ebd83 DA |
1309 | static int r100_get_vtx_size(uint32_t vtx_fmt) |
1310 | { | |
1311 | int vtx_size; | |
1312 | vtx_size = 2; | |
1313 | /* ordered according to bits in spec */ | |
1314 | if (vtx_fmt & RADEON_SE_VTX_FMT_W0) | |
1315 | vtx_size++; | |
1316 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) | |
1317 | vtx_size += 3; | |
1318 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) | |
1319 | vtx_size++; | |
1320 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) | |
1321 | vtx_size++; | |
1322 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) | |
1323 | vtx_size += 3; | |
1324 | if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) | |
1325 | vtx_size++; | |
1326 | if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) | |
1327 | vtx_size++; | |
1328 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) | |
1329 | vtx_size += 2; | |
1330 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) | |
1331 | vtx_size += 2; | |
1332 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) | |
1333 | vtx_size++; | |
1334 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) | |
1335 | vtx_size += 2; | |
1336 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) | |
1337 | vtx_size++; | |
1338 | if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) | |
1339 | vtx_size += 2; | |
1340 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) | |
1341 | vtx_size++; | |
1342 | if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) | |
1343 | vtx_size++; | |
1344 | /* blend weight */ | |
1345 | if (vtx_fmt & (0x7 << 15)) | |
1346 | vtx_size += (vtx_fmt >> 15) & 0x7; | |
1347 | if (vtx_fmt & RADEON_SE_VTX_FMT_N0) | |
1348 | vtx_size += 3; | |
1349 | if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) | |
1350 | vtx_size += 2; | |
1351 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) | |
1352 | vtx_size++; | |
1353 | if (vtx_fmt & RADEON_SE_VTX_FMT_W1) | |
1354 | vtx_size++; | |
1355 | if (vtx_fmt & RADEON_SE_VTX_FMT_N1) | |
1356 | vtx_size++; | |
1357 | if (vtx_fmt & RADEON_SE_VTX_FMT_Z) | |
1358 | vtx_size++; | |
1359 | return vtx_size; | |
1360 | } | |
1361 | ||
771fe6b9 | 1362 | static int r100_packet0_check(struct radeon_cs_parser *p, |
551ebd83 DA |
1363 | struct radeon_cs_packet *pkt, |
1364 | unsigned idx, unsigned reg) | |
771fe6b9 | 1365 | { |
771fe6b9 | 1366 | struct radeon_cs_reloc *reloc; |
551ebd83 | 1367 | struct r100_cs_track *track; |
771fe6b9 JG |
1368 | volatile uint32_t *ib; |
1369 | uint32_t tmp; | |
771fe6b9 | 1370 | int r; |
551ebd83 | 1371 | int i, face; |
e024e110 | 1372 | u32 tile_flags = 0; |
513bcb46 | 1373 | u32 idx_value; |
771fe6b9 JG |
1374 | |
1375 | ib = p->ib->ptr; | |
551ebd83 DA |
1376 | track = (struct r100_cs_track *)p->track; |
1377 | ||
513bcb46 DA |
1378 | idx_value = radeon_get_ib_value(p, idx); |
1379 | ||
551ebd83 DA |
1380 | switch (reg) { |
1381 | case RADEON_CRTC_GUI_TRIG_VLINE: | |
1382 | r = r100_cs_packet_parse_vline(p); | |
1383 | if (r) { | |
1384 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1385 | idx, reg); | |
1386 | r100_cs_dump_packet(p, pkt); | |
1387 | return r; | |
1388 | } | |
1389 | break; | |
771fe6b9 JG |
1390 | /* FIXME: only allow PACKET3 blit? easier to check for out of |
1391 | * range access */ | |
551ebd83 DA |
1392 | case RADEON_DST_PITCH_OFFSET: |
1393 | case RADEON_SRC_PITCH_OFFSET: | |
1394 | r = r100_reloc_pitch_offset(p, pkt, idx, reg); | |
1395 | if (r) | |
1396 | return r; | |
1397 | break; | |
1398 | case RADEON_RB3D_DEPTHOFFSET: | |
1399 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1400 | if (r) { | |
1401 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1402 | idx, reg); | |
1403 | r100_cs_dump_packet(p, pkt); | |
1404 | return r; | |
1405 | } | |
1406 | track->zb.robj = reloc->robj; | |
513bcb46 DA |
1407 | track->zb.offset = idx_value; |
1408 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 DA |
1409 | break; |
1410 | case RADEON_RB3D_COLOROFFSET: | |
1411 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1412 | if (r) { | |
1413 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1414 | idx, reg); | |
1415 | r100_cs_dump_packet(p, pkt); | |
1416 | return r; | |
1417 | } | |
1418 | track->cb[0].robj = reloc->robj; | |
513bcb46 DA |
1419 | track->cb[0].offset = idx_value; |
1420 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 DA |
1421 | break; |
1422 | case RADEON_PP_TXOFFSET_0: | |
1423 | case RADEON_PP_TXOFFSET_1: | |
1424 | case RADEON_PP_TXOFFSET_2: | |
1425 | i = (reg - RADEON_PP_TXOFFSET_0) / 24; | |
1426 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1427 | if (r) { | |
1428 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1429 | idx, reg); | |
1430 | r100_cs_dump_packet(p, pkt); | |
1431 | return r; | |
1432 | } | |
513bcb46 | 1433 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
551ebd83 DA |
1434 | track->textures[i].robj = reloc->robj; |
1435 | break; | |
1436 | case RADEON_PP_CUBIC_OFFSET_T0_0: | |
1437 | case RADEON_PP_CUBIC_OFFSET_T0_1: | |
1438 | case RADEON_PP_CUBIC_OFFSET_T0_2: | |
1439 | case RADEON_PP_CUBIC_OFFSET_T0_3: | |
1440 | case RADEON_PP_CUBIC_OFFSET_T0_4: | |
1441 | i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; | |
1442 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1443 | if (r) { | |
1444 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1445 | idx, reg); | |
1446 | r100_cs_dump_packet(p, pkt); | |
1447 | return r; | |
1448 | } | |
513bcb46 DA |
1449 | track->textures[0].cube_info[i].offset = idx_value; |
1450 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 DA |
1451 | track->textures[0].cube_info[i].robj = reloc->robj; |
1452 | break; | |
1453 | case RADEON_PP_CUBIC_OFFSET_T1_0: | |
1454 | case RADEON_PP_CUBIC_OFFSET_T1_1: | |
1455 | case RADEON_PP_CUBIC_OFFSET_T1_2: | |
1456 | case RADEON_PP_CUBIC_OFFSET_T1_3: | |
1457 | case RADEON_PP_CUBIC_OFFSET_T1_4: | |
1458 | i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; | |
1459 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1460 | if (r) { | |
1461 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1462 | idx, reg); | |
1463 | r100_cs_dump_packet(p, pkt); | |
1464 | return r; | |
1465 | } | |
513bcb46 DA |
1466 | track->textures[1].cube_info[i].offset = idx_value; |
1467 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 DA |
1468 | track->textures[1].cube_info[i].robj = reloc->robj; |
1469 | break; | |
1470 | case RADEON_PP_CUBIC_OFFSET_T2_0: | |
1471 | case RADEON_PP_CUBIC_OFFSET_T2_1: | |
1472 | case RADEON_PP_CUBIC_OFFSET_T2_2: | |
1473 | case RADEON_PP_CUBIC_OFFSET_T2_3: | |
1474 | case RADEON_PP_CUBIC_OFFSET_T2_4: | |
1475 | i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; | |
1476 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1477 | if (r) { | |
1478 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1479 | idx, reg); | |
1480 | r100_cs_dump_packet(p, pkt); | |
1481 | return r; | |
1482 | } | |
513bcb46 DA |
1483 | track->textures[2].cube_info[i].offset = idx_value; |
1484 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); | |
551ebd83 DA |
1485 | track->textures[2].cube_info[i].robj = reloc->robj; |
1486 | break; | |
1487 | case RADEON_RE_WIDTH_HEIGHT: | |
513bcb46 | 1488 | track->maxy = ((idx_value >> 16) & 0x7FF); |
551ebd83 DA |
1489 | break; |
1490 | case RADEON_RB3D_COLORPITCH: | |
1491 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1492 | if (r) { | |
1493 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1494 | idx, reg); | |
1495 | r100_cs_dump_packet(p, pkt); | |
1496 | return r; | |
1497 | } | |
e024e110 | 1498 | |
551ebd83 DA |
1499 | if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) |
1500 | tile_flags |= RADEON_COLOR_TILE_ENABLE; | |
1501 | if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) | |
1502 | tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; | |
e024e110 | 1503 | |
513bcb46 | 1504 | tmp = idx_value & ~(0x7 << 16); |
551ebd83 DA |
1505 | tmp |= tile_flags; |
1506 | ib[idx] = tmp; | |
e024e110 | 1507 | |
513bcb46 | 1508 | track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; |
551ebd83 DA |
1509 | break; |
1510 | case RADEON_RB3D_DEPTHPITCH: | |
513bcb46 | 1511 | track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; |
551ebd83 DA |
1512 | break; |
1513 | case RADEON_RB3D_CNTL: | |
513bcb46 | 1514 | switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { |
551ebd83 DA |
1515 | case 7: |
1516 | case 8: | |
1517 | case 9: | |
1518 | case 11: | |
1519 | case 12: | |
1520 | track->cb[0].cpp = 1; | |
e024e110 | 1521 | break; |
551ebd83 DA |
1522 | case 3: |
1523 | case 4: | |
1524 | case 15: | |
1525 | track->cb[0].cpp = 2; | |
1526 | break; | |
1527 | case 6: | |
1528 | track->cb[0].cpp = 4; | |
1529 | break; | |
1530 | default: | |
1531 | DRM_ERROR("Invalid color buffer format (%d) !\n", | |
513bcb46 | 1532 | ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); |
551ebd83 DA |
1533 | return -EINVAL; |
1534 | } | |
513bcb46 | 1535 | track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); |
551ebd83 DA |
1536 | break; |
1537 | case RADEON_RB3D_ZSTENCILCNTL: | |
513bcb46 | 1538 | switch (idx_value & 0xf) { |
551ebd83 DA |
1539 | case 0: |
1540 | track->zb.cpp = 2; | |
1541 | break; | |
1542 | case 2: | |
1543 | case 3: | |
1544 | case 4: | |
1545 | case 5: | |
1546 | case 9: | |
1547 | case 11: | |
1548 | track->zb.cpp = 4; | |
17782d99 | 1549 | break; |
771fe6b9 | 1550 | default: |
771fe6b9 JG |
1551 | break; |
1552 | } | |
551ebd83 DA |
1553 | break; |
1554 | case RADEON_RB3D_ZPASS_ADDR: | |
1555 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1556 | if (r) { | |
1557 | DRM_ERROR("No reloc for ib[%d]=0x%04X\n", | |
1558 | idx, reg); | |
1559 | r100_cs_dump_packet(p, pkt); | |
1560 | return r; | |
1561 | } | |
513bcb46 | 1562 | ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); |
551ebd83 DA |
1563 | break; |
1564 | case RADEON_PP_CNTL: | |
1565 | { | |
513bcb46 | 1566 | uint32_t temp = idx_value >> 4; |
551ebd83 DA |
1567 | for (i = 0; i < track->num_texture; i++) |
1568 | track->textures[i].enabled = !!(temp & (1 << i)); | |
1569 | } | |
1570 | break; | |
1571 | case RADEON_SE_VF_CNTL: | |
513bcb46 | 1572 | track->vap_vf_cntl = idx_value; |
551ebd83 DA |
1573 | break; |
1574 | case RADEON_SE_VTX_FMT: | |
513bcb46 | 1575 | track->vtx_size = r100_get_vtx_size(idx_value); |
551ebd83 DA |
1576 | break; |
1577 | case RADEON_PP_TEX_SIZE_0: | |
1578 | case RADEON_PP_TEX_SIZE_1: | |
1579 | case RADEON_PP_TEX_SIZE_2: | |
1580 | i = (reg - RADEON_PP_TEX_SIZE_0) / 8; | |
513bcb46 DA |
1581 | track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; |
1582 | track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; | |
551ebd83 DA |
1583 | break; |
1584 | case RADEON_PP_TEX_PITCH_0: | |
1585 | case RADEON_PP_TEX_PITCH_1: | |
1586 | case RADEON_PP_TEX_PITCH_2: | |
1587 | i = (reg - RADEON_PP_TEX_PITCH_0) / 8; | |
513bcb46 | 1588 | track->textures[i].pitch = idx_value + 32; |
551ebd83 DA |
1589 | break; |
1590 | case RADEON_PP_TXFILTER_0: | |
1591 | case RADEON_PP_TXFILTER_1: | |
1592 | case RADEON_PP_TXFILTER_2: | |
1593 | i = (reg - RADEON_PP_TXFILTER_0) / 24; | |
513bcb46 | 1594 | track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) |
551ebd83 | 1595 | >> RADEON_MAX_MIP_LEVEL_SHIFT); |
513bcb46 | 1596 | tmp = (idx_value >> 23) & 0x7; |
551ebd83 DA |
1597 | if (tmp == 2 || tmp == 6) |
1598 | track->textures[i].roundup_w = false; | |
513bcb46 | 1599 | tmp = (idx_value >> 27) & 0x7; |
551ebd83 DA |
1600 | if (tmp == 2 || tmp == 6) |
1601 | track->textures[i].roundup_h = false; | |
1602 | break; | |
1603 | case RADEON_PP_TXFORMAT_0: | |
1604 | case RADEON_PP_TXFORMAT_1: | |
1605 | case RADEON_PP_TXFORMAT_2: | |
1606 | i = (reg - RADEON_PP_TXFORMAT_0) / 24; | |
513bcb46 | 1607 | if (idx_value & RADEON_TXFORMAT_NON_POWER2) { |
551ebd83 DA |
1608 | track->textures[i].use_pitch = 1; |
1609 | } else { | |
1610 | track->textures[i].use_pitch = 0; | |
513bcb46 DA |
1611 | track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); |
1612 | track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); | |
551ebd83 | 1613 | } |
513bcb46 | 1614 | if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) |
551ebd83 | 1615 | track->textures[i].tex_coord_type = 2; |
513bcb46 | 1616 | switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { |
551ebd83 DA |
1617 | case RADEON_TXFORMAT_I8: |
1618 | case RADEON_TXFORMAT_RGB332: | |
1619 | case RADEON_TXFORMAT_Y8: | |
1620 | track->textures[i].cpp = 1; | |
1621 | break; | |
1622 | case RADEON_TXFORMAT_AI88: | |
1623 | case RADEON_TXFORMAT_ARGB1555: | |
1624 | case RADEON_TXFORMAT_RGB565: | |
1625 | case RADEON_TXFORMAT_ARGB4444: | |
1626 | case RADEON_TXFORMAT_VYUY422: | |
1627 | case RADEON_TXFORMAT_YVYU422: | |
551ebd83 DA |
1628 | case RADEON_TXFORMAT_SHADOW16: |
1629 | case RADEON_TXFORMAT_LDUDV655: | |
1630 | case RADEON_TXFORMAT_DUDV88: | |
1631 | track->textures[i].cpp = 2; | |
771fe6b9 | 1632 | break; |
551ebd83 DA |
1633 | case RADEON_TXFORMAT_ARGB8888: |
1634 | case RADEON_TXFORMAT_RGBA8888: | |
551ebd83 DA |
1635 | case RADEON_TXFORMAT_SHADOW32: |
1636 | case RADEON_TXFORMAT_LDUDUV8888: | |
1637 | track->textures[i].cpp = 4; | |
1638 | break; | |
d785d78b DA |
1639 | case RADEON_TXFORMAT_DXT1: |
1640 | track->textures[i].cpp = 1; | |
1641 | track->textures[i].compress_format = R100_TRACK_COMP_DXT1; | |
1642 | break; | |
1643 | case RADEON_TXFORMAT_DXT23: | |
1644 | case RADEON_TXFORMAT_DXT45: | |
1645 | track->textures[i].cpp = 1; | |
1646 | track->textures[i].compress_format = R100_TRACK_COMP_DXT35; | |
1647 | break; | |
551ebd83 | 1648 | } |
513bcb46 DA |
1649 | track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); |
1650 | track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); | |
551ebd83 DA |
1651 | break; |
1652 | case RADEON_PP_CUBIC_FACES_0: | |
1653 | case RADEON_PP_CUBIC_FACES_1: | |
1654 | case RADEON_PP_CUBIC_FACES_2: | |
513bcb46 | 1655 | tmp = idx_value; |
551ebd83 DA |
1656 | i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; |
1657 | for (face = 0; face < 4; face++) { | |
1658 | track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); | |
1659 | track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); | |
771fe6b9 | 1660 | } |
551ebd83 DA |
1661 | break; |
1662 | default: | |
1663 | printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", | |
1664 | reg, idx); | |
1665 | return -EINVAL; | |
771fe6b9 JG |
1666 | } |
1667 | return 0; | |
1668 | } | |
1669 | ||
068a117c JG |
1670 | int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1671 | struct radeon_cs_packet *pkt, | |
4c788679 | 1672 | struct radeon_bo *robj) |
068a117c | 1673 | { |
068a117c | 1674 | unsigned idx; |
513bcb46 | 1675 | u32 value; |
068a117c | 1676 | idx = pkt->idx + 1; |
513bcb46 | 1677 | value = radeon_get_ib_value(p, idx + 2); |
4c788679 | 1678 | if ((value + 1) > radeon_bo_size(robj)) { |
068a117c JG |
1679 | DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
1680 | "(need %u have %lu) !\n", | |
513bcb46 | 1681 | value + 1, |
4c788679 | 1682 | radeon_bo_size(robj)); |
068a117c JG |
1683 | return -EINVAL; |
1684 | } | |
1685 | return 0; | |
1686 | } | |
1687 | ||
771fe6b9 JG |
1688 | static int r100_packet3_check(struct radeon_cs_parser *p, |
1689 | struct radeon_cs_packet *pkt) | |
1690 | { | |
771fe6b9 | 1691 | struct radeon_cs_reloc *reloc; |
551ebd83 | 1692 | struct r100_cs_track *track; |
771fe6b9 | 1693 | unsigned idx; |
771fe6b9 JG |
1694 | volatile uint32_t *ib; |
1695 | int r; | |
1696 | ||
1697 | ib = p->ib->ptr; | |
771fe6b9 | 1698 | idx = pkt->idx + 1; |
551ebd83 | 1699 | track = (struct r100_cs_track *)p->track; |
771fe6b9 JG |
1700 | switch (pkt->opcode) { |
1701 | case PACKET3_3D_LOAD_VBPNTR: | |
513bcb46 DA |
1702 | r = r100_packet3_load_vbpntr(p, pkt, idx); |
1703 | if (r) | |
1704 | return r; | |
771fe6b9 JG |
1705 | break; |
1706 | case PACKET3_INDX_BUFFER: | |
1707 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1708 | if (r) { | |
1709 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | |
1710 | r100_cs_dump_packet(p, pkt); | |
1711 | return r; | |
1712 | } | |
513bcb46 | 1713 | ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); |
068a117c JG |
1714 | r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
1715 | if (r) { | |
1716 | return r; | |
1717 | } | |
771fe6b9 JG |
1718 | break; |
1719 | case 0x23: | |
771fe6b9 JG |
1720 | /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
1721 | r = r100_cs_packet_next_reloc(p, &reloc); | |
1722 | if (r) { | |
1723 | DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); | |
1724 | r100_cs_dump_packet(p, pkt); | |
1725 | return r; | |
1726 | } | |
513bcb46 | 1727 | ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); |
551ebd83 | 1728 | track->num_arrays = 1; |
513bcb46 | 1729 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); |
551ebd83 DA |
1730 | |
1731 | track->arrays[0].robj = reloc->robj; | |
1732 | track->arrays[0].esize = track->vtx_size; | |
1733 | ||
513bcb46 | 1734 | track->max_indx = radeon_get_ib_value(p, idx+1); |
551ebd83 | 1735 | |
513bcb46 | 1736 | track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); |
551ebd83 DA |
1737 | track->immd_dwords = pkt->count - 1; |
1738 | r = r100_cs_track_check(p->rdev, track); | |
1739 | if (r) | |
1740 | return r; | |
771fe6b9 JG |
1741 | break; |
1742 | case PACKET3_3D_DRAW_IMMD: | |
513bcb46 | 1743 | if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { |
551ebd83 DA |
1744 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1745 | return -EINVAL; | |
1746 | } | |
cf57fc7a | 1747 | track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); |
513bcb46 | 1748 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1749 | track->immd_dwords = pkt->count - 1; |
1750 | r = r100_cs_track_check(p->rdev, track); | |
1751 | if (r) | |
1752 | return r; | |
1753 | break; | |
771fe6b9 JG |
1754 | /* triggers drawing using in-packet vertex data */ |
1755 | case PACKET3_3D_DRAW_IMMD_2: | |
513bcb46 | 1756 | if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { |
551ebd83 DA |
1757 | DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); |
1758 | return -EINVAL; | |
1759 | } | |
513bcb46 | 1760 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1761 | track->immd_dwords = pkt->count; |
1762 | r = r100_cs_track_check(p->rdev, track); | |
1763 | if (r) | |
1764 | return r; | |
1765 | break; | |
771fe6b9 JG |
1766 | /* triggers drawing using in-packet vertex data */ |
1767 | case PACKET3_3D_DRAW_VBUF_2: | |
513bcb46 | 1768 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1769 | r = r100_cs_track_check(p->rdev, track); |
1770 | if (r) | |
1771 | return r; | |
1772 | break; | |
771fe6b9 JG |
1773 | /* triggers drawing of vertex buffers setup elsewhere */ |
1774 | case PACKET3_3D_DRAW_INDX_2: | |
513bcb46 | 1775 | track->vap_vf_cntl = radeon_get_ib_value(p, idx); |
551ebd83 DA |
1776 | r = r100_cs_track_check(p->rdev, track); |
1777 | if (r) | |
1778 | return r; | |
1779 | break; | |
771fe6b9 JG |
1780 | /* triggers drawing using indices to vertex buffer */ |
1781 | case PACKET3_3D_DRAW_VBUF: | |
513bcb46 | 1782 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1783 | r = r100_cs_track_check(p->rdev, track); |
1784 | if (r) | |
1785 | return r; | |
1786 | break; | |
771fe6b9 JG |
1787 | /* triggers drawing of vertex buffers setup elsewhere */ |
1788 | case PACKET3_3D_DRAW_INDX: | |
513bcb46 | 1789 | track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); |
551ebd83 DA |
1790 | r = r100_cs_track_check(p->rdev, track); |
1791 | if (r) | |
1792 | return r; | |
1793 | break; | |
771fe6b9 JG |
1794 | /* triggers drawing using indices to vertex buffer */ |
1795 | case PACKET3_NOP: | |
1796 | break; | |
1797 | default: | |
1798 | DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); | |
1799 | return -EINVAL; | |
1800 | } | |
1801 | return 0; | |
1802 | } | |
1803 | ||
1804 | int r100_cs_parse(struct radeon_cs_parser *p) | |
1805 | { | |
1806 | struct radeon_cs_packet pkt; | |
9f022ddf | 1807 | struct r100_cs_track *track; |
771fe6b9 JG |
1808 | int r; |
1809 | ||
9f022ddf JG |
1810 | track = kzalloc(sizeof(*track), GFP_KERNEL); |
1811 | r100_cs_track_clear(p->rdev, track); | |
1812 | p->track = track; | |
771fe6b9 JG |
1813 | do { |
1814 | r = r100_cs_packet_parse(p, &pkt, p->idx); | |
1815 | if (r) { | |
1816 | return r; | |
1817 | } | |
1818 | p->idx += pkt.count + 2; | |
1819 | switch (pkt.type) { | |
068a117c | 1820 | case PACKET_TYPE0: |
551ebd83 DA |
1821 | if (p->rdev->family >= CHIP_R200) |
1822 | r = r100_cs_parse_packet0(p, &pkt, | |
1823 | p->rdev->config.r100.reg_safe_bm, | |
1824 | p->rdev->config.r100.reg_safe_bm_size, | |
1825 | &r200_packet0_check); | |
1826 | else | |
1827 | r = r100_cs_parse_packet0(p, &pkt, | |
1828 | p->rdev->config.r100.reg_safe_bm, | |
1829 | p->rdev->config.r100.reg_safe_bm_size, | |
1830 | &r100_packet0_check); | |
068a117c JG |
1831 | break; |
1832 | case PACKET_TYPE2: | |
1833 | break; | |
1834 | case PACKET_TYPE3: | |
1835 | r = r100_packet3_check(p, &pkt); | |
1836 | break; | |
1837 | default: | |
1838 | DRM_ERROR("Unknown packet type %d !\n", | |
1839 | pkt.type); | |
1840 | return -EINVAL; | |
771fe6b9 JG |
1841 | } |
1842 | if (r) { | |
1843 | return r; | |
1844 | } | |
1845 | } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); | |
1846 | return 0; | |
1847 | } | |
1848 | ||
1849 | ||
1850 | /* | |
1851 | * Global GPU functions | |
1852 | */ | |
1853 | void r100_errata(struct radeon_device *rdev) | |
1854 | { | |
1855 | rdev->pll_errata = 0; | |
1856 | ||
1857 | if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { | |
1858 | rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; | |
1859 | } | |
1860 | ||
1861 | if (rdev->family == CHIP_RV100 || | |
1862 | rdev->family == CHIP_RS100 || | |
1863 | rdev->family == CHIP_RS200) { | |
1864 | rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; | |
1865 | } | |
1866 | } | |
1867 | ||
1868 | /* Wait for vertical sync on primary CRTC */ | |
1869 | void r100_gpu_wait_for_vsync(struct radeon_device *rdev) | |
1870 | { | |
1871 | uint32_t crtc_gen_cntl, tmp; | |
1872 | int i; | |
1873 | ||
1874 | crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); | |
1875 | if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || | |
1876 | !(crtc_gen_cntl & RADEON_CRTC_EN)) { | |
1877 | return; | |
1878 | } | |
1879 | /* Clear the CRTC_VBLANK_SAVE bit */ | |
1880 | WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); | |
1881 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1882 | tmp = RREG32(RADEON_CRTC_STATUS); | |
1883 | if (tmp & RADEON_CRTC_VBLANK_SAVE) { | |
1884 | return; | |
1885 | } | |
1886 | DRM_UDELAY(1); | |
1887 | } | |
1888 | } | |
1889 | ||
1890 | /* Wait for vertical sync on secondary CRTC */ | |
1891 | void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) | |
1892 | { | |
1893 | uint32_t crtc2_gen_cntl, tmp; | |
1894 | int i; | |
1895 | ||
1896 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); | |
1897 | if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || | |
1898 | !(crtc2_gen_cntl & RADEON_CRTC2_EN)) | |
1899 | return; | |
1900 | ||
1901 | /* Clear the CRTC_VBLANK_SAVE bit */ | |
1902 | WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); | |
1903 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1904 | tmp = RREG32(RADEON_CRTC2_STATUS); | |
1905 | if (tmp & RADEON_CRTC2_VBLANK_SAVE) { | |
1906 | return; | |
1907 | } | |
1908 | DRM_UDELAY(1); | |
1909 | } | |
1910 | } | |
1911 | ||
1912 | int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) | |
1913 | { | |
1914 | unsigned i; | |
1915 | uint32_t tmp; | |
1916 | ||
1917 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1918 | tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; | |
1919 | if (tmp >= n) { | |
1920 | return 0; | |
1921 | } | |
1922 | DRM_UDELAY(1); | |
1923 | } | |
1924 | return -1; | |
1925 | } | |
1926 | ||
1927 | int r100_gui_wait_for_idle(struct radeon_device *rdev) | |
1928 | { | |
1929 | unsigned i; | |
1930 | uint32_t tmp; | |
1931 | ||
1932 | if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { | |
1933 | printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" | |
1934 | " Bad things might happen.\n"); | |
1935 | } | |
1936 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1937 | tmp = RREG32(RADEON_RBBM_STATUS); | |
4612dc97 | 1938 | if (!(tmp & RADEON_RBBM_ACTIVE)) { |
771fe6b9 JG |
1939 | return 0; |
1940 | } | |
1941 | DRM_UDELAY(1); | |
1942 | } | |
1943 | return -1; | |
1944 | } | |
1945 | ||
1946 | int r100_mc_wait_for_idle(struct radeon_device *rdev) | |
1947 | { | |
1948 | unsigned i; | |
1949 | uint32_t tmp; | |
1950 | ||
1951 | for (i = 0; i < rdev->usec_timeout; i++) { | |
1952 | /* read MC_STATUS */ | |
4612dc97 AD |
1953 | tmp = RREG32(RADEON_MC_STATUS); |
1954 | if (tmp & RADEON_MC_IDLE) { | |
771fe6b9 JG |
1955 | return 0; |
1956 | } | |
1957 | DRM_UDELAY(1); | |
1958 | } | |
1959 | return -1; | |
1960 | } | |
1961 | ||
225758d8 | 1962 | void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp) |
771fe6b9 | 1963 | { |
225758d8 JG |
1964 | lockup->last_cp_rptr = cp->rptr; |
1965 | lockup->last_jiffies = jiffies; | |
1966 | } | |
1967 | ||
1968 | /** | |
1969 | * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information | |
1970 | * @rdev: radeon device structure | |
1971 | * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations | |
1972 | * @cp: radeon_cp structure holding CP information | |
1973 | * | |
1974 | * We don't need to initialize the lockup tracking information as we will either | |
1975 | * have CP rptr to a different value of jiffies wrap around which will force | |
1976 | * initialization of the lockup tracking informations. | |
1977 | * | |
1978 | * A possible false positivie is if we get call after while and last_cp_rptr == | |
1979 | * the current CP rptr, even if it's unlikely it might happen. To avoid this | |
1980 | * if the elapsed time since last call is bigger than 2 second than we return | |
1981 | * false and update the tracking information. Due to this the caller must call | |
1982 | * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported | |
1983 | * the fencing code should be cautious about that. | |
1984 | * | |
1985 | * Caller should write to the ring to force CP to do something so we don't get | |
1986 | * false positive when CP is just gived nothing to do. | |
1987 | * | |
1988 | **/ | |
1989 | bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp) | |
1990 | { | |
1991 | unsigned long cjiffies, elapsed; | |
1992 | ||
1993 | cjiffies = jiffies; | |
1994 | if (!time_after(cjiffies, lockup->last_jiffies)) { | |
1995 | /* likely a wrap around */ | |
1996 | lockup->last_cp_rptr = cp->rptr; | |
1997 | lockup->last_jiffies = jiffies; | |
1998 | return false; | |
1999 | } | |
2000 | if (cp->rptr != lockup->last_cp_rptr) { | |
2001 | /* CP is still working no lockup */ | |
2002 | lockup->last_cp_rptr = cp->rptr; | |
2003 | lockup->last_jiffies = jiffies; | |
2004 | return false; | |
2005 | } | |
2006 | elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); | |
2007 | if (elapsed >= 3000) { | |
2008 | /* very likely the improbable case where current | |
2009 | * rptr is equal to last recorded, a while ago, rptr | |
2010 | * this is more likely a false positive update tracking | |
2011 | * information which should force us to be recall at | |
2012 | * latter point | |
2013 | */ | |
2014 | lockup->last_cp_rptr = cp->rptr; | |
2015 | lockup->last_jiffies = jiffies; | |
2016 | return false; | |
2017 | } | |
2018 | if (elapsed >= 1000) { | |
2019 | dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); | |
2020 | return true; | |
2021 | } | |
2022 | /* give a chance to the GPU ... */ | |
2023 | return false; | |
771fe6b9 JG |
2024 | } |
2025 | ||
225758d8 | 2026 | bool r100_gpu_is_lockup(struct radeon_device *rdev) |
771fe6b9 | 2027 | { |
225758d8 JG |
2028 | u32 rbbm_status; |
2029 | int r; | |
771fe6b9 | 2030 | |
225758d8 JG |
2031 | rbbm_status = RREG32(R_000E40_RBBM_STATUS); |
2032 | if (!G_000E40_GUI_ACTIVE(rbbm_status)) { | |
2033 | r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp); | |
2034 | return false; | |
2035 | } | |
2036 | /* force CP activities */ | |
2037 | r = radeon_ring_lock(rdev, 2); | |
2038 | if (!r) { | |
2039 | /* PACKET2 NOP */ | |
2040 | radeon_ring_write(rdev, 0x80000000); | |
2041 | radeon_ring_write(rdev, 0x80000000); | |
2042 | radeon_ring_unlock_commit(rdev); | |
2043 | } | |
2044 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); | |
2045 | return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp); | |
771fe6b9 JG |
2046 | } |
2047 | ||
90aca4d2 | 2048 | void r100_bm_disable(struct radeon_device *rdev) |
771fe6b9 | 2049 | { |
90aca4d2 | 2050 | u32 tmp; |
771fe6b9 | 2051 | |
90aca4d2 JG |
2052 | /* disable bus mastering */ |
2053 | tmp = RREG32(R_000030_BUS_CNTL); | |
2054 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); | |
2055 | mdelay(1); | |
2056 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); | |
2057 | mdelay(1); | |
2058 | WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); | |
2059 | tmp = RREG32(RADEON_BUS_CNTL); | |
2060 | mdelay(1); | |
2061 | pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp); | |
2062 | pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB); | |
771fe6b9 | 2063 | mdelay(1); |
771fe6b9 JG |
2064 | } |
2065 | ||
a2d07b74 | 2066 | int r100_asic_reset(struct radeon_device *rdev) |
771fe6b9 | 2067 | { |
90aca4d2 JG |
2068 | struct r100_mc_save save; |
2069 | u32 status, tmp; | |
771fe6b9 | 2070 | |
90aca4d2 JG |
2071 | r100_mc_stop(rdev, &save); |
2072 | status = RREG32(R_000E40_RBBM_STATUS); | |
2073 | if (!G_000E40_GUI_ACTIVE(status)) { | |
2074 | return 0; | |
771fe6b9 | 2075 | } |
90aca4d2 JG |
2076 | status = RREG32(R_000E40_RBBM_STATUS); |
2077 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
2078 | /* stop CP */ | |
2079 | WREG32(RADEON_CP_CSQ_CNTL, 0); | |
2080 | tmp = RREG32(RADEON_CP_RB_CNTL); | |
2081 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); | |
2082 | WREG32(RADEON_CP_RB_RPTR_WR, 0); | |
2083 | WREG32(RADEON_CP_RB_WPTR, 0); | |
2084 | WREG32(RADEON_CP_RB_CNTL, tmp); | |
2085 | /* save PCI state */ | |
2086 | pci_save_state(rdev->pdev); | |
2087 | /* disable bus mastering */ | |
2088 | r100_bm_disable(rdev); | |
2089 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | | |
2090 | S_0000F0_SOFT_RESET_RE(1) | | |
2091 | S_0000F0_SOFT_RESET_PP(1) | | |
2092 | S_0000F0_SOFT_RESET_RB(1)); | |
2093 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
2094 | mdelay(500); | |
2095 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
2096 | mdelay(1); | |
2097 | status = RREG32(R_000E40_RBBM_STATUS); | |
2098 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
771fe6b9 | 2099 | /* reset CP */ |
90aca4d2 JG |
2100 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
2101 | RREG32(R_0000F0_RBBM_SOFT_RESET); | |
2102 | mdelay(500); | |
2103 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); | |
2104 | mdelay(1); | |
2105 | status = RREG32(R_000E40_RBBM_STATUS); | |
2106 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); | |
2107 | /* restore PCI & busmastering */ | |
2108 | pci_restore_state(rdev->pdev); | |
2109 | r100_enable_bm(rdev); | |
771fe6b9 | 2110 | /* Check if GPU is idle */ |
90aca4d2 JG |
2111 | if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || |
2112 | G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { | |
2113 | dev_err(rdev->dev, "failed to reset GPU\n"); | |
2114 | rdev->gpu_lockup = true; | |
771fe6b9 JG |
2115 | return -1; |
2116 | } | |
90aca4d2 JG |
2117 | r100_mc_resume(rdev, &save); |
2118 | dev_info(rdev->dev, "GPU reset succeed\n"); | |
771fe6b9 JG |
2119 | return 0; |
2120 | } | |
2121 | ||
92cde00c AD |
2122 | void r100_set_common_regs(struct radeon_device *rdev) |
2123 | { | |
2739d49c AD |
2124 | struct drm_device *dev = rdev->ddev; |
2125 | bool force_dac2 = false; | |
d668046c | 2126 | u32 tmp; |
2739d49c | 2127 | |
92cde00c AD |
2128 | /* set these so they don't interfere with anything */ |
2129 | WREG32(RADEON_OV0_SCALE_CNTL, 0); | |
2130 | WREG32(RADEON_SUBPIC_CNTL, 0); | |
2131 | WREG32(RADEON_VIPH_CONTROL, 0); | |
2132 | WREG32(RADEON_I2C_CNTL_1, 0); | |
2133 | WREG32(RADEON_DVI_I2C_CNTL_1, 0); | |
2134 | WREG32(RADEON_CAP0_TRIG_CNTL, 0); | |
2135 | WREG32(RADEON_CAP1_TRIG_CNTL, 0); | |
2739d49c AD |
2136 | |
2137 | /* always set up dac2 on rn50 and some rv100 as lots | |
2138 | * of servers seem to wire it up to a VGA port but | |
2139 | * don't report it in the bios connector | |
2140 | * table. | |
2141 | */ | |
2142 | switch (dev->pdev->device) { | |
2143 | /* RN50 */ | |
2144 | case 0x515e: | |
2145 | case 0x5969: | |
2146 | force_dac2 = true; | |
2147 | break; | |
2148 | /* RV100*/ | |
2149 | case 0x5159: | |
2150 | case 0x515a: | |
2151 | /* DELL triple head servers */ | |
2152 | if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && | |
2153 | ((dev->pdev->subsystem_device == 0x016c) || | |
2154 | (dev->pdev->subsystem_device == 0x016d) || | |
2155 | (dev->pdev->subsystem_device == 0x016e) || | |
2156 | (dev->pdev->subsystem_device == 0x016f) || | |
2157 | (dev->pdev->subsystem_device == 0x0170) || | |
2158 | (dev->pdev->subsystem_device == 0x017d) || | |
2159 | (dev->pdev->subsystem_device == 0x017e) || | |
2160 | (dev->pdev->subsystem_device == 0x0183) || | |
2161 | (dev->pdev->subsystem_device == 0x018a) || | |
2162 | (dev->pdev->subsystem_device == 0x019a))) | |
2163 | force_dac2 = true; | |
2164 | break; | |
2165 | } | |
2166 | ||
2167 | if (force_dac2) { | |
2168 | u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); | |
2169 | u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); | |
2170 | u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); | |
2171 | ||
2172 | /* For CRT on DAC2, don't turn it on if BIOS didn't | |
2173 | enable it, even it's detected. | |
2174 | */ | |
2175 | ||
2176 | /* force it to crtc0 */ | |
2177 | dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; | |
2178 | dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; | |
2179 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; | |
2180 | ||
2181 | /* set up the TV DAC */ | |
2182 | tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | | |
2183 | RADEON_TV_DAC_STD_MASK | | |
2184 | RADEON_TV_DAC_RDACPD | | |
2185 | RADEON_TV_DAC_GDACPD | | |
2186 | RADEON_TV_DAC_BDACPD | | |
2187 | RADEON_TV_DAC_BGADJ_MASK | | |
2188 | RADEON_TV_DAC_DACADJ_MASK); | |
2189 | tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | | |
2190 | RADEON_TV_DAC_NHOLD | | |
2191 | RADEON_TV_DAC_STD_PS2 | | |
2192 | (0x58 << 16)); | |
2193 | ||
2194 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); | |
2195 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); | |
2196 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); | |
2197 | } | |
d668046c DA |
2198 | |
2199 | /* switch PM block to ACPI mode */ | |
2200 | tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); | |
2201 | tmp &= ~RADEON_PM_MODE_SEL; | |
2202 | WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); | |
2203 | ||
92cde00c | 2204 | } |
771fe6b9 JG |
2205 | |
2206 | /* | |
2207 | * VRAM info | |
2208 | */ | |
2209 | static void r100_vram_get_type(struct radeon_device *rdev) | |
2210 | { | |
2211 | uint32_t tmp; | |
2212 | ||
2213 | rdev->mc.vram_is_ddr = false; | |
2214 | if (rdev->flags & RADEON_IS_IGP) | |
2215 | rdev->mc.vram_is_ddr = true; | |
2216 | else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) | |
2217 | rdev->mc.vram_is_ddr = true; | |
2218 | if ((rdev->family == CHIP_RV100) || | |
2219 | (rdev->family == CHIP_RS100) || | |
2220 | (rdev->family == CHIP_RS200)) { | |
2221 | tmp = RREG32(RADEON_MEM_CNTL); | |
2222 | if (tmp & RV100_HALF_MODE) { | |
2223 | rdev->mc.vram_width = 32; | |
2224 | } else { | |
2225 | rdev->mc.vram_width = 64; | |
2226 | } | |
2227 | if (rdev->flags & RADEON_SINGLE_CRTC) { | |
2228 | rdev->mc.vram_width /= 4; | |
2229 | rdev->mc.vram_is_ddr = true; | |
2230 | } | |
2231 | } else if (rdev->family <= CHIP_RV280) { | |
2232 | tmp = RREG32(RADEON_MEM_CNTL); | |
2233 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { | |
2234 | rdev->mc.vram_width = 128; | |
2235 | } else { | |
2236 | rdev->mc.vram_width = 64; | |
2237 | } | |
2238 | } else { | |
2239 | /* newer IGPs */ | |
2240 | rdev->mc.vram_width = 128; | |
2241 | } | |
2242 | } | |
2243 | ||
2a0f8918 | 2244 | static u32 r100_get_accessible_vram(struct radeon_device *rdev) |
771fe6b9 | 2245 | { |
2a0f8918 DA |
2246 | u32 aper_size; |
2247 | u8 byte; | |
2248 | ||
2249 | aper_size = RREG32(RADEON_CONFIG_APER_SIZE); | |
2250 | ||
2251 | /* Set HDP_APER_CNTL only on cards that are known not to be broken, | |
2252 | * that is has the 2nd generation multifunction PCI interface | |
2253 | */ | |
2254 | if (rdev->family == CHIP_RV280 || | |
2255 | rdev->family >= CHIP_RV350) { | |
2256 | WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, | |
2257 | ~RADEON_HDP_APER_CNTL); | |
2258 | DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); | |
2259 | return aper_size * 2; | |
2260 | } | |
2261 | ||
2262 | /* Older cards have all sorts of funny issues to deal with. First | |
2263 | * check if it's a multifunction card by reading the PCI config | |
2264 | * header type... Limit those to one aperture size | |
2265 | */ | |
2266 | pci_read_config_byte(rdev->pdev, 0xe, &byte); | |
2267 | if (byte & 0x80) { | |
2268 | DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); | |
2269 | DRM_INFO("Limiting VRAM to one aperture\n"); | |
2270 | return aper_size; | |
2271 | } | |
2272 | ||
2273 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS | |
2274 | * have set it up. We don't write this as it's broken on some ASICs but | |
2275 | * we expect the BIOS to have done the right thing (might be too optimistic...) | |
2276 | */ | |
2277 | if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) | |
2278 | return aper_size * 2; | |
2279 | return aper_size; | |
2280 | } | |
2281 | ||
2282 | void r100_vram_init_sizes(struct radeon_device *rdev) | |
2283 | { | |
2284 | u64 config_aper_size; | |
2a0f8918 | 2285 | |
d594e46a | 2286 | /* work out accessible VRAM */ |
d594e46a JG |
2287 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
2288 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | |
51e5fcd3 JG |
2289 | rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); |
2290 | /* FIXME we don't use the second aperture yet when we could use it */ | |
2291 | if (rdev->mc.visible_vram_size > rdev->mc.aper_size) | |
2292 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | |
2a0f8918 | 2293 | config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); |
771fe6b9 JG |
2294 | if (rdev->flags & RADEON_IS_IGP) { |
2295 | uint32_t tom; | |
2296 | /* read NB_TOM to get the amount of ram stolen for the GPU */ | |
2297 | tom = RREG32(RADEON_NB_TOM); | |
7a50f01a | 2298 | rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); |
7a50f01a DA |
2299 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
2300 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
771fe6b9 | 2301 | } else { |
7a50f01a | 2302 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
771fe6b9 JG |
2303 | /* Some production boards of m6 will report 0 |
2304 | * if it's 8 MB | |
2305 | */ | |
7a50f01a DA |
2306 | if (rdev->mc.real_vram_size == 0) { |
2307 | rdev->mc.real_vram_size = 8192 * 1024; | |
2308 | WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); | |
771fe6b9 | 2309 | } |
d594e46a JG |
2310 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
2311 | * Novell bug 204882 + along with lots of ubuntu ones | |
2312 | */ | |
7a50f01a DA |
2313 | if (config_aper_size > rdev->mc.real_vram_size) |
2314 | rdev->mc.mc_vram_size = config_aper_size; | |
2315 | else | |
2316 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; | |
771fe6b9 | 2317 | } |
2a0f8918 DA |
2318 | } |
2319 | ||
28d52043 DA |
2320 | void r100_vga_set_state(struct radeon_device *rdev, bool state) |
2321 | { | |
2322 | uint32_t temp; | |
2323 | ||
2324 | temp = RREG32(RADEON_CONFIG_CNTL); | |
2325 | if (state == false) { | |
2326 | temp &= ~(1<<8); | |
2327 | temp |= (1<<9); | |
2328 | } else { | |
2329 | temp &= ~(1<<9); | |
2330 | } | |
2331 | WREG32(RADEON_CONFIG_CNTL, temp); | |
2332 | } | |
2333 | ||
d594e46a | 2334 | void r100_mc_init(struct radeon_device *rdev) |
2a0f8918 | 2335 | { |
d594e46a | 2336 | u64 base; |
2a0f8918 | 2337 | |
d594e46a | 2338 | r100_vram_get_type(rdev); |
2a0f8918 | 2339 | r100_vram_init_sizes(rdev); |
d594e46a JG |
2340 | base = rdev->mc.aper_base; |
2341 | if (rdev->flags & RADEON_IS_IGP) | |
2342 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; | |
2343 | radeon_vram_location(rdev, &rdev->mc, base); | |
2344 | if (!(rdev->flags & RADEON_IS_AGP)) | |
2345 | radeon_gtt_location(rdev, &rdev->mc); | |
f47299c5 | 2346 | radeon_update_bandwidth_info(rdev); |
771fe6b9 JG |
2347 | } |
2348 | ||
2349 | ||
2350 | /* | |
2351 | * Indirect registers accessor | |
2352 | */ | |
2353 | void r100_pll_errata_after_index(struct radeon_device *rdev) | |
2354 | { | |
2355 | if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) { | |
2356 | return; | |
2357 | } | |
2358 | (void)RREG32(RADEON_CLOCK_CNTL_DATA); | |
2359 | (void)RREG32(RADEON_CRTC_GEN_CNTL); | |
2360 | } | |
2361 | ||
2362 | static void r100_pll_errata_after_data(struct radeon_device *rdev) | |
2363 | { | |
2364 | /* This workarounds is necessary on RV100, RS100 and RS200 chips | |
2365 | * or the chip could hang on a subsequent access | |
2366 | */ | |
2367 | if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { | |
2368 | udelay(5000); | |
2369 | } | |
2370 | ||
2371 | /* This function is required to workaround a hardware bug in some (all?) | |
2372 | * revisions of the R300. This workaround should be called after every | |
2373 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward | |
2374 | * may not be correct. | |
2375 | */ | |
2376 | if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { | |
2377 | uint32_t save, tmp; | |
2378 | ||
2379 | save = RREG32(RADEON_CLOCK_CNTL_INDEX); | |
2380 | tmp = save & ~(0x3f | RADEON_PLL_WR_EN); | |
2381 | WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); | |
2382 | tmp = RREG32(RADEON_CLOCK_CNTL_DATA); | |
2383 | WREG32(RADEON_CLOCK_CNTL_INDEX, save); | |
2384 | } | |
2385 | } | |
2386 | ||
2387 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) | |
2388 | { | |
2389 | uint32_t data; | |
2390 | ||
2391 | WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); | |
2392 | r100_pll_errata_after_index(rdev); | |
2393 | data = RREG32(RADEON_CLOCK_CNTL_DATA); | |
2394 | r100_pll_errata_after_data(rdev); | |
2395 | return data; | |
2396 | } | |
2397 | ||
2398 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
2399 | { | |
2400 | WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); | |
2401 | r100_pll_errata_after_index(rdev); | |
2402 | WREG32(RADEON_CLOCK_CNTL_DATA, v); | |
2403 | r100_pll_errata_after_data(rdev); | |
2404 | } | |
2405 | ||
d4550907 | 2406 | void r100_set_safe_registers(struct radeon_device *rdev) |
068a117c | 2407 | { |
551ebd83 DA |
2408 | if (ASIC_IS_RN50(rdev)) { |
2409 | rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; | |
2410 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); | |
2411 | } else if (rdev->family < CHIP_R200) { | |
2412 | rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; | |
2413 | rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); | |
2414 | } else { | |
d4550907 | 2415 | r200_set_safe_registers(rdev); |
551ebd83 | 2416 | } |
068a117c JG |
2417 | } |
2418 | ||
771fe6b9 JG |
2419 | /* |
2420 | * Debugfs info | |
2421 | */ | |
2422 | #if defined(CONFIG_DEBUG_FS) | |
2423 | static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) | |
2424 | { | |
2425 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2426 | struct drm_device *dev = node->minor->dev; | |
2427 | struct radeon_device *rdev = dev->dev_private; | |
2428 | uint32_t reg, value; | |
2429 | unsigned i; | |
2430 | ||
2431 | seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); | |
2432 | seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); | |
2433 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); | |
2434 | for (i = 0; i < 64; i++) { | |
2435 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); | |
2436 | reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; | |
2437 | WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); | |
2438 | value = RREG32(RADEON_RBBM_CMDFIFO_DATA); | |
2439 | seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); | |
2440 | } | |
2441 | return 0; | |
2442 | } | |
2443 | ||
2444 | static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) | |
2445 | { | |
2446 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2447 | struct drm_device *dev = node->minor->dev; | |
2448 | struct radeon_device *rdev = dev->dev_private; | |
2449 | uint32_t rdp, wdp; | |
2450 | unsigned count, i, j; | |
2451 | ||
2452 | radeon_ring_free_size(rdev); | |
2453 | rdp = RREG32(RADEON_CP_RB_RPTR); | |
2454 | wdp = RREG32(RADEON_CP_RB_WPTR); | |
2455 | count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; | |
2456 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); | |
2457 | seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); | |
2458 | seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); | |
2459 | seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); | |
2460 | seq_printf(m, "%u dwords in ring\n", count); | |
2461 | for (j = 0; j <= count; j++) { | |
2462 | i = (rdp + j) & rdev->cp.ptr_mask; | |
2463 | seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); | |
2464 | } | |
2465 | return 0; | |
2466 | } | |
2467 | ||
2468 | ||
2469 | static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) | |
2470 | { | |
2471 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2472 | struct drm_device *dev = node->minor->dev; | |
2473 | struct radeon_device *rdev = dev->dev_private; | |
2474 | uint32_t csq_stat, csq2_stat, tmp; | |
2475 | unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; | |
2476 | unsigned i; | |
2477 | ||
2478 | seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); | |
2479 | seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); | |
2480 | csq_stat = RREG32(RADEON_CP_CSQ_STAT); | |
2481 | csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); | |
2482 | r_rptr = (csq_stat >> 0) & 0x3ff; | |
2483 | r_wptr = (csq_stat >> 10) & 0x3ff; | |
2484 | ib1_rptr = (csq_stat >> 20) & 0x3ff; | |
2485 | ib1_wptr = (csq2_stat >> 0) & 0x3ff; | |
2486 | ib2_rptr = (csq2_stat >> 10) & 0x3ff; | |
2487 | ib2_wptr = (csq2_stat >> 20) & 0x3ff; | |
2488 | seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); | |
2489 | seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); | |
2490 | seq_printf(m, "Ring rptr %u\n", r_rptr); | |
2491 | seq_printf(m, "Ring wptr %u\n", r_wptr); | |
2492 | seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); | |
2493 | seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); | |
2494 | seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); | |
2495 | seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); | |
2496 | /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms | |
2497 | * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ | |
2498 | seq_printf(m, "Ring fifo:\n"); | |
2499 | for (i = 0; i < 256; i++) { | |
2500 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
2501 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
2502 | seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); | |
2503 | } | |
2504 | seq_printf(m, "Indirect1 fifo:\n"); | |
2505 | for (i = 256; i <= 512; i++) { | |
2506 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
2507 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
2508 | seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); | |
2509 | } | |
2510 | seq_printf(m, "Indirect2 fifo:\n"); | |
2511 | for (i = 640; i < ib1_wptr; i++) { | |
2512 | WREG32(RADEON_CP_CSQ_ADDR, i << 2); | |
2513 | tmp = RREG32(RADEON_CP_CSQ_DATA); | |
2514 | seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); | |
2515 | } | |
2516 | return 0; | |
2517 | } | |
2518 | ||
2519 | static int r100_debugfs_mc_info(struct seq_file *m, void *data) | |
2520 | { | |
2521 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
2522 | struct drm_device *dev = node->minor->dev; | |
2523 | struct radeon_device *rdev = dev->dev_private; | |
2524 | uint32_t tmp; | |
2525 | ||
2526 | tmp = RREG32(RADEON_CONFIG_MEMSIZE); | |
2527 | seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); | |
2528 | tmp = RREG32(RADEON_MC_FB_LOCATION); | |
2529 | seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); | |
2530 | tmp = RREG32(RADEON_BUS_CNTL); | |
2531 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); | |
2532 | tmp = RREG32(RADEON_MC_AGP_LOCATION); | |
2533 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); | |
2534 | tmp = RREG32(RADEON_AGP_BASE); | |
2535 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); | |
2536 | tmp = RREG32(RADEON_HOST_PATH_CNTL); | |
2537 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); | |
2538 | tmp = RREG32(0x01D0); | |
2539 | seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); | |
2540 | tmp = RREG32(RADEON_AIC_LO_ADDR); | |
2541 | seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); | |
2542 | tmp = RREG32(RADEON_AIC_HI_ADDR); | |
2543 | seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); | |
2544 | tmp = RREG32(0x01E4); | |
2545 | seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); | |
2546 | return 0; | |
2547 | } | |
2548 | ||
2549 | static struct drm_info_list r100_debugfs_rbbm_list[] = { | |
2550 | {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, | |
2551 | }; | |
2552 | ||
2553 | static struct drm_info_list r100_debugfs_cp_list[] = { | |
2554 | {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, | |
2555 | {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, | |
2556 | }; | |
2557 | ||
2558 | static struct drm_info_list r100_debugfs_mc_info_list[] = { | |
2559 | {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, | |
2560 | }; | |
2561 | #endif | |
2562 | ||
2563 | int r100_debugfs_rbbm_init(struct radeon_device *rdev) | |
2564 | { | |
2565 | #if defined(CONFIG_DEBUG_FS) | |
2566 | return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); | |
2567 | #else | |
2568 | return 0; | |
2569 | #endif | |
2570 | } | |
2571 | ||
2572 | int r100_debugfs_cp_init(struct radeon_device *rdev) | |
2573 | { | |
2574 | #if defined(CONFIG_DEBUG_FS) | |
2575 | return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); | |
2576 | #else | |
2577 | return 0; | |
2578 | #endif | |
2579 | } | |
2580 | ||
2581 | int r100_debugfs_mc_info_init(struct radeon_device *rdev) | |
2582 | { | |
2583 | #if defined(CONFIG_DEBUG_FS) | |
2584 | return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); | |
2585 | #else | |
2586 | return 0; | |
2587 | #endif | |
2588 | } | |
e024e110 DA |
2589 | |
2590 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, | |
2591 | uint32_t tiling_flags, uint32_t pitch, | |
2592 | uint32_t offset, uint32_t obj_size) | |
2593 | { | |
2594 | int surf_index = reg * 16; | |
2595 | int flags = 0; | |
2596 | ||
2597 | /* r100/r200 divide by 16 */ | |
2598 | if (rdev->family < CHIP_R300) | |
2599 | flags = pitch / 16; | |
2600 | else | |
2601 | flags = pitch / 8; | |
2602 | ||
2603 | if (rdev->family <= CHIP_RS200) { | |
2604 | if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | |
2605 | == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) | |
2606 | flags |= RADEON_SURF_TILE_COLOR_BOTH; | |
2607 | if (tiling_flags & RADEON_TILING_MACRO) | |
2608 | flags |= RADEON_SURF_TILE_COLOR_MACRO; | |
2609 | } else if (rdev->family <= CHIP_RV280) { | |
2610 | if (tiling_flags & (RADEON_TILING_MACRO)) | |
2611 | flags |= R200_SURF_TILE_COLOR_MACRO; | |
2612 | if (tiling_flags & RADEON_TILING_MICRO) | |
2613 | flags |= R200_SURF_TILE_COLOR_MICRO; | |
2614 | } else { | |
2615 | if (tiling_flags & RADEON_TILING_MACRO) | |
2616 | flags |= R300_SURF_TILE_MACRO; | |
2617 | if (tiling_flags & RADEON_TILING_MICRO) | |
2618 | flags |= R300_SURF_TILE_MICRO; | |
2619 | } | |
2620 | ||
c88f9f0c MD |
2621 | if (tiling_flags & RADEON_TILING_SWAP_16BIT) |
2622 | flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; | |
2623 | if (tiling_flags & RADEON_TILING_SWAP_32BIT) | |
2624 | flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; | |
2625 | ||
e024e110 DA |
2626 | DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); |
2627 | WREG32(RADEON_SURFACE0_INFO + surf_index, flags); | |
2628 | WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); | |
2629 | WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); | |
2630 | return 0; | |
2631 | } | |
2632 | ||
2633 | void r100_clear_surface_reg(struct radeon_device *rdev, int reg) | |
2634 | { | |
2635 | int surf_index = reg * 16; | |
2636 | WREG32(RADEON_SURFACE0_INFO + surf_index, 0); | |
2637 | } | |
c93bb85b JG |
2638 | |
2639 | void r100_bandwidth_update(struct radeon_device *rdev) | |
2640 | { | |
2641 | fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; | |
2642 | fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; | |
2643 | fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; | |
2644 | uint32_t temp, data, mem_trcd, mem_trp, mem_tras; | |
2645 | fixed20_12 memtcas_ff[8] = { | |
68adac5e BS |
2646 | dfixed_init(1), |
2647 | dfixed_init(2), | |
2648 | dfixed_init(3), | |
2649 | dfixed_init(0), | |
2650 | dfixed_init_half(1), | |
2651 | dfixed_init_half(2), | |
2652 | dfixed_init(0), | |
c93bb85b JG |
2653 | }; |
2654 | fixed20_12 memtcas_rs480_ff[8] = { | |
68adac5e BS |
2655 | dfixed_init(0), |
2656 | dfixed_init(1), | |
2657 | dfixed_init(2), | |
2658 | dfixed_init(3), | |
2659 | dfixed_init(0), | |
2660 | dfixed_init_half(1), | |
2661 | dfixed_init_half(2), | |
2662 | dfixed_init_half(3), | |
c93bb85b JG |
2663 | }; |
2664 | fixed20_12 memtcas2_ff[8] = { | |
68adac5e BS |
2665 | dfixed_init(0), |
2666 | dfixed_init(1), | |
2667 | dfixed_init(2), | |
2668 | dfixed_init(3), | |
2669 | dfixed_init(4), | |
2670 | dfixed_init(5), | |
2671 | dfixed_init(6), | |
2672 | dfixed_init(7), | |
c93bb85b JG |
2673 | }; |
2674 | fixed20_12 memtrbs[8] = { | |
68adac5e BS |
2675 | dfixed_init(1), |
2676 | dfixed_init_half(1), | |
2677 | dfixed_init(2), | |
2678 | dfixed_init_half(2), | |
2679 | dfixed_init(3), | |
2680 | dfixed_init_half(3), | |
2681 | dfixed_init(4), | |
2682 | dfixed_init_half(4) | |
c93bb85b JG |
2683 | }; |
2684 | fixed20_12 memtrbs_r4xx[8] = { | |
68adac5e BS |
2685 | dfixed_init(4), |
2686 | dfixed_init(5), | |
2687 | dfixed_init(6), | |
2688 | dfixed_init(7), | |
2689 | dfixed_init(8), | |
2690 | dfixed_init(9), | |
2691 | dfixed_init(10), | |
2692 | dfixed_init(11) | |
c93bb85b JG |
2693 | }; |
2694 | fixed20_12 min_mem_eff; | |
2695 | fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; | |
2696 | fixed20_12 cur_latency_mclk, cur_latency_sclk; | |
2697 | fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, | |
2698 | disp_drain_rate2, read_return_rate; | |
2699 | fixed20_12 time_disp1_drop_priority; | |
2700 | int c; | |
2701 | int cur_size = 16; /* in octawords */ | |
2702 | int critical_point = 0, critical_point2; | |
2703 | /* uint32_t read_return_rate, time_disp1_drop_priority; */ | |
2704 | int stop_req, max_stop_req; | |
2705 | struct drm_display_mode *mode1 = NULL; | |
2706 | struct drm_display_mode *mode2 = NULL; | |
2707 | uint32_t pixel_bytes1 = 0; | |
2708 | uint32_t pixel_bytes2 = 0; | |
2709 | ||
f46c0120 AD |
2710 | radeon_update_display_priority(rdev); |
2711 | ||
c93bb85b JG |
2712 | if (rdev->mode_info.crtcs[0]->base.enabled) { |
2713 | mode1 = &rdev->mode_info.crtcs[0]->base.mode; | |
2714 | pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; | |
2715 | } | |
dfee5614 DA |
2716 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
2717 | if (rdev->mode_info.crtcs[1]->base.enabled) { | |
2718 | mode2 = &rdev->mode_info.crtcs[1]->base.mode; | |
2719 | pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; | |
2720 | } | |
c93bb85b JG |
2721 | } |
2722 | ||
68adac5e | 2723 | min_mem_eff.full = dfixed_const_8(0); |
c93bb85b JG |
2724 | /* get modes */ |
2725 | if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { | |
2726 | uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); | |
2727 | mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); | |
2728 | mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); | |
2729 | /* check crtc enables */ | |
2730 | if (mode2) | |
2731 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); | |
2732 | if (mode1) | |
2733 | mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); | |
2734 | WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); | |
2735 | } | |
2736 | ||
2737 | /* | |
2738 | * determine is there is enough bw for current mode | |
2739 | */ | |
f47299c5 AD |
2740 | sclk_ff = rdev->pm.sclk; |
2741 | mclk_ff = rdev->pm.mclk; | |
c93bb85b JG |
2742 | |
2743 | temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); | |
68adac5e BS |
2744 | temp_ff.full = dfixed_const(temp); |
2745 | mem_bw.full = dfixed_mul(mclk_ff, temp_ff); | |
c93bb85b JG |
2746 | |
2747 | pix_clk.full = 0; | |
2748 | pix_clk2.full = 0; | |
2749 | peak_disp_bw.full = 0; | |
2750 | if (mode1) { | |
68adac5e BS |
2751 | temp_ff.full = dfixed_const(1000); |
2752 | pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ | |
2753 | pix_clk.full = dfixed_div(pix_clk, temp_ff); | |
2754 | temp_ff.full = dfixed_const(pixel_bytes1); | |
2755 | peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); | |
c93bb85b JG |
2756 | } |
2757 | if (mode2) { | |
68adac5e BS |
2758 | temp_ff.full = dfixed_const(1000); |
2759 | pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ | |
2760 | pix_clk2.full = dfixed_div(pix_clk2, temp_ff); | |
2761 | temp_ff.full = dfixed_const(pixel_bytes2); | |
2762 | peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); | |
c93bb85b JG |
2763 | } |
2764 | ||
68adac5e | 2765 | mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); |
c93bb85b JG |
2766 | if (peak_disp_bw.full >= mem_bw.full) { |
2767 | DRM_ERROR("You may not have enough display bandwidth for current mode\n" | |
2768 | "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); | |
2769 | } | |
2770 | ||
2771 | /* Get values from the EXT_MEM_CNTL register...converting its contents. */ | |
2772 | temp = RREG32(RADEON_MEM_TIMING_CNTL); | |
2773 | if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ | |
2774 | mem_trcd = ((temp >> 2) & 0x3) + 1; | |
2775 | mem_trp = ((temp & 0x3)) + 1; | |
2776 | mem_tras = ((temp & 0x70) >> 4) + 1; | |
2777 | } else if (rdev->family == CHIP_R300 || | |
2778 | rdev->family == CHIP_R350) { /* r300, r350 */ | |
2779 | mem_trcd = (temp & 0x7) + 1; | |
2780 | mem_trp = ((temp >> 8) & 0x7) + 1; | |
2781 | mem_tras = ((temp >> 11) & 0xf) + 4; | |
2782 | } else if (rdev->family == CHIP_RV350 || | |
2783 | rdev->family <= CHIP_RV380) { | |
2784 | /* rv3x0 */ | |
2785 | mem_trcd = (temp & 0x7) + 3; | |
2786 | mem_trp = ((temp >> 8) & 0x7) + 3; | |
2787 | mem_tras = ((temp >> 11) & 0xf) + 6; | |
2788 | } else if (rdev->family == CHIP_R420 || | |
2789 | rdev->family == CHIP_R423 || | |
2790 | rdev->family == CHIP_RV410) { | |
2791 | /* r4xx */ | |
2792 | mem_trcd = (temp & 0xf) + 3; | |
2793 | if (mem_trcd > 15) | |
2794 | mem_trcd = 15; | |
2795 | mem_trp = ((temp >> 8) & 0xf) + 3; | |
2796 | if (mem_trp > 15) | |
2797 | mem_trp = 15; | |
2798 | mem_tras = ((temp >> 12) & 0x1f) + 6; | |
2799 | if (mem_tras > 31) | |
2800 | mem_tras = 31; | |
2801 | } else { /* RV200, R200 */ | |
2802 | mem_trcd = (temp & 0x7) + 1; | |
2803 | mem_trp = ((temp >> 8) & 0x7) + 1; | |
2804 | mem_tras = ((temp >> 12) & 0xf) + 4; | |
2805 | } | |
2806 | /* convert to FF */ | |
68adac5e BS |
2807 | trcd_ff.full = dfixed_const(mem_trcd); |
2808 | trp_ff.full = dfixed_const(mem_trp); | |
2809 | tras_ff.full = dfixed_const(mem_tras); | |
c93bb85b JG |
2810 | |
2811 | /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ | |
2812 | temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); | |
2813 | data = (temp & (7 << 20)) >> 20; | |
2814 | if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { | |
2815 | if (rdev->family == CHIP_RS480) /* don't think rs400 */ | |
2816 | tcas_ff = memtcas_rs480_ff[data]; | |
2817 | else | |
2818 | tcas_ff = memtcas_ff[data]; | |
2819 | } else | |
2820 | tcas_ff = memtcas2_ff[data]; | |
2821 | ||
2822 | if (rdev->family == CHIP_RS400 || | |
2823 | rdev->family == CHIP_RS480) { | |
2824 | /* extra cas latency stored in bits 23-25 0-4 clocks */ | |
2825 | data = (temp >> 23) & 0x7; | |
2826 | if (data < 5) | |
68adac5e | 2827 | tcas_ff.full += dfixed_const(data); |
c93bb85b JG |
2828 | } |
2829 | ||
2830 | if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { | |
2831 | /* on the R300, Tcas is included in Trbs. | |
2832 | */ | |
2833 | temp = RREG32(RADEON_MEM_CNTL); | |
2834 | data = (R300_MEM_NUM_CHANNELS_MASK & temp); | |
2835 | if (data == 1) { | |
2836 | if (R300_MEM_USE_CD_CH_ONLY & temp) { | |
2837 | temp = RREG32(R300_MC_IND_INDEX); | |
2838 | temp &= ~R300_MC_IND_ADDR_MASK; | |
2839 | temp |= R300_MC_READ_CNTL_CD_mcind; | |
2840 | WREG32(R300_MC_IND_INDEX, temp); | |
2841 | temp = RREG32(R300_MC_IND_DATA); | |
2842 | data = (R300_MEM_RBS_POSITION_C_MASK & temp); | |
2843 | } else { | |
2844 | temp = RREG32(R300_MC_READ_CNTL_AB); | |
2845 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | |
2846 | } | |
2847 | } else { | |
2848 | temp = RREG32(R300_MC_READ_CNTL_AB); | |
2849 | data = (R300_MEM_RBS_POSITION_A_MASK & temp); | |
2850 | } | |
2851 | if (rdev->family == CHIP_RV410 || | |
2852 | rdev->family == CHIP_R420 || | |
2853 | rdev->family == CHIP_R423) | |
2854 | trbs_ff = memtrbs_r4xx[data]; | |
2855 | else | |
2856 | trbs_ff = memtrbs[data]; | |
2857 | tcas_ff.full += trbs_ff.full; | |
2858 | } | |
2859 | ||
2860 | sclk_eff_ff.full = sclk_ff.full; | |
2861 | ||
2862 | if (rdev->flags & RADEON_IS_AGP) { | |
2863 | fixed20_12 agpmode_ff; | |
68adac5e BS |
2864 | agpmode_ff.full = dfixed_const(radeon_agpmode); |
2865 | temp_ff.full = dfixed_const_666(16); | |
2866 | sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); | |
c93bb85b JG |
2867 | } |
2868 | /* TODO PCIE lanes may affect this - agpmode == 16?? */ | |
2869 | ||
2870 | if (ASIC_IS_R300(rdev)) { | |
68adac5e | 2871 | sclk_delay_ff.full = dfixed_const(250); |
c93bb85b JG |
2872 | } else { |
2873 | if ((rdev->family == CHIP_RV100) || | |
2874 | rdev->flags & RADEON_IS_IGP) { | |
2875 | if (rdev->mc.vram_is_ddr) | |
68adac5e | 2876 | sclk_delay_ff.full = dfixed_const(41); |
c93bb85b | 2877 | else |
68adac5e | 2878 | sclk_delay_ff.full = dfixed_const(33); |
c93bb85b JG |
2879 | } else { |
2880 | if (rdev->mc.vram_width == 128) | |
68adac5e | 2881 | sclk_delay_ff.full = dfixed_const(57); |
c93bb85b | 2882 | else |
68adac5e | 2883 | sclk_delay_ff.full = dfixed_const(41); |
c93bb85b JG |
2884 | } |
2885 | } | |
2886 | ||
68adac5e | 2887 | mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); |
c93bb85b JG |
2888 | |
2889 | if (rdev->mc.vram_is_ddr) { | |
2890 | if (rdev->mc.vram_width == 32) { | |
68adac5e | 2891 | k1.full = dfixed_const(40); |
c93bb85b JG |
2892 | c = 3; |
2893 | } else { | |
68adac5e | 2894 | k1.full = dfixed_const(20); |
c93bb85b JG |
2895 | c = 1; |
2896 | } | |
2897 | } else { | |
68adac5e | 2898 | k1.full = dfixed_const(40); |
c93bb85b JG |
2899 | c = 3; |
2900 | } | |
2901 | ||
68adac5e BS |
2902 | temp_ff.full = dfixed_const(2); |
2903 | mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); | |
2904 | temp_ff.full = dfixed_const(c); | |
2905 | mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); | |
2906 | temp_ff.full = dfixed_const(4); | |
2907 | mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); | |
2908 | mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); | |
c93bb85b JG |
2909 | mc_latency_mclk.full += k1.full; |
2910 | ||
68adac5e BS |
2911 | mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); |
2912 | mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); | |
c93bb85b JG |
2913 | |
2914 | /* | |
2915 | HW cursor time assuming worst case of full size colour cursor. | |
2916 | */ | |
68adac5e | 2917 | temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); |
c93bb85b JG |
2918 | temp_ff.full += trcd_ff.full; |
2919 | if (temp_ff.full < tras_ff.full) | |
2920 | temp_ff.full = tras_ff.full; | |
68adac5e | 2921 | cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); |
c93bb85b | 2922 | |
68adac5e BS |
2923 | temp_ff.full = dfixed_const(cur_size); |
2924 | cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); | |
c93bb85b JG |
2925 | /* |
2926 | Find the total latency for the display data. | |
2927 | */ | |
68adac5e BS |
2928 | disp_latency_overhead.full = dfixed_const(8); |
2929 | disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); | |
c93bb85b JG |
2930 | mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; |
2931 | mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; | |
2932 | ||
2933 | if (mc_latency_mclk.full > mc_latency_sclk.full) | |
2934 | disp_latency.full = mc_latency_mclk.full; | |
2935 | else | |
2936 | disp_latency.full = mc_latency_sclk.full; | |
2937 | ||
2938 | /* setup Max GRPH_STOP_REQ default value */ | |
2939 | if (ASIC_IS_RV100(rdev)) | |
2940 | max_stop_req = 0x5c; | |
2941 | else | |
2942 | max_stop_req = 0x7c; | |
2943 | ||
2944 | if (mode1) { | |
2945 | /* CRTC1 | |
2946 | Set GRPH_BUFFER_CNTL register using h/w defined optimal values. | |
2947 | GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] | |
2948 | */ | |
2949 | stop_req = mode1->hdisplay * pixel_bytes1 / 16; | |
2950 | ||
2951 | if (stop_req > max_stop_req) | |
2952 | stop_req = max_stop_req; | |
2953 | ||
2954 | /* | |
2955 | Find the drain rate of the display buffer. | |
2956 | */ | |
68adac5e BS |
2957 | temp_ff.full = dfixed_const((16/pixel_bytes1)); |
2958 | disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); | |
c93bb85b JG |
2959 | |
2960 | /* | |
2961 | Find the critical point of the display buffer. | |
2962 | */ | |
68adac5e BS |
2963 | crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); |
2964 | crit_point_ff.full += dfixed_const_half(0); | |
c93bb85b | 2965 | |
68adac5e | 2966 | critical_point = dfixed_trunc(crit_point_ff); |
c93bb85b JG |
2967 | |
2968 | if (rdev->disp_priority == 2) { | |
2969 | critical_point = 0; | |
2970 | } | |
2971 | ||
2972 | /* | |
2973 | The critical point should never be above max_stop_req-4. Setting | |
2974 | GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. | |
2975 | */ | |
2976 | if (max_stop_req - critical_point < 4) | |
2977 | critical_point = 0; | |
2978 | ||
2979 | if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { | |
2980 | /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ | |
2981 | critical_point = 0x10; | |
2982 | } | |
2983 | ||
2984 | temp = RREG32(RADEON_GRPH_BUFFER_CNTL); | |
2985 | temp &= ~(RADEON_GRPH_STOP_REQ_MASK); | |
2986 | temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | |
2987 | temp &= ~(RADEON_GRPH_START_REQ_MASK); | |
2988 | if ((rdev->family == CHIP_R350) && | |
2989 | (stop_req > 0x15)) { | |
2990 | stop_req -= 0x10; | |
2991 | } | |
2992 | temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); | |
2993 | temp |= RADEON_GRPH_BUFFER_SIZE; | |
2994 | temp &= ~(RADEON_GRPH_CRITICAL_CNTL | | |
2995 | RADEON_GRPH_CRITICAL_AT_SOF | | |
2996 | RADEON_GRPH_STOP_CNTL); | |
2997 | /* | |
2998 | Write the result into the register. | |
2999 | */ | |
3000 | WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | | |
3001 | (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | |
3002 | ||
3003 | #if 0 | |
3004 | if ((rdev->family == CHIP_RS400) || | |
3005 | (rdev->family == CHIP_RS480)) { | |
3006 | /* attempt to program RS400 disp regs correctly ??? */ | |
3007 | temp = RREG32(RS400_DISP1_REG_CNTL); | |
3008 | temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | | |
3009 | RS400_DISP1_STOP_REQ_LEVEL_MASK); | |
3010 | WREG32(RS400_DISP1_REQ_CNTL1, (temp | | |
3011 | (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | |
3012 | (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | |
3013 | temp = RREG32(RS400_DMIF_MEM_CNTL1); | |
3014 | temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | | |
3015 | RS400_DISP1_CRITICAL_POINT_STOP_MASK); | |
3016 | WREG32(RS400_DMIF_MEM_CNTL1, (temp | | |
3017 | (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | | |
3018 | (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); | |
3019 | } | |
3020 | #endif | |
3021 | ||
3022 | DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n", | |
3023 | /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ | |
3024 | (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); | |
3025 | } | |
3026 | ||
3027 | if (mode2) { | |
3028 | u32 grph2_cntl; | |
3029 | stop_req = mode2->hdisplay * pixel_bytes2 / 16; | |
3030 | ||
3031 | if (stop_req > max_stop_req) | |
3032 | stop_req = max_stop_req; | |
3033 | ||
3034 | /* | |
3035 | Find the drain rate of the display buffer. | |
3036 | */ | |
68adac5e BS |
3037 | temp_ff.full = dfixed_const((16/pixel_bytes2)); |
3038 | disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); | |
c93bb85b JG |
3039 | |
3040 | grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); | |
3041 | grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); | |
3042 | grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); | |
3043 | grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); | |
3044 | if ((rdev->family == CHIP_R350) && | |
3045 | (stop_req > 0x15)) { | |
3046 | stop_req -= 0x10; | |
3047 | } | |
3048 | grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); | |
3049 | grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; | |
3050 | grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | | |
3051 | RADEON_GRPH_CRITICAL_AT_SOF | | |
3052 | RADEON_GRPH_STOP_CNTL); | |
3053 | ||
3054 | if ((rdev->family == CHIP_RS100) || | |
3055 | (rdev->family == CHIP_RS200)) | |
3056 | critical_point2 = 0; | |
3057 | else { | |
3058 | temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; | |
68adac5e BS |
3059 | temp_ff.full = dfixed_const(temp); |
3060 | temp_ff.full = dfixed_mul(mclk_ff, temp_ff); | |
c93bb85b JG |
3061 | if (sclk_ff.full < temp_ff.full) |
3062 | temp_ff.full = sclk_ff.full; | |
3063 | ||
3064 | read_return_rate.full = temp_ff.full; | |
3065 | ||
3066 | if (mode1) { | |
3067 | temp_ff.full = read_return_rate.full - disp_drain_rate.full; | |
68adac5e | 3068 | time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); |
c93bb85b JG |
3069 | } else { |
3070 | time_disp1_drop_priority.full = 0; | |
3071 | } | |
3072 | crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; | |
68adac5e BS |
3073 | crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); |
3074 | crit_point_ff.full += dfixed_const_half(0); | |
c93bb85b | 3075 | |
68adac5e | 3076 | critical_point2 = dfixed_trunc(crit_point_ff); |
c93bb85b JG |
3077 | |
3078 | if (rdev->disp_priority == 2) { | |
3079 | critical_point2 = 0; | |
3080 | } | |
3081 | ||
3082 | if (max_stop_req - critical_point2 < 4) | |
3083 | critical_point2 = 0; | |
3084 | ||
3085 | } | |
3086 | ||
3087 | if (critical_point2 == 0 && rdev->family == CHIP_R300) { | |
3088 | /* some R300 cards have problem with this set to 0 */ | |
3089 | critical_point2 = 0x10; | |
3090 | } | |
3091 | ||
3092 | WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | | |
3093 | (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); | |
3094 | ||
3095 | if ((rdev->family == CHIP_RS400) || | |
3096 | (rdev->family == CHIP_RS480)) { | |
3097 | #if 0 | |
3098 | /* attempt to program RS400 disp2 regs correctly ??? */ | |
3099 | temp = RREG32(RS400_DISP2_REQ_CNTL1); | |
3100 | temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | | |
3101 | RS400_DISP2_STOP_REQ_LEVEL_MASK); | |
3102 | WREG32(RS400_DISP2_REQ_CNTL1, (temp | | |
3103 | (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | | |
3104 | (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); | |
3105 | temp = RREG32(RS400_DISP2_REQ_CNTL2); | |
3106 | temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | | |
3107 | RS400_DISP2_CRITICAL_POINT_STOP_MASK); | |
3108 | WREG32(RS400_DISP2_REQ_CNTL2, (temp | | |
3109 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | | |
3110 | (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); | |
3111 | #endif | |
3112 | WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); | |
3113 | WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); | |
3114 | WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); | |
3115 | WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); | |
3116 | } | |
3117 | ||
3118 | DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n", | |
3119 | (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); | |
3120 | } | |
3121 | } | |
551ebd83 DA |
3122 | |
3123 | static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) | |
3124 | { | |
3125 | DRM_ERROR("pitch %d\n", t->pitch); | |
ceb776bc | 3126 | DRM_ERROR("use_pitch %d\n", t->use_pitch); |
551ebd83 | 3127 | DRM_ERROR("width %d\n", t->width); |
ceb776bc | 3128 | DRM_ERROR("width_11 %d\n", t->width_11); |
551ebd83 | 3129 | DRM_ERROR("height %d\n", t->height); |
ceb776bc | 3130 | DRM_ERROR("height_11 %d\n", t->height_11); |
551ebd83 DA |
3131 | DRM_ERROR("num levels %d\n", t->num_levels); |
3132 | DRM_ERROR("depth %d\n", t->txdepth); | |
3133 | DRM_ERROR("bpp %d\n", t->cpp); | |
3134 | DRM_ERROR("coordinate type %d\n", t->tex_coord_type); | |
3135 | DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); | |
3136 | DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); | |
d785d78b | 3137 | DRM_ERROR("compress format %d\n", t->compress_format); |
551ebd83 DA |
3138 | } |
3139 | ||
3140 | static int r100_cs_track_cube(struct radeon_device *rdev, | |
3141 | struct r100_cs_track *track, unsigned idx) | |
3142 | { | |
3143 | unsigned face, w, h; | |
4c788679 | 3144 | struct radeon_bo *cube_robj; |
551ebd83 DA |
3145 | unsigned long size; |
3146 | ||
3147 | for (face = 0; face < 5; face++) { | |
3148 | cube_robj = track->textures[idx].cube_info[face].robj; | |
3149 | w = track->textures[idx].cube_info[face].width; | |
3150 | h = track->textures[idx].cube_info[face].height; | |
3151 | ||
3152 | size = w * h; | |
3153 | size *= track->textures[idx].cpp; | |
3154 | ||
3155 | size += track->textures[idx].cube_info[face].offset; | |
3156 | ||
4c788679 | 3157 | if (size > radeon_bo_size(cube_robj)) { |
551ebd83 | 3158 | DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", |
4c788679 | 3159 | size, radeon_bo_size(cube_robj)); |
551ebd83 DA |
3160 | r100_cs_track_texture_print(&track->textures[idx]); |
3161 | return -1; | |
3162 | } | |
3163 | } | |
3164 | return 0; | |
3165 | } | |
3166 | ||
d785d78b DA |
3167 | static int r100_track_compress_size(int compress_format, int w, int h) |
3168 | { | |
3169 | int block_width, block_height, block_bytes; | |
3170 | int wblocks, hblocks; | |
3171 | int min_wblocks; | |
3172 | int sz; | |
3173 | ||
3174 | block_width = 4; | |
3175 | block_height = 4; | |
3176 | ||
3177 | switch (compress_format) { | |
3178 | case R100_TRACK_COMP_DXT1: | |
3179 | block_bytes = 8; | |
3180 | min_wblocks = 4; | |
3181 | break; | |
3182 | default: | |
3183 | case R100_TRACK_COMP_DXT35: | |
3184 | block_bytes = 16; | |
3185 | min_wblocks = 2; | |
3186 | break; | |
3187 | } | |
3188 | ||
3189 | hblocks = (h + block_height - 1) / block_height; | |
3190 | wblocks = (w + block_width - 1) / block_width; | |
3191 | if (wblocks < min_wblocks) | |
3192 | wblocks = min_wblocks; | |
3193 | sz = wblocks * hblocks * block_bytes; | |
3194 | return sz; | |
3195 | } | |
3196 | ||
551ebd83 DA |
3197 | static int r100_cs_track_texture_check(struct radeon_device *rdev, |
3198 | struct r100_cs_track *track) | |
3199 | { | |
4c788679 | 3200 | struct radeon_bo *robj; |
551ebd83 | 3201 | unsigned long size; |
b73c5f8b | 3202 | unsigned u, i, w, h, d; |
551ebd83 DA |
3203 | int ret; |
3204 | ||
3205 | for (u = 0; u < track->num_texture; u++) { | |
3206 | if (!track->textures[u].enabled) | |
3207 | continue; | |
3208 | robj = track->textures[u].robj; | |
3209 | if (robj == NULL) { | |
3210 | DRM_ERROR("No texture bound to unit %u\n", u); | |
3211 | return -EINVAL; | |
3212 | } | |
3213 | size = 0; | |
3214 | for (i = 0; i <= track->textures[u].num_levels; i++) { | |
3215 | if (track->textures[u].use_pitch) { | |
3216 | if (rdev->family < CHIP_R300) | |
3217 | w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); | |
3218 | else | |
3219 | w = track->textures[u].pitch / (1 << i); | |
3220 | } else { | |
ceb776bc | 3221 | w = track->textures[u].width; |
551ebd83 DA |
3222 | if (rdev->family >= CHIP_RV515) |
3223 | w |= track->textures[u].width_11; | |
ceb776bc | 3224 | w = w / (1 << i); |
551ebd83 DA |
3225 | if (track->textures[u].roundup_w) |
3226 | w = roundup_pow_of_two(w); | |
3227 | } | |
ceb776bc | 3228 | h = track->textures[u].height; |
551ebd83 DA |
3229 | if (rdev->family >= CHIP_RV515) |
3230 | h |= track->textures[u].height_11; | |
ceb776bc | 3231 | h = h / (1 << i); |
551ebd83 DA |
3232 | if (track->textures[u].roundup_h) |
3233 | h = roundup_pow_of_two(h); | |
b73c5f8b MO |
3234 | if (track->textures[u].tex_coord_type == 1) { |
3235 | d = (1 << track->textures[u].txdepth) / (1 << i); | |
3236 | if (!d) | |
3237 | d = 1; | |
3238 | } else { | |
3239 | d = 1; | |
3240 | } | |
d785d78b DA |
3241 | if (track->textures[u].compress_format) { |
3242 | ||
b73c5f8b | 3243 | size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; |
d785d78b DA |
3244 | /* compressed textures are block based */ |
3245 | } else | |
b73c5f8b | 3246 | size += w * h * d; |
551ebd83 DA |
3247 | } |
3248 | size *= track->textures[u].cpp; | |
d785d78b | 3249 | |
551ebd83 DA |
3250 | switch (track->textures[u].tex_coord_type) { |
3251 | case 0: | |
551ebd83 | 3252 | case 1: |
551ebd83 DA |
3253 | break; |
3254 | case 2: | |
3255 | if (track->separate_cube) { | |
3256 | ret = r100_cs_track_cube(rdev, track, u); | |
3257 | if (ret) | |
3258 | return ret; | |
3259 | } else | |
3260 | size *= 6; | |
3261 | break; | |
3262 | default: | |
3263 | DRM_ERROR("Invalid texture coordinate type %u for unit " | |
3264 | "%u\n", track->textures[u].tex_coord_type, u); | |
3265 | return -EINVAL; | |
3266 | } | |
4c788679 | 3267 | if (size > radeon_bo_size(robj)) { |
551ebd83 | 3268 | DRM_ERROR("Texture of unit %u needs %lu bytes but is " |
4c788679 | 3269 | "%lu\n", u, size, radeon_bo_size(robj)); |
551ebd83 DA |
3270 | r100_cs_track_texture_print(&track->textures[u]); |
3271 | return -EINVAL; | |
3272 | } | |
3273 | } | |
3274 | return 0; | |
3275 | } | |
3276 | ||
3277 | int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) | |
3278 | { | |
3279 | unsigned i; | |
3280 | unsigned long size; | |
3281 | unsigned prim_walk; | |
3282 | unsigned nverts; | |
3283 | ||
3284 | for (i = 0; i < track->num_cb; i++) { | |
3285 | if (track->cb[i].robj == NULL) { | |
797fd5b9 | 3286 | if (!(track->zb_cb_clear || track->color_channel_mask || |
46c64d4b MO |
3287 | track->blend_read_enable)) { |
3288 | continue; | |
3289 | } | |
551ebd83 DA |
3290 | DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); |
3291 | return -EINVAL; | |
3292 | } | |
3293 | size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; | |
3294 | size += track->cb[i].offset; | |
4c788679 | 3295 | if (size > radeon_bo_size(track->cb[i].robj)) { |
551ebd83 DA |
3296 | DRM_ERROR("[drm] Buffer too small for color buffer %d " |
3297 | "(need %lu have %lu) !\n", i, size, | |
4c788679 | 3298 | radeon_bo_size(track->cb[i].robj)); |
551ebd83 DA |
3299 | DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", |
3300 | i, track->cb[i].pitch, track->cb[i].cpp, | |
3301 | track->cb[i].offset, track->maxy); | |
3302 | return -EINVAL; | |
3303 | } | |
3304 | } | |
3305 | if (track->z_enabled) { | |
3306 | if (track->zb.robj == NULL) { | |
3307 | DRM_ERROR("[drm] No buffer for z buffer !\n"); | |
3308 | return -EINVAL; | |
3309 | } | |
3310 | size = track->zb.pitch * track->zb.cpp * track->maxy; | |
3311 | size += track->zb.offset; | |
4c788679 | 3312 | if (size > radeon_bo_size(track->zb.robj)) { |
551ebd83 DA |
3313 | DRM_ERROR("[drm] Buffer too small for z buffer " |
3314 | "(need %lu have %lu) !\n", size, | |
4c788679 | 3315 | radeon_bo_size(track->zb.robj)); |
551ebd83 DA |
3316 | DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", |
3317 | track->zb.pitch, track->zb.cpp, | |
3318 | track->zb.offset, track->maxy); | |
3319 | return -EINVAL; | |
3320 | } | |
3321 | } | |
3322 | prim_walk = (track->vap_vf_cntl >> 4) & 0x3; | |
cae94b0a MO |
3323 | if (track->vap_vf_cntl & (1 << 14)) { |
3324 | nverts = track->vap_alt_nverts; | |
3325 | } else { | |
3326 | nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; | |
3327 | } | |
551ebd83 DA |
3328 | switch (prim_walk) { |
3329 | case 1: | |
3330 | for (i = 0; i < track->num_arrays; i++) { | |
3331 | size = track->arrays[i].esize * track->max_indx * 4; | |
3332 | if (track->arrays[i].robj == NULL) { | |
3333 | DRM_ERROR("(PW %u) Vertex array %u no buffer " | |
3334 | "bound\n", prim_walk, i); | |
3335 | return -EINVAL; | |
3336 | } | |
4c788679 JG |
3337 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
3338 | dev_err(rdev->dev, "(PW %u) Vertex array %u " | |
3339 | "need %lu dwords have %lu dwords\n", | |
3340 | prim_walk, i, size >> 2, | |
3341 | radeon_bo_size(track->arrays[i].robj) | |
3342 | >> 2); | |
551ebd83 DA |
3343 | DRM_ERROR("Max indices %u\n", track->max_indx); |
3344 | return -EINVAL; | |
3345 | } | |
3346 | } | |
3347 | break; | |
3348 | case 2: | |
3349 | for (i = 0; i < track->num_arrays; i++) { | |
3350 | size = track->arrays[i].esize * (nverts - 1) * 4; | |
3351 | if (track->arrays[i].robj == NULL) { | |
3352 | DRM_ERROR("(PW %u) Vertex array %u no buffer " | |
3353 | "bound\n", prim_walk, i); | |
3354 | return -EINVAL; | |
3355 | } | |
4c788679 JG |
3356 | if (size > radeon_bo_size(track->arrays[i].robj)) { |
3357 | dev_err(rdev->dev, "(PW %u) Vertex array %u " | |
3358 | "need %lu dwords have %lu dwords\n", | |
3359 | prim_walk, i, size >> 2, | |
3360 | radeon_bo_size(track->arrays[i].robj) | |
3361 | >> 2); | |
551ebd83 DA |
3362 | return -EINVAL; |
3363 | } | |
3364 | } | |
3365 | break; | |
3366 | case 3: | |
3367 | size = track->vtx_size * nverts; | |
3368 | if (size != track->immd_dwords) { | |
3369 | DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", | |
3370 | track->immd_dwords, size); | |
3371 | DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", | |
3372 | nverts, track->vtx_size); | |
3373 | return -EINVAL; | |
3374 | } | |
3375 | break; | |
3376 | default: | |
3377 | DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", | |
3378 | prim_walk); | |
3379 | return -EINVAL; | |
3380 | } | |
3381 | return r100_cs_track_texture_check(rdev, track); | |
3382 | } | |
3383 | ||
3384 | void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) | |
3385 | { | |
3386 | unsigned i, face; | |
3387 | ||
3388 | if (rdev->family < CHIP_R300) { | |
3389 | track->num_cb = 1; | |
3390 | if (rdev->family <= CHIP_RS200) | |
3391 | track->num_texture = 3; | |
3392 | else | |
3393 | track->num_texture = 6; | |
3394 | track->maxy = 2048; | |
3395 | track->separate_cube = 1; | |
3396 | } else { | |
3397 | track->num_cb = 4; | |
3398 | track->num_texture = 16; | |
3399 | track->maxy = 4096; | |
3400 | track->separate_cube = 0; | |
3401 | } | |
3402 | ||
3403 | for (i = 0; i < track->num_cb; i++) { | |
3404 | track->cb[i].robj = NULL; | |
3405 | track->cb[i].pitch = 8192; | |
3406 | track->cb[i].cpp = 16; | |
3407 | track->cb[i].offset = 0; | |
3408 | } | |
3409 | track->z_enabled = true; | |
3410 | track->zb.robj = NULL; | |
3411 | track->zb.pitch = 8192; | |
3412 | track->zb.cpp = 4; | |
3413 | track->zb.offset = 0; | |
3414 | track->vtx_size = 0x7F; | |
3415 | track->immd_dwords = 0xFFFFFFFFUL; | |
3416 | track->num_arrays = 11; | |
3417 | track->max_indx = 0x00FFFFFFUL; | |
3418 | for (i = 0; i < track->num_arrays; i++) { | |
3419 | track->arrays[i].robj = NULL; | |
3420 | track->arrays[i].esize = 0x7F; | |
3421 | } | |
3422 | for (i = 0; i < track->num_texture; i++) { | |
d785d78b | 3423 | track->textures[i].compress_format = R100_TRACK_COMP_NONE; |
551ebd83 DA |
3424 | track->textures[i].pitch = 16536; |
3425 | track->textures[i].width = 16536; | |
3426 | track->textures[i].height = 16536; | |
3427 | track->textures[i].width_11 = 1 << 11; | |
3428 | track->textures[i].height_11 = 1 << 11; | |
3429 | track->textures[i].num_levels = 12; | |
3430 | if (rdev->family <= CHIP_RS200) { | |
3431 | track->textures[i].tex_coord_type = 0; | |
3432 | track->textures[i].txdepth = 0; | |
3433 | } else { | |
3434 | track->textures[i].txdepth = 16; | |
3435 | track->textures[i].tex_coord_type = 1; | |
3436 | } | |
3437 | track->textures[i].cpp = 64; | |
3438 | track->textures[i].robj = NULL; | |
3439 | /* CS IB emission code makes sure texture unit are disabled */ | |
3440 | track->textures[i].enabled = false; | |
3441 | track->textures[i].roundup_w = true; | |
3442 | track->textures[i].roundup_h = true; | |
3443 | if (track->separate_cube) | |
3444 | for (face = 0; face < 5; face++) { | |
3445 | track->textures[i].cube_info[face].robj = NULL; | |
3446 | track->textures[i].cube_info[face].width = 16536; | |
3447 | track->textures[i].cube_info[face].height = 16536; | |
3448 | track->textures[i].cube_info[face].offset = 0; | |
3449 | } | |
3450 | } | |
3451 | } | |
3ce0a23d JG |
3452 | |
3453 | int r100_ring_test(struct radeon_device *rdev) | |
3454 | { | |
3455 | uint32_t scratch; | |
3456 | uint32_t tmp = 0; | |
3457 | unsigned i; | |
3458 | int r; | |
3459 | ||
3460 | r = radeon_scratch_get(rdev, &scratch); | |
3461 | if (r) { | |
3462 | DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); | |
3463 | return r; | |
3464 | } | |
3465 | WREG32(scratch, 0xCAFEDEAD); | |
3466 | r = radeon_ring_lock(rdev, 2); | |
3467 | if (r) { | |
3468 | DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); | |
3469 | radeon_scratch_free(rdev, scratch); | |
3470 | return r; | |
3471 | } | |
3472 | radeon_ring_write(rdev, PACKET0(scratch, 0)); | |
3473 | radeon_ring_write(rdev, 0xDEADBEEF); | |
3474 | radeon_ring_unlock_commit(rdev); | |
3475 | for (i = 0; i < rdev->usec_timeout; i++) { | |
3476 | tmp = RREG32(scratch); | |
3477 | if (tmp == 0xDEADBEEF) { | |
3478 | break; | |
3479 | } | |
3480 | DRM_UDELAY(1); | |
3481 | } | |
3482 | if (i < rdev->usec_timeout) { | |
3483 | DRM_INFO("ring test succeeded in %d usecs\n", i); | |
3484 | } else { | |
3485 | DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", | |
3486 | scratch, tmp); | |
3487 | r = -EINVAL; | |
3488 | } | |
3489 | radeon_scratch_free(rdev, scratch); | |
3490 | return r; | |
3491 | } | |
3492 | ||
3493 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |
3494 | { | |
3495 | radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); | |
3496 | radeon_ring_write(rdev, ib->gpu_addr); | |
3497 | radeon_ring_write(rdev, ib->length_dw); | |
3498 | } | |
3499 | ||
3500 | int r100_ib_test(struct radeon_device *rdev) | |
3501 | { | |
3502 | struct radeon_ib *ib; | |
3503 | uint32_t scratch; | |
3504 | uint32_t tmp = 0; | |
3505 | unsigned i; | |
3506 | int r; | |
3507 | ||
3508 | r = radeon_scratch_get(rdev, &scratch); | |
3509 | if (r) { | |
3510 | DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); | |
3511 | return r; | |
3512 | } | |
3513 | WREG32(scratch, 0xCAFEDEAD); | |
3514 | r = radeon_ib_get(rdev, &ib); | |
3515 | if (r) { | |
3516 | return r; | |
3517 | } | |
3518 | ib->ptr[0] = PACKET0(scratch, 0); | |
3519 | ib->ptr[1] = 0xDEADBEEF; | |
3520 | ib->ptr[2] = PACKET2(0); | |
3521 | ib->ptr[3] = PACKET2(0); | |
3522 | ib->ptr[4] = PACKET2(0); | |
3523 | ib->ptr[5] = PACKET2(0); | |
3524 | ib->ptr[6] = PACKET2(0); | |
3525 | ib->ptr[7] = PACKET2(0); | |
3526 | ib->length_dw = 8; | |
3527 | r = radeon_ib_schedule(rdev, ib); | |
3528 | if (r) { | |
3529 | radeon_scratch_free(rdev, scratch); | |
3530 | radeon_ib_free(rdev, &ib); | |
3531 | return r; | |
3532 | } | |
3533 | r = radeon_fence_wait(ib->fence, false); | |
3534 | if (r) { | |
3535 | return r; | |
3536 | } | |
3537 | for (i = 0; i < rdev->usec_timeout; i++) { | |
3538 | tmp = RREG32(scratch); | |
3539 | if (tmp == 0xDEADBEEF) { | |
3540 | break; | |
3541 | } | |
3542 | DRM_UDELAY(1); | |
3543 | } | |
3544 | if (i < rdev->usec_timeout) { | |
3545 | DRM_INFO("ib test succeeded in %u usecs\n", i); | |
3546 | } else { | |
3547 | DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", | |
3548 | scratch, tmp); | |
3549 | r = -EINVAL; | |
3550 | } | |
3551 | radeon_scratch_free(rdev, scratch); | |
3552 | radeon_ib_free(rdev, &ib); | |
3553 | return r; | |
3554 | } | |
9f022ddf JG |
3555 | |
3556 | void r100_ib_fini(struct radeon_device *rdev) | |
3557 | { | |
3558 | radeon_ib_pool_fini(rdev); | |
3559 | } | |
3560 | ||
3561 | int r100_ib_init(struct radeon_device *rdev) | |
3562 | { | |
3563 | int r; | |
3564 | ||
3565 | r = radeon_ib_pool_init(rdev); | |
3566 | if (r) { | |
3567 | dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r); | |
3568 | r100_ib_fini(rdev); | |
3569 | return r; | |
3570 | } | |
3571 | r = r100_ib_test(rdev); | |
3572 | if (r) { | |
3573 | dev_err(rdev->dev, "failled testing IB (%d).\n", r); | |
3574 | r100_ib_fini(rdev); | |
3575 | return r; | |
3576 | } | |
3577 | return 0; | |
3578 | } | |
3579 | ||
3580 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) | |
3581 | { | |
3582 | /* Shutdown CP we shouldn't need to do that but better be safe than | |
3583 | * sorry | |
3584 | */ | |
3585 | rdev->cp.ready = false; | |
3586 | WREG32(R_000740_CP_CSQ_CNTL, 0); | |
3587 | ||
3588 | /* Save few CRTC registers */ | |
ca6ffc64 | 3589 | save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); |
9f022ddf JG |
3590 | save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); |
3591 | save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); | |
3592 | save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); | |
3593 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3594 | save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); | |
3595 | save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); | |
3596 | } | |
3597 | ||
3598 | /* Disable VGA aperture access */ | |
ca6ffc64 | 3599 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); |
9f022ddf JG |
3600 | /* Disable cursor, overlay, crtc */ |
3601 | WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); | |
3602 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | | |
3603 | S_000054_CRTC_DISPLAY_DIS(1)); | |
3604 | WREG32(R_000050_CRTC_GEN_CNTL, | |
3605 | (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | | |
3606 | S_000050_CRTC_DISP_REQ_EN_B(1)); | |
3607 | WREG32(R_000420_OV0_SCALE_CNTL, | |
3608 | C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); | |
3609 | WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); | |
3610 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3611 | WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | | |
3612 | S_000360_CUR2_LOCK(1)); | |
3613 | WREG32(R_0003F8_CRTC2_GEN_CNTL, | |
3614 | (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | | |
3615 | S_0003F8_CRTC2_DISPLAY_DIS(1) | | |
3616 | S_0003F8_CRTC2_DISP_REQ_EN_B(1)); | |
3617 | WREG32(R_000360_CUR2_OFFSET, | |
3618 | C_000360_CUR2_LOCK & save->CUR2_OFFSET); | |
3619 | } | |
3620 | } | |
3621 | ||
3622 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) | |
3623 | { | |
3624 | /* Update base address for crtc */ | |
d594e46a | 3625 | WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
9f022ddf | 3626 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
d594e46a | 3627 | WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); |
9f022ddf JG |
3628 | } |
3629 | /* Restore CRTC registers */ | |
ca6ffc64 | 3630 | WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); |
9f022ddf JG |
3631 | WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); |
3632 | WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); | |
3633 | if (!(rdev->flags & RADEON_SINGLE_CRTC)) { | |
3634 | WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); | |
3635 | } | |
3636 | } | |
ca6ffc64 JG |
3637 | |
3638 | void r100_vga_render_disable(struct radeon_device *rdev) | |
3639 | { | |
d4550907 | 3640 | u32 tmp; |
ca6ffc64 | 3641 | |
d4550907 | 3642 | tmp = RREG8(R_0003C2_GENMO_WT); |
ca6ffc64 JG |
3643 | WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); |
3644 | } | |
d4550907 JG |
3645 | |
3646 | static void r100_debugfs(struct radeon_device *rdev) | |
3647 | { | |
3648 | int r; | |
3649 | ||
3650 | r = r100_debugfs_mc_info_init(rdev); | |
3651 | if (r) | |
3652 | dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); | |
3653 | } | |
3654 | ||
3655 | static void r100_mc_program(struct radeon_device *rdev) | |
3656 | { | |
3657 | struct r100_mc_save save; | |
3658 | ||
3659 | /* Stops all mc clients */ | |
3660 | r100_mc_stop(rdev, &save); | |
3661 | if (rdev->flags & RADEON_IS_AGP) { | |
3662 | WREG32(R_00014C_MC_AGP_LOCATION, | |
3663 | S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | | |
3664 | S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); | |
3665 | WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); | |
3666 | if (rdev->family > CHIP_RV200) | |
3667 | WREG32(R_00015C_AGP_BASE_2, | |
3668 | upper_32_bits(rdev->mc.agp_base) & 0xff); | |
3669 | } else { | |
3670 | WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); | |
3671 | WREG32(R_000170_AGP_BASE, 0); | |
3672 | if (rdev->family > CHIP_RV200) | |
3673 | WREG32(R_00015C_AGP_BASE_2, 0); | |
3674 | } | |
3675 | /* Wait for mc idle */ | |
3676 | if (r100_mc_wait_for_idle(rdev)) | |
3677 | dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); | |
3678 | /* Program MC, should be a 32bits limited address space */ | |
3679 | WREG32(R_000148_MC_FB_LOCATION, | |
3680 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | | |
3681 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); | |
3682 | r100_mc_resume(rdev, &save); | |
3683 | } | |
3684 | ||
3685 | void r100_clock_startup(struct radeon_device *rdev) | |
3686 | { | |
3687 | u32 tmp; | |
3688 | ||
3689 | if (radeon_dynclks != -1 && radeon_dynclks) | |
3690 | radeon_legacy_set_clock_gating(rdev, 1); | |
3691 | /* We need to force on some of the block */ | |
3692 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); | |
3693 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); | |
3694 | if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) | |
3695 | tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); | |
3696 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); | |
3697 | } | |
3698 | ||
3699 | static int r100_startup(struct radeon_device *rdev) | |
3700 | { | |
3701 | int r; | |
3702 | ||
92cde00c AD |
3703 | /* set common regs */ |
3704 | r100_set_common_regs(rdev); | |
3705 | /* program mc */ | |
d4550907 JG |
3706 | r100_mc_program(rdev); |
3707 | /* Resume clock */ | |
3708 | r100_clock_startup(rdev); | |
3709 | /* Initialize GPU configuration (# pipes, ...) */ | |
90aca4d2 | 3710 | // r100_gpu_init(rdev); |
d4550907 JG |
3711 | /* Initialize GART (initialize after TTM so we can allocate |
3712 | * memory through TTM but finalize after TTM) */ | |
17e15b0c | 3713 | r100_enable_bm(rdev); |
d4550907 JG |
3714 | if (rdev->flags & RADEON_IS_PCI) { |
3715 | r = r100_pci_gart_enable(rdev); | |
3716 | if (r) | |
3717 | return r; | |
3718 | } | |
3719 | /* Enable IRQ */ | |
d4550907 | 3720 | r100_irq_set(rdev); |
cafe6609 | 3721 | rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
d4550907 JG |
3722 | /* 1M ring buffer */ |
3723 | r = r100_cp_init(rdev, 1024 * 1024); | |
3724 | if (r) { | |
3725 | dev_err(rdev->dev, "failled initializing CP (%d).\n", r); | |
3726 | return r; | |
3727 | } | |
3728 | r = r100_wb_init(rdev); | |
3729 | if (r) | |
3730 | dev_err(rdev->dev, "failled initializing WB (%d).\n", r); | |
3731 | r = r100_ib_init(rdev); | |
3732 | if (r) { | |
3733 | dev_err(rdev->dev, "failled initializing IB (%d).\n", r); | |
3734 | return r; | |
3735 | } | |
3736 | return 0; | |
3737 | } | |
3738 | ||
3739 | int r100_resume(struct radeon_device *rdev) | |
3740 | { | |
3741 | /* Make sur GART are not working */ | |
3742 | if (rdev->flags & RADEON_IS_PCI) | |
3743 | r100_pci_gart_disable(rdev); | |
3744 | /* Resume clock before doing reset */ | |
3745 | r100_clock_startup(rdev); | |
3746 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 3747 | if (radeon_asic_reset(rdev)) { |
d4550907 JG |
3748 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
3749 | RREG32(R_000E40_RBBM_STATUS), | |
3750 | RREG32(R_0007C0_CP_STAT)); | |
3751 | } | |
3752 | /* post */ | |
3753 | radeon_combios_asic_init(rdev->ddev); | |
3754 | /* Resume clock after posting */ | |
3755 | r100_clock_startup(rdev); | |
550e2d92 DA |
3756 | /* Initialize surface registers */ |
3757 | radeon_surface_init(rdev); | |
d4550907 JG |
3758 | return r100_startup(rdev); |
3759 | } | |
3760 | ||
3761 | int r100_suspend(struct radeon_device *rdev) | |
3762 | { | |
3763 | r100_cp_disable(rdev); | |
3764 | r100_wb_disable(rdev); | |
3765 | r100_irq_disable(rdev); | |
3766 | if (rdev->flags & RADEON_IS_PCI) | |
3767 | r100_pci_gart_disable(rdev); | |
3768 | return 0; | |
3769 | } | |
3770 | ||
3771 | void r100_fini(struct radeon_device *rdev) | |
3772 | { | |
d4550907 JG |
3773 | r100_cp_fini(rdev); |
3774 | r100_wb_fini(rdev); | |
3775 | r100_ib_fini(rdev); | |
3776 | radeon_gem_fini(rdev); | |
3777 | if (rdev->flags & RADEON_IS_PCI) | |
3778 | r100_pci_gart_fini(rdev); | |
d0269ed8 | 3779 | radeon_agp_fini(rdev); |
d4550907 JG |
3780 | radeon_irq_kms_fini(rdev); |
3781 | radeon_fence_driver_fini(rdev); | |
4c788679 | 3782 | radeon_bo_fini(rdev); |
d4550907 JG |
3783 | radeon_atombios_fini(rdev); |
3784 | kfree(rdev->bios); | |
3785 | rdev->bios = NULL; | |
3786 | } | |
3787 | ||
d4550907 JG |
3788 | int r100_init(struct radeon_device *rdev) |
3789 | { | |
3790 | int r; | |
3791 | ||
d4550907 JG |
3792 | /* Register debugfs file specific to this group of asics */ |
3793 | r100_debugfs(rdev); | |
3794 | /* Disable VGA */ | |
3795 | r100_vga_render_disable(rdev); | |
3796 | /* Initialize scratch registers */ | |
3797 | radeon_scratch_init(rdev); | |
3798 | /* Initialize surface registers */ | |
3799 | radeon_surface_init(rdev); | |
3800 | /* TODO: disable VGA need to use VGA request */ | |
3801 | /* BIOS*/ | |
3802 | if (!radeon_get_bios(rdev)) { | |
3803 | if (ASIC_IS_AVIVO(rdev)) | |
3804 | return -EINVAL; | |
3805 | } | |
3806 | if (rdev->is_atom_bios) { | |
3807 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); | |
3808 | return -EINVAL; | |
3809 | } else { | |
3810 | r = radeon_combios_init(rdev); | |
3811 | if (r) | |
3812 | return r; | |
3813 | } | |
3814 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ | |
a2d07b74 | 3815 | if (radeon_asic_reset(rdev)) { |
d4550907 JG |
3816 | dev_warn(rdev->dev, |
3817 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", | |
3818 | RREG32(R_000E40_RBBM_STATUS), | |
3819 | RREG32(R_0007C0_CP_STAT)); | |
3820 | } | |
3821 | /* check if cards are posted or not */ | |
72542d77 DA |
3822 | if (radeon_boot_test_post_card(rdev) == false) |
3823 | return -EINVAL; | |
d4550907 JG |
3824 | /* Set asic errata */ |
3825 | r100_errata(rdev); | |
3826 | /* Initialize clocks */ | |
3827 | radeon_get_clock_info(rdev->ddev); | |
d594e46a JG |
3828 | /* initialize AGP */ |
3829 | if (rdev->flags & RADEON_IS_AGP) { | |
3830 | r = radeon_agp_init(rdev); | |
3831 | if (r) { | |
3832 | radeon_agp_disable(rdev); | |
3833 | } | |
3834 | } | |
3835 | /* initialize VRAM */ | |
3836 | r100_mc_init(rdev); | |
d4550907 JG |
3837 | /* Fence driver */ |
3838 | r = radeon_fence_driver_init(rdev); | |
3839 | if (r) | |
3840 | return r; | |
3841 | r = radeon_irq_kms_init(rdev); | |
3842 | if (r) | |
3843 | return r; | |
3844 | /* Memory manager */ | |
4c788679 | 3845 | r = radeon_bo_init(rdev); |
d4550907 JG |
3846 | if (r) |
3847 | return r; | |
3848 | if (rdev->flags & RADEON_IS_PCI) { | |
3849 | r = r100_pci_gart_init(rdev); | |
3850 | if (r) | |
3851 | return r; | |
3852 | } | |
3853 | r100_set_safe_registers(rdev); | |
3854 | rdev->accel_working = true; | |
3855 | r = r100_startup(rdev); | |
3856 | if (r) { | |
3857 | /* Somethings want wront with the accel init stop accel */ | |
3858 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); | |
d4550907 JG |
3859 | r100_cp_fini(rdev); |
3860 | r100_wb_fini(rdev); | |
3861 | r100_ib_fini(rdev); | |
655efd3d | 3862 | radeon_irq_kms_fini(rdev); |
d4550907 JG |
3863 | if (rdev->flags & RADEON_IS_PCI) |
3864 | r100_pci_gart_fini(rdev); | |
d4550907 JG |
3865 | rdev->accel_working = false; |
3866 | } | |
3867 | return 0; | |
3868 | } |