projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon: Mark all possible functions / structs as static
[linux-2.6-block.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9
JG		 30#include "drmP.h"
31#include "drm.h"
32#include "radeon_drm.h"
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "r100d.h"
d4550907
JG		 37#include "rs100d.h"
38#include "rv200d.h"
39#include "rv250d.h"
49e02b73 40#include "atom.h"
3ce0a23d 41
70967ab9
BH		 42#include <linux/firmware.h>
43#include <linux/platform_device.h>
e0cd3608 44#include <linux/module.h>
70967ab9 45
551ebd83
DA		 46#include "r100_reg_safe.h"
47#include "rn50_reg_safe.h"
48
70967ab9
BH		 49/* Firmware Names */
50#define FIRMWARE_R100 "radeon/R100_cp.bin"
51#define FIRMWARE_R200 "radeon/R200_cp.bin"
52#define FIRMWARE_R300 "radeon/R300_cp.bin"
53#define FIRMWARE_R420 "radeon/R420_cp.bin"
54#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
55#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
56#define FIRMWARE_R520 "radeon/R520_cp.bin"
57
58MODULE_FIRMWARE(FIRMWARE_R100);
59MODULE_FIRMWARE(FIRMWARE_R200);
60MODULE_FIRMWARE(FIRMWARE_R300);
61MODULE_FIRMWARE(FIRMWARE_R420);
62MODULE_FIRMWARE(FIRMWARE_RS690);
63MODULE_FIRMWARE(FIRMWARE_RS600);
64MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 65
551ebd83
DA		 66#include "r100_track.h"
67
48ef779f
AD		 68/* This files gather functions specifics to:
69 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
70 * and others in some cases.
71 */
72
73/**
74 * r100_wait_for_vblank - vblank wait asic callback.
75 *
76 * @rdev: radeon_device pointer
77 * @crtc: crtc to wait for vblank on
78 *
79 * Wait for vblank on the requested crtc (r1xx-r4xx).
80 */
3ae19b75
AD		 81void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
82{
3ae19b75
AD		 83 int i;
84
94f768fd
AD		 85 if (crtc >= rdev->num_crtc)
86 return;
87
88 if (crtc == 0) {
3ae19b75
AD		 89 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
90 for (i = 0; i < rdev->usec_timeout; i++) {
91 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
92 break;
93 udelay(1);
94 }
95 for (i = 0; i < rdev->usec_timeout; i++) {
96 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
97 break;
98 udelay(1);
99 }
100 }
101 } else {
102 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
103 for (i = 0; i < rdev->usec_timeout; i++) {
104 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
105 break;
106 udelay(1);
107 }
108 for (i = 0; i < rdev->usec_timeout; i++) {
109 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
110 break;
111 udelay(1);
112 }
113 }
114 }
115}
116
48ef779f
AD		 117/**
118 * r100_pre_page_flip - pre-pageflip callback.
119 *
120 * @rdev: radeon_device pointer
121 * @crtc: crtc to prepare for pageflip on
122 *
123 * Pre-pageflip callback (r1xx-r4xx).
124 * Enables the pageflip irq (vblank irq).
771fe6b9 125 */
6f34be50
AD		 126void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
127{
6f34be50
AD		 128 /* enable the pflip int */
129 radeon_irq_kms_pflip_irq_get(rdev, crtc);
130}
131
48ef779f
AD		 132/**
133 * r100_post_page_flip - pos-pageflip callback.
134 *
135 * @rdev: radeon_device pointer
136 * @crtc: crtc to cleanup pageflip on
137 *
138 * Post-pageflip callback (r1xx-r4xx).
139 * Disables the pageflip irq (vblank irq).
140 */
6f34be50
AD		 141void r100_post_page_flip(struct radeon_device *rdev, int crtc)
142{
143 /* disable the pflip int */
144 radeon_irq_kms_pflip_irq_put(rdev, crtc);
145}
146
48ef779f
AD		 147/**
148 * r100_page_flip - pageflip callback.
149 *
150 * @rdev: radeon_device pointer
151 * @crtc_id: crtc to cleanup pageflip on
152 * @crtc_base: new address of the crtc (GPU MC address)
153 *
154 * Does the actual pageflip (r1xx-r4xx).
155 * During vblank we take the crtc lock and wait for the update_pending
156 * bit to go high, when it does, we release the lock, and allow the
157 * double buffered update to take place.
158 * Returns the current update pending status.
159 */
6f34be50
AD		 160u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
161{
162 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
163 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
f6496479 164 int i;
6f34be50
AD		 165
166 /* Lock the graphics update lock */
167 /* update the scanout addresses */
168 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
169
acb32506 170 /* Wait for update_pending to go high. */
f6496479
AD		 171 for (i = 0; i < rdev->usec_timeout; i++) {
172 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
173 break;
174 udelay(1);
175 }
acb32506 176 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
6f34be50
AD		 177
178 /* Unlock the lock, so double-buffering can take place inside vblank */
179 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
180 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
181
182 /* Return current update_pending status: */
183 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
184}
185
48ef779f
AD		 186/**
187 * r100_pm_get_dynpm_state - look up dynpm power state callback.
188 *
189 * @rdev: radeon_device pointer
190 *
191 * Look up the optimal power state based on the
192 * current state of the GPU (r1xx-r5xx).
193 * Used for dynpm only.
194 */
ce8f5370 195void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 196{
197 int i;
ce8f5370
AD		 198 rdev->pm.dynpm_can_upclock = true;
199 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 200
ce8f5370
AD		 201 switch (rdev->pm.dynpm_planned_action) {
202 case DYNPM_ACTION_MINIMUM:
a48b9b4e 203 rdev->pm.requested_power_state_index = 0;
ce8f5370 204 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 205 break;
ce8f5370 206 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 207 if (rdev->pm.current_power_state_index == 0) {
208 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 209 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 210 } else {
211 if (rdev->pm.active_crtc_count > 1) {
212 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 213 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 214 continue;
215 else if (i >= rdev->pm.current_power_state_index) {
216 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
217 break;
218 } else {
219 rdev->pm.requested_power_state_index = i;
220 break;
221 }
222 }
223 } else
224 rdev->pm.requested_power_state_index =
225 rdev->pm.current_power_state_index - 1;
226 }
d7311171
AD		 227 /* don't use the power state if crtcs are active and no display flag is set */
228 if ((rdev->pm.active_crtc_count > 0) &&
229 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
230 RADEON_PM_MODE_NO_DISPLAY)) {
231 rdev->pm.requested_power_state_index++;
232 }
a48b9b4e 233 break;
ce8f5370 234 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 235 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
236 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 237 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 238 } else {
239 if (rdev->pm.active_crtc_count > 1) {
240 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 241 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 242 continue;
243 else if (i <= rdev->pm.current_power_state_index) {
244 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
245 break;
246 } else {
247 rdev->pm.requested_power_state_index = i;
248 break;
249 }
250 }
251 } else
252 rdev->pm.requested_power_state_index =
253 rdev->pm.current_power_state_index + 1;
254 }
255 break;
ce8f5370 256 case DYNPM_ACTION_DEFAULT:
58e21dff 257 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 258 rdev->pm.dynpm_can_upclock = false;
58e21dff 259 break;
ce8f5370 260 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 261 default:
262 DRM_ERROR("Requested mode for not defined action\n");
263 return;
264 }
265 /* only one clock mode per power state */
266 rdev->pm.requested_clock_mode_index = 0;
267
d9fdaafb 268 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 269 rdev->pm.power_state[rdev->pm.requested_power_state_index].
270 clock_info[rdev->pm.requested_clock_mode_index].sclk,
271 rdev->pm.power_state[rdev->pm.requested_power_state_index].
272 clock_info[rdev->pm.requested_clock_mode_index].mclk,
273 rdev->pm.power_state[rdev->pm.requested_power_state_index].
274 pcie_lanes);
a48b9b4e
AD		 275}
276
48ef779f
AD		 277/**
278 * r100_pm_init_profile - Initialize power profiles callback.
279 *
280 * @rdev: radeon_device pointer
281 *
282 * Initialize the power states used in profile mode
283 * (r1xx-r3xx).
284 * Used for profile mode only.
285 */
ce8f5370
AD		 286void r100_pm_init_profile(struct radeon_device *rdev)
287{
288 /* default */
289 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
290 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
291 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
292 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
293 /* low sh */
294 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
295 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
296 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
297 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 298 /* mid sh */
299 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
300 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
301 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
302 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 303 /* high sh */
304 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
305 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
306 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
308 /* low mh */
309 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
311 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 313 /* mid mh */
314 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
316 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
317 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 318 /* high mh */
319 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
321 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
322 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 323}
324
48ef779f
AD		 325/**
326 * r100_pm_misc - set additional pm hw parameters callback.
327 *
328 * @rdev: radeon_device pointer
329 *
330 * Set non-clock parameters associated with a power state
331 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
332 */
49e02b73
AD		 333void r100_pm_misc(struct radeon_device *rdev)
334{
49e02b73
AD		 335 int requested_index = rdev->pm.requested_power_state_index;
336 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
337 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
338 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
339
340 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
341 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
342 tmp = RREG32(voltage->gpio.reg);
343 if (voltage->active_high)
344 tmp |= voltage->gpio.mask;
345 else
346 tmp &= ~(voltage->gpio.mask);
347 WREG32(voltage->gpio.reg, tmp);
348 if (voltage->delay)
349 udelay(voltage->delay);
350 } else {
351 tmp = RREG32(voltage->gpio.reg);
352 if (voltage->active_high)
353 tmp &= ~voltage->gpio.mask;
354 else
355 tmp |= voltage->gpio.mask;
356 WREG32(voltage->gpio.reg, tmp);
357 if (voltage->delay)
358 udelay(voltage->delay);
359 }
360 }
361
362 sclk_cntl = RREG32_PLL(SCLK_CNTL);
363 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
364 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
365 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
366 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
367 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
368 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
369 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
370 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
371 else
372 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
373 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
374 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
375 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
376 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
377 } else
378 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
379
380 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
381 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
382 if (voltage->delay) {
383 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
384 switch (voltage->delay) {
385 case 33:
386 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
387 break;
388 case 66:
389 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
390 break;
391 case 99:
392 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
393 break;
394 case 132:
395 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
396 break;
397 }
398 } else
399 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
400 } else
401 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
402
403 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
404 sclk_cntl &= ~FORCE_HDP;
405 else
406 sclk_cntl |= FORCE_HDP;
407
408 WREG32_PLL(SCLK_CNTL, sclk_cntl);
409 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
410 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
411
412 /* set pcie lanes */
413 if ((rdev->flags & RADEON_IS_PCIE) &&
414 !(rdev->flags & RADEON_IS_IGP) &&
798bcf73 415 rdev->asic->pm.set_pcie_lanes &&
49e02b73
AD		 416 (ps->pcie_lanes !=
417 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
418 radeon_set_pcie_lanes(rdev,
419 ps->pcie_lanes);
d9fdaafb 420 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 421 }
49e02b73
AD		 422}
423
48ef779f
AD		 424/**
425 * r100_pm_prepare - pre-power state change callback.
426 *
427 * @rdev: radeon_device pointer
428 *
429 * Prepare for a power state change (r1xx-r4xx).
430 */
49e02b73
AD		 431void r100_pm_prepare(struct radeon_device *rdev)
432{
433 struct drm_device *ddev = rdev->ddev;
434 struct drm_crtc *crtc;
435 struct radeon_crtc *radeon_crtc;
436 u32 tmp;
437
438 /* disable any active CRTCs */
439 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
440 radeon_crtc = to_radeon_crtc(crtc);
441 if (radeon_crtc->enabled) {
442 if (radeon_crtc->crtc_id) {
443 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
444 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
445 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
446 } else {
447 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
448 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
449 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
450 }
451 }
452 }
453}
454
48ef779f
AD		 455/**
456 * r100_pm_finish - post-power state change callback.
457 *
458 * @rdev: radeon_device pointer
459 *
460 * Clean up after a power state change (r1xx-r4xx).
461 */
49e02b73
AD		 462void r100_pm_finish(struct radeon_device *rdev)
463{
464 struct drm_device *ddev = rdev->ddev;
465 struct drm_crtc *crtc;
466 struct radeon_crtc *radeon_crtc;
467 u32 tmp;
468
469 /* enable any active CRTCs */
470 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
471 radeon_crtc = to_radeon_crtc(crtc);
472 if (radeon_crtc->enabled) {
473 if (radeon_crtc->crtc_id) {
474 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
475 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
476 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
477 } else {
478 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
479 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
480 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
481 }
482 }
483 }
484}
485
48ef779f
AD		 486/**
487 * r100_gui_idle - gui idle callback.
488 *
489 * @rdev: radeon_device pointer
490 *
491 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
492 * Returns true if idle, false if not.
493 */
def9ba9c
AD		 494bool r100_gui_idle(struct radeon_device *rdev)
495{
496 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
497 return false;
498 else
499 return true;
500}
501
05a05c50 502/* hpd for digital panel detect/disconnect */
48ef779f
AD		 503/**
504 * r100_hpd_sense - hpd sense callback.
505 *
506 * @rdev: radeon_device pointer
507 * @hpd: hpd (hotplug detect) pin
508 *
509 * Checks if a digital monitor is connected (r1xx-r4xx).
510 * Returns true if connected, false if not connected.
511 */
05a05c50
AD		 512bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
513{
514 bool connected = false;
515
516 switch (hpd) {
517 case RADEON_HPD_1:
518 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
519 connected = true;
520 break;
521 case RADEON_HPD_2:
522 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
523 connected = true;
524 break;
525 default:
526 break;
527 }
528 return connected;
529}
530
48ef779f
AD		 531/**
532 * r100_hpd_set_polarity - hpd set polarity callback.
533 *
534 * @rdev: radeon_device pointer
535 * @hpd: hpd (hotplug detect) pin
536 *
537 * Set the polarity of the hpd pin (r1xx-r4xx).
538 */
05a05c50
AD		 539void r100_hpd_set_polarity(struct radeon_device *rdev,
540 enum radeon_hpd_id hpd)
541{
542 u32 tmp;
543 bool connected = r100_hpd_sense(rdev, hpd);
544
545 switch (hpd) {
546 case RADEON_HPD_1:
547 tmp = RREG32(RADEON_FP_GEN_CNTL);
548 if (connected)
549 tmp &= ~RADEON_FP_DETECT_INT_POL;
550 else
551 tmp |= RADEON_FP_DETECT_INT_POL;
552 WREG32(RADEON_FP_GEN_CNTL, tmp);
553 break;
554 case RADEON_HPD_2:
555 tmp = RREG32(RADEON_FP2_GEN_CNTL);
556 if (connected)
557 tmp &= ~RADEON_FP2_DETECT_INT_POL;
558 else
559 tmp |= RADEON_FP2_DETECT_INT_POL;
560 WREG32(RADEON_FP2_GEN_CNTL, tmp);
561 break;
562 default:
563 break;
564 }
565}
566
48ef779f
AD		 567/**
568 * r100_hpd_init - hpd setup callback.
569 *
570 * @rdev: radeon_device pointer
571 *
572 * Setup the hpd pins used by the card (r1xx-r4xx).
573 * Set the polarity, and enable the hpd interrupts.
574 */
05a05c50
AD		 575void r100_hpd_init(struct radeon_device *rdev)
576{
577 struct drm_device *dev = rdev->ddev;
578 struct drm_connector *connector;
fb98257a 579 unsigned enable = 0;
05a05c50
AD		 580
581 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
582 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 583 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 584 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
05a05c50 585 }
fb98257a 586 radeon_irq_kms_enable_hpd(rdev, enable);
05a05c50
AD		 587}
588
48ef779f
AD		 589/**
590 * r100_hpd_fini - hpd tear down callback.
591 *
592 * @rdev: radeon_device pointer
593 *
594 * Tear down the hpd pins used by the card (r1xx-r4xx).
595 * Disable the hpd interrupts.
596 */
05a05c50
AD		 597void r100_hpd_fini(struct radeon_device *rdev)
598{
599 struct drm_device *dev = rdev->ddev;
600 struct drm_connector *connector;
fb98257a 601 unsigned disable = 0;
05a05c50
AD		 602
603 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
604 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 605 disable |= 1 << radeon_connector->hpd.hpd;
05a05c50 606 }
fb98257a 607 radeon_irq_kms_disable_hpd(rdev, disable);
05a05c50
AD		 608}
609
771fe6b9
JG		 610/*
611 * PCI GART
612 */
613void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
614{
615 /* TODO: can we do somethings here ? */
616 /* It seems hw only cache one entry so we should discard this
617 * entry otherwise if first GPU GART read hit this entry it
618 * could end up in wrong address. */
619}
620
4aac0473 621int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 622{
771fe6b9
JG		 623 int r;
624
c9a1be96 625 if (rdev->gart.ptr) {
fce7d61b 626 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 627 return 0;
628 }
771fe6b9
JG		 629 /* Initialize common gart structure */
630 r = radeon_gart_init(rdev);
4aac0473 631 if (r)
771fe6b9 632 return r;
4aac0473 633 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
c5b3b850
AD		 634 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
635 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
4aac0473
JG		 636 return radeon_gart_table_ram_alloc(rdev);
637}
638
639int r100_pci_gart_enable(struct radeon_device *rdev)
640{
641 uint32_t tmp;
642
82568565 643 radeon_gart_restore(rdev);
771fe6b9
JG		 644 /* discard memory request outside of configured range */
645 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
646 WREG32(RADEON_AIC_CNTL, tmp);
647 /* set address range for PCI address translate */
d594e46a
JG		 648 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
649 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 650 /* set PCI GART page-table base address */
651 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
652 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
653 WREG32(RADEON_AIC_CNTL, tmp);
654 r100_pci_gart_tlb_flush(rdev);
43caf451 655 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
fcf4de5a
TV		 656 (unsigned)(rdev->mc.gtt_size >> 20),
657 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 658 rdev->gart.ready = true;
659 return 0;
660}
661
662void r100_pci_gart_disable(struct radeon_device *rdev)
663{
664 uint32_t tmp;
665
666 /* discard memory request outside of configured range */
667 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
668 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
669 WREG32(RADEON_AIC_LO_ADDR, 0);
670 WREG32(RADEON_AIC_HI_ADDR, 0);
671}
672
673int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
674{
c9a1be96
JG		 675 u32 *gtt = rdev->gart.ptr;
676
771fe6b9
JG		 677 if (i < 0 || i > rdev->gart.num_gpu_pages) {
678 return -EINVAL;
679 }
c9a1be96 680 gtt[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 681 return 0;
682}
683
4aac0473 684void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 685{
f9274562 686 radeon_gart_fini(rdev);
4aac0473
JG		 687 r100_pci_gart_disable(rdev);
688 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 689}
690
7ed220d7
MD		 691int r100_irq_set(struct radeon_device *rdev)
692{
693 uint32_t tmp = 0;
694
003e69f9 695 if (!rdev->irq.installed) {
fce7d61b 696 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 697 WREG32(R_000040_GEN_INT_CNTL, 0);
698 return -EINVAL;
699 }
736fc37f 700 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
7ed220d7
MD		 701 tmp |= RADEON_SW_INT_ENABLE;
702 }
6f34be50 703 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 704 atomic_read(&rdev->irq.pflip[0])) {
7ed220d7
MD		 705 tmp |= RADEON_CRTC_VBLANK_MASK;
706 }
6f34be50 707 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 708 atomic_read(&rdev->irq.pflip[1])) {
7ed220d7
MD		 709 tmp |= RADEON_CRTC2_VBLANK_MASK;
710 }
05a05c50
AD		 711 if (rdev->irq.hpd[0]) {
712 tmp |= RADEON_FP_DETECT_MASK;
713 }
714 if (rdev->irq.hpd[1]) {
715 tmp |= RADEON_FP2_DETECT_MASK;
716 }
7ed220d7
MD		 717 WREG32(RADEON_GEN_INT_CNTL, tmp);
718 return 0;
719}
720
9f022ddf
JG		 721void r100_irq_disable(struct radeon_device *rdev)
722{
723 u32 tmp;
724
725 WREG32(R_000040_GEN_INT_CNTL, 0);
726 /* Wait and acknowledge irq */
727 mdelay(1);
728 tmp = RREG32(R_000044_GEN_INT_STATUS);
729 WREG32(R_000044_GEN_INT_STATUS, tmp);
730}
731
cbdd4501 732static uint32_t r100_irq_ack(struct radeon_device *rdev)
7ed220d7
MD		 733{
734 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 735 uint32_t irq_mask = RADEON_SW_INT_TEST |
736 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
737 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 738
739 if (irqs) {
740 WREG32(RADEON_GEN_INT_STATUS, irqs);
741 }
742 return irqs & irq_mask;
743}
744
745int r100_irq_process(struct radeon_device *rdev)
746{
3e5cb98d 747 uint32_t status, msi_rearm;
d4877cf2 748 bool queue_hotplug = false;
7ed220d7
MD		 749
750 status = r100_irq_ack(rdev);
751 if (!status) {
752 return IRQ_NONE;
753 }
a513c184
JG		 754 if (rdev->shutdown) {
755 return IRQ_NONE;
756 }
7ed220d7
MD		 757 while (status) {
758 /* SW interrupt */
759 if (status & RADEON_SW_INT_TEST) {
7465280c 760 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7ed220d7
MD		 761 }
762 /* Vertical blank interrupts */
763 if (status & RADEON_CRTC_VBLANK_STAT) {
6f34be50
AD		 764 if (rdev->irq.crtc_vblank_int[0]) {
765 drm_handle_vblank(rdev->ddev, 0);
766 rdev->pm.vblank_sync = true;
767 wake_up(&rdev->irq.vblank_queue);
768 }
736fc37f 769 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 770 radeon_crtc_handle_flip(rdev, 0);
7ed220d7
MD		 771 }
772 if (status & RADEON_CRTC2_VBLANK_STAT) {
6f34be50
AD		 773 if (rdev->irq.crtc_vblank_int[1]) {
774 drm_handle_vblank(rdev->ddev, 1);
775 rdev->pm.vblank_sync = true;
776 wake_up(&rdev->irq.vblank_queue);
777 }
736fc37f 778 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 779 radeon_crtc_handle_flip(rdev, 1);
7ed220d7 780 }
05a05c50 781 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 782 queue_hotplug = true;
783 DRM_DEBUG("HPD1\n");
05a05c50
AD		 784 }
785 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 786 queue_hotplug = true;
787 DRM_DEBUG("HPD2\n");
05a05c50 788 }
7ed220d7
MD		 789 status = r100_irq_ack(rdev);
790 }
d4877cf2 791 if (queue_hotplug)
32c87fca 792 schedule_work(&rdev->hotplug_work);
3e5cb98d
AD		 793 if (rdev->msi_enabled) {
794 switch (rdev->family) {
795 case CHIP_RS400:
796 case CHIP_RS480:
797 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
798 WREG32(RADEON_AIC_CNTL, msi_rearm);
799 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
800 break;
801 default:
b7f5b7de 802 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
3e5cb98d
AD		 803 break;
804 }
805 }
7ed220d7
MD		 806 return IRQ_HANDLED;
807}
808
809u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
810{
811 if (crtc == 0)
812 return RREG32(RADEON_CRTC_CRNT_FRAME);
813 else
814 return RREG32(RADEON_CRTC2_CRNT_FRAME);
815}
816
9e5b2af7
PN		 817/* Who ever call radeon_fence_emit should call ring_lock and ask
818 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 819void r100_fence_ring_emit(struct radeon_device *rdev,
820 struct radeon_fence *fence)
821{
e32eb50d 822 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 823
9e5b2af7
PN		 824 /* We have to make sure that caches are flushed before
825 * CPU might read something from VRAM. */
e32eb50d
CK		 826 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
827 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
828 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
829 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 830 /* Wait until IDLE & CLEAN */
e32eb50d
CK		 831 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
832 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
833 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
834 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
cafe6609 835 RADEON_HDP_READ_BUFFER_INVALIDATE);
e32eb50d
CK		 836 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
837 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
771fe6b9 838 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 839 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
840 radeon_ring_write(ring, fence->seq);
841 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
842 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
771fe6b9
JG		 843}
844
15d3332f 845void r100_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 846 struct radeon_ring *ring,
15d3332f 847 struct radeon_semaphore *semaphore,
7b1f2485 848 bool emit_wait)
15d3332f
CK		 849{
850 /* Unused on older asics, since we don't have semaphores or multiple rings */
851 BUG();
852}
853
771fe6b9
JG		 854int r100_copy_blit(struct radeon_device *rdev,
855 uint64_t src_offset,
856 uint64_t dst_offset,
003cefe0 857 unsigned num_gpu_pages,
876dc9f3 858 struct radeon_fence **fence)
771fe6b9 859{
e32eb50d 860 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9 861 uint32_t cur_pages;
003cefe0 862 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
771fe6b9
JG		 863 uint32_t pitch;
864 uint32_t stride_pixels;
865 unsigned ndw;
866 int num_loops;
867 int r = 0;
868
869 /* radeon limited to 16k stride */
870 stride_bytes &= 0x3fff;
871 /* radeon pitch is /64 */
872 pitch = stride_bytes / 64;
873 stride_pixels = stride_bytes / 4;
003cefe0 874 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
771fe6b9
JG		 875
876 /* Ask for enough room for blit + flush + fence */
877 ndw = 64 + (10 * num_loops);
e32eb50d 878 r = radeon_ring_lock(rdev, ring, ndw);
771fe6b9
JG		 879 if (r) {
880 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
881 return -EINVAL;
882 }
003cefe0
AD		 883 while (num_gpu_pages > 0) {
884 cur_pages = num_gpu_pages;
771fe6b9
JG		 885 if (cur_pages > 8191) {
886 cur_pages = 8191;
887 }
003cefe0 888 num_gpu_pages -= cur_pages;
771fe6b9
JG		 889
890 /* pages are in Y direction - height
891 page width in X direction - width */
e32eb50d
CK		 892 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
893 radeon_ring_write(ring,
771fe6b9
JG		 894 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
895 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
896 RADEON_GMC_SRC_CLIPPING |
897 RADEON_GMC_DST_CLIPPING |
898 RADEON_GMC_BRUSH_NONE |
899 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
900 RADEON_GMC_SRC_DATATYPE_COLOR |
901 RADEON_ROP3_S |
902 RADEON_DP_SRC_SOURCE_MEMORY |
903 RADEON_GMC_CLR_CMP_CNTL_DIS |
904 RADEON_GMC_WR_MSK_DIS);
e32eb50d
CK		 905 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
906 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
907 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
908 radeon_ring_write(ring, 0);
909 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
910 radeon_ring_write(ring, num_gpu_pages);
911 radeon_ring_write(ring, num_gpu_pages);
912 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
913 }
914 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
915 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
916 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
917 radeon_ring_write(ring,
771fe6b9
JG		 918 RADEON_WAIT_2D_IDLECLEAN |
919 RADEON_WAIT_HOST_IDLECLEAN |
920 RADEON_WAIT_DMA_GUI_IDLE);
921 if (fence) {
876dc9f3 922 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
771fe6b9 923 }
e32eb50d 924 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 925 return r;
926}
927
45600232
JG		 928static int r100_cp_wait_for_idle(struct radeon_device *rdev)
929{
930 unsigned i;
931 u32 tmp;
932
933 for (i = 0; i < rdev->usec_timeout; i++) {
934 tmp = RREG32(R_000E40_RBBM_STATUS);
935 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
936 return 0;
937 }
938 udelay(1);
939 }
940 return -1;
941}
942
f712812e 943void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9
JG		 944{
945 int r;
946
e32eb50d 947 r = radeon_ring_lock(rdev, ring, 2);
771fe6b9
JG		 948 if (r) {
949 return;
950 }
e32eb50d
CK		 951 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
952 radeon_ring_write(ring,
771fe6b9
JG		 953 RADEON_ISYNC_ANY2D_IDLE3D |
954 RADEON_ISYNC_ANY3D_IDLE2D |
955 RADEON_ISYNC_WAIT_IDLEGUI |
956 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
e32eb50d 957 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 958}
959
70967ab9
BH		 960
961/* Load the microcode for the CP */
962static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 963{
70967ab9
BH		 964 struct platform_device *pdev;
965 const char *fw_name = NULL;
966 int err;
771fe6b9 967
d9fdaafb 968 DRM_DEBUG_KMS("\n");
771fe6b9 969
70967ab9
BH		 970 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
971 err = IS_ERR(pdev);
972 if (err) {
973 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
974 return -EINVAL;
975 }
771fe6b9
JG		 976 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
977 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
978 (rdev->family == CHIP_RS200)) {
979 DRM_INFO("Loading R100 Microcode\n");
70967ab9 980 fw_name = FIRMWARE_R100;
771fe6b9
JG		 981 } else if ((rdev->family == CHIP_R200) ||
982 (rdev->family == CHIP_RV250) ||
983 (rdev->family == CHIP_RV280) ||
984 (rdev->family == CHIP_RS300)) {
985 DRM_INFO("Loading R200 Microcode\n");
70967ab9 986 fw_name = FIRMWARE_R200;
771fe6b9
JG		 987 } else if ((rdev->family == CHIP_R300) ||
988 (rdev->family == CHIP_R350) ||
989 (rdev->family == CHIP_RV350) ||
990 (rdev->family == CHIP_RV380) ||
991 (rdev->family == CHIP_RS400) ||
992 (rdev->family == CHIP_RS480)) {
993 DRM_INFO("Loading R300 Microcode\n");
70967ab9 994 fw_name = FIRMWARE_R300;
771fe6b9
JG		 995 } else if ((rdev->family == CHIP_R420) ||
996 (rdev->family == CHIP_R423) ||
997 (rdev->family == CHIP_RV410)) {
998 DRM_INFO("Loading R400 Microcode\n");
70967ab9 999 fw_name = FIRMWARE_R420;
771fe6b9
JG		 1000 } else if ((rdev->family == CHIP_RS690) ||
1001 (rdev->family == CHIP_RS740)) {
1002 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 1003 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 1004 } else if (rdev->family == CHIP_RS600) {
1005 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 1006 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 1007 } else if ((rdev->family == CHIP_RV515) ||
1008 (rdev->family == CHIP_R520) ||
1009 (rdev->family == CHIP_RV530) ||
1010 (rdev->family == CHIP_R580) ||
1011 (rdev->family == CHIP_RV560) ||
1012 (rdev->family == CHIP_RV570)) {
1013 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 1014 fw_name = FIRMWARE_R520;
1015 }
1016
3ce0a23d 1017 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 1018 platform_device_unregister(pdev);
1019 if (err) {
1020 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1021 fw_name);
3ce0a23d 1022 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 1023 printk(KERN_ERR
1024 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 1025 rdev->me_fw->size, fw_name);
70967ab9 1026 err = -EINVAL;
3ce0a23d
JG		 1027 release_firmware(rdev->me_fw);
1028 rdev->me_fw = NULL;
70967ab9
BH		 1029 }
1030 return err;
1031}
d4550907 1032
70967ab9
BH		 1033static void r100_cp_load_microcode(struct radeon_device *rdev)
1034{
1035 const __be32 *fw_data;
1036 int i, size;
1037
1038 if (r100_gui_wait_for_idle(rdev)) {
1039 printk(KERN_WARNING "Failed to wait GUI idle while "
1040 "programming pipes. Bad things might happen.\n");
1041 }
1042
3ce0a23d
JG		 1043 if (rdev->me_fw) {
1044 size = rdev->me_fw->size / 4;
1045 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 1046 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1047 for (i = 0; i < size; i += 2) {
1048 WREG32(RADEON_CP_ME_RAM_DATAH,
1049 be32_to_cpup(&fw_data[i]));
1050 WREG32(RADEON_CP_ME_RAM_DATAL,
1051 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 1052 }
1053 }
1054}
1055
1056int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1057{
e32eb50d 1058 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9
JG		 1059 unsigned rb_bufsz;
1060 unsigned rb_blksz;
1061 unsigned max_fetch;
1062 unsigned pre_write_timer;
1063 unsigned pre_write_limit;
1064 unsigned indirect2_start;
1065 unsigned indirect1_start;
1066 uint32_t tmp;
1067 int r;
1068
1069 if (r100_debugfs_cp_init(rdev)) {
1070 DRM_ERROR("Failed to register debugfs file for CP !\n");
1071 }
3ce0a23d 1072 if (!rdev->me_fw) {
70967ab9
BH		 1073 r = r100_cp_init_microcode(rdev);
1074 if (r) {
1075 DRM_ERROR("Failed to load firmware!\n");
1076 return r;
1077 }
1078 }
1079
771fe6b9
JG		 1080 /* Align ring size */
1081 rb_bufsz = drm_order(ring_size / 8);
1082 ring_size = (1 << (rb_bufsz + 1)) * 4;
1083 r100_cp_load_microcode(rdev);
e32eb50d 1084 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 1085 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1086 0, 0x7fffff, RADEON_CP_PACKET2);
771fe6b9
JG		 1087 if (r) {
1088 return r;
1089 }
1090 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1091 * the rptr copy in system ram */
1092 rb_blksz = 9;
1093 /* cp will read 128bytes at a time (4 dwords) */
1094 max_fetch = 1;
e32eb50d 1095 ring->align_mask = 16 - 1;
771fe6b9
JG		 1096 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1097 pre_write_timer = 64;
1098 /* Force CP_RB_WPTR write if written more than one time before the
1099 * delay expire
1100 */
1101 pre_write_limit = 0;
1102 /* Setup the cp cache like this (cache size is 96 dwords) :
1103 * RING 0 to 15
1104 * INDIRECT1 16 to 79
1105 * INDIRECT2 80 to 95
1106 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1107 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1108 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1109 * Idea being that most of the gpu cmd will be through indirect1 buffer
1110 * so it gets the bigger cache.
1111 */
1112 indirect2_start = 80;
1113 indirect1_start = 16;
1114 /* cp setup */
1115 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 1116 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 1117 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 1118 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 1119#ifdef __BIG_ENDIAN
1120 tmp |= RADEON_BUF_SWAP_32BIT;
1121#endif
724c80e1 1122 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 1123
771fe6b9 1124 /* Set ring address */
e32eb50d
CK		 1125 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1126 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
771fe6b9 1127 /* Force read & write ptr to 0 */
724c80e1 1128 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9 1129 WREG32(RADEON_CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1130 ring->wptr = 0;
1131 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1132
1133 /* set the wb address whether it's enabled or not */
1134 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1135 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1136 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1137
1138 if (rdev->wb.enabled)
1139 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1140 else {
1141 tmp |= RADEON_RB_NO_UPDATE;
1142 WREG32(R_000770_SCRATCH_UMSK, 0);
1143 }
1144
771fe6b9
JG		 1145 WREG32(RADEON_CP_RB_CNTL, tmp);
1146 udelay(10);
e32eb50d 1147 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
771fe6b9
JG		 1148 /* Set cp mode to bus mastering & enable cp*/
1149 WREG32(RADEON_CP_CSQ_MODE,
1150 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1151 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
d75ee3be
AD		 1152 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1153 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
771fe6b9 1154 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
2099810f
DA		 1155
1156 /* at this point everything should be setup correctly to enable master */
1157 pci_set_master(rdev->pdev);
1158
f712812e
AD		 1159 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1160 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
771fe6b9
JG		 1161 if (r) {
1162 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1163 return r;
1164 }
e32eb50d 1165 ring->ready = true;
53595338 1166 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
c7eff978 1167
16c58081
SK		 1168 if (!ring->rptr_save_reg /* not resuming from suspend */
1169 && radeon_ring_supports_scratch_reg(rdev, ring)) {
c7eff978
AD		 1170 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1171 if (r) {
1172 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1173 ring->rptr_save_reg = 0;
1174 }
1175 }
771fe6b9
JG		 1176 return 0;
1177}
1178
1179void r100_cp_fini(struct radeon_device *rdev)
1180{
45600232
JG		 1181 if (r100_cp_wait_for_idle(rdev)) {
1182 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1183 }
771fe6b9 1184 /* Disable ring */
a18d7ea1 1185 r100_cp_disable(rdev);
c7eff978 1186 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
e32eb50d 1187 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
771fe6b9
JG		 1188 DRM_INFO("radeon: cp finalized\n");
1189}
1190
1191void r100_cp_disable(struct radeon_device *rdev)
1192{
1193 /* Disable ring */
53595338 1194 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
e32eb50d 1195 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
771fe6b9
JG		 1196 WREG32(RADEON_CP_CSQ_MODE, 0);
1197 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1198 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1199 if (r100_gui_wait_for_idle(rdev)) {
1200 printk(KERN_WARNING "Failed to wait GUI idle while "
1201 "programming pipes. Bad things might happen.\n");
1202 }
1203}
1204
771fe6b9
JG		 1205/*
1206 * CS functions
1207 */
0242f74d
AD		 1208int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1209 struct radeon_cs_packet *pkt,
1210 unsigned idx,
1211 unsigned reg)
1212{
1213 int r;
1214 u32 tile_flags = 0;
1215 u32 tmp;
1216 struct radeon_cs_reloc *reloc;
1217 u32 value;
1218
1219 r = r100_cs_packet_next_reloc(p, &reloc);
1220 if (r) {
1221 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1222 idx, reg);
1223 r100_cs_dump_packet(p, pkt);
1224 return r;
1225 }
1226
1227 value = radeon_get_ib_value(p, idx);
1228 tmp = value & 0x003fffff;
1229 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1230
1231 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1232 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1233 tile_flags |= RADEON_DST_TILE_MACRO;
1234 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1235 if (reg == RADEON_SRC_PITCH_OFFSET) {
1236 DRM_ERROR("Cannot src blit from microtiled surface\n");
1237 r100_cs_dump_packet(p, pkt);
1238 return -EINVAL;
1239 }
1240 tile_flags |= RADEON_DST_TILE_MICRO;
1241 }
1242
1243 tmp |= tile_flags;
1244 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1245 } else
1246 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1247 return 0;
1248}
1249
1250int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1251 struct radeon_cs_packet *pkt,
1252 int idx)
1253{
1254 unsigned c, i;
1255 struct radeon_cs_reloc *reloc;
1256 struct r100_cs_track *track;
1257 int r = 0;
1258 volatile uint32_t *ib;
1259 u32 idx_value;
1260
1261 ib = p->ib.ptr;
1262 track = (struct r100_cs_track *)p->track;
1263 c = radeon_get_ib_value(p, idx++) & 0x1F;
1264 if (c > 16) {
1265 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1266 pkt->opcode);
1267 r100_cs_dump_packet(p, pkt);
1268 return -EINVAL;
1269 }
1270 track->num_arrays = c;
1271 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1272 r = r100_cs_packet_next_reloc(p, &reloc);
1273 if (r) {
1274 DRM_ERROR("No reloc for packet3 %d\n",
1275 pkt->opcode);
1276 r100_cs_dump_packet(p, pkt);
1277 return r;
1278 }
1279 idx_value = radeon_get_ib_value(p, idx);
1280 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1281
1282 track->arrays[i + 0].esize = idx_value >> 8;
1283 track->arrays[i + 0].robj = reloc->robj;
1284 track->arrays[i + 0].esize &= 0x7F;
1285 r = r100_cs_packet_next_reloc(p, &reloc);
1286 if (r) {
1287 DRM_ERROR("No reloc for packet3 %d\n",
1288 pkt->opcode);
1289 r100_cs_dump_packet(p, pkt);
1290 return r;
1291 }
1292 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1293 track->arrays[i + 1].robj = reloc->robj;
1294 track->arrays[i + 1].esize = idx_value >> 24;
1295 track->arrays[i + 1].esize &= 0x7F;
1296 }
1297 if (c & 1) {
1298 r = r100_cs_packet_next_reloc(p, &reloc);
1299 if (r) {
1300 DRM_ERROR("No reloc for packet3 %d\n",
1301 pkt->opcode);
1302 r100_cs_dump_packet(p, pkt);
1303 return r;
1304 }
1305 idx_value = radeon_get_ib_value(p, idx);
1306 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1307 track->arrays[i + 0].robj = reloc->robj;
1308 track->arrays[i + 0].esize = idx_value >> 8;
1309 track->arrays[i + 0].esize &= 0x7F;
1310 }
1311 return r;
1312}
1313
771fe6b9
JG		 1314int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1315 struct radeon_cs_packet *pkt,
068a117c 1316 const unsigned *auth, unsigned n,
771fe6b9
JG		 1317 radeon_packet0_check_t check)
1318{
1319 unsigned reg;
1320 unsigned i, j, m;
1321 unsigned idx;
1322 int r;
1323
1324 idx = pkt->idx + 1;
1325 reg = pkt->reg;
068a117c
JG		 1326 /* Check that register fall into register range
1327 * determined by the number of entry (n) in the
1328 * safe register bitmap.
1329 */
771fe6b9
JG		 1330 if (pkt->one_reg_wr) {
1331 if ((reg >> 7) > n) {
1332 return -EINVAL;
1333 }
1334 } else {
1335 if (((reg + (pkt->count << 2)) >> 7) > n) {
1336 return -EINVAL;
1337 }
1338 }
1339 for (i = 0; i <= pkt->count; i++, idx++) {
1340 j = (reg >> 7);
1341 m = 1 << ((reg >> 2) & 31);
1342 if (auth[j] & m) {
1343 r = check(p, pkt, idx, reg);
1344 if (r) {
1345 return r;
1346 }
1347 }
1348 if (pkt->one_reg_wr) {
1349 if (!(auth[j] & m)) {
1350 break;
1351 }
1352 } else {
1353 reg += 4;
1354 }
1355 }
1356 return 0;
1357}
1358
771fe6b9
JG		 1359void r100_cs_dump_packet(struct radeon_cs_parser *p,
1360 struct radeon_cs_packet *pkt)
1361{
771fe6b9
JG		 1362 volatile uint32_t *ib;
1363 unsigned i;
1364 unsigned idx;
1365
f2e39221 1366 ib = p->ib.ptr;
771fe6b9
JG		 1367 idx = pkt->idx;
1368 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1369 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1370 }
1371}
1372
1373/**
1374 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1375 * @parser: parser structure holding parsing context.
1376 * @pkt: where to store packet informations
1377 *
1378 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1379 * if packet is bigger than remaining ib size. or if packets is unknown.
1380 **/
1381int r100_cs_packet_parse(struct radeon_cs_parser *p,
1382 struct radeon_cs_packet *pkt,
1383 unsigned idx)
1384{
1385 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 1386 uint32_t header;
771fe6b9
JG		 1387
1388 if (idx >= ib_chunk->length_dw) {
1389 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1390 idx, ib_chunk->length_dw);
1391 return -EINVAL;
1392 }
513bcb46 1393 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 1394 pkt->idx = idx;
1395 pkt->type = CP_PACKET_GET_TYPE(header);
1396 pkt->count = CP_PACKET_GET_COUNT(header);
1397 switch (pkt->type) {
1398 case PACKET_TYPE0:
1399 pkt->reg = CP_PACKET0_GET_REG(header);
1400 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1401 break;
1402 case PACKET_TYPE3:
1403 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1404 break;
1405 case PACKET_TYPE2:
1406 pkt->count = -1;
1407 break;
1408 default:
1409 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1410 return -EINVAL;
1411 }
1412 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1413 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1414 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1415 return -EINVAL;
1416 }
1417 return 0;
1418}
1419
531369e6
DA		 1420/**
1421 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1422 * @parser: parser structure holding parsing context.
1423 *
1424 * Userspace sends a special sequence for VLINE waits.
1425 * PACKET0 - VLINE_START_END + value
1426 * PACKET0 - WAIT_UNTIL +_value
1427 * RELOC (P3) - crtc_id in reloc.
1428 *
1429 * This function parses this and relocates the VLINE START END
1430 * and WAIT UNTIL packets to the correct crtc.
1431 * It also detects a switched off crtc and nulls out the
1432 * wait in that case.
1433 */
1434int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1435{
531369e6
DA		 1436 struct drm_mode_object *obj;
1437 struct drm_crtc *crtc;
1438 struct radeon_crtc *radeon_crtc;
1439 struct radeon_cs_packet p3reloc, waitreloc;
1440 int crtc_id;
1441 int r;
1442 uint32_t header, h_idx, reg;
513bcb46 1443 volatile uint32_t *ib;
531369e6 1444
f2e39221 1445 ib = p->ib.ptr;
531369e6
DA		 1446
1447 /* parse the wait until */
1448 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1449 if (r)
1450 return r;
1451
1452 /* check its a wait until and only 1 count */
1453 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1454 waitreloc.count != 0) {
1455 DRM_ERROR("vline wait had illegal wait until segment\n");
a3a88a66 1456 return -EINVAL;
531369e6
DA		 1457 }
1458
513bcb46 1459 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6 1460 DRM_ERROR("vline wait had illegal wait until\n");
a3a88a66 1461 return -EINVAL;
531369e6
DA		 1462 }
1463
1464 /* jump over the NOP */
90ebd065 1465 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1466 if (r)
1467 return r;
1468
1469 h_idx = p->idx - 2;
90ebd065
AD		 1470 p->idx += waitreloc.count + 2;
1471 p->idx += p3reloc.count + 2;
531369e6 1472
513bcb46
DA		 1473 header = radeon_get_ib_value(p, h_idx);
1474 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 1475 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 1476 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1477 if (!obj) {
1478 DRM_ERROR("cannot find crtc %d\n", crtc_id);
a3a88a66 1479 return -EINVAL;
531369e6
DA		 1480 }
1481 crtc = obj_to_crtc(obj);
1482 radeon_crtc = to_radeon_crtc(crtc);
1483 crtc_id = radeon_crtc->crtc_id;
1484
1485 if (!crtc->enabled) {
1486 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1487 ib[h_idx + 2] = PACKET2(0);
1488 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1489 } else if (crtc_id == 1) {
1490 switch (reg) {
1491 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1492 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1493 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1494 break;
1495 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1496 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1497 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1498 break;
1499 default:
1500 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1501 return -EINVAL;
531369e6 1502 }
513bcb46
DA		 1503 ib[h_idx] = header;
1504 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6 1505 }
a3a88a66
PB		 1506
1507 return 0;
531369e6
DA		 1508}
1509
771fe6b9
JG		 1510/**
1511 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1512 * @parser: parser structure holding parsing context.
1513 * @data: pointer to relocation data
1514 * @offset_start: starting offset
1515 * @offset_mask: offset mask (to align start offset on)
1516 * @reloc: reloc informations
1517 *
1518 * Check next packet is relocation packet3, do bo validation and compute
1519 * GPU offset using the provided start.
1520 **/
1521int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1522 struct radeon_cs_reloc **cs_reloc)
1523{
771fe6b9
JG		 1524 struct radeon_cs_chunk *relocs_chunk;
1525 struct radeon_cs_packet p3reloc;
1526 unsigned idx;
1527 int r;
1528
1529 if (p->chunk_relocs_idx == -1) {
1530 DRM_ERROR("No relocation chunk !\n");
1531 return -EINVAL;
1532 }
1533 *cs_reloc = NULL;
771fe6b9
JG		 1534 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1535 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1536 if (r) {
1537 return r;
1538 }
1539 p->idx += p3reloc.count + 2;
1540 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1541 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1542 p3reloc.idx);
1543 r100_cs_dump_packet(p, &p3reloc);
1544 return -EINVAL;
1545 }
513bcb46 1546 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1547 if (idx >= relocs_chunk->length_dw) {
1548 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1549 idx, relocs_chunk->length_dw);
1550 r100_cs_dump_packet(p, &p3reloc);
1551 return -EINVAL;
1552 }
1553 /* FIXME: we assume reloc size is 4 dwords */
1554 *cs_reloc = p->relocs_ptr[(idx / 4)];
1555 return 0;
1556}
1557
551ebd83
DA		 1558static int r100_get_vtx_size(uint32_t vtx_fmt)
1559{
1560 int vtx_size;
1561 vtx_size = 2;
1562 /* ordered according to bits in spec */
1563 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1564 vtx_size++;
1565 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1566 vtx_size += 3;
1567 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1568 vtx_size++;
1569 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1570 vtx_size++;
1571 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1572 vtx_size += 3;
1573 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1574 vtx_size++;
1575 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1576 vtx_size++;
1577 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1578 vtx_size += 2;
1579 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1580 vtx_size += 2;
1581 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1582 vtx_size++;
1583 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1584 vtx_size += 2;
1585 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1586 vtx_size++;
1587 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1588 vtx_size += 2;
1589 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1590 vtx_size++;
1591 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1592 vtx_size++;
1593 /* blend weight */
1594 if (vtx_fmt & (0x7 << 15))
1595 vtx_size += (vtx_fmt >> 15) & 0x7;
1596 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1597 vtx_size += 3;
1598 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1599 vtx_size += 2;
1600 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1601 vtx_size++;
1602 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1603 vtx_size++;
1604 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1605 vtx_size++;
1606 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1607 vtx_size++;
1608 return vtx_size;
1609}
1610
771fe6b9 1611static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1612 struct radeon_cs_packet *pkt,
1613 unsigned idx, unsigned reg)
771fe6b9 1614{
771fe6b9 1615 struct radeon_cs_reloc *reloc;
551ebd83 1616 struct r100_cs_track *track;
771fe6b9
JG		 1617 volatile uint32_t *ib;
1618 uint32_t tmp;
771fe6b9 1619 int r;
551ebd83 1620 int i, face;
e024e110 1621 u32 tile_flags = 0;
513bcb46 1622 u32 idx_value;
771fe6b9 1623
f2e39221 1624 ib = p->ib.ptr;
551ebd83
DA		 1625 track = (struct r100_cs_track *)p->track;
1626
513bcb46
DA		 1627 idx_value = radeon_get_ib_value(p, idx);
1628
551ebd83
DA		 1629 switch (reg) {
1630 case RADEON_CRTC_GUI_TRIG_VLINE:
1631 r = r100_cs_packet_parse_vline(p);
1632 if (r) {
1633 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1634 idx, reg);
1635 r100_cs_dump_packet(p, pkt);
1636 return r;
1637 }
1638 break;
771fe6b9
JG		 1639 /* FIXME: only allow PACKET3 blit? easier to check for out of
1640 * range access */
551ebd83
DA		 1641 case RADEON_DST_PITCH_OFFSET:
1642 case RADEON_SRC_PITCH_OFFSET:
1643 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1644 if (r)
1645 return r;
1646 break;
1647 case RADEON_RB3D_DEPTHOFFSET:
1648 r = r100_cs_packet_next_reloc(p, &reloc);
1649 if (r) {
1650 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1651 idx, reg);
1652 r100_cs_dump_packet(p, pkt);
1653 return r;
1654 }
1655 track->zb.robj = reloc->robj;
513bcb46 1656 track->zb.offset = idx_value;
40b4a759 1657 track->zb_dirty = true;
513bcb46 1658 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1659 break;
1660 case RADEON_RB3D_COLOROFFSET:
1661 r = r100_cs_packet_next_reloc(p, &reloc);
1662 if (r) {
1663 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1664 idx, reg);
1665 r100_cs_dump_packet(p, pkt);
1666 return r;
1667 }
1668 track->cb[0].robj = reloc->robj;
513bcb46 1669 track->cb[0].offset = idx_value;
40b4a759 1670 track->cb_dirty = true;
513bcb46 1671 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1672 break;
1673 case RADEON_PP_TXOFFSET_0:
1674 case RADEON_PP_TXOFFSET_1:
1675 case RADEON_PP_TXOFFSET_2:
1676 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1677 r = r100_cs_packet_next_reloc(p, &reloc);
1678 if (r) {
1679 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1680 idx, reg);
1681 r100_cs_dump_packet(p, pkt);
1682 return r;
1683 }
f2746f83
AD		 1684 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1685 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1686 tile_flags |= RADEON_TXO_MACRO_TILE;
1687 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1688 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1689
1690 tmp = idx_value & ~(0x7 << 2);
1691 tmp |= tile_flags;
1692 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1693 } else
1694 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1695 track->textures[i].robj = reloc->robj;
40b4a759 1696 track->tex_dirty = true;
551ebd83
DA		 1697 break;
1698 case RADEON_PP_CUBIC_OFFSET_T0_0:
1699 case RADEON_PP_CUBIC_OFFSET_T0_1:
1700 case RADEON_PP_CUBIC_OFFSET_T0_2:
1701 case RADEON_PP_CUBIC_OFFSET_T0_3:
1702 case RADEON_PP_CUBIC_OFFSET_T0_4:
1703 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1704 r = r100_cs_packet_next_reloc(p, &reloc);
1705 if (r) {
1706 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1707 idx, reg);
1708 r100_cs_dump_packet(p, pkt);
1709 return r;
1710 }
513bcb46
DA		 1711 track->textures[0].cube_info[i].offset = idx_value;
1712 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1713 track->textures[0].cube_info[i].robj = reloc->robj;
40b4a759 1714 track->tex_dirty = true;
551ebd83
DA		 1715 break;
1716 case RADEON_PP_CUBIC_OFFSET_T1_0:
1717 case RADEON_PP_CUBIC_OFFSET_T1_1:
1718 case RADEON_PP_CUBIC_OFFSET_T1_2:
1719 case RADEON_PP_CUBIC_OFFSET_T1_3:
1720 case RADEON_PP_CUBIC_OFFSET_T1_4:
1721 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1722 r = r100_cs_packet_next_reloc(p, &reloc);
1723 if (r) {
1724 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1725 idx, reg);
1726 r100_cs_dump_packet(p, pkt);
1727 return r;
1728 }
513bcb46
DA		 1729 track->textures[1].cube_info[i].offset = idx_value;
1730 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1731 track->textures[1].cube_info[i].robj = reloc->robj;
40b4a759 1732 track->tex_dirty = true;
551ebd83
DA		 1733 break;
1734 case RADEON_PP_CUBIC_OFFSET_T2_0:
1735 case RADEON_PP_CUBIC_OFFSET_T2_1:
1736 case RADEON_PP_CUBIC_OFFSET_T2_2:
1737 case RADEON_PP_CUBIC_OFFSET_T2_3:
1738 case RADEON_PP_CUBIC_OFFSET_T2_4:
1739 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1740 r = r100_cs_packet_next_reloc(p, &reloc);
1741 if (r) {
1742 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1743 idx, reg);
1744 r100_cs_dump_packet(p, pkt);
1745 return r;
1746 }
513bcb46
DA		 1747 track->textures[2].cube_info[i].offset = idx_value;
1748 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1749 track->textures[2].cube_info[i].robj = reloc->robj;
40b4a759 1750 track->tex_dirty = true;
551ebd83
DA		 1751 break;
1752 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1753 track->maxy = ((idx_value >> 16) & 0x7FF);
40b4a759
MO		 1754 track->cb_dirty = true;
1755 track->zb_dirty = true;
551ebd83
DA		 1756 break;
1757 case RADEON_RB3D_COLORPITCH:
1758 r = r100_cs_packet_next_reloc(p, &reloc);
1759 if (r) {
1760 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1761 idx, reg);
1762 r100_cs_dump_packet(p, pkt);
1763 return r;
1764 }
c9068eb2
AD		 1765 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1766 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1767 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1768 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1769 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1770
1771 tmp = idx_value & ~(0x7 << 16);
1772 tmp |= tile_flags;
1773 ib[idx] = tmp;
1774 } else
1775 ib[idx] = idx_value;
e024e110 1776
513bcb46 1777 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
40b4a759 1778 track->cb_dirty = true;
551ebd83
DA		 1779 break;
1780 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1781 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
40b4a759 1782 track->zb_dirty = true;
551ebd83
DA		 1783 break;
1784 case RADEON_RB3D_CNTL:
513bcb46 1785 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1786 case 7:
1787 case 8:
1788 case 9:
1789 case 11:
1790 case 12:
1791 track->cb[0].cpp = 1;
e024e110 1792 break;
551ebd83
DA		 1793 case 3:
1794 case 4:
1795 case 15:
1796 track->cb[0].cpp = 2;
1797 break;
1798 case 6:
1799 track->cb[0].cpp = 4;
1800 break;
1801 default:
1802 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1803 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1804 return -EINVAL;
1805 }
513bcb46 1806 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
40b4a759
MO		 1807 track->cb_dirty = true;
1808 track->zb_dirty = true;
551ebd83
DA		 1809 break;
1810 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1811 switch (idx_value & 0xf) {
551ebd83
DA		 1812 case 0:
1813 track->zb.cpp = 2;
1814 break;
1815 case 2:
1816 case 3:
1817 case 4:
1818 case 5:
1819 case 9:
1820 case 11:
1821 track->zb.cpp = 4;
17782d99 1822 break;
771fe6b9 1823 default:
771fe6b9
JG		 1824 break;
1825 }
40b4a759 1826 track->zb_dirty = true;
551ebd83
DA		 1827 break;
1828 case RADEON_RB3D_ZPASS_ADDR:
1829 r = r100_cs_packet_next_reloc(p, &reloc);
1830 if (r) {
1831 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1832 idx, reg);
1833 r100_cs_dump_packet(p, pkt);
1834 return r;
1835 }
513bcb46 1836 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1837 break;
1838 case RADEON_PP_CNTL:
1839 {
513bcb46 1840 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1841 for (i = 0; i < track->num_texture; i++)
1842 track->textures[i].enabled = !!(temp & (1 << i));
40b4a759 1843 track->tex_dirty = true;
551ebd83
DA		 1844 }
1845 break;
1846 case RADEON_SE_VF_CNTL:
513bcb46 1847 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1848 break;
1849 case RADEON_SE_VTX_FMT:
513bcb46 1850 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1851 break;
1852 case RADEON_PP_TEX_SIZE_0:
1853 case RADEON_PP_TEX_SIZE_1:
1854 case RADEON_PP_TEX_SIZE_2:
1855 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1856 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1857 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
40b4a759 1858 track->tex_dirty = true;
551ebd83
DA		 1859 break;
1860 case RADEON_PP_TEX_PITCH_0:
1861 case RADEON_PP_TEX_PITCH_1:
1862 case RADEON_PP_TEX_PITCH_2:
1863 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1864 track->textures[i].pitch = idx_value + 32;
40b4a759 1865 track->tex_dirty = true;
551ebd83
DA		 1866 break;
1867 case RADEON_PP_TXFILTER_0:
1868 case RADEON_PP_TXFILTER_1:
1869 case RADEON_PP_TXFILTER_2:
1870 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1871 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1872 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1873 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1874 if (tmp == 2 || tmp == 6)
1875 track->textures[i].roundup_w = false;
513bcb46 1876 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1877 if (tmp == 2 || tmp == 6)
1878 track->textures[i].roundup_h = false;
40b4a759 1879 track->tex_dirty = true;
551ebd83
DA		 1880 break;
1881 case RADEON_PP_TXFORMAT_0:
1882 case RADEON_PP_TXFORMAT_1:
1883 case RADEON_PP_TXFORMAT_2:
1884 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1885 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1886 track->textures[i].use_pitch = 1;
1887 } else {
1888 track->textures[i].use_pitch = 0;
513bcb46
DA		 1889 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1890 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1891 }
513bcb46 1892 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1893 track->textures[i].tex_coord_type = 2;
513bcb46 1894 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1895 case RADEON_TXFORMAT_I8:
1896 case RADEON_TXFORMAT_RGB332:
1897 case RADEON_TXFORMAT_Y8:
1898 track->textures[i].cpp = 1;
f9da52d5 1899 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1900 break;
1901 case RADEON_TXFORMAT_AI88:
1902 case RADEON_TXFORMAT_ARGB1555:
1903 case RADEON_TXFORMAT_RGB565:
1904 case RADEON_TXFORMAT_ARGB4444:
1905 case RADEON_TXFORMAT_VYUY422:
1906 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1907 case RADEON_TXFORMAT_SHADOW16:
1908 case RADEON_TXFORMAT_LDUDV655:
1909 case RADEON_TXFORMAT_DUDV88:
1910 track->textures[i].cpp = 2;
f9da52d5 1911 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1912 break;
551ebd83
DA		 1913 case RADEON_TXFORMAT_ARGB8888:
1914 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1915 case RADEON_TXFORMAT_SHADOW32:
1916 case RADEON_TXFORMAT_LDUDUV8888:
1917 track->textures[i].cpp = 4;
f9da52d5 1918 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1919 break;
d785d78b
DA		 1920 case RADEON_TXFORMAT_DXT1:
1921 track->textures[i].cpp = 1;
1922 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1923 break;
1924 case RADEON_TXFORMAT_DXT23:
1925 case RADEON_TXFORMAT_DXT45:
1926 track->textures[i].cpp = 1;
1927 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1928 break;
551ebd83 1929 }
513bcb46
DA		 1930 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1931 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
40b4a759 1932 track->tex_dirty = true;
551ebd83
DA		 1933 break;
1934 case RADEON_PP_CUBIC_FACES_0:
1935 case RADEON_PP_CUBIC_FACES_1:
1936 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1937 tmp = idx_value;
551ebd83
DA		 1938 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1939 for (face = 0; face < 4; face++) {
1940 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1941 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1942 }
40b4a759 1943 track->tex_dirty = true;
551ebd83
DA		 1944 break;
1945 default:
1946 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1947 reg, idx);
1948 return -EINVAL;
771fe6b9
JG		 1949 }
1950 return 0;
1951}
1952
068a117c
JG		 1953int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1954 struct radeon_cs_packet *pkt,
4c788679 1955 struct radeon_bo *robj)
068a117c 1956{
068a117c 1957 unsigned idx;
513bcb46 1958 u32 value;
068a117c 1959 idx = pkt->idx + 1;
513bcb46 1960 value = radeon_get_ib_value(p, idx + 2);
4c788679 1961 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1962 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1963 "(need %u have %lu) !\n",
513bcb46 1964 value + 1,
4c788679 1965 radeon_bo_size(robj));
068a117c
JG		 1966 return -EINVAL;
1967 }
1968 return 0;
1969}
1970
771fe6b9
JG		 1971static int r100_packet3_check(struct radeon_cs_parser *p,
1972 struct radeon_cs_packet *pkt)
1973{
771fe6b9 1974 struct radeon_cs_reloc *reloc;
551ebd83 1975 struct r100_cs_track *track;
771fe6b9 1976 unsigned idx;
771fe6b9
JG		 1977 volatile uint32_t *ib;
1978 int r;
1979
f2e39221 1980 ib = p->ib.ptr;
771fe6b9 1981 idx = pkt->idx + 1;
551ebd83 1982 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1983 switch (pkt->opcode) {
1984 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1985 r = r100_packet3_load_vbpntr(p, pkt, idx);
1986 if (r)
1987 return r;
771fe6b9
JG		 1988 break;
1989 case PACKET3_INDX_BUFFER:
1990 r = r100_cs_packet_next_reloc(p, &reloc);
1991 if (r) {
1992 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1993 r100_cs_dump_packet(p, pkt);
1994 return r;
1995 }
513bcb46 1996 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1997 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1998 if (r) {
1999 return r;
2000 }
771fe6b9
JG		 2001 break;
2002 case 0x23:
771fe6b9
JG		 2003 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
2004 r = r100_cs_packet_next_reloc(p, &reloc);
2005 if (r) {
2006 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
2007 r100_cs_dump_packet(p, pkt);
2008 return r;
2009 }
513bcb46 2010 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 2011 track->num_arrays = 1;
513bcb46 2012 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 2013
2014 track->arrays[0].robj = reloc->robj;
2015 track->arrays[0].esize = track->vtx_size;
2016
513bcb46 2017 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 2018
513bcb46 2019 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 2020 track->immd_dwords = pkt->count - 1;
2021 r = r100_cs_track_check(p->rdev, track);
2022 if (r)
2023 return r;
771fe6b9
JG		 2024 break;
2025 case PACKET3_3D_DRAW_IMMD:
513bcb46 2026 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 2027 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
2028 return -EINVAL;
2029 }
cf57fc7a 2030 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 2031 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 2032 track->immd_dwords = pkt->count - 1;
2033 r = r100_cs_track_check(p->rdev, track);
2034 if (r)
2035 return r;
2036 break;
771fe6b9
JG		 2037 /* triggers drawing using in-packet vertex data */
2038 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 2039 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 2040 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
2041 return -EINVAL;
2042 }
513bcb46 2043 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 2044 track->immd_dwords = pkt->count;
2045 r = r100_cs_track_check(p->rdev, track);
2046 if (r)
2047 return r;
2048 break;
771fe6b9
JG		 2049 /* triggers drawing using in-packet vertex data */
2050 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 2051 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 2052 r = r100_cs_track_check(p->rdev, track);
2053 if (r)
2054 return r;
2055 break;
771fe6b9
JG		 2056 /* triggers drawing of vertex buffers setup elsewhere */
2057 case PACKET3_3D_DRAW_INDX_2:
513bcb46 2058 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 2059 r = r100_cs_track_check(p->rdev, track);
2060 if (r)
2061 return r;
2062 break;
771fe6b9
JG		 2063 /* triggers drawing using indices to vertex buffer */
2064 case PACKET3_3D_DRAW_VBUF:
513bcb46 2065 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 2066 r = r100_cs_track_check(p->rdev, track);
2067 if (r)
2068 return r;
2069 break;
771fe6b9
JG		 2070 /* triggers drawing of vertex buffers setup elsewhere */
2071 case PACKET3_3D_DRAW_INDX:
513bcb46 2072 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 2073 r = r100_cs_track_check(p->rdev, track);
2074 if (r)
2075 return r;
2076 break;
771fe6b9 2077 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 2078 case PACKET3_3D_CLEAR_HIZ:
2079 case PACKET3_3D_CLEAR_ZMASK:
2080 if (p->rdev->hyperz_filp != p->filp)
2081 return -EINVAL;
2082 break;
771fe6b9
JG		 2083 case PACKET3_NOP:
2084 break;
2085 default:
2086 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2087 return -EINVAL;
2088 }
2089 return 0;
2090}
2091
2092int r100_cs_parse(struct radeon_cs_parser *p)
2093{
2094 struct radeon_cs_packet pkt;
9f022ddf 2095 struct r100_cs_track *track;
771fe6b9
JG		 2096 int r;
2097
9f022ddf 2098 track = kzalloc(sizeof(*track), GFP_KERNEL);
ce067913
DC		 2099 if (!track)
2100 return -ENOMEM;
9f022ddf
JG		 2101 r100_cs_track_clear(p->rdev, track);
2102 p->track = track;
771fe6b9
JG		 2103 do {
2104 r = r100_cs_packet_parse(p, &pkt, p->idx);
2105 if (r) {
2106 return r;
2107 }
2108 p->idx += pkt.count + 2;
2109 switch (pkt.type) {
068a117c 2110 case PACKET_TYPE0:
551ebd83
DA		 2111 if (p->rdev->family >= CHIP_R200)
2112 r = r100_cs_parse_packet0(p, &pkt,
2113 p->rdev->config.r100.reg_safe_bm,
2114 p->rdev->config.r100.reg_safe_bm_size,
2115 &r200_packet0_check);
2116 else
2117 r = r100_cs_parse_packet0(p, &pkt,
2118 p->rdev->config.r100.reg_safe_bm,
2119 p->rdev->config.r100.reg_safe_bm_size,
2120 &r100_packet0_check);
068a117c
JG		 2121 break;
2122 case PACKET_TYPE2:
2123 break;
2124 case PACKET_TYPE3:
2125 r = r100_packet3_check(p, &pkt);
2126 break;
2127 default:
2128 DRM_ERROR("Unknown packet type %d !\n",
2129 pkt.type);
2130 return -EINVAL;
771fe6b9
JG		 2131 }
2132 if (r) {
2133 return r;
2134 }
2135 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2136 return 0;
2137}
2138
0242f74d 2139static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
771fe6b9 2140{
0242f74d
AD		 2141 DRM_ERROR("pitch %d\n", t->pitch);
2142 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2143 DRM_ERROR("width %d\n", t->width);
2144 DRM_ERROR("width_11 %d\n", t->width_11);
2145 DRM_ERROR("height %d\n", t->height);
2146 DRM_ERROR("height_11 %d\n", t->height_11);
2147 DRM_ERROR("num levels %d\n", t->num_levels);
2148 DRM_ERROR("depth %d\n", t->txdepth);
2149 DRM_ERROR("bpp %d\n", t->cpp);
2150 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2151 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2152 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2153 DRM_ERROR("compress format %d\n", t->compress_format);
771fe6b9
JG		 2154}
2155
0242f74d 2156static int r100_track_compress_size(int compress_format, int w, int h)
771fe6b9 2157{
0242f74d
AD		 2158 int block_width, block_height, block_bytes;
2159 int wblocks, hblocks;
2160 int min_wblocks;
2161 int sz;
771fe6b9 2162
0242f74d
AD		 2163 block_width = 4;
2164 block_height = 4;
2165
2166 switch (compress_format) {
2167 case R100_TRACK_COMP_DXT1:
2168 block_bytes = 8;
2169 min_wblocks = 4;
2170 break;
2171 default:
2172 case R100_TRACK_COMP_DXT35:
2173 block_bytes = 16;
2174 min_wblocks = 2;
2175 break;
771fe6b9 2176 }
0242f74d
AD		 2177
2178 hblocks = (h + block_height - 1) / block_height;
2179 wblocks = (w + block_width - 1) / block_width;
2180 if (wblocks < min_wblocks)
2181 wblocks = min_wblocks;
2182 sz = wblocks * hblocks * block_bytes;
2183 return sz;
771fe6b9
JG		 2184}
2185
0242f74d
AD		 2186static int r100_cs_track_cube(struct radeon_device *rdev,
2187 struct r100_cs_track *track, unsigned idx)
771fe6b9 2188{
0242f74d
AD		 2189 unsigned face, w, h;
2190 struct radeon_bo *cube_robj;
2191 unsigned long size;
2192 unsigned compress_format = track->textures[idx].compress_format;
771fe6b9 2193
0242f74d
AD		 2194 for (face = 0; face < 5; face++) {
2195 cube_robj = track->textures[idx].cube_info[face].robj;
2196 w = track->textures[idx].cube_info[face].width;
2197 h = track->textures[idx].cube_info[face].height;
771fe6b9 2198
0242f74d
AD		 2199 if (compress_format) {
2200 size = r100_track_compress_size(compress_format, w, h);
2201 } else
2202 size = w * h;
2203 size *= track->textures[idx].cpp;
2204
2205 size += track->textures[idx].cube_info[face].offset;
2206
2207 if (size > radeon_bo_size(cube_robj)) {
2208 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2209 size, radeon_bo_size(cube_robj));
2210 r100_cs_track_texture_print(&track->textures[idx]);
2211 return -1;
771fe6b9 2212 }
771fe6b9 2213 }
0242f74d 2214 return 0;
771fe6b9
JG		 2215}
2216
0242f74d
AD		 2217static int r100_cs_track_texture_check(struct radeon_device *rdev,
2218 struct r100_cs_track *track)
771fe6b9 2219{
0242f74d
AD		 2220 struct radeon_bo *robj;
2221 unsigned long size;
2222 unsigned u, i, w, h, d;
2223 int ret;
771fe6b9 2224
0242f74d
AD		 2225 for (u = 0; u < track->num_texture; u++) {
2226 if (!track->textures[u].enabled)
2227 continue;
2228 if (track->textures[u].lookup_disable)
2229 continue;
2230 robj = track->textures[u].robj;
2231 if (robj == NULL) {
2232 DRM_ERROR("No texture bound to unit %u\n", u);
2233 return -EINVAL;
771fe6b9 2234 }
0242f74d
AD		 2235 size = 0;
2236 for (i = 0; i <= track->textures[u].num_levels; i++) {
2237 if (track->textures[u].use_pitch) {
2238 if (rdev->family < CHIP_R300)
2239 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2240 else
2241 w = track->textures[u].pitch / (1 << i);
2242 } else {
2243 w = track->textures[u].width;
2244 if (rdev->family >= CHIP_RV515)
2245 w |= track->textures[u].width_11;
2246 w = w / (1 << i);
2247 if (track->textures[u].roundup_w)
2248 w = roundup_pow_of_two(w);
2249 }
2250 h = track->textures[u].height;
2251 if (rdev->family >= CHIP_RV515)
2252 h |= track->textures[u].height_11;
2253 h = h / (1 << i);
2254 if (track->textures[u].roundup_h)
2255 h = roundup_pow_of_two(h);
2256 if (track->textures[u].tex_coord_type == 1) {
2257 d = (1 << track->textures[u].txdepth) / (1 << i);
2258 if (!d)
2259 d = 1;
2260 } else {
2261 d = 1;
2262 }
2263 if (track->textures[u].compress_format) {
771fe6b9 2264
0242f74d
AD		 2265 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2266 /* compressed textures are block based */
2267 } else
2268 size += w * h * d;
2269 }
2270 size *= track->textures[u].cpp;
771fe6b9 2271
0242f74d
AD		 2272 switch (track->textures[u].tex_coord_type) {
2273 case 0:
2274 case 1:
2275 break;
2276 case 2:
2277 if (track->separate_cube) {
2278 ret = r100_cs_track_cube(rdev, track, u);
2279 if (ret)
2280 return ret;
2281 } else
2282 size *= 6;
2283 break;
2284 default:
2285 DRM_ERROR("Invalid texture coordinate type %u for unit "
2286 "%u\n", track->textures[u].tex_coord_type, u);
2287 return -EINVAL;
2288 }
2289 if (size > radeon_bo_size(robj)) {
2290 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2291 "%lu\n", u, size, radeon_bo_size(robj));
2292 r100_cs_track_texture_print(&track->textures[u]);
2293 return -EINVAL;
771fe6b9 2294 }
771fe6b9 2295 }
0242f74d 2296 return 0;
771fe6b9
JG		 2297}
2298
0242f74d 2299int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
771fe6b9
JG		 2300{
2301 unsigned i;
0242f74d
AD		 2302 unsigned long size;
2303 unsigned prim_walk;
2304 unsigned nverts;
2305 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
771fe6b9 2306
0242f74d
AD		 2307 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2308 !track->blend_read_enable)
2309 num_cb = 0;
2310
2311 for (i = 0; i < num_cb; i++) {
2312 if (track->cb[i].robj == NULL) {
2313 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2314 return -EINVAL;
2315 }
2316 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2317 size += track->cb[i].offset;
2318 if (size > radeon_bo_size(track->cb[i].robj)) {
2319 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2320 "(need %lu have %lu) !\n", i, size,
2321 radeon_bo_size(track->cb[i].robj));
2322 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2323 i, track->cb[i].pitch, track->cb[i].cpp,
2324 track->cb[i].offset, track->maxy);
2325 return -EINVAL;
771fe6b9 2326 }
771fe6b9 2327 }
0242f74d 2328 track->cb_dirty = false;
771fe6b9 2329
0242f74d
AD		 2330 if (track->zb_dirty && track->z_enabled) {
2331 if (track->zb.robj == NULL) {
2332 DRM_ERROR("[drm] No buffer for z buffer !\n");
2333 return -EINVAL;
2334 }
2335 size = track->zb.pitch * track->zb.cpp * track->maxy;
2336 size += track->zb.offset;
2337 if (size > radeon_bo_size(track->zb.robj)) {
2338 DRM_ERROR("[drm] Buffer too small for z buffer "
2339 "(need %lu have %lu) !\n", size,
2340 radeon_bo_size(track->zb.robj));
2341 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2342 track->zb.pitch, track->zb.cpp,
2343 track->zb.offset, track->maxy);
2344 return -EINVAL;
2345 }
225758d8 2346 }
0242f74d 2347 track->zb_dirty = false;
771fe6b9 2348
0242f74d
AD		 2349 if (track->aa_dirty && track->aaresolve) {
2350 if (track->aa.robj == NULL) {
2351 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2352 return -EINVAL;
2353 }
2354 /* I believe the format comes from colorbuffer0. */
2355 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2356 size += track->aa.offset;
2357 if (size > radeon_bo_size(track->aa.robj)) {
2358 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2359 "(need %lu have %lu) !\n", i, size,
2360 radeon_bo_size(track->aa.robj));
2361 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2362 i, track->aa.pitch, track->cb[0].cpp,
2363 track->aa.offset, track->maxy);
2364 return -EINVAL;
2365 }
2366 }
2367 track->aa_dirty = false;
771fe6b9 2368
0242f74d
AD		 2369 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2370 if (track->vap_vf_cntl & (1 << 14)) {
2371 nverts = track->vap_alt_nverts;
2372 } else {
2373 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2739d49c 2374 }
0242f74d
AD		 2375 switch (prim_walk) {
2376 case 1:
2377 for (i = 0; i < track->num_arrays; i++) {
2378 size = track->arrays[i].esize * track->max_indx * 4;
2379 if (track->arrays[i].robj == NULL) {
2380 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2381 "bound\n", prim_walk, i);
2382 return -EINVAL;
2383 }
2384 if (size > radeon_bo_size(track->arrays[i].robj)) {
2385 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2386 "need %lu dwords have %lu dwords\n",
2387 prim_walk, i, size >> 2,
2388 radeon_bo_size(track->arrays[i].robj)
2389 >> 2);
2390 DRM_ERROR("Max indices %u\n", track->max_indx);
2391 return -EINVAL;
2392 }
771fe6b9 2393 }
0242f74d
AD		 2394 break;
2395 case 2:
2396 for (i = 0; i < track->num_arrays; i++) {
2397 size = track->arrays[i].esize * (nverts - 1) * 4;
2398 if (track->arrays[i].robj == NULL) {
2399 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2400 "bound\n", prim_walk, i);
2401 return -EINVAL;
2402 }
2403 if (size > radeon_bo_size(track->arrays[i].robj)) {
2404 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2405 "need %lu dwords have %lu dwords\n",
2406 prim_walk, i, size >> 2,
2407 radeon_bo_size(track->arrays[i].robj)
2408 >> 2);
2409 return -EINVAL;
2410 }
771fe6b9 2411 }
0242f74d
AD		 2412 break;
2413 case 3:
2414 size = track->vtx_size * nverts;
2415 if (size != track->immd_dwords) {
2416 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2417 track->immd_dwords, size);
2418 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2419 nverts, track->vtx_size);
2420 return -EINVAL;
771fe6b9 2421 }
0242f74d
AD		 2422 break;
2423 default:
2424 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2425 prim_walk);
2426 return -EINVAL;
2a0f8918
DA		 2427 }
2428
0242f74d
AD		 2429 if (track->tex_dirty) {
2430 track->tex_dirty = false;
2431 return r100_cs_track_texture_check(rdev, track);
2a0f8918 2432 }
0242f74d 2433 return 0;
2a0f8918
DA		 2434}
2435
0242f74d 2436void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2a0f8918 2437{
0242f74d 2438 unsigned i, face;
2a0f8918 2439
0242f74d
AD		 2440 track->cb_dirty = true;
2441 track->zb_dirty = true;
2442 track->tex_dirty = true;
2443 track->aa_dirty = true;
b7d8cce5 2444
0242f74d
AD		 2445 if (rdev->family < CHIP_R300) {
2446 track->num_cb = 1;
2447 if (rdev->family <= CHIP_RS200)
2448 track->num_texture = 3;
7a50f01a 2449 else
0242f74d
AD		 2450 track->num_texture = 6;
2451 track->maxy = 2048;
2452 track->separate_cube = 1;
28d52043 2453 } else {
0242f74d
AD		 2454 track->num_cb = 4;
2455 track->num_texture = 16;
2456 track->maxy = 4096;
2457 track->separate_cube = 0;
2458 track->aaresolve = false;
2459 track->aa.robj = NULL;
28d52043 2460 }
2a0f8918 2461
0242f74d
AD		 2462 for (i = 0; i < track->num_cb; i++) {
2463 track->cb[i].robj = NULL;
2464 track->cb[i].pitch = 8192;
2465 track->cb[i].cpp = 16;
2466 track->cb[i].offset = 0;
771fe6b9 2467 }
0242f74d
AD		 2468 track->z_enabled = true;
2469 track->zb.robj = NULL;
2470 track->zb.pitch = 8192;
2471 track->zb.cpp = 4;
2472 track->zb.offset = 0;
2473 track->vtx_size = 0x7F;
2474 track->immd_dwords = 0xFFFFFFFFUL;
2475 track->num_arrays = 11;
2476 track->max_indx = 0x00FFFFFFUL;
2477 for (i = 0; i < track->num_arrays; i++) {
2478 track->arrays[i].robj = NULL;
2479 track->arrays[i].esize = 0x7F;
771fe6b9 2480 }
0242f74d
AD		 2481 for (i = 0; i < track->num_texture; i++) {
2482 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2483 track->textures[i].pitch = 16536;
2484 track->textures[i].width = 16536;
2485 track->textures[i].height = 16536;
2486 track->textures[i].width_11 = 1 << 11;
2487 track->textures[i].height_11 = 1 << 11;
2488 track->textures[i].num_levels = 12;
2489 if (rdev->family <= CHIP_RS200) {
2490 track->textures[i].tex_coord_type = 0;
2491 track->textures[i].txdepth = 0;
2492 } else {
2493 track->textures[i].txdepth = 16;
2494 track->textures[i].tex_coord_type = 1;
2495 }
2496 track->textures[i].cpp = 64;
2497 track->textures[i].robj = NULL;
2498 /* CS IB emission code makes sure texture unit are disabled */
2499 track->textures[i].enabled = false;
2500 track->textures[i].lookup_disable = false;
2501 track->textures[i].roundup_w = true;
2502 track->textures[i].roundup_h = true;
2503 if (track->separate_cube)
2504 for (face = 0; face < 5; face++) {
2505 track->textures[i].cube_info[face].robj = NULL;
2506 track->textures[i].cube_info[face].width = 16536;
2507 track->textures[i].cube_info[face].height = 16536;
2508 track->textures[i].cube_info[face].offset = 0;
2509 }
771fe6b9
JG		 2510 }
2511}
2512
0242f74d
AD		 2513/*
2514 * Global GPU functions
2515 */
1109ca09 2516static void r100_errata(struct radeon_device *rdev)
771fe6b9 2517{
0242f74d 2518 rdev->pll_errata = 0;
771fe6b9 2519
0242f74d
AD		 2520 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2521 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2522 }
771fe6b9 2523
0242f74d
AD		 2524 if (rdev->family == CHIP_RV100 ||
2525 rdev->family == CHIP_RS100 ||
2526 rdev->family == CHIP_RS200) {
2527 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2528 }
771fe6b9
JG		 2529}
2530
0242f74d 2531/* Wait for vertical sync on primary CRTC */
1109ca09 2532static void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
068a117c 2533{
0242f74d
AD		 2534 uint32_t crtc_gen_cntl, tmp;
2535 int i;
2536
2537 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2538 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2539 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2540 return;
2541 }
2542 /* Clear the CRTC_VBLANK_SAVE bit */
2543 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2544 for (i = 0; i < rdev->usec_timeout; i++) {
2545 tmp = RREG32(RADEON_CRTC_STATUS);
2546 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2547 return;
2548 }
2549 DRM_UDELAY(1);
551ebd83 2550 }
068a117c
JG		 2551}
2552
0242f74d 2553/* Wait for vertical sync on secondary CRTC */
1109ca09 2554static void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
771fe6b9 2555{
0242f74d
AD		 2556 uint32_t crtc2_gen_cntl, tmp;
2557 int i;
771fe6b9 2558
0242f74d
AD		 2559 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2560 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2561 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2562 return;
2563
2564 /* Clear the CRTC_VBLANK_SAVE bit */
2565 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2566 for (i = 0; i < rdev->usec_timeout; i++) {
2567 tmp = RREG32(RADEON_CRTC2_STATUS);
2568 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2569 return;
2570 }
2571 DRM_UDELAY(1);
771fe6b9 2572 }
771fe6b9
JG		 2573}
2574
1109ca09 2575static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
771fe6b9 2576{
0242f74d
AD		 2577 unsigned i;
2578 uint32_t tmp;
771fe6b9 2579
0242f74d
AD		 2580 for (i = 0; i < rdev->usec_timeout; i++) {
2581 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2582 if (tmp >= n) {
2583 return 0;
2584 }
2585 DRM_UDELAY(1);
771fe6b9 2586 }
0242f74d 2587 return -1;
771fe6b9
JG		 2588}
2589
0242f74d 2590int r100_gui_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2591{
771fe6b9 2592 unsigned i;
0242f74d 2593 uint32_t tmp;
771fe6b9 2594
0242f74d
AD		 2595 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2596 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2597 " Bad things might happen.\n");
771fe6b9 2598 }
0242f74d
AD		 2599 for (i = 0; i < rdev->usec_timeout; i++) {
2600 tmp = RREG32(RADEON_RBBM_STATUS);
2601 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2602 return 0;
2603 }
2604 DRM_UDELAY(1);
771fe6b9 2605 }
0242f74d 2606 return -1;
771fe6b9
JG		 2607}
2608
0242f74d 2609int r100_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2610{
0242f74d 2611 unsigned i;
771fe6b9
JG		 2612 uint32_t tmp;
2613
0242f74d
AD		 2614 for (i = 0; i < rdev->usec_timeout; i++) {
2615 /* read MC_STATUS */
2616 tmp = RREG32(RADEON_MC_STATUS);
2617 if (tmp & RADEON_MC_IDLE) {
2618 return 0;
2619 }
2620 DRM_UDELAY(1);
2621 }
2622 return -1;
771fe6b9
JG		 2623}
2624
0242f74d 2625bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9 2626{
0242f74d 2627 u32 rbbm_status;
771fe6b9 2628
0242f74d
AD		 2629 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2630 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2631 radeon_ring_lockup_update(ring);
2632 return false;
2633 }
2634 /* force CP activities */
2635 radeon_ring_force_activity(rdev, ring);
2636 return radeon_ring_test_lockup(rdev, ring);
771fe6b9
JG		 2637}
2638
74da01dc
AD		 2639/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2640void r100_enable_bm(struct radeon_device *rdev)
2641{
2642 uint32_t tmp;
2643 /* Enable bus mastering */
2644 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2645 WREG32(RADEON_BUS_CNTL, tmp);
2646}
2647
0242f74d 2648void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2649{
0242f74d
AD		 2650 u32 tmp;
2651
2652 /* disable bus mastering */
2653 tmp = RREG32(R_000030_BUS_CNTL);
2654 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2655 mdelay(1);
2656 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2657 mdelay(1);
2658 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2659 tmp = RREG32(RADEON_BUS_CNTL);
2660 mdelay(1);
2661 pci_clear_master(rdev->pdev);
2662 mdelay(1);
771fe6b9 2663}
e024e110 2664
0242f74d 2665int r100_asic_reset(struct radeon_device *rdev)
e024e110 2666{
0242f74d
AD		 2667 struct r100_mc_save save;
2668 u32 status, tmp;
2669 int ret = 0;
e024e110 2670
0242f74d
AD		 2671 status = RREG32(R_000E40_RBBM_STATUS);
2672 if (!G_000E40_GUI_ACTIVE(status)) {
2673 return 0;
e024e110 2674 }
0242f74d
AD		 2675 r100_mc_stop(rdev, &save);
2676 status = RREG32(R_000E40_RBBM_STATUS);
2677 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2678 /* stop CP */
2679 WREG32(RADEON_CP_CSQ_CNTL, 0);
2680 tmp = RREG32(RADEON_CP_RB_CNTL);
2681 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2682 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2683 WREG32(RADEON_CP_RB_WPTR, 0);
2684 WREG32(RADEON_CP_RB_CNTL, tmp);
2685 /* save PCI state */
2686 pci_save_state(rdev->pdev);
2687 /* disable bus mastering */
2688 r100_bm_disable(rdev);
2689 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2690 S_0000F0_SOFT_RESET_RE(1) |
2691 S_0000F0_SOFT_RESET_PP(1) |
2692 S_0000F0_SOFT_RESET_RB(1));
2693 RREG32(R_0000F0_RBBM_SOFT_RESET);
2694 mdelay(500);
2695 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2696 mdelay(1);
2697 status = RREG32(R_000E40_RBBM_STATUS);
2698 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2699 /* reset CP */
2700 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2701 RREG32(R_0000F0_RBBM_SOFT_RESET);
2702 mdelay(500);
2703 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2704 mdelay(1);
2705 status = RREG32(R_000E40_RBBM_STATUS);
2706 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2707 /* restore PCI & busmastering */
2708 pci_restore_state(rdev->pdev);
2709 r100_enable_bm(rdev);
2710 /* Check if GPU is idle */
2711 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2712 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2713 dev_err(rdev->dev, "failed to reset GPU\n");
2714 ret = -1;
2715 } else
2716 dev_info(rdev->dev, "GPU reset succeed\n");
2717 r100_mc_resume(rdev, &save);
2718 return ret;
2719}
e024e110 2720
0242f74d
AD		 2721void r100_set_common_regs(struct radeon_device *rdev)
2722{
2723 struct drm_device *dev = rdev->ddev;
2724 bool force_dac2 = false;
2725 u32 tmp;
f5c5f040 2726
0242f74d
AD		 2727 /* set these so they don't interfere with anything */
2728 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2729 WREG32(RADEON_SUBPIC_CNTL, 0);
2730 WREG32(RADEON_VIPH_CONTROL, 0);
2731 WREG32(RADEON_I2C_CNTL_1, 0);
2732 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2733 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2734 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
f5c5f040 2735
0242f74d
AD		 2736 /* always set up dac2 on rn50 and some rv100 as lots
2737 * of servers seem to wire it up to a VGA port but
2738 * don't report it in the bios connector
2739 * table.
2740 */
2741 switch (dev->pdev->device) {
2742 /* RN50 */
2743 case 0x515e:
2744 case 0x5969:
2745 force_dac2 = true;
2746 break;
2747 /* RV100*/
2748 case 0x5159:
2749 case 0x515a:
2750 /* DELL triple head servers */
2751 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2752 ((dev->pdev->subsystem_device == 0x016c) ||
2753 (dev->pdev->subsystem_device == 0x016d) ||
2754 (dev->pdev->subsystem_device == 0x016e) ||
2755 (dev->pdev->subsystem_device == 0x016f) ||
2756 (dev->pdev->subsystem_device == 0x0170) ||
2757 (dev->pdev->subsystem_device == 0x017d) ||
2758 (dev->pdev->subsystem_device == 0x017e) ||
2759 (dev->pdev->subsystem_device == 0x0183) ||
2760 (dev->pdev->subsystem_device == 0x018a) ||
2761 (dev->pdev->subsystem_device == 0x019a)))
2762 force_dac2 = true;
2763 break;
2764 }
f5c5f040 2765
0242f74d
AD		 2766 if (force_dac2) {
2767 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2768 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2769 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
e024e110 2770
0242f74d
AD		 2771 /* For CRT on DAC2, don't turn it on if BIOS didn't
2772 enable it, even it's detected.
2773 */
c93bb85b 2774
0242f74d
AD		 2775 /* force it to crtc0 */
2776 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2777 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2778 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
c93bb85b 2779
0242f74d
AD		 2780 /* set up the TV DAC */
2781 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2782 RADEON_TV_DAC_STD_MASK |
2783 RADEON_TV_DAC_RDACPD |
2784 RADEON_TV_DAC_GDACPD |
2785 RADEON_TV_DAC_BDACPD |
2786 RADEON_TV_DAC_BGADJ_MASK |
2787 RADEON_TV_DAC_DACADJ_MASK);
2788 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2789 RADEON_TV_DAC_NHOLD |
2790 RADEON_TV_DAC_STD_PS2 |
2791 (0x58 << 16));
f46c0120 2792
0242f74d
AD		 2793 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2794 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2795 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
c93bb85b 2796 }
0242f74d
AD		 2797
2798 /* switch PM block to ACPI mode */
2799 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2800 tmp &= ~RADEON_PM_MODE_SEL;
2801 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2802
2803}
2804
2805/*
2806 * VRAM info
2807 */
2808static void r100_vram_get_type(struct radeon_device *rdev)
2809{
2810 uint32_t tmp;
2811
2812 rdev->mc.vram_is_ddr = false;
2813 if (rdev->flags & RADEON_IS_IGP)
2814 rdev->mc.vram_is_ddr = true;
2815 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2816 rdev->mc.vram_is_ddr = true;
2817 if ((rdev->family == CHIP_RV100) ||
2818 (rdev->family == CHIP_RS100) ||
2819 (rdev->family == CHIP_RS200)) {
2820 tmp = RREG32(RADEON_MEM_CNTL);
2821 if (tmp & RV100_HALF_MODE) {
2822 rdev->mc.vram_width = 32;
2823 } else {
2824 rdev->mc.vram_width = 64;
2825 }
2826 if (rdev->flags & RADEON_SINGLE_CRTC) {
2827 rdev->mc.vram_width /= 4;
2828 rdev->mc.vram_is_ddr = true;
dfee5614 2829 }
0242f74d
AD		 2830 } else if (rdev->family <= CHIP_RV280) {
2831 tmp = RREG32(RADEON_MEM_CNTL);
2832 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2833 rdev->mc.vram_width = 128;
2834 } else {
2835 rdev->mc.vram_width = 64;
2836 }
2837 } else {
2838 /* newer IGPs */
2839 rdev->mc.vram_width = 128;
c93bb85b 2840 }
0242f74d 2841}
c93bb85b 2842
0242f74d
AD		 2843static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2844{
2845 u32 aper_size;
2846 u8 byte;
2847
2848 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2849
2850 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2851 * that is has the 2nd generation multifunction PCI interface
2852 */
2853 if (rdev->family == CHIP_RV280 ||
2854 rdev->family >= CHIP_RV350) {
2855 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2856 ~RADEON_HDP_APER_CNTL);
2857 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2858 return aper_size * 2;
c93bb85b
JG		 2859 }
2860
0242f74d
AD		 2861 /* Older cards have all sorts of funny issues to deal with. First
2862 * check if it's a multifunction card by reading the PCI config
2863 * header type... Limit those to one aperture size
c93bb85b 2864 */
0242f74d
AD		 2865 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2866 if (byte & 0x80) {
2867 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2868 DRM_INFO("Limiting VRAM to one aperture\n");
2869 return aper_size;
2870 }
c93bb85b 2871
0242f74d
AD		 2872 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2873 * have set it up. We don't write this as it's broken on some ASICs but
2874 * we expect the BIOS to have done the right thing (might be too optimistic...)
2875 */
2876 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2877 return aper_size * 2;
2878 return aper_size;
2879}
c93bb85b 2880
0242f74d
AD		 2881void r100_vram_init_sizes(struct radeon_device *rdev)
2882{
2883 u64 config_aper_size;
c93bb85b 2884
0242f74d
AD		 2885 /* work out accessible VRAM */
2886 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2887 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2888 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2889 /* FIXME we don't use the second aperture yet when we could use it */
2890 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2891 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2892 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2893 if (rdev->flags & RADEON_IS_IGP) {
2894 uint32_t tom;
2895 /* read NB_TOM to get the amount of ram stolen for the GPU */
2896 tom = RREG32(RADEON_NB_TOM);
2897 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2898 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2899 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2900 } else {
2901 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2902 /* Some production boards of m6 will report 0
2903 * if it's 8 MB
2904 */
2905 if (rdev->mc.real_vram_size == 0) {
2906 rdev->mc.real_vram_size = 8192 * 1024;
2907 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2908 }
2909 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2910 * Novell bug 204882 + along with lots of ubuntu ones
2911 */
2912 if (rdev->mc.aper_size > config_aper_size)
2913 config_aper_size = rdev->mc.aper_size;
2914
2915 if (config_aper_size > rdev->mc.real_vram_size)
2916 rdev->mc.mc_vram_size = config_aper_size;
2917 else
2918 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
c93bb85b 2919 }
0242f74d 2920}
c93bb85b 2921
0242f74d
AD		 2922void r100_vga_set_state(struct radeon_device *rdev, bool state)
2923{
2924 uint32_t temp;
2925
2926 temp = RREG32(RADEON_CONFIG_CNTL);
2927 if (state == false) {
2928 temp &= ~RADEON_CFG_VGA_RAM_EN;
2929 temp |= RADEON_CFG_VGA_IO_DIS;
2930 } else {
2931 temp &= ~RADEON_CFG_VGA_IO_DIS;
c93bb85b 2932 }
0242f74d
AD		 2933 WREG32(RADEON_CONFIG_CNTL, temp);
2934}
c93bb85b 2935
1109ca09 2936static void r100_mc_init(struct radeon_device *rdev)
0242f74d
AD		 2937{
2938 u64 base;
c93bb85b 2939
0242f74d
AD		 2940 r100_vram_get_type(rdev);
2941 r100_vram_init_sizes(rdev);
2942 base = rdev->mc.aper_base;
2943 if (rdev->flags & RADEON_IS_IGP)
2944 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2945 radeon_vram_location(rdev, &rdev->mc, base);
2946 rdev->mc.gtt_base_align = 0;
2947 if (!(rdev->flags & RADEON_IS_AGP))
2948 radeon_gtt_location(rdev, &rdev->mc);
2949 radeon_update_bandwidth_info(rdev);
2950}
2951
2952
2953/*
2954 * Indirect registers accessor
2955 */
2956void r100_pll_errata_after_index(struct radeon_device *rdev)
2957{
2958 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2959 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2960 (void)RREG32(RADEON_CRTC_GEN_CNTL);
c93bb85b 2961 }
0242f74d 2962}
c93bb85b 2963
0242f74d
AD		 2964static void r100_pll_errata_after_data(struct radeon_device *rdev)
2965{
2966 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2967 * or the chip could hang on a subsequent access
2968 */
2969 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2970 mdelay(5);
c93bb85b
JG		 2971 }
2972
0242f74d
AD		 2973 /* This function is required to workaround a hardware bug in some (all?)
2974 * revisions of the R300. This workaround should be called after every
2975 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2976 * may not be correct.
2977 */
2978 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2979 uint32_t save, tmp;
c93bb85b 2980
0242f74d
AD		 2981 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2982 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2983 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2984 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2985 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
c93bb85b 2986 }
0242f74d 2987}
c93bb85b 2988
0242f74d
AD		 2989uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2990{
2991 uint32_t data;
c93bb85b 2992
0242f74d
AD		 2993 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2994 r100_pll_errata_after_index(rdev);
2995 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2996 r100_pll_errata_after_data(rdev);
2997 return data;
2998}
c93bb85b 2999
0242f74d
AD		 3000void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
3001{
3002 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
3003 r100_pll_errata_after_index(rdev);
3004 WREG32(RADEON_CLOCK_CNTL_DATA, v);
3005 r100_pll_errata_after_data(rdev);
3006}
3007
1109ca09 3008static void r100_set_safe_registers(struct radeon_device *rdev)
0242f74d
AD		 3009{
3010 if (ASIC_IS_RN50(rdev)) {
3011 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
3012 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
3013 } else if (rdev->family < CHIP_R200) {
3014 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
3015 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
c93bb85b 3016 } else {
0242f74d 3017 r200_set_safe_registers(rdev);
c93bb85b 3018 }
0242f74d 3019}
c93bb85b 3020
0242f74d
AD		 3021/*
3022 * Debugfs info
3023 */
3024#if defined(CONFIG_DEBUG_FS)
3025static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
3026{
3027 struct drm_info_node *node = (struct drm_info_node *) m->private;
3028 struct drm_device *dev = node->minor->dev;
3029 struct radeon_device *rdev = dev->dev_private;
3030 uint32_t reg, value;
3031 unsigned i;
c93bb85b 3032
0242f74d
AD		 3033 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
3034 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
3035 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3036 for (i = 0; i < 64; i++) {
3037 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
3038 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
3039 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
3040 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
3041 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
3042 }
3043 return 0;
3044}
c93bb85b 3045
0242f74d
AD		 3046static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
3047{
3048 struct drm_info_node *node = (struct drm_info_node *) m->private;
3049 struct drm_device *dev = node->minor->dev;
3050 struct radeon_device *rdev = dev->dev_private;
3051 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3052 uint32_t rdp, wdp;
3053 unsigned count, i, j;
c93bb85b 3054
0242f74d
AD		 3055 radeon_ring_free_size(rdev, ring);
3056 rdp = RREG32(RADEON_CP_RB_RPTR);
3057 wdp = RREG32(RADEON_CP_RB_WPTR);
3058 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
3059 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3060 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
3061 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
3062 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
3063 seq_printf(m, "%u dwords in ring\n", count);
3064 for (j = 0; j <= count; j++) {
3065 i = (rdp + j) & ring->ptr_mask;
3066 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
3067 }
3068 return 0;
3069}
c93bb85b 3070
c93bb85b 3071
0242f74d
AD		 3072static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
3073{
3074 struct drm_info_node *node = (struct drm_info_node *) m->private;
3075 struct drm_device *dev = node->minor->dev;
3076 struct radeon_device *rdev = dev->dev_private;
3077 uint32_t csq_stat, csq2_stat, tmp;
3078 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
3079 unsigned i;
c93bb85b 3080
0242f74d
AD		 3081 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3082 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
3083 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
3084 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
3085 r_rptr = (csq_stat >> 0) & 0x3ff;
3086 r_wptr = (csq_stat >> 10) & 0x3ff;
3087 ib1_rptr = (csq_stat >> 20) & 0x3ff;
3088 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
3089 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
3090 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
3091 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
3092 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
3093 seq_printf(m, "Ring rptr %u\n", r_rptr);
3094 seq_printf(m, "Ring wptr %u\n", r_wptr);
3095 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3096 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3097 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3098 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3099 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3100 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3101 seq_printf(m, "Ring fifo:\n");
3102 for (i = 0; i < 256; i++) {
3103 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3104 tmp = RREG32(RADEON_CP_CSQ_DATA);
3105 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3106 }
3107 seq_printf(m, "Indirect1 fifo:\n");
3108 for (i = 256; i <= 512; i++) {
3109 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3110 tmp = RREG32(RADEON_CP_CSQ_DATA);
3111 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3112 }
3113 seq_printf(m, "Indirect2 fifo:\n");
3114 for (i = 640; i < ib1_wptr; i++) {
3115 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3116 tmp = RREG32(RADEON_CP_CSQ_DATA);
3117 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3118 }
3119 return 0;
3120}
3121
3122static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3123{
3124 struct drm_info_node *node = (struct drm_info_node *) m->private;
3125 struct drm_device *dev = node->minor->dev;
3126 struct radeon_device *rdev = dev->dev_private;
3127 uint32_t tmp;
c93bb85b 3128
0242f74d
AD		 3129 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3130 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3131 tmp = RREG32(RADEON_MC_FB_LOCATION);
3132 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3133 tmp = RREG32(RADEON_BUS_CNTL);
3134 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3135 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3136 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3137 tmp = RREG32(RADEON_AGP_BASE);
3138 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3139 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3140 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3141 tmp = RREG32(0x01D0);
3142 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3143 tmp = RREG32(RADEON_AIC_LO_ADDR);
3144 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3145 tmp = RREG32(RADEON_AIC_HI_ADDR);
3146 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3147 tmp = RREG32(0x01E4);
3148 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3149 return 0;
3150}
c93bb85b 3151
0242f74d
AD		 3152static struct drm_info_list r100_debugfs_rbbm_list[] = {
3153 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3154};
c93bb85b 3155
0242f74d
AD		 3156static struct drm_info_list r100_debugfs_cp_list[] = {
3157 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3158 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3159};
c93bb85b 3160
0242f74d
AD		 3161static struct drm_info_list r100_debugfs_mc_info_list[] = {
3162 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3163};
3164#endif
c93bb85b 3165
0242f74d
AD		 3166int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3167{
3168#if defined(CONFIG_DEBUG_FS)
3169 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3170#else
3171 return 0;
3172#endif
3173}
c93bb85b 3174
0242f74d
AD		 3175int r100_debugfs_cp_init(struct radeon_device *rdev)
3176{
3177#if defined(CONFIG_DEBUG_FS)
3178 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3179#else
3180 return 0;
3181#endif
3182}
c93bb85b 3183
0242f74d
AD		 3184int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3185{
3186#if defined(CONFIG_DEBUG_FS)
3187 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3188#else
3189 return 0;
3190#endif
3191}
c93bb85b 3192
0242f74d
AD		 3193int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3194 uint32_t tiling_flags, uint32_t pitch,
3195 uint32_t offset, uint32_t obj_size)
3196{
3197 int surf_index = reg * 16;
3198 int flags = 0;
c93bb85b 3199
0242f74d
AD		 3200 if (rdev->family <= CHIP_RS200) {
3201 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3202 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3203 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3204 if (tiling_flags & RADEON_TILING_MACRO)
3205 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3206 } else if (rdev->family <= CHIP_RV280) {
3207 if (tiling_flags & (RADEON_TILING_MACRO))
3208 flags |= R200_SURF_TILE_COLOR_MACRO;
3209 if (tiling_flags & RADEON_TILING_MICRO)
3210 flags |= R200_SURF_TILE_COLOR_MICRO;
3211 } else {
3212 if (tiling_flags & RADEON_TILING_MACRO)
3213 flags |= R300_SURF_TILE_MACRO;
3214 if (tiling_flags & RADEON_TILING_MICRO)
3215 flags |= R300_SURF_TILE_MICRO;
3216 }
c93bb85b 3217
0242f74d
AD		 3218 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3219 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3220 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3221 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3222
3223 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
3224 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
3225 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
3226 if (ASIC_IS_RN50(rdev))
3227 pitch /= 16;
c93bb85b
JG		 3228 }
3229
0242f74d
AD		 3230 /* r100/r200 divide by 16 */
3231 if (rdev->family < CHIP_R300)
3232 flags |= pitch / 16;
3233 else
3234 flags |= pitch / 8;
c93bb85b 3235
c93bb85b 3236
0242f74d
AD		 3237 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3238 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3239 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3240 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3241 return 0;
3242}
c93bb85b 3243
0242f74d
AD		 3244void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3245{
3246 int surf_index = reg * 16;
3247 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3248}
c93bb85b 3249
0242f74d
AD		 3250void r100_bandwidth_update(struct radeon_device *rdev)
3251{
3252 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3253 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3254 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3255 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3256 fixed20_12 memtcas_ff[8] = {
3257 dfixed_init(1),
3258 dfixed_init(2),
3259 dfixed_init(3),
3260 dfixed_init(0),
3261 dfixed_init_half(1),
3262 dfixed_init_half(2),
3263 dfixed_init(0),
3264 };
3265 fixed20_12 memtcas_rs480_ff[8] = {
3266 dfixed_init(0),
3267 dfixed_init(1),
3268 dfixed_init(2),
3269 dfixed_init(3),
3270 dfixed_init(0),
3271 dfixed_init_half(1),
3272 dfixed_init_half(2),
3273 dfixed_init_half(3),
3274 };
3275 fixed20_12 memtcas2_ff[8] = {
3276 dfixed_init(0),
3277 dfixed_init(1),
3278 dfixed_init(2),
3279 dfixed_init(3),
3280 dfixed_init(4),
3281 dfixed_init(5),
3282 dfixed_init(6),
3283 dfixed_init(7),
3284 };
3285 fixed20_12 memtrbs[8] = {
3286 dfixed_init(1),
3287 dfixed_init_half(1),
3288 dfixed_init(2),
3289 dfixed_init_half(2),
3290 dfixed_init(3),
3291 dfixed_init_half(3),
3292 dfixed_init(4),
3293 dfixed_init_half(4)
3294 };
3295 fixed20_12 memtrbs_r4xx[8] = {
3296 dfixed_init(4),
3297 dfixed_init(5),
3298 dfixed_init(6),
3299 dfixed_init(7),
3300 dfixed_init(8),
3301 dfixed_init(9),
3302 dfixed_init(10),
3303 dfixed_init(11)
3304 };
3305 fixed20_12 min_mem_eff;
3306 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3307 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3308 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3309 disp_drain_rate2, read_return_rate;
3310 fixed20_12 time_disp1_drop_priority;
3311 int c;
3312 int cur_size = 16; /* in octawords */
3313 int critical_point = 0, critical_point2;
3314/* uint32_t read_return_rate, time_disp1_drop_priority; */
3315 int stop_req, max_stop_req;
3316 struct drm_display_mode *mode1 = NULL;
3317 struct drm_display_mode *mode2 = NULL;
3318 uint32_t pixel_bytes1 = 0;
3319 uint32_t pixel_bytes2 = 0;
c93bb85b 3320
0242f74d 3321 radeon_update_display_priority(rdev);
c93bb85b 3322
0242f74d
AD		 3323 if (rdev->mode_info.crtcs[0]->base.enabled) {
3324 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3325 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3326 }
3327 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3328 if (rdev->mode_info.crtcs[1]->base.enabled) {
3329 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3330 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3331 }
3332 }
c93bb85b 3333
0242f74d
AD		 3334 min_mem_eff.full = dfixed_const_8(0);
3335 /* get modes */
3336 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3337 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3338 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3339 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3340 /* check crtc enables */
3341 if (mode2)
3342 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3343 if (mode1)
3344 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3345 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3346 }
c93bb85b 3347
0242f74d
AD		 3348 /*
3349 * determine is there is enough bw for current mode
3350 */
3351 sclk_ff = rdev->pm.sclk;
3352 mclk_ff = rdev->pm.mclk;
c93bb85b 3353
0242f74d
AD		 3354 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3355 temp_ff.full = dfixed_const(temp);
3356 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b 3357
0242f74d
AD		 3358 pix_clk.full = 0;
3359 pix_clk2.full = 0;
3360 peak_disp_bw.full = 0;
3361 if (mode1) {
3362 temp_ff.full = dfixed_const(1000);
3363 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3364 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3365 temp_ff.full = dfixed_const(pixel_bytes1);
3366 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3367 }
3368 if (mode2) {
3369 temp_ff.full = dfixed_const(1000);
3370 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3371 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3372 temp_ff.full = dfixed_const(pixel_bytes2);
3373 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3374 }
c93bb85b 3375
0242f74d
AD		 3376 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3377 if (peak_disp_bw.full >= mem_bw.full) {
3378 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3379 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3380 }
c93bb85b 3381
0242f74d
AD		 3382 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3383 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3384 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3385 mem_trcd = ((temp >> 2) & 0x3) + 1;
3386 mem_trp = ((temp & 0x3)) + 1;
3387 mem_tras = ((temp & 0x70) >> 4) + 1;
3388 } else if (rdev->family == CHIP_R300 ||
3389 rdev->family == CHIP_R350) { /* r300, r350 */
3390 mem_trcd = (temp & 0x7) + 1;
3391 mem_trp = ((temp >> 8) & 0x7) + 1;
3392 mem_tras = ((temp >> 11) & 0xf) + 4;
3393 } else if (rdev->family == CHIP_RV350 ||
3394 rdev->family <= CHIP_RV380) {
3395 /* rv3x0 */
3396 mem_trcd = (temp & 0x7) + 3;
3397 mem_trp = ((temp >> 8) & 0x7) + 3;
3398 mem_tras = ((temp >> 11) & 0xf) + 6;
3399 } else if (rdev->family == CHIP_R420 ||
3400 rdev->family == CHIP_R423 ||
3401 rdev->family == CHIP_RV410) {
3402 /* r4xx */
3403 mem_trcd = (temp & 0xf) + 3;
3404 if (mem_trcd > 15)
3405 mem_trcd = 15;
3406 mem_trp = ((temp >> 8) & 0xf) + 3;
3407 if (mem_trp > 15)
3408 mem_trp = 15;
3409 mem_tras = ((temp >> 12) & 0x1f) + 6;
3410 if (mem_tras > 31)
3411 mem_tras = 31;
3412 } else { /* RV200, R200 */
3413 mem_trcd = (temp & 0x7) + 1;
3414 mem_trp = ((temp >> 8) & 0x7) + 1;
3415 mem_tras = ((temp >> 12) & 0xf) + 4;
3416 }
3417 /* convert to FF */
3418 trcd_ff.full = dfixed_const(mem_trcd);
3419 trp_ff.full = dfixed_const(mem_trp);
3420 tras_ff.full = dfixed_const(mem_tras);
c93bb85b 3421
0242f74d
AD		 3422 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3423 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3424 data = (temp & (7 << 20)) >> 20;
3425 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3426 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3427 tcas_ff = memtcas_rs480_ff[data];
3428 else
3429 tcas_ff = memtcas_ff[data];
3430 } else
3431 tcas_ff = memtcas2_ff[data];
c93bb85b 3432
0242f74d
AD		 3433 if (rdev->family == CHIP_RS400 ||
3434 rdev->family == CHIP_RS480) {
3435 /* extra cas latency stored in bits 23-25 0-4 clocks */
3436 data = (temp >> 23) & 0x7;
3437 if (data < 5)
3438 tcas_ff.full += dfixed_const(data);
c93bb85b 3439 }
551ebd83 3440
0242f74d
AD		 3441 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3442 /* on the R300, Tcas is included in Trbs.
3443 */
3444 temp = RREG32(RADEON_MEM_CNTL);
3445 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3446 if (data == 1) {
3447 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3448 temp = RREG32(R300_MC_IND_INDEX);
3449 temp &= ~R300_MC_IND_ADDR_MASK;
3450 temp |= R300_MC_READ_CNTL_CD_mcind;
3451 WREG32(R300_MC_IND_INDEX, temp);
3452 temp = RREG32(R300_MC_IND_DATA);
3453 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3454 } else {
3455 temp = RREG32(R300_MC_READ_CNTL_AB);
3456 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3457 }
3458 } else {
3459 temp = RREG32(R300_MC_READ_CNTL_AB);
3460 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3461 }
3462 if (rdev->family == CHIP_RV410 ||
3463 rdev->family == CHIP_R420 ||
3464 rdev->family == CHIP_R423)
3465 trbs_ff = memtrbs_r4xx[data];
3466 else
3467 trbs_ff = memtrbs[data];
3468 tcas_ff.full += trbs_ff.full;
3469 }
551ebd83 3470
0242f74d 3471 sclk_eff_ff.full = sclk_ff.full;
d785d78b 3472
0242f74d
AD		 3473 if (rdev->flags & RADEON_IS_AGP) {
3474 fixed20_12 agpmode_ff;
3475 agpmode_ff.full = dfixed_const(radeon_agpmode);
3476 temp_ff.full = dfixed_const_666(16);
3477 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3478 }
3479 /* TODO PCIE lanes may affect this - agpmode == 16?? */
d785d78b 3480
0242f74d
AD		 3481 if (ASIC_IS_R300(rdev)) {
3482 sclk_delay_ff.full = dfixed_const(250);
3483 } else {
3484 if ((rdev->family == CHIP_RV100) ||
3485 rdev->flags & RADEON_IS_IGP) {
3486 if (rdev->mc.vram_is_ddr)
3487 sclk_delay_ff.full = dfixed_const(41);
3488 else
3489 sclk_delay_ff.full = dfixed_const(33);
3490 } else {
3491 if (rdev->mc.vram_width == 128)
3492 sclk_delay_ff.full = dfixed_const(57);
3493 else
3494 sclk_delay_ff.full = dfixed_const(41);
3495 }
d785d78b
DA		 3496 }
3497
0242f74d 3498 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
d785d78b 3499
0242f74d
AD		 3500 if (rdev->mc.vram_is_ddr) {
3501 if (rdev->mc.vram_width == 32) {
3502 k1.full = dfixed_const(40);
3503 c = 3;
3504 } else {
3505 k1.full = dfixed_const(20);
3506 c = 1;
3507 }
3508 } else {
3509 k1.full = dfixed_const(40);
3510 c = 3;
3511 }
37cf6b03 3512
0242f74d
AD		 3513 temp_ff.full = dfixed_const(2);
3514 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3515 temp_ff.full = dfixed_const(c);
3516 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3517 temp_ff.full = dfixed_const(4);
3518 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3519 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3520 mc_latency_mclk.full += k1.full;
37cf6b03 3521
0242f74d
AD		 3522 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3523 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
37cf6b03 3524
0242f74d
AD		 3525 /*
3526 HW cursor time assuming worst case of full size colour cursor.
3527 */
3528 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3529 temp_ff.full += trcd_ff.full;
3530 if (temp_ff.full < tras_ff.full)
3531 temp_ff.full = tras_ff.full;
3532 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
37cf6b03 3533
0242f74d
AD		 3534 temp_ff.full = dfixed_const(cur_size);
3535 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3536 /*
3537 Find the total latency for the display data.
3538 */
3539 disp_latency_overhead.full = dfixed_const(8);
3540 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3541 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3542 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
37cf6b03 3543
0242f74d
AD		 3544 if (mc_latency_mclk.full > mc_latency_sclk.full)
3545 disp_latency.full = mc_latency_mclk.full;
3546 else
3547 disp_latency.full = mc_latency_sclk.full;
551ebd83 3548
0242f74d
AD		 3549 /* setup Max GRPH_STOP_REQ default value */
3550 if (ASIC_IS_RV100(rdev))
3551 max_stop_req = 0x5c;
3552 else
3553 max_stop_req = 0x7c;
d785d78b 3554
0242f74d
AD		 3555 if (mode1) {
3556 /* CRTC1
3557 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3558 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3559 */
3560 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
d785d78b 3561
0242f74d
AD		 3562 if (stop_req > max_stop_req)
3563 stop_req = max_stop_req;
551ebd83 3564
0242f74d
AD		 3565 /*
3566 Find the drain rate of the display buffer.
3567 */
3568 temp_ff.full = dfixed_const((16/pixel_bytes1));
3569 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
551ebd83 3570
0242f74d
AD		 3571 /*
3572 Find the critical point of the display buffer.
3573 */
3574 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3575 crit_point_ff.full += dfixed_const_half(0);
a41ceb1c 3576
0242f74d
AD		 3577 critical_point = dfixed_trunc(crit_point_ff);
3578
3579 if (rdev->disp_priority == 2) {
3580 critical_point = 0;
551ebd83 3581 }
40b4a759 3582
0242f74d
AD		 3583 /*
3584 The critical point should never be above max_stop_req-4. Setting
3585 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3586 */
3587 if (max_stop_req - critical_point < 4)
3588 critical_point = 0;
3589
3590 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3591 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3592 critical_point = 0x10;
551ebd83 3593 }
0242f74d
AD		 3594
3595 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3596 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3597 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3598 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3599 if ((rdev->family == CHIP_R350) &&
3600 (stop_req > 0x15)) {
3601 stop_req -= 0x10;
551ebd83 3602 }
0242f74d
AD		 3603 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3604 temp |= RADEON_GRPH_BUFFER_SIZE;
3605 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3606 RADEON_GRPH_CRITICAL_AT_SOF |
3607 RADEON_GRPH_STOP_CNTL);
3608 /*
3609 Write the result into the register.
3610 */
3611 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3612 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
40b4a759 3613
0242f74d
AD		 3614#if 0
3615 if ((rdev->family == CHIP_RS400) ||
3616 (rdev->family == CHIP_RS480)) {
3617 /* attempt to program RS400 disp regs correctly ??? */
3618 temp = RREG32(RS400_DISP1_REG_CNTL);
3619 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3620 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3621 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3622 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3623 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3624 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3625 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3626 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3627 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3628 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3629 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
fff1ce4d 3630 }
0242f74d 3631#endif
fff1ce4d 3632
0242f74d
AD		 3633 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3634 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3635 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
cae94b0a 3636 }
0242f74d
AD		 3637
3638 if (mode2) {
3639 u32 grph2_cntl;
3640 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3641
3642 if (stop_req > max_stop_req)
3643 stop_req = max_stop_req;
3644
3645 /*
3646 Find the drain rate of the display buffer.
3647 */
3648 temp_ff.full = dfixed_const((16/pixel_bytes2));
3649 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3650
3651 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3652 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3653 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3654 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3655 if ((rdev->family == CHIP_R350) &&
3656 (stop_req > 0x15)) {
3657 stop_req -= 0x10;
551ebd83 3658 }
0242f74d
AD		 3659 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3660 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3661 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3662 RADEON_GRPH_CRITICAL_AT_SOF |
3663 RADEON_GRPH_STOP_CNTL);
3664
3665 if ((rdev->family == CHIP_RS100) ||
3666 (rdev->family == CHIP_RS200))
3667 critical_point2 = 0;
3668 else {
3669 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3670 temp_ff.full = dfixed_const(temp);
3671 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3672 if (sclk_ff.full < temp_ff.full)
3673 temp_ff.full = sclk_ff.full;
3674
3675 read_return_rate.full = temp_ff.full;
3676
3677 if (mode1) {
3678 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3679 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3680 } else {
3681 time_disp1_drop_priority.full = 0;
551ebd83 3682 }
0242f74d
AD		 3683 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3684 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3685 crit_point_ff.full += dfixed_const_half(0);
3686
3687 critical_point2 = dfixed_trunc(crit_point_ff);
3688
3689 if (rdev->disp_priority == 2) {
3690 critical_point2 = 0;
551ebd83 3691 }
40b4a759 3692
0242f74d
AD		 3693 if (max_stop_req - critical_point2 < 4)
3694 critical_point2 = 0;
551ebd83 3695
0242f74d 3696 }
551ebd83 3697
0242f74d
AD		 3698 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3699 /* some R300 cards have problem with this set to 0 */
3700 critical_point2 = 0x10;
3701 }
40b4a759 3702
0242f74d
AD		 3703 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3704 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
551ebd83 3705
0242f74d
AD		 3706 if ((rdev->family == CHIP_RS400) ||
3707 (rdev->family == CHIP_RS480)) {
3708#if 0
3709 /* attempt to program RS400 disp2 regs correctly ??? */
3710 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3711 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3712 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3713 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3714 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3715 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3716 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3717 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3718 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3719 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3720 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3721 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3722#endif
3723 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3724 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3725 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3726 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
551ebd83 3727 }
0242f74d
AD		 3728
3729 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3730 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
551ebd83
DA		 3731 }
3732}
3ce0a23d 3733
e32eb50d 3734int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 3735{
3736 uint32_t scratch;
3737 uint32_t tmp = 0;
3738 unsigned i;
3739 int r;
3740
3741 r = radeon_scratch_get(rdev, &scratch);
3742 if (r) {
3743 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3744 return r;
3745 }
3746 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 3747 r = radeon_ring_lock(rdev, ring, 2);
3ce0a23d
JG		 3748 if (r) {
3749 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3750 radeon_scratch_free(rdev, scratch);
3751 return r;
3752 }
e32eb50d
CK		 3753 radeon_ring_write(ring, PACKET0(scratch, 0));
3754 radeon_ring_write(ring, 0xDEADBEEF);
3755 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 3756 for (i = 0; i < rdev->usec_timeout; i++) {
3757 tmp = RREG32(scratch);
3758 if (tmp == 0xDEADBEEF) {
3759 break;
3760 }
3761 DRM_UDELAY(1);
3762 }
3763 if (i < rdev->usec_timeout) {
3764 DRM_INFO("ring test succeeded in %d usecs\n", i);
3765 } else {
369d7ec1 3766 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3767 scratch, tmp);
3768 r = -EINVAL;
3769 }
3770 radeon_scratch_free(rdev, scratch);
3771 return r;
3772}
3773
3774void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3775{
e32eb50d 3776 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3777
c7eff978
AD		 3778 if (ring->rptr_save_reg) {
3779 u32 next_rptr = ring->wptr + 2 + 3;
3780 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3781 radeon_ring_write(ring, next_rptr);
3782 }
3783
e32eb50d
CK		 3784 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3785 radeon_ring_write(ring, ib->gpu_addr);
3786 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3787}
3788
f712812e 3789int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3790{
f2e39221 3791 struct radeon_ib ib;
3ce0a23d
JG		 3792 uint32_t scratch;
3793 uint32_t tmp = 0;
3794 unsigned i;
3795 int r;
3796
3797 r = radeon_scratch_get(rdev, &scratch);
3798 if (r) {
3799 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3800 return r;
3801 }
3802 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3803 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3ce0a23d
JG		 3804 if (r) {
3805 return r;
3806 }
f2e39221
JG		 3807 ib.ptr[0] = PACKET0(scratch, 0);
3808 ib.ptr[1] = 0xDEADBEEF;
3809 ib.ptr[2] = PACKET2(0);
3810 ib.ptr[3] = PACKET2(0);
3811 ib.ptr[4] = PACKET2(0);
3812 ib.ptr[5] = PACKET2(0);
3813 ib.ptr[6] = PACKET2(0);
3814 ib.ptr[7] = PACKET2(0);
3815 ib.length_dw = 8;
4ef72566 3816 r = radeon_ib_schedule(rdev, &ib, NULL);
3ce0a23d
JG		 3817 if (r) {
3818 radeon_scratch_free(rdev, scratch);
3819 radeon_ib_free(rdev, &ib);
3820 return r;
3821 }
f2e39221 3822 r = radeon_fence_wait(ib.fence, false);
3ce0a23d
JG		 3823 if (r) {
3824 return r;
3825 }
3826 for (i = 0; i < rdev->usec_timeout; i++) {
3827 tmp = RREG32(scratch);
3828 if (tmp == 0xDEADBEEF) {
3829 break;
3830 }
3831 DRM_UDELAY(1);
3832 }
3833 if (i < rdev->usec_timeout) {
3834 DRM_INFO("ib test succeeded in %u usecs\n", i);
3835 } else {
62f288cf 3836 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3837 scratch, tmp);
3838 r = -EINVAL;
3839 }
3840 radeon_scratch_free(rdev, scratch);
3841 radeon_ib_free(rdev, &ib);
3842 return r;
3843}
9f022ddf 3844
9f022ddf
JG		 3845void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3846{
3847 /* Shutdown CP we shouldn't need to do that but better be safe than
3848 * sorry
3849 */
e32eb50d 3850 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
9f022ddf
JG		 3851 WREG32(R_000740_CP_CSQ_CNTL, 0);
3852
3853 /* Save few CRTC registers */
ca6ffc64 3854 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3855 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3856 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3857 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3858 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3859 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3860 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3861 }
3862
3863 /* Disable VGA aperture access */
ca6ffc64 3864 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3865 /* Disable cursor, overlay, crtc */
3866 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3867 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3868 S_000054_CRTC_DISPLAY_DIS(1));
3869 WREG32(R_000050_CRTC_GEN_CNTL,
3870 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3871 S_000050_CRTC_DISP_REQ_EN_B(1));
3872 WREG32(R_000420_OV0_SCALE_CNTL,
3873 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3874 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3875 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3876 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3877 S_000360_CUR2_LOCK(1));
3878 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3879 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3880 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3881 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3882 WREG32(R_000360_CUR2_OFFSET,
3883 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3884 }
3885}
3886
3887void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3888{
3889 /* Update base address for crtc */
d594e46a 3890 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3891 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3892 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3893 }
3894 /* Restore CRTC registers */
ca6ffc64 3895 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3896 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3897 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3898 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3899 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3900 }
3901}
ca6ffc64
JG		 3902
3903void r100_vga_render_disable(struct radeon_device *rdev)
3904{
d4550907 3905 u32 tmp;
ca6ffc64 3906
d4550907 3907 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3908 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3909}
d4550907
JG		 3910
3911static void r100_debugfs(struct radeon_device *rdev)
3912{
3913 int r;
3914
3915 r = r100_debugfs_mc_info_init(rdev);
3916 if (r)
3917 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3918}
3919
3920static void r100_mc_program(struct radeon_device *rdev)
3921{
3922 struct r100_mc_save save;
3923
3924 /* Stops all mc clients */
3925 r100_mc_stop(rdev, &save);
3926 if (rdev->flags & RADEON_IS_AGP) {
3927 WREG32(R_00014C_MC_AGP_LOCATION,
3928 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3929 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3930 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3931 if (rdev->family > CHIP_RV200)
3932 WREG32(R_00015C_AGP_BASE_2,
3933 upper_32_bits(rdev->mc.agp_base) & 0xff);
3934 } else {
3935 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3936 WREG32(R_000170_AGP_BASE, 0);
3937 if (rdev->family > CHIP_RV200)
3938 WREG32(R_00015C_AGP_BASE_2, 0);
3939 }
3940 /* Wait for mc idle */
3941 if (r100_mc_wait_for_idle(rdev))
3942 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3943 /* Program MC, should be a 32bits limited address space */
3944 WREG32(R_000148_MC_FB_LOCATION,
3945 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3946 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3947 r100_mc_resume(rdev, &save);
3948}
3949
1109ca09 3950static void r100_clock_startup(struct radeon_device *rdev)
d4550907
JG		 3951{
3952 u32 tmp;
3953
3954 if (radeon_dynclks != -1 && radeon_dynclks)
3955 radeon_legacy_set_clock_gating(rdev, 1);
3956 /* We need to force on some of the block */
3957 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3958 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3959 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3960 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3961 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3962}
3963
3964static int r100_startup(struct radeon_device *rdev)
3965{
3966 int r;
3967
92cde00c
AD		 3968 /* set common regs */
3969 r100_set_common_regs(rdev);
3970 /* program mc */
d4550907
JG		 3971 r100_mc_program(rdev);
3972 /* Resume clock */
3973 r100_clock_startup(rdev);
d4550907
JG		 3974 /* Initialize GART (initialize after TTM so we can allocate
3975 * memory through TTM but finalize after TTM) */
17e15b0c 3976 r100_enable_bm(rdev);
d4550907
JG		 3977 if (rdev->flags & RADEON_IS_PCI) {
3978 r = r100_pci_gart_enable(rdev);
3979 if (r)
3980 return r;
3981 }
724c80e1
AD		 3982
3983 /* allocate wb buffer */
3984 r = radeon_wb_init(rdev);
3985 if (r)
3986 return r;
3987
30eb77f4
JG		 3988 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3989 if (r) {
3990 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3991 return r;
3992 }
3993
d4550907 3994 /* Enable IRQ */
d4550907 3995 r100_irq_set(rdev);
cafe6609 3996 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3997 /* 1M ring buffer */
3998 r = r100_cp_init(rdev, 1024 * 1024);
3999 if (r) {
ec4f2ac4 4000 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
d4550907
JG		 4001 return r;
4002 }
b15ba512 4003
2898c348
CK		 4004 r = radeon_ib_pool_init(rdev);
4005 if (r) {
4006 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 4007 return r;
2898c348 4008 }
b15ba512 4009
d4550907
JG		 4010 return 0;
4011}
4012
4013int r100_resume(struct radeon_device *rdev)
4014{
6b7746e8
JG		 4015 int r;
4016
d4550907
JG		 4017 /* Make sur GART are not working */
4018 if (rdev->flags & RADEON_IS_PCI)
4019 r100_pci_gart_disable(rdev);
4020 /* Resume clock before doing reset */
4021 r100_clock_startup(rdev);
4022 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 4023 if (radeon_asic_reset(rdev)) {
d4550907
JG		 4024 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4025 RREG32(R_000E40_RBBM_STATUS),
4026 RREG32(R_0007C0_CP_STAT));
4027 }
4028 /* post */
4029 radeon_combios_asic_init(rdev->ddev);
4030 /* Resume clock after posting */
4031 r100_clock_startup(rdev);
550e2d92
DA		 4032 /* Initialize surface registers */
4033 radeon_surface_init(rdev);
b15ba512
JG		 4034
4035 rdev->accel_working = true;
6b7746e8
JG		 4036 r = r100_startup(rdev);
4037 if (r) {
4038 rdev->accel_working = false;
4039 }
4040 return r;
d4550907
JG		 4041}
4042
4043int r100_suspend(struct radeon_device *rdev)
4044{
4045 r100_cp_disable(rdev);
724c80e1 4046 radeon_wb_disable(rdev);
d4550907
JG		 4047 r100_irq_disable(rdev);
4048 if (rdev->flags & RADEON_IS_PCI)
4049 r100_pci_gart_disable(rdev);
4050 return 0;
4051}
4052
4053void r100_fini(struct radeon_device *rdev)
4054{
d4550907 4055 r100_cp_fini(rdev);
724c80e1 4056 radeon_wb_fini(rdev);
2898c348 4057 radeon_ib_pool_fini(rdev);
d4550907
JG		 4058 radeon_gem_fini(rdev);
4059 if (rdev->flags & RADEON_IS_PCI)
4060 r100_pci_gart_fini(rdev);
d0269ed8 4061 radeon_agp_fini(rdev);
d4550907
JG		 4062 radeon_irq_kms_fini(rdev);
4063 radeon_fence_driver_fini(rdev);
4c788679 4064 radeon_bo_fini(rdev);
d4550907
JG		 4065 radeon_atombios_fini(rdev);
4066 kfree(rdev->bios);
4067 rdev->bios = NULL;
4068}
4069
4c712e6c
DA		 4070/*
4071 * Due to how kexec works, it can leave the hw fully initialised when it
4072 * boots the new kernel. However doing our init sequence with the CP and
4073 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
4074 * do some quick sanity checks and restore sane values to avoid this
4075 * problem.
4076 */
4077void r100_restore_sanity(struct radeon_device *rdev)
4078{
4079 u32 tmp;
4080
4081 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4082 if (tmp) {
4083 WREG32(RADEON_CP_CSQ_CNTL, 0);
4084 }
4085 tmp = RREG32(RADEON_CP_RB_CNTL);
4086 if (tmp) {
4087 WREG32(RADEON_CP_RB_CNTL, 0);
4088 }
4089 tmp = RREG32(RADEON_SCRATCH_UMSK);
4090 if (tmp) {
4091 WREG32(RADEON_SCRATCH_UMSK, 0);
4092 }
4093}
4094
d4550907
JG		 4095int r100_init(struct radeon_device *rdev)
4096{
4097 int r;
4098
d4550907
JG		 4099 /* Register debugfs file specific to this group of asics */
4100 r100_debugfs(rdev);
4101 /* Disable VGA */
4102 r100_vga_render_disable(rdev);
4103 /* Initialize scratch registers */
4104 radeon_scratch_init(rdev);
4105 /* Initialize surface registers */
4106 radeon_surface_init(rdev);
4c712e6c
DA		 4107 /* sanity check some register to avoid hangs like after kexec */
4108 r100_restore_sanity(rdev);
d4550907
JG		 4109 /* TODO: disable VGA need to use VGA request */
4110 /* BIOS*/
4111 if (!radeon_get_bios(rdev)) {
4112 if (ASIC_IS_AVIVO(rdev))
4113 return -EINVAL;
4114 }
4115 if (rdev->is_atom_bios) {
4116 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4117 return -EINVAL;
4118 } else {
4119 r = radeon_combios_init(rdev);
4120 if (r)
4121 return r;
4122 }
4123 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 4124 if (radeon_asic_reset(rdev)) {
d4550907
JG		 4125 dev_warn(rdev->dev,
4126 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4127 RREG32(R_000E40_RBBM_STATUS),
4128 RREG32(R_0007C0_CP_STAT));
4129 }
4130 /* check if cards are posted or not */
72542d77
DA		 4131 if (radeon_boot_test_post_card(rdev) == false)
4132 return -EINVAL;
d4550907
JG		 4133 /* Set asic errata */
4134 r100_errata(rdev);
4135 /* Initialize clocks */
4136 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 4137 /* initialize AGP */
4138 if (rdev->flags & RADEON_IS_AGP) {
4139 r = radeon_agp_init(rdev);
4140 if (r) {
4141 radeon_agp_disable(rdev);
4142 }
4143 }
4144 /* initialize VRAM */
4145 r100_mc_init(rdev);
d4550907 4146 /* Fence driver */
30eb77f4 4147 r = radeon_fence_driver_init(rdev);
d4550907
JG		 4148 if (r)
4149 return r;
4150 r = radeon_irq_kms_init(rdev);
4151 if (r)
4152 return r;
4153 /* Memory manager */
4c788679 4154 r = radeon_bo_init(rdev);
d4550907
JG		 4155 if (r)
4156 return r;
4157 if (rdev->flags & RADEON_IS_PCI) {
4158 r = r100_pci_gart_init(rdev);
4159 if (r)
4160 return r;
4161 }
4162 r100_set_safe_registers(rdev);
b15ba512 4163
d4550907
JG		 4164 rdev->accel_working = true;
4165 r = r100_startup(rdev);
4166 if (r) {
4167 /* Somethings want wront with the accel init stop accel */
4168 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 4169 r100_cp_fini(rdev);
724c80e1 4170 radeon_wb_fini(rdev);
2898c348 4171 radeon_ib_pool_fini(rdev);
655efd3d 4172 radeon_irq_kms_fini(rdev);
d4550907
JG		 4173 if (rdev->flags & RADEON_IS_PCI)
4174 r100_pci_gart_fini(rdev);
d4550907
JG		 4175 rdev->accel_working = false;
4176 }
4177 return 0;
4178}
6fcbef7a
AK		 4179
4180uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4181{
4182 if (reg < rdev->rmmio_size)
4183 return readl(((void __iomem *)rdev->rmmio) + reg);
4184 else {
4185 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4186 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4187 }
4188}
4189
4190void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4191{
4192 if (reg < rdev->rmmio_size)
4193 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4194 else {
4195 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4196 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4197 }
4198}
4199
4200u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4201{
4202 if (reg < rdev->rio_mem_size)
4203 return ioread32(rdev->rio_mem + reg);
4204 else {
4205 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4206 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4207 }
4208}
4209
4210void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4211{
4212 if (reg < rdev->rio_mem_size)
4213 iowrite32(v, rdev->rio_mem + reg);
4214 else {
4215 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4216 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4217 }
4218}
Linux 6.x block layer and io_uring tree(s)